VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h@ 71204

最後變更 在這個檔案從71204是 71184,由 vboxsync 提交於 7 年 前

CPUM,NEM: Introduced CPUMCTX field for tracking state that's not in the structure. Made NEM/win only get/set the register it needs. New NEM runloop based on low level messages, skipping translations. bugref:9044
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1/* $Id: NEMAllNativeTemplate-win.cpp.h 71184 2018-03-03 15:01:59Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, Windows code template ring-0/3.
4 */
5
6/*
7 * Copyright (C) 2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22/** Copy back a segment from hyper-V. */
23#define NEM_WIN_COPY_BACK_SEG(a_Dst, a_Src) \
24 do { \
25 (a_Dst).u64Base = (a_Src).Base; \
26 (a_Dst).u32Limit = (a_Src).Limit; \
27 (a_Dst).ValidSel = (a_Dst).Sel = (a_Src).Selector; \
28 (a_Dst).Attr.u = (a_Src).Attributes; \
29 (a_Dst).fFlags = CPUMSELREG_FLAGS_VALID; \
30 } while (0)
31
32/** The CPUMCTX_EXTRN_XXX mask for IEM. */
33#define NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM CPUMCTX_EXTRN_ALL
34
35
36/*********************************************************************************************************************************
37* Global Variables *
38*********************************************************************************************************************************/
39/** NEM_WIN_PAGE_STATE_XXX names. */
40NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
41
42
43/*********************************************************************************************************************************
44* Internal Functions *
45*********************************************************************************************************************************/
46NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
47 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged);
48
49
50#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
51
52/**
53 * Wrapper around VMMR0_DO_NEM_MAP_PAGES for a single page.
54 *
55 * @returns VBox status code.
56 * @param pVM The cross context VM structure.
57 * @param pVCpu The cross context virtual CPU structure of the caller.
58 * @param GCPhysSrc The source page. Does not need to be page aligned.
59 * @param GCPhysDst The destination page. Same as @a GCPhysSrc except for
60 * when A20 is disabled.
61 * @param fFlags HV_MAP_GPA_XXX.
62 */
63DECLINLINE(int) nemHCWinHypercallMapPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst, uint32_t fFlags)
64{
65#ifdef IN_RING0
66 /** @todo optimize further, caller generally has the physical address. */
67 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM);
68 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE);
69 return nemR0WinMapPages(pGVM, pVM, &pGVM->aCpus[pVCpu->idCpu], GCPhysSrc, GCPhysDst, 1, fFlags);
70#else
71 pVCpu->nem.s.Hypercall.MapPages.GCPhysSrc = GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
72 pVCpu->nem.s.Hypercall.MapPages.GCPhysDst = GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
73 pVCpu->nem.s.Hypercall.MapPages.cPages = 1;
74 pVCpu->nem.s.Hypercall.MapPages.fFlags = fFlags;
75 return VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_MAP_PAGES, 0, NULL);
76#endif
77}
78
79
80/**
81 * Wrapper around VMMR0_DO_NEM_UNMAP_PAGES for a single page.
82 *
83 * @returns VBox status code.
84 * @param pVM The cross context VM structure.
85 * @param pVCpu The cross context virtual CPU structure of the caller.
86 * @param GCPhys The page to unmap. Does not need to be page aligned.
87 */
88DECLINLINE(int) nemHCWinHypercallUnmapPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
89{
90# ifdef IN_RING0
91 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM);
92 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE);
93 return nemR0WinUnmapPages(pGVM, &pGVM->aCpus[pVCpu->idCpu], GCPhys, 1);
94# else
95 pVCpu->nem.s.Hypercall.UnmapPages.GCPhys = GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK;
96 pVCpu->nem.s.Hypercall.UnmapPages.cPages = 1;
97 return VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_UNMAP_PAGES, 0, NULL);
98# endif
99}
100
101#endif /* NEM_WIN_USE_HYPERCALLS_FOR_PAGES */
102
103
104#ifndef IN_RING0
105
106NEM_TMPL_STATIC int nemHCWinCopyStateToHyperV(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
107{
108#ifdef NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS
109 NOREF(pCtx);
110 int rc = VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_EXPORT_STATE, 0, NULL);
111 AssertLogRelRCReturn(rc, rc);
112 return rc;
113
114#else
115 WHV_REGISTER_NAME aenmNames[128];
116 WHV_REGISTER_VALUE aValues[128];
117
118 /* GPRs */
119 aenmNames[0] = WHvX64RegisterRax;
120 aValues[0].Reg64 = pCtx->rax;
121 aenmNames[1] = WHvX64RegisterRcx;
122 aValues[1].Reg64 = pCtx->rcx;
123 aenmNames[2] = WHvX64RegisterRdx;
124 aValues[2].Reg64 = pCtx->rdx;
125 aenmNames[3] = WHvX64RegisterRbx;
126 aValues[3].Reg64 = pCtx->rbx;
127 aenmNames[4] = WHvX64RegisterRsp;
128 aValues[4].Reg64 = pCtx->rsp;
129 aenmNames[5] = WHvX64RegisterRbp;
130 aValues[5].Reg64 = pCtx->rbp;
131 aenmNames[6] = WHvX64RegisterRsi;
132 aValues[6].Reg64 = pCtx->rsi;
133 aenmNames[7] = WHvX64RegisterRdi;
134 aValues[7].Reg64 = pCtx->rdi;
135 aenmNames[8] = WHvX64RegisterR8;
136 aValues[8].Reg64 = pCtx->r8;
137 aenmNames[9] = WHvX64RegisterR9;
138 aValues[9].Reg64 = pCtx->r9;
139 aenmNames[10] = WHvX64RegisterR10;
140 aValues[10].Reg64 = pCtx->r10;
141 aenmNames[11] = WHvX64RegisterR11;
142 aValues[11].Reg64 = pCtx->r11;
143 aenmNames[12] = WHvX64RegisterR12;
144 aValues[12].Reg64 = pCtx->r12;
145 aenmNames[13] = WHvX64RegisterR13;
146 aValues[13].Reg64 = pCtx->r13;
147 aenmNames[14] = WHvX64RegisterR14;
148 aValues[14].Reg64 = pCtx->r14;
149 aenmNames[15] = WHvX64RegisterR15;
150 aValues[15].Reg64 = pCtx->r15;
151
152 /* RIP & Flags */
153 aenmNames[16] = WHvX64RegisterRip;
154 aValues[16].Reg64 = pCtx->rip;
155 aenmNames[17] = WHvX64RegisterRflags;
156 aValues[17].Reg64 = pCtx->rflags.u;
157
158 /* Segments */
159#define COPY_OUT_SEG(a_idx, a_enmName, a_SReg) \
160 do { \
161 aenmNames[a_idx] = a_enmName; \
162 aValues[a_idx].Segment.Base = (a_SReg).u64Base; \
163 aValues[a_idx].Segment.Limit = (a_SReg).u32Limit; \
164 aValues[a_idx].Segment.Selector = (a_SReg).Sel; \
165 aValues[a_idx].Segment.Attributes = (a_SReg).Attr.u; \
166 } while (0)
167 COPY_OUT_SEG(18, WHvX64RegisterEs, pCtx->es);
168 COPY_OUT_SEG(19, WHvX64RegisterCs, pCtx->cs);
169 COPY_OUT_SEG(20, WHvX64RegisterSs, pCtx->ss);
170 COPY_OUT_SEG(21, WHvX64RegisterDs, pCtx->ds);
171 COPY_OUT_SEG(22, WHvX64RegisterFs, pCtx->fs);
172 COPY_OUT_SEG(23, WHvX64RegisterGs, pCtx->gs);
173 COPY_OUT_SEG(24, WHvX64RegisterLdtr, pCtx->ldtr);
174 COPY_OUT_SEG(25, WHvX64RegisterTr, pCtx->tr);
175
176 uintptr_t iReg = 26;
177 /* Descriptor tables. */
178 aenmNames[iReg] = WHvX64RegisterIdtr;
179 aValues[iReg].Table.Limit = pCtx->idtr.cbIdt;
180 aValues[iReg].Table.Base = pCtx->idtr.pIdt;
181 iReg++;
182 aenmNames[iReg] = WHvX64RegisterGdtr;
183 aValues[iReg].Table.Limit = pCtx->gdtr.cbGdt;
184 aValues[iReg].Table.Base = pCtx->gdtr.pGdt;
185 iReg++;
186
187 /* Control registers. */
188 aenmNames[iReg] = WHvX64RegisterCr0;
189 aValues[iReg].Reg64 = pCtx->cr0;
190 iReg++;
191 aenmNames[iReg] = WHvX64RegisterCr2;
192 aValues[iReg].Reg64 = pCtx->cr2;
193 iReg++;
194 aenmNames[iReg] = WHvX64RegisterCr3;
195 aValues[iReg].Reg64 = pCtx->cr3;
196 iReg++;
197 aenmNames[iReg] = WHvX64RegisterCr4;
198 aValues[iReg].Reg64 = pCtx->cr4;
199 iReg++;
200 aenmNames[iReg] = WHvX64RegisterCr8;
201 aValues[iReg].Reg64 = CPUMGetGuestCR8(pVCpu);
202 iReg++;
203
204 /* Debug registers. */
205/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
206 aenmNames[iReg] = WHvX64RegisterDr0;
207 //aValues[iReg].Reg64 = CPUMGetHyperDR0(pVCpu);
208 aValues[iReg].Reg64 = pCtx->dr[0];
209 iReg++;
210 aenmNames[iReg] = WHvX64RegisterDr1;
211 //aValues[iReg].Reg64 = CPUMGetHyperDR1(pVCpu);
212 aValues[iReg].Reg64 = pCtx->dr[1];
213 iReg++;
214 aenmNames[iReg] = WHvX64RegisterDr2;
215 //aValues[iReg].Reg64 = CPUMGetHyperDR2(pVCpu);
216 aValues[iReg].Reg64 = pCtx->dr[2];
217 iReg++;
218 aenmNames[iReg] = WHvX64RegisterDr3;
219 //aValues[iReg].Reg64 = CPUMGetHyperDR3(pVCpu);
220 aValues[iReg].Reg64 = pCtx->dr[3];
221 iReg++;
222 aenmNames[iReg] = WHvX64RegisterDr6;
223 //aValues[iReg].Reg64 = CPUMGetHyperDR6(pVCpu);
224 aValues[iReg].Reg64 = pCtx->dr[6];
225 iReg++;
226 aenmNames[iReg] = WHvX64RegisterDr7;
227 //aValues[iReg].Reg64 = CPUMGetHyperDR7(pVCpu);
228 aValues[iReg].Reg64 = pCtx->dr[7];
229 iReg++;
230
231 /* Vector state. */
232 aenmNames[iReg] = WHvX64RegisterXmm0;
233 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Lo;
234 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Hi;
235 iReg++;
236 aenmNames[iReg] = WHvX64RegisterXmm1;
237 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Lo;
238 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Hi;
239 iReg++;
240 aenmNames[iReg] = WHvX64RegisterXmm2;
241 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Lo;
242 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Hi;
243 iReg++;
244 aenmNames[iReg] = WHvX64RegisterXmm3;
245 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Lo;
246 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Hi;
247 iReg++;
248 aenmNames[iReg] = WHvX64RegisterXmm4;
249 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Lo;
250 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Hi;
251 iReg++;
252 aenmNames[iReg] = WHvX64RegisterXmm5;
253 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Lo;
254 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Hi;
255 iReg++;
256 aenmNames[iReg] = WHvX64RegisterXmm6;
257 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Lo;
258 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Hi;
259 iReg++;
260 aenmNames[iReg] = WHvX64RegisterXmm7;
261 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Lo;
262 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Hi;
263 iReg++;
264 aenmNames[iReg] = WHvX64RegisterXmm8;
265 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Lo;
266 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Hi;
267 iReg++;
268 aenmNames[iReg] = WHvX64RegisterXmm9;
269 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Lo;
270 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Hi;
271 iReg++;
272 aenmNames[iReg] = WHvX64RegisterXmm10;
273 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Lo;
274 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Hi;
275 iReg++;
276 aenmNames[iReg] = WHvX64RegisterXmm11;
277 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Lo;
278 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Hi;
279 iReg++;
280 aenmNames[iReg] = WHvX64RegisterXmm12;
281 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Lo;
282 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Hi;
283 iReg++;
284 aenmNames[iReg] = WHvX64RegisterXmm13;
285 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Lo;
286 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Hi;
287 iReg++;
288 aenmNames[iReg] = WHvX64RegisterXmm14;
289 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Lo;
290 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Hi;
291 iReg++;
292 aenmNames[iReg] = WHvX64RegisterXmm15;
293 aValues[iReg].Reg128.Low64 = pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Lo;
294 aValues[iReg].Reg128.High64 = pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Hi;
295 iReg++;
296
297 /* Floating point state. */
298 aenmNames[iReg] = WHvX64RegisterFpMmx0;
299 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[0].au64[0];
300 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[0].au64[1];
301 iReg++;
302 aenmNames[iReg] = WHvX64RegisterFpMmx1;
303 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[1].au64[0];
304 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[1].au64[1];
305 iReg++;
306 aenmNames[iReg] = WHvX64RegisterFpMmx2;
307 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[2].au64[0];
308 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[2].au64[1];
309 iReg++;
310 aenmNames[iReg] = WHvX64RegisterFpMmx3;
311 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[3].au64[0];
312 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[3].au64[1];
313 iReg++;
314 aenmNames[iReg] = WHvX64RegisterFpMmx4;
315 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[4].au64[0];
316 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[4].au64[1];
317 iReg++;
318 aenmNames[iReg] = WHvX64RegisterFpMmx5;
319 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[5].au64[0];
320 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[5].au64[1];
321 iReg++;
322 aenmNames[iReg] = WHvX64RegisterFpMmx6;
323 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[6].au64[0];
324 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[6].au64[1];
325 iReg++;
326 aenmNames[iReg] = WHvX64RegisterFpMmx7;
327 aValues[iReg].Fp.AsUINT128.Low64 = pCtx->pXStateR3->x87.aRegs[7].au64[0];
328 aValues[iReg].Fp.AsUINT128.High64 = pCtx->pXStateR3->x87.aRegs[7].au64[1];
329 iReg++;
330
331 aenmNames[iReg] = WHvX64RegisterFpControlStatus;
332 aValues[iReg].FpControlStatus.FpControl = pCtx->pXStateR3->x87.FCW;
333 aValues[iReg].FpControlStatus.FpStatus = pCtx->pXStateR3->x87.FSW;
334 aValues[iReg].FpControlStatus.FpTag = pCtx->pXStateR3->x87.FTW;
335 aValues[iReg].FpControlStatus.Reserved = pCtx->pXStateR3->x87.FTW >> 8;
336 aValues[iReg].FpControlStatus.LastFpOp = pCtx->pXStateR3->x87.FOP;
337 aValues[iReg].FpControlStatus.LastFpRip = (pCtx->pXStateR3->x87.FPUIP)
338 | ((uint64_t)pCtx->pXStateR3->x87.CS << 32)
339 | ((uint64_t)pCtx->pXStateR3->x87.Rsrvd1 << 48);
340 iReg++;
341
342 aenmNames[iReg] = WHvX64RegisterXmmControlStatus;
343 aValues[iReg].XmmControlStatus.LastFpRdp = (pCtx->pXStateR3->x87.FPUDP)
344 | ((uint64_t)pCtx->pXStateR3->x87.DS << 32)
345 | ((uint64_t)pCtx->pXStateR3->x87.Rsrvd2 << 48);
346 aValues[iReg].XmmControlStatus.XmmStatusControl = pCtx->pXStateR3->x87.MXCSR;
347 aValues[iReg].XmmControlStatus.XmmStatusControlMask = pCtx->pXStateR3->x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
348 iReg++;
349
350 /* MSRs */
351 // WHvX64RegisterTsc - don't touch
352 aenmNames[iReg] = WHvX64RegisterEfer;
353 aValues[iReg].Reg64 = pCtx->msrEFER;
354 iReg++;
355 aenmNames[iReg] = WHvX64RegisterKernelGsBase;
356 aValues[iReg].Reg64 = pCtx->msrKERNELGSBASE;
357 iReg++;
358 aenmNames[iReg] = WHvX64RegisterApicBase;
359 aValues[iReg].Reg64 = APICGetBaseMsrNoCheck(pVCpu);
360 iReg++;
361 aenmNames[iReg] = WHvX64RegisterPat;
362 aValues[iReg].Reg64 = pCtx->msrPAT;
363 iReg++;
364 /// @todo WHvX64RegisterSysenterCs
365 /// @todo WHvX64RegisterSysenterEip
366 /// @todo WHvX64RegisterSysenterEsp
367 aenmNames[iReg] = WHvX64RegisterStar;
368 aValues[iReg].Reg64 = pCtx->msrSTAR;
369 iReg++;
370 aenmNames[iReg] = WHvX64RegisterLstar;
371 aValues[iReg].Reg64 = pCtx->msrLSTAR;
372 iReg++;
373 aenmNames[iReg] = WHvX64RegisterCstar;
374 aValues[iReg].Reg64 = pCtx->msrCSTAR;
375 iReg++;
376 aenmNames[iReg] = WHvX64RegisterSfmask;
377 aValues[iReg].Reg64 = pCtx->msrSFMASK;
378 iReg++;
379
380 /* event injection (always clear it). */
381 aenmNames[iReg] = WHvRegisterPendingInterruption;
382 aValues[iReg].Reg64 = 0;
383 iReg++;
384 /// @todo WHvRegisterInterruptState
385 /// @todo WHvRegisterPendingEvent0
386 /// @todo WHvRegisterPendingEvent1
387
388 /*
389 * Set the registers.
390 */
391 Assert(iReg < RT_ELEMENTS(aValues));
392 Assert(iReg < RT_ELEMENTS(aenmNames));
393#ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
394 Log12(("Calling WHvSetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
395 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues));
396#endif
397 HRESULT hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues);
398 if (SUCCEEDED(hrc))
399 return VINF_SUCCESS;
400 AssertLogRelMsgFailed(("WHvSetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
401 pVM->nem.s.hPartition, pVCpu->idCpu, iReg,
402 hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
403 return VERR_INTERNAL_ERROR;
404#endif /* !NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS */
405}
406
407
408NEM_TMPL_STATIC int nemHCWinCopyStateFromHyperV(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fWhat)
409{
410#ifdef NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS
411 /* See NEMR0ImportState */
412 NOREF(pCtx);
413 int rc = VMMR3CallR0Emt(pVM, pVCpu, VMMR0_DO_NEM_IMPORT_STATE, fWhat, NULL);
414 if (RT_SUCCESS(rc))
415 return rc;
416 if (rc == VERR_NEM_FLUSH_TLB)
417 return PGMFlushTLB(pVCpu, pCtx->cr3, true /*fGlobal*/);
418 if (rc == VERR_NEM_CHANGE_PGM_MODE)
419 return PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
420 AssertLogRelRCReturn(rc, rc);
421 return rc;
422
423#else
424 WHV_REGISTER_NAME aenmNames[128];
425
426 /* GPRs */
427 aenmNames[0] = WHvX64RegisterRax;
428 aenmNames[1] = WHvX64RegisterRcx;
429 aenmNames[2] = WHvX64RegisterRdx;
430 aenmNames[3] = WHvX64RegisterRbx;
431 aenmNames[4] = WHvX64RegisterRsp;
432 aenmNames[5] = WHvX64RegisterRbp;
433 aenmNames[6] = WHvX64RegisterRsi;
434 aenmNames[7] = WHvX64RegisterRdi;
435 aenmNames[8] = WHvX64RegisterR8;
436 aenmNames[9] = WHvX64RegisterR9;
437 aenmNames[10] = WHvX64RegisterR10;
438 aenmNames[11] = WHvX64RegisterR11;
439 aenmNames[12] = WHvX64RegisterR12;
440 aenmNames[13] = WHvX64RegisterR13;
441 aenmNames[14] = WHvX64RegisterR14;
442 aenmNames[15] = WHvX64RegisterR15;
443
444 /* RIP & Flags */
445 aenmNames[16] = WHvX64RegisterRip;
446 aenmNames[17] = WHvX64RegisterRflags;
447
448 /* Segments */
449 aenmNames[18] = WHvX64RegisterEs;
450 aenmNames[19] = WHvX64RegisterCs;
451 aenmNames[20] = WHvX64RegisterSs;
452 aenmNames[21] = WHvX64RegisterDs;
453 aenmNames[22] = WHvX64RegisterFs;
454 aenmNames[23] = WHvX64RegisterGs;
455 aenmNames[24] = WHvX64RegisterLdtr;
456 aenmNames[25] = WHvX64RegisterTr;
457
458 /* Descriptor tables. */
459 aenmNames[26] = WHvX64RegisterIdtr;
460 aenmNames[27] = WHvX64RegisterGdtr;
461
462 /* Control registers. */
463 aenmNames[28] = WHvX64RegisterCr0;
464 aenmNames[29] = WHvX64RegisterCr2;
465 aenmNames[30] = WHvX64RegisterCr3;
466 aenmNames[31] = WHvX64RegisterCr4;
467 aenmNames[32] = WHvX64RegisterCr8;
468
469 /* Debug registers. */
470 aenmNames[33] = WHvX64RegisterDr0;
471 aenmNames[34] = WHvX64RegisterDr1;
472 aenmNames[35] = WHvX64RegisterDr2;
473 aenmNames[36] = WHvX64RegisterDr3;
474 aenmNames[37] = WHvX64RegisterDr6;
475 aenmNames[38] = WHvX64RegisterDr7;
476
477 /* Vector state. */
478 aenmNames[39] = WHvX64RegisterXmm0;
479 aenmNames[40] = WHvX64RegisterXmm1;
480 aenmNames[41] = WHvX64RegisterXmm2;
481 aenmNames[42] = WHvX64RegisterXmm3;
482 aenmNames[43] = WHvX64RegisterXmm4;
483 aenmNames[44] = WHvX64RegisterXmm5;
484 aenmNames[45] = WHvX64RegisterXmm6;
485 aenmNames[46] = WHvX64RegisterXmm7;
486 aenmNames[47] = WHvX64RegisterXmm8;
487 aenmNames[48] = WHvX64RegisterXmm9;
488 aenmNames[49] = WHvX64RegisterXmm10;
489 aenmNames[50] = WHvX64RegisterXmm11;
490 aenmNames[51] = WHvX64RegisterXmm12;
491 aenmNames[52] = WHvX64RegisterXmm13;
492 aenmNames[53] = WHvX64RegisterXmm14;
493 aenmNames[54] = WHvX64RegisterXmm15;
494
495 /* Floating point state. */
496 aenmNames[55] = WHvX64RegisterFpMmx0;
497 aenmNames[56] = WHvX64RegisterFpMmx1;
498 aenmNames[57] = WHvX64RegisterFpMmx2;
499 aenmNames[58] = WHvX64RegisterFpMmx3;
500 aenmNames[59] = WHvX64RegisterFpMmx4;
501 aenmNames[60] = WHvX64RegisterFpMmx5;
502 aenmNames[61] = WHvX64RegisterFpMmx6;
503 aenmNames[62] = WHvX64RegisterFpMmx7;
504 aenmNames[63] = WHvX64RegisterFpControlStatus;
505 aenmNames[64] = WHvX64RegisterXmmControlStatus;
506
507 /* MSRs */
508 // WHvX64RegisterTsc - don't touch
509 aenmNames[65] = WHvX64RegisterEfer;
510 aenmNames[66] = WHvX64RegisterKernelGsBase;
511 aenmNames[67] = WHvX64RegisterApicBase;
512 aenmNames[68] = WHvX64RegisterPat;
513 aenmNames[69] = WHvX64RegisterSysenterCs;
514 aenmNames[70] = WHvX64RegisterSysenterEip;
515 aenmNames[71] = WHvX64RegisterSysenterEsp;
516 aenmNames[72] = WHvX64RegisterStar;
517 aenmNames[73] = WHvX64RegisterLstar;
518 aenmNames[74] = WHvX64RegisterCstar;
519 aenmNames[75] = WHvX64RegisterSfmask;
520
521 /* event injection */
522 aenmNames[76] = WHvRegisterPendingInterruption;
523 aenmNames[77] = WHvRegisterInterruptState;
524 aenmNames[78] = WHvRegisterInterruptState;
525 aenmNames[79] = WHvRegisterPendingEvent0;
526 aenmNames[80] = WHvRegisterPendingEvent1;
527 unsigned const cRegs = 81;
528
529 /*
530 * Get the registers.
531 */
532 WHV_REGISTER_VALUE aValues[cRegs];
533 RT_ZERO(aValues);
534 Assert(RT_ELEMENTS(aValues) >= cRegs);
535 Assert(RT_ELEMENTS(aenmNames) >= cRegs);
536#ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
537 Log12(("Calling WHvGetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
538 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues));
539#endif
540 HRESULT hrc = WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues);
541 if (SUCCEEDED(hrc))
542 {
543 /* GPRs */
544 Assert(aenmNames[0] == WHvX64RegisterRax);
545 Assert(aenmNames[15] == WHvX64RegisterR15);
546 pCtx->rax = aValues[0].Reg64;
547 pCtx->rcx = aValues[1].Reg64;
548 pCtx->rdx = aValues[2].Reg64;
549 pCtx->rbx = aValues[3].Reg64;
550 pCtx->rsp = aValues[4].Reg64;
551 pCtx->rbp = aValues[5].Reg64;
552 pCtx->rsi = aValues[6].Reg64;
553 pCtx->rdi = aValues[7].Reg64;
554 pCtx->r8 = aValues[8].Reg64;
555 pCtx->r9 = aValues[9].Reg64;
556 pCtx->r10 = aValues[10].Reg64;
557 pCtx->r11 = aValues[11].Reg64;
558 pCtx->r12 = aValues[12].Reg64;
559 pCtx->r13 = aValues[13].Reg64;
560 pCtx->r14 = aValues[14].Reg64;
561 pCtx->r15 = aValues[15].Reg64;
562
563 /* RIP & Flags */
564 Assert(aenmNames[16] == WHvX64RegisterRip);
565 pCtx->rip = aValues[16].Reg64;
566 pCtx->rflags.u = aValues[17].Reg64;
567
568 /* Segments */
569#define COPY_BACK_SEG(a_idx, a_enmName, a_SReg) \
570 do { \
571 Assert(aenmNames[a_idx] == a_enmName); \
572 NEM_WIN_COPY_BACK_SEG(a_SReg, aValues[a_idx]); \
573 } while (0)
574 COPY_BACK_SEG(18, WHvX64RegisterEs, pCtx->es);
575 COPY_BACK_SEG(19, WHvX64RegisterCs, pCtx->cs);
576 COPY_BACK_SEG(20, WHvX64RegisterSs, pCtx->ss);
577 COPY_BACK_SEG(21, WHvX64RegisterDs, pCtx->ds);
578 COPY_BACK_SEG(22, WHvX64RegisterFs, pCtx->fs);
579 COPY_BACK_SEG(23, WHvX64RegisterGs, pCtx->gs);
580 COPY_BACK_SEG(24, WHvX64RegisterLdtr, pCtx->ldtr);
581 COPY_BACK_SEG(25, WHvX64RegisterTr, pCtx->tr);
582
583 /* Descriptor tables. */
584 Assert(aenmNames[26] == WHvX64RegisterIdtr);
585 pCtx->idtr.cbIdt = aValues[26].Table.Limit;
586 pCtx->idtr.pIdt = aValues[26].Table.Base;
587 Assert(aenmNames[27] == WHvX64RegisterGdtr);
588 pCtx->gdtr.cbGdt = aValues[27].Table.Limit;
589 pCtx->gdtr.pGdt = aValues[27].Table.Base;
590
591 /* Control registers. */
592 Assert(aenmNames[28] == WHvX64RegisterCr0);
593 bool fMaybeChangedMode = false;
594 bool fFlushTlb = false;
595 bool fFlushGlobalTlb = false;
596 if (pCtx->cr0 != aValues[28].Reg64)
597 {
598 CPUMSetGuestCR0(pVCpu, aValues[28].Reg64);
599 fMaybeChangedMode = true;
600 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
601 }
602 Assert(aenmNames[29] == WHvX64RegisterCr2);
603 pCtx->cr2 = aValues[29].Reg64;
604 if (pCtx->cr3 != aValues[30].Reg64)
605 {
606 CPUMSetGuestCR3(pVCpu, aValues[30].Reg64);
607 fFlushTlb = true;
608 }
609 if (pCtx->cr4 != aValues[31].Reg64)
610 {
611 CPUMSetGuestCR4(pVCpu, aValues[31].Reg64);
612 fMaybeChangedMode = true;
613 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
614 }
615 APICSetTpr(pVCpu, (uint8_t)aValues[32].Reg64 << 4);
616
617 /* Debug registers. */
618 Assert(aenmNames[33] == WHvX64RegisterDr0);
619 /** @todo fixme */
620 if (pCtx->dr[0] != aValues[33].Reg64)
621 CPUMSetGuestDR0(pVCpu, aValues[33].Reg64);
622 if (pCtx->dr[1] != aValues[34].Reg64)
623 CPUMSetGuestDR1(pVCpu, aValues[34].Reg64);
624 if (pCtx->dr[2] != aValues[35].Reg64)
625 CPUMSetGuestDR2(pVCpu, aValues[35].Reg64);
626 if (pCtx->dr[3] != aValues[36].Reg64)
627 CPUMSetGuestDR3(pVCpu, aValues[36].Reg64);
628 Assert(aenmNames[37] == WHvX64RegisterDr6);
629 Assert(aenmNames[38] == WHvX64RegisterDr7);
630 if (pCtx->dr[6] != aValues[37].Reg64)
631 CPUMSetGuestDR6(pVCpu, aValues[37].Reg64);
632 if (pCtx->dr[7] != aValues[38].Reg64)
633 CPUMSetGuestDR6(pVCpu, aValues[38].Reg64);
634
635 /* Vector state. */
636 Assert(aenmNames[39] == WHvX64RegisterXmm0);
637 Assert(aenmNames[54] == WHvX64RegisterXmm15);
638 pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Lo = aValues[39].Reg128.Low64;
639 pCtx->pXStateR3->x87.aXMM[0].uXmm.s.Hi = aValues[39].Reg128.High64;
640 pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Lo = aValues[40].Reg128.Low64;
641 pCtx->pXStateR3->x87.aXMM[1].uXmm.s.Hi = aValues[40].Reg128.High64;
642 pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Lo = aValues[41].Reg128.Low64;
643 pCtx->pXStateR3->x87.aXMM[2].uXmm.s.Hi = aValues[41].Reg128.High64;
644 pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Lo = aValues[42].Reg128.Low64;
645 pCtx->pXStateR3->x87.aXMM[3].uXmm.s.Hi = aValues[42].Reg128.High64;
646 pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Lo = aValues[43].Reg128.Low64;
647 pCtx->pXStateR3->x87.aXMM[4].uXmm.s.Hi = aValues[43].Reg128.High64;
648 pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Lo = aValues[44].Reg128.Low64;
649 pCtx->pXStateR3->x87.aXMM[5].uXmm.s.Hi = aValues[44].Reg128.High64;
650 pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Lo = aValues[45].Reg128.Low64;
651 pCtx->pXStateR3->x87.aXMM[6].uXmm.s.Hi = aValues[45].Reg128.High64;
652 pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Lo = aValues[46].Reg128.Low64;
653 pCtx->pXStateR3->x87.aXMM[7].uXmm.s.Hi = aValues[46].Reg128.High64;
654 pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Lo = aValues[47].Reg128.Low64;
655 pCtx->pXStateR3->x87.aXMM[8].uXmm.s.Hi = aValues[47].Reg128.High64;
656 pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Lo = aValues[48].Reg128.Low64;
657 pCtx->pXStateR3->x87.aXMM[9].uXmm.s.Hi = aValues[48].Reg128.High64;
658 pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Lo = aValues[49].Reg128.Low64;
659 pCtx->pXStateR3->x87.aXMM[10].uXmm.s.Hi = aValues[49].Reg128.High64;
660 pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Lo = aValues[50].Reg128.Low64;
661 pCtx->pXStateR3->x87.aXMM[11].uXmm.s.Hi = aValues[50].Reg128.High64;
662 pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Lo = aValues[51].Reg128.Low64;
663 pCtx->pXStateR3->x87.aXMM[12].uXmm.s.Hi = aValues[51].Reg128.High64;
664 pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Lo = aValues[52].Reg128.Low64;
665 pCtx->pXStateR3->x87.aXMM[13].uXmm.s.Hi = aValues[52].Reg128.High64;
666 pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Lo = aValues[53].Reg128.Low64;
667 pCtx->pXStateR3->x87.aXMM[14].uXmm.s.Hi = aValues[53].Reg128.High64;
668 pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Lo = aValues[54].Reg128.Low64;
669 pCtx->pXStateR3->x87.aXMM[15].uXmm.s.Hi = aValues[54].Reg128.High64;
670
671 /* Floating point state. */
672 Assert(aenmNames[55] == WHvX64RegisterFpMmx0);
673 Assert(aenmNames[62] == WHvX64RegisterFpMmx7);
674 pCtx->pXStateR3->x87.aRegs[0].au64[0] = aValues[55].Fp.AsUINT128.Low64;
675 pCtx->pXStateR3->x87.aRegs[0].au64[1] = aValues[55].Fp.AsUINT128.High64;
676 pCtx->pXStateR3->x87.aRegs[1].au64[0] = aValues[56].Fp.AsUINT128.Low64;
677 pCtx->pXStateR3->x87.aRegs[1].au64[1] = aValues[56].Fp.AsUINT128.High64;
678 pCtx->pXStateR3->x87.aRegs[2].au64[0] = aValues[57].Fp.AsUINT128.Low64;
679 pCtx->pXStateR3->x87.aRegs[2].au64[1] = aValues[57].Fp.AsUINT128.High64;
680 pCtx->pXStateR3->x87.aRegs[3].au64[0] = aValues[58].Fp.AsUINT128.Low64;
681 pCtx->pXStateR3->x87.aRegs[3].au64[1] = aValues[58].Fp.AsUINT128.High64;
682 pCtx->pXStateR3->x87.aRegs[4].au64[0] = aValues[59].Fp.AsUINT128.Low64;
683 pCtx->pXStateR3->x87.aRegs[4].au64[1] = aValues[59].Fp.AsUINT128.High64;
684 pCtx->pXStateR3->x87.aRegs[5].au64[0] = aValues[60].Fp.AsUINT128.Low64;
685 pCtx->pXStateR3->x87.aRegs[5].au64[1] = aValues[60].Fp.AsUINT128.High64;
686 pCtx->pXStateR3->x87.aRegs[6].au64[0] = aValues[61].Fp.AsUINT128.Low64;
687 pCtx->pXStateR3->x87.aRegs[6].au64[1] = aValues[61].Fp.AsUINT128.High64;
688 pCtx->pXStateR3->x87.aRegs[7].au64[0] = aValues[62].Fp.AsUINT128.Low64;
689 pCtx->pXStateR3->x87.aRegs[7].au64[1] = aValues[62].Fp.AsUINT128.High64;
690
691 Assert(aenmNames[63] == WHvX64RegisterFpControlStatus);
692 pCtx->pXStateR3->x87.FCW = aValues[63].FpControlStatus.FpControl;
693 pCtx->pXStateR3->x87.FSW = aValues[63].FpControlStatus.FpStatus;
694 pCtx->pXStateR3->x87.FTW = aValues[63].FpControlStatus.FpTag
695 /*| (aValues[63].FpControlStatus.Reserved << 8)*/;
696 pCtx->pXStateR3->x87.FOP = aValues[63].FpControlStatus.LastFpOp;
697 pCtx->pXStateR3->x87.FPUIP = (uint32_t)aValues[63].FpControlStatus.LastFpRip;
698 pCtx->pXStateR3->x87.CS = (uint16_t)(aValues[63].FpControlStatus.LastFpRip >> 32);
699 pCtx->pXStateR3->x87.Rsrvd1 = (uint16_t)(aValues[63].FpControlStatus.LastFpRip >> 48);
700
701 Assert(aenmNames[64] == WHvX64RegisterXmmControlStatus);
702 pCtx->pXStateR3->x87.FPUDP = (uint32_t)aValues[64].XmmControlStatus.LastFpRdp;
703 pCtx->pXStateR3->x87.DS = (uint16_t)(aValues[64].XmmControlStatus.LastFpRdp >> 32);
704 pCtx->pXStateR3->x87.Rsrvd2 = (uint16_t)(aValues[64].XmmControlStatus.LastFpRdp >> 48);
705 pCtx->pXStateR3->x87.MXCSR = aValues[64].XmmControlStatus.XmmStatusControl;
706 pCtx->pXStateR3->x87.MXCSR_MASK = aValues[64].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
707
708 /* MSRs */
709 // WHvX64RegisterTsc - don't touch
710 Assert(aenmNames[65] == WHvX64RegisterEfer);
711 if (aValues[65].Reg64 != pCtx->msrEFER)
712 {
713 pCtx->msrEFER = aValues[65].Reg64;
714 fMaybeChangedMode = true;
715 }
716
717 Assert(aenmNames[66] == WHvX64RegisterKernelGsBase);
718 pCtx->msrKERNELGSBASE = aValues[66].Reg64;
719
720 Assert(aenmNames[67] == WHvX64RegisterApicBase);
721 if (aValues[67].Reg64 != APICGetBaseMsrNoCheck(pVCpu))
722 {
723 VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, aValues[67].Reg64);
724 Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
725 }
726
727 Assert(aenmNames[68] == WHvX64RegisterPat);
728 pCtx->msrPAT = aValues[68].Reg64;
729 /// @todo WHvX64RegisterSysenterCs
730 /// @todo WHvX64RegisterSysenterEip
731 /// @todo WHvX64RegisterSysenterEsp
732 Assert(aenmNames[72] == WHvX64RegisterStar);
733 pCtx->msrSTAR = aValues[72].Reg64;
734 Assert(aenmNames[73] == WHvX64RegisterLstar);
735 pCtx->msrLSTAR = aValues[73].Reg64;
736 Assert(aenmNames[74] == WHvX64RegisterCstar);
737 pCtx->msrCSTAR = aValues[74].Reg64;
738 Assert(aenmNames[75] == WHvX64RegisterSfmask);
739 pCtx->msrSFMASK = aValues[75].Reg64;
740
741 /// @todo WHvRegisterPendingInterruption
742 Assert(aenmNames[76] == WHvRegisterPendingInterruption);
743 WHV_X64_PENDING_INTERRUPTION_REGISTER const * pPendingInt = (WHV_X64_PENDING_INTERRUPTION_REGISTER const *)&aValues[76];
744 if (pPendingInt->InterruptionPending)
745 {
746 Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
747 pPendingInt->InterruptionType, pPendingInt->InterruptionVector, pPendingInt->DeliverErrorCode,
748 pPendingInt->ErrorCode, pPendingInt->InstructionLength, pPendingInt->NestedEvent));
749 AssertMsg((pPendingInt->AsUINT64 & UINT64_C(0xfc00)) == 0, ("%#RX64\n", pPendingInt->AsUINT64));
750 }
751
752 /// @todo WHvRegisterInterruptState
753 /// @todo WHvRegisterPendingEvent0
754 /// @todo WHvRegisterPendingEvent1
755
756 pCtx->fExtrn = 0;
757
758 if (fMaybeChangedMode)
759 {
760 int rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
761 AssertRC(rc);
762 }
763 if (fFlushTlb)
764 {
765 int rc = PGMFlushTLB(pVCpu, pCtx->cr3, fFlushGlobalTlb);
766 AssertRC(rc);
767 }
768
769 return VINF_SUCCESS;
770 }
771
772 AssertLogRelMsgFailed(("WHvGetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
773 pVM->nem.s.hPartition, pVCpu->idCpu, cRegs,
774 hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
775 return VERR_INTERNAL_ERROR;
776#endif /* !NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS */
777}
778
779
780#ifdef LOG_ENABLED
781/**
782 * Get the virtual processor running status.
783 */
784DECLINLINE(VID_PROCESSOR_STATUS) nemHCWinCpuGetRunningStatus(PVMCPU pVCpu)
785{
786# ifdef IN_RING0
787 NOREF(pVCpu);
788 return VidProcessorStatusUndefined;
789# else
790 RTERRVARS Saved;
791 RTErrVarsSave(&Saved);
792
793 /*
794 * This API is disabled in release builds, it seems. On build 17101 it requires
795 * the following patch to be enabled (windbg): eb vid+12180 0f 84 98 00 00 00
796 */
797 VID_PROCESSOR_STATUS enmCpuStatus = VidProcessorStatusUndefined;
798 NTSTATUS rcNt = g_pfnVidGetVirtualProcessorRunningStatus(pVCpu->pVMR3->nem.s.hPartitionDevice, pVCpu->idCpu, &enmCpuStatus);
799 AssertRC(rcNt);
800
801 RTErrVarsRestore(&Saved);
802 return enmCpuStatus;
803# endif
804}
805#endif
806
807
808#ifdef NEM_WIN_USE_OUR_OWN_RUN_API
809# ifdef IN_RING3 /* hopefully not needed in ring-0, as we'd need KTHREADs and KeAlertThread. */
810/**
811 * Our own WHvCancelRunVirtualProcessor that can later be moved to ring-0.
812 *
813 * This is an experiment only.
814 *
815 * @returns VBox status code.
816 * @param pVM The cross context VM structure.
817 * @param pVCpu The cross context virtual CPU structure of the
818 * calling EMT.
819 */
820NEM_TMPL_STATIC int nemHCWinCancelRunVirtualProcessor(PVM pVM, PVMCPU pVCpu)
821{
822 /*
823 * Work the state.
824 *
825 * From the looks of things, we should let the EMT call VidStopVirtualProcessor.
826 * So, we just need to modify the state and kick the EMT if it's waiting on
827 * messages. For the latter we use QueueUserAPC / KeAlterThread.
828 */
829 for (;;)
830 {
831 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu);
832 switch (enmState)
833 {
834 case VMCPUSTATE_STARTED_EXEC_NEM:
835 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED, VMCPUSTATE_STARTED_EXEC_NEM))
836 {
837 Log8(("nemHCWinCancelRunVirtualProcessor: Switched %u to canceled state\n", pVCpu->idCpu));
838 return VINF_SUCCESS;
839 }
840 break;
841
842 case VMCPUSTATE_STARTED_EXEC_NEM_WAIT:
843 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED, VMCPUSTATE_STARTED_EXEC_NEM_WAIT))
844 {
845# ifdef IN_RING0
846 NTSTATUS rcNt = KeAlertThread(??);
847# else
848 NTSTATUS rcNt = NtAlertThread(pVCpu->nem.s.hNativeThreadHandle);
849# endif
850 Log8(("nemHCWinCancelRunVirtualProcessor: Alerted %u: %#x\n", pVCpu->idCpu, rcNt));
851 Assert(rcNt == STATUS_SUCCESS);
852 if (NT_SUCCESS(rcNt))
853 return VINF_SUCCESS;
854 AssertLogRelMsgFailedReturn(("NtAlertThread failed: %#x\n", rcNt), RTErrConvertFromNtStatus(rcNt));
855 }
856 break;
857
858 default:
859 return VINF_SUCCESS;
860 }
861
862 ASMNopPause();
863 RT_NOREF(pVM);
864 }
865}
866# endif /* IN_RING3 */
867#endif /* NEM_WIN_USE_OUR_OWN_RUN_API */
868
869
870#ifdef LOG_ENABLED
871/**
872 * Logs the current CPU state.
873 */
874NEM_TMPL_STATIC void nemHCWinLogState(PVM pVM, PVMCPU pVCpu)
875{
876 if (LogIs3Enabled())
877 {
878# ifdef IN_RING3
879 char szRegs[4096];
880 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
881 "rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
882 "rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
883 "r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
884 "r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
885 "rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
886 "cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
887 "ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
888 "es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
889 "fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
890 "gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
891 "ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
892 "dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
893 "dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
894 "gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
895 "ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
896 "tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
897 " sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
898 " efer=%016VR{efer}\n"
899 " pat=%016VR{pat}\n"
900 " sf_mask=%016VR{sf_mask}\n"
901 "krnl_gs_base=%016VR{krnl_gs_base}\n"
902 " lstar=%016VR{lstar}\n"
903 " star=%016VR{star} cstar=%016VR{cstar}\n"
904 "fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
905 );
906
907 char szInstr[256];
908 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
909 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
910 szInstr, sizeof(szInstr), NULL);
911 Log3(("%s%s\n", szRegs, szInstr));
912# else
913 /** @todo stat logging in ring-0 */
914 RT_NOREF(pVM, pVCpu);
915# endif
916 }
917}
918#endif /* LOG_ENABLED */
919
920
921/**
922 * Advances the guest RIP and clear EFLAGS.RF.
923 *
924 * This may clear VMCPU_FF_INHIBIT_INTERRUPTS.
925 *
926 * @param pVCpu The cross context virtual CPU structure.
927 * @param pCtx The CPU context to update.
928 * @param pExitCtx The exit context.
929 */
930DECLINLINE(void) nemHCWinAdvanceGuestRipAndClearRF(PVMCPU pVCpu, PCPUMCTX pCtx, HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr)
931{
932 Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)));
933
934 /* Advance the RIP. */
935 Assert(pMsgHdr->InstructionLength > 0 && pMsgHdr->InstructionLength < 16);
936 pCtx->rip += pMsgHdr->InstructionLength;
937 pCtx->rflags.Bits.u1RF = 0;
938
939 /* Update interrupt inhibition. */
940 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
941 { /* likely */ }
942 else if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
943 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
944}
945
946
947NEM_TMPL_STATIC VBOXSTRICTRC
948nemHCWinHandleHalt(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
949{
950 NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
951 LogFlow(("nemHCWinHandleHalt\n"));
952 return VINF_EM_HALT;
953}
954
955
956NEM_TMPL_STATIC DECLCALLBACK(int)
957nemHCWinUnmapOnePageCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint8_t *pu2NemState, void *pvUser)
958{
959 RT_NOREF_PV(pvUser);
960#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
961 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
962 AssertRC(rc);
963 if (RT_SUCCESS(rc))
964#else
965 RT_NOREF_PV(pVCpu);
966 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
967 if (SUCCEEDED(hrc))
968#endif
969 {
970 Log5(("NEM GPA unmap all: %RGp (cMappedPages=%u)\n", GCPhys, pVM->nem.s.cMappedPages - 1));
971 *pu2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
972 }
973 else
974 {
975#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
976 LogRel(("nemR3WinUnmapOnePageCallback: GCPhys=%RGp rc=%Rrc\n", GCPhys, rc));
977#else
978 LogRel(("nemR3WinUnmapOnePageCallback: GCPhys=%RGp %s hrc=%Rhrc (%#x) Last=%#x/%u (cMappedPages=%u)\n",
979 GCPhys, g_apszPageStates[*pu2NemState], hrc, hrc, RTNtLastStatusValue(),
980 RTNtLastErrorValue(), pVM->nem.s.cMappedPages));
981#endif
982 *pu2NemState = NEM_WIN_PAGE_STATE_NOT_SET;
983 }
984 if (pVM->nem.s.cMappedPages > 0)
985 ASMAtomicDecU32(&pVM->nem.s.cMappedPages);
986 return VINF_SUCCESS;
987}
988
989
990/**
991 * State to pass between nemHCWinHandleMemoryAccess / nemR3WinWHvHandleMemoryAccess
992 * and nemHCWinHandleMemoryAccessPageCheckerCallback.
993 */
994typedef struct NEMHCWINHMACPCCSTATE
995{
996 /** Input: Write access. */
997 bool fWriteAccess;
998 /** Output: Set if we did something. */
999 bool fDidSomething;
1000 /** Output: Set it we should resume. */
1001 bool fCanResume;
1002} NEMHCWINHMACPCCSTATE;
1003
1004/**
1005 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE,
1006 * Worker for nemR3WinHandleMemoryAccess; pvUser points to a
1007 * NEMHCWINHMACPCCSTATE structure. }
1008 */
1009NEM_TMPL_STATIC DECLCALLBACK(int)
1010nemHCWinHandleMemoryAccessPageCheckerCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1011{
1012 NEMHCWINHMACPCCSTATE *pState = (NEMHCWINHMACPCCSTATE *)pvUser;
1013 pState->fDidSomething = false;
1014 pState->fCanResume = false;
1015
1016 /* If A20 is disabled, we may need to make another query on the masked
1017 page to get the correct protection information. */
1018 uint8_t u2State = pInfo->u2NemState;
1019 RTGCPHYS GCPhysSrc;
1020 if ( pVM->nem.s.fA20Enabled
1021 || !NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
1022 GCPhysSrc = GCPhys;
1023 else
1024 {
1025 GCPhysSrc = GCPhys & ~(RTGCPHYS)RT_BIT_32(20);
1026 PGMPHYSNEMPAGEINFO Info2;
1027 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhysSrc, pState->fWriteAccess, &Info2, NULL, NULL);
1028 AssertRCReturn(rc, rc);
1029
1030 *pInfo = Info2;
1031 pInfo->u2NemState = u2State;
1032 }
1033
1034 /*
1035 * Consolidate current page state with actual page protection and access type.
1036 * We don't really consider downgrades here, as they shouldn't happen.
1037 */
1038#ifndef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1039 /** @todo Someone at microsoft please explain:
1040 * I'm not sure WTF was going on, but I ended up in a loop if I remapped a
1041 * readonly page as writable (unmap, then map again). Specifically, this was an
1042 * issue with the big VRAM mapping at 0xe0000000 when booing DSL 4.4.1. So, in
1043 * a hope to work around that we no longer pre-map anything, just unmap stuff
1044 * and do it lazily here. And here we will first unmap, restart, and then remap
1045 * with new protection or backing.
1046 */
1047#endif
1048 int rc;
1049 switch (u2State)
1050 {
1051 case NEM_WIN_PAGE_STATE_UNMAPPED:
1052 case NEM_WIN_PAGE_STATE_NOT_SET:
1053 if (pInfo->fNemProt == NEM_PAGE_PROT_NONE)
1054 {
1055 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1\n", GCPhys));
1056 return VINF_SUCCESS;
1057 }
1058
1059 /* Don't bother remapping it if it's a write request to a non-writable page. */
1060 if ( pState->fWriteAccess
1061 && !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE))
1062 {
1063 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1w\n", GCPhys));
1064 return VINF_SUCCESS;
1065 }
1066
1067 /* Map the page. */
1068 rc = nemHCNativeSetPhysPage(pVM,
1069 pVCpu,
1070 GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1071 GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1072 pInfo->fNemProt,
1073 &u2State,
1074 true /*fBackingState*/);
1075 pInfo->u2NemState = u2State;
1076 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - synced => %s + %Rrc\n",
1077 GCPhys, g_apszPageStates[u2State], rc));
1078 pState->fDidSomething = true;
1079 pState->fCanResume = true;
1080 return rc;
1081
1082 case NEM_WIN_PAGE_STATE_READABLE:
1083 if ( !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1084 && (pInfo->fNemProt & (NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE)))
1085 {
1086 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #2\n", GCPhys));
1087 return VINF_SUCCESS;
1088 }
1089
1090#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1091 /* Upgrade page to writable. */
1092/** @todo test this*/
1093 if ( (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1094 && pState->fWriteAccess)
1095 {
1096 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhys,
1097 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
1098 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1099 AssertRC(rc);
1100 if (RT_SUCCESS(rc))
1101 {
1102 pInfo->u2NemState = NEM_WIN_PAGE_STATE_WRITABLE;
1103 pState->fDidSomething = true;
1104 pState->fCanResume = true;
1105 Log5(("NEM GPA write-upgrade/exit: %RGp (was %s, cMappedPages=%u)\n",
1106 GCPhys, g_apszPageStates[u2State], pVM->nem.s.cMappedPages));
1107 }
1108 }
1109 else
1110 {
1111 /* Need to emulate the acces. */
1112 AssertBreak(pInfo->fNemProt != NEM_PAGE_PROT_NONE); /* There should be no downgrades. */
1113 rc = VINF_SUCCESS;
1114 }
1115 return rc;
1116#else
1117 break;
1118#endif
1119
1120 case NEM_WIN_PAGE_STATE_WRITABLE:
1121 if (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1122 {
1123 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #3\n", GCPhys));
1124 return VINF_SUCCESS;
1125 }
1126#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1127 AssertFailed(); /* There should be no downgrades. */
1128#endif
1129 break;
1130
1131 default:
1132 AssertLogRelMsgFailedReturn(("u2State=%#x\n", u2State), VERR_INTERNAL_ERROR_3);
1133 }
1134
1135 /*
1136 * Unmap and restart the instruction.
1137 * If this fails, which it does every so often, just unmap everything for now.
1138 */
1139#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1140 rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
1141 AssertRC(rc);
1142 if (RT_SUCCESS(rc))
1143#else
1144 /** @todo figure out whether we mess up the state or if it's WHv. */
1145 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
1146 if (SUCCEEDED(hrc))
1147#endif
1148 {
1149 pState->fDidSomething = true;
1150 pState->fCanResume = true;
1151 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1152 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1153 Log5(("NEM GPA unmapped/exit: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[u2State], cMappedPages));
1154 return VINF_SUCCESS;
1155 }
1156#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1157 LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhys, rc));
1158 return rc;
1159#else
1160 LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp %s hrc=%Rhrc (%#x) Last=%#x/%u (cMappedPages=%u)\n",
1161 GCPhys, g_apszPageStates[u2State], hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue(),
1162 pVM->nem.s.cMappedPages));
1163
1164 PGMPhysNemEnumPagesByState(pVM, pVCpu, NEM_WIN_PAGE_STATE_READABLE, nemR3WinUnmapOnePageCallback, NULL);
1165 Log(("nemHCWinHandleMemoryAccessPageCheckerCallback: Unmapped all (cMappedPages=%u)\n", pVM->nem.s.cMappedPages));
1166
1167 pState->fDidSomething = true;
1168 pState->fCanResume = true;
1169 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1170 return VINF_SUCCESS;
1171#endif
1172}
1173
1174#ifdef IN_RING3
1175
1176/**
1177 * Copies register state from the X64 intercept message header.
1178 *
1179 * ASSUMES no state copied yet.
1180 *
1181 * @param pCtx The registe rcontext.
1182 * @param pHdr The X64 intercept message header.
1183 */
1184DECLINLINE(void) nemHCWinCopyStateFromX64Header(PCPUMCTX pCtx, HV_X64_INTERCEPT_MESSAGE_HEADER const *pHdr)
1185{
1186 Assert( (pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS))
1187 == (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS));
1188 NEM_WIN_COPY_BACK_SEG(pCtx->cs, pHdr->CsSegment);
1189 pCtx->rip = pHdr->Rip;
1190 pCtx->rflags.u = pHdr->Rflags;
1191 pCtx->fExtrn &= ~(CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1192}
1193
1194
1195/**
1196 * Deals with memory intercept message.
1197 *
1198 * @returns Strict VBox status code.
1199 * @param pVM The cross context VM structure.
1200 * @param pVCpu The cross context per CPU structure.
1201 * @param pMsg The message.
1202 * @param pCtx The register context.
1203 */
1204NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageMemory(PVM pVM, PVMCPU pVCpu, HV_X64_MEMORY_INTERCEPT_MESSAGE const *pMsg,
1205 PCPUMCTX pCtx)
1206{
1207 /*
1208 * Whatever we do, we must clear pending event ejection upon resume.
1209 */
1210 if (pMsg->Header.ExecutionState.InterruptionPending)
1211 pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_MASK;
1212
1213 /*
1214 * Ask PGM for information about the given GCPhys. We need to check if we're
1215 * out of sync first.
1216 */
1217 NEMHCWINHMACPCCSTATE State = { pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE, false, false };
1218 PGMPHYSNEMPAGEINFO Info;
1219 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, pMsg->GuestPhysicalAddress, State.fWriteAccess, &Info,
1220 nemHCWinHandleMemoryAccessPageCheckerCallback, &State);
1221 if (RT_SUCCESS(rc))
1222 {
1223 if (Info.fNemProt & ( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE
1224 ? NEM_PAGE_PROT_WRITE : NEM_PAGE_PROT_READ))
1225 {
1226 if (State.fCanResume)
1227 {
1228 Log4(("MemExit: %RGp (=>%RHp) %s fProt=%u%s%s%s; restarting (%s)\n",
1229 pMsg->GuestPhysicalAddress, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1230 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1231 State.fDidSomething ? "" : " no-change", g_apszWHvMemAccesstypes[pMsg->Header.InterceptAccessType]));
1232 return VINF_SUCCESS;
1233 }
1234 }
1235 Log4(("MemExit: %RGp (=>%RHp) %s fProt=%u%s%s%s; emulating (%s)\n",
1236 pMsg->GuestPhysicalAddress, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1237 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1238 State.fDidSomething ? "" : " no-change", g_apszWHvMemAccesstypes[pMsg->Header.InterceptAccessType]));
1239 }
1240 else
1241 Log4(("MemExit: %RGp rc=%Rrc%s; emulating (%s)\n", pMsg->GuestPhysicalAddress, rc,
1242 State.fDidSomething ? " modified-backing" : "", g_apszWHvMemAccesstypes[pMsg->Header.InterceptAccessType]));
1243
1244 /*
1245 * Emulate the memory access, either access handler or special memory.
1246 */
1247 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1248 rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1249 AssertRCReturn(rc, rc);
1250
1251 VBOXSTRICTRC rcStrict;
1252 if (pMsg->InstructionByteCount > 0)
1253 rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(pCtx), pMsg->Header.Rip,
1254 pMsg->InstructionBytes, pMsg->InstructionByteCount);
1255 else
1256 rcStrict = IEMExecOne(pVCpu);
1257 /** @todo do we need to do anything wrt debugging here? */
1258 return rcStrict;
1259
1260}
1261
1262
1263/**
1264 * Deals with I/O port intercept message.
1265 *
1266 * @returns Strict VBox status code.
1267 * @param pVM The cross context VM structure.
1268 * @param pVCpu The cross context per CPU structure.
1269 * @param pMsg The message.
1270 */
1271NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageIoPort(PVM pVM, PVMCPU pVCpu, HV_X64_IO_PORT_INTERCEPT_MESSAGE const *pMsg,
1272 PCPUMCTX pCtx)
1273{
1274 Assert( pMsg->AccessInfo.AccessSize == 1
1275 || pMsg->AccessInfo.AccessSize == 2
1276 || pMsg->AccessInfo.AccessSize == 4);
1277
1278 /*
1279 * Whatever we do, we must clear pending event ejection upon resume.
1280 */
1281 if (pMsg->Header.ExecutionState.InterruptionPending)
1282 pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_MASK;
1283
1284 VBOXSTRICTRC rcStrict;
1285 if (!pMsg->AccessInfo.StringOp)
1286 {
1287 /*
1288 * Simple port I/O.
1289 */
1290 static uint32_t const s_fAndMask[8] =
1291 { UINT32_MAX, UINT32_C(0xff), UINT32_C(0xffff), UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX };
1292 uint32_t const fAndMask = s_fAndMask[pMsg->AccessInfo.AccessSize];
1293 if (pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE)
1294 {
1295 rcStrict = IOMIOPortWrite(pVM, pVCpu, pMsg->PortNumber, (uint32_t)pMsg->Rax & fAndMask, pMsg->AccessInfo.AccessSize);
1296 Log4(("IOExit: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n", pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1297 pMsg->PortNumber, (uint32_t)pMsg->Rax & fAndMask, pMsg->AccessInfo.AccessSize, VBOXSTRICTRC_VAL(rcStrict) ));
1298 if (IOM_SUCCESS(rcStrict))
1299 {
1300 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1301 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1302 }
1303 }
1304 else
1305 {
1306 uint32_t uValue = 0;
1307 rcStrict = IOMIOPortRead(pVM, pVCpu, pMsg->PortNumber, &uValue, pMsg->AccessInfo.AccessSize);
1308 Log4(("IOExit: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n", pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1309 pMsg->PortNumber, pMsg->AccessInfo.AccessSize, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1310 if (IOM_SUCCESS(rcStrict))
1311 {
1312 if (pMsg->AccessInfo.AccessSize != 4)
1313 pCtx->rax = (pMsg->Rax & ~(uint64_t)fAndMask) | (uValue & fAndMask);
1314 else
1315 pCtx->rax = uValue;
1316 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RAX;
1317 Log4(("IOExit: RAX %#RX64 -> %#RX64\n", pMsg->Rax, pCtx->rax));
1318 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1319 nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
1320 }
1321 }
1322 }
1323 else
1324 {
1325 /*
1326 * String port I/O.
1327 */
1328 /** @todo Someone at Microsoft please explain how we can get the address mode
1329 * from the IoPortAccess.VpContext. CS.Attributes is only sufficient for
1330 * getting the default mode, it can always be overridden by a prefix. This
1331 * forces us to interpret the instruction from opcodes, which is suboptimal.
1332 * Both AMD-V and VT-x includes the address size in the exit info, at least on
1333 * CPUs that are reasonably new.
1334 *
1335 * Of course, it's possible this is an undocumented and we just need to do some
1336 * experiments to figure out how it's communicated. Alternatively, we can scan
1337 * the opcode bytes for possible evil prefixes.
1338 */
1339 nemHCWinCopyStateFromX64Header(pCtx, &pMsg->Header);
1340 pCtx->fExtrn &= ~( CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDI | CPUMCTX_EXTRN_RSI
1341 | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES);
1342 NEM_WIN_COPY_BACK_SEG(pCtx->ds, pMsg->DsSegment);
1343 NEM_WIN_COPY_BACK_SEG(pCtx->es, pMsg->EsSegment);
1344 pCtx->rax = pMsg->Rax;
1345 pCtx->rcx = pMsg->Rcx;
1346 pCtx->rdi = pMsg->Rdi;
1347 pCtx->rsi = pMsg->Rsi;
1348 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1349 AssertRCReturn(rc, rc);
1350
1351 Log4(("IOExit: %04x:%08RX64: %s%s %#x LB %u (emulating)\n", pMsg->Header.CsSegment.Selector, pMsg->Header.Rip,
1352 pMsg->AccessInfo.RepPrefix ? "REP " : "",
1353 pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE ? "OUTS" : "INS",
1354 pMsg->PortNumber, pMsg->AccessInfo.AccessSize ));
1355 rcStrict = IEMExecOne(pVCpu);
1356 }
1357 if (IOM_SUCCESS(rcStrict))
1358 {
1359 /*
1360 * Do debug checks.
1361 */
1362 if ( pMsg->Header.ExecutionState.DebugActive /** @todo Microsoft: Does DebugActive this only reflext DR7? */
1363 || (pMsg->Header.Rflags & X86_EFL_TF)
1364 || DBGFBpIsHwIoArmed(pVM) )
1365 {
1366 /** @todo Debugging. */
1367 }
1368 }
1369 return rcStrict;
1370}
1371
1372
1373/**
1374 * Handles messages (VM exits).
1375 *
1376 * @returns Strict VBox status code.
1377 * @param pVM The cross context VM structure.
1378 * @param pVCpu The cross context per CPU structure.
1379 * @param pMappingHeader The message slot mapping.
1380 * @param pCtx The register context.
1381 */
1382NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessage(PVM pVM, PVMCPU pVCpu, VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader,
1383 PCPUMCTX pCtx)
1384{
1385 if (pMappingHeader->enmVidMsgType == VidMessageHypervisorMessage)
1386 {
1387 AssertMsg(pMappingHeader->cbMessage == HV_MESSAGE_SIZE, ("%#x\n", pMappingHeader->cbMessage));
1388 HV_MESSAGE const *pMsg = (HV_MESSAGE const *)(pMappingHeader + 1);
1389 switch (pMsg->Header.MessageType)
1390 {
1391 case HvMessageTypeUnmappedGpa:
1392 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment));
1393 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept, pCtx);
1394
1395 case HvMessageTypeGpaIntercept:
1396 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment));
1397 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept, pCtx);
1398
1399 case HvMessageTypeX64IoPortIntercept:
1400 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64IoPortIntercept));
1401 return nemHCWinHandleMessageIoPort(pVM, pVCpu, &pMsg->X64IoPortIntercept, pCtx);
1402
1403 case HvMessageTypeX64Halt:
1404 return VINF_EM_HALT;
1405
1406 case HvMessageTypeX64InterruptWindow:
1407 AssertLogRelMsgFailedReturn(("Message type %#x not implemented!\n", pMsg->Header.MessageType),
1408 VERR_INTERNAL_ERROR_2);
1409
1410 case HvMessageTypeInvalidVpRegisterValue:
1411 case HvMessageTypeUnrecoverableException:
1412 case HvMessageTypeUnsupportedFeature:
1413 case HvMessageTypeTlbPageSizeMismatch:
1414 AssertLogRelMsgFailedReturn(("Message type %#x not implemented!\n", pMsg->Header.MessageType),
1415 VERR_INTERNAL_ERROR_2);
1416
1417 case HvMessageTypeX64MsrIntercept:
1418 case HvMessageTypeX64CpuidIntercept:
1419 case HvMessageTypeX64ExceptionIntercept:
1420 case HvMessageTypeX64ApicEoi:
1421 case HvMessageTypeX64LegacyFpError:
1422 case HvMessageTypeX64RegisterIntercept:
1423 case HvMessageTypeApicEoi:
1424 case HvMessageTypeFerrAsserted:
1425 case HvMessageTypeEventLogBufferComplete:
1426 case HvMessageTimerExpired:
1427 AssertLogRelMsgFailedReturn(("Unexpected message on CPU #%u: #x\n", pVCpu->idCpu, pMsg->Header.MessageType),
1428 VERR_INTERNAL_ERROR_2);
1429
1430 default:
1431 AssertLogRelMsgFailedReturn(("Unknown message on CPU #%u: #x\n", pVCpu->idCpu, pMsg->Header.MessageType),
1432 VERR_INTERNAL_ERROR_2);
1433 }
1434 }
1435 else
1436 AssertLogRelMsgFailedReturn(("Unexpected VID message type on CPU #%u: %#x LB %u\n",
1437 pVCpu->idCpu, pMappingHeader->enmVidMsgType, pMappingHeader->cbMessage),
1438 VERR_INTERNAL_ERROR_3);
1439}
1440
1441
1442/**
1443 * Worker for nemHCWinRunGC that stops the execution on the way out.
1444 *
1445 * The CPU was running the last time we checked, no there are no messages that
1446 * needs being marked handled/whatever. Caller checks this.
1447 *
1448 * @returns rcStrict on success, error status on failure.
1449 * @param pVM The cross context VM structure.
1450 * @param pVCpu The cross context per CPU structure.
1451 * @param rcStrict The nemHCWinRunGC return status. This is a little
1452 * bit unnecessary, except in internal error cases,
1453 * since we won't need to stop the CPU if we took an
1454 * exit.
1455 * @param pMappingHeader The message slot mapping.
1456 */
1457NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinStopCpu(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rcStrict,
1458 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader)
1459{
1460 /*
1461 * Try stopping the processor. If we're lucky we manage to do this before it
1462 * does another VM exit.
1463 */
1464 BOOL fRet = VidStopVirtualProcessor(pVM->nem.s.hPartitionDevice, pVCpu->idCpu);
1465 if (fRet)
1466 {
1467 Log8(("nemHCWinStopCpu: Stopping CPU succeeded (cpu status %u)\n", nemHCWinCpuGetRunningStatus(pVCpu) ));
1468 return rcStrict;
1469 }
1470
1471 /*
1472 * Dang. The CPU stopped by itself and we got a couple of message to deal with.
1473 */
1474 DWORD dwErr = RTNtLastErrorValue();
1475 AssertLogRelMsgReturn(dwErr == ERROR_VID_STOP_PENDING, ("dwErr=%#u\n", dwErr),
1476 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1477 Log8(("nemHCWinStopCpu: Stopping CPU pending...\n"));
1478
1479 /*
1480 * First message: Exit or similar.
1481 * Note! We can safely ASSUME that rcStrict isn't an important information one.
1482 */
1483 BOOL fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1484 VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/);
1485 AssertLogRelMsgReturn(fWait,
1486 ("1st VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1487 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1488
1489 /* It should be a hypervisor message and definitely not a stop request completed message. */
1490 VID_MESSAGE_TYPE enmVidMsgType = pMappingHeader->enmVidMsgType;
1491 AssertLogRelMsgReturn(enmVidMsgType != VidMessageStopRequestComplete,
1492 ("Unexpected 1st message following ERROR_VID_STOP_PENDING: %#x LB %#x\n",
1493 enmVidMsgType, pMappingHeader->cbMessage),
1494 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1495
1496 VBOXSTRICTRC rcStrict2 = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader, CPUMQueryGuestCtxPtr(pVCpu));
1497 if (rcStrict2 != VINF_SUCCESS && RT_SUCCESS(rcStrict))
1498 rcStrict = rcStrict2;
1499
1500 /*
1501 * Mark it as handled and get the stop request completed message, then mark
1502 * that as handled too. CPU is back into fully stopped stated then.
1503 */
1504 fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1505 VID_MSHAGN_F_HANDLE_MESSAGE | VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/);
1506 AssertLogRelMsgReturn(fWait,
1507 ("2nd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1508 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1509
1510 /* It should be a stop request completed message. */
1511 enmVidMsgType = pMappingHeader->enmVidMsgType;
1512 AssertLogRelMsgReturn(enmVidMsgType == VidMessageStopRequestComplete,
1513 ("Unexpected 2nd message following ERROR_VID_STOP_PENDING: %#x LB %#x\n",
1514 enmVidMsgType, pMappingHeader->cbMessage),
1515 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1516
1517 /* Mark this as handled. */
1518 fWait = g_pfnVidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1519 VID_MSHAGN_F_HANDLE_MESSAGE, 30000 /*ms*/);
1520 AssertLogRelMsgReturn(fWait,
1521 ("3rd VidMessageSlotHandleAndGetNext after ERROR_VID_STOP_PENDING failed: %u\n", RTNtLastErrorValue()),
1522 RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR_3 : rcStrict);
1523 Log8(("nemHCWinStopCpu: Stopped the CPU (rcStrict=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict) ));
1524 return rcStrict;
1525}
1526
1527
1528NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinRunGC(PVM pVM, PVMCPU pVCpu)
1529{
1530 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1531 LogFlow(("nemHCWinRunGC: Entering #%u cs:rip=%04x:%08RX64 efl=%#08RX64\n", pVCpu->idCpu, pCtx->cs.Sel, pCtx->rip, pCtx->rflags));
1532#ifdef LOG_ENABLED
1533 if (LogIs3Enabled())
1534 nemHCWinLogState(pVM, pVCpu);
1535#endif
1536
1537 /*
1538 * The run loop.
1539 *
1540 * Current approach to state updating to use the sledgehammer and sync
1541 * everything every time. This will be optimized later.
1542 */
1543 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader = (VID_MESSAGE_MAPPING_HEADER volatile *)pVCpu->nem.s.pvMsgSlotMapping;
1544 uint32_t cMillies = 5000; /** @todo lower this later... */
1545 const bool fSingleStepping = false; /** @todo get this from somewhere. */
1546 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1547 for (unsigned iLoop = 0;;iLoop++)
1548 {
1549 /*
1550 * Ensure that hyper-V has the whole state.
1551 */
1552 if ((pCtx->fExtrn & (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK)) != (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK))
1553 {
1554 int rc2 = nemHCWinCopyStateToHyperV(pVM, pVCpu, pCtx);
1555 AssertRCReturn(rc2, rc2);
1556 }
1557
1558 /*
1559 * Run a bit.
1560 */
1561 if ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
1562 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
1563 {
1564 if (pVCpu->nem.s.fHandleAndGetFlags)
1565 { /* Very likely that the CPU does NOT need starting (pending msg, running). */ }
1566 else
1567 {
1568 if (g_pfnVidStartVirtualProcessor(pVM->nem.s.hPartitionDevice, pVCpu->idCpu))
1569 pVCpu->nem.s.fHandleAndGetFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE;
1570 else
1571 AssertLogRelMsgFailedReturn(("VidStartVirtualProcessor failed for CPU #%u: %u (%#x, rcNt=%#x)\n",
1572 pVCpu->idCpu, RTNtLastErrorValue(), RTNtLastErrorValue(), RTNtLastStatusValue()),
1573 VERR_INTERNAL_ERROR_3);
1574 }
1575
1576 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
1577 {
1578 BOOL fRet = VidMessageSlotHandleAndGetNext(pVM->nem.s.hPartitionDevice, pVCpu->idCpu,
1579 pVCpu->nem.s.fHandleAndGetFlags, cMillies);
1580 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM);
1581 if (fRet)
1582 {
1583 /*
1584 * Deal with the message.
1585 */
1586 rcStrict = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader, pCtx);
1587 pVCpu->nem.s.fHandleAndGetFlags |= VID_MSHAGN_F_HANDLE_MESSAGE;
1588 }
1589 else
1590 {
1591 /* VID.SYS merges STATUS_ALERTED and STATUS_USER_APC into STATUS_TIMEOUT,
1592 so after NtAlertThread we end up here with a STATUS_TIMEOUT. And yeah,
1593 the error code conversion is into WAIT_XXX, i.e. NT status codes. */
1594 DWORD dwErr = GetLastError();
1595 if ( dwErr == STATUS_TIMEOUT
1596 || dwErr == STATUS_ALERTED /* just in case */
1597 || dwErr == STATUS_USER_APC /* ditto */ )
1598 pVCpu->nem.s.fHandleAndGetFlags = VID_MSHAGN_F_GET_NEXT_MESSAGE; /* exits are likely */
1599 else
1600 AssertLogRelMsgFailedReturn(("VidMessageSlotHandleAndGetNext failed for CPU #%u: %u (%#x, rcNt=%#x)\n",
1601 pVCpu->idCpu, dwErr, dwErr, RTNtLastStatusValue()),
1602 VERR_INTERNAL_ERROR_3);
1603 }
1604
1605 /*
1606 * If no relevant FFs are pending, loop.
1607 */
1608 if ( !VM_FF_IS_PENDING( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
1609 && !VMCPU_FF_IS_PENDING(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
1610 continue;
1611
1612 /** @todo Try handle pending flags, not just return to EM loops. Take care
1613 * not to set important RCs here unless we've handled a message. */
1614 LogFlow(("nemHCWinRunGC: returning: pending FF (%#x / %#x)\n", pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions));
1615 }
1616 else
1617 LogFlow(("nemHCWinRunGC: returning: canceled %d (pre exec)\n", VMCPU_GET_STATE(pVCpu) ));
1618 }
1619 else
1620 LogFlow(("nemHCWinRunGC: returning: pending FF (pre exec)\n"));
1621 break;
1622 } /* the run loop */
1623
1624
1625 /*
1626 * If the CPU is running, make sure to stop it before we try sync back the
1627 * state and return to EM.
1628 */
1629 if (pVCpu->nem.s.fHandleAndGetFlags == VID_MSHAGN_F_GET_NEXT_MESSAGE)
1630 {
1631 pVCpu->nem.s.fHandleAndGetFlags = 0;
1632 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader);
1633 }
1634
1635 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
1636
1637 if (pCtx->fExtrn & (CPUMCTX_EXTRN_ALL | (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)))
1638 {
1639 int rc2 = nemHCWinCopyStateFromHyperV(pVM, pVCpu, pCtx, CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK);
1640 if (RT_SUCCESS(rc2))
1641 pCtx->fExtrn = 0;
1642 else if (RT_SUCCESS(rcStrict))
1643 rcStrict = rc2;
1644 }
1645 else
1646 pCtx->fExtrn = 0;
1647
1648 LogFlow(("nemHCWinRunGC: Leaving #%u cs:rip=%04x:%08RX64 efl=%#08RX64\n", pVCpu->idCpu, pCtx->cs.Sel, pCtx->rip, pCtx->rflags));
1649 return rcStrict;
1650}
1651#endif
1652
1653#endif /* IN_RING0 */
1654
1655
1656/**
1657 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE}
1658 */
1659NEM_TMPL_STATIC DECLCALLBACK(int) nemHCWinUnsetForA20CheckerCallback(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys,
1660 PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1661{
1662 /* We'll just unmap the memory. */
1663 if (pInfo->u2NemState > NEM_WIN_PAGE_STATE_UNMAPPED)
1664 {
1665#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1666 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhys);
1667 AssertRC(rc);
1668 if (RT_SUCCESS(rc))
1669#else
1670 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
1671 if (SUCCEEDED(hrc))
1672#endif
1673 {
1674 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1675 Log5(("NEM GPA unmapped/A20: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[pInfo->u2NemState], cMappedPages));
1676 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1677 }
1678 else
1679 {
1680#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1681 LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp rc=%Rrc\n", GCPhys, rc));
1682 return rc;
1683#else
1684 LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
1685 GCPhys, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
1686 return VERR_INTERNAL_ERROR_2;
1687#endif
1688 }
1689 }
1690 RT_NOREF(pVCpu, pvUser);
1691 return VINF_SUCCESS;
1692}
1693
1694
1695/**
1696 * Unmaps a page from Hyper-V for the purpose of emulating A20 gate behavior.
1697 *
1698 * @returns The PGMPhysNemQueryPageInfo result.
1699 * @param pVM The cross context VM structure.
1700 * @param pVCpu The cross context virtual CPU structure.
1701 * @param GCPhys The page to unmap.
1702 */
1703NEM_TMPL_STATIC int nemHCWinUnmapPageForA20Gate(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
1704{
1705 PGMPHYSNEMPAGEINFO Info;
1706 return PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhys, false /*fMakeWritable*/, &Info,
1707 nemHCWinUnsetForA20CheckerCallback, NULL);
1708}
1709
1710
1711void nemHCNativeNotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
1712{
1713 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
1714 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
1715}
1716
1717
1718void nemHCNativeNotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1719 int fRestoreAsRAM, bool fRestoreAsRAM2)
1720{
1721 Log5(("nemHCNativeNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d fRestoreAsRAM=%d fRestoreAsRAM2=%d\n",
1722 GCPhys, cb, enmKind, fRestoreAsRAM, fRestoreAsRAM2));
1723 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb); NOREF(fRestoreAsRAM); NOREF(fRestoreAsRAM2);
1724}
1725
1726
1727void nemHCNativeNotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
1728 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
1729{
1730 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
1731 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
1732 NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
1733}
1734
1735
1736/**
1737 * Worker that maps pages into Hyper-V.
1738 *
1739 * This is used by the PGM physical page notifications as well as the memory
1740 * access VMEXIT handlers.
1741 *
1742 * @returns VBox status code.
1743 * @param pVM The cross context VM structure.
1744 * @param pVCpu The cross context virtual CPU structure of the
1745 * calling EMT.
1746 * @param GCPhysSrc The source page address.
1747 * @param GCPhysDst The hyper-V destination page. This may differ from
1748 * GCPhysSrc when A20 is disabled.
1749 * @param fPageProt NEM_PAGE_PROT_XXX.
1750 * @param pu2State Our page state (input/output).
1751 * @param fBackingChanged Set if the page backing is being changed.
1752 * @thread EMT(pVCpu)
1753 */
1754NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
1755 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged)
1756{
1757#ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1758 /*
1759 * When using the hypercalls instead of the ring-3 APIs, we don't need to
1760 * unmap memory before modifying it. We still want to track the state though,
1761 * since unmap will fail when called an unmapped page and we don't want to redo
1762 * upgrades/downgrades.
1763 */
1764 uint8_t const u2OldState = *pu2State;
1765 int rc;
1766 if (fPageProt == NEM_PAGE_PROT_NONE)
1767 {
1768 if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
1769 {
1770 rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
1771 if (RT_SUCCESS(rc))
1772 {
1773 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
1774 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1775 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
1776 }
1777 else
1778 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1779 }
1780 else
1781 rc = VINF_SUCCESS;
1782 }
1783 else if (fPageProt & NEM_PAGE_PROT_WRITE)
1784 {
1785 if (u2OldState != NEM_WIN_PAGE_STATE_WRITABLE || fBackingChanged)
1786 {
1787 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
1788 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
1789 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1790 if (RT_SUCCESS(rc))
1791 {
1792 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
1793 uint32_t cMappedPages = u2OldState <= NEM_WIN_PAGE_STATE_UNMAPPED
1794 ? ASMAtomicIncU32(&pVM->nem.s.cMappedPages) : pVM->nem.s.cMappedPages;
1795 Log5(("NEM GPA writable/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
1796 NOREF(cMappedPages);
1797 }
1798 else
1799 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1800 }
1801 else
1802 rc = VINF_SUCCESS;
1803 }
1804 else
1805 {
1806 if (u2OldState != NEM_WIN_PAGE_STATE_READABLE || fBackingChanged)
1807 {
1808 rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
1809 HV_MAP_GPA_READABLE | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1810 if (RT_SUCCESS(rc))
1811 {
1812 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
1813 uint32_t cMappedPages = u2OldState <= NEM_WIN_PAGE_STATE_UNMAPPED
1814 ? ASMAtomicIncU32(&pVM->nem.s.cMappedPages) : pVM->nem.s.cMappedPages;
1815 Log5(("NEM GPA read+exec/set: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
1816 NOREF(cMappedPages);
1817 }
1818 else
1819 AssertLogRelMsgFailed(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1820 }
1821 else
1822 rc = VINF_SUCCESS;
1823 }
1824
1825 return VINF_SUCCESS;
1826
1827#else
1828 /*
1829 * Looks like we need to unmap a page before we can change the backing
1830 * or even modify the protection. This is going to be *REALLY* efficient.
1831 * PGM lends us two bits to keep track of the state here.
1832 */
1833 uint8_t const u2OldState = *pu2State;
1834 uint8_t const u2NewState = fPageProt & NEM_PAGE_PROT_WRITE ? NEM_WIN_PAGE_STATE_WRITABLE
1835 : fPageProt & NEM_PAGE_PROT_READ ? NEM_WIN_PAGE_STATE_READABLE : NEM_WIN_PAGE_STATE_UNMAPPED;
1836 if ( fBackingChanged
1837 || u2NewState != u2OldState)
1838 {
1839 if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
1840 {
1841# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1842 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
1843 AssertRC(rc);
1844 if (RT_SUCCESS(rc))
1845 {
1846 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
1847 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1848 if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
1849 {
1850 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
1851 GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
1852 return VINF_SUCCESS;
1853 }
1854 }
1855 else
1856 {
1857 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1858 return rc;
1859 }
1860# else
1861 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst, X86_PAGE_SIZE);
1862 if (SUCCEEDED(hrc))
1863 {
1864 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
1865 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1866 if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
1867 {
1868 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
1869 GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
1870 return VINF_SUCCESS;
1871 }
1872 }
1873 else
1874 {
1875 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
1876 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
1877 return VERR_NEM_INIT_FAILED;
1878 }
1879# endif
1880 }
1881 }
1882
1883 /*
1884 * Writeable mapping?
1885 */
1886 if (fPageProt & NEM_PAGE_PROT_WRITE)
1887 {
1888# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1889 int rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
1890 HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE
1891 | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1892 AssertRC(rc);
1893 if (RT_SUCCESS(rc))
1894 {
1895 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
1896 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1897 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
1898 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
1899 return VINF_SUCCESS;
1900 }
1901 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1902 return rc;
1903# else
1904 void *pvPage;
1905 int rc = nemR3NativeGCPhys2R3PtrWriteable(pVM, GCPhysSrc, &pvPage);
1906 if (RT_SUCCESS(rc))
1907 {
1908 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, pvPage, GCPhysDst, X86_PAGE_SIZE,
1909 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute | WHvMapGpaRangeFlagWrite);
1910 if (SUCCEEDED(hrc))
1911 {
1912 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
1913 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1914 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
1915 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
1916 return VINF_SUCCESS;
1917 }
1918 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
1919 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
1920 return VERR_NEM_INIT_FAILED;
1921 }
1922 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
1923 return rc;
1924# endif
1925 }
1926
1927 if (fPageProt & NEM_PAGE_PROT_READ)
1928 {
1929# ifdef NEM_WIN_USE_HYPERCALLS_FOR_PAGES
1930 int rc = nemHCWinHypercallMapPage(pVM, pVCpu, GCPhysSrc, GCPhysDst,
1931 HV_MAP_GPA_READABLE | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_EXECUTABLE_AGAIN);
1932 AssertRC(rc);
1933 if (RT_SUCCESS(rc))
1934 {
1935 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
1936 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1937 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
1938 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
1939 return VINF_SUCCESS;
1940 }
1941 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1942 return rc;
1943# else
1944 const void *pvPage;
1945 int rc = nemR3NativeGCPhys2R3PtrReadOnly(pVM, GCPhysSrc, &pvPage);
1946 if (RT_SUCCESS(rc))
1947 {
1948 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, (void *)pvPage, GCPhysDst, X86_PAGE_SIZE,
1949 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute);
1950 if (SUCCEEDED(hrc))
1951 {
1952 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
1953 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1954 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
1955 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
1956 return VINF_SUCCESS;
1957 }
1958 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
1959 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
1960 return VERR_NEM_INIT_FAILED;
1961 }
1962 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
1963 return rc;
1964# endif
1965 }
1966
1967 /* We already unmapped it above. */
1968 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
1969 return VINF_SUCCESS;
1970#endif /* !NEM_WIN_USE_HYPERCALLS_FOR_PAGES */
1971}
1972
1973
1974NEM_TMPL_STATIC int nemHCJustUnmapPageFromHyperV(PVM pVM, RTGCPHYS GCPhysDst, uint8_t *pu2State)
1975{
1976 if (*pu2State <= NEM_WIN_PAGE_STATE_UNMAPPED)
1977 {
1978 Log5(("nemHCJustUnmapPageFromHyperV: %RGp == unmapped\n", GCPhysDst));
1979 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
1980 return VINF_SUCCESS;
1981 }
1982
1983#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
1984 PVMCPU pVCpu = VMMGetCpu(pVM);
1985 int rc = nemHCWinHypercallUnmapPage(pVM, pVCpu, GCPhysDst);
1986 AssertRC(rc);
1987 if (RT_SUCCESS(rc))
1988 {
1989 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1990 Log5(("NEM GPA unmapped/just: %RGp (was %s, cMappedPages=%u)\n", GCPhysDst, g_apszPageStates[*pu2State], cMappedPages));
1991 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
1992 return VINF_SUCCESS;
1993 }
1994 LogRel(("nemHCJustUnmapPageFromHyperV/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
1995 return rc;
1996#else
1997 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, X86_PAGE_SIZE);
1998 if (SUCCEEDED(hrc))
1999 {
2000 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2001 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2002 Log5(("nemHCJustUnmapPageFromHyperV: %RGp => unmapped (total %u)\n", GCPhysDst, cMappedPages));
2003 return VINF_SUCCESS;
2004 }
2005 LogRel(("nemHCJustUnmapPageFromHyperV(%RGp): failed! hrc=%Rhrc (%#x) Last=%#x/%u\n",
2006 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2007 return VERR_INTERNAL_ERROR_3;
2008#endif
2009}
2010
2011
2012int nemHCNativeNotifyPhysPageAllocated(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2013 PGMPAGETYPE enmType, uint8_t *pu2State)
2014{
2015 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2016 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2017 RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
2018
2019 int rc;
2020#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2021 PVMCPU pVCpu = VMMGetCpu(pVM);
2022 if ( pVM->nem.s.fA20Enabled
2023 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2024 rc = nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2025 else
2026 {
2027 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2028 rc = nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2029 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys) && RT_SUCCESS(rc))
2030 rc = nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2031
2032 }
2033#else
2034 RT_NOREF_PV(fPageProt);
2035 if ( pVM->nem.s.fA20Enabled
2036 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2037 rc = nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2038 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2039 rc = nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2040 else
2041 rc = VINF_SUCCESS; /* ignore since we've got the alias page at this address. */
2042#endif
2043 return rc;
2044}
2045
2046
2047void nemHCNativeNotifyPhysPageProtChanged(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2048 PGMPAGETYPE enmType, uint8_t *pu2State)
2049{
2050 Log5(("nemHCNativeNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2051 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2052 RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
2053
2054#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2055 PVMCPU pVCpu = VMMGetCpu(pVM);
2056 if ( pVM->nem.s.fA20Enabled
2057 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2058 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, false /*fBackingChanged*/);
2059 else
2060 {
2061 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2062 nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2063 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2064 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, false /*fBackingChanged*/);
2065 }
2066#else
2067 RT_NOREF_PV(fPageProt);
2068 if ( pVM->nem.s.fA20Enabled
2069 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2070 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2071 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2072 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2073 /* else: ignore since we've got the alias page at this address. */
2074#endif
2075}
2076
2077
2078void nemHCNativeNotifyPhysPageChanged(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2079 uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2080{
2081 Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2082 GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2083 RT_NOREF_PV(HCPhysPrev); RT_NOREF_PV(HCPhysNew); RT_NOREF_PV(enmType);
2084
2085#if defined(NEM_WIN_USE_HYPERCALLS_FOR_PAGES) || defined(IN_RING0)
2086 PVMCPU pVCpu = VMMGetCpu(pVM);
2087 if ( pVM->nem.s.fA20Enabled
2088 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2089 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2090 else
2091 {
2092 /* To keep effort at a minimum, we unmap the HMA page alias and resync it lazily when needed. */
2093 nemHCWinUnmapPageForA20Gate(pVM, pVCpu, GCPhys | RT_BIT_32(20));
2094 if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2095 nemHCNativeSetPhysPage(pVM, pVCpu, GCPhys, GCPhys, fPageProt, pu2State, true /*fBackingChanged*/);
2096 }
2097#else
2098 RT_NOREF_PV(fPageProt);
2099 if ( pVM->nem.s.fA20Enabled
2100 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
2101 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2102 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
2103 nemR3JustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
2104 /* else: ignore since we've got the alias page at this address. */
2105#endif
2106}
2107
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