VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA.asm@ 105490

最後變更 在這個檔案從105490是 105490,由 vboxsync 提交於 8 月 前

VMM/IEM: Basic infrastructure to natively recompile SIMD floating point instructions, bugref:10652

SIMD floating point operation behavior depends on the guest MXCSR value which needs to be written to the
host's floating point control register (MXCSR on x86, FPCR on arm64 which needs conversion) and needs to be
restored to the host's value when the TB finished execution to avoid inconsistencies in case the guest
changes MXCSR. The ARM implementation does not conform to the x86 behavior because default NaN values have
the sign bit clear on arm64 while they are set on x86. There are rounding differences as well and earlier
ARMv8 revisions don't support the FPCR.FIZ and FPCR.AH features. Should still work out as long as the guest
doesn't try to do funny stuff.

  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 8.6 KB
 
1; $Id: IEMAllN8veHlpA.asm 105490 2024-07-24 14:49:29Z vboxsync $
2;; @file
3; IEM - Native Recompiler Assembly Helpers.
4;
5
6;
7; Copyright (C) 2023 Oracle and/or its affiliates.
8;
9; This file is part of VirtualBox base platform packages, as
10; available from https://www.alldomusa.eu.org.
11;
12; This program is free software; you can redistribute it and/or
13; modify it under the terms of the GNU General Public License
14; as published by the Free Software Foundation, in version 3 of the
15; License.
16;
17; This program is distributed in the hope that it will be useful, but
18; WITHOUT ANY WARRANTY; without even the implied warranty of
19; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20; General Public License for more details.
21;
22; You should have received a copy of the GNU General Public License
23; along with this program; if not, see <https://www.gnu.org/licenses>.
24;
25; SPDX-License-Identifier: GPL-3.0-only
26;
27
28;*********************************************************************************************************************************
29;* Header Files *
30;*********************************************************************************************************************************
31%define RT_ASM_WITH_SEH64_ALT ; yasm gets confused by alignment, so we cannot use RT_ASM_WITH_SEH64. sigh.
32%include "VBox/asmdefs.mac"
33
34%include "IEMInternal.mac"
35%include "IEMN8veRecompiler.mac"
36
37
38;*********************************************************************************************************************************
39;* External Symbols *
40;*********************************************************************************************************************************
41BEGINCODE
42extern NAME(iemThreadedFunc_BltIn_LogCpuStateWorker)
43extern NAME(iemNativeHlpCheckTlbLookup)
44
45
46BEGINCODE
47;;
48; This is the common prologue of a TB, saving all volatile registers
49; and creating the stack frame for saving temporary values.
50;
51; @param pVCpu (gcc:rdi, msc:rcx) The cross-context vCPU structure pointer.
52; @param pfnTbStart (gcc:rsi, msc:rdx) The TB instruction start pointer.
53;
54; @note This must match the epilogue code generated by iemNativeEmitEpilog()!
55;
56; Any changes here must also be reflected in the unwind code installed by
57; iemExecMemAllocatorInitAndRegisterUnwindInfoForChunk()!
58;
59ALIGNCODE(64) ; Make sure the whole prolog is within a single cache line.
60BEGINPROC iemNativeTbEntry
61 push rbp
62 SEH64_PUSH_xBP
63 mov rbp, rsp
64 SEH64_SET_FRAME_xBP 0
65 push rbx
66 SEH64_PUSH_GREG rbp
67%ifdef ASM_CALL64_MSC
68 mov IEMNATIVE_REG_FIXED_PVMCPU_ASM, rcx ; ASSUMES IEMNATIVE_REG_FIXED_PVMCPU_ASM is rbx
69 push rsi
70 SEH64_PUSH_GREG rsi
71 push rdi
72 SEH64_PUSH_GREG rdi
73%else
74 mov IEMNATIVE_REG_FIXED_PVMCPU_ASM, rdi ; ASSUMES IEMNATIVE_REG_FIXED_PVMCPU_ASM is rbx
75%endif
76 push r12
77 SEH64_PUSH_GREG r12
78 push r13
79 SEH64_PUSH_GREG r13
80 push r14
81 SEH64_PUSH_GREG r14
82 push r15
83 SEH64_PUSH_GREG r15
84%ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
85 %error "Port me - need to store RBP in IEMCPU::pvTbFramePointerR3; Create ASM version of IEMCPU in IEMInternalStruct.mac"
86%endif
87%define MY_STACK_ALLOC ( IEMNATIVE_FRAME_ALIGN_SIZE \
88 + IEMNATIVE_FRAME_VAR_SIZE \
89 + IEMNATIVE_FRAME_STACK_ARG_COUNT * 8 \
90 + IEMNATIVE_FRAME_SHADOW_ARG_COUNT * 8)
91 sub rsp, MY_STACK_ALLOC
92 SEH64_ALLOCATE_STACK MY_STACK_ALLOC
93
94SEH64_END_PROLOGUE
95
96 ; Jump to the TB code.
97%ifdef ASM_CALL64_MSC
98 jmp rdx
99%else
100 jmp rsi
101%endif
102ENDPROC iemNativeTbEntry
103
104
105;;
106; This does the epilogue of a TB, given the RBP for the frame and eax value to return.
107;
108; @param pFrame (gcc:rdi, msc:rcx) The frame pointer.
109; @param rc (gcc:esi, msc:edx) The return value.
110;
111; @note This doesn't really work for MSC since xmm6 thru xmm15 are non-volatile
112; and since we don't save them in the TB prolog we'll potentially return
113; with different values if any functions on the calling stack uses them
114; as they're unlikely to restore them till they return.
115;
116; For the GCC calling convention all xmm registers are volatile and the
117; only worry would be someone fiddling the control bits of MXCSR or FCW
118; without restoring them. This is highly unlikely, unless we're doing
119; it ourselves, I think.
120;
121ALIGNCODE(16)
122BEGINPROC iemNativeTbLongJmp
123%ifdef ASM_CALL64_MSC
124 mov rbp, rcx
125 mov eax, edx
126%else
127 mov rbp, rdi
128 mov eax, esi
129%endif
130 SEH64_PUSH_xBP ; non-sense, but whatever.
131SEH64_END_PROLOGUE
132
133 ;
134 ; This must exactly match what iemNativeEmitEpilog does.
135 ;
136%ifdef ASM_CALL64_MSC
137 lea rsp, [rbp - 5 * 8]
138%else
139 lea rsp, [rbp - 7 * 8]
140%endif
141 pop r15
142 pop r14
143 pop r13
144 pop r12
145%ifdef ASM_CALL64_MSC
146 pop rdi
147 pop rsi
148%endif
149 pop rbx
150 leave
151 ret
152ENDPROC iemNativeTbLongJmp
153
154
155
156;;
157; This is wrapper function that saves and restores all volatile registers
158; so the impact of inserting LogCpuState is minimal to the other TB code.
159;
160ALIGNCODE(64)
161BEGINPROC iemNativeHlpAsmSafeWrapLogCpuState
162 push xBP
163 SEH64_PUSH_xBP
164 mov xBP, xSP
165 SEH64_SET_FRAME_xBP 0
166SEH64_END_PROLOGUE
167
168 ;
169 ; Save all volatile registers.
170 ;
171 push xAX
172 push xCX
173 push xDX
174%ifdef RT_OS_WINDOWS
175 push xSI
176 push xDI
177%endif
178 push r8
179 push r9
180 push r10
181 push r11
182 sub rsp, 8+20h
183
184 ;
185 ; Call C function to do the actual work.
186 ;
187%ifdef RT_OS_WINDOWS
188 mov rcx, rbx ; IEMNATIVE_REG_FIXED_PVMCPU
189 mov rdx, [rbp + 10h] ; Just in case we decide to put something there.
190 xor r8, r8
191 xor r9, r9
192%else
193 mov rdi, rbx ; IEMNATIVE_REG_FIXED_PVMCPU
194 mov rsi, [rbp + 10h] ; Just in case we decide to put something there.
195 xor ecx, ecx
196 xor edx, edx
197%endif
198 call NAME(iemThreadedFunc_BltIn_LogCpuStateWorker)
199
200 ;
201 ; Restore volatile registers and return to the TB code.
202 ;
203 add rsp, 8+20h
204 pop r11
205 pop r10
206 pop r9
207 pop r8
208%ifdef RT_OS_WINDOWS
209 pop xDI
210 pop xSI
211%endif
212 pop xDX
213 pop xCX
214 pop xAX
215 leave
216 ret
217ENDPROC iemNativeHlpAsmSafeWrapLogCpuState
218
219
220;;
221; This is wrapper function that saves and restores all volatile registers
222; so the impact of inserting CheckTlbLookup is minimal to the other TB code.
223;
224ALIGNCODE(16)
225BEGINPROC iemNativeHlpAsmSafeWrapCheckTlbLookup
226 push xBP
227 SEH64_PUSH_xBP
228 mov xBP, xSP
229 SEH64_SET_FRAME_xBP 0
230SEH64_END_PROLOGUE
231
232 ;
233 ; Save all volatile registers.
234 ;
235 push xAX
236 push xCX
237 push xDX
238%ifdef RT_OS_WINDOWS
239 push xSI
240 push xDI
241%endif
242 push r8
243 push r9
244 push r10
245 push r11
246 sub rsp, 8+20h
247
248 ;
249 ; Call C function to do the actual work.
250 ;
251%ifdef RT_OS_WINDOWS
252 mov rcx, [rbp + 10h]
253 mov rdx, [rbp + 18h]
254 mov r8, [rbp + 20h]
255 mov r9, [rbp + 28h]
256%else
257 mov rdi, [rbp + 10h]
258 mov rsi, [rbp + 18h]
259 mov rcx, [rbp + 20h]
260 mov rdx, [rbp + 28h]
261%endif
262 call NAME(iemNativeHlpCheckTlbLookup)
263
264 ;
265 ; Restore volatile registers and return to the TB code.
266 ;
267 add rsp, 8+20h
268 pop r11
269 pop r10
270 pop r9
271 pop r8
272%ifdef RT_OS_WINDOWS
273 pop xDI
274 pop xSI
275%endif
276 pop xDX
277 pop xCX
278 pop xAX
279 leave
280 ret 20h
281ENDPROC iemNativeHlpAsmSafeWrapCheckTlbLookup
282
283
284;;
285; This is wrapper function that restores MXCSR when TB execution finished.
286;
287; @param uRegFpCtrl (gcc:rdi, msc:rcx) The MXCSR value to restore.
288;
289ALIGNCODE(16)
290BEGINPROC iemNativeFpCtrlRegRestore
291 sub xSP, 4
292%ifdef RT_OS_WINDOWS
293 mov [xSP], edx
294%else
295 mov [xSP], edi
296%endif
297
298 ldmxcsr [xSP]
299 add xSP, 4
300 ret
301ENDPROC iemNativeFpCtrlRegRestore
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