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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap3.cpp.h@ 100694

最後變更 在這個檔案從100694是 100607,由 vboxsync 提交於 20 月 前

VMM/IEM: Implement vperm2f128/vperm2i128 instruction emulations, bugref:9898
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
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1/* $Id: IEMAllInstructionsVexMap3.cpp.h 100607 2023-07-17 16:38:48Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstructionsThree0f3a.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.alldomusa.eu.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 3
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39 * - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40 *
41 * Takes function table for function w/o implicit state parameter.
42 *
43 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44 */
45FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 if (pVCpu->iem.s.uVexLength)
54 {
55 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
56 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
57 IEM_MC_BEGIN(4, 3);
58 IEM_MC_LOCAL(RTUINT256U, uDst);
59 IEM_MC_LOCAL(RTUINT256U, uSrc1);
60 IEM_MC_LOCAL(RTUINT256U, uSrc2);
61 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
62 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
63 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
64 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
65 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
66 IEM_MC_PREPARE_AVX_USAGE();
67 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
68 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
69 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
70 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
71 IEM_MC_ADVANCE_RIP_AND_FINISH();
72 IEM_MC_END();
73 }
74 else
75 {
76 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
77 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
78 IEM_MC_BEGIN(4, 0);
79 IEM_MC_ARG(PRTUINT128U, puDst, 0);
80 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
81 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
82 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
83 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
84 IEM_MC_PREPARE_AVX_USAGE();
85 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
86 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
87 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
88 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
89 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
90 IEM_MC_ADVANCE_RIP_AND_FINISH();
91 IEM_MC_END();
92 }
93 }
94 else
95 {
96 /*
97 * Register, memory.
98 */
99 if (pVCpu->iem.s.uVexLength)
100 {
101 IEM_MC_BEGIN(4, 4);
102 IEM_MC_LOCAL(RTUINT256U, uDst);
103 IEM_MC_LOCAL(RTUINT256U, uSrc1);
104 IEM_MC_LOCAL(RTUINT256U, uSrc2);
105 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
106 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
107 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
108 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
109
110 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
111 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
112 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
113 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
114 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
115 IEM_MC_PREPARE_AVX_USAGE();
116
117 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
118 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
119 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
120 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
121
122 IEM_MC_ADVANCE_RIP_AND_FINISH();
123 IEM_MC_END();
124 }
125 else
126 {
127 IEM_MC_BEGIN(4, 2);
128 IEM_MC_LOCAL(RTUINT128U, uSrc2);
129 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
130 IEM_MC_ARG(PRTUINT128U, puDst, 0);
131 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
132 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
133
134 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
135 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
136 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
137 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
138 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
139 IEM_MC_PREPARE_AVX_USAGE();
140
141 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
142 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
143 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
144 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
145 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
146
147 IEM_MC_ADVANCE_RIP_AND_FINISH();
148 IEM_MC_END();
149 }
150 }
151}
152
153
154/**
155 * Common worker for AVX instructions on the forms:
156 * - vblendps/d xmm0, xmm1, xmm2/mem128, imm8
157 * - vblendps/d ymm0, ymm1, ymm2/mem256, imm8
158 *
159 * Takes function table for function w/o implicit state parameter.
160 *
161 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
162 */
163FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
164{
165 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
166 if (IEM_IS_MODRM_REG_MODE(bRm))
167 {
168 /*
169 * Register, register.
170 */
171 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
172 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
173 if (pVCpu->iem.s.uVexLength)
174 {
175 IEM_MC_BEGIN(4, 3);
176 IEM_MC_LOCAL(RTUINT256U, uDst);
177 IEM_MC_LOCAL(RTUINT256U, uSrc1);
178 IEM_MC_LOCAL(RTUINT256U, uSrc2);
179 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
180 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
181 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
182 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
183 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
184 IEM_MC_PREPARE_AVX_USAGE();
185 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
186 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
187 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
188 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
189 IEM_MC_ADVANCE_RIP_AND_FINISH();
190 IEM_MC_END();
191 }
192 else
193 {
194 IEM_MC_BEGIN(4, 0);
195 IEM_MC_ARG(PRTUINT128U, puDst, 0);
196 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
197 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
198 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
199 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
200 IEM_MC_PREPARE_AVX_USAGE();
201 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
202 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
203 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
204 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
205 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
206 IEM_MC_ADVANCE_RIP_AND_FINISH();
207 IEM_MC_END();
208 }
209 }
210 else
211 {
212 /*
213 * Register, memory.
214 */
215 if (pVCpu->iem.s.uVexLength)
216 {
217 IEM_MC_BEGIN(4, 4);
218 IEM_MC_LOCAL(RTUINT256U, uDst);
219 IEM_MC_LOCAL(RTUINT256U, uSrc1);
220 IEM_MC_LOCAL(RTUINT256U, uSrc2);
221 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
222 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
223 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
224 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
225
226 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
227 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
228 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
229 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
230 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
231 IEM_MC_PREPARE_AVX_USAGE();
232
233 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
234 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
235 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
236 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
237
238 IEM_MC_ADVANCE_RIP_AND_FINISH();
239 IEM_MC_END();
240 }
241 else
242 {
243 IEM_MC_BEGIN(4, 2);
244 IEM_MC_LOCAL(RTUINT128U, uSrc2);
245 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
246 IEM_MC_ARG(PRTUINT128U, puDst, 0);
247 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
248 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
249
250 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
251 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
252 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
253 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
254 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
255 IEM_MC_PREPARE_AVX_USAGE();
256
257 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
258 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
259 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
260 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
261 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
262
263 IEM_MC_ADVANCE_RIP_AND_FINISH();
264 IEM_MC_END();
265 }
266 }
267}
268
269
270/** Opcode VEX.66.0F3A 0x00. */
271FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
272/** Opcode VEX.66.0F3A 0x01. */
273FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
274/** Opcode VEX.66.0F3A 0x02. */
275FNIEMOP_STUB(iemOp_vpblendd_Vx_Wx_Ib);
276/* Opcode VEX.66.0F3A 0x03 - invalid */
277/** Opcode VEX.66.0F3A 0x04. */
278FNIEMOP_STUB(iemOp_vpermilps_Vx_Wx_Ib);
279/** Opcode VEX.66.0F3A 0x05. */
280FNIEMOP_STUB(iemOp_vpermilpd_Vx_Wx_Ib);
281
282
283/** Opcode VEX.66.0F3A 0x06 (vex only) */
284FNIEMOP_DEF(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib)
285{
286 //IEMOP_MNEMONIC4(VEX_RVM, VPERM2F128, vperm2f128, Vqq, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, 0); /** @todo */
287
288 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
289 if (IEM_IS_MODRM_REG_MODE(bRm))
290 {
291 /*
292 * Register, register.
293 */
294 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
295 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
296 IEM_MC_BEGIN(4, 3);
297 IEM_MC_LOCAL(RTUINT256U, uDst);
298 IEM_MC_LOCAL(RTUINT256U, uSrc1);
299 IEM_MC_LOCAL(RTUINT256U, uSrc2);
300 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
301 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
302 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
303 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
304 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
305 IEM_MC_PREPARE_AVX_USAGE();
306 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
307 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
308 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
309 puDst, puSrc1, puSrc2, bImmArg);
310 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
311 IEM_MC_ADVANCE_RIP_AND_FINISH();
312 IEM_MC_END();
313 }
314 else
315 {
316 /*
317 * Register, memory.
318 */
319 IEM_MC_BEGIN(4, 2);
320 IEM_MC_LOCAL(RTUINT256U, uDst);
321 IEM_MC_LOCAL(RTUINT256U, uSrc1);
322 IEM_MC_LOCAL(RTUINT256U, uSrc2);
323 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
324 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
325 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
326 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
327
328 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
329 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
330 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
331 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
332 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
333 IEM_MC_PREPARE_AVX_USAGE();
334
335 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
336 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
337 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
338 puDst, puSrc1, puSrc2, bImmArg);
339 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
340
341 IEM_MC_ADVANCE_RIP_AND_FINISH();
342 IEM_MC_END();
343 }
344}
345
346
347/* Opcode VEX.66.0F3A 0x07 - invalid */
348/** Opcode VEX.66.0F3A 0x08. */
349FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
350/** Opcode VEX.66.0F3A 0x09. */
351FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
352/** Opcode VEX.66.0F3A 0x0a. */
353FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
354/** Opcode VEX.66.0F3A 0x0b. */
355FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
356
357
358/** Opcode VEX.66.0F3A 0x0c.
359 * AVX,AVX */
360FNIEMOP_DEF(iemOp_vblendps_Vx_Hx_Wx_Ib)
361{
362 IEMOP_MNEMONIC3(VEX_RVM, VBLENDPS, vblendps, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
363 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendps);
364 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
365}
366
367
368/** Opcode VEX.66.0F3A 0x0d.
369 * AVX,AVX */
370FNIEMOP_DEF(iemOp_vblendpd_Vx_Hx_Wx_Ib)
371{
372 IEMOP_MNEMONIC3(VEX_RVM, VBLENDPD, vblendpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
373 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendpd);
374 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
375}
376
377
378/** Opcode VEX.66.0F3A 0x0e.
379 * AVX,AVX2 */
380FNIEMOP_DEF(iemOp_vpblendw_Vx_Hx_Wx_Ib)
381{
382 IEMOP_MNEMONIC3(VEX_RVM, VPBLENDW, vpblendw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
383 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendw);
384 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
385}
386
387
388/** Opcode VEX.0F3A 0x0f - invalid. */
389
390
391/** Opcode VEX.66.0F3A 0x0f.
392 * AVX,AVX2 */
393FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
394{
395 IEMOP_MNEMONIC3(VEX_RVM, VPALIGNR, vpalignr, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
396 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
397 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
398}
399
400
401/* Opcode VEX.66.0F3A 0x10 - invalid */
402/* Opcode VEX.66.0F3A 0x11 - invalid */
403/* Opcode VEX.66.0F3A 0x12 - invalid */
404/* Opcode VEX.66.0F3A 0x13 - invalid */
405/** Opcode VEX.66.0F3A 0x14. */
406FNIEMOP_STUB(iemOp_vpextrb_RdMb_Vdq_Ib);
407/** Opcode VEX.66.0F3A 0x15. */
408FNIEMOP_STUB(iemOp_vpextrw_RdMw_Vdq_Ib);
409/** Opcode VEX.66.0F3A 0x16. */
410FNIEMOP_STUB(iemOp_vpextrd_q_RdMw_Vdq_Ib);
411/** Opcode VEX.66.0F3A 0x17. */
412FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
413
414
415/** Opcode VEX.66.0F3A 0x18 (vex only). */
416FNIEMOP_DEF(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib)
417{
418 //IEMOP_MNEMONIC4(VEX_RMI, VINSERTF128, vinsertf128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
419 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
420 if (IEM_IS_MODRM_REG_MODE(bRm))
421 {
422 /*
423 * Register, register.
424 */
425 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
426 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
427
428 IEM_MC_BEGIN(0, 1);
429 IEM_MC_LOCAL(RTUINT128U, uSrc);
430
431 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
432 IEM_MC_PREPARE_AVX_USAGE();
433
434 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
435 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
436 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
437
438 IEM_MC_ADVANCE_RIP_AND_FINISH();
439 IEM_MC_END();
440 }
441 else
442 {
443 /*
444 * Register, memory.
445 */
446 IEM_MC_BEGIN(0, 2);
447 IEM_MC_LOCAL(RTUINT128U, uSrc);
448 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
449
450 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
451 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
452 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
453 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
454 IEM_MC_PREPARE_AVX_USAGE();
455
456 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
457 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
458 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
459
460 IEM_MC_ADVANCE_RIP_AND_FINISH();
461 IEM_MC_END();
462 }
463}
464
465
466/** Opcode VEX.66.0F3A 0x19 (vex only). */
467FNIEMOP_STUB(iemOp_vextractf128_Wdq_Vqq_Ib);
468/* Opcode VEX.66.0F3A 0x1a - invalid */
469/* Opcode VEX.66.0F3A 0x1b - invalid */
470/* Opcode VEX.66.0F3A 0x1c - invalid */
471/** Opcode VEX.66.0F3A 0x1d (vex only). */
472FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
473/* Opcode VEX.66.0F3A 0x1e - invalid */
474/* Opcode VEX.66.0F3A 0x1f - invalid */
475
476
477/** Opcode VEX.66.0F3A 0x20. */
478FNIEMOP_STUB(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib);
479/** Opcode VEX.66.0F3A 0x21, */
480FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
481/** Opcode VEX.66.0F3A 0x22. */
482FNIEMOP_STUB(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib);
483/* Opcode VEX.66.0F3A 0x23 - invalid */
484/* Opcode VEX.66.0F3A 0x24 - invalid */
485/* Opcode VEX.66.0F3A 0x25 - invalid */
486/* Opcode VEX.66.0F3A 0x26 - invalid */
487/* Opcode VEX.66.0F3A 0x27 - invalid */
488/* Opcode VEX.66.0F3A 0x28 - invalid */
489/* Opcode VEX.66.0F3A 0x29 - invalid */
490/* Opcode VEX.66.0F3A 0x2a - invalid */
491/* Opcode VEX.66.0F3A 0x2b - invalid */
492/* Opcode VEX.66.0F3A 0x2c - invalid */
493/* Opcode VEX.66.0F3A 0x2d - invalid */
494/* Opcode VEX.66.0F3A 0x2e - invalid */
495/* Opcode VEX.66.0F3A 0x2f - invalid */
496
497
498/* Opcode VEX.66.0F3A 0x30 - invalid */
499/* Opcode VEX.66.0F3A 0x31 - invalid */
500/* Opcode VEX.66.0F3A 0x32 - invalid */
501/* Opcode VEX.66.0F3A 0x33 - invalid */
502/* Opcode VEX.66.0F3A 0x34 - invalid */
503/* Opcode VEX.66.0F3A 0x35 - invalid */
504/* Opcode VEX.66.0F3A 0x36 - invalid */
505/* Opcode VEX.66.0F3A 0x37 - invalid */
506
507
508/** Opcode VEX.66.0F3A 0x38 (vex only). */
509FNIEMOP_DEF(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib)
510{
511 //IEMOP_MNEMONIC4(VEX_RMI, VINSERTI128, vinserti128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
512 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
513 if (IEM_IS_MODRM_REG_MODE(bRm))
514 {
515 /*
516 * Register, register.
517 */
518 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
519 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
520
521 IEM_MC_BEGIN(0, 1);
522 IEM_MC_LOCAL(RTUINT128U, uSrc);
523
524 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
525 IEM_MC_PREPARE_AVX_USAGE();
526
527 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
528 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
529 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
530
531 IEM_MC_ADVANCE_RIP_AND_FINISH();
532 IEM_MC_END();
533 }
534 else
535 {
536 /*
537 * Register, memory.
538 */
539 IEM_MC_BEGIN(0, 2);
540 IEM_MC_LOCAL(RTUINT128U, uSrc);
541 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
542
543 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
544 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
545 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
546 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
547 IEM_MC_PREPARE_AVX_USAGE();
548
549 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
550 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
551 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
552
553 IEM_MC_ADVANCE_RIP_AND_FINISH();
554 IEM_MC_END();
555 }
556}
557
558
559/** Opcode VEX.66.0F3A 0x39 (vex only). */
560FNIEMOP_STUB(iemOp_vextracti128_Wdq_Vqq_Ib);
561/* Opcode VEX.66.0F3A 0x3a - invalid */
562/* Opcode VEX.66.0F3A 0x3b - invalid */
563/* Opcode VEX.66.0F3A 0x3c - invalid */
564/* Opcode VEX.66.0F3A 0x3d - invalid */
565/* Opcode VEX.66.0F3A 0x3e - invalid */
566/* Opcode VEX.66.0F3A 0x3f - invalid */
567
568
569/** Opcode VEX.66.0F3A 0x40. */
570FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
571/** Opcode VEX.66.0F3A 0x41, */
572FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
573/** Opcode VEX.66.0F3A 0x42. */
574FNIEMOP_STUB(iemOp_vmpsadbw_Vx_Hx_Wx_Ib);
575/* Opcode VEX.66.0F3A 0x43 - invalid */
576
577
578/** Opcode VEX.66.0F3A 0x44. */
579FNIEMOP_DEF(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib)
580{
581 //IEMOP_MNEMONIC3(VEX_RVM, VPCLMULQDQ, vpclmulqdq, Vdq, Hdq, Wdq, DISOPTYPE_HARMLESS, 0); /* @todo */
582
583 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
584 if (IEM_IS_MODRM_REG_MODE(bRm))
585 {
586 /*
587 * Register, register.
588 */
589 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
590 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
591 IEM_MC_BEGIN(4, 0);
592 IEM_MC_ARG(PRTUINT128U, puDst, 0);
593 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
594 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
595 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
596 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
597 IEM_MC_PREPARE_AVX_USAGE();
598 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
599 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
600 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
601 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
602 puDst, puSrc1, puSrc2, bImmArg);
603 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
604 IEM_MC_ADVANCE_RIP_AND_FINISH();
605 IEM_MC_END();
606 }
607 else
608 {
609 /*
610 * Register, memory.
611 */
612 IEM_MC_BEGIN(4, 2);
613 IEM_MC_LOCAL(RTUINT128U, uSrc2);
614 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
615 IEM_MC_ARG(PRTUINT128U, puDst, 0);
616 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
617 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
618
619 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
620 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
621 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
622 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
623 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
624 IEM_MC_PREPARE_AVX_USAGE();
625
626 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
627 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
628 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
629 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
630 puDst, puSrc1, puSrc2, bImmArg);
631 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
632
633 IEM_MC_ADVANCE_RIP_AND_FINISH();
634 IEM_MC_END();
635 }
636}
637
638
639/* Opcode VEX.66.0F3A 0x45 - invalid */
640
641
642/** Opcode VEX.66.0F3A 0x46 (vex only) */
643FNIEMOP_DEF(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib)
644{
645 //IEMOP_MNEMONIC4(VEX_RVM, VPERM2I128, vperm2i128, Vqq, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, 0); /** @todo */
646
647 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
648 if (IEM_IS_MODRM_REG_MODE(bRm))
649 {
650 /*
651 * Register, register.
652 */
653 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
654 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
655 IEM_MC_BEGIN(4, 3);
656 IEM_MC_LOCAL(RTUINT256U, uDst);
657 IEM_MC_LOCAL(RTUINT256U, uSrc1);
658 IEM_MC_LOCAL(RTUINT256U, uSrc2);
659 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
660 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
661 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
662 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
663 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
664 IEM_MC_PREPARE_AVX_USAGE();
665 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
666 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
667 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
668 puDst, puSrc1, puSrc2, bImmArg);
669 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
670 IEM_MC_ADVANCE_RIP_AND_FINISH();
671 IEM_MC_END();
672 }
673 else
674 {
675 /*
676 * Register, memory.
677 */
678 IEM_MC_BEGIN(4, 2);
679 IEM_MC_LOCAL(RTUINT256U, uDst);
680 IEM_MC_LOCAL(RTUINT256U, uSrc1);
681 IEM_MC_LOCAL(RTUINT256U, uSrc2);
682 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
683 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
684 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
685 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
686
687 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
688 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
689 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
690 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
691 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
692 IEM_MC_PREPARE_AVX_USAGE();
693
694 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
695 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
696 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
697 puDst, puSrc1, puSrc2, bImmArg);
698 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
699
700 IEM_MC_ADVANCE_RIP_AND_FINISH();
701 IEM_MC_END();
702 }
703}
704
705
706/* Opcode VEX.66.0F3A 0x47 - invalid */
707/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
708FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
709/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
710FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
711
712
713/**
714 * Common worker for AVX2 instructions on the forms:
715 * - vblendvps/d xmm0, xmm1, xmm2/mem128, xmm4
716 * - vblendvps/d ymm0, ymm1, ymm2/mem256, ymm4
717 *
718 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operations.
719 */
720FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
721{
722 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
723 if (IEM_IS_MODRM_REG_MODE(bRm))
724 {
725 /*
726 * Register, register.
727 */
728 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
729 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
730 if (pVCpu->iem.s.uVexLength)
731 {
732 IEM_MC_BEGIN(4, 4);
733 IEM_MC_LOCAL(RTUINT256U, uDst);
734 IEM_MC_LOCAL(RTUINT256U, uSrc1);
735 IEM_MC_LOCAL(RTUINT256U, uSrc2);
736 IEM_MC_LOCAL(RTUINT256U, uSrc3);
737 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
738 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
739 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
740 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
741 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
742 IEM_MC_PREPARE_AVX_USAGE();
743 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
744 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
745 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
746 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
747 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
748 IEM_MC_ADVANCE_RIP_AND_FINISH();
749 IEM_MC_END();
750 }
751 else
752 {
753 IEM_MC_BEGIN(4, 0);
754 IEM_MC_ARG(PRTUINT128U, puDst, 0);
755 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
756 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
757 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
758 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
759 IEM_MC_PREPARE_AVX_USAGE();
760 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
761 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
762 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
763 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
764 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
765 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
766 IEM_MC_ADVANCE_RIP_AND_FINISH();
767 IEM_MC_END();
768 }
769 }
770 else
771 {
772 /*
773 * Register, memory.
774 */
775 if (pVCpu->iem.s.uVexLength)
776 {
777 IEM_MC_BEGIN(4, 5);
778 IEM_MC_LOCAL(RTUINT256U, uDst);
779 IEM_MC_LOCAL(RTUINT256U, uSrc1);
780 IEM_MC_LOCAL(RTUINT256U, uSrc2);
781 IEM_MC_LOCAL(RTUINT256U, uSrc3);
782 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
783 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
784 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
785 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
786 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
787
788 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
789 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
790
791 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
792 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
793 IEM_MC_PREPARE_AVX_USAGE();
794
795 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
796 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
797 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
798 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
799 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
800 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
801
802 IEM_MC_ADVANCE_RIP_AND_FINISH();
803 IEM_MC_END();
804 }
805 else
806 {
807 IEM_MC_BEGIN(4, 2);
808 IEM_MC_LOCAL(RTUINT128U, uSrc2);
809 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
810 IEM_MC_ARG(PRTUINT128U, puDst, 0);
811 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
812 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
813 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
814
815 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
816 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
817
818 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
819 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
820 IEM_MC_PREPARE_AVX_USAGE();
821
822 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
823 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
824 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
825 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
826 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
827 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
828
829 IEM_MC_ADVANCE_RIP_AND_FINISH();
830 IEM_MC_END();
831 }
832 }
833}
834
835
836/** Opcode VEX.66.0F3A 0x4a (vex only).
837 * AVX, AVX */
838FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
839{
840 //IEMOP_MNEMONIC4(VEX_RVM, VBLENDVPS, vpblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
841 IEMOPBLENDOP_INIT_VARS(vblendvps);
842 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
843}
844
845
846/** Opcode VEX.66.0F3A 0x4b (vex only).
847 * AVX, AVX */
848FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
849{
850 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVPD, blendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
851 IEMOPBLENDOP_INIT_VARS(vblendvpd);
852 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
853}
854
855
856/**
857 * Common worker for AVX2 instructions on the forms:
858 * - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
859 * - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
860 *
861 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
862 */
863FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
864{
865 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
866 if (IEM_IS_MODRM_REG_MODE(bRm))
867 {
868 /*
869 * Register, register.
870 */
871 if (pVCpu->iem.s.uVexLength)
872 {
873 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
874
875 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
876 IEM_MC_BEGIN(4, 4);
877 IEM_MC_LOCAL(RTUINT256U, uDst);
878 IEM_MC_LOCAL(RTUINT256U, uSrc1);
879 IEM_MC_LOCAL(RTUINT256U, uSrc2);
880 IEM_MC_LOCAL(RTUINT256U, uSrc3);
881 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
882 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
883 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
884 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
885 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
886 IEM_MC_PREPARE_AVX_USAGE();
887 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
888 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
889 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
890 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
891 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
892 IEM_MC_ADVANCE_RIP_AND_FINISH();
893 IEM_MC_END();
894 }
895 else
896 {
897 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
898
899 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
900 IEM_MC_BEGIN(4, 0);
901 IEM_MC_ARG(PRTUINT128U, puDst, 0);
902 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
903 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
904 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
905 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
906 IEM_MC_PREPARE_AVX_USAGE();
907 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
908 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
909 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
910 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
911 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
912 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
913 IEM_MC_ADVANCE_RIP_AND_FINISH();
914 IEM_MC_END();
915 }
916 }
917 else
918 {
919 /*
920 * Register, memory.
921 */
922 if (pVCpu->iem.s.uVexLength)
923 {
924 IEM_MC_BEGIN(4, 5);
925 IEM_MC_LOCAL(RTUINT256U, uDst);
926 IEM_MC_LOCAL(RTUINT256U, uSrc1);
927 IEM_MC_LOCAL(RTUINT256U, uSrc2);
928 IEM_MC_LOCAL(RTUINT256U, uSrc3);
929 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
930 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
931 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
932 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
933 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
934
935 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
936 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
937
938 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
939 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
940 IEM_MC_PREPARE_AVX_USAGE();
941
942 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
943 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
944 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
945 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
946 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
947 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
948
949 IEM_MC_ADVANCE_RIP_AND_FINISH();
950 IEM_MC_END();
951 }
952 else
953 {
954 IEM_MC_BEGIN(4, 2);
955 IEM_MC_LOCAL(RTUINT128U, uSrc2);
956 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
957 IEM_MC_ARG(PRTUINT128U, puDst, 0);
958 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
959 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
960 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
961
962 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
963 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
964
965 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
966 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
967 IEM_MC_PREPARE_AVX_USAGE();
968
969 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
970 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
971 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
972 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
973 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
974 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
975
976 IEM_MC_ADVANCE_RIP_AND_FINISH();
977 IEM_MC_END();
978 }
979 }
980}
981
982
983/** Opcode VEX.66.0F3A 0x4c (vex only).
984 * AVX, AVX2 */
985FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
986{
987 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
988 IEMOPBLENDOP_INIT_VARS(vpblendvb);
989 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
990}
991
992
993/* Opcode VEX.66.0F3A 0x4d - invalid */
994/* Opcode VEX.66.0F3A 0x4e - invalid */
995/* Opcode VEX.66.0F3A 0x4f - invalid */
996
997
998/* Opcode VEX.66.0F3A 0x50 - invalid */
999/* Opcode VEX.66.0F3A 0x51 - invalid */
1000/* Opcode VEX.66.0F3A 0x52 - invalid */
1001/* Opcode VEX.66.0F3A 0x53 - invalid */
1002/* Opcode VEX.66.0F3A 0x54 - invalid */
1003/* Opcode VEX.66.0F3A 0x55 - invalid */
1004/* Opcode VEX.66.0F3A 0x56 - invalid */
1005/* Opcode VEX.66.0F3A 0x57 - invalid */
1006/* Opcode VEX.66.0F3A 0x58 - invalid */
1007/* Opcode VEX.66.0F3A 0x59 - invalid */
1008/* Opcode VEX.66.0F3A 0x5a - invalid */
1009/* Opcode VEX.66.0F3A 0x5b - invalid */
1010/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
1011FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
1012/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
1013FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
1014/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
1015FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
1016/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
1017FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
1018
1019
1020/** Opcode VEX.66.0F3A 0x60. */
1021FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
1022/** Opcode VEX.66.0F3A 0x61, */
1023FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
1024/** Opcode VEX.66.0F3A 0x62. */
1025FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
1026/** Opcode VEX.66.0F3A 0x63*/
1027FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
1028/* Opcode VEX.66.0F3A 0x64 - invalid */
1029/* Opcode VEX.66.0F3A 0x65 - invalid */
1030/* Opcode VEX.66.0F3A 0x66 - invalid */
1031/* Opcode VEX.66.0F3A 0x67 - invalid */
1032/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
1033FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
1034/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
1035FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
1036/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
1037FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
1038/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
1039FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
1040/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
1041FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
1042/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
1043FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
1044/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
1045FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
1046/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
1047FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
1048
1049/* Opcode VEX.66.0F3A 0x70 - invalid */
1050/* Opcode VEX.66.0F3A 0x71 - invalid */
1051/* Opcode VEX.66.0F3A 0x72 - invalid */
1052/* Opcode VEX.66.0F3A 0x73 - invalid */
1053/* Opcode VEX.66.0F3A 0x74 - invalid */
1054/* Opcode VEX.66.0F3A 0x75 - invalid */
1055/* Opcode VEX.66.0F3A 0x76 - invalid */
1056/* Opcode VEX.66.0F3A 0x77 - invalid */
1057/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
1058FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
1059/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
1060FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
1061/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
1062FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
1063/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
1064FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
1065/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
1066FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
1067/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
1068FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
1069/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
1070FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
1071/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
1072FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
1073
1074/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
1075
1076
1077/* Opcode 0x0f 0xc0 - invalid */
1078/* Opcode 0x0f 0xc1 - invalid */
1079/* Opcode 0x0f 0xc2 - invalid */
1080/* Opcode 0x0f 0xc3 - invalid */
1081/* Opcode 0x0f 0xc4 - invalid */
1082/* Opcode 0x0f 0xc5 - invalid */
1083/* Opcode 0x0f 0xc6 - invalid */
1084/* Opcode 0x0f 0xc7 - invalid */
1085/* Opcode 0x0f 0xc8 - invalid */
1086/* Opcode 0x0f 0xc9 - invalid */
1087/* Opcode 0x0f 0xca - invalid */
1088/* Opcode 0x0f 0xcb - invalid */
1089/* Opcode 0x0f 0xcc - invalid */
1090/* Opcode 0x0f 0xcd - invalid */
1091/* Opcode 0x0f 0xce - invalid */
1092/* Opcode 0x0f 0xcf - invalid */
1093
1094
1095/* Opcode VEX.66.0F3A 0xd0 - invalid */
1096/* Opcode VEX.66.0F3A 0xd1 - invalid */
1097/* Opcode VEX.66.0F3A 0xd2 - invalid */
1098/* Opcode VEX.66.0F3A 0xd3 - invalid */
1099/* Opcode VEX.66.0F3A 0xd4 - invalid */
1100/* Opcode VEX.66.0F3A 0xd5 - invalid */
1101/* Opcode VEX.66.0F3A 0xd6 - invalid */
1102/* Opcode VEX.66.0F3A 0xd7 - invalid */
1103/* Opcode VEX.66.0F3A 0xd8 - invalid */
1104/* Opcode VEX.66.0F3A 0xd9 - invalid */
1105/* Opcode VEX.66.0F3A 0xda - invalid */
1106/* Opcode VEX.66.0F3A 0xdb - invalid */
1107/* Opcode VEX.66.0F3A 0xdc - invalid */
1108/* Opcode VEX.66.0F3A 0xdd - invalid */
1109/* Opcode VEX.66.0F3A 0xde - invalid */
1110/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
1111FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
1112
1113
1114/** Opcode VEX.F2.0F3A (vex only) */
1115FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
1116{
1117 IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO);
1118 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1119 if (IEM_IS_MODRM_REG_MODE(bRm))
1120 {
1121 /*
1122 * Register, register.
1123 */
1124 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1125 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1126 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1127 {
1128 IEM_MC_BEGIN(3, 0);
1129 IEM_MC_ARG(uint64_t *, pDst, 0);
1130 IEM_MC_ARG(uint64_t, uSrc1, 1);
1131 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1132 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1133 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1134 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1135 IEM_MC_ADVANCE_RIP_AND_FINISH();
1136 IEM_MC_END();
1137 }
1138 else
1139 {
1140 IEM_MC_BEGIN(3, 0);
1141 IEM_MC_ARG(uint32_t *, pDst, 0);
1142 IEM_MC_ARG(uint32_t, uSrc1, 1);
1143 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1144 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1145 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1146 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1147 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
1148 IEM_MC_ADVANCE_RIP_AND_FINISH();
1149 IEM_MC_END();
1150 }
1151 }
1152 else
1153 {
1154 /*
1155 * Register, memory.
1156 */
1157 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1158 {
1159 IEM_MC_BEGIN(3, 1);
1160 IEM_MC_ARG(uint64_t *, pDst, 0);
1161 IEM_MC_ARG(uint64_t, uSrc1, 1);
1162 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1163 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1164 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1165 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1166 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1167 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1168 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1169 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1170 IEM_MC_ADVANCE_RIP_AND_FINISH();
1171 IEM_MC_END();
1172 }
1173 else
1174 {
1175 IEM_MC_BEGIN(3, 1);
1176 IEM_MC_ARG(uint32_t *, pDst, 0);
1177 IEM_MC_ARG(uint32_t, uSrc1, 1);
1178 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1179 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1180 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1181 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1182 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1183 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1184 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1185 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1186 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
1187 IEM_MC_ADVANCE_RIP_AND_FINISH();
1188 IEM_MC_END();
1189 }
1190 }
1191}
1192
1193
1194/**
1195 * VEX opcode map \#3.
1196 *
1197 * @sa g_apfnThreeByte0f3a
1198 */
1199IEM_STATIC const PFNIEMOP g_apfnVexMap3[] =
1200{
1201 /* no prefix, 066h prefix f3h prefix, f2h prefix */
1202 /* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1203 /* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1204 /* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1205 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1206 /* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1207 /* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1208 /* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1209 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1210 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1211 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1212 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1213 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1214 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1215 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1216 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vpblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1217 /* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1218
1219 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1220 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1221 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1222 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1223 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1224 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1225 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1226 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1227 /* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1228 /* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1229 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1230 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1231 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1232 /* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1233 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1234 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1235
1236 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1237 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1238 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1239 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1240 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1241 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1242 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1243 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1244 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1245 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1246 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1247 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1248 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1249 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1250 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1251 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1252
1253 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1254 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1255 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1256 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1257 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1258 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1259 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1260 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1261 /* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1262 /* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1263 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1264 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1265 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1266 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1267 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1268 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1269
1270 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1271 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1272 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1273 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1274 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1275 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1276 /* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1277 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1278 /* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1279 /* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1280 /* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1281 /* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1282 /* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1283 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1284 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1285 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1286
1287 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1288 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1289 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1290 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1291 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1292 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1293 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1294 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1295 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1296 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1297 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1298 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1299 /* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1300 /* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1301 /* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1302 /* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1303
1304 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1305 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1306 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1307 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1308 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1309 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1310 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1311 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1312 /* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1313 /* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1314 /* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1315 /* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1316 /* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1317 /* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1318 /* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1319 /* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1320
1321 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1322 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1323 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1324 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1325 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1326 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1327 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1328 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1329 /* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1330 /* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1331 /* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1332 /* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1333 /* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1334 /* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1335 /* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1336 /* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1337
1338 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1339 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1340 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1341 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1342 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1343 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1344 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1345 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1346 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1347 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1348 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1349 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1350 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1351 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1352 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1353 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1354
1355 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1356 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1357 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1358 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1359 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1360 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1361 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1362 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1363 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1364 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1365 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1366 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1367 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1368 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1369 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1370 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1371
1372 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1373 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1374 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1375 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1376 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1377 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1378 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1379 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1380 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1381 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1382 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1383 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1384 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1385 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1386 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1387 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1388
1389 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1390 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1391 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1392 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1393 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1394 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1395 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1396 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1397 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1398 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1399 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1400 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1401 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1402 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1403 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1404 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1405
1406 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1407 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1408 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1409 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1410 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1411 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1412 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1413 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1414 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1415 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1416 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1417 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1418 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1419 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1420 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1421 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1422
1423 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1424 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1425 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1426 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1427 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1428 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1429 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1430 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1431 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1432 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1433 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1434 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1435 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1436 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1437 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1438 /* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1439
1440 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1441 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1442 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1443 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1444 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1445 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1446 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1447 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1448 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1449 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1450 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1451 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1452 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1453 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1454 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1455 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1456
1457 /* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
1458 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1459 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1460 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1461 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1462 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1463 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1464 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1465 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1466 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1467 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1468 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1469 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1470 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1471 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1472 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1473};
1474AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
1475
1476/** @} */
1477
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