IEMAllInstructionsVexMap2.cpp.h@ 95453

最後變更在這個檔案從95453是 95453,由 vboxsync 提交於 3 年前
VMM/IEM: [v]pcmpeqq and [v]pcmpgtq. bugref:9898
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 71.8 KB

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1	/* $Id: IEMAllInstructionsVexMap2.cpp.h 95453 2022-06-30 09:43:46Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.alldomusa.eu.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name VEX Opcode Map 2
23	* @{
24	*/
25
26	/* Opcode VEX.0F38 0x00 - invalid. */
27	/** Opcode VEX.66.0F38 0x00. */
28	FNIEMOP_STUB(iemOp_vpshufb_Vx_Hx_Wx);
29	/* Opcode VEX.0F38 0x01 - invalid. */
30	/** Opcode VEX.66.0F38 0x01. */
31	FNIEMOP_STUB(iemOp_vphaddw_Vx_Hx_Wx);
32	/* Opcode VEX.0F38 0x02 - invalid. */
33	/** Opcode VEX.66.0F38 0x02. */
34	FNIEMOP_STUB(iemOp_vphaddd_Vx_Hx_Wx);
35	/* Opcode VEX.0F38 0x03 - invalid. */
36	/** Opcode VEX.66.0F38 0x03. */
37	FNIEMOP_STUB(iemOp_vphaddsw_Vx_Hx_Wx);
38	/* Opcode VEX.0F38 0x04 - invalid. */
39	/** Opcode VEX.66.0F38 0x04. */
40	FNIEMOP_STUB(iemOp_vpmaddubsw_Vx_Hx_Wx);
41	/* Opcode VEX.0F38 0x05 - invalid. */
42	/** Opcode VEX.66.0F38 0x05. */
43	FNIEMOP_STUB(iemOp_vphsubw_Vx_Hx_Wx);
44	/* Opcode VEX.0F38 0x06 - invalid. */
45	/** Opcode VEX.66.0F38 0x06. */
46	FNIEMOP_STUB(iemOp_vphsubdq_Vx_Hx_Wx);
47	/* Opcode VEX.0F38 0x07 - invalid. */
48	/** Opcode VEX.66.0F38 0x07. */
49	FNIEMOP_STUB(iemOp_vphsubsw_Vx_Hx_Wx);
50	/* Opcode VEX.0F38 0x08 - invalid. */
51	/** Opcode VEX.66.0F38 0x08. */
52	FNIEMOP_STUB(iemOp_vpsignb_Vx_Hx_Wx);
53	/* Opcode VEX.0F38 0x09 - invalid. */
54	/** Opcode VEX.66.0F38 0x09. */
55	FNIEMOP_STUB(iemOp_vpsignw_Vx_Hx_Wx);
56	/* Opcode VEX.0F38 0x0a - invalid. */
57	/** Opcode VEX.66.0F38 0x0a. */
58	FNIEMOP_STUB(iemOp_vpsignd_Vx_Hx_Wx);
59	/* Opcode VEX.0F38 0x0b - invalid. */
60	/** Opcode VEX.66.0F38 0x0b. */
61	FNIEMOP_STUB(iemOp_vpmulhrsw_Vx_Hx_Wx);
62	/* Opcode VEX.0F38 0x0c - invalid. */
63	/** Opcode VEX.66.0F38 0x0c. */
64	FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
65	/* Opcode VEX.0F38 0x0d - invalid. */
66	/** Opcode VEX.66.0F38 0x0d. */
67	FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
68	/* Opcode VEX.0F38 0x0e - invalid. */
69	/** Opcode VEX.66.0F38 0x0e. */
70	FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
71	/* Opcode VEX.0F38 0x0f - invalid. */
72	/** Opcode VEX.66.0F38 0x0f. */
73	FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
74
75
76	/* Opcode VEX.0F38 0x10 - invalid */
77	/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
78	/* Opcode VEX.0F38 0x11 - invalid */
79	/* Opcode VEX.66.0F38 0x11 - invalid */
80	/* Opcode VEX.0F38 0x12 - invalid */
81	/* Opcode VEX.66.0F38 0x12 - invalid */
82	/* Opcode VEX.0F38 0x13 - invalid */
83	/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
84	/* Opcode VEX.0F38 0x14 - invalid */
85	/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
86	/* Opcode VEX.0F38 0x15 - invalid */
87	/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
88	/* Opcode VEX.0F38 0x16 - invalid */
89	/** Opcode VEX.66.0F38 0x16. */
90	FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
91	/* Opcode VEX.0F38 0x17 - invalid */
92	/** Opcode VEX.66.0F38 0x17 - invalid */
93	FNIEMOP_STUB(iemOp_vptest_Vx_Wx);
94	/* Opcode VEX.0F38 0x18 - invalid */
95	/** Opcode VEX.66.0F38 0x18. */
96	FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
97	/* Opcode VEX.0F38 0x19 - invalid */
98	/** Opcode VEX.66.0F38 0x19. */
99	FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
100	/* Opcode VEX.0F38 0x1a - invalid */
101	/** Opcode VEX.66.0F38 0x1a. */
102	FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
103	/* Opcode VEX.0F38 0x1b - invalid */
104	/* Opcode VEX.66.0F38 0x1b - invalid */
105	/* Opcode VEX.0F38 0x1c - invalid. */
106	/** Opcode VEX.66.0F38 0x1c. */
107	FNIEMOP_STUB(iemOp_vpabsb_Vx_Wx);
108	/* Opcode VEX.0F38 0x1d - invalid. */
109	/** Opcode VEX.66.0F38 0x1d. */
110	FNIEMOP_STUB(iemOp_vpabsw_Vx_Wx);
111	/* Opcode VEX.0F38 0x1e - invalid. */
112	/** Opcode VEX.66.0F38 0x1e. */
113	FNIEMOP_STUB(iemOp_vpabsd_Vx_Wx);
114	/* Opcode VEX.0F38 0x1f - invalid */
115	/* Opcode VEX.66.0F38 0x1f - invalid */
116
117
118	/** Opcode VEX.66.0F38 0x20. */
119	FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
120	/** Opcode VEX.66.0F38 0x21. */
121	FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
122	/** Opcode VEX.66.0F38 0x22. */
123	FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
124	/** Opcode VEX.66.0F38 0x23. */
125	FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
126	/** Opcode VEX.66.0F38 0x24. */
127	FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
128	/** Opcode VEX.66.0F38 0x25. */
129	FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
130	/* Opcode VEX.66.0F38 0x26 - invalid */
131	/* Opcode VEX.66.0F38 0x27 - invalid */
132	/** Opcode VEX.66.0F38 0x28. */
133	FNIEMOP_STUB(iemOp_vpmuldq_Vx_Hx_Wx);
134
135
136	/** Opcode VEX.66.0F38 0x29. */
137	FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
138	{
139	IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
140	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
141	IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpcmpeqq, &g_iemAImpl_vpcmpeqq_fallback));
142	}
143
144
145	FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
146	{
147	Assert(pVCpu->iem.s.uVexLength <= 1);
148	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
149	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
150	{
151	if (pVCpu->iem.s.uVexLength == 0)
152	{
153	/**
154	* @opcode 0x2a
155	* @opcodesub !11 mr/reg vex.l=0
156	* @oppfx 0x66
157	* @opcpuid avx
158	* @opgroup og_avx_cachect
159	* @opxcpttype 1
160	* @optest op1=-1 op2=2 -> op1=2
161	* @optest op1=0 op2=-42 -> op1=-42
162	*/
163	/* 128-bit: Memory, register. */
164	IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
165	DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
166	IEM_MC_BEGIN(0, 2);
167	IEM_MC_LOCAL(RTUINT128U, uSrc);
168	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
169
170	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
171	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
172	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
173	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
174
175	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
176	IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
177
178	IEM_MC_ADVANCE_RIP();
179	IEM_MC_END();
180	}
181	else
182	{
183	/**
184	* @opdone
185	* @opcode 0x2a
186	* @opcodesub !11 mr/reg vex.l=1
187	* @oppfx 0x66
188	* @opcpuid avx2
189	* @opgroup og_avx2_cachect
190	* @opxcpttype 1
191	* @optest op1=-1 op2=2 -> op1=2
192	* @optest op1=0 op2=-42 -> op1=-42
193	*/
194	/* 256-bit: Memory, register. */
195	IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
196	DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
197	IEM_MC_BEGIN(0, 2);
198	IEM_MC_LOCAL(RTUINT256U, uSrc);
199	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
200
201	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
202	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
203	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
204	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
205
206	IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
207	IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
208
209	IEM_MC_ADVANCE_RIP();
210	IEM_MC_END();
211	}
212	return VINF_SUCCESS;
213	}
214
215	/**
216	* @opdone
217	* @opmnemonic udvex660f382arg
218	* @opcode 0x2a
219	* @opcodesub 11 mr/reg
220	* @oppfx 0x66
221	* @opunused immediate
222	* @opcpuid avx
223	* @optest ->
224	*/
225	return IEMOP_RAISE_INVALID_OPCODE();
226
227	}
228
229
230	/** Opcode VEX.66.0F38 0x2b. */
231	FNIEMOP_STUB(iemOp_vpackusdw_Vx_Hx_Wx);
232	/** Opcode VEX.66.0F38 0x2c. */
233	FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
234	/** Opcode VEX.66.0F38 0x2d. */
235	FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
236	/** Opcode VEX.66.0F38 0x2e. */
237	FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
238	/** Opcode VEX.66.0F38 0x2f. */
239	FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
240
241	/** Opcode VEX.66.0F38 0x30. */
242	FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
243	/** Opcode VEX.66.0F38 0x31. */
244	FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
245	/** Opcode VEX.66.0F38 0x32. */
246	FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
247	/** Opcode VEX.66.0F38 0x33. */
248	FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
249	/** Opcode VEX.66.0F38 0x34. */
250	FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
251	/** Opcode VEX.66.0F38 0x35. */
252	FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
253	/* Opcode VEX.66.0F38 0x36. */
254	FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
255
256
257	/** Opcode VEX.66.0F38 0x37. */
258	FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
259	{
260	IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
261	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
262	IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpcmpgtq, &g_iemAImpl_vpcmpgtq_fallback));
263	}
264
265
266	/** Opcode VEX.66.0F38 0x38. */
267	FNIEMOP_STUB(iemOp_vpminsb_Vx_Hx_Wx);
268	/** Opcode VEX.66.0F38 0x39. */
269	FNIEMOP_STUB(iemOp_vpminsd_Vx_Hx_Wx);
270	/** Opcode VEX.66.0F38 0x3a. */
271	FNIEMOP_STUB(iemOp_vpminuw_Vx_Hx_Wx);
272	/** Opcode VEX.66.0F38 0x3b. */
273	FNIEMOP_STUB(iemOp_vpminud_Vx_Hx_Wx);
274	/** Opcode VEX.66.0F38 0x3c. */
275	FNIEMOP_STUB(iemOp_vpmaxsb_Vx_Hx_Wx);
276	/** Opcode VEX.66.0F38 0x3d. */
277	FNIEMOP_STUB(iemOp_vpmaxsd_Vx_Hx_Wx);
278	/** Opcode VEX.66.0F38 0x3e. */
279	FNIEMOP_STUB(iemOp_vpmaxuw_Vx_Hx_Wx);
280	/** Opcode VEX.66.0F38 0x3f. */
281	FNIEMOP_STUB(iemOp_vpmaxud_Vx_Hx_Wx);
282
283
284	/** Opcode VEX.66.0F38 0x40. */
285	FNIEMOP_STUB(iemOp_vpmulld_Vx_Hx_Wx);
286	/** Opcode VEX.66.0F38 0x41. */
287	FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
288	/* Opcode VEX.66.0F38 0x42 - invalid. */
289	/* Opcode VEX.66.0F38 0x43 - invalid. */
290	/* Opcode VEX.66.0F38 0x44 - invalid. */
291	/** Opcode VEX.66.0F38 0x45. */
292	FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
293	/** Opcode VEX.66.0F38 0x46. */
294	FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
295	/** Opcode VEX.66.0F38 0x47. */
296	FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
297	/* Opcode VEX.66.0F38 0x48 - invalid. */
298	/* Opcode VEX.66.0F38 0x49 - invalid. */
299	/* Opcode VEX.66.0F38 0x4a - invalid. */
300	/* Opcode VEX.66.0F38 0x4b - invalid. */
301	/* Opcode VEX.66.0F38 0x4c - invalid. */
302	/* Opcode VEX.66.0F38 0x4d - invalid. */
303	/* Opcode VEX.66.0F38 0x4e - invalid. */
304	/* Opcode VEX.66.0F38 0x4f - invalid. */
305
306	/* Opcode VEX.66.0F38 0x50 - invalid. */
307	/* Opcode VEX.66.0F38 0x51 - invalid. */
308	/* Opcode VEX.66.0F38 0x52 - invalid. */
309	/* Opcode VEX.66.0F38 0x53 - invalid. */
310	/* Opcode VEX.66.0F38 0x54 - invalid. */
311	/* Opcode VEX.66.0F38 0x55 - invalid. */
312	/* Opcode VEX.66.0F38 0x56 - invalid. */
313	/* Opcode VEX.66.0F38 0x57 - invalid. */
314	/** Opcode VEX.66.0F38 0x58. */
315	FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
316	/** Opcode VEX.66.0F38 0x59. */
317	FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
318	/** Opcode VEX.66.0F38 0x5a. */
319	FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
320	/* Opcode VEX.66.0F38 0x5b - invalid. */
321	/* Opcode VEX.66.0F38 0x5c - invalid. */
322	/* Opcode VEX.66.0F38 0x5d - invalid. */
323	/* Opcode VEX.66.0F38 0x5e - invalid. */
324	/* Opcode VEX.66.0F38 0x5f - invalid. */
325
326	/* Opcode VEX.66.0F38 0x60 - invalid. */
327	/* Opcode VEX.66.0F38 0x61 - invalid. */
328	/* Opcode VEX.66.0F38 0x62 - invalid. */
329	/* Opcode VEX.66.0F38 0x63 - invalid. */
330	/* Opcode VEX.66.0F38 0x64 - invalid. */
331	/* Opcode VEX.66.0F38 0x65 - invalid. */
332	/* Opcode VEX.66.0F38 0x66 - invalid. */
333	/* Opcode VEX.66.0F38 0x67 - invalid. */
334	/* Opcode VEX.66.0F38 0x68 - invalid. */
335	/* Opcode VEX.66.0F38 0x69 - invalid. */
336	/* Opcode VEX.66.0F38 0x6a - invalid. */
337	/* Opcode VEX.66.0F38 0x6b - invalid. */
338	/* Opcode VEX.66.0F38 0x6c - invalid. */
339	/* Opcode VEX.66.0F38 0x6d - invalid. */
340	/* Opcode VEX.66.0F38 0x6e - invalid. */
341	/* Opcode VEX.66.0F38 0x6f - invalid. */
342
343	/* Opcode VEX.66.0F38 0x70 - invalid. */
344	/* Opcode VEX.66.0F38 0x71 - invalid. */
345	/* Opcode VEX.66.0F38 0x72 - invalid. */
346	/* Opcode VEX.66.0F38 0x73 - invalid. */
347	/* Opcode VEX.66.0F38 0x74 - invalid. */
348	/* Opcode VEX.66.0F38 0x75 - invalid. */
349	/* Opcode VEX.66.0F38 0x76 - invalid. */
350	/* Opcode VEX.66.0F38 0x77 - invalid. */
351	/** Opcode VEX.66.0F38 0x78. */
352	FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
353	/** Opcode VEX.66.0F38 0x79. */
354	FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
355	/* Opcode VEX.66.0F38 0x7a - invalid. */
356	/* Opcode VEX.66.0F38 0x7b - invalid. */
357	/* Opcode VEX.66.0F38 0x7c - invalid. */
358	/* Opcode VEX.66.0F38 0x7d - invalid. */
359	/* Opcode VEX.66.0F38 0x7e - invalid. */
360	/* Opcode VEX.66.0F38 0x7f - invalid. */
361
362	/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
363	/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
364	/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
365	/* Opcode VEX.66.0F38 0x83 - invalid. */
366	/* Opcode VEX.66.0F38 0x84 - invalid. */
367	/* Opcode VEX.66.0F38 0x85 - invalid. */
368	/* Opcode VEX.66.0F38 0x86 - invalid. */
369	/* Opcode VEX.66.0F38 0x87 - invalid. */
370	/* Opcode VEX.66.0F38 0x88 - invalid. */
371	/* Opcode VEX.66.0F38 0x89 - invalid. */
372	/* Opcode VEX.66.0F38 0x8a - invalid. */
373	/* Opcode VEX.66.0F38 0x8b - invalid. */
374	/** Opcode VEX.66.0F38 0x8c. */
375	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
376	/* Opcode VEX.66.0F38 0x8d - invalid. */
377	/** Opcode VEX.66.0F38 0x8e. */
378	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
379	/* Opcode VEX.66.0F38 0x8f - invalid. */
380
381	/** Opcode VEX.66.0F38 0x90 (vex only). */
382	FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
383	/** Opcode VEX.66.0F38 0x91 (vex only). */
384	FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
385	/** Opcode VEX.66.0F38 0x92 (vex only). */
386	FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
387	/** Opcode VEX.66.0F38 0x93 (vex only). */
388	FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
389	/* Opcode VEX.66.0F38 0x94 - invalid. */
390	/* Opcode VEX.66.0F38 0x95 - invalid. */
391	/** Opcode VEX.66.0F38 0x96 (vex only). */
392	FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
393	/** Opcode VEX.66.0F38 0x97 (vex only). */
394	FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
395	/** Opcode VEX.66.0F38 0x98 (vex only). */
396	FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
397	/** Opcode VEX.66.0F38 0x99 (vex only). */
398	FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
399	/** Opcode VEX.66.0F38 0x9a (vex only). */
400	FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
401	/** Opcode VEX.66.0F38 0x9b (vex only). */
402	FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
403	/** Opcode VEX.66.0F38 0x9c (vex only). */
404	FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
405	/** Opcode VEX.66.0F38 0x9d (vex only). */
406	FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
407	/** Opcode VEX.66.0F38 0x9e (vex only). */
408	FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
409	/** Opcode VEX.66.0F38 0x9f (vex only). */
410	FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
411
412	/* Opcode VEX.66.0F38 0xa0 - invalid. */
413	/* Opcode VEX.66.0F38 0xa1 - invalid. */
414	/* Opcode VEX.66.0F38 0xa2 - invalid. */
415	/* Opcode VEX.66.0F38 0xa3 - invalid. */
416	/* Opcode VEX.66.0F38 0xa4 - invalid. */
417	/* Opcode VEX.66.0F38 0xa5 - invalid. */
418	/** Opcode VEX.66.0F38 0xa6 (vex only). */
419	FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
420	/** Opcode VEX.66.0F38 0xa7 (vex only). */
421	FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
422	/** Opcode VEX.66.0F38 0xa8 (vex only). */
423	FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
424	/** Opcode VEX.66.0F38 0xa9 (vex only). */
425	FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
426	/** Opcode VEX.66.0F38 0xaa (vex only). */
427	FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
428	/** Opcode VEX.66.0F38 0xab (vex only). */
429	FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
430	/** Opcode VEX.66.0F38 0xac (vex only). */
431	FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
432	/** Opcode VEX.66.0F38 0xad (vex only). */
433	FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
434	/** Opcode VEX.66.0F38 0xae (vex only). */
435	FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
436	/** Opcode VEX.66.0F38 0xaf (vex only). */
437	FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
438
439	/* Opcode VEX.66.0F38 0xb0 - invalid. */
440	/* Opcode VEX.66.0F38 0xb1 - invalid. */
441	/* Opcode VEX.66.0F38 0xb2 - invalid. */
442	/* Opcode VEX.66.0F38 0xb3 - invalid. */
443	/* Opcode VEX.66.0F38 0xb4 - invalid. */
444	/* Opcode VEX.66.0F38 0xb5 - invalid. */
445	/** Opcode VEX.66.0F38 0xb6 (vex only). */
446	FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
447	/** Opcode VEX.66.0F38 0xb7 (vex only). */
448	FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
449	/** Opcode VEX.66.0F38 0xb8 (vex only). */
450	FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
451	/** Opcode VEX.66.0F38 0xb9 (vex only). */
452	FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
453	/** Opcode VEX.66.0F38 0xba (vex only). */
454	FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
455	/** Opcode VEX.66.0F38 0xbb (vex only). */
456	FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
457	/** Opcode VEX.66.0F38 0xbc (vex only). */
458	FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
459	/** Opcode VEX.66.0F38 0xbd (vex only). */
460	FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
461	/** Opcode VEX.66.0F38 0xbe (vex only). */
462	FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
463	/** Opcode VEX.66.0F38 0xbf (vex only). */
464	FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
465
466	/* Opcode VEX.0F38 0xc0 - invalid. */
467	/* Opcode VEX.66.0F38 0xc0 - invalid. */
468	/* Opcode VEX.0F38 0xc1 - invalid. */
469	/* Opcode VEX.66.0F38 0xc1 - invalid. */
470	/* Opcode VEX.0F38 0xc2 - invalid. */
471	/* Opcode VEX.66.0F38 0xc2 - invalid. */
472	/* Opcode VEX.0F38 0xc3 - invalid. */
473	/* Opcode VEX.66.0F38 0xc3 - invalid. */
474	/* Opcode VEX.0F38 0xc4 - invalid. */
475	/* Opcode VEX.66.0F38 0xc4 - invalid. */
476	/* Opcode VEX.0F38 0xc5 - invalid. */
477	/* Opcode VEX.66.0F38 0xc5 - invalid. */
478	/* Opcode VEX.0F38 0xc6 - invalid. */
479	/* Opcode VEX.66.0F38 0xc6 - invalid. */
480	/* Opcode VEX.0F38 0xc7 - invalid. */
481	/* Opcode VEX.66.0F38 0xc7 - invalid. */
482	/** Opcode VEX.0F38 0xc8. */
483	FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
484	/* Opcode VEX.66.0F38 0xc8 - invalid. */
485	/** Opcode VEX.0F38 0xc9. */
486	FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
487	/* Opcode VEX.66.0F38 0xc9 - invalid. */
488	/** Opcode VEX.0F38 0xca. */
489	FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
490	/* Opcode VEX.66.0F38 0xca - invalid. */
491	/** Opcode VEX.0F38 0xcb. */
492	FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
493	/* Opcode VEX.66.0F38 0xcb - invalid. */
494	/** Opcode VEX.0F38 0xcc. */
495	FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
496	/* Opcode VEX.66.0F38 0xcc - invalid. */
497	/** Opcode VEX.0F38 0xcd. */
498	FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
499	/* Opcode VEX.66.0F38 0xcd - invalid. */
500	/* Opcode VEX.0F38 0xce - invalid. */
501	/* Opcode VEX.66.0F38 0xce - invalid. */
502	/* Opcode VEX.0F38 0xcf - invalid. */
503	/* Opcode VEX.66.0F38 0xcf - invalid. */
504
505	/* Opcode VEX.66.0F38 0xd0 - invalid. */
506	/* Opcode VEX.66.0F38 0xd1 - invalid. */
507	/* Opcode VEX.66.0F38 0xd2 - invalid. */
508	/* Opcode VEX.66.0F38 0xd3 - invalid. */
509	/* Opcode VEX.66.0F38 0xd4 - invalid. */
510	/* Opcode VEX.66.0F38 0xd5 - invalid. */
511	/* Opcode VEX.66.0F38 0xd6 - invalid. */
512	/* Opcode VEX.66.0F38 0xd7 - invalid. */
513	/* Opcode VEX.66.0F38 0xd8 - invalid. */
514	/* Opcode VEX.66.0F38 0xd9 - invalid. */
515	/* Opcode VEX.66.0F38 0xda - invalid. */
516	/** Opcode VEX.66.0F38 0xdb. */
517	FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
518	/** Opcode VEX.66.0F38 0xdc. */
519	FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
520	/** Opcode VEX.66.0F38 0xdd. */
521	FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
522	/** Opcode VEX.66.0F38 0xde. */
523	FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
524	/** Opcode VEX.66.0F38 0xdf. */
525	FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
526
527	/* Opcode VEX.66.0F38 0xe0 - invalid. */
528	/* Opcode VEX.66.0F38 0xe1 - invalid. */
529	/* Opcode VEX.66.0F38 0xe2 - invalid. */
530	/* Opcode VEX.66.0F38 0xe3 - invalid. */
531	/* Opcode VEX.66.0F38 0xe4 - invalid. */
532	/* Opcode VEX.66.0F38 0xe5 - invalid. */
533	/* Opcode VEX.66.0F38 0xe6 - invalid. */
534	/* Opcode VEX.66.0F38 0xe7 - invalid. */
535	/* Opcode VEX.66.0F38 0xe8 - invalid. */
536	/* Opcode VEX.66.0F38 0xe9 - invalid. */
537	/* Opcode VEX.66.0F38 0xea - invalid. */
538	/* Opcode VEX.66.0F38 0xeb - invalid. */
539	/* Opcode VEX.66.0F38 0xec - invalid. */
540	/* Opcode VEX.66.0F38 0xed - invalid. */
541	/* Opcode VEX.66.0F38 0xee - invalid. */
542	/* Opcode VEX.66.0F38 0xef - invalid. */
543
544
545	/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
546	/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
547	/* Opcode VEX.F3.0F38 0xf0 - invalid. */
548	/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
549
550	/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
551	/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
552	/* Opcode VEX.F3.0F38 0xf1 - invalid. */
553	/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
554
555	/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
556	FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
557	{
558	IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
559	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
560	return iemOp_InvalidNeedRM(pVCpu);
561	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF);
562	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
563	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
564	{
565	/*
566	* Register, register.
567	*/
568	IEMOP_HLP_DONE_VEX_DECODING_L0();
569	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
570	{
571	IEM_MC_BEGIN(4, 0);
572	IEM_MC_ARG(uint64_t *, pDst, 0);
573	IEM_MC_ARG(uint64_t, uSrc1, 1);
574	IEM_MC_ARG(uint64_t, uSrc2, 2);
575	IEM_MC_ARG(uint32_t *, pEFlags, 3);
576	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
577	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
578	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
579	IEM_MC_REF_EFLAGS(pEFlags);
580	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
581	pDst, uSrc1, uSrc2, pEFlags);
582	IEM_MC_ADVANCE_RIP();
583	IEM_MC_END();
584	}
585	else
586	{
587	IEM_MC_BEGIN(4, 0);
588	IEM_MC_ARG(uint32_t *, pDst, 0);
589	IEM_MC_ARG(uint32_t, uSrc1, 1);
590	IEM_MC_ARG(uint32_t, uSrc2, 2);
591	IEM_MC_ARG(uint32_t *, pEFlags, 3);
592	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
593	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
594	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
595	IEM_MC_REF_EFLAGS(pEFlags);
596	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
597	pDst, uSrc1, uSrc2, pEFlags);
598	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
599	IEM_MC_ADVANCE_RIP();
600	IEM_MC_END();
601	}
602	}
603	else
604	{
605	/*
606	* Register, memory.
607	*/
608	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
609	{
610	IEM_MC_BEGIN(4, 1);
611	IEM_MC_ARG(uint64_t *, pDst, 0);
612	IEM_MC_ARG(uint64_t, uSrc1, 1);
613	IEM_MC_ARG(uint64_t, uSrc2, 2);
614	IEM_MC_ARG(uint32_t *, pEFlags, 3);
615	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
616	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
617	IEMOP_HLP_DONE_VEX_DECODING_L0();
618	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
619	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
620	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
621	IEM_MC_REF_EFLAGS(pEFlags);
622	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
623	pDst, uSrc1, uSrc2, pEFlags);
624	IEM_MC_ADVANCE_RIP();
625	IEM_MC_END();
626	}
627	else
628	{
629	IEM_MC_BEGIN(4, 1);
630	IEM_MC_ARG(uint32_t *, pDst, 0);
631	IEM_MC_ARG(uint32_t, uSrc1, 1);
632	IEM_MC_ARG(uint32_t, uSrc2, 2);
633	IEM_MC_ARG(uint32_t *, pEFlags, 3);
634	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
635	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
636	IEMOP_HLP_DONE_VEX_DECODING_L0();
637	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
638	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
639	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
640	IEM_MC_REF_EFLAGS(pEFlags);
641	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
642	pDst, uSrc1, uSrc2, pEFlags);
643	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
644	IEM_MC_ADVANCE_RIP();
645	IEM_MC_END();
646	}
647	}
648	return VINF_SUCCESS;
649	}
650
651	/* Opcode VEX.66.0F38 0xf2 - invalid. */
652	/* Opcode VEX.F3.0F38 0xf2 - invalid. */
653	/* Opcode VEX.F2.0F38 0xf2 - invalid. */
654
655
656	/* Opcode VEX.0F38 0xf3 - invalid. */
657	/* Opcode VEX.66.0F38 0xf3 - invalid. */
658
659	/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
660
661	/** Body for the vex group 17 instructions. */
662	#define IEMOP_BODY_By_Ey(a_Instr) \
663	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
664	return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
665	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF); \
666	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
667	{ \
668	/* \
669	* Register, register. \
670	*/ \
671	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
672	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
673	{ \
674	IEM_MC_BEGIN(3, 0); \
675	IEM_MC_ARG(uint64_t *, pDst, 0); \
676	IEM_MC_ARG(uint64_t, uSrc, 1); \
677	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
678	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
679	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
680	IEM_MC_REF_EFLAGS(pEFlags); \
681	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
682	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
683	IEM_MC_ADVANCE_RIP(); \
684	IEM_MC_END(); \
685	} \
686	else \
687	{ \
688	IEM_MC_BEGIN(3, 0); \
689	IEM_MC_ARG(uint32_t *, pDst, 0); \
690	IEM_MC_ARG(uint32_t, uSrc, 1); \
691	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
692	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
693	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
694	IEM_MC_REF_EFLAGS(pEFlags); \
695	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
696	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
697	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
698	IEM_MC_ADVANCE_RIP(); \
699	IEM_MC_END(); \
700	} \
701	} \
702	else \
703	{ \
704	/* \
705	* Register, memory. \
706	*/ \
707	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
708	{ \
709	IEM_MC_BEGIN(3, 1); \
710	IEM_MC_ARG(uint64_t *, pDst, 0); \
711	IEM_MC_ARG(uint64_t, uSrc, 1); \
712	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
713	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
714	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
715	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
716	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
717	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
718	IEM_MC_REF_EFLAGS(pEFlags); \
719	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
720	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
721	IEM_MC_ADVANCE_RIP(); \
722	IEM_MC_END(); \
723	} \
724	else \
725	{ \
726	IEM_MC_BEGIN(3, 1); \
727	IEM_MC_ARG(uint32_t *, pDst, 0); \
728	IEM_MC_ARG(uint32_t, uSrc, 1); \
729	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
730	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
731	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
732	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
733	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
734	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
735	IEM_MC_REF_EFLAGS(pEFlags); \
736	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
737	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
738	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
739	IEM_MC_ADVANCE_RIP(); \
740	IEM_MC_END(); \
741	} \
742	} \
743	return VINF_SUCCESS
744
745
746	/* Opcode VEX.F3.0F38 0xf3 /1. */
747	/** @opcode /1
748	* @opmaps vexgrp17 */
749	FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
750	{
751	IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
752	IEMOP_BODY_By_Ey(blsr);
753	}
754
755
756	/* Opcode VEX.F3.0F38 0xf3 /2. */
757	/** @opcode /2
758	* @opmaps vexgrp17 */
759	FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
760	{
761	IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
762	IEMOP_BODY_By_Ey(blsmsk);
763	}
764
765
766	/* Opcode VEX.F3.0F38 0xf3 /3. */
767	/** @opcode /3
768	* @opmaps vexgrp17 */
769	FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
770	{
771	IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
772	IEMOP_BODY_By_Ey(blsi);
773	}
774
775
776	/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
777	/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
778	/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
779	/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
780
781	/**
782	* Group 17 jump table for the VEX.F3 variant.
783	*/
784	IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
785	{
786	/* /0 */ iemOp_InvalidWithRM,
787	/* /1 */ iemOp_VGrp17_blsr_By_Ey,
788	/* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
789	/* /3 */ iemOp_VGrp17_blsi_By_Ey,
790	/* /4 */ iemOp_InvalidWithRM,
791	/* /5 */ iemOp_InvalidWithRM,
792	/* /6 */ iemOp_InvalidWithRM,
793	/* /7 */ iemOp_InvalidWithRM
794	};
795	AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
796
797	/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
798	FNIEMOP_DEF(iemOp_VGrp17_f3)
799	{
800	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
801	return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)], bRm);
802	}
803
804	/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
805
806
807	/* Opcode VEX.0F38 0xf4 - invalid. */
808	/* Opcode VEX.66.0F38 0xf4 - invalid. */
809	/* Opcode VEX.F3.0F38 0xf4 - invalid. */
810	/* Opcode VEX.F2.0F38 0xf4 - invalid. */
811
812	/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
813	#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
814	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
815	return iemOp_InvalidNeedRM(pVCpu); \
816	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
817	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
818	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
819	{ \
820	/* \
821	* Register, register. \
822	*/ \
823	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
824	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
825	{ \
826	IEM_MC_BEGIN(4, 0); \
827	IEM_MC_ARG(uint64_t *, pDst, 0); \
828	IEM_MC_ARG(uint64_t, uSrc1, 1); \
829	IEM_MC_ARG(uint64_t, uSrc2, 2); \
830	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
831	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
832	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
833	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
834	IEM_MC_REF_EFLAGS(pEFlags); \
835	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
836	iemAImpl_ ## a_Instr ## _u64_fallback), \
837	pDst, uSrc1, uSrc2, pEFlags); \
838	IEM_MC_ADVANCE_RIP(); \
839	IEM_MC_END(); \
840	} \
841	else \
842	{ \
843	IEM_MC_BEGIN(4, 0); \
844	IEM_MC_ARG(uint32_t *, pDst, 0); \
845	IEM_MC_ARG(uint32_t, uSrc1, 1); \
846	IEM_MC_ARG(uint32_t, uSrc2, 2); \
847	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
848	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
849	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
850	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
851	IEM_MC_REF_EFLAGS(pEFlags); \
852	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
853	iemAImpl_ ## a_Instr ## _u32_fallback), \
854	pDst, uSrc1, uSrc2, pEFlags); \
855	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
856	IEM_MC_ADVANCE_RIP(); \
857	IEM_MC_END(); \
858	} \
859	} \
860	else \
861	{ \
862	/* \
863	* Register, memory. \
864	*/ \
865	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
866	{ \
867	IEM_MC_BEGIN(4, 1); \
868	IEM_MC_ARG(uint64_t *, pDst, 0); \
869	IEM_MC_ARG(uint64_t, uSrc1, 1); \
870	IEM_MC_ARG(uint64_t, uSrc2, 2); \
871	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
872	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
873	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
874	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
875	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
876	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
877	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
878	IEM_MC_REF_EFLAGS(pEFlags); \
879	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
880	iemAImpl_ ## a_Instr ## _u64_fallback), \
881	pDst, uSrc1, uSrc2, pEFlags); \
882	IEM_MC_ADVANCE_RIP(); \
883	IEM_MC_END(); \
884	} \
885	else \
886	{ \
887	IEM_MC_BEGIN(4, 1); \
888	IEM_MC_ARG(uint32_t *, pDst, 0); \
889	IEM_MC_ARG(uint32_t, uSrc1, 1); \
890	IEM_MC_ARG(uint32_t, uSrc2, 2); \
891	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
892	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
893	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
894	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
895	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
896	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
897	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
898	IEM_MC_REF_EFLAGS(pEFlags); \
899	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
900	iemAImpl_ ## a_Instr ## _u32_fallback), \
901	pDst, uSrc1, uSrc2, pEFlags); \
902	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
903	IEM_MC_ADVANCE_RIP(); \
904	IEM_MC_END(); \
905	} \
906	} \
907	return VINF_SUCCESS
908
909	/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
910	#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
911	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
912	return iemOp_InvalidNeedRM(pVCpu); \
913	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
914	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
915	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
916	{ \
917	/* \
918	* Register, register. \
919	*/ \
920	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
921	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
922	{ \
923	IEM_MC_BEGIN(3, 0); \
924	IEM_MC_ARG(uint64_t *, pDst, 0); \
925	IEM_MC_ARG(uint64_t, uSrc1, 1); \
926	IEM_MC_ARG(uint64_t, uSrc2, 2); \
927	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
928	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
929	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
930	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
931	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
932	IEM_MC_ADVANCE_RIP(); \
933	IEM_MC_END(); \
934	} \
935	else \
936	{ \
937	IEM_MC_BEGIN(3, 0); \
938	IEM_MC_ARG(uint32_t *, pDst, 0); \
939	IEM_MC_ARG(uint32_t, uSrc1, 1); \
940	IEM_MC_ARG(uint32_t, uSrc2, 2); \
941	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
942	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
943	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
944	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
945	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
946	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
947	IEM_MC_ADVANCE_RIP(); \
948	IEM_MC_END(); \
949	} \
950	} \
951	else \
952	{ \
953	/* \
954	* Register, memory. \
955	*/ \
956	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
957	{ \
958	IEM_MC_BEGIN(3, 1); \
959	IEM_MC_ARG(uint64_t *, pDst, 0); \
960	IEM_MC_ARG(uint64_t, uSrc1, 1); \
961	IEM_MC_ARG(uint64_t, uSrc2, 2); \
962	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
963	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
964	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
965	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
966	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
967	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
968	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
969	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
970	IEM_MC_ADVANCE_RIP(); \
971	IEM_MC_END(); \
972	} \
973	else \
974	{ \
975	IEM_MC_BEGIN(3, 1); \
976	IEM_MC_ARG(uint32_t *, pDst, 0); \
977	IEM_MC_ARG(uint32_t, uSrc1, 1); \
978	IEM_MC_ARG(uint32_t, uSrc2, 2); \
979	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
980	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
981	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
982	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
983	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
984	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
985	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
986	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
987	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
988	IEM_MC_ADVANCE_RIP(); \
989	IEM_MC_END(); \
990	} \
991	} \
992	return VINF_SUCCESS
993
994	/** Opcode VEX.0F38 0xf5 (vex only). */
995	FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
996	{
997	IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
998	IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF \| X86_EFL_PF);
999	}
1000
1001	/* Opcode VEX.66.0F38 0xf5 - invalid. */
1002
1003	/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1004	#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1005	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1006	return iemOp_InvalidNeedRM(pVCpu); \
1007	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1008	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
1009	{ \
1010	/* \
1011	* Register, register. \
1012	*/ \
1013	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1014	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1015	{ \
1016	IEM_MC_BEGIN(3, 0); \
1017	IEM_MC_ARG(uint64_t *, pDst, 0); \
1018	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1019	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1020	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1021	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1022	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1023	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1024	iemAImpl_ ## a_Instr ## _u64, \
1025	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1026	IEM_MC_ADVANCE_RIP(); \
1027	IEM_MC_END(); \
1028	} \
1029	else \
1030	{ \
1031	IEM_MC_BEGIN(3, 0); \
1032	IEM_MC_ARG(uint32_t *, pDst, 0); \
1033	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1034	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1035	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1036	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1037	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1038	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1039	iemAImpl_ ## a_Instr ## _u32, \
1040	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1041	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1042	IEM_MC_ADVANCE_RIP(); \
1043	IEM_MC_END(); \
1044	} \
1045	} \
1046	else \
1047	{ \
1048	/* \
1049	* Register, memory. \
1050	*/ \
1051	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1052	{ \
1053	IEM_MC_BEGIN(3, 1); \
1054	IEM_MC_ARG(uint64_t *, pDst, 0); \
1055	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1056	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1057	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1058	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1059	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1060	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1061	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1062	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1063	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1064	iemAImpl_ ## a_Instr ## _u64, \
1065	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1066	IEM_MC_ADVANCE_RIP(); \
1067	IEM_MC_END(); \
1068	} \
1069	else \
1070	{ \
1071	IEM_MC_BEGIN(3, 1); \
1072	IEM_MC_ARG(uint32_t *, pDst, 0); \
1073	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1074	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1075	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1076	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1077	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1078	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1079	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1080	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1081	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1082	iemAImpl_ ## a_Instr ## _u32, \
1083	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1084	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1085	IEM_MC_ADVANCE_RIP(); \
1086	IEM_MC_END(); \
1087	} \
1088	} \
1089	return VINF_SUCCESS;
1090
1091
1092	/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1093	FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1094	{
1095	IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1096	IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1097	}
1098
1099
1100	/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1101	FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1102	{
1103	IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1104	IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1105	}
1106
1107
1108	/* Opcode VEX.0F38 0xf6 - invalid. */
1109	/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1110	/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1111
1112
1113	/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1114	FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1115	{
1116	IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1117	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
1118	return iemOp_InvalidNeedRM(pVCpu);
1119	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1120	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1121	{
1122	/*
1123	* Register, register.
1124	*/
1125	IEMOP_HLP_DONE_VEX_DECODING_L0();
1126	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1127	{
1128	IEM_MC_BEGIN(4, 0);
1129	IEM_MC_ARG(uint64_t *, pDst1, 0);
1130	IEM_MC_ARG(uint64_t *, pDst2, 1);
1131	IEM_MC_ARG(uint64_t, uSrc1, 2);
1132	IEM_MC_ARG(uint64_t, uSrc2, 3);
1133	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1134	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1135	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1136	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1137	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1138	pDst1, pDst2, uSrc1, uSrc2);
1139	IEM_MC_ADVANCE_RIP();
1140	IEM_MC_END();
1141	}
1142	else
1143	{
1144	IEM_MC_BEGIN(4, 0);
1145	IEM_MC_ARG(uint32_t *, pDst1, 0);
1146	IEM_MC_ARG(uint32_t *, pDst2, 1);
1147	IEM_MC_ARG(uint32_t, uSrc1, 2);
1148	IEM_MC_ARG(uint32_t, uSrc2, 3);
1149	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1150	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1151	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1152	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1153	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1154	pDst1, pDst2, uSrc1, uSrc2);
1155	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1156	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1157	IEM_MC_ADVANCE_RIP();
1158	IEM_MC_END();
1159	}
1160	}
1161	else
1162	{
1163	/*
1164	* Register, memory.
1165	*/
1166	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1167	{
1168	IEM_MC_BEGIN(4, 1);
1169	IEM_MC_ARG(uint64_t *, pDst1, 0);
1170	IEM_MC_ARG(uint64_t *, pDst2, 1);
1171	IEM_MC_ARG(uint64_t, uSrc1, 2);
1172	IEM_MC_ARG(uint64_t, uSrc2, 3);
1173	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1174	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1175	IEMOP_HLP_DONE_VEX_DECODING_L0();
1176	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1177	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1178	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1179	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1180	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1181	pDst1, pDst2, uSrc1, uSrc2);
1182	IEM_MC_ADVANCE_RIP();
1183	IEM_MC_END();
1184	}
1185	else
1186	{
1187	IEM_MC_BEGIN(4, 1);
1188	IEM_MC_ARG(uint32_t *, pDst1, 0);
1189	IEM_MC_ARG(uint32_t *, pDst2, 1);
1190	IEM_MC_ARG(uint32_t, uSrc1, 2);
1191	IEM_MC_ARG(uint32_t, uSrc2, 3);
1192	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1193	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1194	IEMOP_HLP_DONE_VEX_DECODING_L0();
1195	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1196	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1197	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1198	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1199	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1200	pDst1, pDst2, uSrc1, uSrc2);
1201	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1202	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1203	IEM_MC_ADVANCE_RIP();
1204	IEM_MC_END();
1205	}
1206	}
1207	return VINF_SUCCESS;
1208	}
1209
1210
1211	/** Opcode VEX.0F38 0xf7 (vex only). */
1212	FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1213	{
1214	IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1215	IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF);
1216	}
1217
1218
1219	/** Opcode VEX.66.0F38 0xf7 (vex only). */
1220	FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1221	{
1222	IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1223	IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1224	}
1225
1226
1227	/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1228	FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1229	{
1230	IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1231	IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1232	}
1233
1234
1235	/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1236	FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1237	{
1238	IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1239	IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1240	}
1241
1242	/* Opcode VEX.0F38 0xf8 - invalid. */
1243	/* Opcode VEX.66.0F38 0xf8 - invalid. */
1244	/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1245	/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1246
1247	/* Opcode VEX.0F38 0xf9 - invalid. */
1248	/* Opcode VEX.66.0F38 0xf9 - invalid. */
1249	/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1250	/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1251
1252	/* Opcode VEX.0F38 0xfa - invalid. */
1253	/* Opcode VEX.66.0F38 0xfa - invalid. */
1254	/* Opcode VEX.F3.0F38 0xfa - invalid. */
1255	/* Opcode VEX.F2.0F38 0xfa - invalid. */
1256
1257	/* Opcode VEX.0F38 0xfb - invalid. */
1258	/* Opcode VEX.66.0F38 0xfb - invalid. */
1259	/* Opcode VEX.F3.0F38 0xfb - invalid. */
1260	/* Opcode VEX.F2.0F38 0xfb - invalid. */
1261
1262	/* Opcode VEX.0F38 0xfc - invalid. */
1263	/* Opcode VEX.66.0F38 0xfc - invalid. */
1264	/* Opcode VEX.F3.0F38 0xfc - invalid. */
1265	/* Opcode VEX.F2.0F38 0xfc - invalid. */
1266
1267	/* Opcode VEX.0F38 0xfd - invalid. */
1268	/* Opcode VEX.66.0F38 0xfd - invalid. */
1269	/* Opcode VEX.F3.0F38 0xfd - invalid. */
1270	/* Opcode VEX.F2.0F38 0xfd - invalid. */
1271
1272	/* Opcode VEX.0F38 0xfe - invalid. */
1273	/* Opcode VEX.66.0F38 0xfe - invalid. */
1274	/* Opcode VEX.F3.0F38 0xfe - invalid. */
1275	/* Opcode VEX.F2.0F38 0xfe - invalid. */
1276
1277	/* Opcode VEX.0F38 0xff - invalid. */
1278	/* Opcode VEX.66.0F38 0xff - invalid. */
1279	/* Opcode VEX.F3.0F38 0xff - invalid. */
1280	/* Opcode VEX.F2.0F38 0xff - invalid. */
1281
1282
1283	/**
1284	* VEX opcode map \#2.
1285	*
1286	* @sa g_apfnThreeByte0f38
1287	*/
1288	IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1289	{
1290	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1291	/* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1292	/* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1293	/* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1294	/* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1295	/* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1296	/* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1297	/* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1298	/* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1299	/* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1300	/* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1301	/* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1302	/* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1303	/* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1304	/* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1305	/* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1306	/* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1307
1308	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1309	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1310	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1311	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1312	/* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1313	/* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1314	/* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1315	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1316	/* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1317	/* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1318	/* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1319	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1320	/* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1321	/* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1322	/* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1323	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1324
1325	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1326	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1327	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1328	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1329	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1330	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1331	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1332	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1333	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1334	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1335	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1336	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1337	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1338	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1339	/* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1340	/* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1341
1342	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1343	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1344	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1345	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1346	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1347	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1348	/* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1349	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1350	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1351	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1352	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1353	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1354	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1355	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1356	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1357	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1358
1359	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1360	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1361	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1362	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1363	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1364	/* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1365	/* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1366	/* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1367	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1368	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1369	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1370	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1371	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1372	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1373	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1374	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1375
1376	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1377	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1378	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1379	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1380	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1381	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1382	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1383	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1384	/* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1385	/* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1386	/* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1387	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1388	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1389	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1390	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1391	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1392
1393	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1394	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1395	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1396	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1397	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1398	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1399	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1400	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1401	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1402	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1403	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1404	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1405	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1406	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1407	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1408	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1409
1410	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1411	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1412	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1413	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1414	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1415	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1416	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1417	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1418	/* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1419	/* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1420	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1421	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1422	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1423	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1424	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1425	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1426
1427	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1428	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1429	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1430	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1431	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1432	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1433	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1434	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1435	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1436	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1437	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1438	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1439	/* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1440	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1441	/* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1442	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1443
1444	/* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1445	/* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1446	/* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1447	/* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1448	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1449	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1450	/* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1451	/* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1452	/* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1453	/* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1454	/* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1455	/* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1456	/* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1457	/* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1458	/* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1459	/* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1460
1461	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1462	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1463	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1464	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1465	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1466	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1467	/* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1468	/* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1469	/* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1470	/* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1471	/* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1472	/* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1473	/* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1474	/* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1475	/* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1476	/* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1477
1478	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1479	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1480	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1481	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1482	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1483	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1484	/* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1485	/* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1486	/* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1487	/* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1488	/* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1489	/* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1490	/* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1491	/* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1492	/* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1493	/* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1494
1495	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1496	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1497	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1498	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1499	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1500	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1501	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1502	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1503	/* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1504	/* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1505	/* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1506	/* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1507	/* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1508	/* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1509	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1510	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1511
1512	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1513	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1514	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1515	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1516	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1517	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1518	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1519	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1520	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1521	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1522	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1523	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1524	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1525	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1526	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1527	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1528
1529	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1530	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1531	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1532	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1533	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1534	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1535	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1536	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1537	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1538	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1539	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1540	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1541	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1542	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1543	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1544	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1545
1546	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1547	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1548	/* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1549	/* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1550	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1551	/* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1552	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1553	/* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1554	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1555	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1556	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1557	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1558	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1559	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1560	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1561	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1562	};
1563	AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1564
1565	/** @} */
1566

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 95453

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