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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h@ 98506

最後變更 在這個檔案從98506是 98103,由 vboxsync 提交於 2 年 前

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1/* $Id: IEMAllInstructionsThree0f3a.cpp.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstructionsVexMap3.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.alldomusa.eu.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33 * @{
34 */
35
36/**
37 * Common worker for SSSE3 instructions on the forms:
38 * pxxx xmm1, xmm2/mem128, imm8
39 *
40 * Proper alignment of the 128-bit operand is enforced.
41 * Exceptions type 4. SSSE3 cpuid checks.
42 *
43 * @sa iemOpCommonSse41_FullFullImm8_To_Full
44 */
45FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
55 IEM_MC_BEGIN(3, 0);
56 IEM_MC_ARG(PRTUINT128U, puDst, 0);
57 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
59 IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
60 IEM_MC_PREPARE_SSE_USAGE();
61 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64 IEM_MC_ADVANCE_RIP_AND_FINISH();
65 IEM_MC_END();
66 }
67 else
68 {
69 /*
70 * Register, memory.
71 */
72 IEM_MC_BEGIN(3, 2);
73 IEM_MC_ARG(PRTUINT128U, puDst, 0);
74 IEM_MC_LOCAL(RTUINT128U, uSrc);
75 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
81 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
82 IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
83 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85 IEM_MC_PREPARE_SSE_USAGE();
86 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89 IEM_MC_ADVANCE_RIP_AND_FINISH();
90 IEM_MC_END();
91 }
92}
93
94
95/**
96 * Common worker for SSE 4.1 instructions on the forms:
97 * pxxx xmm1, xmm2/mem128, imm8
98 *
99 * Proper alignment of the 128-bit operand is enforced.
100 * No SIMD exceptions. SSE 4.1 cpuid checks.
101 *
102 * @sa iemOpCommonSsse3_FullFullImm8_To_Full
103 */
104FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105{
106 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107 if (IEM_IS_MODRM_REG_MODE(bRm))
108 {
109 /*
110 * XMM, XMM, imm8
111 */
112 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
114 IEM_MC_BEGIN(3, 0);
115 IEM_MC_ARG(PRTUINT128U, puDst, 0);
116 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
118 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
119 IEM_MC_PREPARE_SSE_USAGE();
120 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123 IEM_MC_ADVANCE_RIP_AND_FINISH();
124 IEM_MC_END();
125 }
126 else
127 {
128 /*
129 * XMM, [mem128], imm8.
130 */
131 IEM_MC_BEGIN(3, 2);
132 IEM_MC_ARG(PRTUINT128U, puDst, 0);
133 IEM_MC_LOCAL(RTUINT128U, uSrc);
134 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
140 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
141 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
142 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144 IEM_MC_PREPARE_SSE_USAGE();
145 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148 IEM_MC_ADVANCE_RIP_AND_FINISH();
149 IEM_MC_END();
150 }
151}
152
153
154/**
155 * Common worker for SSE 4.1 instructions of the form:
156 * xxx xmm1, xmm2/mem128, imm8
157 *
158 * Proper alignment of the 128-bit operand is enforced.
159 * MXCSR is used as input and output.
160 * Exceptions type 4. SSE 4.1 cpuid checks.
161 *
162 * @sa iemOpCommonSse41_FullFullImm8_To_Full
163 */
164FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullFullImm8_To_Full, FNIEMAIMPLMXCSRF2XMMIMM8, pfnU128)
165{
166 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167 if (IEM_IS_MODRM_REG_MODE(bRm))
168 {
169 /*
170 * XMM, XMM, imm8.
171 */
172 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
174 IEM_MC_BEGIN(4, 2);
175 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
176 IEM_MC_LOCAL(X86XMMREG, Dst);
177 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
178 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
179 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
180 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
181 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
182 IEM_MC_PREPARE_SSE_USAGE();
183 IEM_MC_REF_MXCSR(pfMxcsr);
184 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
185 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
186 IEM_MC_CALL_VOID_AIMPL_4(pfnU128, pfMxcsr, pDst, pSrc, bImmArg);
187 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
188 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
189
190 IEM_MC_ADVANCE_RIP_AND_FINISH();
191 IEM_MC_END();
192 }
193 else
194 {
195 /*
196 * XMM, [mem128], imm8.
197 */
198 IEM_MC_BEGIN(4, 3);
199 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
200 IEM_MC_LOCAL(X86XMMREG, Dst);
201 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
202 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
203 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
204 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
205
206 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
207 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
208 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
209 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
210 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
211 IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
212
213 IEM_MC_PREPARE_SSE_USAGE();
214 IEM_MC_REF_MXCSR(pfMxcsr);
215 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
216 IEM_MC_CALL_VOID_AIMPL_4(pfnU128, pfMxcsr, pDst, pSrc, bImmArg);
217 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
218 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
219
220 IEM_MC_ADVANCE_RIP_AND_FINISH();
221 IEM_MC_END();
222 }
223}
224
225
226/**
227 * Common worker for SSE-style AES-NI instructions of the form:
228 * aesxxx xmm1, xmm2/mem128, imm8
229 *
230 * Proper alignment of the 128-bit operand is enforced.
231 * Exceptions type 4. AES-NI cpuid checks.
232 *
233 * @sa iemOpCommonSsse3_FullFullImm8_To_Full
234 * @sa iemOpCommonSse41_FullFullImm8_To_Full
235 */
236FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
237{
238 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
239 if (IEM_IS_MODRM_REG_MODE(bRm))
240 {
241 /*
242 * Register, register.
243 */
244 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
245 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
246 IEM_MC_BEGIN(3, 0);
247 IEM_MC_ARG(PRTUINT128U, puDst, 0);
248 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
249 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
250 IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
251 IEM_MC_PREPARE_SSE_USAGE();
252 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
253 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
254 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
255 IEM_MC_ADVANCE_RIP_AND_FINISH();
256 IEM_MC_END();
257 }
258 else
259 {
260 /*
261 * Register, memory.
262 */
263 IEM_MC_BEGIN(3, 2);
264 IEM_MC_ARG(PRTUINT128U, puDst, 0);
265 IEM_MC_LOCAL(RTUINT128U, uSrc);
266 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
267 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
268
269 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
270 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
271 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
272 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
273 IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
274 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
275
276 IEM_MC_PREPARE_SSE_USAGE();
277 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
278 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
279
280 IEM_MC_ADVANCE_RIP_AND_FINISH();
281 IEM_MC_END();
282 }
283}
284
285
286/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
287/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
288/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
289/* Opcode 0x66 0x0f 0x03 - invalid */
290/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
291/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
292/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
293/* Opcode 0x66 0x0f 0x07 - invalid */
294/** Opcode 0x66 0x0f 0x08. */
295FNIEMOP_DEF(iemOp_roundps_Vx_Wx_Ib)
296{
297 IEMOP_MNEMONIC3(RMI, ROUNDPS, roundps, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
298 return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
299 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback));
300}
301
302
303/** Opcode 0x66 0x0f 0x09. */
304FNIEMOP_DEF(iemOp_roundpd_Vx_Wx_Ib)
305{
306 IEMOP_MNEMONIC3(RMI, ROUNDPD, roundpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
307 return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
308 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback));
309}
310
311
312/** Opcode 0x66 0x0f 0x0a. */
313FNIEMOP_DEF(iemOp_roundss_Vss_Wss_Ib)
314{
315 /* The instruction form is very similar to CMPSS. */
316 IEMOP_MNEMONIC3(RMI, ROUNDSS, roundss, Vss, Wss, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
317
318 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
319 if (IEM_IS_MODRM_REG_MODE(bRm))
320 {
321 /*
322 * XMM32, XMM32.
323 */
324 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
325 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
326 IEM_MC_BEGIN(4, 2);
327 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
328 IEM_MC_LOCAL(X86XMMREG, Dst);
329 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
330 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
331 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
332 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
333 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
334 IEM_MC_PREPARE_SSE_USAGE();
335 IEM_MC_REF_MXCSR(pfMxcsr);
336 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
337 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
338 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundss_u128, pfMxcsr, pDst, pSrc, bImmArg);
339 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
340 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
341
342 IEM_MC_ADVANCE_RIP_AND_FINISH();
343 IEM_MC_END();
344 }
345 else
346 {
347 /*
348 * XMM32, [mem32].
349 */
350 IEM_MC_BEGIN(4, 3);
351 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
352 IEM_MC_LOCAL(X86XMMREG, Dst);
353 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
354 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
355 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
356 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
357
358 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
359 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
360 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
361 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
362 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
363 IEM_MC_FETCH_MEM_XMM_U32(Src.uSrc2, 0 /*a_iDword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
364
365 IEM_MC_PREPARE_SSE_USAGE();
366 IEM_MC_REF_MXCSR(pfMxcsr);
367 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
368 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundss_u128, pfMxcsr, pDst, pSrc, bImmArg);
369 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
370 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
371
372 IEM_MC_ADVANCE_RIP_AND_FINISH();
373 IEM_MC_END();
374 }
375}
376
377/** Opcode 0x66 0x0f 0x0b. */
378FNIEMOP_DEF(iemOp_roundsd_Vsd_Wsd_Ib)
379{
380 /* The instruction form is very similar to CMPSD. */
381 IEMOP_MNEMONIC3(RMI, ROUNDSD, roundsd, Vsd, Wsd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
382
383 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
384 if (IEM_IS_MODRM_REG_MODE(bRm))
385 {
386 /*
387 * XMM64, XMM64, imm8.
388 */
389 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
390 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
391 IEM_MC_BEGIN(4, 2);
392 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
393 IEM_MC_LOCAL(X86XMMREG, Dst);
394 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
395 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
396 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
397 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
398 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
399 IEM_MC_PREPARE_SSE_USAGE();
400 IEM_MC_REF_MXCSR(pfMxcsr);
401 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
402 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
403 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundsd_u128, pfMxcsr, pDst, pSrc, bImmArg);
404 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
405 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
406
407 IEM_MC_ADVANCE_RIP_AND_FINISH();
408 IEM_MC_END();
409 }
410 else
411 {
412 /*
413 * XMM64, [mem64], imm8.
414 */
415 IEM_MC_BEGIN(4, 3);
416 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
417 IEM_MC_LOCAL(X86XMMREG, Dst);
418 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
419 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
420 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
421 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
422
423 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
424 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
425 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
426 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
427 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
428 IEM_MC_FETCH_MEM_XMM_U64(Src.uSrc2, 0 /*a_iQword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
429
430 IEM_MC_PREPARE_SSE_USAGE();
431 IEM_MC_REF_MXCSR(pfMxcsr);
432 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
433 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundsd_u128, pfMxcsr, pDst, pSrc, bImmArg);
434 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
435 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
436
437 IEM_MC_ADVANCE_RIP_AND_FINISH();
438 IEM_MC_END();
439 }
440}
441
442
443/** Opcode 0x66 0x0f 0x0c. */
444FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
445{
446 IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
447 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
448 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
449}
450
451
452/** Opcode 0x66 0x0f 0x0d. */
453FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
454{
455 IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
456 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
457 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
458}
459
460
461/** Opcode 0x66 0x0f 0x0e. */
462FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
463{
464 IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
465 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
466 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
467}
468
469
470/** Opcode 0x0f 0x0f. */
471FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
472{
473 IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
474 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
475 if (IEM_IS_MODRM_REG_MODE(bRm))
476 {
477 /*
478 * Register, register.
479 */
480 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
481 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
482 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
483 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
484 IEM_MC_BEGIN(3, 0);
485 IEM_MC_ARG(uint64_t *, pDst, 0);
486 IEM_MC_ARG(uint64_t, uSrc, 1);
487 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
488 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
489 IEM_MC_PREPARE_FPU_USAGE();
490 IEM_MC_FPU_TO_MMX_MODE();
491 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
492 IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
493 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
494 pDst, uSrc, bImmArg);
495 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
496 IEM_MC_ADVANCE_RIP_AND_FINISH();
497 IEM_MC_END();
498 }
499 else
500 {
501 /*
502 * Register, memory.
503 */
504 IEM_MC_BEGIN(3, 1);
505 IEM_MC_ARG(uint64_t *, pDst, 0);
506 IEM_MC_ARG(uint64_t, uSrc, 1);
507 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
508
509 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
510 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
511 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
512 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
513 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
514 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
515
516 IEM_MC_PREPARE_FPU_USAGE();
517 IEM_MC_FPU_TO_MMX_MODE();
518 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
519 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
520 pDst, uSrc, bImmArg);
521 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
522
523 IEM_MC_ADVANCE_RIP_AND_FINISH();
524 IEM_MC_END();
525 }
526}
527
528
529/** Opcode 0x66 0x0f 0x0f. */
530FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
531{
532 IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
533 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
534 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
535}
536
537
538/* Opcode 0x66 0x0f 0x10 - invalid */
539/* Opcode 0x66 0x0f 0x11 - invalid */
540/* Opcode 0x66 0x0f 0x12 - invalid */
541/* Opcode 0x66 0x0f 0x13 - invalid */
542
543
544/** Opcode 0x66 0x0f 0x14. */
545FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib)
546{
547 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
548 IEMOP_MNEMONIC3(MRI, PEXTRB, pextrb, Ev, Vq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
549 if (IEM_IS_MODRM_REG_MODE(bRm))
550 {
551 /*
552 * greg32, XMM.
553 */
554 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
555 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
556 IEM_MC_BEGIN(0, 1);
557 IEM_MC_LOCAL(uint8_t, uValue);
558 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
559 IEM_MC_PREPARE_SSE_USAGE();
560 IEM_MC_AND_LOCAL_U8(bImm, 15);
561 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iByte*/);
562 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
563 IEM_MC_ADVANCE_RIP_AND_FINISH();
564 IEM_MC_END();
565 }
566 else
567 {
568 /*
569 * [mem8], XMM.
570 */
571 IEM_MC_BEGIN(0, 2);
572 IEM_MC_LOCAL(uint8_t, uValue);
573 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
574
575 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
576 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
577 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
578 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
579 IEM_MC_PREPARE_SSE_USAGE();
580
581 IEM_MC_AND_LOCAL_U8(bImm, 15);
582 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iByte*/);
583 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
584 IEM_MC_ADVANCE_RIP_AND_FINISH();
585 IEM_MC_END();
586 }
587}
588
589
590/** Opcode 0x66 0x0f 0x15. */
591FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib)
592{
593 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
594 IEMOP_MNEMONIC3(MRI, PEXTRW, pextrw, Ev, Vq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
595 if (IEM_IS_MODRM_REG_MODE(bRm))
596 {
597 /*
598 * greg32, XMM.
599 */
600 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
601 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
602 IEM_MC_BEGIN(0, 1);
603 IEM_MC_LOCAL(uint16_t, uValue);
604 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
605 IEM_MC_PREPARE_SSE_USAGE();
606 IEM_MC_AND_LOCAL_U8(bImm, 7);
607 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iWord*/);
608 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
609 IEM_MC_ADVANCE_RIP_AND_FINISH();
610 IEM_MC_END();
611 }
612 else
613 {
614 /*
615 * [mem16], XMM.
616 */
617 IEM_MC_BEGIN(0, 2);
618 IEM_MC_LOCAL(uint16_t, uValue);
619 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
620
621 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
622 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
623 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
624 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
625 IEM_MC_PREPARE_SSE_USAGE();
626
627 IEM_MC_AND_LOCAL_U8(bImm, 7);
628 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iWord*/);
629 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
630 IEM_MC_ADVANCE_RIP_AND_FINISH();
631 IEM_MC_END();
632 }
633}
634
635
636FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib)
637{
638 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
639 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
640 {
641 /**
642 * @opcode 0x16
643 * @opcodesub rex.w=1
644 * @oppfx 0x66
645 * @opcpuid sse
646 */
647 IEMOP_MNEMONIC3(MRI, PEXTRQ, pextrq, Ev, Vq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
648 if (IEM_IS_MODRM_REG_MODE(bRm))
649 {
650 /*
651 * greg64, XMM.
652 */
653 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
654 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
655 IEM_MC_BEGIN(0, 1);
656 IEM_MC_LOCAL(uint64_t, uSrc);
657 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
658 IEM_MC_PREPARE_SSE_USAGE();
659 IEM_MC_AND_LOCAL_U8(bImm, 1);
660 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iQword*/);
661 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
662 IEM_MC_ADVANCE_RIP_AND_FINISH();
663 IEM_MC_END();
664 }
665 else
666 {
667 /*
668 * [mem64], XMM.
669 */
670 IEM_MC_BEGIN(0, 2);
671 IEM_MC_LOCAL(uint64_t, uSrc);
672 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
673
674 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
675 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
676 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
677 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
678 IEM_MC_PREPARE_SSE_USAGE();
679
680 IEM_MC_AND_LOCAL_U8(bImm, 1);
681 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iQword*/);
682 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
683 IEM_MC_ADVANCE_RIP_AND_FINISH();
684 IEM_MC_END();
685 }
686 }
687 else
688 {
689 /**
690 * @opdone
691 * @opcode 0x16
692 * @opcodesub rex.w=0
693 * @oppfx 0x66
694 * @opcpuid sse
695 */
696 IEMOP_MNEMONIC3(MRI, PEXTRD, pextrd, Ey, Vd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
697 if (IEM_IS_MODRM_REG_MODE(bRm))
698 {
699 /*
700 * greg32, XMM.
701 */
702 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
703 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
704 IEM_MC_BEGIN(0, 1);
705 IEM_MC_LOCAL(uint32_t, uSrc);
706 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
707 IEM_MC_PREPARE_SSE_USAGE();
708 IEM_MC_AND_LOCAL_U8(bImm, 3);
709 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iDword*/);
710 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
711 IEM_MC_ADVANCE_RIP_AND_FINISH();
712 IEM_MC_END();
713 }
714 else
715 {
716 /*
717 * [mem32], XMM.
718 */
719 IEM_MC_BEGIN(0, 2);
720 IEM_MC_LOCAL(uint32_t, uSrc);
721 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
722
723 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
724 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
725 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
726 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
727 IEM_MC_PREPARE_SSE_USAGE();
728 IEM_MC_AND_LOCAL_U8(bImm, 3);
729 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iDword*/);
730 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
731 IEM_MC_ADVANCE_RIP_AND_FINISH();
732 IEM_MC_END();
733 }
734 }
735}
736
737
738/** Opcode 0x66 0x0f 0x17. */
739FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib)
740{
741 IEMOP_MNEMONIC3(MRI, EXTRACTPS, extractps, Ed, Vdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
742 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
743 if (IEM_IS_MODRM_REG_MODE(bRm))
744 {
745 /*
746 * greg32, XMM.
747 */
748 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
749 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
750 IEM_MC_BEGIN(0, 1);
751 IEM_MC_LOCAL(uint32_t, uSrc);
752 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
753 IEM_MC_PREPARE_SSE_USAGE();
754 IEM_MC_AND_LOCAL_U8(bImm, 3);
755 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iDword*/);
756 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
757 IEM_MC_ADVANCE_RIP_AND_FINISH();
758 IEM_MC_END();
759 }
760 else
761 {
762 /*
763 * [mem32], XMM.
764 */
765 IEM_MC_BEGIN(0, 2);
766 IEM_MC_LOCAL(uint32_t, uSrc);
767 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
768
769 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
770 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
771 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
772 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
773 IEM_MC_PREPARE_SSE_USAGE();
774 IEM_MC_AND_LOCAL_U8(bImm, 3);
775 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iDword*/);
776 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
777 IEM_MC_ADVANCE_RIP_AND_FINISH();
778 IEM_MC_END();
779 }
780}
781
782
783/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
784/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
785/* Opcode 0x66 0x0f 0x1a - invalid */
786/* Opcode 0x66 0x0f 0x1b - invalid */
787/* Opcode 0x66 0x0f 0x1c - invalid */
788/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
789/* Opcode 0x66 0x0f 0x1e - invalid */
790/* Opcode 0x66 0x0f 0x1f - invalid */
791
792
793/** Opcode 0x66 0x0f 0x20. */
794FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib)
795{
796 IEMOP_MNEMONIC3(RMI, PINSRB, pinsrb, Vd, Ey, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
797 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
798 if (IEM_IS_MODRM_REG_MODE(bRm))
799 {
800 /*
801 * XMM, greg32.
802 */
803 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
804 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
805 IEM_MC_BEGIN(0, 1);
806 IEM_MC_LOCAL(uint8_t, uSrc);
807 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
808 IEM_MC_PREPARE_SSE_USAGE();
809 IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
810 IEM_MC_AND_LOCAL_U8(bImm, 15);
811 IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iByte*/, uSrc);
812 IEM_MC_ADVANCE_RIP_AND_FINISH();
813 IEM_MC_END();
814 }
815 else
816 {
817 /*
818 * XMM, [mem8].
819 */
820 IEM_MC_BEGIN(0, 2);
821 IEM_MC_LOCAL(uint8_t, uSrc);
822 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
823
824 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
825 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
826 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
827 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
828 IEM_MC_PREPARE_SSE_USAGE();
829
830 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
831 IEM_MC_AND_LOCAL_U8(bImm, 15);
832 IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iByte*/, uSrc);
833 IEM_MC_ADVANCE_RIP_AND_FINISH();
834 IEM_MC_END();
835 }
836}
837
838/** Opcode 0x66 0x0f 0x21, */
839FNIEMOP_DEF(iemOp_insertps_Vdq_UdqMd_Ib)
840{
841 IEMOP_MNEMONIC3(RMI, INSERTPS, insertps, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0); /// @todo
842 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
843 if (IEM_IS_MODRM_REG_MODE(bRm))
844 {
845 /*
846 * XMM, XMM.
847 */
848 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
849 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
850 IEM_MC_BEGIN(0, 3);
851 IEM_MC_LOCAL(uint32_t, uSrc);
852 IEM_MC_LOCAL(uint8_t, uSrcSel);
853 IEM_MC_LOCAL(uint8_t, uDstSel);
854 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
855 IEM_MC_PREPARE_SSE_USAGE();
856 IEM_MC_ASSIGN(uSrcSel, bImm);
857 IEM_MC_SHR_LOCAL_U8(uSrcSel, 6);
858 IEM_MC_AND_LOCAL_U8(uSrcSel, 3);
859 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), uSrcSel);
860 IEM_MC_ASSIGN(uDstSel, bImm);
861 IEM_MC_SHR_LOCAL_U8(uDstSel, 4);
862 IEM_MC_AND_LOCAL_U8(uDstSel, 3);
863 IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
864 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uDstSel, uSrc);
865 IEM_MC_ADVANCE_RIP_AND_FINISH();
866 IEM_MC_END();
867 }
868 else
869 {
870 /*
871 * XMM, [mem32].
872 */
873 IEM_MC_BEGIN(0, 3);
874 IEM_MC_LOCAL(uint32_t, uSrc);
875 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
876 IEM_MC_LOCAL(uint8_t, uDstSel);
877
878 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
879 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
880 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
881 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
882 IEM_MC_PREPARE_SSE_USAGE();
883
884 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
885 IEM_MC_ASSIGN(uDstSel, bImm);
886 IEM_MC_SHR_LOCAL_U8(uDstSel, 4);
887 IEM_MC_AND_LOCAL_U8(uDstSel, 3);
888 IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
889 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uDstSel, uSrc);
890 IEM_MC_ADVANCE_RIP_AND_FINISH();
891 IEM_MC_END();
892 }
893}
894
895FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
896{
897 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
898 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
899 {
900 /**
901 * @opcode 0x22
902 * @opcodesub rex.w=1
903 * @oppfx 0x66
904 * @opcpuid sse
905 */
906 IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
907 if (IEM_IS_MODRM_REG_MODE(bRm))
908 {
909 /*
910 * XMM, greg64.
911 */
912 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
913 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
914 IEM_MC_BEGIN(0, 1);
915 IEM_MC_LOCAL(uint64_t, uSrc);
916 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
917 IEM_MC_PREPARE_SSE_USAGE();
918 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
919 IEM_MC_AND_LOCAL_U8(bImm, 1);
920 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iQword*/, uSrc);
921 IEM_MC_ADVANCE_RIP_AND_FINISH();
922 IEM_MC_END();
923 }
924 else
925 {
926 /*
927 * XMM, [mem64].
928 */
929 IEM_MC_BEGIN(0, 2);
930 IEM_MC_LOCAL(uint64_t, uSrc);
931 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
932
933 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
934 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
935 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
936 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
937 IEM_MC_PREPARE_SSE_USAGE();
938
939 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
940 IEM_MC_AND_LOCAL_U8(bImm, 1);
941 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iQword*/, uSrc);
942 IEM_MC_ADVANCE_RIP_AND_FINISH();
943 IEM_MC_END();
944 }
945 }
946 else
947 {
948 /**
949 * @opdone
950 * @opcode 0x22
951 * @opcodesub rex.w=0
952 * @oppfx 0x66
953 * @opcpuid sse
954 */
955 IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
956 if (IEM_IS_MODRM_REG_MODE(bRm))
957 {
958 /*
959 * XMM, greg32.
960 */
961 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
962 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
963 IEM_MC_BEGIN(0, 1);
964 IEM_MC_LOCAL(uint32_t, uSrc);
965 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
966 IEM_MC_PREPARE_SSE_USAGE();
967 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
968 IEM_MC_AND_LOCAL_U8(bImm, 3);
969 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iDword*/, uSrc);
970 IEM_MC_ADVANCE_RIP_AND_FINISH();
971 IEM_MC_END();
972 }
973 else
974 {
975 /*
976 * XMM, [mem32].
977 */
978 IEM_MC_BEGIN(0, 2);
979 IEM_MC_LOCAL(uint32_t, uSrc);
980 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
981
982 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
983 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
984 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
985 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
986 IEM_MC_PREPARE_SSE_USAGE();
987
988 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
989 IEM_MC_AND_LOCAL_U8(bImm, 3);
990 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /*a_iDword*/, uSrc);
991 IEM_MC_ADVANCE_RIP_AND_FINISH();
992 IEM_MC_END();
993 }
994 }
995}
996
997
998/* Opcode 0x66 0x0f 0x23 - invalid */
999/* Opcode 0x66 0x0f 0x24 - invalid */
1000/* Opcode 0x66 0x0f 0x25 - invalid */
1001/* Opcode 0x66 0x0f 0x26 - invalid */
1002/* Opcode 0x66 0x0f 0x27 - invalid */
1003/* Opcode 0x66 0x0f 0x28 - invalid */
1004/* Opcode 0x66 0x0f 0x29 - invalid */
1005/* Opcode 0x66 0x0f 0x2a - invalid */
1006/* Opcode 0x66 0x0f 0x2b - invalid */
1007/* Opcode 0x66 0x0f 0x2c - invalid */
1008/* Opcode 0x66 0x0f 0x2d - invalid */
1009/* Opcode 0x66 0x0f 0x2e - invalid */
1010/* Opcode 0x66 0x0f 0x2f - invalid */
1011
1012
1013/* Opcode 0x66 0x0f 0x30 - invalid */
1014/* Opcode 0x66 0x0f 0x31 - invalid */
1015/* Opcode 0x66 0x0f 0x32 - invalid */
1016/* Opcode 0x66 0x0f 0x33 - invalid */
1017/* Opcode 0x66 0x0f 0x34 - invalid */
1018/* Opcode 0x66 0x0f 0x35 - invalid */
1019/* Opcode 0x66 0x0f 0x36 - invalid */
1020/* Opcode 0x66 0x0f 0x37 - invalid */
1021/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
1022/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
1023/* Opcode 0x66 0x0f 0x3a - invalid */
1024/* Opcode 0x66 0x0f 0x3b - invalid */
1025/* Opcode 0x66 0x0f 0x3c - invalid */
1026/* Opcode 0x66 0x0f 0x3d - invalid */
1027/* Opcode 0x66 0x0f 0x3e - invalid */
1028/* Opcode 0x66 0x0f 0x3f - invalid */
1029
1030
1031/** Opcode 0x66 0x0f 0x40. */
1032FNIEMOP_STUB(iemOp_dpps_Vx_Wx_Ib);
1033/** Opcode 0x66 0x0f 0x41, */
1034FNIEMOP_STUB(iemOp_dppd_Vdq_Wdq_Ib);
1035/** Opcode 0x66 0x0f 0x42. */
1036FNIEMOP_STUB(iemOp_mpsadbw_Vx_Wx_Ib);
1037/* Opcode 0x66 0x0f 0x43 - invalid */
1038
1039
1040/** Opcode 0x66 0x0f 0x44. */
1041FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
1042{
1043 IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
1044
1045 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1046 if (IEM_IS_MODRM_REG_MODE(bRm))
1047 {
1048 /*
1049 * Register, register.
1050 */
1051 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1052 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1053 IEM_MC_BEGIN(3, 0);
1054 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1055 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1056 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
1057 IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
1058 IEM_MC_PREPARE_SSE_USAGE();
1059 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1060 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1061 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1062 iemAImpl_pclmulqdq_u128,
1063 iemAImpl_pclmulqdq_u128_fallback),
1064 puDst, puSrc, bImmArg);
1065 IEM_MC_ADVANCE_RIP_AND_FINISH();
1066 IEM_MC_END();
1067 }
1068 else
1069 {
1070 /*
1071 * Register, memory.
1072 */
1073 IEM_MC_BEGIN(3, 2);
1074 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1075 IEM_MC_LOCAL(RTUINT128U, uSrc);
1076 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1077 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1078
1079 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1080 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1081 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
1082 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1083 IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
1084 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1085
1086 IEM_MC_PREPARE_SSE_USAGE();
1087 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1088 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1089 iemAImpl_pclmulqdq_u128,
1090 iemAImpl_pclmulqdq_u128_fallback),
1091 puDst, puSrc, bImmArg);
1092
1093 IEM_MC_ADVANCE_RIP_AND_FINISH();
1094 IEM_MC_END();
1095 }
1096}
1097
1098
1099/* Opcode 0x66 0x0f 0x45 - invalid */
1100/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
1101/* Opcode 0x66 0x0f 0x47 - invalid */
1102/* Opcode 0x66 0x0f 0x48 - invalid */
1103/* Opcode 0x66 0x0f 0x49 - invalid */
1104/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
1105/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
1106/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
1107/* Opcode 0x66 0x0f 0x4d - invalid */
1108/* Opcode 0x66 0x0f 0x4e - invalid */
1109/* Opcode 0x66 0x0f 0x4f - invalid */
1110
1111
1112/* Opcode 0x66 0x0f 0x50 - invalid */
1113/* Opcode 0x66 0x0f 0x51 - invalid */
1114/* Opcode 0x66 0x0f 0x52 - invalid */
1115/* Opcode 0x66 0x0f 0x53 - invalid */
1116/* Opcode 0x66 0x0f 0x54 - invalid */
1117/* Opcode 0x66 0x0f 0x55 - invalid */
1118/* Opcode 0x66 0x0f 0x56 - invalid */
1119/* Opcode 0x66 0x0f 0x57 - invalid */
1120/* Opcode 0x66 0x0f 0x58 - invalid */
1121/* Opcode 0x66 0x0f 0x59 - invalid */
1122/* Opcode 0x66 0x0f 0x5a - invalid */
1123/* Opcode 0x66 0x0f 0x5b - invalid */
1124/* Opcode 0x66 0x0f 0x5c - invalid */
1125/* Opcode 0x66 0x0f 0x5d - invalid */
1126/* Opcode 0x66 0x0f 0x5e - invalid */
1127/* Opcode 0x66 0x0f 0x5f - invalid */
1128
1129
1130/** Opcode 0x66 0x0f 0x60. */
1131FNIEMOP_STUB(iemOp_pcmpestrm_Vdq_Wdq_Ib);
1132/** Opcode 0x66 0x0f 0x61, */
1133FNIEMOP_STUB(iemOp_pcmpestri_Vdq_Wdq_Ib);
1134/** Opcode 0x66 0x0f 0x62. */
1135FNIEMOP_STUB(iemOp_pcmpistrm_Vdq_Wdq_Ib);
1136
1137
1138/** Opcode 0x66 0x0f 0x63*/
1139FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
1140{
1141 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1142 if (IEM_IS_MODRM_REG_MODE(bRm))
1143 {
1144 /*
1145 * Register, register.
1146 */
1147 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1148 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1149 IEM_MC_BEGIN(4, 1);
1150 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1151 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1152 IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
1153 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
1154 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1155 IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1156 IEM_MC_PREPARE_SSE_USAGE();
1157 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1158 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1159 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1160 IEM_MC_REF_EFLAGS(pEFlags);
1161 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1162 iemAImpl_pcmpistri_u128,
1163 iemAImpl_pcmpistri_u128_fallback),
1164 pu32Ecx, pEFlags, pSrc, bImmArg);
1165 /** @todo testcase: High dword of RCX cleared? */
1166 IEM_MC_ADVANCE_RIP_AND_FINISH();
1167 IEM_MC_END();
1168 }
1169 else
1170 {
1171 /*
1172 * Register, memory.
1173 */
1174 IEM_MC_BEGIN(4, 3);
1175 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1176 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1177 IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
1178 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
1179 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1180
1181 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1182 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1183 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1184 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1185 IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1186 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1187
1188 IEM_MC_PREPARE_SSE_USAGE();
1189 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1190 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1191 IEM_MC_REF_EFLAGS(pEFlags);
1192 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1193 iemAImpl_pcmpistri_u128,
1194 iemAImpl_pcmpistri_u128_fallback),
1195 pu32Ecx, pEFlags, pSrc, bImmArg);
1196 /** @todo testcase: High dword of RCX cleared? */
1197 IEM_MC_ADVANCE_RIP_AND_FINISH();
1198 IEM_MC_END();
1199 }
1200}
1201
1202
1203/* Opcode 0x66 0x0f 0x64 - invalid */
1204/* Opcode 0x66 0x0f 0x65 - invalid */
1205/* Opcode 0x66 0x0f 0x66 - invalid */
1206/* Opcode 0x66 0x0f 0x67 - invalid */
1207/* Opcode 0x66 0x0f 0x68 - invalid */
1208/* Opcode 0x66 0x0f 0x69 - invalid */
1209/* Opcode 0x66 0x0f 0x6a - invalid */
1210/* Opcode 0x66 0x0f 0x6b - invalid */
1211/* Opcode 0x66 0x0f 0x6c - invalid */
1212/* Opcode 0x66 0x0f 0x6d - invalid */
1213/* Opcode 0x66 0x0f 0x6e - invalid */
1214/* Opcode 0x66 0x0f 0x6f - invalid */
1215
1216/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
1217
1218
1219/* Opcode 0x0f 0xc0 - invalid */
1220/* Opcode 0x0f 0xc1 - invalid */
1221/* Opcode 0x0f 0xc2 - invalid */
1222/* Opcode 0x0f 0xc3 - invalid */
1223/* Opcode 0x0f 0xc4 - invalid */
1224/* Opcode 0x0f 0xc5 - invalid */
1225/* Opcode 0x0f 0xc6 - invalid */
1226/* Opcode 0x0f 0xc7 - invalid */
1227/* Opcode 0x0f 0xc8 - invalid */
1228/* Opcode 0x0f 0xc9 - invalid */
1229/* Opcode 0x0f 0xca - invalid */
1230/* Opcode 0x0f 0xcb - invalid */
1231/* Opcode 0x0f 0xcc */
1232FNIEMOP_STUB(iemOp_sha1rnds4_Vdq_Wdq_Ib);
1233/* Opcode 0x0f 0xcd - invalid */
1234/* Opcode 0x0f 0xce - invalid */
1235/* Opcode 0x0f 0xcf - invalid */
1236
1237
1238/* Opcode 0x66 0x0f 0xd0 - invalid */
1239/* Opcode 0x66 0x0f 0xd1 - invalid */
1240/* Opcode 0x66 0x0f 0xd2 - invalid */
1241/* Opcode 0x66 0x0f 0xd3 - invalid */
1242/* Opcode 0x66 0x0f 0xd4 - invalid */
1243/* Opcode 0x66 0x0f 0xd5 - invalid */
1244/* Opcode 0x66 0x0f 0xd6 - invalid */
1245/* Opcode 0x66 0x0f 0xd7 - invalid */
1246/* Opcode 0x66 0x0f 0xd8 - invalid */
1247/* Opcode 0x66 0x0f 0xd9 - invalid */
1248/* Opcode 0x66 0x0f 0xda - invalid */
1249/* Opcode 0x66 0x0f 0xdb - invalid */
1250/* Opcode 0x66 0x0f 0xdc - invalid */
1251/* Opcode 0x66 0x0f 0xdd - invalid */
1252/* Opcode 0x66 0x0f 0xde - invalid */
1253
1254
1255/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
1256FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
1257{
1258 IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
1259 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
1260 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
1261}
1262
1263
1264/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
1265
1266
1267/**
1268 * Three byte opcode map, first two bytes are 0x0f 0x3a.
1269 * @sa g_apfnVexMap2
1270 */
1271IEM_STATIC const PFNIEMOP g_apfnThreeByte0f3a[] =
1272{
1273 /* no prefix, 066h prefix f3h prefix, f2h prefix */
1274 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1275 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1276 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1277 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1278 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1279 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1280 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1281 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1282 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1283 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1284 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1285 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1286 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1287 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1288 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1289 /* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1290
1291 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1292 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1293 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1294 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1295 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1296 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1297 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1298 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1299 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1300 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1301 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1302 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1303 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1304 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1305 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1306 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1307
1308 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1309 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1310 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1311 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1312 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1313 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1314 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1315 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1316 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1317 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1318 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1319 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1320 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1321 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1322 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1323 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1324
1325 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1326 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1327 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1328 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1329 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1330 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1331 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1332 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1333 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1334 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1335 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1336 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1337 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1338 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1339 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1340 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1341
1342 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1343 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1344 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1345 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1346 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1347 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1348 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1349 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1350 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1351 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1352 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1353 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1354 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1355 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1356 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1357 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1358
1359 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1360 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1361 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1362 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1363 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1364 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1365 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1366 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1367 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1368 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1369 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1370 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1371 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1372 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1373 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1374 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1375
1376 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1377 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1378 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1379 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1380 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1381 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1382 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1383 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1384 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1385 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1386 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1387 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1388 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1389 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1390 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1391 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1392
1393 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1394 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1395 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1396 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1397 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1398 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1399 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1400 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1401 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1402 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1403 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1404 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1405 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1406 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1407 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1408 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1409
1410 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1411 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1412 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1413 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1414 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1415 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1416 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1417 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1418 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1419 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1420 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1421 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1422 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1423 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1424 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1425 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1426
1427 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1428 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1429 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1430 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1431 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1432 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1433 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1434 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1435 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1436 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1437 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1438 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1439 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1440 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1441 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1442 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1443
1444 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1445 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1446 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1447 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1448 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1449 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1450 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1451 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1452 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1453 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1454 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1455 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1456 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1457 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1458 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1459 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1460
1461 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1462 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1463 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1464 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1465 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1466 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1467 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1468 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1469 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1470 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1471 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1472 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1473 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1474 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1475 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1476 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1477
1478 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1479 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1480 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1481 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1482 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1483 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1484 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1485 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1486 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1487 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1488 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1489 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1490 /* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1491 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1492 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1493 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1494
1495 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1496 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1497 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1498 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1499 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1500 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1501 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1502 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1503 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1504 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1505 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1506 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1507 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1508 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1509 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1510 /* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1511
1512 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1513 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1514 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1515 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1516 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1517 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1518 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1519 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1520 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1521 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1522 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1523 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1524 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1525 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1526 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1527 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1528
1529 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1530 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1531 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1532 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1533 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1534 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1535 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1536 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1537 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1538 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1539 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1540 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1541 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1542 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1543 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1544 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1545};
1546AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1547
1548/** @} */
1549
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