VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 99647

最後變更 在這個檔案從99647是 99369,由 vboxsync 提交於 2 年 前

VMM/IEM: @todo regarding nested VMX APIC page access handler management in IEM. bugref:10318
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 410.3 KB
行 
1/* $Id: IEMAllCImplVmxInstr.cpp 99369 2023-04-10 23:36:09Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.alldomusa.eu.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/dbgf.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/gim.h>
40#include <VBox/vmm/hm.h>
41#include <VBox/vmm/pgm.h>
42#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43# include <VBox/vmm/hmvmxinline.h>
44#endif
45#include <VBox/vmm/tm.h>
46#include "IEMInternal.h"
47#include <VBox/vmm/vmcc.h>
48#include <VBox/log.h>
49#include <VBox/err.h>
50#include <VBox/param.h>
51#include <VBox/disopcode-x86-amd64.h>
52#include <iprt/asm-math.h>
53#include <iprt/assert.h>
54#include <iprt/string.h>
55#include <iprt/x86.h>
56
57#include "IEMInline.h"
58
59
60/*********************************************************************************************************************************
61* Defined Constants And Macros *
62*********************************************************************************************************************************/
63#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
64/**
65 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
66 * relative offsets.
67 */
68# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
69# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
70# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
71# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
77# if 0
78# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
79# endif
80# else /* !IEM_WITH_CODE_TLB */
81# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
82 do \
83 { \
84 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
86 } while (0)
87
88# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
89
90# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
91 do \
92 { \
93 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
94 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
95 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
96 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
97 } while (0)
98
99# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
100 do \
101 { \
102 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
103 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
104 } while (0)
105
106# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107 do \
108 { \
109 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
110 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
111 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
112 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
113 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
114 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
115 } while (0)
116
117# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
118 do \
119 { \
120 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
121 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
122 } while (0)
123
124# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
125 do \
126 { \
127 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
128 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
129 } while (0)
130
131# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
132 do \
133 { \
134 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
135 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
136 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
137 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
138 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
139 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
140 } while (0)
141# endif /* !IEM_WITH_CODE_TLB */
142
143/** Check for VMX instructions requiring to be in VMX operation.
144 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
145# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
146 do \
147 { \
148 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
149 { /* likely */ } \
150 else \
151 { \
152 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
153 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
154 return iemRaiseUndefinedOpcode(a_pVCpu); \
155 } \
156 } while (0)
157
158/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
159# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
160 do \
161 { \
162 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
163 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
164 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
165 return VERR_VMX_VMENTRY_FAILED; \
166 } while (0)
167
168/** Marks a VM-entry failure with an return code, diagnostic reason, logs and
169 * returns. */
170# define IEM_VMX_VMENTRY_FAILED_RET_2(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag, a_rc) \
171 do \
172 { \
173 LogRel(("%s: VM-entry failed! rc=%Rrc enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_rc), (a_VmxDiag), \
174 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
175 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
176 return VERR_VMX_VMENTRY_FAILED; \
177 } while (0)
178
179/** Marks a VM-exit failure with a diagnostic reason and logs. */
180# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
181 do \
182 { \
183 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
184 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
185 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
186 } while (0)
187
188/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
189# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
190 do \
191 { \
192 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
193 return VERR_VMX_VMEXIT_FAILED; \
194 } while (0)
195
196
197/*********************************************************************************************************************************
198* Global Variables *
199*********************************************************************************************************************************/
200/** @todo NSTVMX: The following VM-exit intercepts are pending:
201 * VMX_EXIT_IO_SMI
202 * VMX_EXIT_SMI
203 * VMX_EXIT_GETSEC
204 * VMX_EXIT_RSM
205 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
206 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
207 * VMX_EXIT_RDRAND
208 * VMX_EXIT_VMFUNC
209 * VMX_EXIT_ENCLS
210 * VMX_EXIT_RDSEED
211 * VMX_EXIT_PML_FULL
212 * VMX_EXIT_XSAVES
213 * VMX_EXIT_XRSTORS
214 */
215/**
216 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
217 *
218 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
219 * second dimension is the Index, see VMXVMCSFIELD.
220 */
221uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
222{
223 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
224 {
225 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
226 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
227 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
228 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u16HlatPrefixSize),
229 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
230 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
232 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
233 },
234 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
235 {
236 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
240 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
241 },
242 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
243 {
244 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
245 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
246 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
247 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
248 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
249 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
250 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
251 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
252 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
253 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
254 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
255 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
256 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
257 /* 34 */ UINT16_MAX
258 },
259 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
260 {
261 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
262 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
263 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
264 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
265 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
266 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
267 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
268 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
269 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
270 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
271 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
272 },
273 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
274 {
275 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
276 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
277 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
278 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
279 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
280 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
281 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
282 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
283 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
284 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
285 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
286 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
287 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
288 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
289 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
290 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
291 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
292 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
293 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
294 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
295 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
296 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
297 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
298 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
299 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
300 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
301 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
302 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap),
303 /* 28 */ UINT16_MAX,
304 /* 29 */ UINT16_MAX,
305 /* 30 */ UINT16_MAX,
306 /* 31 */ RT_UOFFSETOF(VMXVVMCS, u64PconfigExitBitmap),
307 /* 32 */ RT_UOFFSETOF(VMXVVMCS, u64HlatPtr),
308 /* 33 */ UINT16_MAX,
309 /* 34 */ RT_UOFFSETOF(VMXVVMCS, u64ExitCtls2)
310 },
311 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
312 {
313 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
314 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
315 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
316 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
317 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
318 /* 33-34*/ UINT16_MAX, UINT16_MAX
319 },
320 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
321 {
322 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
323 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
324 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
325 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
326 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
327 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
328 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
329 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
330 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
331 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
332 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
333 /* 11 */ UINT16_MAX,
334 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
335 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 21-28 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
337 /* 29-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
338 },
339 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
340 {
341 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
342 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
343 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
344 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
345 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
346 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
347 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
348 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
349 },
350 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
351 {
352 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
353 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
354 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
355 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
356 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
357 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
358 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
359 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
360 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
361 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
362 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
363 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
364 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
365 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
366 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
367 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
368 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
369 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
370 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
372 /* 34 */ UINT16_MAX
373 },
374 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
375 {
376 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
377 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
378 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
379 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
380 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
381 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
382 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
383 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
384 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
386 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
387 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
388 },
389 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
390 {
391 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
392 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
393 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
394 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
395 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
396 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
397 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
398 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
399 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
400 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
401 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
402 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
403 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
404 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
405 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
406 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
407 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
408 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
409 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
410 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
411 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
412 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
413 /* 22 */ UINT16_MAX,
414 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
415 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
416 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
417 },
418 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
419 {
420 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
421 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
422 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
423 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
424 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
425 /* 33-34 */ UINT16_MAX, UINT16_MAX
426 },
427 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
428 {
429 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
430 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
431 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
432 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
433 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
434 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
435 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
436 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
437 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
439 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
440 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
441 },
442 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
443 {
444 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
445 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
446 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
447 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
448 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
449 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
450 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
451 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 22-29 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
453 /* 30-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
454 },
455 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
456 {
457 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
458 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
459 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
460 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
461 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
462 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
463 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
464 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
465 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
466 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
467 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
468 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
469 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
470 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
471 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
472 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
473 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
474 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
475 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
476 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
477 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
478 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
479 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
480 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
481 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
482 },
483 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
484 {
485 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
486 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
487 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
488 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
489 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
490 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
491 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
492 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
493 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
494 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
495 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
496 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
497 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
498 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
499 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
500 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
501 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
502 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
503 }
504};
505
506
507/**
508 * Gets a host selector from the VMCS.
509 *
510 * @param pVmcs Pointer to the virtual VMCS.
511 * @param iSelReg The index of the segment register (X86_SREG_XXX).
512 */
513DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
514{
515 Assert(iSegReg < X86_SREG_COUNT);
516 RTSEL HostSel;
517 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
518 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
519 uint8_t const uWidthType = (uWidth << 2) | uType;
520 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
521 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
522 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
523 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
524 uint8_t const *pbField = pbVmcs + offField;
525 HostSel = *(uint16_t *)pbField;
526 return HostSel;
527}
528
529
530/**
531 * Sets a guest segment register in the VMCS.
532 *
533 * @param pVmcs Pointer to the virtual VMCS.
534 * @param iSegReg The index of the segment register (X86_SREG_XXX).
535 * @param pSelReg Pointer to the segment register.
536 */
537static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
538{
539 Assert(pSelReg);
540 Assert(iSegReg < X86_SREG_COUNT);
541
542 /* Selector. */
543 {
544 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
545 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
546 uint8_t const uWidthType = (uWidth << 2) | uType;
547 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
548 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
549 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
550 uint8_t *pbVmcs = (uint8_t *)pVmcs;
551 uint8_t *pbField = pbVmcs + offField;
552 *(uint16_t *)pbField = pSelReg->Sel;
553 }
554
555 /* Limit. */
556 {
557 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
558 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
559 uint8_t const uWidthType = (uWidth << 2) | uType;
560 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
561 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
562 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
563 uint8_t *pbVmcs = (uint8_t *)pVmcs;
564 uint8_t *pbField = pbVmcs + offField;
565 *(uint32_t *)pbField = pSelReg->u32Limit;
566 }
567
568 /* Base. */
569 {
570 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
571 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
572 uint8_t const uWidthType = (uWidth << 2) | uType;
573 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
574 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
575 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
576 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
577 uint8_t const *pbField = pbVmcs + offField;
578 *(uint64_t *)pbField = pSelReg->u64Base;
579 }
580
581 /* Attributes. */
582 {
583 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
584 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
585 | X86DESCATTR_UNUSABLE;
586 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
587 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
588 uint8_t const uWidthType = (uWidth << 2) | uType;
589 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
590 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
591 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
592 uint8_t *pbVmcs = (uint8_t *)pVmcs;
593 uint8_t *pbField = pbVmcs + offField;
594 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
595 }
596}
597
598
599/**
600 * Gets a guest segment register from the VMCS.
601 *
602 * @returns VBox status code.
603 * @param pVmcs Pointer to the virtual VMCS.
604 * @param iSegReg The index of the segment register (X86_SREG_XXX).
605 * @param pSelReg Where to store the segment register (only updated when
606 * VINF_SUCCESS is returned).
607 *
608 * @remarks Warning! This does not validate the contents of the retrieved segment
609 * register.
610 */
611static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
612{
613 Assert(pSelReg);
614 Assert(iSegReg < X86_SREG_COUNT);
615
616 /* Selector. */
617 uint16_t u16Sel;
618 {
619 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
620 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
621 uint8_t const uWidthType = (uWidth << 2) | uType;
622 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
623 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
624 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
625 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
626 uint8_t const *pbField = pbVmcs + offField;
627 u16Sel = *(uint16_t *)pbField;
628 }
629
630 /* Limit. */
631 uint32_t u32Limit;
632 {
633 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
634 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
635 uint8_t const uWidthType = (uWidth << 2) | uType;
636 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
637 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
638 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
639 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
640 uint8_t const *pbField = pbVmcs + offField;
641 u32Limit = *(uint32_t *)pbField;
642 }
643
644 /* Base. */
645 uint64_t u64Base;
646 {
647 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
648 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
649 uint8_t const uWidthType = (uWidth << 2) | uType;
650 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
651 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
652 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
653 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
654 uint8_t const *pbField = pbVmcs + offField;
655 u64Base = *(uint64_t *)pbField;
656 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
657 }
658
659 /* Attributes. */
660 uint32_t u32Attr;
661 {
662 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
663 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
664 uint8_t const uWidthType = (uWidth << 2) | uType;
665 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
666 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
667 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
668 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
669 uint8_t const *pbField = pbVmcs + offField;
670 u32Attr = *(uint32_t *)pbField;
671 }
672
673 pSelReg->Sel = u16Sel;
674 pSelReg->ValidSel = u16Sel;
675 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
676 pSelReg->u32Limit = u32Limit;
677 pSelReg->u64Base = u64Base;
678 pSelReg->Attr.u = u32Attr;
679 return VINF_SUCCESS;
680}
681
682
683/**
684 * Converts an IEM exception event type to a VMX event type.
685 *
686 * @returns The VMX event type.
687 * @param uVector The interrupt / exception vector.
688 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
689 */
690DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
691{
692 /* Paranoia (callers may use these interchangeably). */
693 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
694 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
695 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
696 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
697 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
698 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
699 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
700 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
701 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
702 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
703 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
704 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
705
706 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
707 {
708 if (uVector == X86_XCPT_NMI)
709 return VMX_EXIT_INT_INFO_TYPE_NMI;
710 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
711 }
712
713 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
714 {
715 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
716 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
717 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
718 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
719 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
720 }
721
722 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
723 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
724}
725
726
727/**
728 * Determines whether the guest is using PAE paging given the VMCS.
729 *
730 * @returns @c true if PAE paging mode is used, @c false otherwise.
731 * @param pVmcs Pointer to the virtual VMCS.
732 *
733 * @warning Only use this prior to switching the guest-CPU state with the
734 * nested-guest CPU state!
735 */
736DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
737{
738 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
739 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
740 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
741}
742
743
744/**
745 * Sets the Exit qualification VMCS field.
746 *
747 * @param pVCpu The cross context virtual CPU structure.
748 * @param u64ExitQual The Exit qualification.
749 */
750DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
751{
752 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
753}
754
755
756/**
757 * Sets the VM-exit interruption information field.
758 *
759 * @param pVCpu The cross context virtual CPU structure.
760 * @param uExitIntInfo The VM-exit interruption information.
761 */
762DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
763{
764 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
765}
766
767
768/**
769 * Sets the VM-exit interruption error code.
770 *
771 * @param pVCpu The cross context virtual CPU structure.
772 * @param uErrCode The error code.
773 */
774DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
775{
776 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
777}
778
779
780/**
781 * Sets the IDT-vectoring information field.
782 *
783 * @param pVCpu The cross context virtual CPU structure.
784 * @param uIdtVectorInfo The IDT-vectoring information.
785 */
786DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
787{
788 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
789}
790
791
792/**
793 * Sets the IDT-vectoring error code field.
794 *
795 * @param pVCpu The cross context virtual CPU structure.
796 * @param uErrCode The error code.
797 */
798DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
799{
800 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
801}
802
803
804/**
805 * Sets the VM-exit guest-linear address VMCS field.
806 *
807 * @param pVCpu The cross context virtual CPU structure.
808 * @param uGuestLinearAddr The VM-exit guest-linear address.
809 */
810DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
811{
812 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
813 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
814 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
815}
816
817
818/**
819 * Sets the VM-exit guest-physical address VMCS field.
820 *
821 * @param pVCpu The cross context virtual CPU structure.
822 * @param uGuestPhysAddr The VM-exit guest-physical address.
823 */
824DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
825{
826 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
827}
828
829
830/**
831 * Sets the VM-exit instruction length VMCS field.
832 *
833 * @param pVCpu The cross context virtual CPU structure.
834 * @param cbInstr The VM-exit instruction length in bytes.
835 *
836 * @remarks Callers may clear this field to 0. Hence, this function does not check
837 * the validity of the instruction length.
838 */
839DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
840{
841 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
842}
843
844
845/**
846 * Sets the VM-exit instruction info. VMCS field.
847 *
848 * @param pVCpu The cross context virtual CPU structure.
849 * @param uExitInstrInfo The VM-exit instruction information.
850 */
851DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
852{
853 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
854}
855
856
857/**
858 * Sets the guest pending-debug exceptions field.
859 *
860 * @param pVCpu The cross context virtual CPU structure.
861 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
862 */
863DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
864{
865 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
866 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
867}
868
869
870/**
871 * Implements VMSucceed for VMX instruction success.
872 *
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
876{
877 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
878}
879
880
881/**
882 * Implements VMFailInvalid for VMX instruction failure.
883 *
884 * @param pVCpu The cross context virtual CPU structure.
885 */
886DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
887{
888 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
889}
890
891
892/**
893 * Implements VMFail for VMX instruction failure.
894 *
895 * @param pVCpu The cross context virtual CPU structure.
896 * @param enmInsErr The VM instruction error.
897 */
898DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
899{
900 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
901}
902
903
904/**
905 * Checks if the given auto-load/store MSR area count is valid for the
906 * implementation.
907 *
908 * @returns @c true if it's within the valid limit, @c false otherwise.
909 * @param pVCpu The cross context virtual CPU structure.
910 * @param uMsrCount The MSR area count to check.
911 */
912DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
913{
914 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
915 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
916 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
917 if (uMsrCount <= cMaxSupportedMsrs)
918 return true;
919 return false;
920}
921
922
923/**
924 * Flushes the current VMCS contents back to guest memory.
925 *
926 * @returns VBox status code.
927 * @param pVCpu The cross context virtual CPU structure.
928 */
929DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
930{
931 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
932 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
933 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
934 return rc;
935}
936
937
938/**
939 * Populates the current VMCS contents from guest memory.
940 *
941 * @returns VBox status code.
942 * @param pVCpu The cross context virtual CPU structure.
943 */
944DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
945{
946 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
947 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
948 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
949 return rc;
950}
951
952
953/**
954 * Gets the instruction diagnostic for segment base checks during VM-entry of a
955 * nested-guest.
956 *
957 * @param iSegReg The segment index (X86_SREG_XXX).
958 */
959static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
960{
961 switch (iSegReg)
962 {
963 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
964 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
965 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
966 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
967 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
968 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
969 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
970 }
971}
972
973
974/**
975 * Gets the instruction diagnostic for segment base checks during VM-entry of a
976 * nested-guest that is in Virtual-8086 mode.
977 *
978 * @param iSegReg The segment index (X86_SREG_XXX).
979 */
980static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
981{
982 switch (iSegReg)
983 {
984 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
985 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
986 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
987 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
988 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
989 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
990 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
991 }
992}
993
994
995/**
996 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
997 * nested-guest that is in Virtual-8086 mode.
998 *
999 * @param iSegReg The segment index (X86_SREG_XXX).
1000 */
1001static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
1002{
1003 switch (iSegReg)
1004 {
1005 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1006 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1007 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1008 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1009 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1010 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1011 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1012 }
1013}
1014
1015
1016/**
1017 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1018 * nested-guest that is in Virtual-8086 mode.
1019 *
1020 * @param iSegReg The segment index (X86_SREG_XXX).
1021 */
1022static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
1023{
1024 switch (iSegReg)
1025 {
1026 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1027 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1028 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1029 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1030 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1031 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1032 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1033 }
1034}
1035
1036
1037/**
1038 * Gets the instruction diagnostic for segment attributes reserved bits failure
1039 * during VM-entry of a nested-guest.
1040 *
1041 * @param iSegReg The segment index (X86_SREG_XXX).
1042 */
1043static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1044{
1045 switch (iSegReg)
1046 {
1047 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1048 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1049 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1050 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1051 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1052 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1053 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1054 }
1055}
1056
1057
1058/**
1059 * Gets the instruction diagnostic for segment attributes descriptor-type
1060 * (code/segment or system) failure during VM-entry of a nested-guest.
1061 *
1062 * @param iSegReg The segment index (X86_SREG_XXX).
1063 */
1064static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1065{
1066 switch (iSegReg)
1067 {
1068 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1069 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1070 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1071 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1072 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1073 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1074 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1075 }
1076}
1077
1078
1079/**
1080 * Gets the instruction diagnostic for segment attributes descriptor-type
1081 * (code/segment or system) failure during VM-entry of a nested-guest.
1082 *
1083 * @param iSegReg The segment index (X86_SREG_XXX).
1084 */
1085static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1086{
1087 switch (iSegReg)
1088 {
1089 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1090 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1091 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1092 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1093 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1094 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1095 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1096 }
1097}
1098
1099
1100/**
1101 * Gets the instruction diagnostic for segment attribute granularity failure during
1102 * VM-entry of a nested-guest.
1103 *
1104 * @param iSegReg The segment index (X86_SREG_XXX).
1105 */
1106static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1107{
1108 switch (iSegReg)
1109 {
1110 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1111 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1112 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1113 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1114 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1115 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1116 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1117 }
1118}
1119
1120/**
1121 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1122 * VM-entry of a nested-guest.
1123 *
1124 * @param iSegReg The segment index (X86_SREG_XXX).
1125 */
1126static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1127{
1128 switch (iSegReg)
1129 {
1130 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1131 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1132 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1133 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1134 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1135 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1136 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1137 }
1138}
1139
1140
1141/**
1142 * Gets the instruction diagnostic for segment attribute type accessed failure
1143 * during VM-entry of a nested-guest.
1144 *
1145 * @param iSegReg The segment index (X86_SREG_XXX).
1146 */
1147static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1148{
1149 switch (iSegReg)
1150 {
1151 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1152 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1153 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1154 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1155 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1156 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1157 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1158 }
1159}
1160
1161
1162/**
1163 * Saves the guest control registers, debug registers and some MSRs are part of
1164 * VM-exit.
1165 *
1166 * @param pVCpu The cross context virtual CPU structure.
1167 */
1168static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1169{
1170 /*
1171 * Saves the guest control registers, debug registers and some MSRs.
1172 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1173 */
1174 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1175
1176 /* Save control registers. */
1177 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1178 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1179 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1180
1181 /* Save SYSENTER CS, ESP, EIP. */
1182 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1183 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1184 {
1185 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1186 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1187 }
1188 else
1189 {
1190 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1191 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1192 }
1193
1194 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1195 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1196 {
1197 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1198 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1199 }
1200
1201 /* Save PAT MSR. */
1202 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1203 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1204
1205 /* Save EFER MSR. */
1206 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1207 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1208
1209 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1210 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1211
1212 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1213}
1214
1215
1216/**
1217 * Saves the guest force-flags in preparation of entering the nested-guest.
1218 *
1219 * @param pVCpu The cross context virtual CPU structure.
1220 */
1221static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1222{
1223 /* We shouldn't be called multiple times during VM-entry. */
1224 Assert(pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit == 0);
1225
1226 /* MTF should not be set outside VMX non-root mode. */
1227 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1228
1229 /*
1230 * Preserve the required force-flags.
1231 *
1232 * We cache and clear force-flags that would affect the execution of the
1233 * nested-guest. Cached flags are then restored while returning to the guest
1234 * if necessary.
1235 *
1236 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1237 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1238 * instruction. Interrupt inhibition for any nested-guest instruction
1239 * is supplied by the guest-interruptibility state VMCS field and will
1240 * be set up as part of loading the guest state. Technically
1241 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1242 * disallow it since we can't distinguish it from blocking-by-MovSS
1243 * and no nested-hypervisor we care about uses STI immediately
1244 * followed by VMLAUNCH/VMRESUME.
1245 *
1246 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1247 * successful VM-entry (due to invalid guest-state) need to continue
1248 * blocking NMIs if it was in effect before VM-entry.
1249 *
1250 * - MTF need not be preserved as it's used only in VMX non-root mode and
1251 * is supplied through the VM-execution controls.
1252 *
1253 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1254 * we will be able to generate interrupts that may cause VM-exits for
1255 * the nested-guest.
1256 */
1257 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
1258}
1259
1260
1261/**
1262 * Restores the guest force-flags in preparation of exiting the nested-guest.
1263 *
1264 * @param pVCpu The cross context virtual CPU structure.
1265 */
1266static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1267{
1268 /** @todo r=bird: why aren't we clearing the nested guest flags first here?
1269 * If there is some other code doing that already, it would be great
1270 * to point to it here... */
1271 pVCpu->cpum.GstCtx.eflags.uBoth |= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
1272 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = 0;
1273}
1274
1275
1276/**
1277 * Performs the VMX transition to/from VMX non-root mode.
1278 *
1279 * @param pVCpu The cross context virtual CPU structure.
1280*/
1281static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1282{
1283 /*
1284 * Inform PGM about paging mode changes.
1285 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1286 * see comment in iemMemPageTranslateAndCheckAccess().
1287 */
1288 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1289 true /* fForce */);
1290 if (RT_SUCCESS(rc))
1291 { /* likely */ }
1292 else
1293 return rc;
1294
1295 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1296 IEMTlbInvalidateAll(pVCpu);
1297
1298 /* Inform CPUM (recompiler), can later be removed. */
1299 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1300
1301 /* Re-initialize IEM cache/state after the drastic mode switch. */
1302 iemReInitExec(pVCpu);
1303 return rc;
1304}
1305
1306
1307/**
1308 * Calculates the current VMX-preemption timer value.
1309 *
1310 * @returns The current VMX-preemption timer value.
1311 * @param pVCpu The cross context virtual CPU structure.
1312 */
1313static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1314{
1315 /*
1316 * Assume the following:
1317 * PreemptTimerShift = 5
1318 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1319 * EntryTick = 50000 (TSC at time of VM-entry)
1320 *
1321 * CurTick Delta PreemptTimerVal
1322 * ----------------------------------
1323 * 60000 10000 2
1324 * 80000 30000 1
1325 * 90000 40000 0 -> VM-exit.
1326 *
1327 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1328 * The saved VMX-preemption timer value is calculated as follows:
1329 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1330 * E.g.:
1331 * Delta = 10000
1332 * Tmp = 10000 / (2 * 10000) = 0.5
1333 * NewPt = 2 - 0.5 = 2
1334 * Delta = 30000
1335 * Tmp = 30000 / (2 * 10000) = 1.5
1336 * NewPt = 2 - 1.5 = 1
1337 * Delta = 40000
1338 * Tmp = 40000 / 20000 = 2
1339 * NewPt = 2 - 2 = 0
1340 */
1341 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1342 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1343 if (uVmcsPreemptVal > 0)
1344 {
1345 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1346 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1347 uint64_t const uDelta = uCurTick - uEntryTick;
1348 uint32_t const uPreemptTimer = uVmcsPreemptVal
1349 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1350 return uPreemptTimer;
1351 }
1352 return 0;
1353}
1354
1355
1356/**
1357 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1358 *
1359 * @param pVCpu The cross context virtual CPU structure.
1360 */
1361static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1362{
1363 /*
1364 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1365 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1366 */
1367 /* CS, SS, ES, DS, FS, GS. */
1368 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1369 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1370 {
1371 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1372 if (!pSelReg->Attr.n.u1Unusable)
1373 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1374 else
1375 {
1376 /*
1377 * For unusable segments the attributes are undefined except for CS and SS.
1378 * For the rest we don't bother preserving anything but the unusable bit.
1379 */
1380 switch (iSegReg)
1381 {
1382 case X86_SREG_CS:
1383 pVmcs->GuestCs = pSelReg->Sel;
1384 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1385 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1386 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1387 | X86DESCATTR_UNUSABLE);
1388 break;
1389
1390 case X86_SREG_SS:
1391 pVmcs->GuestSs = pSelReg->Sel;
1392 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1393 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1394 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1395 break;
1396
1397 case X86_SREG_DS:
1398 pVmcs->GuestDs = pSelReg->Sel;
1399 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1400 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1401 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1402 break;
1403
1404 case X86_SREG_ES:
1405 pVmcs->GuestEs = pSelReg->Sel;
1406 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1407 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1408 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1409 break;
1410
1411 case X86_SREG_FS:
1412 pVmcs->GuestFs = pSelReg->Sel;
1413 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1414 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1415 break;
1416
1417 case X86_SREG_GS:
1418 pVmcs->GuestGs = pSelReg->Sel;
1419 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1420 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1421 break;
1422 }
1423 }
1424 }
1425
1426 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1427 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1428 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1429 | X86DESCATTR_UNUSABLE;
1430 /* LDTR. */
1431 {
1432 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1433 pVmcs->GuestLdtr = pSelReg->Sel;
1434 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1435 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1436 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1437 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1438 }
1439
1440 /* TR. */
1441 {
1442 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1443 pVmcs->GuestTr = pSelReg->Sel;
1444 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1445 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1446 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1447 }
1448
1449 /* GDTR. */
1450 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1451 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1452
1453 /* IDTR. */
1454 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1455 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1456}
1457
1458
1459/**
1460 * Saves guest non-register state as part of VM-exit.
1461 *
1462 * @param pVCpu The cross context virtual CPU structure.
1463 * @param uExitReason The VM-exit reason.
1464 */
1465static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1466{
1467 /*
1468 * Save guest non-register state.
1469 * See Intel spec. 27.3.4 "Saving Non-Register State".
1470 */
1471 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1472
1473 /*
1474 * Activity state.
1475 * Most VM-exits will occur in the active state. However, if the first instruction
1476 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1477 * the VM-exit will be from the HLT activity state.
1478 *
1479 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1480 */
1481 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1482 * not? */
1483 EMSTATE const enmActivityState = EMGetState(pVCpu);
1484 switch (enmActivityState)
1485 {
1486 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1487 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1488 }
1489
1490 /*
1491 * Interruptibility-state.
1492 */
1493 /* NMI. */
1494 pVmcs->u32GuestIntrState = 0;
1495 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1496 {
1497 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1498 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1499 }
1500 else
1501 {
1502 if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
1503 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1504 }
1505
1506 /* Blocking-by-STI or blocking-by-MovSS. */
1507 uint32_t fInhibitShw;
1508 if (!CPUMIsInInterruptShadowWithUpdateEx(&pVCpu->cpum.GstCtx, &fInhibitShw))
1509 { /* probable */}
1510 else
1511 {
1512 if (pVCpu->cpum.GstCtx.rip == pVCpu->cpum.GstCtx.uRipInhibitInt)
1513 {
1514 /*
1515 * We must ensure only one of these bits is set.
1516 * Our emulation can have both set (perhaps because AMD doesn't distinguish
1517 * between the two?). Hence, the 'else' with blocking-by-MovSS taking priority
1518 * since it blocks more. Nested Ubuntu 22.04.2 running inside a Hyper-V enabled
1519 * Windows Server 2008 R2 guest runs into this issue.
1520 *
1521 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
1522 */
1523 if (fInhibitShw & CPUMCTX_INHIBIT_SHADOW_SS)
1524 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
1525 else
1526 {
1527 Assert(fInhibitShw & CPUMCTX_INHIBIT_SHADOW_STI);
1528 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1529 }
1530 }
1531 }
1532 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1533
1534 /*
1535 * Pending debug exceptions.
1536 *
1537 * For VM-exits where it is not applicable, we can safely zero out the field.
1538 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1539 */
1540 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1541 && uExitReason != VMX_EXIT_SMI
1542 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1543 && !VMXIsVmexitTrapLike(uExitReason))
1544 {
1545 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1546 * block-by-MovSS is in effect. */
1547 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1548 }
1549
1550 /*
1551 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1552 *
1553 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1554 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1555 */
1556 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1557 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1558 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1559
1560 /*
1561 * Save the guest PAE PDPTEs.
1562 */
1563 if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1564 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1565 {
1566 /*
1567 * Without EPT or when the nested-guest is not using PAE paging, the values saved
1568 * in the VMCS during VM-exit are undefined. We zero them here for consistency.
1569 */
1570 pVmcs->u64GuestPdpte0.u = 0;
1571 pVmcs->u64GuestPdpte1.u = 0;
1572 pVmcs->u64GuestPdpte2.u = 0;
1573 pVmcs->u64GuestPdpte3.u = 0;
1574 }
1575 else
1576 {
1577 /*
1578 * With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1579 * the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1580 * of the nested-guest is expected to have updated them.
1581 */
1582 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1583 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1584 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1585 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1586 }
1587
1588 /* Clear PGM's copy of the EPT pointer for added safety. */
1589 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1590 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1591}
1592
1593
1594/**
1595 * Saves the guest-state as part of VM-exit.
1596 *
1597 * @returns VBox status code.
1598 * @param pVCpu The cross context virtual CPU structure.
1599 * @param uExitReason The VM-exit reason.
1600 */
1601static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1602{
1603 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1604 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1605
1606 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1607 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1608 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1609
1610 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1611}
1612
1613
1614/**
1615 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1616 *
1617 * @returns VBox status code.
1618 * @param pVCpu The cross context virtual CPU structure.
1619 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1620 */
1621static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1622{
1623 /*
1624 * Save guest MSRs.
1625 * See Intel spec. 27.4 "Saving MSRs".
1626 */
1627 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1628 const char * const pszFailure = "VMX-abort";
1629
1630 /*
1631 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1632 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1633 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1634 */
1635 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1636 if (!cMsrs)
1637 return VINF_SUCCESS;
1638
1639 /*
1640 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1641 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1642 * implementation causes a VMX-abort followed by a triple-fault.
1643 */
1644 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1645 if (fIsMsrCountValid)
1646 { /* likely */ }
1647 else
1648 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1649
1650 /*
1651 * Optimization if the nested hypervisor is using the same guest-physical page for both
1652 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1653 */
1654 PVMXAUTOMSR pMsrArea;
1655 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1656 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1657 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1658 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1659 else
1660 {
1661 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1662 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1663 if (RT_SUCCESS(rc))
1664 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1665 else
1666 {
1667 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1668 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1669 }
1670 }
1671
1672 /*
1673 * Update VM-exit MSR store area.
1674 */
1675 PVMXAUTOMSR pMsr = pMsrArea;
1676 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1677 {
1678 if ( !pMsr->u32Reserved
1679 && pMsr->u32Msr != MSR_IA32_SMBASE
1680 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1681 {
1682 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1683 if (rcStrict == VINF_SUCCESS)
1684 continue;
1685
1686 /*
1687 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1688 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1689 * recording the MSR index in the auxiliary info. field and indicated further by our
1690 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1691 * if possible, or come up with a better, generic solution.
1692 */
1693 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1694 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1695 ? kVmxVDiag_Vmexit_MsrStoreRing3
1696 : kVmxVDiag_Vmexit_MsrStore;
1697 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1698 }
1699 else
1700 {
1701 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1702 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1703 }
1704 }
1705
1706 /*
1707 * Commit the VM-exit MSR store are to guest memory.
1708 */
1709 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1710 if (RT_SUCCESS(rc))
1711 return VINF_SUCCESS;
1712
1713 NOREF(uExitReason);
1714 NOREF(pszFailure);
1715
1716 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1717 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1718}
1719
1720
1721/**
1722 * Performs a VMX abort (due to an fatal error during VM-exit).
1723 *
1724 * @returns Strict VBox status code.
1725 * @param pVCpu The cross context virtual CPU structure.
1726 * @param enmAbort The VMX abort reason.
1727 */
1728static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1729{
1730 /*
1731 * Perform the VMX abort.
1732 * See Intel spec. 27.7 "VMX Aborts".
1733 */
1734 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1735
1736 /* We don't support SMX yet. */
1737 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1738 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1739 {
1740 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1741 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1742 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1743 }
1744
1745 return VINF_EM_TRIPLE_FAULT;
1746}
1747
1748
1749/**
1750 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1751 *
1752 * @param pVCpu The cross context virtual CPU structure.
1753 */
1754static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1755{
1756 /*
1757 * Load host control registers, debug registers and MSRs.
1758 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1759 */
1760 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1761 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1762
1763 /* CR0. */
1764 {
1765 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1766 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK;
1767 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1768 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1769 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1770
1771 /* Verify we have not modified CR0 fixed bits in VMX operation. */
1772#ifdef VBOX_STRICT
1773 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
1774 bool const fUx = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1775 AssertMsg( (uValidHostCr0 & uCr0Mb1) == uCr0Mb1
1776 && (uValidHostCr0 & ~VMX_V_CR0_FIXED1) == 0,
1777 ("host=%#RX64 guest=%#RX64 mb1=%#RX64 valid_host_cr0=%#RX64 fUx=%RTbool\n",
1778 uHostCr0, uGuestCr0, uCr0Mb1, uValidHostCr0, fUx));
1779#endif
1780 Assert(!(uValidHostCr0 >> 32));
1781 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1782 }
1783
1784 /* CR4. */
1785 {
1786 /* CR4 fixed bits are not modified. */
1787 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1788 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1789 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1790 uint64_t uValidHostCr4 = (uHostCr4 & uCr4Mb0) | uCr4Mb1;
1791 if (fHostInLongMode)
1792 uValidHostCr4 |= X86_CR4_PAE;
1793 else
1794 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1795
1796 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1797 AssertMsg( (uValidHostCr4 & uCr4Mb1) == uCr4Mb1
1798 && (uValidHostCr4 & ~uCr4Mb0) == 0,
1799 ("host=%#RX64 guest=%#RX64, uCr4Mb1=%#RX64 uCr4Mb0=%#RX64 valid_host_cr4=%#RX64\n",
1800 uHostCr4, pVCpu->cpum.GstCtx.cr4, uCr4Mb1, uCr4Mb0, uValidHostCr4));
1801 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1802 }
1803
1804 /* CR3 (host value validated while checking host-state during VM-entry). */
1805 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1806
1807 /* DR7. */
1808 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1809
1810 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1811
1812 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1813 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1814 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1815 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1816
1817 /* FS, GS bases are loaded later while we load host segment registers. */
1818
1819 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1820 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1821 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1822 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1823 {
1824 if (fHostInLongMode)
1825 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1826 else
1827 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1828 }
1829
1830 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1831
1832 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1833 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1834 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1835
1836 /* We don't support IA32_BNDCFGS MSR yet. */
1837}
1838
1839
1840/**
1841 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1842 *
1843 * @param pVCpu The cross context virtual CPU structure.
1844 */
1845static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1846{
1847 /*
1848 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1849 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1850 *
1851 * Warning! Be careful to not touch fields that are reserved by VT-x,
1852 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1853 */
1854 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1855 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1856
1857 /* CS, SS, ES, DS, FS, GS. */
1858 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1859 {
1860 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1861 bool const fUnusable = RT_BOOL(HostSel == 0);
1862 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1863
1864 /* Selector. */
1865 pSelReg->Sel = HostSel;
1866 pSelReg->ValidSel = HostSel;
1867 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1868
1869 /* Limit. */
1870 pSelReg->u32Limit = 0xffffffff;
1871
1872 /* Base. */
1873 pSelReg->u64Base = 0;
1874
1875 /* Attributes. */
1876 if (iSegReg == X86_SREG_CS)
1877 {
1878 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1879 pSelReg->Attr.n.u1DescType = 1;
1880 pSelReg->Attr.n.u2Dpl = 0;
1881 pSelReg->Attr.n.u1Present = 1;
1882 pSelReg->Attr.n.u1Long = fHostInLongMode;
1883 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1884 pSelReg->Attr.n.u1Granularity = 1;
1885 Assert(!pSelReg->Attr.n.u1Unusable);
1886 Assert(!fUnusable);
1887 }
1888 else
1889 {
1890 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1891 pSelReg->Attr.n.u1DescType = 1;
1892 pSelReg->Attr.n.u2Dpl = 0;
1893 pSelReg->Attr.n.u1Present = 1;
1894 pSelReg->Attr.n.u1DefBig = 1;
1895 pSelReg->Attr.n.u1Granularity = 1;
1896 pSelReg->Attr.n.u1Unusable = fUnusable;
1897 }
1898 }
1899
1900 /* FS base. */
1901 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1902 || fHostInLongMode)
1903 {
1904 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1905 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1906 }
1907
1908 /* GS base. */
1909 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1910 || fHostInLongMode)
1911 {
1912 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1913 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1914 }
1915
1916 /* TR. */
1917 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1918 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1919 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1920 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1921 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1922 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1923 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1924 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1925 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1926 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1927 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1928 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1929 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1930
1931 /* LDTR (Warning! do not touch the base and limits here). */
1932 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1933 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1934 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1935 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1936
1937 /* GDTR. */
1938 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1939 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1940 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1941
1942 /* IDTR.*/
1943 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1944 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1945 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1946}
1947
1948
1949/**
1950 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1951 *
1952 * @returns VBox status code.
1953 * @param pVCpu The cross context virtual CPU structure.
1954 * @param uExitReason The VMX instruction name (for logging purposes).
1955 */
1956static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1957{
1958 /*
1959 * Load host MSRs.
1960 * See Intel spec. 27.6 "Loading MSRs".
1961 */
1962 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1963 const char * const pszFailure = "VMX-abort";
1964
1965 /*
1966 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1967 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1968 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1969 */
1970 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1971 if (!cMsrs)
1972 return VINF_SUCCESS;
1973
1974 /*
1975 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1976 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1977 * implementation causes a VMX-abort followed by a triple-fault.
1978 */
1979 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1980 if (fIsMsrCountValid)
1981 { /* likely */ }
1982 else
1983 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1984
1985 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1986 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1987 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1988 if (RT_SUCCESS(rc))
1989 {
1990 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1991 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1992 {
1993 if ( !pMsr->u32Reserved
1994 && pMsr->u32Msr != MSR_K8_FS_BASE
1995 && pMsr->u32Msr != MSR_K8_GS_BASE
1996 && pMsr->u32Msr != MSR_K6_EFER
1997 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1998 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1999 {
2000 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2001 if (rcStrict == VINF_SUCCESS)
2002 continue;
2003
2004 /*
2005 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2006 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2007 * recording the MSR index in the auxiliary info. field and indicated further by our
2008 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2009 * if possible, or come up with a better, generic solution.
2010 */
2011 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2012 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2013 ? kVmxVDiag_Vmexit_MsrLoadRing3
2014 : kVmxVDiag_Vmexit_MsrLoad;
2015 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2016 }
2017 else
2018 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2019 }
2020 }
2021 else
2022 {
2023 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2024 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2025 }
2026
2027 NOREF(uExitReason);
2028 NOREF(pszFailure);
2029 return VINF_SUCCESS;
2030}
2031
2032
2033/**
2034 * Loads the host state as part of VM-exit.
2035 *
2036 * @returns Strict VBox status code.
2037 * @param pVCpu The cross context virtual CPU structure.
2038 * @param uExitReason The VM-exit reason (for logging purposes).
2039 */
2040static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
2041{
2042 /*
2043 * Load host state.
2044 * See Intel spec. 27.5 "Loading Host State".
2045 */
2046 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2047 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2048
2049 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2050 if ( CPUMIsGuestInLongMode(pVCpu)
2051 && !fHostInLongMode)
2052 {
2053 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2054 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2055 }
2056
2057 /*
2058 * Check host PAE PDPTEs prior to loading the host state.
2059 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2060 */
2061 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2062 && !fHostInLongMode
2063 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2064 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2065 {
2066 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2067 if (RT_SUCCESS(rc))
2068 { /* likely*/ }
2069 else
2070 {
2071 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2072 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2073 }
2074 }
2075
2076 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2077 iemVmxVmexitLoadHostSegRegs(pVCpu);
2078
2079 /*
2080 * Load host RIP, RSP and RFLAGS.
2081 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2082 */
2083 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2084 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2085 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2086
2087 /* Clear address range monitoring. */
2088 EMMonitorWaitClear(pVCpu);
2089
2090 /* Perform the VMX transition (PGM updates). */
2091 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2092 if (rcStrict == VINF_SUCCESS)
2093 { /* likely */ }
2094 else if (RT_SUCCESS(rcStrict))
2095 {
2096 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2097 uExitReason));
2098 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2099 }
2100 else
2101 {
2102 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2103 return VBOXSTRICTRC_VAL(rcStrict);
2104 }
2105
2106 Assert(rcStrict == VINF_SUCCESS);
2107
2108 /* Load MSRs from the VM-exit auto-load MSR area. */
2109 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2110 if (RT_FAILURE(rc))
2111 {
2112 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2113 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2114 }
2115 return VINF_SUCCESS;
2116}
2117
2118
2119/**
2120 * Gets VM-exit instruction information along with any displacement for an
2121 * instruction VM-exit.
2122 *
2123 * @returns The VM-exit instruction information.
2124 * @param pVCpu The cross context virtual CPU structure.
2125 * @param uExitReason The VM-exit reason.
2126 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2127 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2128 * NULL.
2129 */
2130static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2131{
2132 RTGCPTR GCPtrDisp;
2133 VMXEXITINSTRINFO ExitInstrInfo;
2134 ExitInstrInfo.u = 0;
2135
2136 /*
2137 * Get and parse the ModR/M byte from our decoded opcodes.
2138 */
2139 uint8_t bRm;
2140 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2141 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2142 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2143 {
2144 /*
2145 * ModR/M indicates register addressing.
2146 *
2147 * The primary/secondary register operands are reported in the iReg1 or iReg2
2148 * fields depending on whether it is a read/write form.
2149 */
2150 uint8_t idxReg1;
2151 uint8_t idxReg2;
2152 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2153 {
2154 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2155 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2156 }
2157 else
2158 {
2159 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2160 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2161 }
2162 ExitInstrInfo.All.u2Scaling = 0;
2163 ExitInstrInfo.All.iReg1 = idxReg1;
2164 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2165 ExitInstrInfo.All.fIsRegOperand = 1;
2166 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2167 ExitInstrInfo.All.iSegReg = 0;
2168 ExitInstrInfo.All.iIdxReg = 0;
2169 ExitInstrInfo.All.fIdxRegInvalid = 1;
2170 ExitInstrInfo.All.iBaseReg = 0;
2171 ExitInstrInfo.All.fBaseRegInvalid = 1;
2172 ExitInstrInfo.All.iReg2 = idxReg2;
2173
2174 /* Displacement not applicable for register addressing. */
2175 GCPtrDisp = 0;
2176 }
2177 else
2178 {
2179 /*
2180 * ModR/M indicates memory addressing.
2181 */
2182 uint8_t uScale = 0;
2183 bool fBaseRegValid = false;
2184 bool fIdxRegValid = false;
2185 uint8_t iBaseReg = 0;
2186 uint8_t iIdxReg = 0;
2187 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2188 {
2189 /*
2190 * Parse the ModR/M, displacement for 16-bit addressing mode.
2191 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2192 */
2193 uint16_t u16Disp = 0;
2194 uint8_t const offDisp = offModRm + sizeof(bRm);
2195 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2196 {
2197 /* Displacement without any registers. */
2198 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2199 }
2200 else
2201 {
2202 /* Register (index and base). */
2203 switch (bRm & X86_MODRM_RM_MASK)
2204 {
2205 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2206 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2207 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2208 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2209 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2210 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2211 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2212 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2213 }
2214
2215 /* Register + displacement. */
2216 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2217 {
2218 case 0: break;
2219 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2220 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2221 default:
2222 {
2223 /* Register addressing, handled at the beginning. */
2224 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2225 break;
2226 }
2227 }
2228 }
2229
2230 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2231 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2232 }
2233 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2234 {
2235 /*
2236 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2237 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2238 */
2239 uint32_t u32Disp = 0;
2240 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2241 {
2242 /* Displacement without any registers. */
2243 uint8_t const offDisp = offModRm + sizeof(bRm);
2244 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2245 }
2246 else
2247 {
2248 /* Register (and perhaps scale, index and base). */
2249 uint8_t offDisp = offModRm + sizeof(bRm);
2250 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2251 if (iBaseReg == 4)
2252 {
2253 /* An SIB byte follows the ModR/M byte, parse it. */
2254 uint8_t bSib;
2255 uint8_t const offSib = offModRm + sizeof(bRm);
2256 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2257
2258 /* A displacement may follow SIB, update its offset. */
2259 offDisp += sizeof(bSib);
2260
2261 /* Get the scale. */
2262 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2263
2264 /* Get the index register. */
2265 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2266 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2267
2268 /* Get the base register. */
2269 iBaseReg = bSib & X86_SIB_BASE_MASK;
2270 fBaseRegValid = true;
2271 if (iBaseReg == 5)
2272 {
2273 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2274 {
2275 /* Mod is 0 implies a 32-bit displacement with no base. */
2276 fBaseRegValid = false;
2277 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2278 }
2279 else
2280 {
2281 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2282 iBaseReg = X86_GREG_xBP;
2283 }
2284 }
2285 }
2286
2287 /* Register + displacement. */
2288 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2289 {
2290 case 0: /* Handled above */ break;
2291 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2292 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2293 default:
2294 {
2295 /* Register addressing, handled at the beginning. */
2296 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2297 break;
2298 }
2299 }
2300 }
2301
2302 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2303 }
2304 else
2305 {
2306 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2307
2308 /*
2309 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2310 * See Intel instruction spec. 2.2 "IA-32e Mode".
2311 */
2312 uint64_t u64Disp = 0;
2313 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2314 if (fRipRelativeAddr)
2315 {
2316 /*
2317 * RIP-relative addressing mode.
2318 *
2319 * The displacement is 32-bit signed implying an offset range of +/-2G.
2320 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2321 */
2322 uint8_t const offDisp = offModRm + sizeof(bRm);
2323 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2324 }
2325 else
2326 {
2327 uint8_t offDisp = offModRm + sizeof(bRm);
2328
2329 /*
2330 * Register (and perhaps scale, index and base).
2331 *
2332 * REX.B extends the most-significant bit of the base register. However, REX.B
2333 * is ignored while determining whether an SIB follows the opcode. Hence, we
2334 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2335 *
2336 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2337 */
2338 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2339 if (iBaseReg == 4)
2340 {
2341 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2342 uint8_t bSib;
2343 uint8_t const offSib = offModRm + sizeof(bRm);
2344 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2345
2346 /* Displacement may follow SIB, update its offset. */
2347 offDisp += sizeof(bSib);
2348
2349 /* Get the scale. */
2350 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2351
2352 /* Get the index. */
2353 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2354 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2355
2356 /* Get the base. */
2357 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2358 fBaseRegValid = true;
2359 if (iBaseReg == 5)
2360 {
2361 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2362 {
2363 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2364 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2365 }
2366 else
2367 {
2368 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2369 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2370 }
2371 }
2372 }
2373 iBaseReg |= pVCpu->iem.s.uRexB;
2374
2375 /* Register + displacement. */
2376 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2377 {
2378 case 0: /* Handled above */ break;
2379 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2380 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2381 default:
2382 {
2383 /* Register addressing, handled at the beginning. */
2384 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2385 break;
2386 }
2387 }
2388 }
2389
2390 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2391 }
2392
2393 /*
2394 * The primary or secondary register operand is reported in iReg2 depending
2395 * on whether the primary operand is in read/write form.
2396 */
2397 uint8_t idxReg2;
2398 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2399 {
2400 idxReg2 = bRm & X86_MODRM_RM_MASK;
2401 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2402 idxReg2 |= pVCpu->iem.s.uRexB;
2403 }
2404 else
2405 {
2406 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2407 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2408 idxReg2 |= pVCpu->iem.s.uRexReg;
2409 }
2410 ExitInstrInfo.All.u2Scaling = uScale;
2411 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2412 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2413 ExitInstrInfo.All.fIsRegOperand = 0;
2414 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2415 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2416 ExitInstrInfo.All.iIdxReg = iIdxReg;
2417 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2418 ExitInstrInfo.All.iBaseReg = iBaseReg;
2419 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2420 ExitInstrInfo.All.iReg2 = idxReg2;
2421 }
2422
2423 /*
2424 * Handle exceptions to the norm for certain instructions.
2425 * (e.g. some instructions convey an instruction identity in place of iReg2).
2426 */
2427 switch (uExitReason)
2428 {
2429 case VMX_EXIT_GDTR_IDTR_ACCESS:
2430 {
2431 Assert(VMXINSTRID_IS_VALID(uInstrId));
2432 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2433 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2434 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2435 break;
2436 }
2437
2438 case VMX_EXIT_LDTR_TR_ACCESS:
2439 {
2440 Assert(VMXINSTRID_IS_VALID(uInstrId));
2441 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2442 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2443 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2444 break;
2445 }
2446
2447 case VMX_EXIT_RDRAND:
2448 case VMX_EXIT_RDSEED:
2449 {
2450 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2451 break;
2452 }
2453 }
2454
2455 /* Update displacement and return the constructed VM-exit instruction information field. */
2456 if (pGCPtrDisp)
2457 *pGCPtrDisp = GCPtrDisp;
2458
2459 return ExitInstrInfo.u;
2460}
2461
2462
2463/**
2464 * VMX VM-exit handler.
2465 *
2466 * @returns Strict VBox status code.
2467 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2468 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2469 * triple-fault.
2470 *
2471 * @param pVCpu The cross context virtual CPU structure.
2472 * @param uExitReason The VM-exit reason.
2473 * @param u64ExitQual The Exit qualification.
2474 *
2475 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2476 * called. Failures during VM-entry can cause VM-exits as well, so we
2477 * -cannot- assert we're in VMX non-root mode here.
2478 */
2479VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2480{
2481# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2482 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2483 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2484 return VERR_IEM_IPE_7;
2485# else
2486 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2487
2488 /* Just count this as an exit and be done with that. */
2489 pVCpu->iem.s.cPotentialExits++;
2490
2491 /*
2492 * Import all the guest-CPU state.
2493 *
2494 * HM on returning to guest execution would have to reset up a whole lot of state
2495 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2496 * the state and flag reloading the entire state on re-entry. So import the entire
2497 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2498 */
2499 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2500
2501 /*
2502 * Ensure VM-entry interruption information valid bit is cleared.
2503 *
2504 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2505 * by invalid-guest state or machine-check exceptions) also clear this bit.
2506 *
2507 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2508 */
2509 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2510 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2511
2512 /*
2513 * Update the VM-exit reason and Exit qualification.
2514 * Other VMCS read-only data fields are expected to be updated by the caller already.
2515 */
2516 pVmcs->u32RoExitReason = uExitReason;
2517 pVmcs->u64RoExitQual.u = u64ExitQual;
2518
2519 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2520 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2521 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u));
2522
2523 /*
2524 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2525 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2526 */
2527 {
2528 uint8_t uVector;
2529 uint32_t fFlags;
2530 uint32_t uErrCode;
2531 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2532 if (fInEventDelivery)
2533 {
2534 /*
2535 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2536 * caused by a triple-fault or the original event results in a double-fault that
2537 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2538 * original event information into the IDT-vectoring information fields.
2539 *
2540 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2541 */
2542 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2543 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2544 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2545 {
2546 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2547 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2548 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2549 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2550 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2551 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2552 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2553 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2554 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2555 pVCpu->cpum.GstCtx.cr2));
2556 }
2557 }
2558 }
2559
2560 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2561 Assert(pVmcs->u64RoIoRcx.u == 0);
2562 Assert(pVmcs->u64RoIoRsi.u == 0);
2563 Assert(pVmcs->u64RoIoRdi.u == 0);
2564 Assert(pVmcs->u64RoIoRip.u == 0);
2565
2566 /*
2567 * Save the guest state back into the VMCS.
2568 * We only need to save the state when the VM-entry was successful.
2569 */
2570 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2571 if (!fVmentryFailed)
2572 {
2573 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2574 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2575 {
2576 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2577 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2578 }
2579
2580 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2581 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2582
2583 /*
2584 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2585 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2586 *
2587 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2588 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2589 * as guest-CPU state would not been modified. Hence for now, we do this only when
2590 * the VM-entry succeeded.
2591 */
2592 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2593 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2594 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2595 {
2596 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2597 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2598 else
2599 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2600 }
2601
2602 /*
2603 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2604 * occurs in enclave mode/SMM which we don't support yet.
2605 *
2606 * If we ever add support for it, we can pass just the lower bits to the functions
2607 * below, till then an assert should suffice.
2608 */
2609 Assert(!RT_HI_U16(uExitReason));
2610
2611 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2612 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2613 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2614 if (RT_SUCCESS(rc))
2615 { /* likely */ }
2616 else
2617 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2618
2619 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2620 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit &= ~CPUMCTX_INHIBIT_NMI;
2621 }
2622 else
2623 {
2624 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2625 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2626 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2627 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2628 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2629 }
2630
2631 /*
2632 * Stop any running VMX-preemption timer if necessary.
2633 */
2634 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2635 CPUMStopGuestVmxPremptTimer(pVCpu);
2636
2637 /*
2638 * Clear any pending VMX nested-guest force-flags.
2639 * These force-flags have no effect on (outer) guest execution and will
2640 * be re-evaluated and setup on the next nested-guest VM-entry.
2641 */
2642 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2643
2644 /*
2645 * We're no longer in nested-guest execution mode.
2646 *
2647 * It is important to do this prior to loading the host state because
2648 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2649 * second-level address translation while switching to host CR3.
2650 */
2651 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2652
2653 /* Restore the host (outer guest) state. */
2654 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2655 if (RT_SUCCESS(rcStrict))
2656 {
2657 Assert(rcStrict == VINF_SUCCESS);
2658 rcStrict = VINF_VMX_VMEXIT;
2659 }
2660 else
2661 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2662
2663 /*
2664 * Restore non-zero Secondary-processor based VM-execution controls
2665 * when the "activate secondary controls" bit was not set.
2666 */
2667 if (pVmcs->u32RestoreProcCtls2)
2668 {
2669 Assert(!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS));
2670 pVmcs->u32ProcCtls2 = pVmcs->u32RestoreProcCtls2;
2671 pVmcs->u32RestoreProcCtls2 = 0;
2672 }
2673
2674 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2675 {
2676 /* Notify HM that the current VMCS fields have been modified. */
2677 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2678
2679 /* Notify HM that we've completed the VM-exit. */
2680 HMNotifyVmxNstGstVmexit(pVCpu);
2681 }
2682
2683# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2684 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2685 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2686 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2687 if (rcSched != VINF_SUCCESS)
2688 iemSetPassUpStatus(pVCpu, rcSched);
2689# endif
2690 return rcStrict;
2691# endif
2692}
2693
2694
2695/**
2696 * VMX VM-exit handler for VM-exits due to instruction execution.
2697 *
2698 * This is intended for instructions where the caller provides all the relevant
2699 * VM-exit information.
2700 *
2701 * @returns Strict VBox status code.
2702 * @param pVCpu The cross context virtual CPU structure.
2703 * @param pExitInfo Pointer to the VM-exit information.
2704 */
2705static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2706{
2707 /*
2708 * For instructions where any of the following fields are not applicable:
2709 * - Exit qualification must be cleared.
2710 * - VM-exit instruction info. is undefined.
2711 * - Guest-linear address is undefined.
2712 * - Guest-physical address is undefined.
2713 *
2714 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2715 * instruction execution. For VM-exits that are not due to instruction execution this
2716 * field is undefined.
2717 *
2718 * In our implementation in IEM, all undefined fields are generally cleared. However,
2719 * if the caller supplies information (from say the physical CPU directly) it is
2720 * then possible that the undefined fields are not cleared.
2721 *
2722 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2723 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2724 */
2725 Assert(pExitInfo);
2726 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2727 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2728 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2729
2730 /* Update all the relevant fields from the VM-exit instruction information struct. */
2731 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2732 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2733 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2734 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2735
2736 /* Perform the VM-exit. */
2737 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2738}
2739
2740
2741/**
2742 * VMX VM-exit handler for VM-exits due to instruction execution.
2743 *
2744 * This is intended for instructions that only provide the VM-exit instruction
2745 * length.
2746 *
2747 * @param pVCpu The cross context virtual CPU structure.
2748 * @param uExitReason The VM-exit reason.
2749 * @param cbInstr The instruction length in bytes.
2750 */
2751VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2752{
2753#ifdef VBOX_STRICT
2754 /*
2755 * To prevent us from shooting ourselves in the foot.
2756 * The follow instructions should convey more than just the instruction length.
2757 */
2758 switch (uExitReason)
2759 {
2760 case VMX_EXIT_INVEPT:
2761 case VMX_EXIT_INVPCID:
2762 case VMX_EXIT_INVVPID:
2763 case VMX_EXIT_LDTR_TR_ACCESS:
2764 case VMX_EXIT_GDTR_IDTR_ACCESS:
2765 case VMX_EXIT_VMCLEAR:
2766 case VMX_EXIT_VMPTRLD:
2767 case VMX_EXIT_VMPTRST:
2768 case VMX_EXIT_VMREAD:
2769 case VMX_EXIT_VMWRITE:
2770 case VMX_EXIT_VMXON:
2771 case VMX_EXIT_XRSTORS:
2772 case VMX_EXIT_XSAVES:
2773 case VMX_EXIT_RDRAND:
2774 case VMX_EXIT_RDSEED:
2775 case VMX_EXIT_IO_INSTR:
2776 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2777 break;
2778 }
2779#endif
2780
2781 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2782 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2783}
2784
2785
2786/**
2787 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2788 *
2789 * @returns Strict VBox status code.
2790 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2791 * @thread EMT(pVCpu)
2792 */
2793VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2794{
2795 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2796 Assert(!pVCpu->iem.s.cActiveMappings);
2797 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2798}
2799
2800
2801/**
2802 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2803 *
2804 * @returns Strict VBox status code.
2805 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2806 * @param uVector The SIPI vector.
2807 * @thread EMT(pVCpu)
2808 */
2809VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2810{
2811 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2812 Assert(!pVCpu->iem.s.cActiveMappings);
2813 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2814}
2815
2816
2817/**
2818 * Interface for HM and EM to emulate a VM-exit.
2819 *
2820 * If a specialized version of a VM-exit handler exists, that must be used instead.
2821 *
2822 * @returns Strict VBox status code.
2823 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2824 * @param uExitReason The VM-exit reason.
2825 * @param u64ExitQual The Exit qualification.
2826 * @thread EMT(pVCpu)
2827 */
2828VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2829{
2830 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2831 Assert(!pVCpu->iem.s.cActiveMappings);
2832 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2833}
2834
2835
2836/**
2837 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2838 *
2839 * This is meant to be used for those instructions that VMX provides additional
2840 * decoding information beyond just the instruction length!
2841 *
2842 * @returns Strict VBox status code.
2843 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2844 * @param pExitInfo Pointer to the VM-exit information.
2845 * @thread EMT(pVCpu)
2846 */
2847VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2848{
2849 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2850 Assert(!pVCpu->iem.s.cActiveMappings);
2851 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2852}
2853
2854
2855/**
2856 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2857 *
2858 * This is meant to be used for those instructions that VMX provides only the
2859 * instruction length.
2860 *
2861 * @returns Strict VBox status code.
2862 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2863 * @param pExitInfo Pointer to the VM-exit information.
2864 * @param cbInstr The instruction length in bytes.
2865 * @thread EMT(pVCpu)
2866 */
2867VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2868{
2869 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2870 Assert(!pVCpu->iem.s.cActiveMappings);
2871 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2872}
2873
2874
2875/**
2876 * VMX VM-exit handler for VM-exits due to instruction execution.
2877 *
2878 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2879 * instruction information and Exit qualification fields.
2880 *
2881 * @param pVCpu The cross context virtual CPU structure.
2882 * @param uExitReason The VM-exit reason.
2883 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2884 * @param cbInstr The instruction length in bytes.
2885 *
2886 * @remarks Do not use this for INS/OUTS instruction.
2887 */
2888VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2889{
2890#ifdef VBOX_STRICT
2891 /*
2892 * To prevent us from shooting ourselves in the foot.
2893 * The follow instructions convey specific info that require using their respective handlers.
2894 */
2895 switch (uExitReason)
2896 {
2897 case VMX_EXIT_INVEPT:
2898 case VMX_EXIT_INVPCID:
2899 case VMX_EXIT_INVVPID:
2900 case VMX_EXIT_LDTR_TR_ACCESS:
2901 case VMX_EXIT_GDTR_IDTR_ACCESS:
2902 case VMX_EXIT_VMCLEAR:
2903 case VMX_EXIT_VMPTRLD:
2904 case VMX_EXIT_VMPTRST:
2905 case VMX_EXIT_VMREAD:
2906 case VMX_EXIT_VMWRITE:
2907 case VMX_EXIT_VMXON:
2908 case VMX_EXIT_XRSTORS:
2909 case VMX_EXIT_XSAVES:
2910 case VMX_EXIT_RDRAND:
2911 case VMX_EXIT_RDSEED:
2912 break;
2913 default:
2914 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2915 break;
2916 }
2917#endif
2918
2919 /*
2920 * Update the Exit qualification field with displacement bytes.
2921 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2922 */
2923 /* Construct the VM-exit instruction information. */
2924 RTGCPTR GCPtrDisp;
2925 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2926
2927 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2928 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2929}
2930
2931
2932/**
2933 * VMX VM-exit handler for VM-exits due to INVLPG.
2934 *
2935 * @returns Strict VBox status code.
2936 * @param pVCpu The cross context virtual CPU structure.
2937 * @param GCPtrPage The guest-linear address of the page being invalidated.
2938 * @param cbInstr The instruction length in bytes.
2939 */
2940VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2941{
2942 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2943 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2944 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2945}
2946
2947
2948/**
2949 * VMX VM-exit handler for VM-exits due to LMSW.
2950 *
2951 * @returns Strict VBox status code.
2952 * @param pVCpu The cross context virtual CPU structure.
2953 * @param uGuestCr0 The current guest CR0.
2954 * @param pu16NewMsw The machine-status word specified in LMSW's source
2955 * operand. This will be updated depending on the VMX
2956 * guest/host CR0 mask if LMSW is not intercepted.
2957 * @param GCPtrEffDst The guest-linear address of the source operand in case
2958 * of a memory operand. For register operand, pass
2959 * NIL_RTGCPTR.
2960 * @param cbInstr The instruction length in bytes.
2961 */
2962VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2963 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2964{
2965 Assert(pu16NewMsw);
2966
2967 uint16_t const uNewMsw = *pu16NewMsw;
2968 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2969 {
2970 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2971 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2972 VMXVEXITINFO ExitInfo
2973 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2974 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2975 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2976 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2977 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2978 cbInstr);
2979 if (fMemOperand)
2980 {
2981 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2982 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2983 }
2984 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2985 }
2986
2987 /*
2988 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2989 * CR0 guest/host mask must be left unmodified.
2990 *
2991 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2992 */
2993 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2994 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2995 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2996
2997 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2998}
2999
3000
3001/**
3002 * VMX VM-exit handler for VM-exits due to CLTS.
3003 *
3004 * @returns Strict VBox status code.
3005 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3006 * VM-exit but must not modify the guest CR0.TS bit.
3007 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3008 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3009 * CR0 fixed bits in VMX operation).
3010 * @param pVCpu The cross context virtual CPU structure.
3011 * @param cbInstr The instruction length in bytes.
3012 */
3013VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3014{
3015 /*
3016 * If CR0.TS is owned by the host:
3017 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3018 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3019 * CLTS instruction completes without clearing CR0.TS.
3020 *
3021 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3022 */
3023 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3024 if (fGstHostMask & X86_CR0_TS)
3025 {
3026 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
3027 {
3028 Log2(("clts: Guest intercept -> VM-exit\n"));
3029 VMXVEXITINFO const ExitInfo
3030 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3031 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3032 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3033 VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
3034 cbInstr);
3035 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3036 }
3037 return VINF_VMX_MODIFIES_BEHAVIOR;
3038 }
3039
3040 /*
3041 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3042 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3043 */
3044 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3045}
3046
3047
3048/**
3049 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3050 * (CR0/CR4 write).
3051 *
3052 * @returns Strict VBox status code.
3053 * @param pVCpu The cross context virtual CPU structure.
3054 * @param iCrReg The control register (either CR0 or CR4).
3055 * @param uGuestCrX The current guest CR0/CR4.
3056 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3057 * VM-exit is caused.
3058 * @param iGReg The general register from which the CR0/CR4 value is being
3059 * loaded.
3060 * @param cbInstr The instruction length in bytes.
3061 */
3062VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3063 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3064{
3065 Assert(puNewCrX);
3066 Assert(iCrReg == 0 || iCrReg == 4);
3067 Assert(iGReg < X86_GREG_COUNT);
3068
3069 uint64_t const uNewCrX = *puNewCrX;
3070 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3071 {
3072 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3073 VMXVEXITINFO const ExitInfo
3074 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3075 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3076 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3077 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3078 cbInstr);
3079 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3080 }
3081
3082 /*
3083 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3084 * must not be modified the instruction.
3085 *
3086 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3087 */
3088 uint64_t uGuestCrX;
3089 uint64_t fGstHostMask;
3090 if (iCrReg == 0)
3091 {
3092 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3093 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3094 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3095 }
3096 else
3097 {
3098 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3099 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3100 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3101 }
3102
3103 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3104 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3105}
3106
3107
3108/**
3109 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3110 *
3111 * @returns VBox strict status code.
3112 * @param pVCpu The cross context virtual CPU structure.
3113 * @param iGReg The general register to which the CR3 value is being stored.
3114 * @param cbInstr The instruction length in bytes.
3115 */
3116VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3117{
3118 Assert(iGReg < X86_GREG_COUNT);
3119 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3120
3121 /*
3122 * If the CR3-store exiting control is set, we must cause a VM-exit.
3123 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3124 */
3125 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3126 {
3127 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3128 VMXVEXITINFO const ExitInfo
3129 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3130 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3131 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3132 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3133 cbInstr);
3134 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3135 }
3136 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3137}
3138
3139
3140/**
3141 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3142 *
3143 * @returns VBox strict status code.
3144 * @param pVCpu The cross context virtual CPU structure.
3145 * @param uNewCr3 The new CR3 value.
3146 * @param iGReg The general register from which the CR3 value is being
3147 * loaded.
3148 * @param cbInstr The instruction length in bytes.
3149 */
3150VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3151{
3152 Assert(iGReg < X86_GREG_COUNT);
3153
3154 /*
3155 * If the CR3-load exiting control is set and the new CR3 value does not
3156 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3157 *
3158 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3159 */
3160 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3161 {
3162 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3163 VMXVEXITINFO const ExitInfo
3164 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3165 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3166 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3167 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3168 VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3169 cbInstr);
3170 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3171 }
3172 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3173}
3174
3175
3176/**
3177 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3178 *
3179 * @returns VBox strict status code.
3180 * @param pVCpu The cross context virtual CPU structure.
3181 * @param iGReg The general register to which the CR8 value is being stored.
3182 * @param cbInstr The instruction length in bytes.
3183 */
3184VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3185{
3186 Assert(iGReg < X86_GREG_COUNT);
3187
3188 /*
3189 * If the CR8-store exiting control is set, we must cause a VM-exit.
3190 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3191 */
3192 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3193 {
3194 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3195 VMXVEXITINFO const ExitInfo
3196 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3197 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3198 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3199 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3200 cbInstr);
3201 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3202 }
3203 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3204}
3205
3206
3207/**
3208 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3209 *
3210 * @returns VBox strict status code.
3211 * @param pVCpu The cross context virtual CPU structure.
3212 * @param iGReg The general register from which the CR8 value is being
3213 * loaded.
3214 * @param cbInstr The instruction length in bytes.
3215 */
3216VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3217{
3218 Assert(iGReg < X86_GREG_COUNT);
3219
3220 /*
3221 * If the CR8-load exiting control is set, we must cause a VM-exit.
3222 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3223 */
3224 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3225 {
3226 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3227 VMXVEXITINFO const ExitInfo
3228 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3229 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3230 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3231 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3232 cbInstr);
3233 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3234 }
3235 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3236}
3237
3238
3239/**
3240 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3241 * GReg,DRx' (DRx read).
3242 *
3243 * @returns VBox strict status code.
3244 * @param pVCpu The cross context virtual CPU structure.
3245 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3246 * VMXINSTRID_MOV_FROM_DRX).
3247 * @param iDrReg The debug register being accessed.
3248 * @param iGReg The general register to/from which the DRx value is being
3249 * store/loaded.
3250 * @param cbInstr The instruction length in bytes.
3251 */
3252VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3253 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3254{
3255 Assert(iDrReg <= 7);
3256 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3257 Assert(iGReg < X86_GREG_COUNT);
3258
3259 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3260 {
3261 VMXVEXITINFO const ExitInfo
3262 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3263 RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3264 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3265 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3266 uInstrId == VMXINSTRID_MOV_TO_DRX
3267 ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3268 : VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3269 cbInstr);
3270 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3271 }
3272
3273 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3274}
3275
3276
3277/**
3278 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3279 *
3280 * @returns VBox strict status code.
3281 * @param pVCpu The cross context virtual CPU structure.
3282 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3283 * VMXINSTRID_IO_OUT).
3284 * @param u16Port The I/O port being accessed.
3285 * @param fImm Whether the I/O port was encoded using an immediate operand
3286 * or the implicit DX register.
3287 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3288 * @param cbInstr The instruction length in bytes.
3289 */
3290VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3291 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3292{
3293 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3294 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3295
3296 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3297 {
3298 VMXVEXITINFO const ExitInfo
3299 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3300 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3301 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3302 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3303 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3304 uInstrId == VMXINSTRID_IO_IN
3305 ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3306 : VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3307 cbInstr);
3308 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3309 }
3310 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3311}
3312
3313
3314/**
3315 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3316 *
3317 * @returns VBox strict status code.
3318 * @param pVCpu The cross context virtual CPU structure.
3319 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3320 * VMXINSTRID_IO_OUTS).
3321 * @param u16Port The I/O port being accessed.
3322 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3323 * @param fRep Whether the instruction has a REP prefix or not.
3324 * @param ExitInstrInfo The VM-exit instruction info. field.
3325 * @param cbInstr The instruction length in bytes.
3326 */
3327VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3328 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3329{
3330 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3331 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3332 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3333 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3334 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3335
3336 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3337 {
3338 /*
3339 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3340 */
3341 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3342 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3343 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3344 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3345 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3346
3347 uint32_t uDirection;
3348 uint64_t uGuestLinearAddr;
3349 if (uInstrId == VMXINSTRID_IO_INS)
3350 {
3351 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3352 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3353 }
3354 else
3355 {
3356 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3357 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3358 }
3359
3360 /*
3361 * If the segment is unusable, the guest-linear address in undefined.
3362 * We shall clear it for consistency.
3363 *
3364 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3365 */
3366 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3367 uGuestLinearAddr = 0;
3368
3369 VMXVEXITINFO const ExitInfo
3370 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3371 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3372 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3373 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3374 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3375 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3376 VMX_EXIT_QUAL_IO_ENCODING_DX)
3377 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3378 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3379 ? ExitInstrInfo.u : 0,
3380 cbInstr,
3381 uGuestLinearAddr);
3382 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3383 }
3384
3385 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3386}
3387
3388
3389/**
3390 * VMX VM-exit handler for VM-exits due to MWAIT.
3391 *
3392 * @returns VBox strict status code.
3393 * @param pVCpu The cross context virtual CPU structure.
3394 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3395 * @param cbInstr The instruction length in bytes.
3396 */
3397VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3398{
3399 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3400 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3401}
3402
3403
3404/**
3405 * VMX VM-exit handler for VM-exits due to PAUSE.
3406 *
3407 * @returns VBox strict status code.
3408 * @param pVCpu The cross context virtual CPU structure.
3409 * @param cbInstr The instruction length in bytes.
3410 */
3411static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3412{
3413 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3414
3415 /*
3416 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3417 * "PAUSE-loop exiting" control.
3418 *
3419 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3420 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3421 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3422 * a VM-exit.
3423 *
3424 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3425 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3426 */
3427 bool fIntercept = false;
3428 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3429 fIntercept = true;
3430 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3431 && pVCpu->iem.s.uCpl == 0)
3432 {
3433 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3434
3435 /*
3436 * A previous-PAUSE-tick value of 0 is used to identify the first time
3437 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3438 * consider this to be the first execution of PAUSE in a loop according
3439 * to the Intel.
3440 *
3441 * All subsequent records for the previous-PAUSE-tick we ensure that it
3442 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3443 */
3444 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3445 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3446 uint64_t const uTick = TMCpuTickGet(pVCpu);
3447 uint32_t const uPleGap = pVmcs->u32PleGap;
3448 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3449 if ( *puPrevPauseTick == 0
3450 || uTick - *puPrevPauseTick > uPleGap)
3451 *puFirstPauseLoopTick = uTick;
3452 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3453 fIntercept = true;
3454
3455 *puPrevPauseTick = uTick | 1;
3456 }
3457
3458 if (fIntercept)
3459 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3460
3461 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3462}
3463
3464
3465/**
3466 * VMX VM-exit handler for VM-exits due to task switches.
3467 *
3468 * @returns VBox strict status code.
3469 * @param pVCpu The cross context virtual CPU structure.
3470 * @param enmTaskSwitch The cause of the task switch.
3471 * @param SelNewTss The selector of the new TSS.
3472 * @param cbInstr The instruction length in bytes.
3473 */
3474VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3475{
3476 /*
3477 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3478 *
3479 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3480 * instruction or delivery of the exception generated by one of these instructions
3481 * lead to a task switch through a task gate in the IDT, we need to provide the
3482 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3483 * leaves the VM-exit instruction length field undefined.
3484 *
3485 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3486 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3487 */
3488 Assert(cbInstr <= 15);
3489
3490 uint8_t uType;
3491 switch (enmTaskSwitch)
3492 {
3493 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3494 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3495 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3496 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3497 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3498 }
3499
3500 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3501 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3502 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3503 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3504}
3505
3506
3507/**
3508 * VMX VM-exit handler for trap-like VM-exits.
3509 *
3510 * @returns VBox strict status code.
3511 * @param pVCpu The cross context virtual CPU structure.
3512 * @param pExitInfo Pointer to the VM-exit information.
3513 * @param pExitEventInfo Pointer to the VM-exit event information.
3514 */
3515static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3516{
3517 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3518 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3519 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3520}
3521
3522
3523/**
3524 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3525 * Virtualized-EOI, TPR-below threshold).
3526 *
3527 * @returns Strict VBox status code.
3528 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3529 * @param pExitInfo Pointer to the VM-exit information.
3530 * @thread EMT(pVCpu)
3531 */
3532VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3533{
3534 Assert(pExitInfo);
3535 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3536 Assert(!pVCpu->iem.s.cActiveMappings);
3537 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3538}
3539
3540
3541/**
3542 * VMX VM-exit handler for VM-exits due to task switches.
3543 *
3544 * This is intended for task switches where the caller provides all the relevant
3545 * VM-exit information.
3546 *
3547 * @returns VBox strict status code.
3548 * @param pVCpu The cross context virtual CPU structure.
3549 * @param pExitInfo Pointer to the VM-exit information.
3550 * @param pExitEventInfo Pointer to the VM-exit event information.
3551 */
3552static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3553 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3554{
3555 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3556 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3557 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3558 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3559 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3560}
3561
3562
3563/**
3564 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3565 *
3566 * @returns Strict VBox status code.
3567 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3568 * @param pExitInfo Pointer to the VM-exit information.
3569 * @param pExitEventInfo Pointer to the VM-exit event information.
3570 * @thread EMT(pVCpu)
3571 */
3572VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3573{
3574 Assert(pExitInfo);
3575 Assert(pExitEventInfo);
3576 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3577 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3578 Assert(!pVCpu->iem.s.cActiveMappings);
3579 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3580}
3581
3582
3583/**
3584 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3585 *
3586 * @returns VBox strict status code.
3587 * @param pVCpu The cross context virtual CPU structure.
3588 */
3589VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3590{
3591 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3592 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3593
3594 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3595 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3596
3597 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3598 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3599 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3600
3601 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3602 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3603}
3604
3605
3606/**
3607 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3608 *
3609 * @returns Strict VBox status code.
3610 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3611 * @thread EMT(pVCpu)
3612 */
3613VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3614{
3615 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3616 Assert(!pVCpu->iem.s.cActiveMappings);
3617 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3618}
3619
3620
3621/**
3622 * VMX VM-exit handler for VM-exits due to external interrupts.
3623 *
3624 * @returns VBox strict status code.
3625 * @param pVCpu The cross context virtual CPU structure.
3626 * @param uVector The external interrupt vector (pass 0 if the interrupt
3627 * is still pending since we typically won't know the
3628 * vector).
3629 * @param fIntPending Whether the external interrupt is pending or
3630 * acknowledged in the interrupt controller.
3631 */
3632static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3633{
3634 Assert(!fIntPending || uVector == 0);
3635
3636 /* The VM-exit is subject to "External interrupt exiting" being set. */
3637 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3638 {
3639 if (fIntPending)
3640 {
3641 /*
3642 * If the interrupt is pending and we don't need to acknowledge the
3643 * interrupt on VM-exit, cause the VM-exit immediately.
3644 *
3645 * See Intel spec 25.2 "Other Causes Of VM Exits".
3646 */
3647 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3648 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3649
3650 /*
3651 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3652 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3653 * acknowledged that the interrupt has been consumed. Callers would have to call
3654 * us again after getting the vector (and ofc, with fIntPending with false).
3655 */
3656 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3657 }
3658
3659 /*
3660 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3661 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3662 * all set, we need to record the vector of the external interrupt in the
3663 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3664 *
3665 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3666 */
3667 uint32_t uExitIntInfo;
3668 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3669 {
3670 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3671 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3672 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3673 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3674 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3675 }
3676 else
3677 uExitIntInfo = 0;
3678 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3679
3680 /*
3681 * Cause the VM-exit whether or not the vector has been stored
3682 * in the VM-exit interruption-information field.
3683 */
3684 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3685 }
3686
3687 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3688}
3689
3690
3691/**
3692 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3693 *
3694 * @returns Strict VBox status code.
3695 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3696 * @param uVector The external interrupt vector (pass 0 if the external
3697 * interrupt is still pending).
3698 * @param fIntPending Whether the external interrupt is pending or
3699 * acknowledged in the interrupt controller.
3700 * @thread EMT(pVCpu)
3701 */
3702VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3703{
3704 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3705 Assert(!pVCpu->iem.s.cActiveMappings);
3706 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3707}
3708
3709
3710/**
3711 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3712 * an event.
3713 *
3714 * @returns VBox strict status code.
3715 * @param pVCpu The cross context virtual CPU structure.
3716 */
3717VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3718{
3719 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3720 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3721 {
3722 /*
3723 * The NMI-unblocking due to IRET field need not be set for double faults.
3724 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3725 */
3726 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3727 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3728 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3729 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3730 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3731 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3732 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3733 }
3734
3735 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3736}
3737
3738
3739/**
3740 * VMX VM-exit handler for VM-exit due to delivery of an events.
3741 *
3742 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3743 * all the relevant VM-exit information.
3744 *
3745 * @returns VBox strict status code.
3746 * @param pVCpu The cross context virtual CPU structure.
3747 * @param pExitInfo Pointer to the VM-exit information.
3748 * @param pExitEventInfo Pointer to the VM-exit event information.
3749 */
3750static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3751{
3752 Assert(pExitInfo);
3753 Assert(pExitEventInfo);
3754 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3755 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3756
3757 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3758 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3759 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3760 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3761 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3762 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3763}
3764
3765
3766/**
3767 * Interface for HM and EM to emulate VM-exit due to NMIs.
3768 *
3769 * @returns Strict VBox status code.
3770 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3771 * @thread EMT(pVCpu)
3772 */
3773VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3774{
3775 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3776 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3777 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3778 VMX_EXIT_INT_INFO_TYPE_NMI)
3779 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3780 X86_XCPT_NMI),
3781 0);
3782 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3783 Assert(!pVCpu->iem.s.cActiveMappings);
3784 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3785}
3786
3787
3788/**
3789 * Interface for HM and EM to emulate VM-exit due to exceptions.
3790 *
3791 * Exception includes NMIs, software exceptions (those generated by INT3 or
3792 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3793 *
3794 * @returns Strict VBox status code.
3795 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3796 * @param pExitInfo Pointer to the VM-exit information.
3797 * @param pExitEventInfo Pointer to the VM-exit event information.
3798 * @thread EMT(pVCpu)
3799 */
3800VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3801{
3802 Assert(pExitInfo);
3803 Assert(pExitEventInfo);
3804 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3805 Assert(!pVCpu->iem.s.cActiveMappings);
3806 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3807}
3808
3809
3810/**
3811 * VMX VM-exit handler for VM-exits due to delivery of an event.
3812 *
3813 * @returns VBox strict status code.
3814 * @param pVCpu The cross context virtual CPU structure.
3815 * @param uVector The interrupt / exception vector.
3816 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3817 * @param uErrCode The error code associated with the event.
3818 * @param uCr2 The CR2 value in case of a \#PF exception.
3819 * @param cbInstr The instruction length in bytes.
3820 */
3821VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3822 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3823{
3824 /*
3825 * If the event is being injected as part of VM-entry, it is -not- subject to event
3826 * intercepts in the nested-guest. However, secondary exceptions that occur during
3827 * injection of any event -are- subject to event interception.
3828 *
3829 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3830 */
3831 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3832 {
3833 /*
3834 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3835 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3836 *
3837 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3838 */
3839 if ( uVector == X86_XCPT_NMI
3840 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3841 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3842 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3843 else
3844 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3845
3846 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3847 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3848 }
3849
3850 /*
3851 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3852 * If not, the caller will continue delivery of the external interrupt as it would
3853 * normally. The interrupt is no longer pending in the interrupt controller at this
3854 * point.
3855 */
3856 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3857 {
3858 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3859 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3860 }
3861
3862 /*
3863 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3864 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3865 * interrupts.
3866 */
3867 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3868 bool fIntercept;
3869 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3870 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3871 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3872 else
3873 {
3874 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3875 fIntercept = false;
3876 }
3877
3878 /*
3879 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3880 * relevant VM-exit information and cause the VM-exit.
3881 */
3882 if (fIntercept)
3883 {
3884 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3885
3886 /* Construct the rest of the event related information fields and cause the VM-exit. */
3887 uint64_t u64ExitQual;
3888 if (uVector == X86_XCPT_PF)
3889 {
3890 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3891 u64ExitQual = uCr2;
3892 }
3893 else if (uVector == X86_XCPT_DB)
3894 {
3895 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3896 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3897 }
3898 else
3899 u64ExitQual = 0;
3900
3901 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3902 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3903 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3904 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3905 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3906 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3907 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3908 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3909 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3910 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3911
3912 /*
3913 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3914 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3915 * length.
3916 */
3917 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3918 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3919 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3920 else
3921 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3922
3923 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3924 }
3925
3926 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3927}
3928
3929
3930/**
3931 * VMX VM-exit handler for EPT misconfiguration.
3932 *
3933 * @param pVCpu The cross context virtual CPU structure.
3934 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3935 * This need not be page aligned (e.g. nested-guest in real
3936 * mode).
3937 */
3938static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3939{
3940 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3941 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3942}
3943
3944
3945/**
3946 * VMX VM-exit handler for EPT misconfiguration.
3947 *
3948 * This is intended for EPT misconfigurations where the caller provides all the
3949 * relevant VM-exit information.
3950 *
3951 * @param pVCpu The cross context virtual CPU structure.
3952 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3953 * This need not be page aligned (e.g. nested-guest in real
3954 * mode).
3955 * @param pExitEventInfo Pointer to the VM-exit event information.
3956 */
3957static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3958{
3959 Assert(pExitEventInfo);
3960 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3961 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3962 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3963 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3964 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3965}
3966
3967
3968/**
3969 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3970 *
3971 * @returns Strict VBox status code.
3972 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3973 * @param GCPhysAddr The nested-guest physical address causing the EPT
3974 * misconfiguration.
3975 * @param pExitEventInfo Pointer to the VM-exit event information.
3976 * @thread EMT(pVCpu)
3977 */
3978VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3979{
3980 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3981
3982 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3983 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3984 Assert(!pVCpu->iem.s.cActiveMappings);
3985 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3986}
3987
3988
3989/**
3990 * VMX VM-exit handler for EPT violation.
3991 *
3992 * @param pVCpu The cross context virtual CPU structure.
3993 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3994 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3995 * @param fEptAccess The EPT paging structure bits.
3996 * @param GCPhysAddr The physical address causing the EPT violation. This
3997 * need not be page aligned (e.g. nested-guest in real
3998 * mode).
3999 * @param fIsLinearAddrValid Whether translation of a linear address caused this
4000 * EPT violation. If @c false, GCPtrAddr must be 0.
4001 * @param GCPtrAddr The linear address causing the EPT violation.
4002 * @param cbInstr The VM-exit instruction length.
4003 */
4004static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
4005 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
4006 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
4007{
4008 /*
4009 * If the linear address isn't valid (can happen when loading PDPTEs
4010 * as part of MOV CR execution) the linear address field is undefined.
4011 * While we can leave it this way, it's preferable to zero it for consistency.
4012 */
4013 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
4014
4015 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
4016 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
4017
4018 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
4019 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
4020 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
4021 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
4022 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
4023 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
4024 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
4025 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
4026 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
4027 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4028 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
4029
4030 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
4031 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
4032 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
4033 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
4034 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4035 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4036 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4037 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4038 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4039
4040#ifdef VBOX_STRICT
4041 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4042 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4043 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4044 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4045 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4046 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4047#endif
4048
4049 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4050 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4051 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4052
4053 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4054}
4055
4056
4057/**
4058 * VMX VM-exit handler for EPT violation.
4059 *
4060 * This is intended for EPT violations where the caller provides all the
4061 * relevant VM-exit information.
4062 *
4063 * @returns VBox strict status code.
4064 * @param pVCpu The cross context virtual CPU structure.
4065 * @param pExitInfo Pointer to the VM-exit information.
4066 * @param pExitEventInfo Pointer to the VM-exit event information.
4067 */
4068static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4069 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4070{
4071 Assert(pExitInfo);
4072 Assert(pExitEventInfo);
4073 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4074 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4075
4076 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4077 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4078
4079 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4080 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4081 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4082 else
4083 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4084 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4085 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4086}
4087
4088
4089/**
4090 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4091 *
4092 * @returns Strict VBox status code.
4093 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4094 * @param pExitInfo Pointer to the VM-exit information.
4095 * @param pExitEventInfo Pointer to the VM-exit event information.
4096 * @thread EMT(pVCpu)
4097 */
4098VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4099 PCVMXVEXITEVENTINFO pExitEventInfo)
4100{
4101 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4102
4103 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4104 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4105 Assert(!pVCpu->iem.s.cActiveMappings);
4106 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4107}
4108
4109
4110/**
4111 * VMX VM-exit handler for EPT-induced VM-exits.
4112 *
4113 * @param pVCpu The cross context virtual CPU structure.
4114 * @param pWalk The page walk info.
4115 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4116 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4117 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4118 * applicable.
4119 */
4120VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4121{
4122 Assert(pWalk->fIsSlat);
4123 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4124 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4125 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4126
4127 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4128 {
4129 LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4130 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4131 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4132 pWalk->GCPtr, cbInstr);
4133 }
4134
4135 LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4136 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4137 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4138}
4139
4140
4141/**
4142 * VMX VM-exit handler for APIC accesses.
4143 *
4144 * @param pVCpu The cross context virtual CPU structure.
4145 * @param offAccess The offset of the register being accessed.
4146 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4147 */
4148static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4149{
4150 VMXAPICACCESS enmAccess;
4151 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4152 if (fInEventDelivery)
4153 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4154 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4155 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4156 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4157 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4158 else
4159 enmAccess = VMXAPICACCESS_LINEAR_READ;
4160
4161 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4162 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4163 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4164}
4165
4166
4167/**
4168 * VMX VM-exit handler for APIC accesses.
4169 *
4170 * This is intended for APIC accesses where the caller provides all the
4171 * relevant VM-exit information.
4172 *
4173 * @returns VBox strict status code.
4174 * @param pVCpu The cross context virtual CPU structure.
4175 * @param pExitInfo Pointer to the VM-exit information.
4176 * @param pExitEventInfo Pointer to the VM-exit event information.
4177 */
4178static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4179 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4180{
4181 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4182 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4183 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4184 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4185 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4186 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4187 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4188 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4189 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4190}
4191
4192
4193/**
4194 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4195 *
4196 * @returns Strict VBox status code.
4197 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4198 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4199 *
4200 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4201 * @param pExitInfo Pointer to the VM-exit information.
4202 * @param pExitEventInfo Pointer to the VM-exit event information.
4203 * @thread EMT(pVCpu)
4204 */
4205VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4206{
4207 Assert(pExitInfo);
4208 Assert(pExitEventInfo);
4209 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4210 Assert(!pVCpu->iem.s.cActiveMappings);
4211 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4212}
4213
4214
4215/**
4216 * VMX VM-exit handler for APIC-write VM-exits.
4217 *
4218 * @param pVCpu The cross context virtual CPU structure.
4219 * @param offApic The write to the virtual-APIC page offset that caused this
4220 * VM-exit.
4221 */
4222static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4223{
4224 Assert(offApic < XAPIC_OFF_END + 4);
4225 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4226 offApic &= UINT16_C(0xfff);
4227 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4228}
4229
4230
4231/**
4232 * Clears any pending virtual-APIC write emulation.
4233 *
4234 * @returns The virtual-APIC offset that was written before clearing it.
4235 * @param pVCpu The cross context virtual CPU structure.
4236 */
4237DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4238{
4239 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4240 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4241 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4242 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4243 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4244 return offVirtApicWrite;
4245}
4246
4247
4248/**
4249 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4250 *
4251 * @returns The register from the virtual-APIC page.
4252 * @param pVCpu The cross context virtual CPU structure.
4253 * @param offReg The offset of the register being read.
4254 */
4255uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4256{
4257 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4258
4259 uint32_t uReg = 0;
4260 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4261 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4262 AssertMsgStmt(RT_SUCCESS(rc),
4263 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4264 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4265 uReg = 0);
4266 return uReg;
4267}
4268
4269
4270/**
4271 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4272 *
4273 * @returns The register from the virtual-APIC page.
4274 * @param pVCpu The cross context virtual CPU structure.
4275 * @param offReg The offset of the register being read.
4276 */
4277static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4278{
4279 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4280
4281 uint64_t uReg = 0;
4282 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4283 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4284 AssertMsgStmt(RT_SUCCESS(rc),
4285 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4286 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4287 uReg = 0);
4288 return uReg;
4289}
4290
4291
4292/**
4293 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4294 *
4295 * @param pVCpu The cross context virtual CPU structure.
4296 * @param offReg The offset of the register being written.
4297 * @param uReg The register value to write.
4298 */
4299void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4300{
4301 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4302
4303 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4304 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4305 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4306 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4307}
4308
4309
4310/**
4311 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4312 *
4313 * @param pVCpu The cross context virtual CPU structure.
4314 * @param offReg The offset of the register being written.
4315 * @param uReg The register value to write.
4316 */
4317static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4318{
4319 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4320
4321 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4322 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4323 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4324 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4325}
4326
4327
4328/**
4329 * Sets the vector in a virtual-APIC 256-bit sparse register.
4330 *
4331 * @param pVCpu The cross context virtual CPU structure.
4332 * @param offReg The offset of the 256-bit spare register.
4333 * @param uVector The vector to set.
4334 *
4335 * @remarks This is based on our APIC device code.
4336 */
4337static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4338{
4339 /* Determine the vector offset within the chunk. */
4340 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4341
4342 /* Read the chunk at the offset. */
4343 uint32_t uReg;
4344 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4345 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4346 if (RT_SUCCESS(rc))
4347 {
4348 /* Modify the chunk. */
4349 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4350 uReg |= RT_BIT(idxVectorBit);
4351
4352 /* Write the chunk. */
4353 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4354 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4355 uVector, offReg, GCPhysVirtApic, rc));
4356 }
4357 else
4358 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4359 uVector, offReg, GCPhysVirtApic, rc));
4360}
4361
4362
4363/**
4364 * Clears the vector in a virtual-APIC 256-bit sparse register.
4365 *
4366 * @param pVCpu The cross context virtual CPU structure.
4367 * @param offReg The offset of the 256-bit spare register.
4368 * @param uVector The vector to clear.
4369 *
4370 * @remarks This is based on our APIC device code.
4371 */
4372static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4373{
4374 /* Determine the vector offset within the chunk. */
4375 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4376
4377 /* Read the chunk at the offset. */
4378 uint32_t uReg;
4379 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4380 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4381 if (RT_SUCCESS(rc))
4382 {
4383 /* Modify the chunk. */
4384 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4385 uReg &= ~RT_BIT(idxVectorBit);
4386
4387 /* Write the chunk. */
4388 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4389 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4390 uVector, offReg, GCPhysVirtApic, rc));
4391 }
4392 else
4393 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4394 uVector, offReg, GCPhysVirtApic, rc));
4395}
4396
4397
4398/**
4399 * Checks if a memory access to the APIC-access page must causes an APIC-access
4400 * VM-exit.
4401 *
4402 * @param pVCpu The cross context virtual CPU structure.
4403 * @param offAccess The offset of the register being accessed.
4404 * @param cbAccess The size of the access in bytes.
4405 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4406 *
4407 * @remarks This must not be used for MSR-based APIC-access page accesses!
4408 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4409 */
4410static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4411{
4412 Assert(cbAccess > 0);
4413 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4414
4415 /*
4416 * We must cause a VM-exit if any of the following are true:
4417 * - TPR shadowing isn't active.
4418 * - The access size exceeds 32-bits.
4419 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4420 *
4421 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4422 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4423 */
4424 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4425 || cbAccess > sizeof(uint32_t)
4426 || ((offAccess + cbAccess - 1) & 0xc)
4427 || offAccess >= XAPIC_OFF_END + 4)
4428 return true;
4429
4430 /*
4431 * If the access is part of an operation where we have already
4432 * virtualized a virtual-APIC write, we must cause a VM-exit.
4433 */
4434 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4435 return true;
4436
4437 /*
4438 * Check write accesses to the APIC-access page that cause VM-exits.
4439 */
4440 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4441 {
4442 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4443 {
4444 /*
4445 * With APIC-register virtualization, a write access to any of the
4446 * following registers are virtualized. Accessing any other register
4447 * causes a VM-exit.
4448 */
4449 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4450 switch (offAlignedAccess)
4451 {
4452 case XAPIC_OFF_ID:
4453 case XAPIC_OFF_TPR:
4454 case XAPIC_OFF_EOI:
4455 case XAPIC_OFF_LDR:
4456 case XAPIC_OFF_DFR:
4457 case XAPIC_OFF_SVR:
4458 case XAPIC_OFF_ESR:
4459 case XAPIC_OFF_ICR_LO:
4460 case XAPIC_OFF_ICR_HI:
4461 case XAPIC_OFF_LVT_TIMER:
4462 case XAPIC_OFF_LVT_THERMAL:
4463 case XAPIC_OFF_LVT_PERF:
4464 case XAPIC_OFF_LVT_LINT0:
4465 case XAPIC_OFF_LVT_LINT1:
4466 case XAPIC_OFF_LVT_ERROR:
4467 case XAPIC_OFF_TIMER_ICR:
4468 case XAPIC_OFF_TIMER_DCR:
4469 break;
4470 default:
4471 return true;
4472 }
4473 }
4474 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4475 {
4476 /*
4477 * With virtual-interrupt delivery, a write access to any of the
4478 * following registers are virtualized. Accessing any other register
4479 * causes a VM-exit.
4480 *
4481 * Note! The specification does not allow writing to offsets in-between
4482 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4483 */
4484 switch (offAccess)
4485 {
4486 case XAPIC_OFF_TPR:
4487 case XAPIC_OFF_EOI:
4488 case XAPIC_OFF_ICR_LO:
4489 break;
4490 default:
4491 return true;
4492 }
4493 }
4494 else
4495 {
4496 /*
4497 * Without APIC-register virtualization or virtual-interrupt delivery,
4498 * only TPR accesses are virtualized.
4499 */
4500 if (offAccess == XAPIC_OFF_TPR)
4501 { /* likely */ }
4502 else
4503 return true;
4504 }
4505 }
4506 else
4507 {
4508 /*
4509 * Check read accesses to the APIC-access page that cause VM-exits.
4510 */
4511 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4512 {
4513 /*
4514 * With APIC-register virtualization, a read access to any of the
4515 * following registers are virtualized. Accessing any other register
4516 * causes a VM-exit.
4517 */
4518 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4519 switch (offAlignedAccess)
4520 {
4521 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4522 case XAPIC_OFF_ID:
4523 case XAPIC_OFF_VERSION:
4524 case XAPIC_OFF_TPR:
4525 case XAPIC_OFF_EOI:
4526 case XAPIC_OFF_LDR:
4527 case XAPIC_OFF_DFR:
4528 case XAPIC_OFF_SVR:
4529 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4530 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4531 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4532 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4533 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4534 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4535 case XAPIC_OFF_ESR:
4536 case XAPIC_OFF_ICR_LO:
4537 case XAPIC_OFF_ICR_HI:
4538 case XAPIC_OFF_LVT_TIMER:
4539 case XAPIC_OFF_LVT_THERMAL:
4540 case XAPIC_OFF_LVT_PERF:
4541 case XAPIC_OFF_LVT_LINT0:
4542 case XAPIC_OFF_LVT_LINT1:
4543 case XAPIC_OFF_LVT_ERROR:
4544 case XAPIC_OFF_TIMER_ICR:
4545 case XAPIC_OFF_TIMER_DCR:
4546 break;
4547 default:
4548 return true;
4549 }
4550 }
4551 else
4552 {
4553 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4554 if (offAccess == XAPIC_OFF_TPR)
4555 { /* likely */ }
4556 else
4557 return true;
4558 }
4559 }
4560
4561 /* The APIC access is virtualized, does not cause a VM-exit. */
4562 return false;
4563}
4564
4565
4566/**
4567 * Virtualizes a memory-based APIC access by certain instructions even though they
4568 * do not use the address to access memory.
4569 *
4570 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4571 * page-faults but do not use the address to access memory.
4572 *
4573 * @param pVCpu The cross context virtual CPU structure.
4574 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4575 * @param cbAccess The size of the access in bytes.
4576 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4577 */
4578VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4579{
4580 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4581 Assert(pGCPhysAccess);
4582
4583 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4584 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4585 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4586
4587 if (GCPhysAccess == GCPhysApic)
4588 {
4589 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4590 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4591 if (fIntercept)
4592 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4593
4594 *pGCPhysAccess = GCPhysApic | offAccess;
4595 return VINF_VMX_MODIFIES_BEHAVIOR;
4596 }
4597
4598 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4599}
4600
4601
4602/**
4603 * Virtualizes a memory-based APIC access.
4604 *
4605 * @returns VBox strict status code.
4606 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4607 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4608 *
4609 * @param pVCpu The cross context virtual CPU structure.
4610 * @param offAccess The offset of the register being accessed (within the
4611 * APIC-access page).
4612 * @param cbAccess The size of the access in bytes.
4613 * @param pvData Pointer to the data being written or where to store the data
4614 * being read.
4615 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4616 */
4617static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4618 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4619{
4620 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4621 Assert(pvData);
4622
4623 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4624 if (fIntercept)
4625 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4626
4627 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4628 {
4629 /*
4630 * A write access to the APIC-access page that is virtualized (rather than
4631 * causing a VM-exit) writes data to the virtual-APIC page.
4632 */
4633 uint32_t const u32Data = *(uint32_t *)pvData;
4634 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4635
4636 /*
4637 * Record the currently updated APIC offset, as we need this later for figuring
4638 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4639 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4640 *
4641 * After completion of the current operation, we need to perform TPR virtualization,
4642 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4643 *
4644 * The current operation may be a REP-prefixed string instruction, execution of any
4645 * other instruction, or delivery of an event through the IDT.
4646 *
4647 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4648 * performed now but later after completion of the current operation.
4649 *
4650 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4651 */
4652 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4653
4654 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4655 }
4656 else
4657 {
4658 /*
4659 * A read access from the APIC-access page that is virtualized (rather than
4660 * causing a VM-exit) returns data from the virtual-APIC page.
4661 *
4662 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4663 */
4664 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4665
4666 Assert(cbAccess <= 4);
4667 Assert(offAccess < XAPIC_OFF_END + 4);
4668 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4669
4670 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4671 u32Data &= s_auAccessSizeMasks[cbAccess];
4672 *(uint32_t *)pvData = u32Data;
4673
4674 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4675 }
4676
4677 return VINF_VMX_MODIFIES_BEHAVIOR;
4678}
4679
4680
4681/**
4682 * Virtualizes an MSR-based APIC read access.
4683 *
4684 * @returns VBox strict status code.
4685 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4686 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4687 * handled by the x2APIC device.
4688 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4689 * not within the range of valid MSRs, caller must raise \#GP(0).
4690 * @param pVCpu The cross context virtual CPU structure.
4691 * @param idMsr The x2APIC MSR being read.
4692 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4693 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4694 */
4695static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4696{
4697 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4698 Assert(pu64Value);
4699
4700 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4701 {
4702 if ( idMsr >= MSR_IA32_X2APIC_START
4703 && idMsr <= MSR_IA32_X2APIC_END)
4704 {
4705 uint16_t const offReg = (idMsr & 0xff) << 4;
4706 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4707 *pu64Value = u64Value;
4708 return VINF_VMX_MODIFIES_BEHAVIOR;
4709 }
4710 return VERR_OUT_OF_RANGE;
4711 }
4712
4713 if (idMsr == MSR_IA32_X2APIC_TPR)
4714 {
4715 uint16_t const offReg = (idMsr & 0xff) << 4;
4716 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4717 *pu64Value = u64Value;
4718 return VINF_VMX_MODIFIES_BEHAVIOR;
4719 }
4720
4721 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4722}
4723
4724
4725/**
4726 * Virtualizes an MSR-based APIC write access.
4727 *
4728 * @returns VBox strict status code.
4729 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4730 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4731 * not within the range of valid MSRs, caller must raise \#GP(0).
4732 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4733 *
4734 * @param pVCpu The cross context virtual CPU structure.
4735 * @param idMsr The x2APIC MSR being written.
4736 * @param u64Value The value of the x2APIC MSR being written.
4737 */
4738static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4739{
4740 /*
4741 * Check if the access is to be virtualized.
4742 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4743 */
4744 if ( idMsr == MSR_IA32_X2APIC_TPR
4745 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4746 && ( idMsr == MSR_IA32_X2APIC_EOI
4747 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4748 {
4749 /* Validate the MSR write depending on the register. */
4750 switch (idMsr)
4751 {
4752 case MSR_IA32_X2APIC_TPR:
4753 case MSR_IA32_X2APIC_SELF_IPI:
4754 {
4755 if (u64Value & UINT64_C(0xffffffffffffff00))
4756 return VERR_OUT_OF_RANGE;
4757 break;
4758 }
4759 case MSR_IA32_X2APIC_EOI:
4760 {
4761 if (u64Value != 0)
4762 return VERR_OUT_OF_RANGE;
4763 break;
4764 }
4765 }
4766
4767 /* Write the MSR to the virtual-APIC page. */
4768 uint16_t const offReg = (idMsr & 0xff) << 4;
4769 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4770
4771 /*
4772 * Record the currently updated APIC offset, as we need this later for figuring
4773 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4774 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4775 */
4776 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4777
4778 return VINF_VMX_MODIFIES_BEHAVIOR;
4779 }
4780
4781 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4782}
4783
4784
4785/**
4786 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4787 *
4788 * @returns Strict VBox status code.
4789 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4790 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4791 * the x2APIC device.
4792 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4793 *
4794 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4795 * @param idMsr The MSR being read.
4796 * @param pu64Value Pointer to the value being written or where to store the
4797 * value being read.
4798 * @param fWrite Whether this is an MSR write or read access.
4799 * @thread EMT(pVCpu)
4800 */
4801VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4802{
4803 Assert(pu64Value);
4804
4805 VBOXSTRICTRC rcStrict;
4806 if (fWrite)
4807 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4808 else
4809 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4810 Assert(!pVCpu->iem.s.cActiveMappings);
4811 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4812
4813}
4814
4815
4816/**
4817 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4818 *
4819 * @returns VBox status code.
4820 * @retval VINF_SUCCESS when the highest set bit is found.
4821 * @retval VERR_NOT_FOUND when no bit is set.
4822 *
4823 * @param pVCpu The cross context virtual CPU structure.
4824 * @param offReg The offset of the APIC 256-bit sparse register.
4825 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4826 * set in the register. Only valid when VINF_SUCCESS is
4827 * returned.
4828 *
4829 * @remarks The format of the 256-bit sparse register here mirrors that found in
4830 * real APIC hardware.
4831 */
4832static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4833{
4834 Assert(offReg < XAPIC_OFF_END + 4);
4835 Assert(pidxHighestBit);
4836
4837 /*
4838 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4839 * However, in each fragment only the first 4 bytes are used.
4840 */
4841 uint8_t const cFrags = 8;
4842 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4843 {
4844 uint16_t const offFrag = iFrag * 16;
4845 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4846 if (!u32Frag)
4847 continue;
4848
4849 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4850 Assert(idxHighestBit > 0);
4851 --idxHighestBit;
4852 Assert(idxHighestBit <= UINT8_MAX);
4853 *pidxHighestBit = idxHighestBit;
4854 return VINF_SUCCESS;
4855 }
4856 return VERR_NOT_FOUND;
4857}
4858
4859
4860/**
4861 * Evaluates pending virtual interrupts.
4862 *
4863 * @param pVCpu The cross context virtual CPU structure.
4864 */
4865static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4866{
4867 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4868
4869 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4870 {
4871 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4872 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4873
4874 if ((uRvi >> 4) > (uPpr >> 4))
4875 {
4876 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4877 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4878 }
4879 else
4880 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4881 }
4882}
4883
4884
4885/**
4886 * Performs PPR virtualization.
4887 *
4888 * @returns VBox strict status code.
4889 * @param pVCpu The cross context virtual CPU structure.
4890 */
4891static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4892{
4893 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4894 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4895
4896 /*
4897 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4898 * or EOI-virtualization.
4899 *
4900 * See Intel spec. 29.1.3 "PPR Virtualization".
4901 */
4902 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4903 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4904
4905 uint32_t uPpr;
4906 if ((uTpr & 0xf0) >= uSvi)
4907 uPpr = uTpr;
4908 else
4909 uPpr = uSvi;
4910
4911 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4912 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4913}
4914
4915
4916/**
4917 * Performs VMX TPR virtualization.
4918 *
4919 * @returns VBox strict status code.
4920 * @param pVCpu The cross context virtual CPU structure.
4921 */
4922static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4923{
4924 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4925
4926 /*
4927 * We should have already performed the virtual-APIC write to the TPR offset
4928 * in the virtual-APIC page. We now perform TPR virtualization.
4929 *
4930 * See Intel spec. 29.1.2 "TPR Virtualization".
4931 */
4932 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4933 {
4934 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4935 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4936
4937 /*
4938 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4939 * See Intel spec. 29.1.2 "TPR Virtualization".
4940 */
4941 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4942 {
4943 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4944 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4945 }
4946 }
4947 else
4948 {
4949 iemVmxPprVirtualization(pVCpu);
4950 iemVmxEvalPendingVirtIntrs(pVCpu);
4951 }
4952
4953 return VINF_SUCCESS;
4954}
4955
4956
4957/**
4958 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4959 * not.
4960 *
4961 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4962 * @param pVCpu The cross context virtual CPU structure.
4963 * @param uVector The interrupt that was acknowledged using an EOI.
4964 */
4965static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4966{
4967 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4968 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4969
4970 if (uVector < 64)
4971 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4972 if (uVector < 128)
4973 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4974 if (uVector < 192)
4975 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4976 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4977}
4978
4979
4980/**
4981 * Performs EOI virtualization.
4982 *
4983 * @returns VBox strict status code.
4984 * @param pVCpu The cross context virtual CPU structure.
4985 */
4986static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4987{
4988 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4989 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4990
4991 /*
4992 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4993 * and get the next guest-interrupt that's in-service (if any).
4994 *
4995 * See Intel spec. 29.1.4 "EOI Virtualization".
4996 */
4997 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4998 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4999 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
5000
5001 uint8_t uVector = uSvi;
5002 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
5003
5004 uVector = 0;
5005 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
5006
5007 if (uVector)
5008 Log2(("eoi_virt: next interrupt %#x\n", uVector));
5009 else
5010 Log2(("eoi_virt: no interrupt pending in ISR\n"));
5011
5012 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
5013 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5014
5015 iemVmxPprVirtualization(pVCpu);
5016 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5017 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
5018 iemVmxEvalPendingVirtIntrs(pVCpu);
5019 return VINF_SUCCESS;
5020}
5021
5022
5023/**
5024 * Performs self-IPI virtualization.
5025 *
5026 * @returns VBox strict status code.
5027 * @param pVCpu The cross context virtual CPU structure.
5028 */
5029static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
5030{
5031 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5032 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5033
5034 /*
5035 * We should have already performed the virtual-APIC write to the self-IPI offset
5036 * in the virtual-APIC page. We now perform self-IPI virtualization.
5037 *
5038 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5039 */
5040 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5041 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5042 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5043 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5044 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5045 if (uVector > uRvi)
5046 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5047 iemVmxEvalPendingVirtIntrs(pVCpu);
5048 return VINF_SUCCESS;
5049}
5050
5051
5052/**
5053 * Performs VMX APIC-write emulation.
5054 *
5055 * @returns VBox strict status code.
5056 * @param pVCpu The cross context virtual CPU structure.
5057 */
5058VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5059{
5060 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5061
5062 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5063 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5064
5065 /*
5066 * Perform APIC-write emulation based on the virtual-APIC register written.
5067 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5068 */
5069 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5070 VBOXSTRICTRC rcStrict;
5071 switch (offApicWrite)
5072 {
5073 case XAPIC_OFF_TPR:
5074 {
5075 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5076 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5077 uTpr &= UINT32_C(0x000000ff);
5078 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5079 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5080 rcStrict = iemVmxTprVirtualization(pVCpu);
5081 break;
5082 }
5083
5084 case XAPIC_OFF_EOI:
5085 {
5086 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5087 {
5088 /* Clear VEOI and perform EOI virtualization. */
5089 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5090 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5091 rcStrict = iemVmxEoiVirtualization(pVCpu);
5092 }
5093 else
5094 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5095 break;
5096 }
5097
5098 case XAPIC_OFF_ICR_LO:
5099 {
5100 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5101 {
5102 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5103 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5104 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5105 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5106 if ( !(uIcrLo & fIcrLoMb0)
5107 && (uIcrLo & fIcrLoMb1))
5108 {
5109 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5110 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5111 }
5112 else
5113 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5114 }
5115 else
5116 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5117 break;
5118 }
5119
5120 case XAPIC_OFF_ICR_HI:
5121 {
5122 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5123 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5124 uIcrHi &= UINT32_C(0xff000000);
5125 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5126 rcStrict = VINF_SUCCESS;
5127 break;
5128 }
5129
5130 default:
5131 {
5132 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5133 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5134 break;
5135 }
5136 }
5137
5138 return rcStrict;
5139}
5140
5141
5142/**
5143 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5144 * VM-exit.
5145 *
5146 * @returns Strict VBox status code.
5147 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5148 * @thread EMT(pVCpu)
5149 */
5150VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5151{
5152 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5153 Assert(!pVCpu->iem.s.cActiveMappings);
5154 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5155}
5156
5157
5158/**
5159 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5160 *
5161 * @param pVCpu The cross context virtual CPU structure.
5162 * @param pszInstr The VMX instruction name (for logging purposes).
5163 */
5164DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5165{
5166 /*
5167 * Guest Control Registers, Debug Registers, and MSRs.
5168 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5169 */
5170 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5171 const char * const pszFailure = "VM-exit";
5172 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5173
5174 /* CR0 reserved bits. */
5175 {
5176 /* CR0 MB1 bits. */
5177 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
5178 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5179 { /* likely */ }
5180 else
5181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5182
5183 /* CR0 MBZ bits. */
5184 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5185 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5186 { /* likely */ }
5187 else
5188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5189
5190 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5191 if ( !fUnrestrictedGuest
5192 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5193 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5195 }
5196
5197 /* CR4 reserved bits. */
5198 {
5199 /* CR4 MB1 bits. */
5200 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5201 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5202 { /* likely */ }
5203 else
5204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5205
5206 /* CR4 MBZ bits. */
5207 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5208 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5209 { /* likely */ }
5210 else
5211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5212 }
5213
5214 /* DEBUGCTL MSR. */
5215 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5216 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5217 { /* likely */ }
5218 else
5219 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5220
5221 /* 64-bit CPU checks. */
5222 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5223 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5224 {
5225 if (fGstInLongMode)
5226 {
5227 /* PAE must be set. */
5228 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5229 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5230 { /* likely */ }
5231 else
5232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5233 }
5234 else
5235 {
5236 /* PCIDE should not be set. */
5237 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5238 { /* likely */ }
5239 else
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5241 }
5242
5243 /* CR3. */
5244 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5245 { /* likely */ }
5246 else
5247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5248
5249 /* DR7. */
5250 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5251 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5252 { /* likely */ }
5253 else
5254 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5255
5256 /* SYSENTER ESP and SYSENTER EIP. */
5257 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5258 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5259 { /* likely */ }
5260 else
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5262 }
5263
5264 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5265 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5266
5267 /* PAT MSR. */
5268 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5269 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5270 { /* likely */ }
5271 else
5272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5273
5274 /* EFER MSR. */
5275 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5276 {
5277 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5278 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5279 { /* likely */ }
5280 else
5281 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5282
5283 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5284 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5285 if ( fGstLma == fGstInLongMode
5286 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5287 || fGstLma == fGstLme))
5288 { /* likely */ }
5289 else
5290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5291 }
5292
5293 /* We don't support IA32_BNDCFGS MSR yet. */
5294 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5295
5296 NOREF(pszInstr);
5297 NOREF(pszFailure);
5298 return VINF_SUCCESS;
5299}
5300
5301
5302/**
5303 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5304 *
5305 * @param pVCpu The cross context virtual CPU structure.
5306 * @param pszInstr The VMX instruction name (for logging purposes).
5307 */
5308DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5309{
5310 /*
5311 * Segment registers.
5312 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5313 */
5314 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5315 const char * const pszFailure = "VM-exit";
5316 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5317 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5318 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5319
5320 /* Selectors. */
5321 if ( !fGstInV86Mode
5322 && !fUnrestrictedGuest
5323 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5325
5326 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5327 {
5328 CPUMSELREG SelReg;
5329 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5330 if (RT_LIKELY(rc == VINF_SUCCESS))
5331 { /* likely */ }
5332 else
5333 return rc;
5334
5335 /*
5336 * Virtual-8086 mode checks.
5337 */
5338 if (fGstInV86Mode)
5339 {
5340 /* Base address. */
5341 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5342 { /* likely */ }
5343 else
5344 {
5345 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5346 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5347 }
5348
5349 /* Limit. */
5350 if (SelReg.u32Limit == 0xffff)
5351 { /* likely */ }
5352 else
5353 {
5354 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5355 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5356 }
5357
5358 /* Attribute. */
5359 if (SelReg.Attr.u == 0xf3)
5360 { /* likely */ }
5361 else
5362 {
5363 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5364 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5365 }
5366
5367 /* We're done; move to checking the next segment. */
5368 continue;
5369 }
5370
5371 /* Checks done by 64-bit CPUs. */
5372 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5373 {
5374 /* Base address. */
5375 if ( iSegReg == X86_SREG_FS
5376 || iSegReg == X86_SREG_GS)
5377 {
5378 if (X86_IS_CANONICAL(SelReg.u64Base))
5379 { /* likely */ }
5380 else
5381 {
5382 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5384 }
5385 }
5386 else if (iSegReg == X86_SREG_CS)
5387 {
5388 if (!RT_HI_U32(SelReg.u64Base))
5389 { /* likely */ }
5390 else
5391 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5392 }
5393 else
5394 {
5395 if ( SelReg.Attr.n.u1Unusable
5396 || !RT_HI_U32(SelReg.u64Base))
5397 { /* likely */ }
5398 else
5399 {
5400 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5401 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5402 }
5403 }
5404 }
5405
5406 /*
5407 * Checks outside Virtual-8086 mode.
5408 */
5409 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5410 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5411 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5412 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5413 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5414 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5415 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5416 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5417
5418 /* Code or usable segment. */
5419 if ( iSegReg == X86_SREG_CS
5420 || fUsable)
5421 {
5422 /* Reserved bits (bits 31:17 and bits 11:8). */
5423 if (!(SelReg.Attr.u & 0xfffe0f00))
5424 { /* likely */ }
5425 else
5426 {
5427 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5429 }
5430
5431 /* Descriptor type. */
5432 if (fCodeDataSeg)
5433 { /* likely */ }
5434 else
5435 {
5436 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5437 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5438 }
5439
5440 /* Present. */
5441 if (fPresent)
5442 { /* likely */ }
5443 else
5444 {
5445 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5447 }
5448
5449 /* Granularity. */
5450 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5451 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5452 { /* likely */ }
5453 else
5454 {
5455 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5456 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5457 }
5458 }
5459
5460 if (iSegReg == X86_SREG_CS)
5461 {
5462 /* Segment Type and DPL. */
5463 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5464 && fUnrestrictedGuest)
5465 {
5466 if (uDpl == 0)
5467 { /* likely */ }
5468 else
5469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5470 }
5471 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5472 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5473 {
5474 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5475 if (uDpl == AttrSs.n.u2Dpl)
5476 { /* likely */ }
5477 else
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5479 }
5480 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5481 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5482 {
5483 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5484 if (uDpl <= AttrSs.n.u2Dpl)
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5488 }
5489 else
5490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5491
5492 /* Def/Big. */
5493 if ( fGstInLongMode
5494 && fSegLong)
5495 {
5496 if (uDefBig == 0)
5497 { /* likely */ }
5498 else
5499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5500 }
5501 }
5502 else if (iSegReg == X86_SREG_SS)
5503 {
5504 /* Segment Type. */
5505 if ( !fUsable
5506 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5507 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5508 { /* likely */ }
5509 else
5510 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5511
5512 /* DPL. */
5513 if (!fUnrestrictedGuest)
5514 {
5515 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5516 { /* likely */ }
5517 else
5518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5519 }
5520 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5521 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5522 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5523 {
5524 if (uDpl == 0)
5525 { /* likely */ }
5526 else
5527 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5528 }
5529 }
5530 else
5531 {
5532 /* DS, ES, FS, GS. */
5533 if (fUsable)
5534 {
5535 /* Segment type. */
5536 if (uSegType & X86_SEL_TYPE_ACCESSED)
5537 { /* likely */ }
5538 else
5539 {
5540 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5541 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5542 }
5543
5544 if ( !(uSegType & X86_SEL_TYPE_CODE)
5545 || (uSegType & X86_SEL_TYPE_READ))
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5549
5550 /* DPL. */
5551 if ( !fUnrestrictedGuest
5552 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5553 {
5554 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5555 { /* likely */ }
5556 else
5557 {
5558 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5560 }
5561 }
5562 }
5563 }
5564 }
5565
5566 /*
5567 * LDTR.
5568 */
5569 {
5570 CPUMSELREG Ldtr;
5571 Ldtr.Sel = pVmcs->GuestLdtr;
5572 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5573 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5574 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5575
5576 if (!Ldtr.Attr.n.u1Unusable)
5577 {
5578 /* Selector. */
5579 if (!(Ldtr.Sel & X86_SEL_LDT))
5580 { /* likely */ }
5581 else
5582 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5583
5584 /* Base. */
5585 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5586 {
5587 if (X86_IS_CANONICAL(Ldtr.u64Base))
5588 { /* likely */ }
5589 else
5590 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5591 }
5592
5593 /* Attributes. */
5594 /* Reserved bits (bits 31:17 and bits 11:8). */
5595 if (!(Ldtr.Attr.u & 0xfffe0f00))
5596 { /* likely */ }
5597 else
5598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5599
5600 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5601 { /* likely */ }
5602 else
5603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5604
5605 if (!Ldtr.Attr.n.u1DescType)
5606 { /* likely */ }
5607 else
5608 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5609
5610 if (Ldtr.Attr.n.u1Present)
5611 { /* likely */ }
5612 else
5613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5614
5615 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5616 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5617 { /* likely */ }
5618 else
5619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5620 }
5621 }
5622
5623 /*
5624 * TR.
5625 */
5626 {
5627 CPUMSELREG Tr;
5628 Tr.Sel = pVmcs->GuestTr;
5629 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5630 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5631 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5632
5633 /* Selector. */
5634 if (!(Tr.Sel & X86_SEL_LDT))
5635 { /* likely */ }
5636 else
5637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5638
5639 /* Base. */
5640 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5641 {
5642 if (X86_IS_CANONICAL(Tr.u64Base))
5643 { /* likely */ }
5644 else
5645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5646 }
5647
5648 /* Attributes. */
5649 /* Reserved bits (bits 31:17 and bits 11:8). */
5650 if (!(Tr.Attr.u & 0xfffe0f00))
5651 { /* likely */ }
5652 else
5653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5654
5655 if (!Tr.Attr.n.u1Unusable)
5656 { /* likely */ }
5657 else
5658 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5659
5660 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5661 || ( !fGstInLongMode
5662 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5663 { /* likely */ }
5664 else
5665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5666
5667 if (!Tr.Attr.n.u1DescType)
5668 { /* likely */ }
5669 else
5670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5671
5672 if (Tr.Attr.n.u1Present)
5673 { /* likely */ }
5674 else
5675 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5676
5677 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5678 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5679 { /* likely */ }
5680 else
5681 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5682 }
5683
5684 NOREF(pszInstr);
5685 NOREF(pszFailure);
5686 return VINF_SUCCESS;
5687}
5688
5689
5690/**
5691 * Checks guest GDTR and IDTR as part of VM-entry.
5692 *
5693 * @param pVCpu The cross context virtual CPU structure.
5694 * @param pszInstr The VMX instruction name (for logging purposes).
5695 */
5696DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5697{
5698 /*
5699 * GDTR and IDTR.
5700 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5701 */
5702 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5703 const char *const pszFailure = "VM-exit";
5704
5705 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5706 {
5707 /* Base. */
5708 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5709 { /* likely */ }
5710 else
5711 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5712
5713 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5714 { /* likely */ }
5715 else
5716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5717 }
5718
5719 /* Limit. */
5720 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5721 { /* likely */ }
5722 else
5723 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5724
5725 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5726 { /* likely */ }
5727 else
5728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5729
5730 NOREF(pszInstr);
5731 NOREF(pszFailure);
5732 return VINF_SUCCESS;
5733}
5734
5735
5736/**
5737 * Checks guest RIP and RFLAGS as part of VM-entry.
5738 *
5739 * @param pVCpu The cross context virtual CPU structure.
5740 * @param pszInstr The VMX instruction name (for logging purposes).
5741 */
5742DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5743{
5744 /*
5745 * RIP and RFLAGS.
5746 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5747 */
5748 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5749 const char *const pszFailure = "VM-exit";
5750 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5751
5752 /* RIP. */
5753 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5754 {
5755 X86DESCATTR AttrCs;
5756 AttrCs.u = pVmcs->u32GuestCsAttr;
5757 if ( !fGstInLongMode
5758 || !AttrCs.n.u1Long)
5759 {
5760 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5761 { /* likely */ }
5762 else
5763 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5764 }
5765
5766 if ( fGstInLongMode
5767 && AttrCs.n.u1Long)
5768 {
5769 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5770 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5771 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5772 { /* likely */ }
5773 else
5774 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5775 }
5776 }
5777
5778 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5779 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5780 : pVmcs->u64GuestRFlags.s.Lo;
5781 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5782 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5783 { /* likely */ }
5784 else
5785 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5786
5787 if (!(uGuestRFlags & X86_EFL_VM))
5788 { /* likely */ }
5789 else
5790 {
5791 if ( fGstInLongMode
5792 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5793 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5794 }
5795
5796 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5797 {
5798 if (uGuestRFlags & X86_EFL_IF)
5799 { /* likely */ }
5800 else
5801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5802 }
5803
5804 NOREF(pszInstr);
5805 NOREF(pszFailure);
5806 return VINF_SUCCESS;
5807}
5808
5809
5810/**
5811 * Checks guest non-register state as part of VM-entry.
5812 *
5813 * @param pVCpu The cross context virtual CPU structure.
5814 * @param pszInstr The VMX instruction name (for logging purposes).
5815 */
5816DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5817{
5818 /*
5819 * Guest non-register state.
5820 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5821 */
5822 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5823 const char *const pszFailure = "VM-exit";
5824
5825 /*
5826 * Activity state.
5827 */
5828 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5829 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5830 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5831 { /* likely */ }
5832 else
5833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5834
5835 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5836 if ( !AttrSs.n.u2Dpl
5837 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5838 { /* likely */ }
5839 else
5840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5841
5842 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5843 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5844 {
5845 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5846 { /* likely */ }
5847 else
5848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5849 }
5850
5851 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5852 {
5853 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5854 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5855 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5856 switch (pVmcs->u32GuestActivityState)
5857 {
5858 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5859 {
5860 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5861 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5862 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5863 && ( uVector == X86_XCPT_DB
5864 || uVector == X86_XCPT_MC))
5865 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5866 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5867 { /* likely */ }
5868 else
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5870 break;
5871 }
5872
5873 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5874 {
5875 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5876 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5877 && uVector == X86_XCPT_MC))
5878 { /* likely */ }
5879 else
5880 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5881 break;
5882 }
5883
5884 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5885 default:
5886 break;
5887 }
5888 }
5889
5890 /*
5891 * Interruptibility state.
5892 */
5893 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5894 { /* likely */ }
5895 else
5896 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5897
5898 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5899 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5900 { /* likely */ }
5901 else
5902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5903
5904 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5905 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5906 { /* likely */ }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5909
5910 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5911 {
5912 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5913 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5914 {
5915 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5916 { /* likely */ }
5917 else
5918 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5919 }
5920 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5921 {
5922 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5923 { /* likely */ }
5924 else
5925 {
5926 /*
5927 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5928 * We update the Exit qualification only when blocking-by-STI is set
5929 * without blocking-by-MovSS being set. Although in practise it does not
5930 * make much difference since the order of checks are implementation defined.
5931 */
5932 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5933 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5934 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5935 }
5936
5937 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5938 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5939 { /* likely */ }
5940 else
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5942 }
5943 }
5944
5945 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5946 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5947 { /* likely */ }
5948 else
5949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5950
5951 /* We don't support SGX yet. So enclave-interruption must not be set. */
5952 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5953 { /* likely */ }
5954 else
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5956
5957 /*
5958 * Pending debug exceptions.
5959 */
5960 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5961 ? pVmcs->u64GuestPendingDbgXcpts.u
5962 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5963 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5964 { /* likely */ }
5965 else
5966 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5967
5968 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5969 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5970 {
5971 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5972 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5973 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5974 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5975
5976 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5977 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5978 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5979 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5980 }
5981
5982 /* We don't support RTM (Real-time Transactional Memory) yet. */
5983 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5984 { /* likely */ }
5985 else
5986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5987
5988 /*
5989 * VMCS link pointer.
5990 */
5991 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5992 {
5993 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5994 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5995 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5996 { /* likely */ }
5997 else
5998 {
5999 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
6001 }
6002
6003 /* Validate the address. */
6004 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
6005 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6006 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
6007 { /* likely */ }
6008 else
6009 {
6010 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6011 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
6012 }
6013 }
6014
6015 NOREF(pszInstr);
6016 NOREF(pszFailure);
6017 return VINF_SUCCESS;
6018}
6019
6020
6021#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6022/**
6023 * Checks guest PDPTEs as part of VM-entry.
6024 *
6025 * @param pVCpu The cross context virtual CPU structure.
6026 * @param pszInstr The VMX instruction name (for logging purposes).
6027 */
6028static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6029{
6030 /*
6031 * Guest PDPTEs.
6032 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6033 */
6034 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6035 const char * const pszFailure = "VM-exit";
6036
6037 /*
6038 * When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
6039 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6040 */
6041 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6042 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6043 {
6044 /* Get PDPTEs from the VMCS. */
6045 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6046 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6047 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6048 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6049 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6050
6051 /* Check validity of the PDPTEs. */
6052 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
6053 { /* likely */ }
6054 else
6055 {
6056 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6058 }
6059 }
6060
6061 NOREF(pszFailure);
6062 NOREF(pszInstr);
6063 return VINF_SUCCESS;
6064}
6065#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6066
6067
6068/**
6069 * Checks guest-state as part of VM-entry.
6070 *
6071 * @returns VBox status code.
6072 * @param pVCpu The cross context virtual CPU structure.
6073 * @param pszInstr The VMX instruction name (for logging purposes).
6074 */
6075static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6076{
6077 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6078 if (RT_SUCCESS(rc))
6079 {
6080 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6081 if (RT_SUCCESS(rc))
6082 {
6083 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6084 if (RT_SUCCESS(rc))
6085 {
6086 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6087 if (RT_SUCCESS(rc))
6088 {
6089 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6090#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6091 if (RT_SUCCESS(rc))
6092 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6093#endif
6094 }
6095 }
6096 }
6097 }
6098 return rc;
6099}
6100
6101
6102/**
6103 * Checks host-state as part of VM-entry.
6104 *
6105 * @returns VBox status code.
6106 * @param pVCpu The cross context virtual CPU structure.
6107 * @param pszInstr The VMX instruction name (for logging purposes).
6108 */
6109static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6110{
6111 /*
6112 * Host Control Registers and MSRs.
6113 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6114 */
6115 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6116 const char * const pszFailure = "VMFail";
6117
6118 /* CR0 reserved bits. */
6119 {
6120 /* CR0 MB1 bits. */
6121 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
6122 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6123 { /* likely */ }
6124 else
6125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6126
6127 /* CR0 MBZ bits. */
6128 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6129 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6130 { /* likely */ }
6131 else
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6133 }
6134
6135 /* CR4 reserved bits. */
6136 {
6137 /* CR4 MB1 bits. */
6138 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6139 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6140 { /* likely */ }
6141 else
6142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6143
6144 /* CR4 MBZ bits. */
6145 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6146 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6147 { /* likely */ }
6148 else
6149 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6150 }
6151
6152 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6153 {
6154 /* CR3 reserved bits. */
6155 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6156 { /* likely */ }
6157 else
6158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6159
6160 /* SYSENTER ESP and SYSENTER EIP. */
6161 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6162 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6163 { /* likely */ }
6164 else
6165 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6166 }
6167
6168 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6169 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6170
6171 /* PAT MSR. */
6172 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6173 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6174 { /* likely */ }
6175 else
6176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6177
6178 /* EFER MSR. */
6179 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6180 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6181 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6182 {
6183 if (!(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6184 { /* likely */ }
6185 else
6186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6187
6188 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6189 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6190 if ( fHostInLongMode == fHostLma
6191 && fHostInLongMode == fHostLme)
6192 { /* likely */ }
6193 else
6194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6195 }
6196
6197 /*
6198 * Host Segment and Descriptor-Table Registers.
6199 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6200 */
6201 /* Selector RPL and TI. */
6202 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6203 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6204 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6205 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6206 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6207 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6208 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6209 { /* likely */ }
6210 else
6211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6212
6213 /* CS and TR selectors cannot be 0. */
6214 if ( pVmcs->HostCs
6215 && pVmcs->HostTr)
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6219
6220 /* SS cannot be 0 if 32-bit host. */
6221 if ( fHostInLongMode
6222 || pVmcs->HostSs)
6223 { /* likely */ }
6224 else
6225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6226
6227 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6228 {
6229 /* FS, GS, GDTR, IDTR, TR base address. */
6230 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6231 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6232 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6233 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6234 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6235 { /* likely */ }
6236 else
6237 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6238 }
6239
6240 /*
6241 * Host address-space size for 64-bit CPUs.
6242 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6243 */
6244 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6245 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6246 {
6247 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6248
6249 /* Logical processor in IA-32e mode. */
6250 if (fCpuInLongMode)
6251 {
6252 if (fHostInLongMode)
6253 {
6254 /* PAE must be set. */
6255 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6256 { /* likely */ }
6257 else
6258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6259
6260 /* RIP must be canonical. */
6261 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6262 { /* likely */ }
6263 else
6264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6265 }
6266 else
6267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6268 }
6269 else
6270 {
6271 /* Logical processor is outside IA-32e mode. */
6272 if ( !fGstInLongMode
6273 && !fHostInLongMode)
6274 {
6275 /* PCIDE should not be set. */
6276 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6277 { /* likely */ }
6278 else
6279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6280
6281 /* The high 32-bits of RIP MBZ. */
6282 if (!pVmcs->u64HostRip.s.Hi)
6283 { /* likely */ }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6286 }
6287 else
6288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6289 }
6290 }
6291 else
6292 {
6293 /* Host address-space size for 32-bit CPUs. */
6294 if ( !fGstInLongMode
6295 && !fHostInLongMode)
6296 { /* likely */ }
6297 else
6298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6299 }
6300
6301 NOREF(pszInstr);
6302 NOREF(pszFailure);
6303 return VINF_SUCCESS;
6304}
6305
6306
6307#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6308/**
6309 * Checks the EPT pointer VMCS field as part of VM-entry.
6310 *
6311 * @returns VBox status code.
6312 * @param pVCpu The cross context virtual CPU structure.
6313 * @param uEptPtr The EPT pointer to check.
6314 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6315 * updated on success). Optional, can be NULL.
6316 */
6317static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6318{
6319 VMXVDIAG enmVmxDiag;
6320
6321 /* Reserved bits. */
6322 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6323 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6324 if (uEptPtr & fValidMask)
6325 {
6326 /* Memory Type. */
6327 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6328 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6329 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6330 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6331 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6332 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6333 {
6334 /*
6335 * Page walk length (PML4).
6336 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6337 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6338 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6339 */
6340 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6341 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6342 {
6343 /* Access and dirty bits support in EPT structures. */
6344 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6345 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6346 return VINF_SUCCESS;
6347
6348 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6349 }
6350 else
6351 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6352 }
6353 else
6354 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6355 }
6356 else
6357 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6358
6359 if (penmVmxDiag)
6360 *penmVmxDiag = enmVmxDiag;
6361 return VERR_VMX_VMENTRY_FAILED;
6362}
6363#endif
6364
6365
6366/**
6367 * Checks VMCS controls fields as part of VM-entry.
6368 *
6369 * @returns VBox status code.
6370 * @param pVCpu The cross context virtual CPU structure.
6371 * @param pszInstr The VMX instruction name (for logging purposes).
6372 *
6373 * @remarks This may update secondary-processor based VM-execution control fields
6374 * in the current VMCS if necessary.
6375 */
6376static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6377{
6378 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6379 const char * const pszFailure = "VMFail";
6380 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6381
6382 /*
6383 * VM-execution controls.
6384 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6385 */
6386 {
6387 /* Pin-based VM-execution controls. */
6388 {
6389 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6390 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6391 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6392 { /* likely */ }
6393 else
6394 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6395
6396 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6397 { /* likely */ }
6398 else
6399 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6400 }
6401
6402 /* Processor-based VM-execution controls. */
6403 {
6404 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6405 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6406 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6407 { /* likely */ }
6408 else
6409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6410
6411 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6412 { /* likely */ }
6413 else
6414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6415 }
6416
6417 /* Secondary processor-based VM-execution controls. */
6418 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6419 {
6420 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6421 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6422 { /* likely */ }
6423 else
6424 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6425
6426 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6427 { /* likely */ }
6428 else
6429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6430 }
6431 else if (pVmcs->u32ProcCtls2)
6432 {
6433 /*
6434 * If the "activate secondary controls" is clear, then the secondary processor-based VM-execution controls
6435 * is treated as 0.
6436 *
6437 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6438 *
6439 * Since this is a rather rare occurrence (only observed for a few VM-entries with Microsoft Hyper-V
6440 * enabled Windows Server 2008 R2 guest), it's not worth changing every place that reads this control to
6441 * also check the "activate secondary controls" bit. Instead, we temporarily save the guest programmed
6442 * control here, zero out the value the rest of our code uses and restore the guest programmed value
6443 * on VM-exit.
6444 */
6445 pVmcs->u32RestoreProcCtls2 = pVmcs->u32ProcCtls2;
6446 pVmcs->u32ProcCtls2 = 0;
6447 }
6448
6449 /* CR3-target count. */
6450 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6451 { /* likely */ }
6452 else
6453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6454
6455 /* I/O bitmaps physical addresses. */
6456 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6457 {
6458 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6459 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6460 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6461 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6462 { /* likely */ }
6463 else
6464 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6465
6466 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6467 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6468 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6469 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6470 { /* likely */ }
6471 else
6472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6473 }
6474
6475 /* MSR bitmap physical address. */
6476 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6477 {
6478 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6479 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6480 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6481 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6482 { /* likely */ }
6483 else
6484 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6485 }
6486
6487 /* TPR shadow related controls. */
6488 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6489 {
6490 /* Virtual-APIC page physical address. */
6491 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6492 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6493 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6494 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6495 { /* likely */ }
6496 else
6497 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6498
6499 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6500 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6501 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6502 { /* likely */ }
6503 else
6504 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6505
6506 /* The rest done XXX document */
6507 }
6508 else
6509 {
6510 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6511 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6512 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6513 { /* likely */ }
6514 else
6515 {
6516 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6518 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6520 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6522 }
6523 }
6524
6525 /* NMI exiting and virtual-NMIs. */
6526 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6527 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6528 { /* likely */ }
6529 else
6530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6531
6532 /* Virtual-NMIs and NMI-window exiting. */
6533 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6534 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6535 { /* likely */ }
6536 else
6537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6538
6539 /* Virtualize APIC accesses. */
6540 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6541 {
6542 /* APIC-access physical address. */
6543 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6544 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6545 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6546 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6547 { /* likely */ }
6548 else
6549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6550
6551 /*
6552 * Disallow APIC-access page and virtual-APIC page from being the same address.
6553 * Note! This is not an Intel requirement, but one imposed by our implementation.
6554 */
6555 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6556 * redirecting accesses between the APIC-access page and the virtual-APIC
6557 * page. If any nested hypervisor requires this, we can implement it later. */
6558 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6559 {
6560 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6561 if (GCPhysVirtApic != GCPhysApicAccess)
6562 { /* likely */ }
6563 else
6564 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6565 }
6566 }
6567
6568 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6569 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6570 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6571 { /* likely */ }
6572 else
6573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6574
6575 /* Virtual-interrupt delivery requires external interrupt exiting. */
6576 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6577 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6578 { /* likely */ }
6579 else
6580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6581
6582 /* VPID. */
6583 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6584 || pVmcs->u16Vpid != 0)
6585 { /* likely */ }
6586 else
6587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6588
6589#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6590 /* Extended-Page-Table Pointer (EPTP). */
6591 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6592 {
6593 VMXVDIAG enmVmxDiag;
6594 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6595 if (RT_SUCCESS(rc))
6596 { /* likely */ }
6597 else
6598 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, enmVmxDiag, rc);
6599 }
6600#else
6601 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6602 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6603#endif
6604 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6605 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6606 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6607 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6608 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6609
6610 /* VMCS shadowing. */
6611 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6612 {
6613 /* VMREAD-bitmap physical address. */
6614 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6615 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6616 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6617 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6618 { /* likely */ }
6619 else
6620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6621
6622 /* VMWRITE-bitmap physical address. */
6623 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6624 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6625 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6626 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6627 { /* likely */ }
6628 else
6629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6630 }
6631 }
6632
6633 /*
6634 * VM-exit controls.
6635 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6636 */
6637 {
6638 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6639 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6640 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6641 { /* likely */ }
6642 else
6643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6644
6645 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6646 { /* likely */ }
6647 else
6648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6649
6650 /* Save preemption timer without activating it. */
6651 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6652 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6653 { /* likely */ }
6654 else
6655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6656
6657 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6658 if (pVmcs->u32ExitMsrStoreCount)
6659 {
6660 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6661 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6662 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6663 { /* likely */ }
6664 else
6665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6666 }
6667
6668 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6669 if (pVmcs->u32ExitMsrLoadCount)
6670 {
6671 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6672 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6673 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6674 { /* likely */ }
6675 else
6676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6677 }
6678 }
6679
6680 /*
6681 * VM-entry controls.
6682 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6683 */
6684 {
6685 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6686 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6687 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6688 { /* likely */ }
6689 else
6690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6691
6692 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6693 { /* likely */ }
6694 else
6695 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6696
6697 /* Event injection. */
6698 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6699 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6700 {
6701 /* Type and vector. */
6702 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6703 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6704 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6705 if ( !uRsvd
6706 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6707 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6708 { /* likely */ }
6709 else
6710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6711
6712 /* Exception error code. */
6713 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6714 {
6715 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6716 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6717 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6718 { /* likely */ }
6719 else
6720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6721
6722 /* Exceptions that provide an error code. */
6723 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6724 && ( uVector == X86_XCPT_DF
6725 || uVector == X86_XCPT_TS
6726 || uVector == X86_XCPT_NP
6727 || uVector == X86_XCPT_SS
6728 || uVector == X86_XCPT_GP
6729 || uVector == X86_XCPT_PF
6730 || uVector == X86_XCPT_AC))
6731 { /* likely */ }
6732 else
6733 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6734
6735 /* Exception error-code reserved bits. */
6736 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6737 { /* likely */ }
6738 else
6739 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6740
6741 /* Injecting a software interrupt, software exception or privileged software exception. */
6742 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6743 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6744 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6745 {
6746 /* Instruction length must be in the range 0-15. */
6747 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6748 { /* likely */ }
6749 else
6750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6751
6752 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6753 if ( pVmcs->u32EntryInstrLen != 0
6754 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6755 { /* likely */ }
6756 else
6757 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6758 }
6759 }
6760 }
6761
6762 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6763 if (pVmcs->u32EntryMsrLoadCount)
6764 {
6765 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6766 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6767 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6768 { /* likely */ }
6769 else
6770 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6771 }
6772
6773 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6774 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6775 }
6776
6777 NOREF(pszInstr);
6778 NOREF(pszFailure);
6779 return VINF_SUCCESS;
6780}
6781
6782
6783/**
6784 * Loads the guest control registers, debug register and some MSRs as part of
6785 * VM-entry.
6786 *
6787 * @param pVCpu The cross context virtual CPU structure.
6788 */
6789static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6790{
6791 /*
6792 * Load guest control registers, debug registers and MSRs.
6793 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6794 */
6795 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6796
6797 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6798 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6799 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6800 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6801 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6802 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6803
6804 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6805 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6806
6807 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6808 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6809 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6810
6811 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6812 {
6813 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6814
6815 /* EFER MSR. */
6816 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6817 {
6818 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6819 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6820 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6821 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6822 if (fGstInLongMode)
6823 {
6824 /* If the nested-guest is in long mode, LMA and LME are both set. */
6825 Assert(fGstPaging);
6826 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6827 }
6828 else
6829 {
6830 /*
6831 * If the nested-guest is outside long mode:
6832 * - With paging: LMA is cleared, LME is cleared.
6833 * - Without paging: LMA is cleared, LME is left unmodified.
6834 */
6835 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6836 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6837 }
6838 }
6839 /* else: see below. */
6840 }
6841
6842 /* PAT MSR. */
6843 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6844 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6845
6846 /* EFER MSR. */
6847 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6848 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6849
6850 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6851 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6852
6853 /* We don't support IA32_BNDCFGS MSR yet. */
6854 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6855
6856 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6857}
6858
6859
6860/**
6861 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6862 *
6863 * @param pVCpu The cross context virtual CPU structure.
6864 */
6865static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6866{
6867 /*
6868 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6869 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6870 */
6871 /* CS, SS, ES, DS, FS, GS. */
6872 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6873 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6874 {
6875 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6876 CPUMSELREG VmcsSelReg;
6877 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6878 AssertRC(rc); NOREF(rc);
6879 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6880 {
6881 pGstSelReg->Sel = VmcsSelReg.Sel;
6882 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6883 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6884 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6885 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6886 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6887 }
6888 else
6889 {
6890 pGstSelReg->Sel = VmcsSelReg.Sel;
6891 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6892 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6893 switch (iSegReg)
6894 {
6895 case X86_SREG_CS:
6896 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6897 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6898 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6899 break;
6900
6901 case X86_SREG_SS:
6902 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6903 pGstSelReg->u32Limit = 0;
6904 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6905 break;
6906
6907 case X86_SREG_ES:
6908 case X86_SREG_DS:
6909 pGstSelReg->u64Base = 0;
6910 pGstSelReg->u32Limit = 0;
6911 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6912 break;
6913
6914 case X86_SREG_FS:
6915 case X86_SREG_GS:
6916 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6917 pGstSelReg->u32Limit = 0;
6918 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6919 break;
6920 }
6921 Assert(pGstSelReg->Attr.n.u1Unusable);
6922 }
6923 }
6924
6925 /* LDTR. */
6926 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6927 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6928 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6929 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6930 {
6931 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6932 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6933 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6934 }
6935 else
6936 {
6937 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6938 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6939 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6940 }
6941
6942 /* TR. */
6943 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6944 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6945 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6946 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6947 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6948 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6949 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6950
6951 /* GDTR. */
6952 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6953 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6954
6955 /* IDTR. */
6956 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6957 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6958}
6959
6960
6961/**
6962 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6963 *
6964 * @returns VBox status code.
6965 * @param pVCpu The cross context virtual CPU structure.
6966 * @param pszInstr The VMX instruction name (for logging purposes).
6967 */
6968static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6969{
6970 /*
6971 * Load guest MSRs.
6972 * See Intel spec. 26.4 "Loading MSRs".
6973 */
6974 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6975 const char *const pszFailure = "VM-exit";
6976
6977 /*
6978 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6979 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6980 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6981 */
6982 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6983 if (!cMsrs)
6984 return VINF_SUCCESS;
6985
6986 /*
6987 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6988 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6989 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6990 */
6991 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6992 if (fIsMsrCountValid)
6993 { /* likely */ }
6994 else
6995 {
6996 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6997 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6998 }
6999
7000 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7001 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
7002 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7003 if (RT_SUCCESS(rc))
7004 {
7005 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
7006 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7007 {
7008 if ( !pMsr->u32Reserved
7009 && pMsr->u32Msr != MSR_K8_FS_BASE
7010 && pMsr->u32Msr != MSR_K8_GS_BASE
7011 && pMsr->u32Msr != MSR_K6_EFER
7012 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7013 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7014 {
7015 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7016 if (rcStrict == VINF_SUCCESS)
7017 continue;
7018
7019 /*
7020 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7021 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7022 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
7023 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7024 * MSR in ring-0 if possible, or come up with a better, generic solution.
7025 */
7026 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7027 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7028 ? kVmxVDiag_Vmentry_MsrLoadRing3
7029 : kVmxVDiag_Vmentry_MsrLoad;
7030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7031 }
7032 else
7033 {
7034 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7035 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7036 }
7037 }
7038 }
7039 else
7040 {
7041 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7042 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys, rc);
7043 }
7044
7045 NOREF(pszInstr);
7046 NOREF(pszFailure);
7047 return VINF_SUCCESS;
7048}
7049
7050
7051/**
7052 * Loads the guest-state non-register state as part of VM-entry.
7053 *
7054 * @returns VBox status code.
7055 * @param pVCpu The cross context virtual CPU structure.
7056 * @param pszInstr The VMX instruction name (for logging purposes).
7057 *
7058 * @remarks This must be called only after loading the nested-guest register state
7059 * (especially nested-guest RIP).
7060 */
7061static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7062{
7063 /*
7064 * Load guest non-register state.
7065 * See Intel spec. 26.6 "Special Features of VM Entry"
7066 */
7067 const char *const pszFailure = "VM-exit";
7068 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7069
7070 /*
7071 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7072 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7073 *
7074 * See Intel spec. 26.6.1 "Interruptibility State".
7075 */
7076 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7077 if ( !fEntryVectoring
7078 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7079 CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcs->u64GuestRip.u);
7080 else
7081 Assert(!CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx));
7082
7083 /* NMI blocking. */
7084 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7085 {
7086 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7087 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7088 else
7089 {
7090 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7091 CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
7092 }
7093 }
7094 else
7095 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7096
7097 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7098
7099 /*
7100 * Set PGM's copy of the EPT pointer.
7101 * The EPTP has already been validated while checking guest state.
7102 *
7103 * It is important to do this prior to mapping PAE PDPTEs (below).
7104 */
7105 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7106 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7107
7108 /*
7109 * Load the guest's PAE PDPTEs.
7110 */
7111 if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7112 {
7113 /*
7114 * When PAE paging is not used we clear the PAE PDPTEs for safety
7115 * in case we might be switching from a PAE host to a non-PAE guest.
7116 */
7117 pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7118 pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7119 pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7120 pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7121 }
7122 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7123 {
7124 /*
7125 * With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7126 * while checking the guest state. We can load them into the nested-guest CPU state now.
7127 * They'll later be used while mapping CR3 and the PAE PDPTEs.
7128 */
7129 pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7130 pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7131 pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7132 pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7133 }
7134 else
7135 {
7136 /*
7137 * Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7138 * referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7139 */
7140 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7141 if (RT_SUCCESS(rc))
7142 { /* likely */ }
7143 else
7144 {
7145 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7146 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte, rc);
7147 }
7148 }
7149
7150 /* VPID is irrelevant. We don't support VPID yet. */
7151
7152 /* Clear address-range monitoring. */
7153 EMMonitorWaitClear(pVCpu);
7154
7155 return VINF_SUCCESS;
7156}
7157
7158
7159/**
7160 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7161 *
7162 * @param pVCpu The cross context virtual CPU structure.
7163 * @param pszInstr The VMX instruction name (for logging purposes).
7164 *
7165 * @remarks This assumes various VMCS related data structure pointers have already
7166 * been verified prior to calling this function.
7167 */
7168static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7169{
7170 const char *const pszFailure = "VM-exit";
7171 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7172
7173 /*
7174 * Virtualize APIC accesses.
7175 */
7176 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7177 {
7178 /* APIC-access physical address. */
7179 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7180
7181 /*
7182 * Register the handler for the APIC-access page.
7183 *
7184 * We don't deregister the APIC-access page handler during the VM-exit as a different
7185 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7186 *
7187 * We leave the page registered until the first access that happens outside VMX non-root
7188 * mode. Guest software is allowed to access structures such as the APIC-access page
7189 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7190 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7191 *
7192 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7193 */
7194 /** @todo r=bird: The lazy deregistration of the page is potentially slightly
7195 * problematic, as the guest may cause us to create lots of access
7196 * handler entries. However, any slowdown or similar effects should
7197 * only ever affect the guest itself, so not a big issue. Though, I
7198 * wish there was most recently used approach or something to tracking
7199 * these... */
7200 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7201 int rc = PGMHandlerPhysicalRegisterVmxApicAccessPage(pVM, GCPhysApicAccess, pVM->iem.s.hVmxApicAccessPage);
7202 if (RT_SUCCESS(rc))
7203 { /* likely */ }
7204 else
7205 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg, rc);
7206 }
7207
7208 /*
7209 * VMCS shadowing.
7210 */
7211 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7212 {
7213 /* Read the VMREAD-bitmap. */
7214 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7215 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7216 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7217 if (RT_SUCCESS(rc))
7218 { /* likely */ }
7219 else
7220 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys, rc);
7221
7222 /* Read the VMWRITE-bitmap. */
7223 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7224 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7225 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7226 if (RT_SUCCESS(rc))
7227 { /* likely */ }
7228 else
7229 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys, rc);
7230 }
7231
7232 /*
7233 * I/O bitmaps.
7234 */
7235 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7236 {
7237 /* Read the IO bitmap A. */
7238 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7239 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7240 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7241 if (RT_SUCCESS(rc))
7242 { /* likely */ }
7243 else
7244 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys, rc);
7245
7246 /* Read the IO bitmap B. */
7247 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7248 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7249 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7250 if (RT_SUCCESS(rc))
7251 { /* likely */ }
7252 else
7253 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys, rc);
7254 }
7255
7256 /*
7257 * TPR shadow and Virtual-APIC page.
7258 */
7259 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7260 {
7261 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7262 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7263 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7264 {
7265 /* Read the VTPR from the virtual-APIC page. */
7266 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7267 uint8_t u8VTpr;
7268 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7269 if (RT_SUCCESS(rc))
7270 { /* likely */ }
7271 else
7272 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys, rc);
7273
7274 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7275 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7276 { /* likely */ }
7277 else
7278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7279 }
7280 }
7281
7282 /*
7283 * VMCS link pointer.
7284 */
7285 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7286 {
7287 /* Read the VMCS-link pointer from guest memory. */
7288 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7289 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7290 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7291 if (RT_SUCCESS(rc))
7292 { /* likely */ }
7293 else
7294 {
7295 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7296 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys, rc);
7297 }
7298
7299 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7300 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7301 { /* likely */ }
7302 else
7303 {
7304 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7305 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7306 }
7307
7308 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7309 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7310 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7311 { /* likely */ }
7312 else
7313 {
7314 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7316 }
7317
7318 /* Update our cache of the guest physical address of the shadow VMCS. */
7319 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7320 }
7321
7322 /*
7323 * MSR bitmap.
7324 */
7325 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7326 {
7327 /* Read the MSR bitmap. */
7328 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7329 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7330 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7331 if (RT_SUCCESS(rc))
7332 { /* likely */ }
7333 else
7334 IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys, rc);
7335 }
7336
7337 NOREF(pszFailure);
7338 NOREF(pszInstr);
7339 return VINF_SUCCESS;
7340}
7341
7342
7343/**
7344 * Loads the guest-state as part of VM-entry.
7345 *
7346 * @returns VBox status code.
7347 * @param pVCpu The cross context virtual CPU structure.
7348 * @param pszInstr The VMX instruction name (for logging purposes).
7349 *
7350 * @remarks This must be done after all the necessary steps prior to loading of
7351 * guest-state (e.g. checking various VMCS state).
7352 */
7353static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7354{
7355 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7356 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7357
7358 /* Load guest segment registers. */
7359 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7360
7361 /*
7362 * Load guest RIP, RSP and RFLAGS.
7363 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7364 */
7365 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7366 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7367 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7368 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7369
7370 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7371 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7372 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7373
7374 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7375 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7376 if (rc == VINF_SUCCESS)
7377 { /* likely */ }
7378 else
7379 return rc;
7380
7381 /* Load VMX related structures and state referenced by the VMCS. */
7382 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7383 if (rc == VINF_SUCCESS)
7384 { /* likely */ }
7385 else
7386 return rc;
7387
7388 NOREF(pszInstr);
7389 return VINF_SUCCESS;
7390}
7391
7392
7393/**
7394 * Returns whether there are is a pending debug exception on VM-entry.
7395 *
7396 * @param pVCpu The cross context virtual CPU structure.
7397 * @param pszInstr The VMX instruction name (for logging purposes).
7398 */
7399static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7400{
7401 /*
7402 * Pending debug exceptions.
7403 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7404 */
7405 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7406 Assert(pVmcs);
7407
7408 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7409 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7410 if (fPendingDbgXcpt)
7411 {
7412 uint8_t uEntryIntInfoType;
7413 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7414 if (fEntryVectoring)
7415 {
7416 switch (uEntryIntInfoType)
7417 {
7418 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7419 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7420 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7421 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7422 fPendingDbgXcpt = false;
7423 break;
7424
7425 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7426 {
7427 /*
7428 * Whether the pending debug exception for software exceptions other than
7429 * #BP and #OF is delivered after injecting the exception or is discard
7430 * is CPU implementation specific. We will discard them (easier).
7431 */
7432 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7433 if ( uVector != X86_XCPT_BP
7434 && uVector != X86_XCPT_OF)
7435 fPendingDbgXcpt = false;
7436 RT_FALL_THRU();
7437 }
7438 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7439 {
7440 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7441 fPendingDbgXcpt = false;
7442 break;
7443 }
7444 }
7445 }
7446 else
7447 {
7448 /*
7449 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7450 * pending debug exception is held pending or is discarded is CPU implementation
7451 * specific. We will discard them (easier).
7452 */
7453 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7454 fPendingDbgXcpt = false;
7455
7456 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7457 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7458 fPendingDbgXcpt = false;
7459 }
7460 }
7461
7462 NOREF(pszInstr);
7463 return fPendingDbgXcpt;
7464}
7465
7466
7467/**
7468 * Set up the monitor-trap flag (MTF).
7469 *
7470 * @param pVCpu The cross context virtual CPU structure.
7471 * @param pszInstr The VMX instruction name (for logging purposes).
7472 */
7473static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7474{
7475 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7476 Assert(pVmcs);
7477 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7478 {
7479 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7480 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7481 }
7482 else
7483 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7484 NOREF(pszInstr);
7485}
7486
7487
7488/**
7489 * Sets up NMI-window exiting.
7490 *
7491 * @param pVCpu The cross context virtual CPU structure.
7492 * @param pszInstr The VMX instruction name (for logging purposes).
7493 */
7494static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7495{
7496 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7497 Assert(pVmcs);
7498 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7499 {
7500 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7501 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7502 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7503 }
7504 else
7505 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7506 NOREF(pszInstr);
7507}
7508
7509
7510/**
7511 * Sets up interrupt-window exiting.
7512 *
7513 * @param pVCpu The cross context virtual CPU structure.
7514 * @param pszInstr The VMX instruction name (for logging purposes).
7515 */
7516static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7517{
7518 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7519 Assert(pVmcs);
7520 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7521 {
7522 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7523 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7524 }
7525 else
7526 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7527 NOREF(pszInstr);
7528}
7529
7530
7531/**
7532 * Set up the VMX-preemption timer.
7533 *
7534 * @param pVCpu The cross context virtual CPU structure.
7535 * @param pszInstr The VMX instruction name (for logging purposes).
7536 */
7537static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7538{
7539 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7540 Assert(pVmcs);
7541 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7542 {
7543 /*
7544 * If the timer is 0, we must cause a VM-exit before executing the first
7545 * nested-guest instruction. So we can flag as though the timer has already
7546 * expired and we will check and cause a VM-exit at the right priority elsewhere
7547 * in the code.
7548 */
7549 uint64_t uEntryTick;
7550 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7551 if (uPreemptTimer)
7552 {
7553 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7554 AssertRC(rc);
7555 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7556 }
7557 else
7558 {
7559 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7560 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7561 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7562 }
7563
7564 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7565 }
7566 else
7567 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7568
7569 NOREF(pszInstr);
7570}
7571
7572
7573/**
7574 * Injects an event using TRPM given a VM-entry interruption info and related
7575 * fields.
7576 *
7577 * @param pVCpu The cross context virtual CPU structure.
7578 * @param pszInstr The VMX instruction name (for logging purposes).
7579 * @param uEntryIntInfo The VM-entry interruption info.
7580 * @param uErrCode The error code associated with the event if any.
7581 * @param cbInstr The VM-entry instruction length (for software
7582 * interrupts and software exceptions). Pass 0
7583 * otherwise.
7584 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7585 */
7586static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7587 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7588{
7589 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7590
7591 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7592 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7593 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7594
7595 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7596
7597 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7598 AssertRC(rc);
7599 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7600
7601 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7602 {
7603 TRPMSetErrorCode(pVCpu, uErrCode);
7604 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7605 }
7606
7607 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7608 {
7609 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7610 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7611 }
7612 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7613 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7614 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7615 {
7616 TRPMSetInstrLength(pVCpu, cbInstr);
7617 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7618 }
7619
7620 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7621 {
7622 TRPMSetTrapDueToIcebp(pVCpu);
7623 Log(("%s: Injecting: icebp\n", pszInstr));
7624 }
7625
7626 NOREF(pszInstr);
7627}
7628
7629
7630/**
7631 * Performs event injection (if any) as part of VM-entry.
7632 *
7633 * @param pVCpu The cross context virtual CPU structure.
7634 * @param pszInstr The VMX instruction name (for logging purposes).
7635 */
7636static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7637{
7638 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7639
7640 /*
7641 * Inject events.
7642 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7643 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7644 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7645 * the actually delivery of this event.
7646 *
7647 * See Intel spec. 26.5 "Event Injection".
7648 */
7649 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7650 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7651
7652 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7653 if (fEntryIntInfoValid)
7654 {
7655 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7656 {
7657 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7658 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7659 }
7660 else
7661 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7662 pVCpu->cpum.GstCtx.cr2);
7663
7664 /*
7665 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7666 *
7667 * However, we do it here on VM-entry as well because while it isn't visible to guest
7668 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7669 * execution using hardware-assisted VMX, it will not try to inject the event again.
7670 *
7671 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7672 */
7673 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7674 }
7675 else
7676 {
7677 /*
7678 * Inject any pending guest debug exception.
7679 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7680 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7681 */
7682 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7683 if (fPendingDbgXcpt)
7684 {
7685 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7686 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7687 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7688 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7689 0 /* GCPtrFaultAddress */);
7690 }
7691 }
7692
7693 NOREF(pszInstr);
7694}
7695
7696
7697/**
7698 * Initializes all read-only VMCS fields as part of VM-entry.
7699 *
7700 * @param pVCpu The cross context virtual CPU structure.
7701 */
7702static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7703{
7704 /*
7705 * Any VMCS field which we do not establish on every VM-exit but may potentially
7706 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7707 * specified to be undefined, needs to be initialized here.
7708 *
7709 * Thus, it is especially important to clear the Exit qualification field
7710 * since it must be zero for VM-exits where it is not used. Similarly, the
7711 * VM-exit interruption information field's valid bit needs to be cleared for
7712 * the same reasons.
7713 */
7714 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7715 Assert(pVmcs);
7716
7717 /* 16-bit (none currently). */
7718 /* 32-bit. */
7719 pVmcs->u32RoVmInstrError = 0;
7720 pVmcs->u32RoExitReason = 0;
7721 pVmcs->u32RoExitIntInfo = 0;
7722 pVmcs->u32RoExitIntErrCode = 0;
7723 pVmcs->u32RoIdtVectoringInfo = 0;
7724 pVmcs->u32RoIdtVectoringErrCode = 0;
7725 pVmcs->u32RoExitInstrLen = 0;
7726 pVmcs->u32RoExitInstrInfo = 0;
7727
7728 /* 64-bit. */
7729 pVmcs->u64RoGuestPhysAddr.u = 0;
7730
7731 /* Natural-width. */
7732 pVmcs->u64RoExitQual.u = 0;
7733 pVmcs->u64RoIoRcx.u = 0;
7734 pVmcs->u64RoIoRsi.u = 0;
7735 pVmcs->u64RoIoRdi.u = 0;
7736 pVmcs->u64RoIoRip.u = 0;
7737 pVmcs->u64RoGuestLinearAddr.u = 0;
7738}
7739
7740
7741/**
7742 * VMLAUNCH/VMRESUME instruction execution worker.
7743 *
7744 * @returns Strict VBox status code.
7745 * @param pVCpu The cross context virtual CPU structure.
7746 * @param cbInstr The instruction length in bytes.
7747 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7748 * VMXINSTRID_VMRESUME).
7749 *
7750 * @remarks Common VMX instruction checks are already expected to by the caller,
7751 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7752 */
7753static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7754{
7755# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7756 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7757 return VINF_EM_RAW_EMULATE_INSTR;
7758# else
7759 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7760 || uInstrId == VMXINSTRID_VMRESUME);
7761 const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7762
7763 /* Nested-guest intercept. */
7764 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7765 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7766
7767 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7768
7769 /*
7770 * Basic VM-entry checks.
7771 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7772 * The checks following that do not have to follow a specific order.
7773 *
7774 * See Intel spec. 26.1 "Basic VM-entry Checks".
7775 */
7776
7777 /* CPL. */
7778 if (pVCpu->iem.s.uCpl == 0)
7779 { /* likely */ }
7780 else
7781 {
7782 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7784 return iemRaiseGeneralProtectionFault0(pVCpu);
7785 }
7786
7787 /* Current VMCS valid. */
7788 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7789 { /* likely */ }
7790 else
7791 {
7792 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7793 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7794 iemVmxVmFailInvalid(pVCpu);
7795 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7796 }
7797
7798 /* Current VMCS is not a shadow VMCS. */
7799 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7800 { /* likely */ }
7801 else
7802 {
7803 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7804 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7805 iemVmxVmFailInvalid(pVCpu);
7806 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7807 }
7808
7809 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7810 * use block-by-STI here which is not quite correct. */
7811 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
7812 { /* likely */ }
7813 else
7814 {
7815 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7816 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7817 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7818 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7819 }
7820
7821 if (uInstrId == VMXINSTRID_VMLAUNCH)
7822 {
7823 /* VMLAUNCH with non-clear VMCS. */
7824 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7825 { /* likely */ }
7826 else
7827 {
7828 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7829 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7830 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7831 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7832 }
7833 }
7834 else
7835 {
7836 /* VMRESUME with non-launched VMCS. */
7837 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7838 { /* likely */ }
7839 else
7840 {
7841 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7842 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7843 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7844 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7845 }
7846 }
7847
7848 /*
7849 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7850 * while entering VMX non-root mode. We do some of this while checking VM-execution
7851 * controls. The nested hypervisor should not make assumptions and cannot expect
7852 * predictable behavior if changes to these structures are made in guest memory while
7853 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7854 * modify them anyway as we cache them in host memory.
7855 *
7856 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7857 */
7858 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7859
7860 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7861 if (RT_SUCCESS(rc))
7862 {
7863 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7864 if (RT_SUCCESS(rc))
7865 {
7866 /*
7867 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7868 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7869 * ones that may occur during VM-entry below).
7870 */
7871 iemVmxVmentryInitReadOnlyFields(pVCpu);
7872
7873 /*
7874 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7875 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7876 * VM-exit when required.
7877 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7878 */
7879 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7880
7881 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7882 Assert(pVmcs);
7883
7884 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7885 if (RT_SUCCESS(rc))
7886 {
7887 /*
7888 * We've now entered nested-guest execution.
7889 *
7890 * It is important do this prior to loading the guest state because
7891 * as part of loading the guest state, PGM (and perhaps other components
7892 * in the future) relies on detecting whether VMX non-root mode has been
7893 * entered.
7894 */
7895 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7896
7897 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7898 if (RT_SUCCESS(rc))
7899 {
7900 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7901 if (RT_SUCCESS(rc))
7902 {
7903 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7904
7905 /* VMLAUNCH instruction must update the VMCS launch state. */
7906 if (uInstrId == VMXINSTRID_VMLAUNCH)
7907 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7908
7909 /* Perform the VMX transition (PGM updates). */
7910 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7911 if (rcStrict == VINF_SUCCESS)
7912 { /* likely */ }
7913 else if (RT_SUCCESS(rcStrict))
7914 {
7915 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7916 VBOXSTRICTRC_VAL(rcStrict)));
7917 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7918 }
7919 else
7920 {
7921 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7922 return rcStrict;
7923 }
7924
7925 /* Paranoia. */
7926 Assert(rcStrict == VINF_SUCCESS);
7927
7928 /*
7929 * The priority of potential VM-exits during VM-entry is important.
7930 * The priorities of VM-exits and events are listed from highest
7931 * to lowest as follows:
7932 *
7933 * 1. Event injection.
7934 * 2. Trap on task-switch (T flag set in TSS).
7935 * 3. TPR below threshold / APIC-write.
7936 * 4. SMI, INIT.
7937 * 5. MTF exit.
7938 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7939 * 7. VMX-preemption timer.
7940 * 9. NMI-window exit.
7941 * 10. NMI injection.
7942 * 11. Interrupt-window exit.
7943 * 12. Virtual-interrupt injection.
7944 * 13. Interrupt injection.
7945 * 14. Process next instruction (fetch, decode, execute).
7946 */
7947
7948 /* Setup VMX-preemption timer. */
7949 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7950
7951 /* Setup monitor-trap flag. */
7952 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7953
7954 /* Setup NMI-window exiting. */
7955 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7956
7957 /* Setup interrupt-window exiting. */
7958 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7959
7960 /*
7961 * Inject any event that the nested hypervisor wants to inject.
7962 * Note! We cannot immediately perform the event injection here as we may have
7963 * pending PGM operations to perform due to switching page tables and/or
7964 * mode.
7965 */
7966 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7967
7968# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7969 /* Reschedule to IEM-only execution of the nested-guest. */
7970 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7971 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7972 if (rcSched != VINF_SUCCESS)
7973 iemSetPassUpStatus(pVCpu, rcSched);
7974# endif
7975
7976 /* Finally, done. */
7977 Log2(("vmentry: %s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7978 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7979 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7980 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7981 return VINF_SUCCESS;
7982 }
7983 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7984 }
7985 }
7986 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7987 }
7988
7989 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7990 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7991 }
7992
7993 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7994 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7995# endif
7996}
7997
7998
7999/**
8000 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
8001 *
8002 * @returns Strict VBox status code.
8003 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8004 * @param cbInstr The instruction length in bytes.
8005 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
8006 * VMXINSTRID_VMRESUME).
8007 * @thread EMT(pVCpu)
8008 */
8009VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
8010{
8011 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
8012 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
8013
8014 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8015 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
8016 Assert(!pVCpu->iem.s.cActiveMappings);
8017 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8018}
8019
8020
8021/**
8022 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
8023 * (causes a VM-exit) or not.
8024 *
8025 * @returns @c true if the instruction is intercepted, @c false otherwise.
8026 * @param pVCpu The cross context virtual CPU structure.
8027 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
8028 * VMX_EXIT_WRMSR).
8029 * @param idMsr The MSR.
8030 */
8031bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
8032{
8033 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
8034 Assert( uExitReason == VMX_EXIT_RDMSR
8035 || uExitReason == VMX_EXIT_WRMSR);
8036
8037 /* Consult the MSR bitmap if the feature is supported. */
8038 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
8039 Assert(pVmcs);
8040 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
8041 {
8042 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
8043 if (uExitReason == VMX_EXIT_RDMSR)
8044 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8045 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8046 }
8047
8048 /* Without MSR bitmaps, all MSR accesses are intercepted. */
8049 return true;
8050}
8051
8052
8053/**
8054 * VMREAD instruction execution worker that does not perform any validation checks.
8055 *
8056 * Callers are expected to have performed the necessary checks and to ensure the
8057 * VMREAD will succeed.
8058 *
8059 * @param pVmcs Pointer to the virtual VMCS.
8060 * @param pu64Dst Where to write the VMCS value.
8061 * @param u64VmcsField The VMCS field.
8062 *
8063 * @remarks May be called with interrupts disabled.
8064 */
8065static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8066{
8067 VMXVMCSFIELD VmcsField;
8068 VmcsField.u = u64VmcsField;
8069 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8070 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8071 uint8_t const uWidthType = (uWidth << 2) | uType;
8072 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8073 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8074 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8075 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8076 uWidth, uType, uIndex, uIndex));
8077 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8078
8079 /*
8080 * Read the VMCS component based on the field's effective width.
8081 *
8082 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8083 * indicates high bits (little endian).
8084 *
8085 * Note! The caller is responsible to trim the result and update registers
8086 * or memory locations are required. Here we just zero-extend to the largest
8087 * type (i.e. 64-bits).
8088 */
8089 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8090 uint8_t const *pbField = pbVmcs + offField;
8091 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8092 switch (uEffWidth)
8093 {
8094 case VMX_VMCSFIELD_WIDTH_64BIT:
8095 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8096 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8097 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8098 }
8099}
8100
8101
8102/**
8103 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8104 *
8105 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8106 * are performed. Bounds checks are strict builds only.
8107 *
8108 * @param pVmcs Pointer to the virtual VMCS.
8109 * @param u64VmcsField The VMCS field.
8110 * @param pu64Dst Where to store the VMCS value.
8111 *
8112 * @remarks May be called with interrupts disabled.
8113 * @todo This should probably be moved to CPUM someday.
8114 */
8115VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8116{
8117 AssertPtr(pVmcs);
8118 AssertPtr(pu64Dst);
8119 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8120}
8121
8122
8123/**
8124 * VMREAD common (memory/register) instruction execution worker.
8125 *
8126 * @returns Strict VBox status code.
8127 * @param pVCpu The cross context virtual CPU structure.
8128 * @param cbInstr The instruction length in bytes.
8129 * @param pu64Dst Where to write the VMCS value (only updated when
8130 * VINF_SUCCESS is returned).
8131 * @param u64VmcsField The VMCS field.
8132 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8133 * NULL.
8134 */
8135static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8136 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8137{
8138 /* Nested-guest intercept. */
8139 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8140 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8141 {
8142 if (pExitInfo)
8143 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8144 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8145 }
8146
8147 /* CPL. */
8148 if (pVCpu->iem.s.uCpl == 0)
8149 { /* likely */ }
8150 else
8151 {
8152 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8153 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8154 return iemRaiseGeneralProtectionFault0(pVCpu);
8155 }
8156
8157 pVCpu->iem.s.cPotentialExits++;
8158
8159 /* VMCS pointer in root mode. */
8160 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8161 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8162 { /* likely */ }
8163 else
8164 {
8165 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8166 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8167 iemVmxVmFailInvalid(pVCpu);
8168 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8169 }
8170
8171 /* VMCS-link pointer in non-root mode. */
8172 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8173 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8174 { /* likely */ }
8175 else
8176 {
8177 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8178 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8179 iemVmxVmFailInvalid(pVCpu);
8180 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8181 }
8182
8183 /* Supported VMCS field. */
8184 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8185 { /* likely */ }
8186 else
8187 {
8188 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8189 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8190 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8191 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8192 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8193 }
8194
8195 /*
8196 * Reading from the current or shadow VMCS.
8197 */
8198 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8199 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8200 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8201 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8202 Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8203 return VINF_SUCCESS;
8204}
8205
8206
8207/**
8208 * VMREAD (64-bit register) instruction execution worker.
8209 *
8210 * @returns Strict VBox status code.
8211 * @param pVCpu The cross context virtual CPU structure.
8212 * @param cbInstr The instruction length in bytes.
8213 * @param pu64Dst Where to store the VMCS field's value.
8214 * @param u64VmcsField The VMCS field.
8215 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8216 * NULL.
8217 */
8218static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8219 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8220{
8221 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8222 if (rcStrict == VINF_SUCCESS)
8223 {
8224 iemVmxVmSucceed(pVCpu);
8225 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8226 }
8227
8228 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8229 return rcStrict;
8230}
8231
8232
8233/**
8234 * VMREAD (32-bit register) instruction execution worker.
8235 *
8236 * @returns Strict VBox status code.
8237 * @param pVCpu The cross context virtual CPU structure.
8238 * @param cbInstr The instruction length in bytes.
8239 * @param pu32Dst Where to store the VMCS field's value.
8240 * @param u32VmcsField The VMCS field.
8241 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8242 * NULL.
8243 */
8244static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8245 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8246{
8247 uint64_t u64Dst;
8248 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8249 if (rcStrict == VINF_SUCCESS)
8250 {
8251 *pu32Dst = u64Dst;
8252 iemVmxVmSucceed(pVCpu);
8253 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8254 }
8255
8256 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8257 return rcStrict;
8258}
8259
8260
8261/**
8262 * VMREAD (memory) instruction execution worker.
8263 *
8264 * @returns Strict VBox status code.
8265 * @param pVCpu The cross context virtual CPU structure.
8266 * @param cbInstr The instruction length in bytes.
8267 * @param iEffSeg The effective segment register to use with @a u64Val.
8268 * Pass UINT8_MAX if it is a register access.
8269 * @param GCPtrDst The guest linear address to store the VMCS field's
8270 * value.
8271 * @param u64VmcsField The VMCS field.
8272 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8273 * NULL.
8274 */
8275static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8276 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8277{
8278 uint64_t u64Dst;
8279 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8280 if (rcStrict == VINF_SUCCESS)
8281 {
8282 /*
8283 * Write the VMCS field's value to the location specified in guest-memory.
8284 */
8285 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8286 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8287 else
8288 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8289 if (rcStrict == VINF_SUCCESS)
8290 {
8291 iemVmxVmSucceed(pVCpu);
8292 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8293 }
8294
8295 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8296 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8297 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8298 return rcStrict;
8299 }
8300
8301 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8302 return rcStrict;
8303}
8304
8305
8306/**
8307 * Interface for HM and EM to emulate the VMREAD instruction.
8308 *
8309 * @returns Strict VBox status code.
8310 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8311 * @param pExitInfo Pointer to the VM-exit information.
8312 * @thread EMT(pVCpu)
8313 */
8314VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8315{
8316 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8317 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8318 Assert(pExitInfo);
8319
8320 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8321
8322 VBOXSTRICTRC rcStrict;
8323 uint8_t const cbInstr = pExitInfo->cbInstr;
8324 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8325 uint64_t const u64FieldEnc = fIs64BitMode
8326 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8327 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8328 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8329 {
8330 if (fIs64BitMode)
8331 {
8332 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8333 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8334 }
8335 else
8336 {
8337 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8338 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8339 }
8340 }
8341 else
8342 {
8343 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8344 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8345 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8346 }
8347 Assert(!pVCpu->iem.s.cActiveMappings);
8348 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8349}
8350
8351
8352/**
8353 * VMWRITE instruction execution worker that does not perform any validation
8354 * checks.
8355 *
8356 * Callers are expected to have performed the necessary checks and to ensure the
8357 * VMWRITE will succeed.
8358 *
8359 * @param pVmcs Pointer to the virtual VMCS.
8360 * @param u64Val The value to write.
8361 * @param u64VmcsField The VMCS field.
8362 *
8363 * @remarks May be called with interrupts disabled.
8364 */
8365static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8366{
8367 VMXVMCSFIELD VmcsField;
8368 VmcsField.u = u64VmcsField;
8369 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8370 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8371 uint8_t const uWidthType = (uWidth << 2) | uType;
8372 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8373 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8374 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8375 Assert(offField < VMX_V_VMCS_SIZE);
8376 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8377
8378 /*
8379 * Write the VMCS component based on the field's effective width.
8380 *
8381 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8382 * indicates high bits (little endian).
8383 */
8384 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8385 uint8_t *pbField = pbVmcs + offField;
8386 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8387 switch (uEffWidth)
8388 {
8389 case VMX_VMCSFIELD_WIDTH_64BIT:
8390 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8391 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8392 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8393 }
8394}
8395
8396
8397/**
8398 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8399 *
8400 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8401 * are performed. Bounds checks are strict builds only.
8402 *
8403 * @param pVmcs Pointer to the virtual VMCS.
8404 * @param u64VmcsField The VMCS field.
8405 * @param u64Val The value to write.
8406 *
8407 * @remarks May be called with interrupts disabled.
8408 * @todo This should probably be moved to CPUM someday.
8409 */
8410VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8411{
8412 AssertPtr(pVmcs);
8413 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8414}
8415
8416
8417/**
8418 * VMWRITE instruction execution worker.
8419 *
8420 * @returns Strict VBox status code.
8421 * @param pVCpu The cross context virtual CPU structure.
8422 * @param cbInstr The instruction length in bytes.
8423 * @param iEffSeg The effective segment register to use with @a u64Val.
8424 * Pass UINT8_MAX if it is a register access.
8425 * @param u64Val The value to write (or guest linear address to the
8426 * value), @a iEffSeg will indicate if it's a memory
8427 * operand.
8428 * @param u64VmcsField The VMCS field.
8429 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8430 * NULL.
8431 */
8432static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8433 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8434{
8435 /* Nested-guest intercept. */
8436 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8437 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8438 {
8439 if (pExitInfo)
8440 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8441 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8442 }
8443
8444 /* CPL. */
8445 if (pVCpu->iem.s.uCpl == 0)
8446 { /* likely */ }
8447 else
8448 {
8449 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8450 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8451 return iemRaiseGeneralProtectionFault0(pVCpu);
8452 }
8453
8454 pVCpu->iem.s.cPotentialExits++;
8455
8456 /* VMCS pointer in root mode. */
8457 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8458 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8459 { /* likely */ }
8460 else
8461 {
8462 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8463 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8464 iemVmxVmFailInvalid(pVCpu);
8465 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8466 }
8467
8468 /* VMCS-link pointer in non-root mode. */
8469 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8470 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8471 { /* likely */ }
8472 else
8473 {
8474 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8475 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8476 iemVmxVmFailInvalid(pVCpu);
8477 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8478 }
8479
8480 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8481 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8482 if (!fIsRegOperand)
8483 {
8484 /* Read the value from the specified guest memory location. */
8485 VBOXSTRICTRC rcStrict;
8486 RTGCPTR const GCPtrVal = u64Val;
8487 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8488 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8489 else
8490 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8491 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8492 {
8493 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8494 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8495 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8496 return rcStrict;
8497 }
8498 }
8499 else
8500 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8501
8502 /* Supported VMCS field. */
8503 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8504 { /* likely */ }
8505 else
8506 {
8507 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8508 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8509 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8510 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8511 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8512 }
8513
8514 /* Read-only VMCS field. */
8515 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8516 if ( !fIsFieldReadOnly
8517 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8518 { /* likely */ }
8519 else
8520 {
8521 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8522 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8523 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8524 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8525 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8526 }
8527
8528 /*
8529 * Write to the current or shadow VMCS.
8530 */
8531 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8532 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8533 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8534 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8535 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8536 Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8537
8538 if ( !fInVmxNonRootMode
8539 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8540 {
8541 /* Notify HM that the VMCS content might have changed. */
8542 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8543 }
8544
8545 iemVmxVmSucceed(pVCpu);
8546 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8547}
8548
8549
8550/**
8551 * Interface for HM and EM to emulate the VMWRITE instruction.
8552 *
8553 * @returns Strict VBox status code.
8554 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8555 * @param pExitInfo Pointer to the VM-exit information.
8556 * @thread EMT(pVCpu)
8557 */
8558VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8559{
8560 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8561 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8562 Assert(pExitInfo);
8563
8564 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8565
8566 uint64_t u64Val;
8567 uint8_t iEffSeg;
8568 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8569 {
8570 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8571 iEffSeg = UINT8_MAX;
8572 }
8573 else
8574 {
8575 u64Val = pExitInfo->GCPtrEffAddr;
8576 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8577 }
8578 uint8_t const cbInstr = pExitInfo->cbInstr;
8579 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8580 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8581 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8582 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8583 Assert(!pVCpu->iem.s.cActiveMappings);
8584 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8585}
8586
8587
8588/**
8589 * VMCLEAR instruction execution worker.
8590 *
8591 * @returns Strict VBox status code.
8592 * @param pVCpu The cross context virtual CPU structure.
8593 * @param cbInstr The instruction length in bytes.
8594 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8595 * @param GCPtrVmcs The linear address of the VMCS pointer.
8596 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8597 *
8598 * @remarks Common VMX instruction checks are already expected to by the caller,
8599 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8600 */
8601static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8602 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8603{
8604 /* Nested-guest intercept. */
8605 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8606 {
8607 if (pExitInfo)
8608 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8609 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8610 }
8611
8612 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8613
8614 /* CPL. */
8615 if (pVCpu->iem.s.uCpl == 0)
8616 { /* likely */ }
8617 else
8618 {
8619 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8621 return iemRaiseGeneralProtectionFault0(pVCpu);
8622 }
8623
8624 /* Get the VMCS pointer from the location specified by the source memory operand. */
8625 RTGCPHYS GCPhysVmcs;
8626 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8627 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8628 { /* likely */ }
8629 else
8630 {
8631 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8632 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8633 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8634 return rcStrict;
8635 }
8636
8637 /* VMCS pointer alignment. */
8638 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8639 { /* likely */ }
8640 else
8641 {
8642 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8643 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8644 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8645 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8646 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8647 }
8648
8649 /* VMCS physical-address width limits. */
8650 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8651 { /* likely */ }
8652 else
8653 {
8654 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8655 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8656 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8657 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8658 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8659 }
8660
8661 /* VMCS is not the VMXON region. */
8662 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8663 { /* likely */ }
8664 else
8665 {
8666 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8667 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8668 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8669 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8670 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8671 }
8672
8673 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8674 restriction imposed by our implementation. */
8675 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8676 { /* likely */ }
8677 else
8678 {
8679 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8681 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8682 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8683 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8684 }
8685
8686 /*
8687 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8688 *
8689 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8690 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8691 * to 'clear'.
8692 */
8693 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8694 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8695 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8696 {
8697 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8698 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8699 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8700 }
8701 else
8702 {
8703 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8704 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8705 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8706 if (RT_FAILURE(rcStrict))
8707 return rcStrict;
8708 }
8709
8710 iemVmxVmSucceed(pVCpu);
8711 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8712}
8713
8714
8715/**
8716 * Interface for HM and EM to emulate the VMCLEAR instruction.
8717 *
8718 * @returns Strict VBox status code.
8719 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8720 * @param pExitInfo Pointer to the VM-exit information.
8721 * @thread EMT(pVCpu)
8722 */
8723VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8724{
8725 Assert(pExitInfo);
8726 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8727 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8728
8729 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8730
8731 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8732 uint8_t const cbInstr = pExitInfo->cbInstr;
8733 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8734 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8735 Assert(!pVCpu->iem.s.cActiveMappings);
8736 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8737}
8738
8739
8740/**
8741 * VMPTRST instruction execution worker.
8742 *
8743 * @returns Strict VBox status code.
8744 * @param pVCpu The cross context virtual CPU structure.
8745 * @param cbInstr The instruction length in bytes.
8746 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8747 * @param GCPtrVmcs The linear address of where to store the current VMCS
8748 * pointer.
8749 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8750 *
8751 * @remarks Common VMX instruction checks are already expected to by the caller,
8752 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8753 */
8754static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8755 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8756{
8757 /* Nested-guest intercept. */
8758 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8759 {
8760 if (pExitInfo)
8761 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8762 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8763 }
8764
8765 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8766
8767 /* CPL. */
8768 if (pVCpu->iem.s.uCpl == 0)
8769 { /* likely */ }
8770 else
8771 {
8772 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8773 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8774 return iemRaiseGeneralProtectionFault0(pVCpu);
8775 }
8776
8777 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8778 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8779 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8780 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8781 {
8782 iemVmxVmSucceed(pVCpu);
8783 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8784 }
8785
8786 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8787 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8788 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8789 return rcStrict;
8790}
8791
8792
8793/**
8794 * Interface for HM and EM to emulate the VMPTRST instruction.
8795 *
8796 * @returns Strict VBox status code.
8797 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8798 * @param pExitInfo Pointer to the VM-exit information.
8799 * @thread EMT(pVCpu)
8800 */
8801VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8802{
8803 Assert(pExitInfo);
8804 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8805 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8806
8807 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8808
8809 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8810 uint8_t const cbInstr = pExitInfo->cbInstr;
8811 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8812 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8813 Assert(!pVCpu->iem.s.cActiveMappings);
8814 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8815}
8816
8817
8818/**
8819 * VMPTRLD instruction execution worker.
8820 *
8821 * @returns Strict VBox status code.
8822 * @param pVCpu The cross context virtual CPU structure.
8823 * @param cbInstr The instruction length in bytes.
8824 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8825 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8826 *
8827 * @remarks Common VMX instruction checks are already expected to by the caller,
8828 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8829 */
8830static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8831 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8832{
8833 /* Nested-guest intercept. */
8834 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8835 {
8836 if (pExitInfo)
8837 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8838 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8839 }
8840
8841 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8842
8843 /* CPL. */
8844 if (pVCpu->iem.s.uCpl == 0)
8845 { /* likely */ }
8846 else
8847 {
8848 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8849 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8850 return iemRaiseGeneralProtectionFault0(pVCpu);
8851 }
8852
8853 /* Get the VMCS pointer from the location specified by the source memory operand. */
8854 RTGCPHYS GCPhysVmcs;
8855 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8856 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8857 { /* likely */ }
8858 else
8859 {
8860 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8861 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8862 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8863 return rcStrict;
8864 }
8865
8866 /* VMCS pointer alignment. */
8867 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8868 { /* likely */ }
8869 else
8870 {
8871 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8872 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8873 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8874 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8875 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8876 }
8877
8878 /* VMCS physical-address width limits. */
8879 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8880 { /* likely */ }
8881 else
8882 {
8883 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8884 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8885 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8886 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8887 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8888 }
8889
8890 /* VMCS is not the VMXON region. */
8891 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8892 { /* likely */ }
8893 else
8894 {
8895 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8896 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8897 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8898 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8899 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8900 }
8901
8902 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8903 restriction imposed by our implementation. */
8904 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8905 { /* likely */ }
8906 else
8907 {
8908 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8909 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8910 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8911 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8912 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8913 }
8914
8915 /* Read just the VMCS revision from the VMCS. */
8916 VMXVMCSREVID VmcsRevId;
8917 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8918 if (RT_SUCCESS(rc))
8919 { /* likely */ }
8920 else
8921 {
8922 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8923 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8924 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8925 return rc;
8926 }
8927
8928 /*
8929 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8930 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8931 */
8932 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8933 && ( !VmcsRevId.n.fIsShadowVmcs
8934 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8935 { /* likely */ }
8936 else
8937 {
8938 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8939 {
8940 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8941 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8942 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8943 }
8944 else
8945 {
8946 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8947 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8948 }
8949 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8950 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8951 }
8952
8953 /*
8954 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8955 * the cache of an existing, current VMCS back to guest memory before loading a new,
8956 * different current VMCS.
8957 */
8958 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8959 {
8960 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8961 {
8962 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8963 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8964 }
8965
8966 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8967 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8968 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8969 if (RT_SUCCESS(rc))
8970 {
8971 /* Notify HM that a new, current VMCS is loaded. */
8972 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8973 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8974 }
8975 else
8976 {
8977 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8978 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8979 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8980 return rc;
8981 }
8982 }
8983
8984 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8985 iemVmxVmSucceed(pVCpu);
8986 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8987}
8988
8989
8990/**
8991 * Interface for HM and EM to emulate the VMPTRLD instruction.
8992 *
8993 * @returns Strict VBox status code.
8994 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8995 * @param pExitInfo Pointer to the VM-exit information.
8996 * @thread EMT(pVCpu)
8997 */
8998VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8999{
9000 Assert(pExitInfo);
9001 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9002 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9003
9004 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9005
9006 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9007 uint8_t const cbInstr = pExitInfo->cbInstr;
9008 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
9009 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
9010 Assert(!pVCpu->iem.s.cActiveMappings);
9011 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9012}
9013
9014
9015/**
9016 * INVVPID instruction execution worker.
9017 *
9018 * @returns Strict VBox status code.
9019 * @param pVCpu The cross context virtual CPU structure.
9020 * @param cbInstr The instruction length in bytes.
9021 * @param iEffSeg The segment of the invvpid descriptor.
9022 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
9023 * @param u64InvvpidType The invalidation type.
9024 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9025 * NULL.
9026 *
9027 * @remarks Common VMX instruction checks are already expected to by the caller,
9028 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9029 */
9030VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
9031 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9032{
9033 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
9034 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
9035 return iemRaiseUndefinedOpcode(pVCpu);
9036
9037 /* Nested-guest intercept. */
9038 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9039 {
9040 if (pExitInfo)
9041 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9042 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9043 }
9044
9045 /* CPL. */
9046 if (pVCpu->iem.s.uCpl != 0)
9047 {
9048 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9049 return iemRaiseGeneralProtectionFault0(pVCpu);
9050 }
9051
9052 /*
9053 * Validate INVVPID invalidation type.
9054 *
9055 * The instruction specifies exactly ONE of the supported invalidation types.
9056 *
9057 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9058 * supported. In theory, it's possible for a CPU to not support flushing individual
9059 * addresses but all the other types or any other combination. We do not take any
9060 * shortcuts here by assuming the types we currently expose to the guest.
9061 */
9062 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9063 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9064 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9065 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9066 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9067 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9068
9069 bool afSupportedTypes[4];
9070 afSupportedTypes[0] = fTypeIndivAddr;
9071 afSupportedTypes[1] = fTypeSingleCtx;
9072 afSupportedTypes[2] = fTypeAllCtx;
9073 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9074
9075 if ( fInvvpidSupported
9076 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9077 && afSupportedTypes[u64InvvpidType & 3])
9078 { /* likely */ }
9079 else
9080 {
9081 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9082 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9083 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9084 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9085 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9086 }
9087
9088 /*
9089 * Fetch the invvpid descriptor from guest memory.
9090 */
9091 RTUINT128U uDesc;
9092 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9093 if (rcStrict == VINF_SUCCESS)
9094 {
9095 /*
9096 * Validate the descriptor.
9097 */
9098 if (uDesc.s.Lo <= 0xffff)
9099 { /* likely */ }
9100 else
9101 {
9102 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9103 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9104 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9105 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9106 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9107 }
9108
9109 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9110 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9111 uint16_t const uVpid = uDesc.Words.w0;
9112 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9113 switch (u64InvvpidType)
9114 {
9115 case VMXTLBFLUSHVPID_INDIV_ADDR:
9116 {
9117 if (uVpid != 0)
9118 {
9119 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9120 {
9121 /* Invalidate mappings for the linear address tagged with VPID. */
9122 /** @todo PGM support for VPID? Currently just flush everything. */
9123 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9124 iemVmxVmSucceed(pVCpu);
9125 }
9126 else
9127 {
9128 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9129 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9130 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9131 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9132 }
9133 }
9134 else
9135 {
9136 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9137 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9138 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9139 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9140 }
9141 break;
9142 }
9143
9144 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9145 {
9146 if (uVpid != 0)
9147 {
9148 /* Invalidate all mappings with VPID. */
9149 /** @todo PGM support for VPID? Currently just flush everything. */
9150 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9151 iemVmxVmSucceed(pVCpu);
9152 }
9153 else
9154 {
9155 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9157 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9158 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9159 }
9160 break;
9161 }
9162
9163 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9164 {
9165 /* Invalidate all mappings with non-zero VPIDs. */
9166 /** @todo PGM support for VPID? Currently just flush everything. */
9167 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9168 iemVmxVmSucceed(pVCpu);
9169 break;
9170 }
9171
9172 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9173 {
9174 if (uVpid != 0)
9175 {
9176 /* Invalidate all mappings with VPID except global translations. */
9177 /** @todo PGM support for VPID? Currently just flush everything. */
9178 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9179 iemVmxVmSucceed(pVCpu);
9180 }
9181 else
9182 {
9183 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9184 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9185 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9186 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9187 }
9188 break;
9189 }
9190 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9191 }
9192 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9193 }
9194 return rcStrict;
9195}
9196
9197
9198/**
9199 * Interface for HM and EM to emulate the INVVPID instruction.
9200 *
9201 * @returns Strict VBox status code.
9202 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9203 * @param pExitInfo Pointer to the VM-exit information.
9204 * @thread EMT(pVCpu)
9205 */
9206VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9207{
9208 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9209 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9210 Assert(pExitInfo);
9211
9212 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9213
9214 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9215 uint8_t const cbInstr = pExitInfo->cbInstr;
9216 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9217 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9218 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9219 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9220 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9221 Assert(!pVCpu->iem.s.cActiveMappings);
9222 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9223}
9224
9225#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9226
9227/**
9228 * INVEPT instruction execution worker.
9229 *
9230 * @returns Strict VBox status code.
9231 * @param pVCpu The cross context virtual CPU structure.
9232 * @param cbInstr The instruction length in bytes.
9233 * @param iEffSeg The segment of the invept descriptor.
9234 * @param GCPtrInveptDesc The address of invept descriptor.
9235 * @param u64InveptType The invalidation type.
9236 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9237 * NULL.
9238 *
9239 * @remarks Common VMX instruction checks are already expected to by the caller,
9240 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9241 */
9242static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9243 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9244{
9245 /* Check if EPT is supported, otherwise raise #UD. */
9246 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9247 return iemRaiseUndefinedOpcode(pVCpu);
9248
9249 /* Nested-guest intercept. */
9250 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9251 {
9252 if (pExitInfo)
9253 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9254 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9255 }
9256
9257 /* CPL. */
9258 if (pVCpu->iem.s.uCpl != 0)
9259 {
9260 Log(("invept: CPL != 0 -> #GP(0)\n"));
9261 return iemRaiseGeneralProtectionFault0(pVCpu);
9262 }
9263
9264 /*
9265 * Validate INVEPT invalidation type.
9266 *
9267 * The instruction specifies exactly ONE of the supported invalidation types.
9268 *
9269 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9270 * supported. In theory, it's possible for a CPU to not support flushing individual
9271 * addresses but all the other types or any other combination. We do not take any
9272 * shortcuts here by assuming the types we currently expose to the guest.
9273 */
9274 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9275 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9276 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9277 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9278
9279 bool afSupportedTypes[4];
9280 afSupportedTypes[0] = false;
9281 afSupportedTypes[1] = fTypeSingleCtx;
9282 afSupportedTypes[2] = fTypeAllCtx;
9283 afSupportedTypes[3] = false;
9284
9285 if ( fInveptSupported
9286 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9287 && afSupportedTypes[u64InveptType & 3])
9288 { /* likely */ }
9289 else
9290 {
9291 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9292 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9293 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9294 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9295 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9296 }
9297
9298 /*
9299 * Fetch the invept descriptor from guest memory.
9300 */
9301 RTUINT128U uDesc;
9302 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9303 if (rcStrict == VINF_SUCCESS)
9304 {
9305 /*
9306 * Validate the descriptor.
9307 *
9308 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9309 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9310 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9311 * better to be strict in our emulation until proven otherwise.
9312 */
9313 if (uDesc.s.Hi)
9314 {
9315 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9316 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9317 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9318 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9319 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9320 }
9321
9322 /*
9323 * Flush TLB mappings based on the EPT type.
9324 */
9325 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9326 {
9327 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9328 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9329 if (RT_SUCCESS(rc))
9330 { /* likely */ }
9331 else
9332 {
9333 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9334 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9335 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9336 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9337 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9338 }
9339 }
9340
9341 /** @todo PGM support for EPT tags? Currently just flush everything. */
9342 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9343 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9344 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9345
9346 iemVmxVmSucceed(pVCpu);
9347 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9348 }
9349
9350 return rcStrict;
9351}
9352
9353
9354/**
9355 * Interface for HM and EM to emulate the INVEPT instruction.
9356 *
9357 * @returns Strict VBox status code.
9358 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9359 * @param pExitInfo Pointer to the VM-exit information.
9360 * @thread EMT(pVCpu)
9361 */
9362VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9363{
9364 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9365 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9366 Assert(pExitInfo);
9367
9368 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9369
9370 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9371 uint8_t const cbInstr = pExitInfo->cbInstr;
9372 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9373 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9374 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9375 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9376 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9377 Assert(!pVCpu->iem.s.cActiveMappings);
9378 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9379}
9380
9381#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9382
9383/**
9384 * VMXON instruction execution worker.
9385 *
9386 * @returns Strict VBox status code.
9387 * @param pVCpu The cross context virtual CPU structure.
9388 * @param cbInstr The instruction length in bytes.
9389 * @param iEffSeg The effective segment register to use with @a
9390 * GCPtrVmxon.
9391 * @param GCPtrVmxon The linear address of the VMXON pointer.
9392 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9393 *
9394 * @remarks Common VMX instruction checks are already expected to by the caller,
9395 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9396 */
9397static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9398 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9399{
9400 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9401 {
9402 /* CPL. */
9403 if (pVCpu->iem.s.uCpl == 0)
9404 { /* likely */ }
9405 else
9406 {
9407 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9408 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9409 return iemRaiseGeneralProtectionFault0(pVCpu);
9410 }
9411
9412 /* A20M (A20 Masked) mode. */
9413 if (PGMPhysIsA20Enabled(pVCpu))
9414 { /* likely */ }
9415 else
9416 {
9417 Log(("vmxon: A20M mode -> #GP(0)\n"));
9418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9419 return iemRaiseGeneralProtectionFault0(pVCpu);
9420 }
9421
9422 /* CR0. */
9423 {
9424 /*
9425 * CR0 MB1 bits.
9426 *
9427 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9428 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9429 * when the guest running in VMX non-root mode with unrestricted-guest control
9430 * enabled in the VMCS.
9431 */
9432 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9433 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9434 { /* likely */ }
9435 else
9436 {
9437 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9438 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9439 return iemRaiseGeneralProtectionFault0(pVCpu);
9440 }
9441
9442 /* CR0 MBZ bits. */
9443 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9444 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9445 { /* likely */ }
9446 else
9447 {
9448 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9449 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9450 return iemRaiseGeneralProtectionFault0(pVCpu);
9451 }
9452 }
9453
9454 /* CR4. */
9455 {
9456 /* CR4 MB1 bits. */
9457 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9458 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9459 { /* likely */ }
9460 else
9461 {
9462 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9463 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9464 return iemRaiseGeneralProtectionFault0(pVCpu);
9465 }
9466
9467 /* CR4 MBZ bits. */
9468 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9469 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9470 { /* likely */ }
9471 else
9472 {
9473 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9474 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9475 return iemRaiseGeneralProtectionFault0(pVCpu);
9476 }
9477 }
9478
9479 /* Feature control MSR's LOCK and VMXON bits. */
9480 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9481 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9482 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9483 { /* likely */ }
9484 else
9485 {
9486 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9487 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9488 return iemRaiseGeneralProtectionFault0(pVCpu);
9489 }
9490
9491 /* Get the VMXON pointer from the location specified by the source memory operand. */
9492 RTGCPHYS GCPhysVmxon;
9493 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9494 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9495 { /* likely */ }
9496 else
9497 {
9498 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9499 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9500 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9501 return rcStrict;
9502 }
9503
9504 /* VMXON region pointer alignment. */
9505 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9506 { /* likely */ }
9507 else
9508 {
9509 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9510 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9511 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9512 iemVmxVmFailInvalid(pVCpu);
9513 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9514 }
9515
9516 /* VMXON physical-address width limits. */
9517 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9518 { /* likely */ }
9519 else
9520 {
9521 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9522 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9523 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9524 iemVmxVmFailInvalid(pVCpu);
9525 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9526 }
9527
9528 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9529 restriction imposed by our implementation. */
9530 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9531 { /* likely */ }
9532 else
9533 {
9534 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9535 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9536 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9537 iemVmxVmFailInvalid(pVCpu);
9538 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9539 }
9540
9541 /* Read the VMCS revision ID from the VMXON region. */
9542 VMXVMCSREVID VmcsRevId;
9543 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9544 if (RT_SUCCESS(rc))
9545 { /* likely */ }
9546 else
9547 {
9548 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9549 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9550 return rc;
9551 }
9552
9553 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9554 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9555 { /* likely */ }
9556 else
9557 {
9558 /* Revision ID mismatch. */
9559 if (!VmcsRevId.n.fIsShadowVmcs)
9560 {
9561 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9562 VmcsRevId.n.u31RevisionId));
9563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9564 iemVmxVmFailInvalid(pVCpu);
9565 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9566 }
9567
9568 /* Shadow VMCS disallowed. */
9569 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9570 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9571 iemVmxVmFailInvalid(pVCpu);
9572 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9573 }
9574
9575 /*
9576 * Record that we're in VMX operation, block INIT, block and disable A20M.
9577 */
9578 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9579 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9580 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9581
9582 /* Clear address-range monitoring. */
9583 EMMonitorWaitClear(pVCpu);
9584 /** @todo NSTVMX: Intel PT. */
9585
9586 iemVmxVmSucceed(pVCpu);
9587 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9588 }
9589 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9590 {
9591 /* Nested-guest intercept. */
9592 if (pExitInfo)
9593 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9594 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9595 }
9596
9597 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9598
9599 /* CPL. */
9600 if (pVCpu->iem.s.uCpl > 0)
9601 {
9602 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9603 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9604 return iemRaiseGeneralProtectionFault0(pVCpu);
9605 }
9606
9607 /* VMXON when already in VMX root mode. */
9608 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9609 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9610 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9611}
9612
9613
9614/**
9615 * Interface for HM and EM to emulate the VMXON instruction.
9616 *
9617 * @returns Strict VBox status code.
9618 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9619 * @param pExitInfo Pointer to the VM-exit information.
9620 * @thread EMT(pVCpu)
9621 */
9622VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9623{
9624 Assert(pExitInfo);
9625 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9626 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9627
9628 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9629
9630 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9631 uint8_t const cbInstr = pExitInfo->cbInstr;
9632 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9633 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9634 Assert(!pVCpu->iem.s.cActiveMappings);
9635 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9636}
9637
9638
9639/**
9640 * Implements 'VMXOFF'.
9641 *
9642 * @remarks Common VMX instruction checks are already expected to by the caller,
9643 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9644 */
9645IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9646{
9647 /* Nested-guest intercept. */
9648 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9649 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9650
9651 /* CPL. */
9652 if (pVCpu->iem.s.uCpl == 0)
9653 { /* likely */ }
9654 else
9655 {
9656 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9657 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9658 return iemRaiseGeneralProtectionFault0(pVCpu);
9659 }
9660
9661 /* Dual monitor treatment of SMIs and SMM. */
9662 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9663 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9664 { /* likely */ }
9665 else
9666 {
9667 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9668 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9669 }
9670
9671 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9672 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9673 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9674
9675 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9676 { /** @todo NSTVMX: Unblock SMI. */ }
9677
9678 EMMonitorWaitClear(pVCpu);
9679 /** @todo NSTVMX: Unblock and enable A20M. */
9680
9681 iemVmxVmSucceed(pVCpu);
9682 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9683}
9684
9685
9686/**
9687 * Interface for HM and EM to emulate the VMXOFF instruction.
9688 *
9689 * @returns Strict VBox status code.
9690 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9691 * @param cbInstr The instruction length in bytes.
9692 * @thread EMT(pVCpu)
9693 */
9694VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9695{
9696 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9697 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9698
9699 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9700 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9701 Assert(!pVCpu->iem.s.cActiveMappings);
9702 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9703}
9704
9705
9706/**
9707 * Implements 'VMXON'.
9708 */
9709IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9710{
9711 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9712}
9713
9714
9715/**
9716 * Implements 'VMLAUNCH'.
9717 */
9718IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9719{
9720 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9721}
9722
9723
9724/**
9725 * Implements 'VMRESUME'.
9726 */
9727IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9728{
9729 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9730}
9731
9732
9733/**
9734 * Implements 'VMPTRLD'.
9735 */
9736IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9737{
9738 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9739}
9740
9741
9742/**
9743 * Implements 'VMPTRST'.
9744 */
9745IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9746{
9747 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9748}
9749
9750
9751/**
9752 * Implements 'VMCLEAR'.
9753 */
9754IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9755{
9756 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9757}
9758
9759
9760/**
9761 * Implements 'VMWRITE' register.
9762 */
9763IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9764{
9765 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9766}
9767
9768
9769/**
9770 * Implements 'VMWRITE' memory.
9771 */
9772IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9773{
9774 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9775}
9776
9777
9778/**
9779 * Implements 'VMREAD' register (64-bit).
9780 */
9781IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9782{
9783 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9784}
9785
9786
9787/**
9788 * Implements 'VMREAD' register (32-bit).
9789 */
9790IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint64_t *, pu64Dst, uint32_t, u32VmcsField)
9791{
9792 VBOXSTRICTRC const rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, (uint32_t *)pu64Dst, u32VmcsField, NULL /* pExitInfo */);
9793 /* Zero the high part of the register on success. */
9794 if (rcStrict == VINF_SUCCESS)
9795 *pu64Dst = (uint32_t)*pu64Dst;
9796 return rcStrict;
9797}
9798
9799
9800/**
9801 * Implements 'VMREAD' memory, 64-bit register.
9802 */
9803IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9804{
9805 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9806}
9807
9808
9809/**
9810 * Implements 'VMREAD' memory, 32-bit register.
9811 */
9812IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9813{
9814 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9815}
9816
9817
9818/**
9819 * Implements 'INVVPID'.
9820 */
9821IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9822{
9823 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9824}
9825
9826
9827#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9828/**
9829 * Implements 'INVEPT'.
9830 */
9831IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9832{
9833 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9834}
9835#endif
9836
9837
9838/**
9839 * Implements VMX's implementation of PAUSE.
9840 */
9841IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9842{
9843 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9844 {
9845 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9846 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9847 return rcStrict;
9848 }
9849
9850 /*
9851 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9852 * a VM-exit, the instruction operates normally.
9853 */
9854 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9855}
9856
9857#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9858
9859
9860/**
9861 * Implements 'VMCALL'.
9862 */
9863IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9864{
9865 pVCpu->iem.s.cPotentialExits++;
9866
9867#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9868 /* Nested-guest intercept. */
9869 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9870 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9871#endif
9872
9873 /* Join forces with vmmcall. */
9874 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9875}
9876
9877
9878#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9879
9880/**
9881 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9882 *
9883 * @remarks The @a uUser argument is currently unused.
9884 */
9885DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9886 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9887 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9888{
9889 RT_NOREF3(pvPhys, enmOrigin, uUser);
9890
9891 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9892 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9893 {
9894 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9895 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9896
9897 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9898 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9899
9900 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9901 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9902 if (RT_FAILURE(rcStrict))
9903 return rcStrict;
9904
9905 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9906 return VINF_SUCCESS;
9907 }
9908
9909 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9910 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9911 if (RT_FAILURE(rc))
9912 return rc;
9913
9914 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9915 return VINF_PGM_HANDLER_DO_DEFAULT;
9916}
9917
9918
9919# ifndef IN_RING3
9920/**
9921 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9922 * \#PF access handler callback for guest VMX APIC-access page.}
9923 */
9924DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
9925 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9926
9927{
9928 RT_NOREF3(pVM, pCtx, uUser);
9929
9930 /*
9931 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9932 * Otherwise we must deregister the page and allow regular RAM access.
9933 * Failing to do so lands us with endless EPT VM-exits.
9934 */
9935 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9936 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9937 {
9938 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9939 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9940
9941 /*
9942 * Check if the access causes an APIC-access VM-exit.
9943 */
9944 uint32_t fAccess;
9945 if (uErr & X86_TRAP_PF_ID)
9946 fAccess = IEM_ACCESS_INSTRUCTION;
9947 else if (uErr & X86_TRAP_PF_RW)
9948 fAccess = IEM_ACCESS_DATA_W;
9949 else
9950 fAccess = IEM_ACCESS_DATA_R;
9951
9952 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9953 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9954 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9955 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9956 if (fIntercept)
9957 {
9958 /*
9959 * Query the source VM-exit (from the execution engine) that caused this access
9960 * within the APIC-access page. Currently only HM is supported.
9961 */
9962 AssertMsg(VM_IS_HM_ENABLED(pVM),
9963 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9964
9965 HMEXITAUX HmExitAux;
9966 RT_ZERO(HmExitAux);
9967 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9968 | HMVMX_READ_EXIT_QUALIFICATION
9969 | HMVMX_READ_IDT_VECTORING_INFO
9970 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9971 AssertRC(rc);
9972
9973 /*
9974 * Verify the VM-exit reason must be an EPT violation.
9975 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9976 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9977 */
9978 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9979 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9980 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9981
9982 /*
9983 * Construct the virtual APIC-access VM-exit.
9984 */
9985 VMXAPICACCESS enmAccess;
9986 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9987 {
9988 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9989 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9990 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9991 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9992 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9993 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9994 else
9995 enmAccess = VMXAPICACCESS_LINEAR_READ;
9996
9997 /* For linear-address accesss the instruction length must be valid. */
9998 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9999 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
10000 }
10001 else
10002 {
10003 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
10004 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
10005 else
10006 {
10007 /** @todo How to distinguish between monitoring/trace vs other instructions
10008 * here? */
10009 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
10010 }
10011
10012 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
10013 HmExitAux.Vmx.cbInstr = 0;
10014 }
10015
10016 /*
10017 * Raise the APIC-access VM-exit.
10018 */
10019 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
10020 VMXVEXITINFO const ExitInfo
10021 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
10022 RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
10023 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
10024 HmExitAux.Vmx.cbInstr);
10025 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
10026 HmExitAux.Vmx.uIdtVectoringErrCode);
10027 VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
10028 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
10029 }
10030
10031 /*
10032 * The access isn't intercepted, which means it needs to be virtualized.
10033 *
10034 * This requires emulating the instruction because we need the bytes being
10035 * read/written by the instruction not just the offset being accessed within
10036 * the APIC-access page (which we derive from the faulting address).
10037 */
10038 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
10039 return VINF_EM_RAW_EMULATE_INSTR;
10040 }
10041
10042 /** @todo This isn't ideal but works for now as nested-hypervisors generally play
10043 * nice because the spec states that this page should be modified only when
10044 * no CPU refers to it VMX non-root mode. Nonetheless, we could use an atomic
10045 * reference counter to ensure the aforementioned condition before
10046 * de-registering the page. */
10047 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10048 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10049 if (RT_FAILURE(rc))
10050 return rc;
10051
10052 return VINF_SUCCESS;
10053}
10054# endif /* !IN_RING3 */
10055
10056#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10057
注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette