VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 80317

最後變更 在這個檔案從80317是 80268,由 vboxsync 提交於 6 年 前

VMM: Refactoring VMMAll/* to use VMCC & VMMCPUCC. bugref:9217
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 348.3 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 80268 2019-08-14 11:25:13Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Converts an IEM exception event type to a VMX event type.
621 *
622 * @returns The VMX event type.
623 * @param uVector The interrupt / exception vector.
624 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
625 */
626DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
627{
628 /* Paranoia (callers may use these interchangeably). */
629 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
630 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
631 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
632 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
633 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
634 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
635 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
636 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
637 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
638 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
639 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
640 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
641
642 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
643 {
644 if (uVector == X86_XCPT_NMI)
645 return VMX_EXIT_INT_INFO_TYPE_NMI;
646 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
647 }
648
649 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
650 {
651 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
652 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
653 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
654 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
655 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
656 }
657
658 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
659 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
660}
661
662
663/**
664 * Sets the Exit qualification VMCS field.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param u64ExitQual The Exit qualification.
668 */
669DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
670{
671 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
672 pVmcs->u64RoExitQual.u = u64ExitQual;
673}
674
675
676/**
677 * Sets the VM-exit interruption information field.
678 *
679 * @param pVCpu The cross context virtual CPU structure.
680 * @param uExitIntInfo The VM-exit interruption information.
681 */
682DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
683{
684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
685 pVmcs->u32RoExitIntInfo = uExitIntInfo;
686}
687
688
689/**
690 * Sets the VM-exit interruption error code.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uErrCode The error code.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
696{
697 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
698 pVmcs->u32RoExitIntErrCode = uErrCode;
699}
700
701
702/**
703 * Sets the IDT-vectoring information field.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param uIdtVectorInfo The IDT-vectoring information.
707 */
708DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
709{
710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
711 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
712}
713
714
715/**
716 * Sets the IDT-vectoring error code field.
717 *
718 * @param pVCpu The cross context virtual CPU structure.
719 * @param uErrCode The error code.
720 */
721DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
722{
723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
724 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
725}
726
727
728/**
729 * Sets the VM-exit guest-linear address VMCS field.
730 *
731 * @param pVCpu The cross context virtual CPU structure.
732 * @param uGuestLinearAddr The VM-exit guest-linear address.
733 */
734DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
735{
736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
737 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
738}
739
740
741/**
742 * Sets the VM-exit guest-physical address VMCS field.
743 *
744 * @param pVCpu The cross context virtual CPU structure.
745 * @param uGuestPhysAddr The VM-exit guest-physical address.
746 */
747DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
748{
749 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
750 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
751}
752
753
754/**
755 * Sets the VM-exit instruction length VMCS field.
756 *
757 * @param pVCpu The cross context virtual CPU structure.
758 * @param cbInstr The VM-exit instruction length in bytes.
759 *
760 * @remarks Callers may clear this field to 0. Hence, this function does not check
761 * the validity of the instruction length.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
764{
765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
766 pVmcs->u32RoExitInstrLen = cbInstr;
767}
768
769
770/**
771 * Sets the VM-exit instruction info. VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uExitInstrInfo The VM-exit instruction information.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
777{
778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
779 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
780}
781
782
783/**
784 * Implements VMSucceed for VMX instruction success.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 */
788DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
789{
790 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
791}
792
793
794/**
795 * Implements VMFailInvalid for VMX instruction failure.
796 *
797 * @param pVCpu The cross context virtual CPU structure.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
800{
801 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
802}
803
804
805/**
806 * Implements VMFail for VMX instruction failure.
807 *
808 * @param pVCpu The cross context virtual CPU structure.
809 * @param enmInsErr The VM instruction error.
810 */
811DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
812{
813 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
814}
815
816
817/**
818 * Checks if the given auto-load/store MSR area count is valid for the
819 * implementation.
820 *
821 * @returns @c true if it's within the valid limit, @c false otherwise.
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param uMsrCount The MSR area count to check.
824 */
825DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
826{
827 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
828 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
829 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
830 if (uMsrCount <= cMaxSupportedMsrs)
831 return true;
832 return false;
833}
834
835
836/**
837 * Flushes the current VMCS contents back to guest memory.
838 *
839 * @returns VBox status code.
840 * @param pVCpu The cross context virtual CPU structure.
841 */
842DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
843{
844 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
845 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
846 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
847 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
848 return rc;
849}
850
851
852/**
853 * Populates the current VMCS contents from guest memory.
854 *
855 * @returns VBox status code.
856 * @param pVCpu The cross context virtual CPU structure.
857 */
858DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
859{
860 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
861 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
862 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
863 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
864 return rc;
865}
866
867
868/**
869 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
870 *
871 * @param pVCpu The cross context virtual CPU structure.
872 */
873DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
874{
875 iemVmxVmSucceed(pVCpu);
876 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
877}
878
879
880/**
881 * Gets the instruction diagnostic for segment base checks during VM-entry of a
882 * nested-guest.
883 *
884 * @param iSegReg The segment index (X86_SREG_XXX).
885 */
886IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
887{
888 switch (iSegReg)
889 {
890 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
891 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
892 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
893 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
894 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
895 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
896 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
897 }
898}
899
900
901/**
902 * Gets the instruction diagnostic for segment base checks during VM-entry of a
903 * nested-guest that is in Virtual-8086 mode.
904 *
905 * @param iSegReg The segment index (X86_SREG_XXX).
906 */
907IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
908{
909 switch (iSegReg)
910 {
911 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
912 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
913 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
914 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
915 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
916 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
917 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
918 }
919}
920
921
922/**
923 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
924 * nested-guest that is in Virtual-8086 mode.
925 *
926 * @param iSegReg The segment index (X86_SREG_XXX).
927 */
928IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
929{
930 switch (iSegReg)
931 {
932 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
933 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
934 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
935 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
936 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
937 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
938 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
939 }
940}
941
942
943/**
944 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
945 * nested-guest that is in Virtual-8086 mode.
946 *
947 * @param iSegReg The segment index (X86_SREG_XXX).
948 */
949IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
950{
951 switch (iSegReg)
952 {
953 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
954 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
955 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
956 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
957 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
958 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
959 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
960 }
961}
962
963
964/**
965 * Gets the instruction diagnostic for segment attributes reserved bits failure
966 * during VM-entry of a nested-guest.
967 *
968 * @param iSegReg The segment index (X86_SREG_XXX).
969 */
970IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
971{
972 switch (iSegReg)
973 {
974 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
975 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
976 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
977 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
978 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
979 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
980 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
981 }
982}
983
984
985/**
986 * Gets the instruction diagnostic for segment attributes descriptor-type
987 * (code/segment or system) failure during VM-entry of a nested-guest.
988 *
989 * @param iSegReg The segment index (X86_SREG_XXX).
990 */
991IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
992{
993 switch (iSegReg)
994 {
995 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
996 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
997 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
998 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
999 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1000 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1001 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1002 }
1003}
1004
1005
1006/**
1007 * Gets the instruction diagnostic for segment attributes descriptor-type
1008 * (code/segment or system) failure during VM-entry of a nested-guest.
1009 *
1010 * @param iSegReg The segment index (X86_SREG_XXX).
1011 */
1012IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1013{
1014 switch (iSegReg)
1015 {
1016 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1017 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1018 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1019 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1020 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1021 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1022 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1023 }
1024}
1025
1026
1027/**
1028 * Gets the instruction diagnostic for segment attribute granularity failure during
1029 * VM-entry of a nested-guest.
1030 *
1031 * @param iSegReg The segment index (X86_SREG_XXX).
1032 */
1033IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1034{
1035 switch (iSegReg)
1036 {
1037 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1038 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1039 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1040 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1041 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1042 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1043 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1044 }
1045}
1046
1047/**
1048 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1049 * VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attribute type accessed failure
1070 * during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1091 * failure during VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The PDPTE entry index.
1094 */
1095IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1096{
1097 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1098 switch (iPdpte)
1099 {
1100 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1101 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1102 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1103 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1104 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1105 }
1106}
1107
1108
1109/**
1110 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1111 * failure during VM-exit of a nested-guest.
1112 *
1113 * @param iSegReg The PDPTE entry index.
1114 */
1115IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1116{
1117 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1118 switch (iPdpte)
1119 {
1120 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1121 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1122 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1123 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1124 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1125 }
1126}
1127
1128
1129/**
1130 * Saves the guest control registers, debug registers and some MSRs are part of
1131 * VM-exit.
1132 *
1133 * @param pVCpu The cross context virtual CPU structure.
1134 */
1135IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1136{
1137 /*
1138 * Saves the guest control registers, debug registers and some MSRs.
1139 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1140 */
1141 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1142
1143 /* Save control registers. */
1144 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1145 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1146 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1147
1148 /* Save SYSENTER CS, ESP, EIP. */
1149 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1150 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1151 {
1152 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1153 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1154 }
1155 else
1156 {
1157 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1158 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1159 }
1160
1161 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1162 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1163 {
1164 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1165 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1166 }
1167
1168 /* Save PAT MSR. */
1169 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1170 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1171
1172 /* Save EFER MSR. */
1173 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1174 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1175
1176 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1177 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1178
1179 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1180}
1181
1182
1183/**
1184 * Saves the guest force-flags in preparation of entering the nested-guest.
1185 *
1186 * @param pVCpu The cross context virtual CPU structure.
1187 */
1188IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1189{
1190 /* We shouldn't be called multiple times during VM-entry. */
1191 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1192
1193 /* MTF should not be set outside VMX non-root mode. */
1194 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1195
1196 /*
1197 * Preserve the required force-flags.
1198 *
1199 * We cache and clear force-flags that would affect the execution of the
1200 * nested-guest. Cached flags are then restored while returning to the guest
1201 * if necessary.
1202 *
1203 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1204 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1205 * instruction. Interrupt inhibition for any nested-guest instruction
1206 * is supplied by the guest-interruptibility state VMCS field and will
1207 * be set up as part of loading the guest state.
1208 *
1209 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1210 * successful VM-entry (due to invalid guest-state) need to continue
1211 * blocking NMIs if it was in effect before VM-entry.
1212 *
1213 * - MTF need not be preserved as it's used only in VMX non-root mode and
1214 * is supplied through the VM-execution controls.
1215 *
1216 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1217 * we will be able to generate interrupts that may cause VM-exits for
1218 * the nested-guest.
1219 */
1220 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1221}
1222
1223
1224/**
1225 * Restores the guest force-flags in preparation of exiting the nested-guest.
1226 *
1227 * @param pVCpu The cross context virtual CPU structure.
1228 */
1229IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1230{
1231 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1232 {
1233 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1235 }
1236}
1237
1238
1239/**
1240 * Perform a VMX transition updated PGM, IEM and CPUM.
1241 *
1242 * @param pVCpu The cross context virtual CPU structure.
1243 */
1244IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1245{
1246 /*
1247 * Inform PGM about paging mode changes.
1248 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1249 * see comment in iemMemPageTranslateAndCheckAccess().
1250 */
1251 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1252# ifdef IN_RING3
1253 Assert(rc != VINF_PGM_CHANGE_MODE);
1254# endif
1255 AssertRCReturn(rc, rc);
1256
1257 /* Inform CPUM (recompiler), can later be removed. */
1258 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1259
1260 /*
1261 * Flush the TLB with new CR3. This is required in case the PGM mode change
1262 * above doesn't actually change anything.
1263 */
1264 if (rc == VINF_SUCCESS)
1265 {
1266 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1267 AssertRCReturn(rc, rc);
1268 }
1269
1270 /* Re-initialize IEM cache/state after the drastic mode switch. */
1271 iemReInitExec(pVCpu);
1272 return rc;
1273}
1274
1275
1276/**
1277 * Calculates the current VMX-preemption timer value.
1278 *
1279 * @returns The current VMX-preemption timer value.
1280 * @param pVCpu The cross context virtual CPU structure.
1281 */
1282IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1283{
1284 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1285 Assert(pVmcs);
1286
1287 /*
1288 * Assume the following:
1289 * PreemptTimerShift = 5
1290 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1291 * EntryTick = 50000 (TSC at time of VM-entry)
1292 *
1293 * CurTick Delta PreemptTimerVal
1294 * ----------------------------------
1295 * 60000 10000 2
1296 * 80000 30000 1
1297 * 90000 40000 0 -> VM-exit.
1298 *
1299 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1300 * The saved VMX-preemption timer value is calculated as follows:
1301 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1302 * E.g.:
1303 * Delta = 10000
1304 * Tmp = 10000 / (2 * 10000) = 0.5
1305 * NewPt = 2 - 0.5 = 2
1306 * Delta = 30000
1307 * Tmp = 30000 / (2 * 10000) = 1.5
1308 * NewPt = 2 - 1.5 = 1
1309 * Delta = 40000
1310 * Tmp = 40000 / 20000 = 2
1311 * NewPt = 2 - 2 = 0
1312 */
1313 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1314 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1315 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1316 uint64_t const uDelta = uCurTick - uEntryTick;
1317 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1318 uint32_t const uPreemptTimer = uVmcsPreemptVal
1319 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1320 return uPreemptTimer;
1321}
1322
1323
1324/**
1325 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1326 *
1327 * @param pVCpu The cross context virtual CPU structure.
1328 */
1329IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1330{
1331 /*
1332 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1333 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1334 */
1335 /* CS, SS, ES, DS, FS, GS. */
1336 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1337 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1338 {
1339 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1340 if (!pSelReg->Attr.n.u1Unusable)
1341 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1342 else
1343 {
1344 /*
1345 * For unusable segments the attributes are undefined except for CS and SS.
1346 * For the rest we don't bother preserving anything but the unusable bit.
1347 */
1348 switch (iSegReg)
1349 {
1350 case X86_SREG_CS:
1351 pVmcs->GuestCs = pSelReg->Sel;
1352 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1353 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1354 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1355 | X86DESCATTR_UNUSABLE);
1356 break;
1357
1358 case X86_SREG_SS:
1359 pVmcs->GuestSs = pSelReg->Sel;
1360 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1361 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1362 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1363 break;
1364
1365 case X86_SREG_DS:
1366 pVmcs->GuestDs = pSelReg->Sel;
1367 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1368 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1369 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1370 break;
1371
1372 case X86_SREG_ES:
1373 pVmcs->GuestEs = pSelReg->Sel;
1374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1375 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1376 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1377 break;
1378
1379 case X86_SREG_FS:
1380 pVmcs->GuestFs = pSelReg->Sel;
1381 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1382 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1383 break;
1384
1385 case X86_SREG_GS:
1386 pVmcs->GuestGs = pSelReg->Sel;
1387 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1388 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1389 break;
1390 }
1391 }
1392 }
1393
1394 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1395 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1396 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1397 | X86DESCATTR_UNUSABLE;
1398 /* LDTR. */
1399 {
1400 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1401 pVmcs->GuestLdtr = pSelReg->Sel;
1402 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1403 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1404 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1405 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1406 }
1407
1408 /* TR. */
1409 {
1410 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1411 pVmcs->GuestTr = pSelReg->Sel;
1412 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1413 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1414 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1415 }
1416
1417 /* GDTR. */
1418 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1419 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1420
1421 /* IDTR. */
1422 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1423 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1424}
1425
1426
1427/**
1428 * Saves guest non-register state as part of VM-exit.
1429 *
1430 * @param pVCpu The cross context virtual CPU structure.
1431 * @param uExitReason The VM-exit reason.
1432 */
1433IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1434{
1435 /*
1436 * Save guest non-register state.
1437 * See Intel spec. 27.3.4 "Saving Non-Register State".
1438 */
1439 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1440
1441 /*
1442 * Activity state.
1443 * Most VM-exits will occur in the active state. However, if the first instruction
1444 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1445 * the VM-exit will be from the HLT activity state.
1446 *
1447 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1448 */
1449 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1450 * not? */
1451 EMSTATE const enmActivityState = EMGetState(pVCpu);
1452 switch (enmActivityState)
1453 {
1454 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1455 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1456 }
1457
1458 /*
1459 * Interruptibility-state.
1460 */
1461 /* NMI. */
1462 pVmcs->u32GuestIntrState = 0;
1463 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1464 {
1465 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1466 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1467 }
1468 else
1469 {
1470 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1471 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1472 }
1473
1474 /* Blocking-by-STI. */
1475 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1476 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1477 {
1478 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1479 * currently. */
1480 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1481 }
1482 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1483
1484 /*
1485 * Pending debug exceptions.
1486 */
1487 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1488 && uExitReason != VMX_EXIT_SMI
1489 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1490 && !VMXIsVmexitTrapLike(uExitReason))
1491 {
1492 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1493 * block-by-MovSS is in effect. */
1494 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1495 }
1496 else
1497 {
1498 /*
1499 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1500 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1501 *
1502 * See Intel spec. 24.4.2 "Guest Non-Register State".
1503 */
1504 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1505 * DR6. */
1506 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1507 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1508 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1509 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1510 if (fPendingDbgMask & fBpHitMask)
1511 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1512 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1513 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1514 }
1515
1516 /*
1517 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1518 *
1519 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1520 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1521 */
1522 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1523 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1524 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1525
1526 /* PDPTEs. */
1527 /* We don't support EPT yet. */
1528 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1529 pVmcs->u64GuestPdpte0.u = 0;
1530 pVmcs->u64GuestPdpte1.u = 0;
1531 pVmcs->u64GuestPdpte2.u = 0;
1532 pVmcs->u64GuestPdpte3.u = 0;
1533}
1534
1535
1536/**
1537 * Saves the guest-state as part of VM-exit.
1538 *
1539 * @returns VBox status code.
1540 * @param pVCpu The cross context virtual CPU structure.
1541 * @param uExitReason The VM-exit reason.
1542 */
1543IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1544{
1545 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1546 Assert(pVmcs);
1547
1548 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1549 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1550
1551 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1552 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1553 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1554
1555 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1556}
1557
1558
1559/**
1560 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1561 *
1562 * @returns VBox status code.
1563 * @param pVCpu The cross context virtual CPU structure.
1564 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1565 */
1566IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1567{
1568 /*
1569 * Save guest MSRs.
1570 * See Intel spec. 27.4 "Saving MSRs".
1571 */
1572 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1573 const char *const pszFailure = "VMX-abort";
1574
1575 /*
1576 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1577 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1578 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1579 */
1580 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1581 if (!cMsrs)
1582 return VINF_SUCCESS;
1583
1584 /*
1585 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1586 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1587 * implementation causes a VMX-abort followed by a triple-fault.
1588 */
1589 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1590 if (fIsMsrCountValid)
1591 { /* likely */ }
1592 else
1593 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1594
1595 /*
1596 * Optimization if the guest hypervisor is using the same guest-physical page for both
1597 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1598 */
1599 PVMXAUTOMSR pMsrArea;
1600 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1601 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1602 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1603 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1604 else
1605 {
1606 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1607 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1608 if (RT_SUCCESS(rc))
1609 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1610 else
1611 {
1612 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1613 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1614 }
1615 }
1616
1617 /*
1618 * Update VM-exit MSR store area.
1619 */
1620 PVMXAUTOMSR pMsr = pMsrArea;
1621 Assert(pMsr);
1622 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1623 {
1624 if ( !pMsr->u32Reserved
1625 && pMsr->u32Msr != MSR_IA32_SMBASE
1626 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1627 {
1628 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1629 if (rcStrict == VINF_SUCCESS)
1630 continue;
1631
1632 /*
1633 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1634 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1635 * recording the MSR index in the auxiliary info. field and indicated further by our
1636 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1637 * if possible, or come up with a better, generic solution.
1638 */
1639 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1640 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1641 ? kVmxVDiag_Vmexit_MsrStoreRing3
1642 : kVmxVDiag_Vmexit_MsrStore;
1643 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1644 }
1645 else
1646 {
1647 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1648 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1649 }
1650 }
1651
1652 /*
1653 * Commit the VM-exit MSR store are to guest memory.
1654 */
1655 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1656 if (RT_SUCCESS(rc))
1657 return VINF_SUCCESS;
1658
1659 NOREF(uExitReason);
1660 NOREF(pszFailure);
1661
1662 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1663 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1664}
1665
1666
1667/**
1668 * Performs a VMX abort (due to an fatal error during VM-exit).
1669 *
1670 * @returns Strict VBox status code.
1671 * @param pVCpu The cross context virtual CPU structure.
1672 * @param enmAbort The VMX abort reason.
1673 */
1674IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1675{
1676 /*
1677 * Perform the VMX abort.
1678 * See Intel spec. 27.7 "VMX Aborts".
1679 */
1680 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1681
1682 /* We don't support SMX yet. */
1683 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1684 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1685 {
1686 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1687 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1688 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1689 }
1690
1691 return VINF_EM_TRIPLE_FAULT;
1692}
1693
1694
1695/**
1696 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1697 *
1698 * @param pVCpu The cross context virtual CPU structure.
1699 */
1700IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1701{
1702 /*
1703 * Load host control registers, debug registers and MSRs.
1704 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1705 */
1706 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1707 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1708
1709 /* CR0. */
1710 {
1711 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1712 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1713 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1714 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1715 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1716 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1717 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1718 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1719 }
1720
1721 /* CR4. */
1722 {
1723 /* Fixed CR4 bits are not modified. */
1724 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1725 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1726 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1727 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1728 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1729 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1730 if (fHostInLongMode)
1731 uValidHostCr4 |= X86_CR4_PAE;
1732 else
1733 uValidHostCr4 &= ~X86_CR4_PCIDE;
1734 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1735 }
1736
1737 /* CR3 (host value validated while checking host-state during VM-entry). */
1738 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1739
1740 /* DR7. */
1741 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1742
1743 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1744
1745 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1746 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1747 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1748 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1749
1750 /* FS, GS bases are loaded later while we load host segment registers. */
1751
1752 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1753 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1754 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1755 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1756 {
1757 if (fHostInLongMode)
1758 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1759 else
1760 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1761 }
1762
1763 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1764
1765 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1766 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1767 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1768
1769 /* We don't support IA32_BNDCFGS MSR yet. */
1770}
1771
1772
1773/**
1774 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1775 *
1776 * @param pVCpu The cross context virtual CPU structure.
1777 */
1778IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1779{
1780 /*
1781 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1782 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1783 *
1784 * Warning! Be careful to not touch fields that are reserved by VT-x,
1785 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1786 */
1787 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1788 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1789
1790 /* CS, SS, ES, DS, FS, GS. */
1791 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1792 {
1793 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1794 bool const fUnusable = RT_BOOL(HostSel == 0);
1795 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1796
1797 /* Selector. */
1798 pSelReg->Sel = HostSel;
1799 pSelReg->ValidSel = HostSel;
1800 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1801
1802 /* Limit. */
1803 pSelReg->u32Limit = 0xffffffff;
1804
1805 /* Base. */
1806 pSelReg->u64Base = 0;
1807
1808 /* Attributes. */
1809 if (iSegReg == X86_SREG_CS)
1810 {
1811 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1812 pSelReg->Attr.n.u1DescType = 1;
1813 pSelReg->Attr.n.u2Dpl = 0;
1814 pSelReg->Attr.n.u1Present = 1;
1815 pSelReg->Attr.n.u1Long = fHostInLongMode;
1816 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1817 pSelReg->Attr.n.u1Granularity = 1;
1818 Assert(!pSelReg->Attr.n.u1Unusable);
1819 Assert(!fUnusable);
1820 }
1821 else
1822 {
1823 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1824 pSelReg->Attr.n.u1DescType = 1;
1825 pSelReg->Attr.n.u2Dpl = 0;
1826 pSelReg->Attr.n.u1Present = 1;
1827 pSelReg->Attr.n.u1DefBig = 1;
1828 pSelReg->Attr.n.u1Granularity = 1;
1829 pSelReg->Attr.n.u1Unusable = fUnusable;
1830 }
1831 }
1832
1833 /* FS base. */
1834 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1835 || fHostInLongMode)
1836 {
1837 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1838 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1839 }
1840
1841 /* GS base. */
1842 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1843 || fHostInLongMode)
1844 {
1845 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1846 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1847 }
1848
1849 /* TR. */
1850 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1851 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1852 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1853 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1854 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1855 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1856 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1858 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1859 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1860 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1861 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1862 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1863
1864 /* LDTR (Warning! do not touch the base and limits here). */
1865 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1866 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1867 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1868 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1869
1870 /* GDTR. */
1871 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1872 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1873 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1874
1875 /* IDTR.*/
1876 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1877 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1878 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1879}
1880
1881
1882/**
1883 * Checks host PDPTes as part of VM-exit.
1884 *
1885 * @param pVCpu The cross context virtual CPU structure.
1886 * @param uExitReason The VM-exit reason (for logging purposes).
1887 */
1888IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1889{
1890 /*
1891 * Check host PDPTEs.
1892 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1893 */
1894 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1895 const char *const pszFailure = "VMX-abort";
1896 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1897
1898 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1899 && !fHostInLongMode)
1900 {
1901 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1902 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1903 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1904 if (RT_SUCCESS(rc))
1905 {
1906 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1907 {
1908 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1909 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1910 { /* likely */ }
1911 else
1912 {
1913 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1914 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1915 }
1916 }
1917 }
1918 else
1919 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1920 }
1921
1922 NOREF(pszFailure);
1923 NOREF(uExitReason);
1924 return VINF_SUCCESS;
1925}
1926
1927
1928/**
1929 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1930 *
1931 * @returns VBox status code.
1932 * @param pVCpu The cross context virtual CPU structure.
1933 * @param pszInstr The VMX instruction name (for logging purposes).
1934 */
1935IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1936{
1937 /*
1938 * Load host MSRs.
1939 * See Intel spec. 27.6 "Loading MSRs".
1940 */
1941 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1942 const char *const pszFailure = "VMX-abort";
1943
1944 /*
1945 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1946 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1947 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1948 */
1949 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1950 if (!cMsrs)
1951 return VINF_SUCCESS;
1952
1953 /*
1954 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1955 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1956 * implementation causes a VMX-abort followed by a triple-fault.
1957 */
1958 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1959 if (fIsMsrCountValid)
1960 { /* likely */ }
1961 else
1962 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1963
1964 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1965 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1966 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1967 if (RT_SUCCESS(rc))
1968 {
1969 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1970 Assert(pMsr);
1971 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1972 {
1973 if ( !pMsr->u32Reserved
1974 && pMsr->u32Msr != MSR_K8_FS_BASE
1975 && pMsr->u32Msr != MSR_K8_GS_BASE
1976 && pMsr->u32Msr != MSR_K6_EFER
1977 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1978 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1979 {
1980 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1981 if (rcStrict == VINF_SUCCESS)
1982 continue;
1983
1984 /*
1985 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1986 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1987 * recording the MSR index in the auxiliary info. field and indicated further by our
1988 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1989 * if possible, or come up with a better, generic solution.
1990 */
1991 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1992 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1993 ? kVmxVDiag_Vmexit_MsrLoadRing3
1994 : kVmxVDiag_Vmexit_MsrLoad;
1995 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1996 }
1997 else
1998 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1999 }
2000 }
2001 else
2002 {
2003 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2004 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2005 }
2006
2007 NOREF(uExitReason);
2008 NOREF(pszFailure);
2009 return VINF_SUCCESS;
2010}
2011
2012
2013/**
2014 * Loads the host state as part of VM-exit.
2015 *
2016 * @returns Strict VBox status code.
2017 * @param pVCpu The cross context virtual CPU structure.
2018 * @param uExitReason The VM-exit reason (for logging purposes).
2019 */
2020IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2021{
2022 /*
2023 * Load host state.
2024 * See Intel spec. 27.5 "Loading Host State".
2025 */
2026 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2027 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2028
2029 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2030 if ( CPUMIsGuestInLongMode(pVCpu)
2031 && !fHostInLongMode)
2032 {
2033 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2034 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2035 }
2036
2037 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2038 iemVmxVmexitLoadHostSegRegs(pVCpu);
2039
2040 /*
2041 * Load host RIP, RSP and RFLAGS.
2042 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2043 */
2044 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2045 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2046 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2047
2048 /* Clear address range monitoring. */
2049 EMMonitorWaitClear(pVCpu);
2050
2051 /* Perform the VMX transition (PGM updates). */
2052 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2053 if (rcStrict == VINF_SUCCESS)
2054 {
2055 /* Check host PDPTEs (only when we've fully switched page tables_. */
2056 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2057 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2058 if (RT_FAILURE(rc))
2059 {
2060 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2061 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2062 }
2063 }
2064 else if (RT_SUCCESS(rcStrict))
2065 {
2066 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2067 uExitReason));
2068 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2069 }
2070 else
2071 {
2072 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2073 return VBOXSTRICTRC_VAL(rcStrict);
2074 }
2075
2076 Assert(rcStrict == VINF_SUCCESS);
2077
2078 /* Load MSRs from the VM-exit auto-load MSR area. */
2079 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2080 if (RT_FAILURE(rc))
2081 {
2082 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2083 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2084 }
2085 return VINF_SUCCESS;
2086}
2087
2088
2089/**
2090 * Gets VM-exit instruction information along with any displacement for an
2091 * instruction VM-exit.
2092 *
2093 * @returns The VM-exit instruction information.
2094 * @param pVCpu The cross context virtual CPU structure.
2095 * @param uExitReason The VM-exit reason.
2096 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2097 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2098 * NULL.
2099 */
2100IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2101{
2102 RTGCPTR GCPtrDisp;
2103 VMXEXITINSTRINFO ExitInstrInfo;
2104 ExitInstrInfo.u = 0;
2105
2106 /*
2107 * Get and parse the ModR/M byte from our decoded opcodes.
2108 */
2109 uint8_t bRm;
2110 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2111 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2112 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2113 {
2114 /*
2115 * ModR/M indicates register addressing.
2116 *
2117 * The primary/secondary register operands are reported in the iReg1 or iReg2
2118 * fields depending on whether it is a read/write form.
2119 */
2120 uint8_t idxReg1;
2121 uint8_t idxReg2;
2122 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2123 {
2124 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2125 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2126 }
2127 else
2128 {
2129 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2130 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2131 }
2132 ExitInstrInfo.All.u2Scaling = 0;
2133 ExitInstrInfo.All.iReg1 = idxReg1;
2134 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2135 ExitInstrInfo.All.fIsRegOperand = 1;
2136 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2137 ExitInstrInfo.All.iSegReg = 0;
2138 ExitInstrInfo.All.iIdxReg = 0;
2139 ExitInstrInfo.All.fIdxRegInvalid = 1;
2140 ExitInstrInfo.All.iBaseReg = 0;
2141 ExitInstrInfo.All.fBaseRegInvalid = 1;
2142 ExitInstrInfo.All.iReg2 = idxReg2;
2143
2144 /* Displacement not applicable for register addressing. */
2145 GCPtrDisp = 0;
2146 }
2147 else
2148 {
2149 /*
2150 * ModR/M indicates memory addressing.
2151 */
2152 uint8_t uScale = 0;
2153 bool fBaseRegValid = false;
2154 bool fIdxRegValid = false;
2155 uint8_t iBaseReg = 0;
2156 uint8_t iIdxReg = 0;
2157 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2158 {
2159 /*
2160 * Parse the ModR/M, displacement for 16-bit addressing mode.
2161 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2162 */
2163 uint16_t u16Disp = 0;
2164 uint8_t const offDisp = offModRm + sizeof(bRm);
2165 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2166 {
2167 /* Displacement without any registers. */
2168 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2169 }
2170 else
2171 {
2172 /* Register (index and base). */
2173 switch (bRm & X86_MODRM_RM_MASK)
2174 {
2175 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2176 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2177 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2178 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2179 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2180 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2181 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2182 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2183 }
2184
2185 /* Register + displacement. */
2186 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2187 {
2188 case 0: break;
2189 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2190 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2191 default:
2192 {
2193 /* Register addressing, handled at the beginning. */
2194 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2195 break;
2196 }
2197 }
2198 }
2199
2200 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2201 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2202 }
2203 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2204 {
2205 /*
2206 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2207 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2208 */
2209 uint32_t u32Disp = 0;
2210 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2211 {
2212 /* Displacement without any registers. */
2213 uint8_t const offDisp = offModRm + sizeof(bRm);
2214 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2215 }
2216 else
2217 {
2218 /* Register (and perhaps scale, index and base). */
2219 uint8_t offDisp = offModRm + sizeof(bRm);
2220 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2221 if (iBaseReg == 4)
2222 {
2223 /* An SIB byte follows the ModR/M byte, parse it. */
2224 uint8_t bSib;
2225 uint8_t const offSib = offModRm + sizeof(bRm);
2226 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2227
2228 /* A displacement may follow SIB, update its offset. */
2229 offDisp += sizeof(bSib);
2230
2231 /* Get the scale. */
2232 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2233
2234 /* Get the index register. */
2235 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2236 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2237
2238 /* Get the base register. */
2239 iBaseReg = bSib & X86_SIB_BASE_MASK;
2240 fBaseRegValid = true;
2241 if (iBaseReg == 5)
2242 {
2243 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2244 {
2245 /* Mod is 0 implies a 32-bit displacement with no base. */
2246 fBaseRegValid = false;
2247 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2248 }
2249 else
2250 {
2251 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2252 iBaseReg = X86_GREG_xBP;
2253 }
2254 }
2255 }
2256
2257 /* Register + displacement. */
2258 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2259 {
2260 case 0: /* Handled above */ break;
2261 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2262 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2263 default:
2264 {
2265 /* Register addressing, handled at the beginning. */
2266 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2267 break;
2268 }
2269 }
2270 }
2271
2272 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2273 }
2274 else
2275 {
2276 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2277
2278 /*
2279 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2280 * See Intel instruction spec. 2.2 "IA-32e Mode".
2281 */
2282 uint64_t u64Disp = 0;
2283 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2284 if (fRipRelativeAddr)
2285 {
2286 /*
2287 * RIP-relative addressing mode.
2288 *
2289 * The displacement is 32-bit signed implying an offset range of +/-2G.
2290 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2291 */
2292 uint8_t const offDisp = offModRm + sizeof(bRm);
2293 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2294 }
2295 else
2296 {
2297 uint8_t offDisp = offModRm + sizeof(bRm);
2298
2299 /*
2300 * Register (and perhaps scale, index and base).
2301 *
2302 * REX.B extends the most-significant bit of the base register. However, REX.B
2303 * is ignored while determining whether an SIB follows the opcode. Hence, we
2304 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2305 *
2306 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2307 */
2308 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2309 if (iBaseReg == 4)
2310 {
2311 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2312 uint8_t bSib;
2313 uint8_t const offSib = offModRm + sizeof(bRm);
2314 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2315
2316 /* Displacement may follow SIB, update its offset. */
2317 offDisp += sizeof(bSib);
2318
2319 /* Get the scale. */
2320 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2321
2322 /* Get the index. */
2323 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2324 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2325
2326 /* Get the base. */
2327 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2328 fBaseRegValid = true;
2329 if (iBaseReg == 5)
2330 {
2331 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2332 {
2333 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2334 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2335 }
2336 else
2337 {
2338 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2339 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2340 }
2341 }
2342 }
2343 iBaseReg |= pVCpu->iem.s.uRexB;
2344
2345 /* Register + displacement. */
2346 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2347 {
2348 case 0: /* Handled above */ break;
2349 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2350 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2351 default:
2352 {
2353 /* Register addressing, handled at the beginning. */
2354 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2355 break;
2356 }
2357 }
2358 }
2359
2360 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2361 }
2362
2363 /*
2364 * The primary or secondary register operand is reported in iReg2 depending
2365 * on whether the primary operand is in read/write form.
2366 */
2367 uint8_t idxReg2;
2368 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2369 {
2370 idxReg2 = bRm & X86_MODRM_RM_MASK;
2371 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2372 idxReg2 |= pVCpu->iem.s.uRexB;
2373 }
2374 else
2375 {
2376 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2377 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2378 idxReg2 |= pVCpu->iem.s.uRexReg;
2379 }
2380 ExitInstrInfo.All.u2Scaling = uScale;
2381 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2382 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2383 ExitInstrInfo.All.fIsRegOperand = 0;
2384 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2385 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2386 ExitInstrInfo.All.iIdxReg = iIdxReg;
2387 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2388 ExitInstrInfo.All.iBaseReg = iBaseReg;
2389 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2390 ExitInstrInfo.All.iReg2 = idxReg2;
2391 }
2392
2393 /*
2394 * Handle exceptions to the norm for certain instructions.
2395 * (e.g. some instructions convey an instruction identity in place of iReg2).
2396 */
2397 switch (uExitReason)
2398 {
2399 case VMX_EXIT_GDTR_IDTR_ACCESS:
2400 {
2401 Assert(VMXINSTRID_IS_VALID(uInstrId));
2402 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2403 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2404 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2405 break;
2406 }
2407
2408 case VMX_EXIT_LDTR_TR_ACCESS:
2409 {
2410 Assert(VMXINSTRID_IS_VALID(uInstrId));
2411 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2412 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2413 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2414 break;
2415 }
2416
2417 case VMX_EXIT_RDRAND:
2418 case VMX_EXIT_RDSEED:
2419 {
2420 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2421 break;
2422 }
2423 }
2424
2425 /* Update displacement and return the constructed VM-exit instruction information field. */
2426 if (pGCPtrDisp)
2427 *pGCPtrDisp = GCPtrDisp;
2428
2429 return ExitInstrInfo.u;
2430}
2431
2432
2433/**
2434 * VMX VM-exit handler.
2435 *
2436 * @returns Strict VBox status code.
2437 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2438 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2439 * triple-fault.
2440 *
2441 * @param pVCpu The cross context virtual CPU structure.
2442 * @param uExitReason The VM-exit reason.
2443 * @param u64ExitQual The Exit qualification.
2444 */
2445IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2446{
2447# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2448 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2449 return VINF_EM_RAW_EMULATE_INSTR;
2450# else
2451 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2452 Assert(pVmcs);
2453
2454 /*
2455 * Import all the guest-CPU state.
2456 *
2457 * HM on returning to guest execution would have to reset up a whole lot of state
2458 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2459 * the state and flag reloading the entire state on re-entry. So import the entire
2460 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2461 */
2462 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2463
2464 /*
2465 * Ensure VM-entry interruption information valid bit is cleared.
2466 *
2467 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2468 * by invalid-guest state or machine-check exceptions) also clear this bit.
2469 *
2470 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2471 */
2472 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2473 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2474
2475 /*
2476 * Update the VM-exit reason and Exit qualification.
2477 * Other VMCS read-only data fields are expected to be updated by the caller already.
2478 */
2479 pVmcs->u32RoExitReason = uExitReason;
2480 pVmcs->u64RoExitQual.u = u64ExitQual;
2481
2482 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2483 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2484
2485 /*
2486 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2487 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2488 */
2489 {
2490 uint8_t uVector;
2491 uint32_t fFlags;
2492 uint32_t uErrCode;
2493 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2494 if (fInEventDelivery)
2495 {
2496 /*
2497 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2498 * caused by a triple-fault or the original event results in a double-fault that
2499 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2500 * original event information into the IDT-vectoring information fields.
2501 *
2502 * See Intel spec. 27.2.4 Information for VM Exits During Event Delivery
2503 */
2504 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2505 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2506 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2507 {
2508 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2509 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2510 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2511 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2512 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2513 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2514 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2515 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2516 }
2517 }
2518 }
2519
2520 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2521 Assert(pVmcs->u64RoIoRcx.u == 0);
2522 Assert(pVmcs->u64RoIoRsi.u == 0);
2523 Assert(pVmcs->u64RoIoRdi.u == 0);
2524 Assert(pVmcs->u64RoIoRip.u == 0);
2525
2526 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2527 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2528 {
2529 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2530 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2531 }
2532
2533 /* Paranoia. */
2534 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2535
2536 /*
2537 * Save the guest state back into the VMCS.
2538 * We only need to save the state when the VM-entry was successful.
2539 */
2540 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2541 if (!fVmentryFailed)
2542 {
2543 /*
2544 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2545 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2546 *
2547 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2548 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2549 * as guest-CPU state would not been modified. Hence for now, we do this only when
2550 * the VM-entry succeeded.
2551 */
2552 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2553 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2554 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2555 {
2556 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2557 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2558 else
2559 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2560 }
2561
2562 /*
2563 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2564 * occurs in enclave mode/SMM which we don't support yet.
2565 *
2566 * If we ever add support for it, we can pass just the lower bits to the functions
2567 * below, till then an assert should suffice.
2568 */
2569 Assert(!RT_HI_U16(uExitReason));
2570
2571 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2572 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2573 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2574 if (RT_SUCCESS(rc))
2575 { /* likely */ }
2576 else
2577 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2578
2579 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2580 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2581 }
2582 else
2583 {
2584 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2585 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2586 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2587 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2588 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2589 }
2590
2591 /*
2592 * Clear any pending VMX nested-guest force-flags.
2593 * These force-flags have no effect on guest execution and will
2594 * be re-evaluated and setup on the next nested-guest VM-entry.
2595 */
2596 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2597 | VMCPU_FF_VMX_MTF
2598 | VMCPU_FF_VMX_APIC_WRITE
2599 | VMCPU_FF_VMX_INT_WINDOW
2600 | VMCPU_FF_VMX_NMI_WINDOW);
2601
2602 /* Restore the host (outer guest) state. */
2603 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2604 if (RT_SUCCESS(rcStrict))
2605 {
2606 Assert(rcStrict == VINF_SUCCESS);
2607 rcStrict = VINF_VMX_VMEXIT;
2608 }
2609 else
2610 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2611
2612 /* We're no longer in nested-guest execution mode. */
2613 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2614
2615 /* Notify HM that the current VMCS fields have been modified. */
2616 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2617
2618 /* Notify HM that we've completed the VM-exit. */
2619 HMNotifyVmxNstGstVmexit(pVCpu);
2620
2621# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2622 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2623 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2624 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2625 if (rcSched != VINF_SUCCESS)
2626 iemSetPassUpStatus(pVCpu, rcSched);
2627# endif
2628 return rcStrict;
2629# endif
2630}
2631
2632
2633/**
2634 * VMX VM-exit handler for VM-exits due to instruction execution.
2635 *
2636 * This is intended for instructions where the caller provides all the relevant
2637 * VM-exit information.
2638 *
2639 * @returns Strict VBox status code.
2640 * @param pVCpu The cross context virtual CPU structure.
2641 * @param pExitInfo Pointer to the VM-exit information.
2642 */
2643IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2644{
2645 /*
2646 * For instructions where any of the following fields are not applicable:
2647 * - Exit qualification must be cleared.
2648 * - VM-exit instruction info. is undefined.
2649 * - Guest-linear address is undefined.
2650 * - Guest-physical address is undefined.
2651 *
2652 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2653 * instruction execution. For VM-exits that are not due to instruction execution this
2654 * field is undefined.
2655 *
2656 * In our implementation in IEM, all undefined fields are generally cleared. However,
2657 * if the caller supplies information (from say the physical CPU directly) it is
2658 * then possible that the undefined fields are not cleared.
2659 *
2660 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2661 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2662 */
2663 Assert(pExitInfo);
2664 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2665 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2666 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2667
2668 /* Update all the relevant fields from the VM-exit instruction information struct. */
2669 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2670 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2671 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2672 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2673
2674 /* Perform the VM-exit. */
2675 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2676}
2677
2678
2679/**
2680 * VMX VM-exit handler for VM-exits due to instruction execution.
2681 *
2682 * This is intended for instructions that only provide the VM-exit instruction
2683 * length.
2684 *
2685 * @param pVCpu The cross context virtual CPU structure.
2686 * @param uExitReason The VM-exit reason.
2687 * @param cbInstr The instruction length in bytes.
2688 */
2689IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2690{
2691 VMXVEXITINFO ExitInfo;
2692 RT_ZERO(ExitInfo);
2693 ExitInfo.uReason = uExitReason;
2694 ExitInfo.cbInstr = cbInstr;
2695
2696#ifdef VBOX_STRICT
2697 /*
2698 * To prevent us from shooting ourselves in the foot.
2699 * The follow instructions should convey more than just the instruction length.
2700 */
2701 switch (uExitReason)
2702 {
2703 case VMX_EXIT_INVEPT:
2704 case VMX_EXIT_INVPCID:
2705 case VMX_EXIT_INVVPID:
2706 case VMX_EXIT_LDTR_TR_ACCESS:
2707 case VMX_EXIT_GDTR_IDTR_ACCESS:
2708 case VMX_EXIT_VMCLEAR:
2709 case VMX_EXIT_VMPTRLD:
2710 case VMX_EXIT_VMPTRST:
2711 case VMX_EXIT_VMREAD:
2712 case VMX_EXIT_VMWRITE:
2713 case VMX_EXIT_VMXON:
2714 case VMX_EXIT_XRSTORS:
2715 case VMX_EXIT_XSAVES:
2716 case VMX_EXIT_RDRAND:
2717 case VMX_EXIT_RDSEED:
2718 case VMX_EXIT_IO_INSTR:
2719 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2720 break;
2721 }
2722#endif
2723
2724 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2725}
2726
2727
2728/**
2729 * VMX VM-exit handler for VM-exits due to instruction execution.
2730 *
2731 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2732 * instruction information and Exit qualification fields.
2733 *
2734 * @param pVCpu The cross context virtual CPU structure.
2735 * @param uExitReason The VM-exit reason.
2736 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2737 * @param cbInstr The instruction length in bytes.
2738 *
2739 * @remarks Do not use this for INS/OUTS instruction.
2740 */
2741IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2742{
2743 VMXVEXITINFO ExitInfo;
2744 RT_ZERO(ExitInfo);
2745 ExitInfo.uReason = uExitReason;
2746 ExitInfo.cbInstr = cbInstr;
2747
2748 /*
2749 * Update the Exit qualification field with displacement bytes.
2750 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2751 */
2752 switch (uExitReason)
2753 {
2754 case VMX_EXIT_INVEPT:
2755 case VMX_EXIT_INVPCID:
2756 case VMX_EXIT_INVVPID:
2757 case VMX_EXIT_LDTR_TR_ACCESS:
2758 case VMX_EXIT_GDTR_IDTR_ACCESS:
2759 case VMX_EXIT_VMCLEAR:
2760 case VMX_EXIT_VMPTRLD:
2761 case VMX_EXIT_VMPTRST:
2762 case VMX_EXIT_VMREAD:
2763 case VMX_EXIT_VMWRITE:
2764 case VMX_EXIT_VMXON:
2765 case VMX_EXIT_XRSTORS:
2766 case VMX_EXIT_XSAVES:
2767 case VMX_EXIT_RDRAND:
2768 case VMX_EXIT_RDSEED:
2769 {
2770 /* Construct the VM-exit instruction information. */
2771 RTGCPTR GCPtrDisp;
2772 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2773
2774 /* Update the VM-exit instruction information. */
2775 ExitInfo.InstrInfo.u = uInstrInfo;
2776
2777 /* Update the Exit qualification. */
2778 ExitInfo.u64Qual = GCPtrDisp;
2779 break;
2780 }
2781
2782 default:
2783 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2784 break;
2785 }
2786
2787 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2788}
2789
2790
2791/**
2792 * VMX VM-exit handler for VM-exits due to INVLPG.
2793 *
2794 * @returns Strict VBox status code.
2795 * @param pVCpu The cross context virtual CPU structure.
2796 * @param GCPtrPage The guest-linear address of the page being invalidated.
2797 * @param cbInstr The instruction length in bytes.
2798 */
2799IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2800{
2801 VMXVEXITINFO ExitInfo;
2802 RT_ZERO(ExitInfo);
2803 ExitInfo.uReason = VMX_EXIT_INVLPG;
2804 ExitInfo.cbInstr = cbInstr;
2805 ExitInfo.u64Qual = GCPtrPage;
2806 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2807
2808 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2809}
2810
2811
2812/**
2813 * VMX VM-exit handler for VM-exits due to LMSW.
2814 *
2815 * @returns Strict VBox status code.
2816 * @param pVCpu The cross context virtual CPU structure.
2817 * @param uGuestCr0 The current guest CR0.
2818 * @param pu16NewMsw The machine-status word specified in LMSW's source
2819 * operand. This will be updated depending on the VMX
2820 * guest/host CR0 mask if LMSW is not intercepted.
2821 * @param GCPtrEffDst The guest-linear address of the source operand in case
2822 * of a memory operand. For register operand, pass
2823 * NIL_RTGCPTR.
2824 * @param cbInstr The instruction length in bytes.
2825 */
2826IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2827 uint8_t cbInstr)
2828{
2829 Assert(pu16NewMsw);
2830
2831 uint16_t const uNewMsw = *pu16NewMsw;
2832 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2833 {
2834 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2835
2836 VMXVEXITINFO ExitInfo;
2837 RT_ZERO(ExitInfo);
2838 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2839 ExitInfo.cbInstr = cbInstr;
2840
2841 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2842 if (fMemOperand)
2843 {
2844 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2845 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2846 }
2847
2848 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2849 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2850 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2851 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2852
2853 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2854 }
2855
2856 /*
2857 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2858 * CR0 guest/host mask must be left unmodified.
2859 *
2860 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2861 */
2862 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2863 Assert(pVmcs);
2864 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2865 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2866 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2867
2868 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2869}
2870
2871
2872/**
2873 * VMX VM-exit handler for VM-exits due to CLTS.
2874 *
2875 * @returns Strict VBox status code.
2876 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2877 * VM-exit but must not modify the guest CR0.TS bit.
2878 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2879 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2880 * CR0 fixed bits in VMX operation).
2881 * @param pVCpu The cross context virtual CPU structure.
2882 * @param cbInstr The instruction length in bytes.
2883 */
2884IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2885{
2886 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2887 Assert(pVmcs);
2888
2889 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2890 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2891
2892 /*
2893 * If CR0.TS is owned by the host:
2894 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2895 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2896 * CLTS instruction completes without clearing CR0.TS.
2897 *
2898 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2899 */
2900 if (fGstHostMask & X86_CR0_TS)
2901 {
2902 if (fReadShadow & X86_CR0_TS)
2903 {
2904 Log2(("clts: Guest intercept -> VM-exit\n"));
2905
2906 VMXVEXITINFO ExitInfo;
2907 RT_ZERO(ExitInfo);
2908 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2909 ExitInfo.cbInstr = cbInstr;
2910 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2911 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2912 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2913 }
2914
2915 return VINF_VMX_MODIFIES_BEHAVIOR;
2916 }
2917
2918 /*
2919 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2920 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2921 */
2922 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2923}
2924
2925
2926/**
2927 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2928 * (CR0/CR4 write).
2929 *
2930 * @returns Strict VBox status code.
2931 * @param pVCpu The cross context virtual CPU structure.
2932 * @param iCrReg The control register (either CR0 or CR4).
2933 * @param uGuestCrX The current guest CR0/CR4.
2934 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2935 * VM-exit is caused.
2936 * @param iGReg The general register from which the CR0/CR4 value is being
2937 * loaded.
2938 * @param cbInstr The instruction length in bytes.
2939 */
2940IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2941 uint8_t cbInstr)
2942{
2943 Assert(puNewCrX);
2944 Assert(iCrReg == 0 || iCrReg == 4);
2945 Assert(iGReg < X86_GREG_COUNT);
2946
2947 uint64_t const uNewCrX = *puNewCrX;
2948 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2949 {
2950 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2951
2952 VMXVEXITINFO ExitInfo;
2953 RT_ZERO(ExitInfo);
2954 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2955 ExitInfo.cbInstr = cbInstr;
2956 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2957 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2958 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2959 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2960 }
2961
2962 /*
2963 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2964 * must not be modified the instruction.
2965 *
2966 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2967 */
2968 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2969 Assert(pVmcs);
2970 uint64_t uGuestCrX;
2971 uint64_t fGstHostMask;
2972 if (iCrReg == 0)
2973 {
2974 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2975 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2976 fGstHostMask = pVmcs->u64Cr0Mask.u;
2977 }
2978 else
2979 {
2980 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2981 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2982 fGstHostMask = pVmcs->u64Cr4Mask.u;
2983 }
2984
2985 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2986 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2987}
2988
2989
2990/**
2991 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2992 *
2993 * @returns VBox strict status code.
2994 * @param pVCpu The cross context virtual CPU structure.
2995 * @param iGReg The general register to which the CR3 value is being stored.
2996 * @param cbInstr The instruction length in bytes.
2997 */
2998IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2999{
3000 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3001 Assert(pVmcs);
3002 Assert(iGReg < X86_GREG_COUNT);
3003 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3004
3005 /*
3006 * If the CR3-store exiting control is set, we must cause a VM-exit.
3007 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3008 */
3009 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3010 {
3011 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3012
3013 VMXVEXITINFO ExitInfo;
3014 RT_ZERO(ExitInfo);
3015 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3016 ExitInfo.cbInstr = cbInstr;
3017 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3018 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3019 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3020 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3021 }
3022
3023 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3024}
3025
3026
3027/**
3028 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3029 *
3030 * @returns VBox strict status code.
3031 * @param pVCpu The cross context virtual CPU structure.
3032 * @param uNewCr3 The new CR3 value.
3033 * @param iGReg The general register from which the CR3 value is being
3034 * loaded.
3035 * @param cbInstr The instruction length in bytes.
3036 */
3037IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3038{
3039 Assert(iGReg < X86_GREG_COUNT);
3040
3041 /*
3042 * If the CR3-load exiting control is set and the new CR3 value does not
3043 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3044 *
3045 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3046 */
3047 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3048 {
3049 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3050
3051 VMXVEXITINFO ExitInfo;
3052 RT_ZERO(ExitInfo);
3053 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3054 ExitInfo.cbInstr = cbInstr;
3055 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3056 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3057 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3058 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3059 }
3060
3061 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3062}
3063
3064
3065/**
3066 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3067 *
3068 * @returns VBox strict status code.
3069 * @param pVCpu The cross context virtual CPU structure.
3070 * @param iGReg The general register to which the CR8 value is being stored.
3071 * @param cbInstr The instruction length in bytes.
3072 */
3073IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3074{
3075 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3076 Assert(pVmcs);
3077 Assert(iGReg < X86_GREG_COUNT);
3078
3079 /*
3080 * If the CR8-store exiting control is set, we must cause a VM-exit.
3081 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3082 */
3083 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3084 {
3085 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3086
3087 VMXVEXITINFO ExitInfo;
3088 RT_ZERO(ExitInfo);
3089 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3090 ExitInfo.cbInstr = cbInstr;
3091 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3094 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3095 }
3096
3097 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3098}
3099
3100
3101/**
3102 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3103 *
3104 * @returns VBox strict status code.
3105 * @param pVCpu The cross context virtual CPU structure.
3106 * @param iGReg The general register from which the CR8 value is being
3107 * loaded.
3108 * @param cbInstr The instruction length in bytes.
3109 */
3110IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3111{
3112 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3113 Assert(pVmcs);
3114 Assert(iGReg < X86_GREG_COUNT);
3115
3116 /*
3117 * If the CR8-load exiting control is set, we must cause a VM-exit.
3118 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3119 */
3120 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3121 {
3122 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3123
3124 VMXVEXITINFO ExitInfo;
3125 RT_ZERO(ExitInfo);
3126 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3127 ExitInfo.cbInstr = cbInstr;
3128 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3129 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3130 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3131 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3132 }
3133
3134 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3135}
3136
3137
3138/**
3139 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3140 * GReg,DRx' (DRx read).
3141 *
3142 * @returns VBox strict status code.
3143 * @param pVCpu The cross context virtual CPU structure.
3144 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3145 * VMXINSTRID_MOV_FROM_DRX).
3146 * @param iDrReg The debug register being accessed.
3147 * @param iGReg The general register to/from which the DRx value is being
3148 * store/loaded.
3149 * @param cbInstr The instruction length in bytes.
3150 */
3151IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3152 uint8_t cbInstr)
3153{
3154 Assert(iDrReg <= 7);
3155 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3156 Assert(iGReg < X86_GREG_COUNT);
3157
3158 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3159 Assert(pVmcs);
3160
3161 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3162 {
3163 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3164 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3165 VMXVEXITINFO ExitInfo;
3166 RT_ZERO(ExitInfo);
3167 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3168 ExitInfo.cbInstr = cbInstr;
3169 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3170 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3171 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3172 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3173 }
3174
3175 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3176}
3177
3178
3179/**
3180 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3181 *
3182 * @returns VBox strict status code.
3183 * @param pVCpu The cross context virtual CPU structure.
3184 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3185 * VMXINSTRID_IO_OUT).
3186 * @param u16Port The I/O port being accessed.
3187 * @param fImm Whether the I/O port was encoded using an immediate operand
3188 * or the implicit DX register.
3189 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3190 * @param cbInstr The instruction length in bytes.
3191 */
3192IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3193 uint8_t cbInstr)
3194{
3195 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3196 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3197
3198 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3199 if (fIntercept)
3200 {
3201 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3202 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3203 VMXVEXITINFO ExitInfo;
3204 RT_ZERO(ExitInfo);
3205 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3206 ExitInfo.cbInstr = cbInstr;
3207 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3208 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3209 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3210 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3211 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3212 }
3213
3214 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3215}
3216
3217
3218/**
3219 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3220 *
3221 * @returns VBox strict status code.
3222 * @param pVCpu The cross context virtual CPU structure.
3223 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3224 * VMXINSTRID_IO_OUTS).
3225 * @param u16Port The I/O port being accessed.
3226 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3227 * @param fRep Whether the instruction has a REP prefix or not.
3228 * @param ExitInstrInfo The VM-exit instruction info. field.
3229 * @param cbInstr The instruction length in bytes.
3230 */
3231IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3232 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3233{
3234 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3235 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3236 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3237 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3238 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3239
3240 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3241 if (fIntercept)
3242 {
3243 /*
3244 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3245 */
3246 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3247 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3248 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3249 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3250 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3251
3252 uint32_t uDirection;
3253 uint64_t uGuestLinearAddr;
3254 if (uInstrId == VMXINSTRID_IO_INS)
3255 {
3256 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3257 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3258 }
3259 else
3260 {
3261 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3262 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3263 }
3264
3265 /*
3266 * If the segment is unusable, the guest-linear address in undefined.
3267 * We shall clear it for consistency.
3268 *
3269 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3270 */
3271 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3272 uGuestLinearAddr = 0;
3273
3274 VMXVEXITINFO ExitInfo;
3275 RT_ZERO(ExitInfo);
3276 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3277 ExitInfo.cbInstr = cbInstr;
3278 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3279 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3280 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3281 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3282 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3283 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3284 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3285 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3286 ExitInfo.InstrInfo = ExitInstrInfo;
3287 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3288 }
3289
3290 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3291}
3292
3293
3294/**
3295 * VMX VM-exit handler for VM-exits due to MWAIT.
3296 *
3297 * @returns VBox strict status code.
3298 * @param pVCpu The cross context virtual CPU structure.
3299 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3300 * @param cbInstr The instruction length in bytes.
3301 */
3302IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3303{
3304 VMXVEXITINFO ExitInfo;
3305 RT_ZERO(ExitInfo);
3306 ExitInfo.uReason = VMX_EXIT_MWAIT;
3307 ExitInfo.cbInstr = cbInstr;
3308 ExitInfo.u64Qual = fMonitorHwArmed;
3309 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3310}
3311
3312
3313/**
3314 * VMX VM-exit handler for VM-exits due to PAUSE.
3315 *
3316 * @returns VBox strict status code.
3317 * @param pVCpu The cross context virtual CPU structure.
3318 * @param cbInstr The instruction length in bytes.
3319 */
3320IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3321{
3322 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3323 Assert(pVmcs);
3324
3325 /*
3326 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3327 * "PAUSE-loop exiting" control.
3328 *
3329 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3330 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3331 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3332 * a VM-exit.
3333 *
3334 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3335 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3336 */
3337 bool fIntercept = false;
3338 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3339 fIntercept = true;
3340 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3341 && pVCpu->iem.s.uCpl == 0)
3342 {
3343 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3344
3345 /*
3346 * A previous-PAUSE-tick value of 0 is used to identify the first time
3347 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3348 * consider this to be the first execution of PAUSE in a loop according
3349 * to the Intel.
3350 *
3351 * All subsequent records for the previous-PAUSE-tick we ensure that it
3352 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3353 */
3354 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3355 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3356 uint64_t const uTick = TMCpuTickGet(pVCpu);
3357 uint32_t const uPleGap = pVmcs->u32PleGap;
3358 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3359 if ( *puPrevPauseTick == 0
3360 || uTick - *puPrevPauseTick > uPleGap)
3361 *puFirstPauseLoopTick = uTick;
3362 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3363 fIntercept = true;
3364
3365 *puPrevPauseTick = uTick | 1;
3366 }
3367
3368 if (fIntercept)
3369 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3370
3371 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3372}
3373
3374
3375/**
3376 * VMX VM-exit handler for VM-exits due to task switches.
3377 *
3378 * @returns VBox strict status code.
3379 * @param pVCpu The cross context virtual CPU structure.
3380 * @param enmTaskSwitch The cause of the task switch.
3381 * @param SelNewTss The selector of the new TSS.
3382 * @param cbInstr The instruction length in bytes.
3383 */
3384IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3385{
3386 /*
3387 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3388 *
3389 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3390 * instruction or delivery of the exception generated by one of these instructions
3391 * lead to a task switch through a task gate in the IDT, we need to provide the
3392 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3393 * leaves the VM-exit instruction length field undefined.
3394 *
3395 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3396 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3397 */
3398 Assert(cbInstr <= 15);
3399
3400 uint8_t uType;
3401 switch (enmTaskSwitch)
3402 {
3403 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3404 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3405 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3406 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3407 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3408 }
3409
3410 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3411 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3412 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3413 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3414}
3415
3416
3417/**
3418 * VMX VM-exit handler for VM-exits due to task switches.
3419 *
3420 * This is intended for task switches where the caller provides all the relevant
3421 * VM-exit information.
3422 *
3423 * @returns VBox strict status code.
3424 * @param pVCpu The cross context virtual CPU structure.
3425 * @param pExitInfo Pointer to the VM-exit information.
3426 * @param pExitEventInfo Pointer to the VM-exit event information.
3427 */
3428IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3429 PCVMXVEXITEVENTINFO pExitEventInfo)
3430{
3431 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3432 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3433 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3434 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3435 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3436}
3437
3438
3439/**
3440 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3441 *
3442 * @returns VBox strict status code.
3443 * @param pVCpu The cross context virtual CPU structure.
3444 */
3445IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3446{
3447 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3448 Assert(pVmcs);
3449
3450 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3451 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3452 {
3453 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3454 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3455
3456 /*
3457 * Calculate the current VMX-preemption timer value.
3458 * Only if the value has reached zero, we cause the VM-exit.
3459 */
3460 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3461 if (!uPreemptTimer)
3462 {
3463 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3464 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3465 pVmcs->u32PreemptTimer = 0;
3466
3467 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3468 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3469 }
3470 }
3471
3472 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3473}
3474
3475
3476/**
3477 * VMX VM-exit handler for VM-exits due to external interrupts.
3478 *
3479 * @returns VBox strict status code.
3480 * @param pVCpu The cross context virtual CPU structure.
3481 * @param uVector The external interrupt vector (pass 0 if the interrupt
3482 * is still pending since we typically won't know the
3483 * vector).
3484 * @param fIntPending Whether the external interrupt is pending or
3485 * acknowledged in the interrupt controller.
3486 */
3487IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3488{
3489 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3490 Assert(pVmcs);
3491 Assert(fIntPending || uVector == 0);
3492
3493 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3494 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3495 * functions require prior checking of a blanket intercept and which don't.
3496 * It is better for the caller to check a blanket intercept performance wise
3497 * than making a function call. Leaving this as a todo because it is more
3498 * a performance issue. */
3499
3500 /* The VM-exit is subject to "External interrupt exiting" being set. */
3501 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3502 {
3503 if (fIntPending)
3504 {
3505 /*
3506 * If the interrupt is pending and we don't need to acknowledge the
3507 * interrupt on VM-exit, cause the VM-exit immediately.
3508 *
3509 * See Intel spec 25.2 "Other Causes Of VM Exits".
3510 */
3511 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3512 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3513
3514 /*
3515 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3516 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3517 * acknowledged that the interrupt has been consumed.
3518 */
3519 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3520 }
3521
3522 /*
3523 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3524 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3525 * all set, we cause the VM-exit now. We need to record the external interrupt that
3526 * just occurred in the VM-exit interruption information field.
3527 *
3528 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3529 */
3530 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3531 {
3532 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3533 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3534 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3535 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3536 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3537 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3538 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3539 }
3540 }
3541
3542 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3543}
3544
3545
3546/**
3547 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3548 * an event.
3549 *
3550 * @returns VBox strict status code.
3551 * @param pVCpu The cross context virtual CPU structure.
3552 */
3553IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3554{
3555 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3556 Assert(pVmcs);
3557
3558 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3559 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3560 {
3561 /*
3562 * The NMI-unblocking due to IRET field need not be set for double faults.
3563 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3564 */
3565 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3566 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3567 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3568 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3569 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3570 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3571 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3572 }
3573
3574 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3575}
3576
3577
3578/**
3579 * VMX VM-exit handler for VM-exit due to delivery of an events.
3580 *
3581 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3582 * all the relevant VM-exit information.
3583 *
3584 * @returns VBox strict status code.
3585 * @param pVCpu The cross context virtual CPU structure.
3586 * @param pExitInfo Pointer to the VM-exit information.
3587 * @param pExitEventInfo Pointer to the VM-exit event information.
3588 */
3589IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3590{
3591 Assert(pExitInfo);
3592 Assert(pExitEventInfo);
3593 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3594
3595 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3596 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3597 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3598 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3599 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3600 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3601}
3602
3603
3604/**
3605 * VMX VM-exit handler for VM-exits due to delivery of an event.
3606 *
3607 * @returns VBox strict status code.
3608 * @param pVCpu The cross context virtual CPU structure.
3609 * @param uVector The interrupt / exception vector.
3610 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3611 * @param uErrCode The error code associated with the event.
3612 * @param uCr2 The CR2 value in case of a \#PF exception.
3613 * @param cbInstr The instruction length in bytes.
3614 */
3615IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3616 uint8_t cbInstr)
3617{
3618 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3619 Assert(pVmcs);
3620
3621 /*
3622 * If the event is being injected as part of VM-entry, it is -not- subject to event
3623 * intercepts in the nested-guest. However, secondary exceptions that occur during
3624 * injection of any event -are- subject to event interception.
3625 *
3626 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3627 */
3628 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3629 {
3630 /*
3631 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3632 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3633 *
3634 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3635 */
3636 if ( uVector == X86_XCPT_NMI
3637 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3638 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3639 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3640 else
3641 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3642
3643 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3644 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3645 }
3646
3647 /*
3648 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3649 * If not, the caller will continue delivery of the external interrupt as it would
3650 * normally. The interrupt is no longer pending in the interrupt controller at this
3651 * point.
3652 */
3653 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3654 {
3655 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3656 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3657 }
3658
3659 /*
3660 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3661 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3662 * interrupts.
3663 */
3664 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3665 bool fIntercept;
3666 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3667 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3668 {
3669 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3670 }
3671 else
3672 {
3673 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3674 fIntercept = false;
3675 }
3676
3677 /*
3678 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3679 * relevant VM-exit information and cause the VM-exit.
3680 */
3681 if (fIntercept)
3682 {
3683 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3684
3685 /* Construct the rest of the event related information fields and cause the VM-exit. */
3686 uint64_t u64ExitQual;
3687 if (uVector == X86_XCPT_PF)
3688 {
3689 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3690 u64ExitQual = uCr2;
3691 }
3692 else if (uVector == X86_XCPT_DB)
3693 {
3694 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3695 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3696 }
3697 else
3698 u64ExitQual = 0;
3699
3700 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3701 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3702 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3703 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3704 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3705 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3706 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3707 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3708 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3709 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3710
3711 /*
3712 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3713 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3714 * length.
3715 */
3716 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3717 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3718 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3719 else
3720 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3721
3722 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3723 }
3724
3725 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3726}
3727
3728
3729/**
3730 * VMX VM-exit handler for APIC accesses.
3731 *
3732 * @param pVCpu The cross context virtual CPU structure.
3733 * @param offAccess The offset of the register being accessed.
3734 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3735 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3736 */
3737IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3738{
3739 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3740
3741 VMXAPICACCESS enmAccess;
3742 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3743 if (fInEventDelivery)
3744 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3745 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3746 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3747 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3748 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3749 else
3750 enmAccess = VMXAPICACCESS_LINEAR_READ;
3751
3752 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3753 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3754 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3755}
3756
3757
3758/**
3759 * VMX VM-exit handler for APIC accesses.
3760 *
3761 * This is intended for APIC accesses where the caller provides all the
3762 * relevant VM-exit information.
3763 *
3764 * @returns VBox strict status code.
3765 * @param pVCpu The cross context virtual CPU structure.
3766 * @param pExitInfo Pointer to the VM-exit information.
3767 * @param pExitEventInfo Pointer to the VM-exit event information.
3768 */
3769IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3770 PCVMXVEXITEVENTINFO pExitEventInfo)
3771{
3772 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3773 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3774 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3775 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3776 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3777 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3778 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3779 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3780 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3781}
3782
3783
3784/**
3785 * VMX VM-exit handler for APIC-write VM-exits.
3786 *
3787 * @param pVCpu The cross context virtual CPU structure.
3788 * @param offApic The write to the virtual-APIC page offset that caused this
3789 * VM-exit.
3790 */
3791IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3792{
3793 Assert(offApic < XAPIC_OFF_END + 4);
3794 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3795 offApic &= UINT16_C(0xfff);
3796 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3797}
3798
3799
3800/**
3801 * Sets virtual-APIC write emulation as pending.
3802 *
3803 * @param pVCpu The cross context virtual CPU structure.
3804 * @param offApic The offset in the virtual-APIC page that was written.
3805 */
3806DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3807{
3808 Assert(offApic < XAPIC_OFF_END + 4);
3809
3810 /*
3811 * Record the currently updated APIC offset, as we need this later for figuring
3812 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3813 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3814 */
3815 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3816
3817 /*
3818 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3819 * virtualization or APIC-write emulation).
3820 */
3821 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3822 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3823}
3824
3825
3826/**
3827 * Clears any pending virtual-APIC write emulation.
3828 *
3829 * @returns The virtual-APIC offset that was written before clearing it.
3830 * @param pVCpu The cross context virtual CPU structure.
3831 */
3832DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3833{
3834 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3835 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3836 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3837 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3838 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3839 return offVirtApicWrite;
3840}
3841
3842
3843/**
3844 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3845 *
3846 * @returns The register from the virtual-APIC page.
3847 * @param pVCpu The cross context virtual CPU structure.
3848 * @param offReg The offset of the register being read.
3849 */
3850IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3851{
3852 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3853 Assert(pVmcs);
3854 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3855
3856 uint32_t uReg;
3857 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3858 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3859 if (RT_SUCCESS(rc))
3860 { /* likely */ }
3861 else
3862 {
3863 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3864 GCPhysVirtApic));
3865 uReg = 0;
3866 }
3867 return uReg;
3868}
3869
3870
3871/**
3872 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3873 *
3874 * @returns The register from the virtual-APIC page.
3875 * @param pVCpu The cross context virtual CPU structure.
3876 * @param offReg The offset of the register being read.
3877 */
3878IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3879{
3880 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3881 Assert(pVmcs);
3882 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3883
3884 uint64_t uReg;
3885 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3886 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3887 if (RT_SUCCESS(rc))
3888 { /* likely */ }
3889 else
3890 {
3891 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3892 GCPhysVirtApic));
3893 uReg = 0;
3894 }
3895 return uReg;
3896}
3897
3898
3899/**
3900 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3901 *
3902 * @param pVCpu The cross context virtual CPU structure.
3903 * @param offReg The offset of the register being written.
3904 * @param uReg The register value to write.
3905 */
3906IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3907{
3908 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3909 Assert(pVmcs);
3910 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3911
3912 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3913 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3914 if (RT_SUCCESS(rc))
3915 { /* likely */ }
3916 else
3917 {
3918 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3919 GCPhysVirtApic));
3920 }
3921}
3922
3923
3924/**
3925 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3926 *
3927 * @param pVCpu The cross context virtual CPU structure.
3928 * @param offReg The offset of the register being written.
3929 * @param uReg The register value to write.
3930 */
3931IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3932{
3933 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3934 Assert(pVmcs);
3935 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3936
3937 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3938 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3939 if (RT_SUCCESS(rc))
3940 { /* likely */ }
3941 else
3942 {
3943 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3944 GCPhysVirtApic));
3945 }
3946}
3947
3948
3949/**
3950 * Sets the vector in a virtual-APIC 256-bit sparse register.
3951 *
3952 * @param pVCpu The cross context virtual CPU structure.
3953 * @param offReg The offset of the 256-bit spare register.
3954 * @param uVector The vector to set.
3955 *
3956 * @remarks This is based on our APIC device code.
3957 */
3958IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3959{
3960 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3961 Assert(pVmcs);
3962
3963 /* Determine the vector offset within the chunk. */
3964 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3965
3966 /* Read the chunk at the offset. */
3967 uint32_t uReg;
3968 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3969 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3970 if (RT_SUCCESS(rc))
3971 {
3972 /* Modify the chunk. */
3973 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3974 uReg |= RT_BIT(idxVectorBit);
3975
3976 /* Write the chunk. */
3977 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3978 if (RT_SUCCESS(rc))
3979 { /* likely */ }
3980 else
3981 {
3982 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
3983 uVector, offReg, GCPhysVirtApic));
3984 }
3985 }
3986 else
3987 {
3988 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
3989 uVector, offReg, GCPhysVirtApic));
3990 }
3991}
3992
3993
3994/**
3995 * Clears the vector in a virtual-APIC 256-bit sparse register.
3996 *
3997 * @param pVCpu The cross context virtual CPU structure.
3998 * @param offReg The offset of the 256-bit spare register.
3999 * @param uVector The vector to clear.
4000 *
4001 * @remarks This is based on our APIC device code.
4002 */
4003IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4004{
4005 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4006 Assert(pVmcs);
4007
4008 /* Determine the vector offset within the chunk. */
4009 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4010
4011 /* Read the chunk at the offset. */
4012 uint32_t uReg;
4013 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4014 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4015 if (RT_SUCCESS(rc))
4016 {
4017 /* Modify the chunk. */
4018 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4019 uReg &= ~RT_BIT(idxVectorBit);
4020
4021 /* Write the chunk. */
4022 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4023 if (RT_SUCCESS(rc))
4024 { /* likely */ }
4025 else
4026 {
4027 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4028 uVector, offReg, GCPhysVirtApic));
4029 }
4030 }
4031 else
4032 {
4033 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4034 uVector, offReg, GCPhysVirtApic));
4035 }
4036}
4037
4038
4039/**
4040 * Checks if a memory access to the APIC-access page must causes an APIC-access
4041 * VM-exit.
4042 *
4043 * @param pVCpu The cross context virtual CPU structure.
4044 * @param offAccess The offset of the register being accessed.
4045 * @param cbAccess The size of the access in bytes.
4046 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4047 * IEM_ACCESS_TYPE_WRITE).
4048 *
4049 * @remarks This must not be used for MSR-based APIC-access page accesses!
4050 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4051 */
4052IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4053{
4054 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4055 Assert(pVmcs);
4056 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4057
4058 /*
4059 * We must cause a VM-exit if any of the following are true:
4060 * - TPR shadowing isn't active.
4061 * - The access size exceeds 32-bits.
4062 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4063 *
4064 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4065 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4066 */
4067 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4068 || cbAccess > sizeof(uint32_t)
4069 || ((offAccess + cbAccess - 1) & 0xc)
4070 || offAccess >= XAPIC_OFF_END + 4)
4071 return true;
4072
4073 /*
4074 * If the access is part of an operation where we have already
4075 * virtualized a virtual-APIC write, we must cause a VM-exit.
4076 */
4077 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4078 return true;
4079
4080 /*
4081 * Check write accesses to the APIC-access page that cause VM-exits.
4082 */
4083 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4084 {
4085 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4086 {
4087 /*
4088 * With APIC-register virtualization, a write access to any of the
4089 * following registers are virtualized. Accessing any other register
4090 * causes a VM-exit.
4091 */
4092 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4093 switch (offAlignedAccess)
4094 {
4095 case XAPIC_OFF_ID:
4096 case XAPIC_OFF_TPR:
4097 case XAPIC_OFF_EOI:
4098 case XAPIC_OFF_LDR:
4099 case XAPIC_OFF_DFR:
4100 case XAPIC_OFF_SVR:
4101 case XAPIC_OFF_ESR:
4102 case XAPIC_OFF_ICR_LO:
4103 case XAPIC_OFF_ICR_HI:
4104 case XAPIC_OFF_LVT_TIMER:
4105 case XAPIC_OFF_LVT_THERMAL:
4106 case XAPIC_OFF_LVT_PERF:
4107 case XAPIC_OFF_LVT_LINT0:
4108 case XAPIC_OFF_LVT_LINT1:
4109 case XAPIC_OFF_LVT_ERROR:
4110 case XAPIC_OFF_TIMER_ICR:
4111 case XAPIC_OFF_TIMER_DCR:
4112 break;
4113 default:
4114 return true;
4115 }
4116 }
4117 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4118 {
4119 /*
4120 * With virtual-interrupt delivery, a write access to any of the
4121 * following registers are virtualized. Accessing any other register
4122 * causes a VM-exit.
4123 *
4124 * Note! The specification does not allow writing to offsets in-between
4125 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4126 */
4127 switch (offAccess)
4128 {
4129 case XAPIC_OFF_TPR:
4130 case XAPIC_OFF_EOI:
4131 case XAPIC_OFF_ICR_LO:
4132 break;
4133 default:
4134 return true;
4135 }
4136 }
4137 else
4138 {
4139 /*
4140 * Without APIC-register virtualization or virtual-interrupt delivery,
4141 * only TPR accesses are virtualized.
4142 */
4143 if (offAccess == XAPIC_OFF_TPR)
4144 { /* likely */ }
4145 else
4146 return true;
4147 }
4148 }
4149 else
4150 {
4151 /*
4152 * Check read accesses to the APIC-access page that cause VM-exits.
4153 */
4154 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4155 {
4156 /*
4157 * With APIC-register virtualization, a read access to any of the
4158 * following registers are virtualized. Accessing any other register
4159 * causes a VM-exit.
4160 */
4161 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4162 switch (offAlignedAccess)
4163 {
4164 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4165 case XAPIC_OFF_ID:
4166 case XAPIC_OFF_VERSION:
4167 case XAPIC_OFF_TPR:
4168 case XAPIC_OFF_EOI:
4169 case XAPIC_OFF_LDR:
4170 case XAPIC_OFF_DFR:
4171 case XAPIC_OFF_SVR:
4172 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4173 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4174 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4175 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4176 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4177 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4178 case XAPIC_OFF_ESR:
4179 case XAPIC_OFF_ICR_LO:
4180 case XAPIC_OFF_ICR_HI:
4181 case XAPIC_OFF_LVT_TIMER:
4182 case XAPIC_OFF_LVT_THERMAL:
4183 case XAPIC_OFF_LVT_PERF:
4184 case XAPIC_OFF_LVT_LINT0:
4185 case XAPIC_OFF_LVT_LINT1:
4186 case XAPIC_OFF_LVT_ERROR:
4187 case XAPIC_OFF_TIMER_ICR:
4188 case XAPIC_OFF_TIMER_DCR:
4189 break;
4190 default:
4191 return true;
4192 }
4193 }
4194 else
4195 {
4196 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4197 if (offAccess == XAPIC_OFF_TPR)
4198 { /* likely */ }
4199 else
4200 return true;
4201 }
4202 }
4203
4204 /* The APIC access is virtualized, does not cause a VM-exit. */
4205 return false;
4206}
4207
4208
4209/**
4210 * Virtualizes a memory-based APIC access where the address is not used to access
4211 * memory.
4212 *
4213 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4214 * page-faults but do not use the address to access memory.
4215 *
4216 * @param pVCpu The cross context virtual CPU structure.
4217 * @param pGCPhysAccess Pointer to the guest-physical address used.
4218 */
4219IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4220{
4221 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4222 Assert(pVmcs);
4223 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4224 Assert(pGCPhysAccess);
4225
4226 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4227 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4228 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4229
4230 if (GCPhysAccess == GCPhysApic)
4231 {
4232 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4233 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4234 uint16_t const cbAccess = 1;
4235 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4236 if (fIntercept)
4237 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4238
4239 *pGCPhysAccess = GCPhysApic | offAccess;
4240 return VINF_VMX_MODIFIES_BEHAVIOR;
4241 }
4242
4243 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4244}
4245
4246
4247/**
4248 * Virtualizes a memory-based APIC access.
4249 *
4250 * @returns VBox strict status code.
4251 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4252 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4253 *
4254 * @param pVCpu The cross context virtual CPU structure.
4255 * @param offAccess The offset of the register being accessed (within the
4256 * APIC-access page).
4257 * @param cbAccess The size of the access in bytes.
4258 * @param pvData Pointer to the data being written or where to store the data
4259 * being read.
4260 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4261 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4262 */
4263IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4264 uint32_t fAccess)
4265{
4266 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4267 Assert(pVmcs);
4268 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4269 Assert(pvData);
4270 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4271 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4272 || (fAccess & IEM_ACCESS_INSTRUCTION));
4273
4274 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4275 if (fIntercept)
4276 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4277
4278 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4279 {
4280 /*
4281 * A write access to the APIC-access page that is virtualized (rather than
4282 * causing a VM-exit) writes data to the virtual-APIC page.
4283 */
4284 uint32_t const u32Data = *(uint32_t *)pvData;
4285 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4286
4287 /*
4288 * Record the currently updated APIC offset, as we need this later for figuring
4289 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4290 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4291 *
4292 * After completion of the current operation, we need to perform TPR virtualization,
4293 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4294 *
4295 * The current operation may be a REP-prefixed string instruction, execution of any
4296 * other instruction, or delivery of an event through the IDT.
4297 *
4298 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4299 * performed now but later after completion of the current operation.
4300 *
4301 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4302 */
4303 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4304 }
4305 else
4306 {
4307 /*
4308 * A read access from the APIC-access page that is virtualized (rather than
4309 * causing a VM-exit) returns data from the virtual-APIC page.
4310 *
4311 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4312 */
4313 Assert(cbAccess <= 4);
4314 Assert(offAccess < XAPIC_OFF_END + 4);
4315 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4316
4317 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4318 u32Data &= s_auAccessSizeMasks[cbAccess];
4319 *(uint32_t *)pvData = u32Data;
4320 }
4321
4322 return VINF_VMX_MODIFIES_BEHAVIOR;
4323}
4324
4325
4326/**
4327 * Virtualizes an MSR-based APIC read access.
4328 *
4329 * @returns VBox strict status code.
4330 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4331 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4332 * handled by the x2APIC device.
4333 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4334 * not within the range of valid MSRs, caller must raise \#GP(0).
4335 * @param pVCpu The cross context virtual CPU structure.
4336 * @param idMsr The x2APIC MSR being read.
4337 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4338 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4339 */
4340IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4341{
4342 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4343 Assert(pVmcs);
4344 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4345 Assert(pu64Value);
4346
4347 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4348 {
4349 /*
4350 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4351 * what the end of the valid x2APIC MSR range is. Hence the use of different
4352 * macros here.
4353 *
4354 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4355 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4356 */
4357 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4358 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4359 {
4360 uint16_t const offReg = (idMsr & 0xff) << 4;
4361 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4362 *pu64Value = u64Value;
4363 return VINF_VMX_MODIFIES_BEHAVIOR;
4364 }
4365 return VERR_OUT_OF_RANGE;
4366 }
4367
4368 if (idMsr == MSR_IA32_X2APIC_TPR)
4369 {
4370 uint16_t const offReg = (idMsr & 0xff) << 4;
4371 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4372 *pu64Value = u64Value;
4373 return VINF_VMX_MODIFIES_BEHAVIOR;
4374 }
4375
4376 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4377}
4378
4379
4380/**
4381 * Virtualizes an MSR-based APIC write access.
4382 *
4383 * @returns VBox strict status code.
4384 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4385 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4386 * not within the range of valid MSRs, caller must raise \#GP(0).
4387 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4388 *
4389 * @param pVCpu The cross context virtual CPU structure.
4390 * @param idMsr The x2APIC MSR being written.
4391 * @param u64Value The value of the x2APIC MSR being written.
4392 */
4393IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4394{
4395 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4396 Assert(pVmcs);
4397
4398 /*
4399 * Check if the access is to be virtualized.
4400 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4401 */
4402 if ( idMsr == MSR_IA32_X2APIC_TPR
4403 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4404 && ( idMsr == MSR_IA32_X2APIC_EOI
4405 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4406 {
4407 /* Validate the MSR write depending on the register. */
4408 switch (idMsr)
4409 {
4410 case MSR_IA32_X2APIC_TPR:
4411 case MSR_IA32_X2APIC_SELF_IPI:
4412 {
4413 if (u64Value & UINT64_C(0xffffffffffffff00))
4414 return VERR_OUT_OF_RANGE;
4415 break;
4416 }
4417 case MSR_IA32_X2APIC_EOI:
4418 {
4419 if (u64Value != 0)
4420 return VERR_OUT_OF_RANGE;
4421 break;
4422 }
4423 }
4424
4425 /* Write the MSR to the virtual-APIC page. */
4426 uint16_t const offReg = (idMsr & 0xff) << 4;
4427 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4428
4429 /*
4430 * Record the currently updated APIC offset, as we need this later for figuring
4431 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4432 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4433 */
4434 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4435
4436 return VINF_VMX_MODIFIES_BEHAVIOR;
4437 }
4438
4439 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4440}
4441
4442
4443/**
4444 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4445 *
4446 * @returns VBox status code.
4447 * @retval VINF_SUCCESS when the highest set bit is found.
4448 * @retval VERR_NOT_FOUND when no bit is set.
4449 *
4450 * @param pVCpu The cross context virtual CPU structure.
4451 * @param offReg The offset of the APIC 256-bit sparse register.
4452 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4453 * set in the register. Only valid when VINF_SUCCESS is
4454 * returned.
4455 *
4456 * @remarks The format of the 256-bit sparse register here mirrors that found in
4457 * real APIC hardware.
4458 */
4459static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4460{
4461 Assert(offReg < XAPIC_OFF_END + 4);
4462 Assert(pidxHighestBit);
4463 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4464
4465 /*
4466 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4467 * However, in each fragment only the first 4 bytes are used.
4468 */
4469 uint8_t const cFrags = 8;
4470 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4471 {
4472 uint16_t const offFrag = iFrag * 16;
4473 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4474 if (!u32Frag)
4475 continue;
4476
4477 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4478 Assert(idxHighestBit > 0);
4479 --idxHighestBit;
4480 Assert(idxHighestBit <= UINT8_MAX);
4481 *pidxHighestBit = idxHighestBit;
4482 return VINF_SUCCESS;
4483 }
4484 return VERR_NOT_FOUND;
4485}
4486
4487
4488/**
4489 * Evaluates pending virtual interrupts.
4490 *
4491 * @param pVCpu The cross context virtual CPU structure.
4492 */
4493IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4494{
4495 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4496 Assert(pVmcs);
4497 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4498
4499 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4500 {
4501 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4502 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4503
4504 if ((uRvi >> 4) > (uPpr >> 4))
4505 {
4506 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4507 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4508 }
4509 else
4510 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4511 }
4512}
4513
4514
4515/**
4516 * Performs PPR virtualization.
4517 *
4518 * @returns VBox strict status code.
4519 * @param pVCpu The cross context virtual CPU structure.
4520 */
4521IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4522{
4523 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4524 Assert(pVmcs);
4525 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4526 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4527
4528 /*
4529 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4530 * or EOI-virtualization.
4531 *
4532 * See Intel spec. 29.1.3 "PPR Virtualization".
4533 */
4534 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4535 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4536
4537 uint32_t uPpr;
4538 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4539 uPpr = uTpr & 0xff;
4540 else
4541 uPpr = uSvi & 0xf0;
4542
4543 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4544 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4545}
4546
4547
4548/**
4549 * Performs VMX TPR virtualization.
4550 *
4551 * @returns VBox strict status code.
4552 * @param pVCpu The cross context virtual CPU structure.
4553 */
4554IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4555{
4556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4557 Assert(pVmcs);
4558 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4559
4560 /*
4561 * We should have already performed the virtual-APIC write to the TPR offset
4562 * in the virtual-APIC page. We now perform TPR virtualization.
4563 *
4564 * See Intel spec. 29.1.2 "TPR Virtualization".
4565 */
4566 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4567 {
4568 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4569 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4570
4571 /*
4572 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4573 * See Intel spec. 29.1.2 "TPR Virtualization".
4574 */
4575 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4576 {
4577 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4578 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4579 }
4580 }
4581 else
4582 {
4583 iemVmxPprVirtualization(pVCpu);
4584 iemVmxEvalPendingVirtIntrs(pVCpu);
4585 }
4586
4587 return VINF_SUCCESS;
4588}
4589
4590
4591/**
4592 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4593 * not.
4594 *
4595 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4596 * @param pVCpu The cross context virtual CPU structure.
4597 * @param uVector The interrupt that was acknowledged using an EOI.
4598 */
4599IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4600{
4601 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4602 Assert(pVmcs);
4603 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4604
4605 if (uVector < 64)
4606 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4607 if (uVector < 128)
4608 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4609 if (uVector < 192)
4610 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4611 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4612}
4613
4614
4615/**
4616 * Performs EOI virtualization.
4617 *
4618 * @returns VBox strict status code.
4619 * @param pVCpu The cross context virtual CPU structure.
4620 */
4621IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4622{
4623 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4624 Assert(pVmcs);
4625 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4626
4627 /*
4628 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4629 * and get the next guest-interrupt that's in-service (if any).
4630 *
4631 * See Intel spec. 29.1.4 "EOI Virtualization".
4632 */
4633 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4634 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4635 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4636
4637 uint8_t uVector = uSvi;
4638 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4639
4640 uVector = 0;
4641 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4642
4643 if (uVector)
4644 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4645 else
4646 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4647
4648 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4649 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4650
4651 iemVmxPprVirtualization(pVCpu);
4652 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4653 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4654 iemVmxEvalPendingVirtIntrs(pVCpu);
4655 return VINF_SUCCESS;
4656}
4657
4658
4659/**
4660 * Performs self-IPI virtualization.
4661 *
4662 * @returns VBox strict status code.
4663 * @param pVCpu The cross context virtual CPU structure.
4664 */
4665IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4666{
4667 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4668 Assert(pVmcs);
4669 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4670
4671 /*
4672 * We should have already performed the virtual-APIC write to the self-IPI offset
4673 * in the virtual-APIC page. We now perform self-IPI virtualization.
4674 *
4675 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4676 */
4677 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4678 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4679 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4680 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4681 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4682 if (uVector > uRvi)
4683 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4684 iemVmxEvalPendingVirtIntrs(pVCpu);
4685 return VINF_SUCCESS;
4686}
4687
4688
4689/**
4690 * Performs VMX APIC-write emulation.
4691 *
4692 * @returns VBox strict status code.
4693 * @param pVCpu The cross context virtual CPU structure.
4694 */
4695IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4696{
4697 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4698 Assert(pVmcs);
4699
4700 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4701 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4702
4703 /*
4704 * Perform APIC-write emulation based on the virtual-APIC register written.
4705 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4706 */
4707 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4708 VBOXSTRICTRC rcStrict;
4709 switch (offApicWrite)
4710 {
4711 case XAPIC_OFF_TPR:
4712 {
4713 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4714 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4715 uTpr &= UINT32_C(0x000000ff);
4716 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4717 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4718 rcStrict = iemVmxTprVirtualization(pVCpu);
4719 break;
4720 }
4721
4722 case XAPIC_OFF_EOI:
4723 {
4724 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4725 {
4726 /* Clear VEOI and perform EOI virtualization. */
4727 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4728 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4729 rcStrict = iemVmxEoiVirtualization(pVCpu);
4730 }
4731 else
4732 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4733 break;
4734 }
4735
4736 case XAPIC_OFF_ICR_LO:
4737 {
4738 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4739 {
4740 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4741 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4742 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4743 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4744 if ( !(uIcrLo & fIcrLoMb0)
4745 && (uIcrLo & fIcrLoMb1))
4746 {
4747 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4748 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4749 }
4750 else
4751 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4752 }
4753 else
4754 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4755 break;
4756 }
4757
4758 case XAPIC_OFF_ICR_HI:
4759 {
4760 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4761 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4762 uIcrHi &= UINT32_C(0xff000000);
4763 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4764 rcStrict = VINF_SUCCESS;
4765 break;
4766 }
4767
4768 default:
4769 {
4770 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4771 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4772 break;
4773 }
4774 }
4775
4776 return rcStrict;
4777}
4778
4779
4780/**
4781 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4782 *
4783 * @param pVCpu The cross context virtual CPU structure.
4784 * @param pszInstr The VMX instruction name (for logging purposes).
4785 */
4786IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4787{
4788 /*
4789 * Guest Control Registers, Debug Registers, and MSRs.
4790 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4791 */
4792 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4793 const char *const pszFailure = "VM-exit";
4794 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4795
4796 /* CR0 reserved bits. */
4797 {
4798 /* CR0 MB1 bits. */
4799 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4800 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4801 if (fUnrestrictedGuest)
4802 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4803 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4804 { /* likely */ }
4805 else
4806 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4807
4808 /* CR0 MBZ bits. */
4809 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4810 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4811 { /* likely */ }
4812 else
4813 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4814
4815 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4816 if ( !fUnrestrictedGuest
4817 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4818 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4820 }
4821
4822 /* CR4 reserved bits. */
4823 {
4824 /* CR4 MB1 bits. */
4825 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4826 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4827 { /* likely */ }
4828 else
4829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4830
4831 /* CR4 MBZ bits. */
4832 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4833 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4834 { /* likely */ }
4835 else
4836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4837 }
4838
4839 /* DEBUGCTL MSR. */
4840 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4841 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4842 { /* likely */ }
4843 else
4844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4845
4846 /* 64-bit CPU checks. */
4847 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4848 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4849 {
4850 if (fGstInLongMode)
4851 {
4852 /* PAE must be set. */
4853 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4854 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4855 { /* likely */ }
4856 else
4857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4858 }
4859 else
4860 {
4861 /* PCIDE should not be set. */
4862 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4863 { /* likely */ }
4864 else
4865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4866 }
4867
4868 /* CR3. */
4869 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4870 { /* likely */ }
4871 else
4872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4873
4874 /* DR7. */
4875 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4876 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4877 { /* likely */ }
4878 else
4879 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4880
4881 /* SYSENTER ESP and SYSENTER EIP. */
4882 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4883 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4884 { /* likely */ }
4885 else
4886 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4887 }
4888
4889 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4890 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4891
4892 /* PAT MSR. */
4893 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4894 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4895 { /* likely */ }
4896 else
4897 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4898
4899 /* EFER MSR. */
4900 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4901 {
4902 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4903 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4904 { /* likely */ }
4905 else
4906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4907
4908 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4909 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4910 if ( fGstLma == fGstInLongMode
4911 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4912 || fGstLma == fGstLme))
4913 { /* likely */ }
4914 else
4915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4916 }
4917
4918 /* We don't support IA32_BNDCFGS MSR yet. */
4919 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4920
4921 NOREF(pszInstr);
4922 NOREF(pszFailure);
4923 return VINF_SUCCESS;
4924}
4925
4926
4927/**
4928 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4929 *
4930 * @param pVCpu The cross context virtual CPU structure.
4931 * @param pszInstr The VMX instruction name (for logging purposes).
4932 */
4933IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4934{
4935 /*
4936 * Segment registers.
4937 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4938 */
4939 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4940 const char *const pszFailure = "VM-exit";
4941 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4942 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4943 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4944
4945 /* Selectors. */
4946 if ( !fGstInV86Mode
4947 && !fUnrestrictedGuest
4948 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4950
4951 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4952 {
4953 CPUMSELREG SelReg;
4954 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4955 if (RT_LIKELY(rc == VINF_SUCCESS))
4956 { /* likely */ }
4957 else
4958 return rc;
4959
4960 /*
4961 * Virtual-8086 mode checks.
4962 */
4963 if (fGstInV86Mode)
4964 {
4965 /* Base address. */
4966 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4967 { /* likely */ }
4968 else
4969 {
4970 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4972 }
4973
4974 /* Limit. */
4975 if (SelReg.u32Limit == 0xffff)
4976 { /* likely */ }
4977 else
4978 {
4979 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4980 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4981 }
4982
4983 /* Attribute. */
4984 if (SelReg.Attr.u == 0xf3)
4985 { /* likely */ }
4986 else
4987 {
4988 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4990 }
4991
4992 /* We're done; move to checking the next segment. */
4993 continue;
4994 }
4995
4996 /* Checks done by 64-bit CPUs. */
4997 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4998 {
4999 /* Base address. */
5000 if ( iSegReg == X86_SREG_FS
5001 || iSegReg == X86_SREG_GS)
5002 {
5003 if (X86_IS_CANONICAL(SelReg.u64Base))
5004 { /* likely */ }
5005 else
5006 {
5007 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5008 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5009 }
5010 }
5011 else if (iSegReg == X86_SREG_CS)
5012 {
5013 if (!RT_HI_U32(SelReg.u64Base))
5014 { /* likely */ }
5015 else
5016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5017 }
5018 else
5019 {
5020 if ( SelReg.Attr.n.u1Unusable
5021 || !RT_HI_U32(SelReg.u64Base))
5022 { /* likely */ }
5023 else
5024 {
5025 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5026 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5027 }
5028 }
5029 }
5030
5031 /*
5032 * Checks outside Virtual-8086 mode.
5033 */
5034 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5035 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5036 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5037 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5038 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5039 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5040 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5041 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5042
5043 /* Code or usable segment. */
5044 if ( iSegReg == X86_SREG_CS
5045 || fUsable)
5046 {
5047 /* Reserved bits (bits 31:17 and bits 11:8). */
5048 if (!(SelReg.Attr.u & 0xfffe0f00))
5049 { /* likely */ }
5050 else
5051 {
5052 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5053 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5054 }
5055
5056 /* Descriptor type. */
5057 if (fCodeDataSeg)
5058 { /* likely */ }
5059 else
5060 {
5061 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5063 }
5064
5065 /* Present. */
5066 if (fPresent)
5067 { /* likely */ }
5068 else
5069 {
5070 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5071 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5072 }
5073
5074 /* Granularity. */
5075 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5076 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5077 { /* likely */ }
5078 else
5079 {
5080 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5082 }
5083 }
5084
5085 if (iSegReg == X86_SREG_CS)
5086 {
5087 /* Segment Type and DPL. */
5088 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5089 && fUnrestrictedGuest)
5090 {
5091 if (uDpl == 0)
5092 { /* likely */ }
5093 else
5094 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5095 }
5096 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5097 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5098 {
5099 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5100 if (uDpl == AttrSs.n.u2Dpl)
5101 { /* likely */ }
5102 else
5103 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5104 }
5105 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5106 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5107 {
5108 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5109 if (uDpl <= AttrSs.n.u2Dpl)
5110 { /* likely */ }
5111 else
5112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5113 }
5114 else
5115 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5116
5117 /* Def/Big. */
5118 if ( fGstInLongMode
5119 && fSegLong)
5120 {
5121 if (uDefBig == 0)
5122 { /* likely */ }
5123 else
5124 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5125 }
5126 }
5127 else if (iSegReg == X86_SREG_SS)
5128 {
5129 /* Segment Type. */
5130 if ( !fUsable
5131 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5132 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5133 { /* likely */ }
5134 else
5135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5136
5137 /* DPL. */
5138 if (!fUnrestrictedGuest)
5139 {
5140 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5141 { /* likely */ }
5142 else
5143 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5144 }
5145 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5146 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5147 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5148 {
5149 if (uDpl == 0)
5150 { /* likely */ }
5151 else
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5153 }
5154 }
5155 else
5156 {
5157 /* DS, ES, FS, GS. */
5158 if (fUsable)
5159 {
5160 /* Segment type. */
5161 if (uSegType & X86_SEL_TYPE_ACCESSED)
5162 { /* likely */ }
5163 else
5164 {
5165 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5167 }
5168
5169 if ( !(uSegType & X86_SEL_TYPE_CODE)
5170 || (uSegType & X86_SEL_TYPE_READ))
5171 { /* likely */ }
5172 else
5173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5174
5175 /* DPL. */
5176 if ( !fUnrestrictedGuest
5177 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5178 {
5179 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5180 { /* likely */ }
5181 else
5182 {
5183 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5185 }
5186 }
5187 }
5188 }
5189 }
5190
5191 /*
5192 * LDTR.
5193 */
5194 {
5195 CPUMSELREG Ldtr;
5196 Ldtr.Sel = pVmcs->GuestLdtr;
5197 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5198 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5199 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5200
5201 if (!Ldtr.Attr.n.u1Unusable)
5202 {
5203 /* Selector. */
5204 if (!(Ldtr.Sel & X86_SEL_LDT))
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5208
5209 /* Base. */
5210 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5211 {
5212 if (X86_IS_CANONICAL(Ldtr.u64Base))
5213 { /* likely */ }
5214 else
5215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5216 }
5217
5218 /* Attributes. */
5219 /* Reserved bits (bits 31:17 and bits 11:8). */
5220 if (!(Ldtr.Attr.u & 0xfffe0f00))
5221 { /* likely */ }
5222 else
5223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5224
5225 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5226 { /* likely */ }
5227 else
5228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5229
5230 if (!Ldtr.Attr.n.u1DescType)
5231 { /* likely */ }
5232 else
5233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5234
5235 if (Ldtr.Attr.n.u1Present)
5236 { /* likely */ }
5237 else
5238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5239
5240 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5241 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5242 { /* likely */ }
5243 else
5244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5245 }
5246 }
5247
5248 /*
5249 * TR.
5250 */
5251 {
5252 CPUMSELREG Tr;
5253 Tr.Sel = pVmcs->GuestTr;
5254 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5255 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5256 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5257
5258 /* Selector. */
5259 if (!(Tr.Sel & X86_SEL_LDT))
5260 { /* likely */ }
5261 else
5262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5263
5264 /* Base. */
5265 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5266 {
5267 if (X86_IS_CANONICAL(Tr.u64Base))
5268 { /* likely */ }
5269 else
5270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5271 }
5272
5273 /* Attributes. */
5274 /* Reserved bits (bits 31:17 and bits 11:8). */
5275 if (!(Tr.Attr.u & 0xfffe0f00))
5276 { /* likely */ }
5277 else
5278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5279
5280 if (!Tr.Attr.n.u1Unusable)
5281 { /* likely */ }
5282 else
5283 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5284
5285 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5286 || ( !fGstInLongMode
5287 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5288 { /* likely */ }
5289 else
5290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5291
5292 if (!Tr.Attr.n.u1DescType)
5293 { /* likely */ }
5294 else
5295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5296
5297 if (Tr.Attr.n.u1Present)
5298 { /* likely */ }
5299 else
5300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5301
5302 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5303 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5304 { /* likely */ }
5305 else
5306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5307 }
5308
5309 NOREF(pszInstr);
5310 NOREF(pszFailure);
5311 return VINF_SUCCESS;
5312}
5313
5314
5315/**
5316 * Checks guest GDTR and IDTR as part of VM-entry.
5317 *
5318 * @param pVCpu The cross context virtual CPU structure.
5319 * @param pszInstr The VMX instruction name (for logging purposes).
5320 */
5321IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5322{
5323 /*
5324 * GDTR and IDTR.
5325 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5326 */
5327 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5328 const char *const pszFailure = "VM-exit";
5329
5330 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5331 {
5332 /* Base. */
5333 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5334 { /* likely */ }
5335 else
5336 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5337
5338 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5339 { /* likely */ }
5340 else
5341 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5342 }
5343
5344 /* Limit. */
5345 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5346 { /* likely */ }
5347 else
5348 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5349
5350 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5351 { /* likely */ }
5352 else
5353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5354
5355 NOREF(pszInstr);
5356 NOREF(pszFailure);
5357 return VINF_SUCCESS;
5358}
5359
5360
5361/**
5362 * Checks guest RIP and RFLAGS as part of VM-entry.
5363 *
5364 * @param pVCpu The cross context virtual CPU structure.
5365 * @param pszInstr The VMX instruction name (for logging purposes).
5366 */
5367IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5368{
5369 /*
5370 * RIP and RFLAGS.
5371 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5372 */
5373 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5374 const char *const pszFailure = "VM-exit";
5375 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5376
5377 /* RIP. */
5378 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5379 {
5380 X86DESCATTR AttrCs;
5381 AttrCs.u = pVmcs->u32GuestCsAttr;
5382 if ( !fGstInLongMode
5383 || !AttrCs.n.u1Long)
5384 {
5385 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5386 { /* likely */ }
5387 else
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5389 }
5390
5391 if ( fGstInLongMode
5392 && AttrCs.n.u1Long)
5393 {
5394 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5395 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5396 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5397 { /* likely */ }
5398 else
5399 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5400 }
5401 }
5402
5403 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5404 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5405 : pVmcs->u64GuestRFlags.s.Lo;
5406 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5407 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5408 { /* likely */ }
5409 else
5410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5411
5412 if ( fGstInLongMode
5413 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5414 {
5415 if (!(uGuestRFlags & X86_EFL_VM))
5416 { /* likely */ }
5417 else
5418 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5419 }
5420
5421 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5422 {
5423 if (uGuestRFlags & X86_EFL_IF)
5424 { /* likely */ }
5425 else
5426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5427 }
5428
5429 NOREF(pszInstr);
5430 NOREF(pszFailure);
5431 return VINF_SUCCESS;
5432}
5433
5434
5435/**
5436 * Checks guest non-register state as part of VM-entry.
5437 *
5438 * @param pVCpu The cross context virtual CPU structure.
5439 * @param pszInstr The VMX instruction name (for logging purposes).
5440 */
5441IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5442{
5443 /*
5444 * Guest non-register state.
5445 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5446 */
5447 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5448 const char *const pszFailure = "VM-exit";
5449
5450 /*
5451 * Activity state.
5452 */
5453 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5454 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5455 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5456 { /* likely */ }
5457 else
5458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5459
5460 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5461 if ( !AttrSs.n.u2Dpl
5462 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5463 { /* likely */ }
5464 else
5465 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5466
5467 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5468 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5469 {
5470 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5471 { /* likely */ }
5472 else
5473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5474 }
5475
5476 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5477 {
5478 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5479 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5480 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5481 switch (pVmcs->u32GuestActivityState)
5482 {
5483 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5484 {
5485 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5486 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5487 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5488 && ( uVector == X86_XCPT_DB
5489 || uVector == X86_XCPT_MC))
5490 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5491 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5492 { /* likely */ }
5493 else
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5495 break;
5496 }
5497
5498 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5499 {
5500 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5501 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5502 && uVector == X86_XCPT_MC))
5503 { /* likely */ }
5504 else
5505 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5506 break;
5507 }
5508
5509 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5510 default:
5511 break;
5512 }
5513 }
5514
5515 /*
5516 * Interruptibility state.
5517 */
5518 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5519 { /* likely */ }
5520 else
5521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5522
5523 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5524 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5525 { /* likely */ }
5526 else
5527 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5528
5529 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5530 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5531 { /* likely */ }
5532 else
5533 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5534
5535 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5536 {
5537 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5538 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5539 {
5540 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5541 { /* likely */ }
5542 else
5543 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5544 }
5545 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5546 {
5547 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5548 { /* likely */ }
5549 else
5550 {
5551 /*
5552 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5553 * We update the Exit qualification only when blocking-by-STI is set
5554 * without blocking-by-MovSS being set. Although in practise it does not
5555 * make much difference since the order of checks are implementation defined.
5556 */
5557 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5558 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5560 }
5561
5562 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5563 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5564 { /* likely */ }
5565 else
5566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5567 }
5568 }
5569
5570 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5571 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5572 { /* likely */ }
5573 else
5574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5575
5576 /* We don't support SGX yet. So enclave-interruption must not be set. */
5577 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5578 { /* likely */ }
5579 else
5580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5581
5582 /*
5583 * Pending debug exceptions.
5584 */
5585 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5586 ? pVmcs->u64GuestPendingDbgXcpt.u
5587 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5588 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5589 { /* likely */ }
5590 else
5591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5592
5593 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5594 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5595 {
5596 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5597 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5598 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5599 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5600
5601 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5602 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5603 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5605 }
5606
5607 /* We don't support RTM (Real-time Transactional Memory) yet. */
5608 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5609 { /* likely */ }
5610 else
5611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5612
5613 /*
5614 * VMCS link pointer.
5615 */
5616 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5617 {
5618 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5619 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5620 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5621 { /* likely */ }
5622 else
5623 {
5624 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5626 }
5627
5628 /* Validate the address. */
5629 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5630 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5631 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5632 { /* likely */ }
5633 else
5634 {
5635 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5636 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5637 }
5638
5639 /* Read the VMCS-link pointer from guest memory. */
5640 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5641 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5642 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
5643 if (RT_SUCCESS(rc))
5644 { /* likely */ }
5645 else
5646 {
5647 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5649 }
5650
5651 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5652 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5653 { /* likely */ }
5654 else
5655 {
5656 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5657 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5658 }
5659
5660 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5661 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5662 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5663 { /* likely */ }
5664 else
5665 {
5666 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5667 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5668 }
5669
5670 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5671 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5672 }
5673
5674 NOREF(pszInstr);
5675 NOREF(pszFailure);
5676 return VINF_SUCCESS;
5677}
5678
5679
5680/**
5681 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5682 * VM-entry.
5683 *
5684 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5685 * @param pVCpu The cross context virtual CPU structure.
5686 * @param pszInstr The VMX instruction name (for logging purposes).
5687 * @param pVmcs Pointer to the virtual VMCS.
5688 */
5689IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5690{
5691 /*
5692 * Check PDPTEs.
5693 * See Intel spec. 4.4.1 "PDPTE Registers".
5694 */
5695 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5696 const char *const pszFailure = "VM-exit";
5697
5698 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5699 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5700 if (RT_SUCCESS(rc))
5701 {
5702 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5703 {
5704 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5705 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5706 { /* likely */ }
5707 else
5708 {
5709 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5710 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5711 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5712 }
5713 }
5714 }
5715 else
5716 {
5717 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5718 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5719 }
5720
5721 NOREF(pszFailure);
5722 NOREF(pszInstr);
5723 return rc;
5724}
5725
5726
5727/**
5728 * Checks guest PDPTEs as part of VM-entry.
5729 *
5730 * @param pVCpu The cross context virtual CPU structure.
5731 * @param pszInstr The VMX instruction name (for logging purposes).
5732 */
5733IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5734{
5735 /*
5736 * Guest PDPTEs.
5737 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5738 */
5739 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5740 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5741
5742 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5743 int rc;
5744 if ( !fGstInLongMode
5745 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5746 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5747 {
5748 /*
5749 * We don't support nested-paging for nested-guests yet.
5750 *
5751 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5752 * rather we need to check the PDPTEs referenced by the guest CR3.
5753 */
5754 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5755 }
5756 else
5757 rc = VINF_SUCCESS;
5758 return rc;
5759}
5760
5761
5762/**
5763 * Checks guest-state as part of VM-entry.
5764 *
5765 * @returns VBox status code.
5766 * @param pVCpu The cross context virtual CPU structure.
5767 * @param pszInstr The VMX instruction name (for logging purposes).
5768 */
5769IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5770{
5771 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5772 if (RT_SUCCESS(rc))
5773 {
5774 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5775 if (RT_SUCCESS(rc))
5776 {
5777 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5778 if (RT_SUCCESS(rc))
5779 {
5780 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5781 if (RT_SUCCESS(rc))
5782 {
5783 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5784 if (RT_SUCCESS(rc))
5785 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5786 }
5787 }
5788 }
5789 }
5790 return rc;
5791}
5792
5793
5794/**
5795 * Checks host-state as part of VM-entry.
5796 *
5797 * @returns VBox status code.
5798 * @param pVCpu The cross context virtual CPU structure.
5799 * @param pszInstr The VMX instruction name (for logging purposes).
5800 */
5801IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5802{
5803 /*
5804 * Host Control Registers and MSRs.
5805 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5806 */
5807 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5808 const char * const pszFailure = "VMFail";
5809
5810 /* CR0 reserved bits. */
5811 {
5812 /* CR0 MB1 bits. */
5813 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5814 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5815 { /* likely */ }
5816 else
5817 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5818
5819 /* CR0 MBZ bits. */
5820 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5821 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5822 { /* likely */ }
5823 else
5824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5825 }
5826
5827 /* CR4 reserved bits. */
5828 {
5829 /* CR4 MB1 bits. */
5830 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5831 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5832 { /* likely */ }
5833 else
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5835
5836 /* CR4 MBZ bits. */
5837 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5838 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5839 { /* likely */ }
5840 else
5841 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5842 }
5843
5844 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5845 {
5846 /* CR3 reserved bits. */
5847 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5848 { /* likely */ }
5849 else
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5851
5852 /* SYSENTER ESP and SYSENTER EIP. */
5853 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5854 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5855 { /* likely */ }
5856 else
5857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5858 }
5859
5860 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5861 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5862
5863 /* PAT MSR. */
5864 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5865 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5866 { /* likely */ }
5867 else
5868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5869
5870 /* EFER MSR. */
5871 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5872 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5873 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5874 { /* likely */ }
5875 else
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5877
5878 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5879 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5880 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5881 if ( fHostInLongMode == fHostLma
5882 && fHostInLongMode == fHostLme)
5883 { /* likely */ }
5884 else
5885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5886
5887 /*
5888 * Host Segment and Descriptor-Table Registers.
5889 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5890 */
5891 /* Selector RPL and TI. */
5892 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5893 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5894 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5895 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5896 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5897 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5898 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5899 { /* likely */ }
5900 else
5901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5902
5903 /* CS and TR selectors cannot be 0. */
5904 if ( pVmcs->HostCs
5905 && pVmcs->HostTr)
5906 { /* likely */ }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5909
5910 /* SS cannot be 0 if 32-bit host. */
5911 if ( fHostInLongMode
5912 || pVmcs->HostSs)
5913 { /* likely */ }
5914 else
5915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5916
5917 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5918 {
5919 /* FS, GS, GDTR, IDTR, TR base address. */
5920 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5921 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5922 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5923 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5924 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5925 { /* likely */ }
5926 else
5927 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5928 }
5929
5930 /*
5931 * Host address-space size for 64-bit CPUs.
5932 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5933 */
5934 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5935 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5936 {
5937 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5938
5939 /* Logical processor in IA-32e mode. */
5940 if (fCpuInLongMode)
5941 {
5942 if (fHostInLongMode)
5943 {
5944 /* PAE must be set. */
5945 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5946 { /* likely */ }
5947 else
5948 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5949
5950 /* RIP must be canonical. */
5951 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5952 { /* likely */ }
5953 else
5954 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5955 }
5956 else
5957 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5958 }
5959 else
5960 {
5961 /* Logical processor is outside IA-32e mode. */
5962 if ( !fGstInLongMode
5963 && !fHostInLongMode)
5964 {
5965 /* PCIDE should not be set. */
5966 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5967 { /* likely */ }
5968 else
5969 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5970
5971 /* The high 32-bits of RIP MBZ. */
5972 if (!pVmcs->u64HostRip.s.Hi)
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5976 }
5977 else
5978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5979 }
5980 }
5981 else
5982 {
5983 /* Host address-space size for 32-bit CPUs. */
5984 if ( !fGstInLongMode
5985 && !fHostInLongMode)
5986 { /* likely */ }
5987 else
5988 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5989 }
5990
5991 NOREF(pszInstr);
5992 NOREF(pszFailure);
5993 return VINF_SUCCESS;
5994}
5995
5996
5997/**
5998 * Checks VM-entry controls fields as part of VM-entry.
5999 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6000 *
6001 * @returns VBox status code.
6002 * @param pVCpu The cross context virtual CPU structure.
6003 * @param pszInstr The VMX instruction name (for logging purposes).
6004 */
6005IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPUCC pVCpu, const char *pszInstr)
6006{
6007 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6008 const char * const pszFailure = "VMFail";
6009
6010 /* VM-entry controls. */
6011 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6012 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6013 { /* likely */ }
6014 else
6015 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6016
6017 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6018 { /* likely */ }
6019 else
6020 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6021
6022 /* Event injection. */
6023 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6024 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6025 {
6026 /* Type and vector. */
6027 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6028 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6029 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6030 if ( !uRsvd
6031 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6032 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6033 { /* likely */ }
6034 else
6035 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6036
6037 /* Exception error code. */
6038 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6039 {
6040 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6041 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6042 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6043 { /* likely */ }
6044 else
6045 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6046
6047 /* Exceptions that provide an error code. */
6048 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6049 && ( uVector == X86_XCPT_DF
6050 || uVector == X86_XCPT_TS
6051 || uVector == X86_XCPT_NP
6052 || uVector == X86_XCPT_SS
6053 || uVector == X86_XCPT_GP
6054 || uVector == X86_XCPT_PF
6055 || uVector == X86_XCPT_AC))
6056 { /* likely */ }
6057 else
6058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6059
6060 /* Exception error-code reserved bits. */
6061 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6062 { /* likely */ }
6063 else
6064 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6065
6066 /* Injecting a software interrupt, software exception or privileged software exception. */
6067 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6068 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6069 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6070 {
6071 /* Instruction length must be in the range 0-15. */
6072 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6073 { /* likely */ }
6074 else
6075 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6076
6077 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6078 if ( pVmcs->u32EntryInstrLen != 0
6079 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6080 { /* likely */ }
6081 else
6082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6083 }
6084 }
6085 }
6086
6087 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6088 if (pVmcs->u32EntryMsrLoadCount)
6089 {
6090 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6091 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6092 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6093 { /* likely */ }
6094 else
6095 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6096 }
6097
6098 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6099 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6100
6101 NOREF(pszInstr);
6102 NOREF(pszFailure);
6103 return VINF_SUCCESS;
6104}
6105
6106
6107/**
6108 * Checks VM-exit controls fields as part of VM-entry.
6109 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6110 *
6111 * @returns VBox status code.
6112 * @param pVCpu The cross context virtual CPU structure.
6113 * @param pszInstr The VMX instruction name (for logging purposes).
6114 */
6115IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPUCC pVCpu, const char *pszInstr)
6116{
6117 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6118 const char * const pszFailure = "VMFail";
6119
6120 /* VM-exit controls. */
6121 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6122 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6123 { /* likely */ }
6124 else
6125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6126
6127 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6128 { /* likely */ }
6129 else
6130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6131
6132 /* Save preemption timer without activating it. */
6133 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6134 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6135 { /* likely */ }
6136 else
6137 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6138
6139 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6140 if (pVmcs->u32ExitMsrStoreCount)
6141 {
6142 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6143 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6144 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6145 { /* likely */ }
6146 else
6147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6148 }
6149
6150 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6151 if (pVmcs->u32ExitMsrLoadCount)
6152 {
6153 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6154 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6155 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6156 { /* likely */ }
6157 else
6158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6159 }
6160
6161 NOREF(pszInstr);
6162 NOREF(pszFailure);
6163 return VINF_SUCCESS;
6164}
6165
6166
6167/**
6168 * Checks VM-execution controls fields as part of VM-entry.
6169 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6170 *
6171 * @returns VBox status code.
6172 * @param pVCpu The cross context virtual CPU structure.
6173 * @param pszInstr The VMX instruction name (for logging purposes).
6174 *
6175 * @remarks This may update secondary-processor based VM-execution control fields
6176 * in the current VMCS if necessary.
6177 */
6178IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPUCC pVCpu, const char *pszInstr)
6179{
6180 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6181 const char * const pszFailure = "VMFail";
6182
6183 /* Pin-based VM-execution controls. */
6184 {
6185 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6186 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6187 { /* likely */ }
6188 else
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6190
6191 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6192 { /* likely */ }
6193 else
6194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6195 }
6196
6197 /* Processor-based VM-execution controls. */
6198 {
6199 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6200 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6201 { /* likely */ }
6202 else
6203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6204
6205 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6209 }
6210
6211 /* Secondary processor-based VM-execution controls. */
6212 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6213 {
6214 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6215 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6219
6220 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6221 { /* likely */ }
6222 else
6223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6224 }
6225 else
6226 Assert(!pVmcs->u32ProcCtls2);
6227
6228 /* CR3-target count. */
6229 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6230 { /* likely */ }
6231 else
6232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6233
6234 /* I/O bitmaps physical addresses. */
6235 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6236 {
6237 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6238 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6239 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6240 { /* likely */ }
6241 else
6242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6243
6244 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6245 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6246 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6247 { /* likely */ }
6248 else
6249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6250 }
6251
6252 /* MSR bitmap physical address. */
6253 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6254 {
6255 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6256 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6257 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6258 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6259 { /* likely */ }
6260 else
6261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6262
6263 /* Read the MSR bitmap. */
6264 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6265 * implementing fast path. */
6266 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6267 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6268 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6269 if (RT_SUCCESS(rc))
6270 { /* likely */ }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6273 }
6274
6275 /* TPR shadow related controls. */
6276 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6277 {
6278 /* Virtual-APIC page physical address. */
6279 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6280 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6281 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6282 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6283 { /* likely */ }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6286
6287 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6288 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6289 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6290 { /* likely */ }
6291 else
6292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6293
6294 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6295 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6296 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6297 {
6298 /* Read the VTPR from the virtual-APIC page. */
6299 uint8_t u8VTpr;
6300 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6301 if (RT_SUCCESS(rc))
6302 { /* likely */ }
6303 else
6304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6305
6306 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6307 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6308 { /* likely */ }
6309 else
6310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6311 }
6312 }
6313 else
6314 {
6315 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6316 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6317 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6318 { /* likely */ }
6319 else
6320 {
6321 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6323 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6325 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6327 }
6328 }
6329
6330 /* NMI exiting and virtual-NMIs. */
6331 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6332 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6333 { /* likely */ }
6334 else
6335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6336
6337 /* Virtual-NMIs and NMI-window exiting. */
6338 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6339 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6340 { /* likely */ }
6341 else
6342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6343
6344 /* Virtualize APIC accesses. */
6345 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6346 {
6347 /* APIC-access physical address. */
6348 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6349 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6350 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6351 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6352 { /* likely */ }
6353 else
6354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6355
6356 /*
6357 * Disallow APIC-access page and virtual-APIC page from being the same address.
6358 * Note! This is not an Intel requirement, but one imposed by our implementation.
6359 */
6360 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6361 * redirecting accesses between the APIC-access page and the virtual-APIC
6362 * page. If any guest hypervisor requires this, we can implement it later. */
6363 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6364 {
6365 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6366 if (GCPhysVirtApic != GCPhysApicAccess)
6367 { /* likely */ }
6368 else
6369 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6370 }
6371
6372 /*
6373 * Register the handler for the APIC-access page.
6374 *
6375 * We don't deregister the APIC-access page handler during the VM-exit as a different
6376 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6377 *
6378 * We leave the page registered until the first access that happens outside VMX non-root
6379 * mode. Guest software is allowed to access structures such as the APIC-access page
6380 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6381 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6382 *
6383 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6384 */
6385 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6386 {
6387 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6388 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6389 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6390 if (RT_SUCCESS(rc))
6391 { /* likely */ }
6392 else
6393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6394 }
6395 }
6396
6397 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6398 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6399 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6400 { /* likely */ }
6401 else
6402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6403
6404 /* Virtual-interrupt delivery requires external interrupt exiting. */
6405 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6406 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6407 { /* likely */ }
6408 else
6409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6410
6411 /* VPID. */
6412 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6413 || pVmcs->u16Vpid != 0)
6414 { /* likely */ }
6415 else
6416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6417
6418 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6419 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6420 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6421 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6422 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6423 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6424 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6425
6426 /* VMCS shadowing. */
6427 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6428 {
6429 /* VMREAD-bitmap physical address. */
6430 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6431 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6432 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6433 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6434 { /* likely */ }
6435 else
6436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6437
6438 /* VMWRITE-bitmap physical address. */
6439 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6440 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6441 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6442 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6443 { /* likely */ }
6444 else
6445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6446
6447 /* Read the VMREAD-bitmap. */
6448 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6449 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6450 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6451 if (RT_SUCCESS(rc))
6452 { /* likely */ }
6453 else
6454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6455
6456 /* Read the VMWRITE-bitmap. */
6457 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6458 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6459 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6460 if (RT_SUCCESS(rc))
6461 { /* likely */ }
6462 else
6463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6464 }
6465
6466 NOREF(pszInstr);
6467 NOREF(pszFailure);
6468 return VINF_SUCCESS;
6469}
6470
6471
6472/**
6473 * Loads the guest control registers, debug register and some MSRs as part of
6474 * VM-entry.
6475 *
6476 * @param pVCpu The cross context virtual CPU structure.
6477 */
6478IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6479{
6480 /*
6481 * Load guest control registers, debug registers and MSRs.
6482 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6483 */
6484 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6485
6486 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6487 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6488 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6489 CPUMSetGuestCR0(pVCpu, uGstCr0);
6490 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6491 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6492
6493 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6494 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6495
6496 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6497 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6498 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6499
6500 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6501 {
6502 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6503
6504 /* EFER MSR. */
6505 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6506 {
6507 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6508 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6509 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6510 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6511 if (fGstInLongMode)
6512 {
6513 /* If the nested-guest is in long mode, LMA and LME are both set. */
6514 Assert(fGstPaging);
6515 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6516 }
6517 else
6518 {
6519 /*
6520 * If the nested-guest is outside long mode:
6521 * - With paging: LMA is cleared, LME is cleared.
6522 * - Without paging: LMA is cleared, LME is left unmodified.
6523 */
6524 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6525 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6526 }
6527 }
6528 /* else: see below. */
6529 }
6530
6531 /* PAT MSR. */
6532 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6533 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6534
6535 /* EFER MSR. */
6536 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6537 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6538
6539 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6540 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6541
6542 /* We don't support IA32_BNDCFGS MSR yet. */
6543 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6544
6545 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6546}
6547
6548
6549/**
6550 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6551 *
6552 * @param pVCpu The cross context virtual CPU structure.
6553 */
6554IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6555{
6556 /*
6557 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6558 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6559 */
6560 /* CS, SS, ES, DS, FS, GS. */
6561 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6562 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6563 {
6564 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6565 CPUMSELREG VmcsSelReg;
6566 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6567 AssertRC(rc); NOREF(rc);
6568 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6569 {
6570 pGstSelReg->Sel = VmcsSelReg.Sel;
6571 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6572 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6573 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6574 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6575 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6576 }
6577 else
6578 {
6579 pGstSelReg->Sel = VmcsSelReg.Sel;
6580 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6581 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6582 switch (iSegReg)
6583 {
6584 case X86_SREG_CS:
6585 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6586 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6587 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6588 break;
6589
6590 case X86_SREG_SS:
6591 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6592 pGstSelReg->u32Limit = 0;
6593 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6594 break;
6595
6596 case X86_SREG_ES:
6597 case X86_SREG_DS:
6598 pGstSelReg->u64Base = 0;
6599 pGstSelReg->u32Limit = 0;
6600 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6601 break;
6602
6603 case X86_SREG_FS:
6604 case X86_SREG_GS:
6605 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6606 pGstSelReg->u32Limit = 0;
6607 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6608 break;
6609 }
6610 Assert(pGstSelReg->Attr.n.u1Unusable);
6611 }
6612 }
6613
6614 /* LDTR. */
6615 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6616 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6617 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6618 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6619 {
6620 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6621 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6622 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6623 }
6624 else
6625 {
6626 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6627 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6628 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6629 }
6630
6631 /* TR. */
6632 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6633 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6634 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6635 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6636 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6637 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6638 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6639
6640 /* GDTR. */
6641 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6642 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6643
6644 /* IDTR. */
6645 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6646 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6647}
6648
6649
6650/**
6651 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6652 *
6653 * @returns VBox status code.
6654 * @param pVCpu The cross context virtual CPU structure.
6655 * @param pszInstr The VMX instruction name (for logging purposes).
6656 */
6657IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6658{
6659 /*
6660 * Load guest MSRs.
6661 * See Intel spec. 26.4 "Loading MSRs".
6662 */
6663 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6664 const char *const pszFailure = "VM-exit";
6665
6666 /*
6667 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6668 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6669 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6670 */
6671 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6672 if (!cMsrs)
6673 return VINF_SUCCESS;
6674
6675 /*
6676 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6677 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6678 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6679 */
6680 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6681 if (fIsMsrCountValid)
6682 { /* likely */ }
6683 else
6684 {
6685 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6687 }
6688
6689 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6690 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6691 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6692 if (RT_SUCCESS(rc))
6693 {
6694 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6695 Assert(pMsr);
6696 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6697 {
6698 if ( !pMsr->u32Reserved
6699 && pMsr->u32Msr != MSR_K8_FS_BASE
6700 && pMsr->u32Msr != MSR_K8_GS_BASE
6701 && pMsr->u32Msr != MSR_K6_EFER
6702 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6703 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6704 {
6705 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6706 if (rcStrict == VINF_SUCCESS)
6707 continue;
6708
6709 /*
6710 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6711 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6712 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6713 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6714 * MSR in ring-0 if possible, or come up with a better, generic solution.
6715 */
6716 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6717 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6718 ? kVmxVDiag_Vmentry_MsrLoadRing3
6719 : kVmxVDiag_Vmentry_MsrLoad;
6720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6721 }
6722 else
6723 {
6724 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6725 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6726 }
6727 }
6728 }
6729 else
6730 {
6731 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6733 }
6734
6735 NOREF(pszInstr);
6736 NOREF(pszFailure);
6737 return VINF_SUCCESS;
6738}
6739
6740
6741/**
6742 * Loads the guest-state non-register state as part of VM-entry.
6743 *
6744 * @returns VBox status code.
6745 * @param pVCpu The cross context virtual CPU structure.
6746 *
6747 * @remarks This must be called only after loading the nested-guest register state
6748 * (especially nested-guest RIP).
6749 */
6750IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6751{
6752 /*
6753 * Load guest non-register state.
6754 * See Intel spec. 26.6 "Special Features of VM Entry"
6755 */
6756 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6757
6758 /*
6759 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6760 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6761 *
6762 * See Intel spec. 26.6.1 "Interruptibility State".
6763 */
6764 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6765 if ( !fEntryVectoring
6766 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6767 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6768 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6769 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6770
6771 /* NMI blocking. */
6772 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6773 {
6774 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6775 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6776 else
6777 {
6778 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6779 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6780 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6781 }
6782 }
6783 else
6784 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6785
6786 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6787
6788 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6789 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6790
6791 /* VPID is irrelevant. We don't support VPID yet. */
6792
6793 /* Clear address-range monitoring. */
6794 EMMonitorWaitClear(pVCpu);
6795}
6796
6797
6798/**
6799 * Loads the guest-state as part of VM-entry.
6800 *
6801 * @returns VBox status code.
6802 * @param pVCpu The cross context virtual CPU structure.
6803 * @param pszInstr The VMX instruction name (for logging purposes).
6804 *
6805 * @remarks This must be done after all the necessary steps prior to loading of
6806 * guest-state (e.g. checking various VMCS state).
6807 */
6808IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6809{
6810 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6811 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6812
6813 /*
6814 * Load guest RIP, RSP and RFLAGS.
6815 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6816 */
6817 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6818 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6819 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6820 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6821
6822 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6823 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6824 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6825
6826 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6827
6828 NOREF(pszInstr);
6829 return VINF_SUCCESS;
6830}
6831
6832
6833/**
6834 * Returns whether there are is a pending debug exception on VM-entry.
6835 *
6836 * @param pVCpu The cross context virtual CPU structure.
6837 * @param pszInstr The VMX instruction name (for logging purposes).
6838 */
6839IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6840{
6841 /*
6842 * Pending debug exceptions.
6843 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6844 */
6845 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6846 Assert(pVmcs);
6847
6848 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6849 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6850 if (fPendingDbgXcpt)
6851 {
6852 uint8_t uEntryIntInfoType;
6853 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6854 if (fEntryVectoring)
6855 {
6856 switch (uEntryIntInfoType)
6857 {
6858 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6859 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6860 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6861 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6862 fPendingDbgXcpt = false;
6863 break;
6864
6865 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6866 {
6867 /*
6868 * Whether the pending debug exception for software exceptions other than
6869 * #BP and #OF is delivered after injecting the exception or is discard
6870 * is CPU implementation specific. We will discard them (easier).
6871 */
6872 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6873 if ( uVector != X86_XCPT_BP
6874 && uVector != X86_XCPT_OF)
6875 fPendingDbgXcpt = false;
6876 RT_FALL_THRU();
6877 }
6878 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6879 {
6880 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6881 fPendingDbgXcpt = false;
6882 break;
6883 }
6884 }
6885 }
6886 else
6887 {
6888 /*
6889 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6890 * pending debug exception is held pending or is discarded is CPU implementation
6891 * specific. We will discard them (easier).
6892 */
6893 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6894 fPendingDbgXcpt = false;
6895
6896 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6897 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6898 fPendingDbgXcpt = false;
6899 }
6900 }
6901
6902 NOREF(pszInstr);
6903 return fPendingDbgXcpt;
6904}
6905
6906
6907/**
6908 * Set up the monitor-trap flag (MTF).
6909 *
6910 * @param pVCpu The cross context virtual CPU structure.
6911 * @param pszInstr The VMX instruction name (for logging purposes).
6912 */
6913IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
6914{
6915 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6916 Assert(pVmcs);
6917 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6918 {
6919 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6920 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6921 }
6922 else
6923 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6924 NOREF(pszInstr);
6925}
6926
6927
6928/**
6929 * Sets up NMI-window exiting.
6930 *
6931 * @param pVCpu The cross context virtual CPU structure.
6932 * @param pszInstr The VMX instruction name (for logging purposes).
6933 */
6934IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
6935{
6936 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6937 Assert(pVmcs);
6938 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6939 {
6940 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6941 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6942 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6943 }
6944 else
6945 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6946 NOREF(pszInstr);
6947}
6948
6949
6950/**
6951 * Sets up interrupt-window exiting.
6952 *
6953 * @param pVCpu The cross context virtual CPU structure.
6954 * @param pszInstr The VMX instruction name (for logging purposes).
6955 */
6956IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
6957{
6958 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6959 Assert(pVmcs);
6960 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6961 {
6962 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6963 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6964 }
6965 else
6966 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6967 NOREF(pszInstr);
6968}
6969
6970
6971/**
6972 * Set up the VMX-preemption timer.
6973 *
6974 * @param pVCpu The cross context virtual CPU structure.
6975 * @param pszInstr The VMX instruction name (for logging purposes).
6976 */
6977IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
6978{
6979 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6980 Assert(pVmcs);
6981 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6982 {
6983 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
6984 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
6985 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
6986
6987 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
6988 }
6989 else
6990 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
6991
6992 NOREF(pszInstr);
6993}
6994
6995
6996/**
6997 * Injects an event using TRPM given a VM-entry interruption info. and related
6998 * fields.
6999 *
7000 * @param pVCpu The cross context virtual CPU structure.
7001 * @param uEntryIntInfo The VM-entry interruption info.
7002 * @param uErrCode The error code associated with the event if any.
7003 * @param cbInstr The VM-entry instruction length (for software
7004 * interrupts and software exceptions). Pass 0
7005 * otherwise.
7006 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7007 */
7008IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7009 RTGCUINTPTR GCPtrFaultAddress)
7010{
7011 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7012 Assert(VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7013
7014 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7015 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7016
7017 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7018 AssertRC(rc);
7019
7020 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7021 TRPMSetErrorCode(pVCpu, uErrCode);
7022
7023 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7024 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7025 else
7026 {
7027 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7028 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7029 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7030 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7031 TRPMSetInstrLength(pVCpu, cbInstr);
7032 }
7033}
7034
7035
7036/**
7037 * Performs event injection (if any) as part of VM-entry.
7038 *
7039 * @param pVCpu The cross context virtual CPU structure.
7040 * @param pszInstr The VMX instruction name (for logging purposes).
7041 */
7042IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7043{
7044 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7045
7046 /*
7047 * Inject events.
7048 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7049 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7050 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7051 * the actually delivery of this event.
7052 *
7053 * See Intel spec. 26.5 "Event Injection".
7054 */
7055 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7056 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7057
7058 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7059 if (fEntryIntInfoValid)
7060 {
7061 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7062 {
7063 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7064 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7065 }
7066 else
7067 iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7068 pVCpu->cpum.GstCtx.cr2);
7069
7070 /*
7071 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7072 *
7073 * However, we do it here on VM-entry as well because while it isn't visible to guest
7074 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7075 * execution using hardware-assisted VT-x, it will not be try to inject the event again.
7076 *
7077 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7078 */
7079 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7080 }
7081 else
7082 {
7083 /*
7084 * Inject any pending guest debug exception.
7085 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7086 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7087 */
7088 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7089 if (fPendingDbgXcpt)
7090 {
7091 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7092 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7093 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7094 iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7095 0 /* GCPtrFaultAddress */);
7096 }
7097 }
7098
7099 NOREF(pszInstr);
7100}
7101
7102
7103/**
7104 * Initializes all read-only VMCS fields as part of VM-entry.
7105 *
7106 * @param pVCpu The cross context virtual CPU structure.
7107 */
7108IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7109{
7110 /*
7111 * Any VMCS field which we do not establish on every VM-exit but may potentially
7112 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7113 * specified to be undefined needs to be initialized here.
7114 *
7115 * Thus, it is especially important to clear the Exit qualification field
7116 * since it must be zero for VM-exits where it is not used. Similarly, the
7117 * VM-exit interruption information field's valid bit needs to be cleared for
7118 * the same reasons.
7119 */
7120 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7121 Assert(pVmcs);
7122
7123 /* 16-bit (none currently). */
7124 /* 32-bit. */
7125 pVmcs->u32RoVmInstrError = 0;
7126 pVmcs->u32RoExitReason = 0;
7127 pVmcs->u32RoExitIntInfo = 0;
7128 pVmcs->u32RoExitIntErrCode = 0;
7129 pVmcs->u32RoIdtVectoringInfo = 0;
7130 pVmcs->u32RoIdtVectoringErrCode = 0;
7131 pVmcs->u32RoExitInstrLen = 0;
7132 pVmcs->u32RoExitInstrInfo = 0;
7133
7134 /* 64-bit. */
7135 pVmcs->u64RoGuestPhysAddr.u = 0;
7136
7137 /* Natural-width. */
7138 pVmcs->u64RoExitQual.u = 0;
7139 pVmcs->u64RoIoRcx.u = 0;
7140 pVmcs->u64RoIoRsi.u = 0;
7141 pVmcs->u64RoIoRdi.u = 0;
7142 pVmcs->u64RoIoRip.u = 0;
7143 pVmcs->u64RoGuestLinearAddr.u = 0;
7144}
7145
7146
7147/**
7148 * VMLAUNCH/VMRESUME instruction execution worker.
7149 *
7150 * @returns Strict VBox status code.
7151 * @param pVCpu The cross context virtual CPU structure.
7152 * @param cbInstr The instruction length in bytes.
7153 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7154 * VMXINSTRID_VMRESUME).
7155 *
7156 * @remarks Common VMX instruction checks are already expected to by the caller,
7157 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7158 */
7159IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7160{
7161# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7162 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7163 return VINF_EM_RAW_EMULATE_INSTR;
7164# else
7165 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7166 || uInstrId == VMXINSTRID_VMRESUME);
7167 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7168
7169 /* Nested-guest intercept. */
7170 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7171 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7172
7173 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7174
7175 /*
7176 * Basic VM-entry checks.
7177 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7178 * The checks following that do not have to follow a specific order.
7179 *
7180 * See Intel spec. 26.1 "Basic VM-entry Checks".
7181 */
7182
7183 /* CPL. */
7184 if (pVCpu->iem.s.uCpl == 0)
7185 { /* likely */ }
7186 else
7187 {
7188 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7189 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7190 return iemRaiseGeneralProtectionFault0(pVCpu);
7191 }
7192
7193 /* Current VMCS valid. */
7194 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7195 { /* likely */ }
7196 else
7197 {
7198 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7199 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7200 iemVmxVmFailInvalid(pVCpu);
7201 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7202 return VINF_SUCCESS;
7203 }
7204
7205 /* Current VMCS is not a shadow VMCS. */
7206 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7207 { /* likely */ }
7208 else
7209 {
7210 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7211 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7212 iemVmxVmFailInvalid(pVCpu);
7213 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7214 return VINF_SUCCESS;
7215 }
7216
7217 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7218 * use block-by-STI here which is not quite correct. */
7219 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7220 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7221 { /* likely */ }
7222 else
7223 {
7224 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7225 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7226 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7227 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7228 return VINF_SUCCESS;
7229 }
7230
7231 if (uInstrId == VMXINSTRID_VMLAUNCH)
7232 {
7233 /* VMLAUNCH with non-clear VMCS. */
7234 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7235 { /* likely */ }
7236 else
7237 {
7238 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7239 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7240 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7241 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7242 return VINF_SUCCESS;
7243 }
7244 }
7245 else
7246 {
7247 /* VMRESUME with non-launched VMCS. */
7248 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7249 { /* likely */ }
7250 else
7251 {
7252 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7253 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7254 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7255 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7256 return VINF_SUCCESS;
7257 }
7258 }
7259
7260 /*
7261 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7262 * while entering VMX non-root mode. We do some of this while checking VM-execution
7263 * controls. The guest hypervisor should not make assumptions and cannot expect
7264 * predictable behavior if changes to these structures are made in guest memory while
7265 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7266 * modify them anyway as we cache them in host memory.
7267 *
7268 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7269 */
7270 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7271 Assert(pVmcs);
7272 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7273
7274 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7275 if (RT_SUCCESS(rc))
7276 {
7277 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7278 if (RT_SUCCESS(rc))
7279 {
7280 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7281 if (RT_SUCCESS(rc))
7282 {
7283 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7284 if (RT_SUCCESS(rc))
7285 {
7286 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7287 iemVmxVmentryInitReadOnlyFields(pVCpu);
7288
7289 /*
7290 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7291 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7292 * VM-exit when required.
7293 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7294 */
7295 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7296
7297 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7298 if (RT_SUCCESS(rc))
7299 {
7300 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7301 if (RT_SUCCESS(rc))
7302 {
7303 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7304 if (RT_SUCCESS(rc))
7305 {
7306 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7307
7308 /* VMLAUNCH instruction must update the VMCS launch state. */
7309 if (uInstrId == VMXINSTRID_VMLAUNCH)
7310 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7311
7312 /* Perform the VMX transition (PGM updates). */
7313 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7314 if (rcStrict == VINF_SUCCESS)
7315 { /* likely */ }
7316 else if (RT_SUCCESS(rcStrict))
7317 {
7318 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7319 VBOXSTRICTRC_VAL(rcStrict)));
7320 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7321 }
7322 else
7323 {
7324 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7325 return rcStrict;
7326 }
7327
7328 /* Paranoia. */
7329 Assert(rcStrict == VINF_SUCCESS);
7330
7331 /* We've now entered nested-guest execution. */
7332 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7333
7334 /*
7335 * The priority of potential VM-exits during VM-entry is important.
7336 * The priorities of VM-exits and events are listed from highest
7337 * to lowest as follows:
7338 *
7339 * 1. Event injection.
7340 * 2. Trap on task-switch (T flag set in TSS).
7341 * 3. TPR below threshold / APIC-write.
7342 * 4. SMI, INIT.
7343 * 5. MTF exit.
7344 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7345 * 7. VMX-preemption timer.
7346 * 9. NMI-window exit.
7347 * 10. NMI injection.
7348 * 11. Interrupt-window exit.
7349 * 12. Virtual-interrupt injection.
7350 * 13. Interrupt injection.
7351 * 14. Process next instruction (fetch, decode, execute).
7352 */
7353
7354 /* Setup VMX-preemption timer. */
7355 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7356
7357 /* Setup monitor-trap flag. */
7358 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7359
7360 /* Setup NMI-window exiting. */
7361 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7362
7363 /* Setup interrupt-window exiting. */
7364 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7365
7366 /*
7367 * Inject any event that the guest hypervisor wants to inject.
7368 * Note! We cannot immediately perform the event injection here as we may have
7369 * pending PGM operations to perform due to switching page tables and/or
7370 * mode.
7371 */
7372 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7373
7374# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7375 /* Reschedule to IEM-only execution of the nested-guest. */
7376 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7377 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7378 if (rcSched != VINF_SUCCESS)
7379 iemSetPassUpStatus(pVCpu, rcSched);
7380# endif
7381
7382 /* Finally, done. */
7383 Log(("%s: cs:rip=%#04x:%#RX64\n", pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7384 return VINF_SUCCESS;
7385 }
7386 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7387 pVmcs->u64RoExitQual.u);
7388 }
7389 }
7390 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7391 pVmcs->u64RoExitQual.u);
7392 }
7393
7394 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7395 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7396 return VINF_SUCCESS;
7397 }
7398 }
7399 }
7400
7401 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7402 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7403 return VINF_SUCCESS;
7404# endif
7405}
7406
7407
7408/**
7409 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7410 * (causes a VM-exit) or not.
7411 *
7412 * @returns @c true if the instruction is intercepted, @c false otherwise.
7413 * @param pVCpu The cross context virtual CPU structure.
7414 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7415 * VMX_EXIT_WRMSR).
7416 * @param idMsr The MSR.
7417 */
7418IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7419{
7420 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7421 Assert( uExitReason == VMX_EXIT_RDMSR
7422 || uExitReason == VMX_EXIT_WRMSR);
7423
7424 /* Consult the MSR bitmap if the feature is supported. */
7425 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7426 Assert(pVmcs);
7427 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7428 {
7429 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7430 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7431 if (uExitReason == VMX_EXIT_RDMSR)
7432 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7433 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7434 }
7435
7436 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7437 return true;
7438}
7439
7440
7441/**
7442 * VMREAD instruction execution worker that does not perform any validation checks.
7443 *
7444 * Callers are expected to have performed the necessary checks and to ensure the
7445 * VMREAD will succeed.
7446 *
7447 * @param pVmcs Pointer to the virtual VMCS.
7448 * @param pu64Dst Where to write the VMCS value.
7449 * @param u64VmcsField The VMCS field.
7450 *
7451 * @remarks May be called with interrupts disabled.
7452 */
7453IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7454{
7455 VMXVMCSFIELD VmcsField;
7456 VmcsField.u = u64VmcsField;
7457 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7458 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7459 uint8_t const uWidthType = (uWidth << 2) | uType;
7460 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7461 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7462 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7463 Assert(offField < VMX_V_VMCS_SIZE);
7464 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7465
7466 /*
7467 * Read the VMCS component based on the field's effective width.
7468 *
7469 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7470 * indicates high bits (little endian).
7471 *
7472 * Note! The caller is responsible to trim the result and update registers
7473 * or memory locations are required. Here we just zero-extend to the largest
7474 * type (i.e. 64-bits).
7475 */
7476 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7477 uint8_t const *pbField = pbVmcs + offField;
7478 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7479 switch (uEffWidth)
7480 {
7481 case VMX_VMCSFIELD_WIDTH_64BIT:
7482 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7483 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7484 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7485 }
7486}
7487
7488
7489/**
7490 * VMREAD common (memory/register) instruction execution worker.
7491 *
7492 * @returns Strict VBox status code.
7493 * @param pVCpu The cross context virtual CPU structure.
7494 * @param cbInstr The instruction length in bytes.
7495 * @param pu64Dst Where to write the VMCS value (only updated when
7496 * VINF_SUCCESS is returned).
7497 * @param u64VmcsField The VMCS field.
7498 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7499 * NULL.
7500 */
7501IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7502 PCVMXVEXITINFO pExitInfo)
7503{
7504 /* Nested-guest intercept. */
7505 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7506 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7507 {
7508 if (pExitInfo)
7509 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7510 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7511 }
7512
7513 /* CPL. */
7514 if (pVCpu->iem.s.uCpl == 0)
7515 { /* likely */ }
7516 else
7517 {
7518 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7519 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7520 return iemRaiseGeneralProtectionFault0(pVCpu);
7521 }
7522
7523 /* VMCS pointer in root mode. */
7524 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7525 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7526 { /* likely */ }
7527 else
7528 {
7529 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7530 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7531 iemVmxVmFailInvalid(pVCpu);
7532 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7533 return VINF_SUCCESS;
7534 }
7535
7536 /* VMCS-link pointer in non-root mode. */
7537 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7538 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7539 { /* likely */ }
7540 else
7541 {
7542 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7543 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7544 iemVmxVmFailInvalid(pVCpu);
7545 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7546 return VINF_SUCCESS;
7547 }
7548
7549 /* Supported VMCS field. */
7550 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7551 { /* likely */ }
7552 else
7553 {
7554 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7555 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7556 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7557 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7558 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7559 return VINF_SUCCESS;
7560 }
7561
7562 /*
7563 * Reading from the current or shadow VMCS.
7564 */
7565 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7566 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7567 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7568 Assert(pVmcs);
7569 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7570 return VINF_SUCCESS;
7571}
7572
7573
7574/**
7575 * VMREAD (64-bit register) instruction execution worker.
7576 *
7577 * @returns Strict VBox status code.
7578 * @param pVCpu The cross context virtual CPU structure.
7579 * @param cbInstr The instruction length in bytes.
7580 * @param pu64Dst Where to store the VMCS field's value.
7581 * @param u64VmcsField The VMCS field.
7582 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7583 * NULL.
7584 */
7585IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7586 PCVMXVEXITINFO pExitInfo)
7587{
7588 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7589 if (rcStrict == VINF_SUCCESS)
7590 {
7591 iemVmxVmreadSuccess(pVCpu, cbInstr);
7592 return VINF_SUCCESS;
7593 }
7594
7595 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7596 return rcStrict;
7597}
7598
7599
7600/**
7601 * VMREAD (32-bit register) instruction execution worker.
7602 *
7603 * @returns Strict VBox status code.
7604 * @param pVCpu The cross context virtual CPU structure.
7605 * @param cbInstr The instruction length in bytes.
7606 * @param pu32Dst Where to store the VMCS field's value.
7607 * @param u32VmcsField The VMCS field.
7608 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7609 * NULL.
7610 */
7611IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7612 PCVMXVEXITINFO pExitInfo)
7613{
7614 uint64_t u64Dst;
7615 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7616 if (rcStrict == VINF_SUCCESS)
7617 {
7618 *pu32Dst = u64Dst;
7619 iemVmxVmreadSuccess(pVCpu, cbInstr);
7620 return VINF_SUCCESS;
7621 }
7622
7623 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7624 return rcStrict;
7625}
7626
7627
7628/**
7629 * VMREAD (memory) instruction execution worker.
7630 *
7631 * @returns Strict VBox status code.
7632 * @param pVCpu The cross context virtual CPU structure.
7633 * @param cbInstr The instruction length in bytes.
7634 * @param iEffSeg The effective segment register to use with @a u64Val.
7635 * Pass UINT8_MAX if it is a register access.
7636 * @param GCPtrDst The guest linear address to store the VMCS field's
7637 * value.
7638 * @param u64VmcsField The VMCS field.
7639 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7640 * NULL.
7641 */
7642IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7643 PCVMXVEXITINFO pExitInfo)
7644{
7645 uint64_t u64Dst;
7646 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7647 if (rcStrict == VINF_SUCCESS)
7648 {
7649 /*
7650 * Write the VMCS field's value to the location specified in guest-memory.
7651 */
7652 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7653 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7654 else
7655 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7656 if (rcStrict == VINF_SUCCESS)
7657 {
7658 iemVmxVmreadSuccess(pVCpu, cbInstr);
7659 return VINF_SUCCESS;
7660 }
7661
7662 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7663 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7664 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7665 return rcStrict;
7666 }
7667
7668 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7669 return rcStrict;
7670}
7671
7672
7673/**
7674 * VMWRITE instruction execution worker that does not perform any validation
7675 * checks.
7676 *
7677 * Callers are expected to have performed the necessary checks and to ensure the
7678 * VMWRITE will succeed.
7679 *
7680 * @param pVmcs Pointer to the virtual VMCS.
7681 * @param u64Val The value to write.
7682 * @param u64VmcsField The VMCS field.
7683 *
7684 * @remarks May be called with interrupts disabled.
7685 */
7686IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7687{
7688 VMXVMCSFIELD VmcsField;
7689 VmcsField.u = u64VmcsField;
7690 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7691 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7692 uint8_t const uWidthType = (uWidth << 2) | uType;
7693 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7694 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7695 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7696 Assert(offField < VMX_V_VMCS_SIZE);
7697 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7698
7699 /*
7700 * Write the VMCS component based on the field's effective width.
7701 *
7702 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7703 * indicates high bits (little endian).
7704 */
7705 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7706 uint8_t *pbField = pbVmcs + offField;
7707 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7708 switch (uEffWidth)
7709 {
7710 case VMX_VMCSFIELD_WIDTH_64BIT:
7711 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7712 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7713 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7714 }
7715}
7716
7717
7718/**
7719 * VMWRITE instruction execution worker.
7720 *
7721 * @returns Strict VBox status code.
7722 * @param pVCpu The cross context virtual CPU structure.
7723 * @param cbInstr The instruction length in bytes.
7724 * @param iEffSeg The effective segment register to use with @a u64Val.
7725 * Pass UINT8_MAX if it is a register access.
7726 * @param u64Val The value to write (or guest linear address to the
7727 * value), @a iEffSeg will indicate if it's a memory
7728 * operand.
7729 * @param u64VmcsField The VMCS field.
7730 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7731 * NULL.
7732 */
7733IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7734 PCVMXVEXITINFO pExitInfo)
7735{
7736 /* Nested-guest intercept. */
7737 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7738 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7739 {
7740 if (pExitInfo)
7741 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7742 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7743 }
7744
7745 /* CPL. */
7746 if (pVCpu->iem.s.uCpl == 0)
7747 { /* likely */ }
7748 else
7749 {
7750 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7751 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7752 return iemRaiseGeneralProtectionFault0(pVCpu);
7753 }
7754
7755 /* VMCS pointer in root mode. */
7756 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7757 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7758 { /* likely */ }
7759 else
7760 {
7761 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7762 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7763 iemVmxVmFailInvalid(pVCpu);
7764 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7765 return VINF_SUCCESS;
7766 }
7767
7768 /* VMCS-link pointer in non-root mode. */
7769 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7770 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7771 { /* likely */ }
7772 else
7773 {
7774 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7775 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7776 iemVmxVmFailInvalid(pVCpu);
7777 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7778 return VINF_SUCCESS;
7779 }
7780
7781 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7782 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7783 if (!fIsRegOperand)
7784 {
7785 /* Read the value from the specified guest memory location. */
7786 VBOXSTRICTRC rcStrict;
7787 RTGCPTR const GCPtrVal = u64Val;
7788 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7789 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7790 else
7791 {
7792 uint32_t u32Val;
7793 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7794 u64Val = u32Val;
7795 }
7796 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7797 {
7798 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7799 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7800 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7801 return rcStrict;
7802 }
7803 }
7804 else
7805 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7806
7807 /* Supported VMCS field. */
7808 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7809 { /* likely */ }
7810 else
7811 {
7812 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7813 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7814 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7815 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7816 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7817 return VINF_SUCCESS;
7818 }
7819
7820 /* Read-only VMCS field. */
7821 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7822 if ( !fIsFieldReadOnly
7823 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7824 { /* likely */ }
7825 else
7826 {
7827 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7828 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7829 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7830 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7831 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7832 return VINF_SUCCESS;
7833 }
7834
7835 /*
7836 * Write to the current or shadow VMCS.
7837 */
7838 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7839 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7840 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7841 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7842 Assert(pVmcs);
7843 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7844
7845 /* Notify HM that the VMCS content might have changed. */
7846 if (!fInVmxNonRootMode)
7847 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7848
7849 iemVmxVmSucceed(pVCpu);
7850 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7851 return VINF_SUCCESS;
7852}
7853
7854
7855/**
7856 * VMCLEAR instruction execution worker.
7857 *
7858 * @returns Strict VBox status code.
7859 * @param pVCpu The cross context virtual CPU structure.
7860 * @param cbInstr The instruction length in bytes.
7861 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7862 * @param GCPtrVmcs The linear address of the VMCS pointer.
7863 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7864 *
7865 * @remarks Common VMX instruction checks are already expected to by the caller,
7866 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7867 */
7868IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7869 PCVMXVEXITINFO pExitInfo)
7870{
7871 /* Nested-guest intercept. */
7872 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7873 {
7874 if (pExitInfo)
7875 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7876 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7877 }
7878
7879 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7880
7881 /* CPL. */
7882 if (pVCpu->iem.s.uCpl == 0)
7883 { /* likely */ }
7884 else
7885 {
7886 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7887 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7888 return iemRaiseGeneralProtectionFault0(pVCpu);
7889 }
7890
7891 /* Get the VMCS pointer from the location specified by the source memory operand. */
7892 RTGCPHYS GCPhysVmcs;
7893 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7894 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7895 { /* likely */ }
7896 else
7897 {
7898 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7899 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7900 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
7901 return rcStrict;
7902 }
7903
7904 /* VMCS pointer alignment. */
7905 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7906 { /* likely */ }
7907 else
7908 {
7909 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7910 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7911 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7912 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7914 return VINF_SUCCESS;
7915 }
7916
7917 /* VMCS physical-address width limits. */
7918 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7919 { /* likely */ }
7920 else
7921 {
7922 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7923 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7924 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7925 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7926 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7927 return VINF_SUCCESS;
7928 }
7929
7930 /* VMCS is not the VMXON region. */
7931 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7932 { /* likely */ }
7933 else
7934 {
7935 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7936 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7937 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7938 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7939 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7940 return VINF_SUCCESS;
7941 }
7942
7943 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7944 restriction imposed by our implementation. */
7945 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7946 { /* likely */ }
7947 else
7948 {
7949 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7950 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7951 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7952 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7953 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7954 return VINF_SUCCESS;
7955 }
7956
7957 /*
7958 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7959 *
7960 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7961 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7962 * to 'clear'.
7963 */
7964 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7965 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7966 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7967 {
7968 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
7969 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
7970 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7971 }
7972 else
7973 {
7974 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
7975 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
7976 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
7977 if (RT_FAILURE(rcStrict))
7978 return rcStrict;
7979 }
7980
7981 iemVmxVmSucceed(pVCpu);
7982 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7983 return VINF_SUCCESS;
7984}
7985
7986
7987/**
7988 * VMPTRST instruction execution worker.
7989 *
7990 * @returns Strict VBox status code.
7991 * @param pVCpu The cross context virtual CPU structure.
7992 * @param cbInstr The instruction length in bytes.
7993 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7994 * @param GCPtrVmcs The linear address of where to store the current VMCS
7995 * pointer.
7996 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7997 *
7998 * @remarks Common VMX instruction checks are already expected to by the caller,
7999 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8000 */
8001IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8002 PCVMXVEXITINFO pExitInfo)
8003{
8004 /* Nested-guest intercept. */
8005 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8006 {
8007 if (pExitInfo)
8008 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8009 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8010 }
8011
8012 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8013
8014 /* CPL. */
8015 if (pVCpu->iem.s.uCpl == 0)
8016 { /* likely */ }
8017 else
8018 {
8019 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8020 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8021 return iemRaiseGeneralProtectionFault0(pVCpu);
8022 }
8023
8024 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8025 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8026 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8027 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8028 {
8029 iemVmxVmSucceed(pVCpu);
8030 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8031 return rcStrict;
8032 }
8033
8034 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8035 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8036 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8037 return rcStrict;
8038}
8039
8040
8041/**
8042 * VMPTRLD instruction execution worker.
8043 *
8044 * @returns Strict VBox status code.
8045 * @param pVCpu The cross context virtual CPU structure.
8046 * @param cbInstr The instruction length in bytes.
8047 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8048 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8049 *
8050 * @remarks Common VMX instruction checks are already expected to by the caller,
8051 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8052 */
8053IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8054 PCVMXVEXITINFO pExitInfo)
8055{
8056 /* Nested-guest intercept. */
8057 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8058 {
8059 if (pExitInfo)
8060 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8061 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8062 }
8063
8064 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8065
8066 /* CPL. */
8067 if (pVCpu->iem.s.uCpl == 0)
8068 { /* likely */ }
8069 else
8070 {
8071 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8072 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8073 return iemRaiseGeneralProtectionFault0(pVCpu);
8074 }
8075
8076 /* Get the VMCS pointer from the location specified by the source memory operand. */
8077 RTGCPHYS GCPhysVmcs;
8078 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8079 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8080 { /* likely */ }
8081 else
8082 {
8083 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8085 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8086 return rcStrict;
8087 }
8088
8089 /* VMCS pointer alignment. */
8090 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8091 { /* likely */ }
8092 else
8093 {
8094 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8095 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8096 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8097 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8098 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8099 return VINF_SUCCESS;
8100 }
8101
8102 /* VMCS physical-address width limits. */
8103 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8104 { /* likely */ }
8105 else
8106 {
8107 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8108 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8109 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8110 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8111 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8112 return VINF_SUCCESS;
8113 }
8114
8115 /* VMCS is not the VMXON region. */
8116 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8117 { /* likely */ }
8118 else
8119 {
8120 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8121 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8122 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8123 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8124 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8125 return VINF_SUCCESS;
8126 }
8127
8128 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8129 restriction imposed by our implementation. */
8130 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8131 { /* likely */ }
8132 else
8133 {
8134 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8135 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8136 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8137 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8138 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8139 return VINF_SUCCESS;
8140 }
8141
8142 /* Read just the VMCS revision from the VMCS. */
8143 VMXVMCSREVID VmcsRevId;
8144 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8145 if (RT_SUCCESS(rc))
8146 { /* likely */ }
8147 else
8148 {
8149 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8150 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8151 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8152 return rc;
8153 }
8154
8155 /*
8156 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8157 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8158 */
8159 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8160 && ( !VmcsRevId.n.fIsShadowVmcs
8161 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8162 { /* likely */ }
8163 else
8164 {
8165 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8166 {
8167 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8168 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8169 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8170 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8171 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8172 return VINF_SUCCESS;
8173 }
8174
8175 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8176 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8177 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8178 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8179 return VINF_SUCCESS;
8180 }
8181
8182 /*
8183 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8184 * the cache of an existing, current VMCS back to guest memory before loading a new,
8185 * different current VMCS.
8186 */
8187 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8188 {
8189 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8190 {
8191 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8192 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8193 }
8194
8195 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8196 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8197 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8198 if (RT_SUCCESS(rc))
8199 {
8200 /* Notify HM that a new, current VMCS is loaded. */
8201 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8202 }
8203 else
8204 {
8205 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8206 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8207 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8208 return rc;
8209 }
8210 }
8211
8212 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8213 iemVmxVmSucceed(pVCpu);
8214 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8215 return VINF_SUCCESS;
8216}
8217
8218
8219/**
8220 * INVVPID instruction execution worker.
8221 *
8222 * @returns Strict VBox status code.
8223 * @param pVCpu The cross context virtual CPU structure.
8224 * @param cbInstr The instruction length in bytes.
8225 * @param iEffSeg The segment of the invvpid descriptor.
8226 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8227 * @param u64InvvpidType The invalidation type.
8228 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8229 * NULL.
8230 *
8231 * @remarks Common VMX instruction checks are already expected to by the caller,
8232 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8233 */
8234IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8235 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8236{
8237 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8238 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8239 return iemRaiseUndefinedOpcode(pVCpu);
8240
8241 /* Nested-guest intercept. */
8242 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8243 {
8244 if (pExitInfo)
8245 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8246 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8247 }
8248
8249 /* CPL. */
8250 if (pVCpu->iem.s.uCpl != 0)
8251 {
8252 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8253 return iemRaiseGeneralProtectionFault0(pVCpu);
8254 }
8255
8256 /*
8257 * Validate INVVPID invalidation type.
8258 *
8259 * The instruction specifies exactly ONE of the supported invalidation types.
8260 *
8261 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8262 * supported. In theory, it's possible for a CPU to not support flushing individual
8263 * addresses but all the other types or any other combination. We do not take any
8264 * shortcuts here by assuming the types we currently expose to the guest.
8265 */
8266 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8267 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8268 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8269 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8270 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8271 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8272 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8273 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8274 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8275 { /* likely */ }
8276 else
8277 {
8278 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8279 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8280 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8281 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8282 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8283 return VINF_SUCCESS;
8284 }
8285
8286 /*
8287 * Fetch the invvpid descriptor from guest memory.
8288 */
8289 RTUINT128U uDesc;
8290 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8291 if (rcStrict == VINF_SUCCESS)
8292 {
8293 /*
8294 * Validate the descriptor.
8295 */
8296 if (uDesc.s.Lo > 0xfff)
8297 {
8298 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8299 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8300 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8301 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8302 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8303 return VINF_SUCCESS;
8304 }
8305
8306 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8307 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8308 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8309 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8310 switch (u64InvvpidType)
8311 {
8312 case VMXTLBFLUSHVPID_INDIV_ADDR:
8313 {
8314 if (uVpid != 0)
8315 {
8316 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8317 {
8318 /* Invalidate mappings for the linear address tagged with VPID. */
8319 /** @todo PGM support for VPID? Currently just flush everything. */
8320 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8321 iemVmxVmSucceed(pVCpu);
8322 }
8323 else
8324 {
8325 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8326 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8327 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8328 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8329 }
8330 }
8331 else
8332 {
8333 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8334 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8335 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8336 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8337 }
8338 break;
8339 }
8340
8341 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8342 {
8343 if (uVpid != 0)
8344 {
8345 /* Invalidate all mappings with VPID. */
8346 /** @todo PGM support for VPID? Currently just flush everything. */
8347 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8348 iemVmxVmSucceed(pVCpu);
8349 }
8350 else
8351 {
8352 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8353 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8354 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8355 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8356 }
8357 break;
8358 }
8359
8360 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8361 {
8362 /* Invalidate all mappings with non-zero VPIDs. */
8363 /** @todo PGM support for VPID? Currently just flush everything. */
8364 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8365 iemVmxVmSucceed(pVCpu);
8366 break;
8367 }
8368
8369 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8370 {
8371 if (uVpid != 0)
8372 {
8373 /* Invalidate all mappings with VPID except global translations. */
8374 /** @todo PGM support for VPID? Currently just flush everything. */
8375 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8376 iemVmxVmSucceed(pVCpu);
8377 }
8378 else
8379 {
8380 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8381 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8382 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8383 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8384 }
8385 break;
8386 }
8387 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8388 }
8389 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8390 }
8391 return rcStrict;
8392}
8393
8394
8395/**
8396 * VMXON instruction execution worker.
8397 *
8398 * @returns Strict VBox status code.
8399 * @param pVCpu The cross context virtual CPU structure.
8400 * @param cbInstr The instruction length in bytes.
8401 * @param iEffSeg The effective segment register to use with @a
8402 * GCPtrVmxon.
8403 * @param GCPtrVmxon The linear address of the VMXON pointer.
8404 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8405 *
8406 * @remarks Common VMX instruction checks are already expected to by the caller,
8407 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8408 */
8409IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8410 PCVMXVEXITINFO pExitInfo)
8411{
8412 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8413 {
8414 /* CPL. */
8415 if (pVCpu->iem.s.uCpl == 0)
8416 { /* likely */ }
8417 else
8418 {
8419 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8420 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8421 return iemRaiseGeneralProtectionFault0(pVCpu);
8422 }
8423
8424 /* A20M (A20 Masked) mode. */
8425 if (PGMPhysIsA20Enabled(pVCpu))
8426 { /* likely */ }
8427 else
8428 {
8429 Log(("vmxon: A20M mode -> #GP(0)\n"));
8430 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8431 return iemRaiseGeneralProtectionFault0(pVCpu);
8432 }
8433
8434 /* CR0. */
8435 {
8436 /* CR0 MB1 bits. */
8437 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8438 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8439 { /* likely */ }
8440 else
8441 {
8442 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8443 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8444 return iemRaiseGeneralProtectionFault0(pVCpu);
8445 }
8446
8447 /* CR0 MBZ bits. */
8448 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8449 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8450 { /* likely */ }
8451 else
8452 {
8453 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8454 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8455 return iemRaiseGeneralProtectionFault0(pVCpu);
8456 }
8457 }
8458
8459 /* CR4. */
8460 {
8461 /* CR4 MB1 bits. */
8462 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8463 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8464 { /* likely */ }
8465 else
8466 {
8467 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8469 return iemRaiseGeneralProtectionFault0(pVCpu);
8470 }
8471
8472 /* CR4 MBZ bits. */
8473 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8474 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8475 { /* likely */ }
8476 else
8477 {
8478 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8479 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8480 return iemRaiseGeneralProtectionFault0(pVCpu);
8481 }
8482 }
8483
8484 /* Feature control MSR's LOCK and VMXON bits. */
8485 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8486 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8487 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8488 { /* likely */ }
8489 else
8490 {
8491 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8492 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8493 return iemRaiseGeneralProtectionFault0(pVCpu);
8494 }
8495
8496 /* Get the VMXON pointer from the location specified by the source memory operand. */
8497 RTGCPHYS GCPhysVmxon;
8498 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8499 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8500 { /* likely */ }
8501 else
8502 {
8503 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8504 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8505 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8506 return rcStrict;
8507 }
8508
8509 /* VMXON region pointer alignment. */
8510 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8511 { /* likely */ }
8512 else
8513 {
8514 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8515 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8516 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8517 iemVmxVmFailInvalid(pVCpu);
8518 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8519 return VINF_SUCCESS;
8520 }
8521
8522 /* VMXON physical-address width limits. */
8523 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8524 { /* likely */ }
8525 else
8526 {
8527 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8528 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8529 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8530 iemVmxVmFailInvalid(pVCpu);
8531 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8532 return VINF_SUCCESS;
8533 }
8534
8535 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8536 restriction imposed by our implementation. */
8537 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8538 { /* likely */ }
8539 else
8540 {
8541 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8542 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8543 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8544 iemVmxVmFailInvalid(pVCpu);
8545 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8546 return VINF_SUCCESS;
8547 }
8548
8549 /* Read the VMCS revision ID from the VMXON region. */
8550 VMXVMCSREVID VmcsRevId;
8551 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8552 if (RT_SUCCESS(rc))
8553 { /* likely */ }
8554 else
8555 {
8556 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8557 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8558 return rc;
8559 }
8560
8561 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8562 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8563 { /* likely */ }
8564 else
8565 {
8566 /* Revision ID mismatch. */
8567 if (!VmcsRevId.n.fIsShadowVmcs)
8568 {
8569 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8570 VmcsRevId.n.u31RevisionId));
8571 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8572 iemVmxVmFailInvalid(pVCpu);
8573 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8574 return VINF_SUCCESS;
8575 }
8576
8577 /* Shadow VMCS disallowed. */
8578 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8579 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8580 iemVmxVmFailInvalid(pVCpu);
8581 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8582 return VINF_SUCCESS;
8583 }
8584
8585 /*
8586 * Record that we're in VMX operation, block INIT, block and disable A20M.
8587 */
8588 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8589 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8590 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8591
8592 /* Clear address-range monitoring. */
8593 EMMonitorWaitClear(pVCpu);
8594 /** @todo NSTVMX: Intel PT. */
8595
8596 iemVmxVmSucceed(pVCpu);
8597 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8598 return VINF_SUCCESS;
8599 }
8600 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8601 {
8602 /* Nested-guest intercept. */
8603 if (pExitInfo)
8604 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8605 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8606 }
8607
8608 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8609
8610 /* CPL. */
8611 if (pVCpu->iem.s.uCpl > 0)
8612 {
8613 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8614 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8615 return iemRaiseGeneralProtectionFault0(pVCpu);
8616 }
8617
8618 /* VMXON when already in VMX root mode. */
8619 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8621 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8622 return VINF_SUCCESS;
8623}
8624
8625
8626/**
8627 * Implements 'VMXOFF'.
8628 *
8629 * @remarks Common VMX instruction checks are already expected to by the caller,
8630 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8631 */
8632IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8633{
8634 /* Nested-guest intercept. */
8635 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8636 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8637
8638 /* CPL. */
8639 if (pVCpu->iem.s.uCpl == 0)
8640 { /* likely */ }
8641 else
8642 {
8643 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8644 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8645 return iemRaiseGeneralProtectionFault0(pVCpu);
8646 }
8647
8648 /* Dual monitor treatment of SMIs and SMM. */
8649 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8650 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8651 { /* likely */ }
8652 else
8653 {
8654 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8655 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8656 return VINF_SUCCESS;
8657 }
8658
8659 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8660 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8661 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8662
8663 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8664 { /** @todo NSTVMX: Unblock SMI. */ }
8665
8666 EMMonitorWaitClear(pVCpu);
8667 /** @todo NSTVMX: Unblock and enable A20M. */
8668
8669 iemVmxVmSucceed(pVCpu);
8670 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8671 return VINF_SUCCESS;
8672}
8673
8674
8675/**
8676 * Implements 'VMXON'.
8677 */
8678IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8679{
8680 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8681}
8682
8683
8684/**
8685 * Implements 'VMLAUNCH'.
8686 */
8687IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8688{
8689 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8690}
8691
8692
8693/**
8694 * Implements 'VMRESUME'.
8695 */
8696IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8697{
8698 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8699}
8700
8701
8702/**
8703 * Implements 'VMPTRLD'.
8704 */
8705IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8706{
8707 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8708}
8709
8710
8711/**
8712 * Implements 'VMPTRST'.
8713 */
8714IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8715{
8716 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8717}
8718
8719
8720/**
8721 * Implements 'VMCLEAR'.
8722 */
8723IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8724{
8725 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8726}
8727
8728
8729/**
8730 * Implements 'VMWRITE' register.
8731 */
8732IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8733{
8734 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8735}
8736
8737
8738/**
8739 * Implements 'VMWRITE' memory.
8740 */
8741IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8742{
8743 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8744}
8745
8746
8747/**
8748 * Implements 'VMREAD' register (64-bit).
8749 */
8750IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8751{
8752 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8753}
8754
8755
8756/**
8757 * Implements 'VMREAD' register (32-bit).
8758 */
8759IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8760{
8761 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8762}
8763
8764
8765/**
8766 * Implements 'VMREAD' memory, 64-bit register.
8767 */
8768IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8769{
8770 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8771}
8772
8773
8774/**
8775 * Implements 'VMREAD' memory, 32-bit register.
8776 */
8777IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8778{
8779 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8780}
8781
8782
8783/**
8784 * Implements 'INVVPID'.
8785 */
8786IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8787{
8788 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8789}
8790
8791
8792/**
8793 * Implements VMX's implementation of PAUSE.
8794 */
8795IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8796{
8797 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8798 {
8799 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8800 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8801 return rcStrict;
8802 }
8803
8804 /*
8805 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8806 * a VM-exit, the instruction operates normally.
8807 */
8808 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8809 return VINF_SUCCESS;
8810}
8811
8812#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8813
8814
8815/**
8816 * Implements 'VMCALL'.
8817 */
8818IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8819{
8820#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8821 /* Nested-guest intercept. */
8822 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8823 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8824#endif
8825
8826 /* Join forces with vmmcall. */
8827 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8828}
8829
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