HMVMXAll.cpp@ 76553

最後變更在這個檔案從76553是 76553,由 vboxsync 提交於 6 年前
scm --update-copyright-year
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
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行
1	/* $Id: HMVMXAll.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/err.h>
28
29
30	/*********************************************************************************************************************************
31	* Global Variables *
32	*********************************************************************************************************************************/
33	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
34	/** VMX virtual-instructions and VM-exit diagnostics. */
35	static const char * const g_apszVmxVDiagDesc[] =
36	{
37	/* Internal processing errors. */
38	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
39	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
54	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
55	/* VMXON. */
56	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
75	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
76	/* VMXOFF. */
77	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
82	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
83	/* VMPTRLD. */
84	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
95	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
96	/* VMPTRST. */
97	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
98	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
101	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
102	/* VMCLEAR. */
103	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
104	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
112	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
113	/* VMWRITE. */
114	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
115	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
122	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
123	/* VMREAD. */
124	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
125	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
131	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
132	/* VMLAUNCH/VMRESUME. */
133	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
134	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic" ),
135	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessHandlerReg , "AddrApicAccessHandlerReg" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
144	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
145	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
146	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
153	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys , "GuestPdpteCr3ReadPhys" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte0Rsvd , "GuestPdpte0Rsvd" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte1Rsvd , "GuestPdpte1Rsvd" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte2Rsvd , "GuestPdpte2Rsvd" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte3Rsvd , "GuestPdpte3Rsvd" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrReadPhys , "PtrReadPhys" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys , "HostPdpteCr3ReadPhys" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte0Rsvd , "HostPdpte0Rsvd" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte1Rsvd , "HostPdpte1Rsvd" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte2Rsvd , "HostPdpte2Rsvd" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte3Rsvd , "HostPdpte3Rsvd" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
357	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
358	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
359	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" )
360	/* kVmxVDiag_End */
361	};
362	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
363	#undef VMXV_DIAG_DESC
364
365
366	/**
367	* Gets the descriptive name of a VMX instruction/VM-exit diagnostic code.
368	*
369	* @returns The descriptive string.
370	* @param enmDiag The VMX diagnostic.
371	*/
372	VMM_INT_DECL(const char *) HMVmxGetDiagDesc(VMXVDIAG enmDiag)
373	{
374	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
375	return g_apszVmxVDiagDesc[enmDiag];
376	return "Unknown/invalid";
377	}
378
379
380	/**
381	* Gets the description for a VMX abort reason.
382	*
383	* @returns The descriptive string.
384	* @param enmAbort The VMX abort reason.
385	*/
386	VMM_INT_DECL(const char *) HMVmxGetAbortDesc(VMXABORT enmAbort)
387	{
388	switch (enmAbort)
389	{
390	case VMXABORT_NONE: return "VMXABORT_NONE";
391	case VMXABORT_SAVE_GUEST_MSRS: return "VMXABORT_SAVE_GUEST_MSRS";
392	case VMXBOART_HOST_PDPTE: return "VMXBOART_HOST_PDPTE";
393	case VMXABORT_CURRENT_VMCS_CORRUPT: return "VMXABORT_CURRENT_VMCS_CORRUPT";
394	case VMXABORT_LOAD_HOST_MSR: return "VMXABORT_LOAD_HOST_MSR";
395	case VMXABORT_MACHINE_CHECK_XCPT: return "VMXABORT_MACHINE_CHECK_XCPT";
396	case VMXABORT_HOST_NOT_IN_LONG_MODE: return "VMXABORT_HOST_NOT_IN_LONG_MODE";
397	default:
398	break;
399	}
400	return "Unknown/invalid";
401	}
402
403
404	/**
405	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
406	* VMX when unrestricted execution isn't available.
407	*
408	* @returns true if selector is suitable for VMX, otherwise
409	* false.
410	* @param pSel Pointer to the selector to check (CS).
411	* @param uStackDpl The CPL, aka the DPL of the stack segment.
412	*/
413	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
414	{
415	/*
416	* Segment must be an accessed code segment, it must be present and it must
417	* be usable.
418	* Note! These are all standard requirements and if CS holds anything else
419	* we've got buggy code somewhere!
420	*/
421	AssertCompile(X86DESCATTR_TYPE == 0xf);
422	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
423	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
424	("%#x\n", pSel->Attr.u),
425	false);
426
427	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
428	must equal SS.DPL for non-confroming segments.
429	Note! This is also a hard requirement like above. */
430	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
431	? pSel->Attr.n.u2Dpl <= uStackDpl
432	: pSel->Attr.n.u2Dpl == uStackDpl,
433	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
434	false);
435
436	/*
437	* The following two requirements are VT-x specific:
438	* - G bit must be set if any high limit bits are set.
439	* - G bit must be clear if any low limit bits are clear.
440	*/
441	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
442	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
443	return true;
444	return false;
445	}
446
447
448	/**
449	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
450	* hardware-assisted VMX when unrestricted execution isn't available.
451	*
452	* @returns true if selector is suitable for VMX, otherwise
453	* false.
454	* @param pSel Pointer to the selector to check
455	* (DS/ES/FS/GS).
456	*/
457	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
458	{
459	/*
460	* Unusable segments are OK. These days they should be marked as such, as
461	* but as an alternative we for old saved states and AMD<->VT-x migration
462	* we also treat segments with all the attributes cleared as unusable.
463	*/
464	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
465	return true;
466
467	/** @todo tighten these checks. Will require CPUM load adjusting. */
468
469	/* Segment must be accessed. */
470	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
471	{
472	/* Code segments must also be readable. */
473	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
474	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
475	{
476	/* The S bit must be set. */
477	if (pSel->Attr.n.u1DescType)
478	{
479	/* Except for conforming segments, DPL >= RPL. */
480	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
481	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
482	{
483	/* Segment must be present. */
484	if (pSel->Attr.n.u1Present)
485	{
486	/*
487	* The following two requirements are VT-x specific:
488	* - G bit must be set if any high limit bits are set.
489	* - G bit must be clear if any low limit bits are clear.
490	*/
491	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
492	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
493	return true;
494	}
495	}
496	}
497	}
498	}
499
500	return false;
501	}
502
503
504	/**
505	* Checks if the stack selector (SS) is suitable for execution using
506	* hardware-assisted VMX when unrestricted execution isn't available.
507	*
508	* @returns true if selector is suitable for VMX, otherwise
509	* false.
510	* @param pSel Pointer to the selector to check (SS).
511	*/
512	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
513	{
514	/*
515	* Unusable segments are OK. These days they should be marked as such, as
516	* but as an alternative we for old saved states and AMD<->VT-x migration
517	* we also treat segments with all the attributes cleared as unusable.
518	*/
519	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
520	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
521	return true;
522
523	/*
524	* Segment must be an accessed writable segment, it must be present.
525	* Note! These are all standard requirements and if SS holds anything else
526	* we've got buggy code somewhere!
527	*/
528	AssertCompile(X86DESCATTR_TYPE == 0xf);
529	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
530	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
531	("%#x\n", pSel->Attr.u), false);
532
533	/*
534	* DPL must equal RPL. But in real mode or soon after enabling protected
535	* mode, it might not be.
536	*/
537	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
538	{
539	/*
540	* The following two requirements are VT-x specific:
541	* - G bit must be set if any high limit bits are set.
542	* - G bit must be clear if any low limit bits are clear.
543	*/
544	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
545	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
546	return true;
547	}
548	return false;
549	}
550
551
552	/**
553	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
554	*
555	* @returns @c true if it is suitable, @c false otherwise.
556	* @param pVCpu The cross context virtual CPU structure.
557	* @param pCtx Pointer to the guest CPU context.
558	*
559	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
560	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
561	* Secondly, if additional checks are added that require more of the CPU
562	* state, make sure REM (which supplies a partial state) is updated.
563	*/
564	VMM_INT_DECL(bool) HMVmxCanExecuteGuest(PVMCPU pVCpu, PCCPUMCTX pCtx)
565	{
566	PVM pVM = pVCpu->CTX_SUFF(pVM);
567	Assert(HMIsEnabled(pVM));
568	Assert(!CPUMIsGuestVmxEnabled(pCtx));
569	Assert( ( pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
570	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
571
572	pVCpu->hm.s.fActive = false;
573
574	bool const fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
575	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
576	{
577	/*
578	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
579	* guest execution feature is missing (VT-x only).
580	*/
581	if (fSupportsRealMode)
582	{
583	if (CPUMIsGuestInRealModeEx(pCtx))
584	{
585	/*
586	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
587	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
588	* and attrributes must be 0x9b for code and 0x93 for code segments.
589	* If this is not true, we cannot execute real mode as V86 and have to fall
590	* back to emulation.
591	*/
592	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
593	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
594	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
595	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
596	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
597	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
598	{
599	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
600	return false;
601	}
602	if ( (pCtx->cs.u32Limit != 0xffff)
603	\|\| (pCtx->ds.u32Limit != 0xffff)
604	\|\| (pCtx->es.u32Limit != 0xffff)
605	\|\| (pCtx->ss.u32Limit != 0xffff)
606	\|\| (pCtx->fs.u32Limit != 0xffff)
607	\|\| (pCtx->gs.u32Limit != 0xffff))
608	{
609	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
610	return false;
611	}
612	if ( (pCtx->cs.Attr.u != 0x9b)
613	\|\| (pCtx->ds.Attr.u != 0x93)
614	\|\| (pCtx->es.Attr.u != 0x93)
615	\|\| (pCtx->ss.Attr.u != 0x93)
616	\|\| (pCtx->fs.Attr.u != 0x93)
617	\|\| (pCtx->gs.Attr.u != 0x93))
618	{
619	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
620	return false;
621	}
622	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
623	}
624	else
625	{
626	/*
627	* Verify the requirements for executing code in protected mode. VT-x can't
628	* handle the CPU state right after a switch from real to protected mode
629	* (all sorts of RPL & DPL assumptions).
630	*/
631	if (pVCpu->hm.s.vmx.fWasInRealMode)
632	{
633	/** @todo If guest is in V86 mode, these checks should be different! */
634	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
635	{
636	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
637	return false;
638	}
639	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
640	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
641	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
642	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
643	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
644	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
645	{
646	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
647	return false;
648	}
649	}
650	}
651	}
652	else
653	{
654	if ( !CPUMIsGuestInLongModeEx(pCtx)
655	&& !pVM->hm.s.vmx.fUnrestrictedGuest)
656	{
657	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
658	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
659	return false;
660
661	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
662	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
663	return false;
664
665	/*
666	* The guest is about to complete the switch to protected mode. Wait a bit longer.
667	* Windows XP; switch to protected mode; all selectors are marked not present
668	* in the hidden registers (possible recompiler bug; see load_seg_vm).
669	*/
670	/** @todo Is this supposed recompiler bug still relevant with IEM? */
671	if (pCtx->cs.Attr.n.u1Present == 0)
672	return false;
673	if (pCtx->ss.Attr.n.u1Present == 0)
674	return false;
675
676	/*
677	* Windows XP: possible same as above, but new recompiler requires new
678	* heuristics? VT-x doesn't seem to like something about the guest state and
679	* this stuff avoids it.
680	*/
681	/** @todo This check is actually wrong, it doesn't take the direction of the
682	* stack segment into account. But, it does the job for now. */
683	if (pCtx->rsp >= pCtx->ss.u32Limit)
684	return false;
685	}
686	}
687	}
688
689	if (pVM->hm.s.vmx.fEnabled)
690	{
691	uint32_t uCr0Mask;
692
693	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
694	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
695
696	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
697	uCr0Mask &= ~X86_CR0_NE;
698
699	if (fSupportsRealMode)
700	{
701	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
702	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
703	}
704	else
705	{
706	/* We support protected mode without paging using identity mapping. */
707	uCr0Mask &= ~X86_CR0_PG;
708	}
709	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
710	return false;
711
712	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
713	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
714	if ((pCtx->cr0 & uCr0Mask) != 0)
715	return false;
716
717	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
718	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
719	uCr0Mask &= ~X86_CR4_VMXE;
720	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
721	return false;
722
723	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
724	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
725	if ((pCtx->cr4 & uCr0Mask) != 0)
726	return false;
727
728	pVCpu->hm.s.fActive = true;
729	return true;
730	}
731
732	return false;
733	}
734
735
736	/**
737	* Injects an event using TRPM given a VM-entry interruption info. and related
738	* fields.
739	*
740	* @returns VBox status code.
741	* @param pVCpu The cross context virtual CPU structure.
742	* @param uEntryIntInfo The VM-entry interruption info.
743	* @param uErrCode The error code associated with the event if any.
744	* @param cbInstr The VM-entry instruction length (for software
745	* interrupts and software exceptions). Pass 0
746	* otherwise.
747	* @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
748	*/
749	VMM_INT_DECL(int) HMVmxEntryIntInfoInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
750	RTGCUINTPTR GCPtrFaultAddress)
751	{
752	Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
753
754	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
755	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
756	bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
757
758	TRPMEVENT enmTrapType;
759	switch (uType)
760	{
761	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
762	enmTrapType = TRPM_HARDWARE_INT;
763	break;
764
765	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
766	enmTrapType = TRPM_SOFTWARE_INT;
767	break;
768
769	case VMX_ENTRY_INT_INFO_TYPE_NMI:
770	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
771	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
772	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
773	enmTrapType = TRPM_TRAP;
774	break;
775
776	default:
777	/* Shouldn't really happen. */
778	AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
779	break;
780	}
781
782	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
783	AssertRCReturn(rc, rc);
784
785	if (fErrCodeValid)
786	TRPMSetErrorCode(pVCpu, uErrCode);
787
788	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
789	&& uVector == X86_XCPT_PF)
790	TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
791	else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
792	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
793	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
794	{
795	AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
796	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
797	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
798	TRPMSetInstrLength(pVCpu, cbInstr);
799	}
800
801	return VINF_SUCCESS;
802	}
803
804
805	/**
806	* Gets the permission bits for the specified MSR in the specified MSR bitmap.
807	*
808	* @returns VBox status code.
809	* @param pvMsrBitmap Pointer to the MSR bitmap.
810	* @param idMsr The MSR.
811	* @param penmRead Where to store the read permissions. Optional, can be
812	* NULL.
813	* @param penmWrite Where to store the write permissions. Optional, can be
814	* NULL.
815	*/
816	VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
817	PVMXMSREXITWRITE penmWrite)
818	{
819	AssertPtrReturn(pvMsrBitmap, VERR_INVALID_PARAMETER);
820
821	int32_t iBit;
822	uint8_t const pbMsrBitmap = (uint8_t )pvMsrBitmap;
823
824	/*
825	* MSR Layout:
826	* Byte index MSR range Interpreted as
827	* 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
828	* 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
829	* 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
830	* 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
831	*
832	* A bit corresponding to an MSR within the above range causes a VM-exit
833	* if the bit is 1 on executions of RDMSR/WRMSR.
834	*
835	* If an MSR falls out of the MSR range, it always cause a VM-exit.
836	*
837	* See Intel spec. 24.6.9 "MSR-Bitmap Address".
838	*/
839	if (idMsr <= 0x00001fff)
840	iBit = idMsr;
841	else if ( idMsr >= 0xc0000000
842	&& idMsr <= 0xc0001fff)
843	{
844	iBit = (idMsr - 0xc0000000);
845	pbMsrBitmap += 0x400;
846	}
847	else
848	{
849	if (penmRead)
850	*penmRead = VMXMSREXIT_INTERCEPT_READ;
851	if (penmWrite)
852	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
853	Log(("CPUMVmxGetMsrPermission: Warning! Out of range MSR %#RX32\n", idMsr));
854	return VINF_SUCCESS;
855	}
856
857	/* Validate the MSR bit position. */
858	Assert(iBit <= 0x1fff);
859
860	/* Get the MSR read permissions. */
861	if (penmRead)
862	{
863	if (ASMBitTest(pbMsrBitmap, iBit))
864	*penmRead = VMXMSREXIT_INTERCEPT_READ;
865	else
866	*penmRead = VMXMSREXIT_PASSTHRU_READ;
867	}
868
869	/* Get the MSR write permissions. */
870	if (penmWrite)
871	{
872	if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
873	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
874	else
875	*penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
876	}
877
878	return VINF_SUCCESS;
879	}
880
881
882	/**
883	* Gets the permission bits for the specified I/O port from the given I/O bitmaps.
884	*
885	* @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
886	* @param pvIoBitmapA Pointer to I/O bitmap A.
887	* @param pvIoBitmapB Pointer to I/O bitmap B.
888	* @param uPort The I/O port being accessed.
889	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
890	*/
891	VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const pvIoBitmapA, void const pvIoBitmapB, uint16_t uPort,
892	uint8_t cbAccess)
893	{
894	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
895
896	/*
897	* If the I/O port access wraps around the 16-bit port I/O space,
898	* we must cause a VM-exit.
899	*
900	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
901	*/
902	/** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc
903	* respectively are valid and do not constitute a wrap around from what I
904	* understand. Verify this later. */
905	uint32_t const uPortLast = uPort + cbAccess;
906	if (uPortLast > 0x10000)
907	return true;
908
909	/* Read the appropriate bit from the corresponding IO bitmap. */
910	void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB;
911	return ASMBitTest(pvIoBitmap, uPort);
912	}
913

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 76553

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