HMSVMAll.cpp@ 70781

最後變更在這個檔案從70781是 70781,由 vboxsync 提交於 7 年前
VMM: Nested Hw.virt: Clean up interrupt injection for nested-guests.
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1	/* $Id: HMSVMAll.cpp 70781 2018-01-29 05:24:06Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/hm_svm.h>
31
32
33	#ifndef IN_RC
34	/**
35	* Emulates a simple MOV TPR (CR8) instruction.
36	*
37	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
38	* at EIP and does the required.
39	*
40	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
41	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
42	* TPR). See hmR3ReplaceTprInstr() for the details.
43	*
44	* @returns VBox status code.
45	* @retval VINF_SUCCESS if the access was handled successfully.
46	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
47	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
48	*
49	* @param pVCpu The cross context virtual CPU structure.
50	* @param pCtx Pointer to the guest-CPU context.
51	* @param pfUpdateRipAndRF Whether the guest RIP/EIP has been updated as
52	* part of the TPR patch operation.
53	*/
54	static int hmSvmEmulateMovTpr(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdateRipAndRF)
55	{
56	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
57
58	/*
59	* We do this in a loop as we increment the RIP after a successful emulation
60	* and the new RIP may be a patched instruction which needs emulation as well.
61	*/
62	bool fUpdateRipAndRF = false;
63	bool fPatchFound = false;
64	PVM pVM = pVCpu->CTX_SUFF(pVM);
65	for (;;)
66	{
67	bool fPending;
68	uint8_t u8Tpr;
69
70	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
71	if (!pPatch)
72	break;
73
74	fPatchFound = true;
75	switch (pPatch->enmType)
76	{
77	case HMTPRINSTR_READ:
78	{
79	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
80	AssertRC(rc);
81
82	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
83	AssertRC(rc);
84	pCtx->rip += pPatch->cbOp;
85	pCtx->eflags.Bits.u1RF = 0;
86	fUpdateRipAndRF = true;
87	break;
88	}
89
90	case HMTPRINSTR_WRITE_REG:
91	case HMTPRINSTR_WRITE_IMM:
92	{
93	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
94	{
95	uint32_t u32Val;
96	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
97	AssertRC(rc);
98	u8Tpr = u32Val;
99	}
100	else
101	u8Tpr = (uint8_t)pPatch->uSrcOperand;
102
103	int rc2 = APICSetTpr(pVCpu, u8Tpr);
104	AssertRC(rc2);
105	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
106
107	pCtx->rip += pPatch->cbOp;
108	pCtx->eflags.Bits.u1RF = 0;
109	fUpdateRipAndRF = true;
110	break;
111	}
112
113	default:
114	{
115	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
116	pVCpu->hm.s.u32HMError = pPatch->enmType;
117	*pfUpdateRipAndRF = fUpdateRipAndRF;
118	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
119	}
120	}
121	}
122
123	*pfUpdateRipAndRF = fUpdateRipAndRF;
124	if (fPatchFound)
125	return VINF_SUCCESS;
126	return VERR_NOT_FOUND;
127	}
128
129
130	/**
131	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
132	* in IEM).
133	*
134	* @param pVCpu The cross context virtual CPU structure.
135	* @param pCtx Pointer to the guest-CPU context.
136	*
137	* @sa hmR0SvmVmRunCacheVmcb.
138	*/
139	VMM_INT_DECL(void) HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PCPUMCTX pCtx)
140	{
141	/*
142	* Restore the nested-guest VMCB fields which have been modified for executing
143	* the nested-guest under SVM R0.
144	*/
145	if (pCtx->hwvirt.svm.fHMCachedVmcb)
146	{
147	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
148	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
149	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
150	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
151
152	pVmcbNstGstCtrl->u16InterceptRdCRx = pNstGstVmcbCache->u16InterceptRdCRx;
153	pVmcbNstGstCtrl->u16InterceptWrCRx = pNstGstVmcbCache->u16InterceptWrCRx;
154	pVmcbNstGstCtrl->u16InterceptRdDRx = pNstGstVmcbCache->u16InterceptRdDRx;
155	pVmcbNstGstCtrl->u16InterceptWrDRx = pNstGstVmcbCache->u16InterceptWrDRx;
156	pVmcbNstGstCtrl->u32InterceptXcpt = pNstGstVmcbCache->u32InterceptXcpt;
157	pVmcbNstGstCtrl->u64InterceptCtrl = pNstGstVmcbCache->u64InterceptCtrl;
158	pVmcbNstGstState->u64CR0 = pNstGstVmcbCache->u64CR0;
159	pVmcbNstGstState->u64CR3 = pNstGstVmcbCache->u64CR3;
160	pVmcbNstGstState->u64CR4 = pNstGstVmcbCache->u64CR4;
161	pVmcbNstGstState->u64EFER = pNstGstVmcbCache->u64EFER;
162	pVmcbNstGstState->u64DBGCTL = pNstGstVmcbCache->u64DBGCTL;
163	pVmcbNstGstCtrl->u32VmcbCleanBits = pNstGstVmcbCache->u32VmcbCleanBits;
164	pVmcbNstGstCtrl->u64IOPMPhysAddr = pNstGstVmcbCache->u64IOPMPhysAddr;
165	pVmcbNstGstCtrl->u64MSRPMPhysAddr = pNstGstVmcbCache->u64MSRPMPhysAddr;
166	pVmcbNstGstCtrl->u64TSCOffset = pNstGstVmcbCache->u64TSCOffset;
167	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pNstGstVmcbCache->fVIntrMasking;
168	pVmcbNstGstCtrl->TLBCtrl = pNstGstVmcbCache->TLBCtrl;
169	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pNstGstVmcbCache->u1NestedPaging;
170	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pNstGstVmcbCache->u1LbrVirt;
171	pCtx->hwvirt.svm.fHMCachedVmcb = false;
172	}
173
174	/*
175	* Currently, VMRUN, #VMEXIT transitions involves trips to ring-3 that would flag a full
176	* CPU state change. However, if we exit to ring-3 in response to receiving a physical
177	* interrupt, we skip signaling any CPU state change as normally no change
178	* is done to the execution state (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
179	* However, with nested-guests, the state can change for e.g., we might perform a
180	* SVM_EXIT_INTR #VMEXIT for the nested-guest in ring-3. Hence we signal a full CPU
181	* state change here.
182	*/
183	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
184	}
185
186
187	/**
188	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
189	* enabled for the VM.
190	*
191	* @returns @c true if VGIF is enabled, @c false otherwise.
192	* @param pVM The cross context VM structure.
193	*
194	* @remarks This value returned by this functions is expected by the callers not
195	* to change throughout the lifetime of the VM.
196	*/
197	VMM_INT_DECL(bool) HMSvmIsVGifActive(PVM pVM)
198	{
199	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
200	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
201
202	return HMIsEnabled(pVM) && fVGif && fUseVGif;
203	}
204	#endif /* !IN_RC */
205
206
207	/**
208	* Performs the operations necessary that are part of the vmmcall instruction
209	* execution in the guest.
210	*
211	* @returns Strict VBox status code (i.e. informational status codes too).
212	* @retval VINF_SUCCESS on successful handling, no \#UD needs to be thrown,
213	* update RIP and eflags.RF depending on @a pfUpdatedRipAndRF and
214	* continue guest execution.
215	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
216	* RIP.
217	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
218	*
219	* @param pVCpu The cross context virtual CPU structure.
220	* @param pCtx Pointer to the guest-CPU context.
221	* @param pfUpdatedRipAndRF Whether the guest RIP/EIP has been updated as
222	* part of handling the VMMCALL operation.
223	*/
224	VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmmcall(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdatedRipAndRF)
225	{
226	#ifndef IN_RC
227	/*
228	* TPR patched instruction emulation for 32-bit guests.
229	*/
230	PVM pVM = pVCpu->CTX_SUFF(pVM);
231	if (pVM->hm.s.fTprPatchingAllowed)
232	{
233	int rc = hmSvmEmulateMovTpr(pVCpu, pCtx, pfUpdatedRipAndRF);
234	if (RT_SUCCESS(rc))
235	return VINF_SUCCESS;
236
237	if (rc != VERR_NOT_FOUND)
238	{
239	Log(("hmSvmExitVmmCall: hmSvmEmulateMovTpr returns %Rrc\n", rc));
240	return rc;
241	}
242	}
243	#endif
244
245	/*
246	* Paravirtualized hypercalls.
247	*/
248	*pfUpdatedRipAndRF = false;
249	if (pVCpu->hm.s.fHypercallsEnabled)
250	return GIMHypercall(pVCpu, pCtx);
251
252	return VERR_NOT_AVAILABLE;
253	}
254
255
256	/**
257	* Converts an SVM event type to a TRPM event type.
258	*
259	* @returns The TRPM event type.
260	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
261	* of recognized trap types.
262	*
263	* @param pEvent Pointer to the SVM event.
264	*/
265	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent)
266	{
267	uint8_t const uType = pEvent->n.u3Type;
268	switch (uType)
269	{
270	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
271	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
272	case SVM_EVENT_EXCEPTION:
273	case SVM_EVENT_NMI: return TRPM_TRAP;
274	default:
275	break;
276	}
277	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
278	return TRPM_32BIT_HACK;
279	}
280
281
282	/**
283	* Gets the MSR permission bitmap byte and bit offset for the specified MSR.
284	*
285	* @returns VBox status code.
286	* @param idMsr The MSR being requested.
287	* @param pbOffMsrpm Where to store the byte offset in the MSR permission
288	* bitmap for @a idMsr.
289	* @param puMsrpmBit Where to store the bit offset starting at the byte
290	* returned in @a pbOffMsrpm.
291	*/
292	VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint32_t puMsrpmBit)
293	{
294	Assert(pbOffMsrpm);
295	Assert(puMsrpmBit);
296
297	/*
298	* MSRPM Layout:
299	* Byte offset MSR range
300	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
301	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
302	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
303	* 0x1800 - 0x1fff Reserved
304	*
305	* Each MSR is represented by 2 permission bits (read and write).
306	*/
307	if (idMsr <= 0x00001fff)
308	{
309	/* Pentium-compatible MSRs. */
310	*pbOffMsrpm = 0;
311	*puMsrpmBit = idMsr << 1;
312	return VINF_SUCCESS;
313	}
314
315	if ( idMsr >= 0xc0000000
316	&& idMsr <= 0xc0001fff)
317	{
318	/* AMD Sixth Generation x86 Processor MSRs. */
319	*pbOffMsrpm = 0x800;
320	*puMsrpmBit = (idMsr - 0xc0000000) << 1;
321	return VINF_SUCCESS;
322	}
323
324	if ( idMsr >= 0xc0010000
325	&& idMsr <= 0xc0011fff)
326	{
327	/* AMD Seventh and Eighth Generation Processor MSRs. */
328	*pbOffMsrpm = 0x1000;
329	*puMsrpmBit = (idMsr - 0xc0010000) << 1;
330	return VINF_SUCCESS;
331	}
332
333	*pbOffMsrpm = 0;
334	*puMsrpmBit = 0;
335	return VERR_OUT_OF_RANGE;
336	}
337
338
339	/**
340	* Determines whether an IOIO intercept is active for the nested-guest or not.
341	*
342	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
343	* @param u16Port The IO port being accessed.
344	* @param enmIoType The type of IO access.
345	* @param cbReg The IO operand size in bytes.
346	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
347	* @param iEffSeg The effective segment number.
348	* @param fRep Whether this is a repeating IO instruction (REP prefix).
349	* @param fStrIo Whether this is a string IO instruction.
350	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
351	* Optional, can be NULL.
352	*/
353	VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
354	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
355	PSVMIOIOEXITINFO pIoExitInfo)
356	{
357	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
358	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
359
360	/*
361	* The IOPM layout:
362	* Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
363	* two 4K pages.
364	*
365	* For IO instructions that access more than a single byte, the permission bits
366	* for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
367	*
368	* Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
369	* we need 3 extra bits beyond the second 4K page.
370	*/
371	static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
372
373	uint16_t const offIopm = u16Port >> 3;
374	uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
375	uint8_t const cShift = u16Port - (offIopm << 3);
376	uint16_t const fIopmMask = (1 << cShift) \| (fSizeMask << cShift);
377
378	uint8_t const pbIopm = (uint8_t )pvIoBitmap;
379	Assert(pbIopm);
380	pbIopm += offIopm;
381	uint16_t const u16Iopm = (uint16_t )pbIopm;
382	if (u16Iopm & fIopmMask)
383	{
384	if (pIoExitInfo)
385	{
386	static const uint32_t s_auIoOpSize[] =
387	{ SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
388
389	static const uint32_t s_auIoAddrSize[] =
390	{ 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
391
392	pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
393	pIoExitInfo->u \|= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
394	pIoExitInfo->n.u1STR = fStrIo;
395	pIoExitInfo->n.u1REP = fRep;
396	pIoExitInfo->n.u3SEG = iEffSeg & 7;
397	pIoExitInfo->n.u1Type = enmIoType;
398	pIoExitInfo->n.u16Port = u16Port;
399	}
400	return true;
401	}
402
403	/** @todo remove later (for debugging as VirtualBox always traps all IO
404	* intercepts). */
405	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
406	return false;
407	}
408
409
410	/**
411	* Checks if the guest VMCB has the specified ctrl/instruction intercept active.
412	*
413	* @returns @c true if in intercept is set, @c false otherwise.
414	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
415	* @param pCtx Pointer to the context.
416	* @param fIntercept The SVM control/instruction intercept, see
417	* SVM_CTRL_INTERCEPT_*.
418	*/
419	VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
420	{
421	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
422	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
423	return RT_BOOL(pVmcbNstGstCache->u64InterceptCtrl & fIntercept);
424	}
425
426
427	/**
428	* Checks if the guest VMCB has the specified CR read intercept active.
429	*
430	* @returns @c true if in intercept is set, @c false otherwise.
431	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
432	* @param pCtx Pointer to the context.
433	* @param uCr The CR register number (0 to 15).
434	*/
435	VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
436	{
437	Assert(uCr < 16);
438	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
439	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
440	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdCRx & (1 << uCr));
441	}
442
443
444	/**
445	* Checks if the guest VMCB has the specified CR write intercept
446	* active.
447	*
448	* @returns @c true if in intercept is set, @c false otherwise.
449	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
450	* @param pCtx Pointer to the context.
451	* @param uCr The CR register number (0 to 15).
452	*/
453	VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
454	{
455	Assert(uCr < 16);
456	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
457	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
458	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrCRx & (1 << uCr));
459	}
460
461
462	/**
463	* Checks if the guest VMCB has the specified DR read intercept
464	* active.
465	*
466	* @returns @c true if in intercept is set, @c false otherwise.
467	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
468	* @param pCtx Pointer to the context.
469	* @param uDr The DR register number (0 to 15).
470	*/
471	VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
472	{
473	Assert(uDr < 16);
474	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
475	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
476	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdDRx & (1 << uDr));
477	}
478
479
480	/**
481	* Checks if the guest VMCB has the specified DR write intercept active.
482	*
483	* @returns @c true if in intercept is set, @c false otherwise.
484	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
485	* @param pCtx Pointer to the context.
486	* @param uDr The DR register number (0 to 15).
487	*/
488	VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
489	{
490	Assert(uDr < 16);
491	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
492	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
493	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrDRx & (1 << uDr));
494	}
495
496
497	/**
498	* Checks if the guest VMCB has the specified exception intercept active.
499	*
500	* @returns true if in intercept is active, false otherwise.
501	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
502	* @param pCtx Pointer to the context.
503	* @param uVector The exception / interrupt vector.
504	*/
505	VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
506	{
507	Assert(uVector < 32);
508	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
509	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
510	return RT_BOOL(pVmcbNstGstCache->u32InterceptXcpt & (1 << uVector));
511	}
512
513
514	/**
515	* Checks whether the SVM nested-guest is in a state to receive physical (APIC)
516	* interrupts.
517	*
518	* @returns true if it's ready, false otherwise.
519	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
520	* @param pCtx The guest-CPU context.
521	*
522	* @remarks This function looks at the VMCB cache rather than directly at the
523	* nested-guest VMCB. The latter may have been modified for executing
524	* using hardware-assisted SVM.
525	*
526	* @sa CPUMCanSvmNstGstTakePhysIntr.
527	*/
528	VMM_INT_DECL(bool) HMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
529	{
530	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
531	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
532	X86EFLAGS fEFlags;
533	if (pVmcbNstGstCache->fVIntrMasking)
534	fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
535	else
536	fEFlags.u = pCtx->eflags.u;
537	return fEFlags.Bits.u1IF;
538	}
539
540
541	/**
542	* Checks whether the SVM nested-guest is in a state to receive virtual (setup
543	* for injection by VMRUN instruction) interrupts.
544	*
545	* @returns true if it's ready, false otherwise.
546	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
547	* @param pCtx The guest-CPU context.
548	*
549	* @remarks This function looks at the VMCB cache rather than directly at the
550	* nested-guest VMCB. The latter may have been modified for executing
551	* using hardware-assisted SVM.
552	*
553	* @sa CPUMCanSvmNstGstTakeVirtIntr.
554	*/
555	VMM_INT_DECL(bool) HMCanSvmNstGstTakeVirtIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
556	{
557	#ifdef IN_RC
558	RT_NOREF2(pVCpu, pCtx);
559	AssertReleaseFailedReturn(false);
560	#else
561	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
562	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
563
564	PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
565	if ( !pVmcbCtrl->IntCtrl.n.u1IgnoreTPR
566	&& pVmcbCtrl->IntCtrl.n.u4VIntrPrio <= pVmcbCtrl->IntCtrl.n.u8VTPR)
567	return false;
568
569	X86EFLAGS fEFlags;
570	if (pVmcbNstGstCache->fVIntrMasking)
571	fEFlags.u = pCtx->eflags.u;
572	else
573	fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
574	return fEFlags.Bits.u1IF;
575	#endif
576	}
577

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 70781

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