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source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 80317

最後變更 在這個檔案從80317是 80268,由 vboxsync 提交於 6 年 前

VMM: Refactoring VMMAll/* to use VMCC & VMMCPUCC. bugref:9217
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
檔案大小: 14.5 KB
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1/* $Id: DBGFAll.cpp 80268 2019-08-14 11:25:13Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, All Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define VBOX_BUGREF_9217_PART_I
23#define LOG_GROUP LOG_GROUP_DBGF
24#include <VBox/vmm/dbgf.h>
25#include "DBGFInternal.h"
26#include <VBox/vmm/vmcc.h>
27#include <VBox/err.h>
28#include <iprt/assert.h>
29#include <iprt/asm.h>
30#include <iprt/stdarg.h>
31
32
33/*
34 * Check the read-only VM members.
35 */
36AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
37AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
38AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
39AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
40AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
41AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
42
43
44/**
45 * Gets the hardware breakpoint configuration as DR7.
46 *
47 * @returns DR7 from the DBGF point of view.
48 * @param pVM The cross context VM structure.
49 */
50VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
51{
52 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
53 PDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
54 unsigned cLeft = RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints);
55 while (cLeft-- > 0)
56 {
57 if ( pBp->enmType == DBGFBPTYPE_REG
58 && pBp->fEnabled)
59 {
60 static const uint8_t s_au8Sizes[8] =
61 {
62 X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
63 X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
64 };
65 uDr7 |= X86_DR7_G(pBp->u.Reg.iReg)
66 | X86_DR7_RW(pBp->u.Reg.iReg, pBp->u.Reg.fType)
67 | X86_DR7_LEN(pBp->u.Reg.iReg, s_au8Sizes[pBp->u.Reg.cb]);
68 }
69 pBp++;
70 }
71 return uDr7;
72}
73
74
75/**
76 * Gets the address of the hardware breakpoint number 0.
77 *
78 * @returns DR0 from the DBGF point of view.
79 * @param pVM The cross context VM structure.
80 */
81VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
82{
83 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
84 Assert(pBp->u.Reg.iReg == 0);
85 return pBp->u.Reg.GCPtr;
86}
87
88
89/**
90 * Gets the address of the hardware breakpoint number 1.
91 *
92 * @returns DR1 from the DBGF point of view.
93 * @param pVM The cross context VM structure.
94 */
95VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
96{
97 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[1];
98 Assert(pBp->u.Reg.iReg == 1);
99 return pBp->u.Reg.GCPtr;
100}
101
102
103/**
104 * Gets the address of the hardware breakpoint number 2.
105 *
106 * @returns DR2 from the DBGF point of view.
107 * @param pVM The cross context VM structure.
108 */
109VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
110{
111 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[2];
112 Assert(pBp->u.Reg.iReg == 2);
113 return pBp->u.Reg.GCPtr;
114}
115
116
117/**
118 * Gets the address of the hardware breakpoint number 3.
119 *
120 * @returns DR3 from the DBGF point of view.
121 * @param pVM The cross context VM structure.
122 */
123VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
124{
125 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[3];
126 Assert(pBp->u.Reg.iReg == 3);
127 return pBp->u.Reg.GCPtr;
128}
129
130
131/**
132 * Checks if any of the hardware breakpoints are armed.
133 *
134 * @returns true if armed, false if not.
135 * @param pVM The cross context VM structure.
136 * @remarks Don't call this from CPUMRecalcHyperDRx!
137 */
138VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
139{
140 return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
141}
142
143
144/**
145 * Checks if any of the hardware I/O breakpoints are armed.
146 *
147 * @returns true if armed, false if not.
148 * @param pVM The cross context VM structure.
149 * @remarks Don't call this from CPUMRecalcHyperDRx!
150 */
151VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
152{
153 return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
154}
155
156
157/**
158 * Checks if any INT3 breakpoints are armed.
159 *
160 * @returns true if armed, false if not.
161 * @param pVM The cross context VM structure.
162 * @remarks Don't call this from CPUMRecalcHyperDRx!
163 */
164VMM_INT_DECL(bool) DBGFBpIsInt3Armed(PVM pVM)
165{
166 return pVM->dbgf.s.cEnabledInt3Breakpoints > 0;
167}
168
169
170/**
171 * Checks I/O access for guest or hypervisor breakpoints.
172 *
173 * @returns Strict VBox status code
174 * @retval VINF_SUCCESS no breakpoint.
175 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
176 * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
177 * been updated appropriately.
178 *
179 * @param pVM The cross context VM structure.
180 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
181 * @param pCtx The CPU context for the calling EMT.
182 * @param uIoPort The I/O port being accessed.
183 * @param cbValue The size/width of the access, in bytes.
184 */
185VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
186{
187 uint32_t const uIoPortFirst = uIoPort;
188 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
189
190
191 /*
192 * Check hyper breakpoints first as the VMM debugger has priority over
193 * the guest.
194 */
195 if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
196 {
197 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
198 {
199 if ( pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.fType == X86_DR7_RW_IO
200 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
201 && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG )
202 {
203 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
204 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.GCPtr & ~(uint64_t)(cbReg - 1);
205 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
206 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
207 {
208 /* (See also DBGFRZTrap01Handler.) */
209 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
210 pVCpu->dbgf.s.fSingleSteppingRaw = false;
211
212 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
213 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
214 return VINF_EM_DBG_BREAKPOINT;
215 }
216 }
217 }
218 }
219
220 /*
221 * Check the guest.
222 */
223 uint32_t const uDr7 = pCtx->dr[7];
224 if ( (uDr7 & X86_DR7_ENABLED_MASK)
225 && X86_DR7_ANY_RW_IO(uDr7)
226 && (pCtx->cr4 & X86_CR4_DE) )
227 {
228 for (unsigned iBp = 0; iBp < 4; iBp++)
229 {
230 if ( (uDr7 & X86_DR7_L_G(iBp))
231 && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
232 {
233 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
234 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
235 uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
236 uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
237 uint64_t uDrXLast = uDrXFirst + cbInvAlign;
238
239 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
240 {
241 /*
242 * Update DR6 and DR7.
243 *
244 * See "AMD64 Architecture Programmer's Manual Volume 2",
245 * chapter 13.1.1.3 for details on DR6 bits. The basics is
246 * that the B0..B3 bits are always cleared while the others
247 * must be cleared by software.
248 *
249 * The following sub chapters says the GD bit is always
250 * cleared when generating a #DB so the handler can safely
251 * access the debug registers.
252 */
253 pCtx->dr[6] &= ~X86_DR6_B_MASK;
254 pCtx->dr[6] |= X86_DR6_B(iBp);
255 pCtx->dr[7] &= ~X86_DR7_GD;
256 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
257 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
258 return VINF_EM_RAW_GUEST_TRAP;
259 }
260 }
261 }
262 }
263 return VINF_SUCCESS;
264}
265
266
267/**
268 * Returns the single stepping state for a virtual CPU.
269 *
270 * @returns stepping (true) or not (false).
271 *
272 * @param pVCpu The cross context virtual CPU structure.
273 */
274VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
275{
276 return pVCpu->dbgf.s.fSingleSteppingRaw;
277}
278
279
280/**
281 * Checks if the specified generic event is enabled or not.
282 *
283 * @returns true / false.
284 * @param pVM The cross context VM structure.
285 * @param enmEvent The generic event being raised.
286 * @param uEventArg The argument of that event.
287 */
288DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
289{
290 if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
291 {
292 switch (enmEvent)
293 {
294 case DBGFEVENT_INTERRUPT_HARDWARE:
295 AssertReturn(uEventArg < 256, false);
296 return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
297
298 case DBGFEVENT_INTERRUPT_SOFTWARE:
299 AssertReturn(uEventArg < 256, false);
300 return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
301
302 default:
303 return true;
304
305 }
306 }
307 return false;
308}
309
310
311/**
312 * Raises a generic debug event if enabled and not being ignored.
313 *
314 * @returns Strict VBox status code.
315 * @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
316 * return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
317 * is okay not to pass this along in some situations.
318 * @retval VINF_SUCCESS if the event was disabled or ignored.
319 *
320 * @param pVM The cross context VM structure.
321 * @param pVCpu The cross context virtual CPU structure.
322 * @param enmEvent The generic event being raised.
323 * @param enmCtx The context in which this event is being raised.
324 * @param cArgs Number of arguments (0 - 6).
325 * @param ... Event arguments.
326 *
327 * @thread EMT(pVCpu)
328 */
329VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArgs(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, DBGFEVENTCTX enmCtx,
330 unsigned cArgs, ...)
331{
332 Assert(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[0].Event.u.Generic.auArgs));
333
334 /*
335 * Is it enabled.
336 */
337 va_list va;
338 va_start(va, cArgs);
339 uint64_t uEventArg0 = cArgs ? va_arg(va, uint64_t) : 0;
340 if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg0))
341 {
342 /*
343 * Any events on the stack. Should the incoming event be ignored?
344 */
345 uint64_t const rip = CPUMGetGuestRIP(pVCpu);
346 uint32_t i = pVCpu->dbgf.s.cEvents;
347 if (i > 0)
348 {
349 while (i-- > 0)
350 {
351 if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
352 && pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
353 && pVCpu->dbgf.s.aEvents[i].rip == rip)
354 {
355 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
356 va_end(va);
357 return VINF_SUCCESS;
358 }
359 Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
360 }
361
362 /*
363 * Trim the event stack.
364 */
365 i = pVCpu->dbgf.s.cEvents;
366 while (i-- > 0)
367 {
368 if ( pVCpu->dbgf.s.aEvents[i].rip == rip
369 && ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
370 || pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
371 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
372 else
373 {
374 if (i + 1 != pVCpu->dbgf.s.cEvents)
375 memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
376 (pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
377 pVCpu->dbgf.s.cEvents--;
378 }
379 }
380
381 i = pVCpu->dbgf.s.cEvents;
382 AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
383 }
384
385 /*
386 * Push the event.
387 */
388 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
389 pVCpu->dbgf.s.aEvents[i].rip = rip;
390 pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
391 pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
392 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.cArgs = cArgs;
393 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[0] = uEventArg0;
394 if (cArgs > 1)
395 {
396 AssertStmt(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs),
397 cArgs = RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs));
398 for (unsigned iArg = 1; iArg < cArgs; iArg++)
399 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[iArg] = va_arg(va, uint64_t);
400 }
401 pVCpu->dbgf.s.cEvents = i + 1;
402
403 VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
404 va_end(va);
405 return VINF_EM_DBG_EVENT;
406 }
407
408 va_end(va);
409 return VINF_SUCCESS;
410}
411
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