CPUMAllCpuId.cpp

最後變更在這個檔案是 108412,由 vboxsync 提交於 2 週前
VMM/KVM: Some linux.arm64 build fixes, bugref:10391
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1	/* $Id: CPUMAllCpuId.cpp 108412 2025-02-27 19:10:58Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part, common bits.
4	*/
5
6	/*
7	* Copyright (C) 2013-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.alldomusa.eu.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/hm.h>
35	#include <VBox/vmm/ssm.h>
36	#include "CPUMInternal.h"
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/sup.h>
39
40	#include <VBox/err.h>
41	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
42	# include <iprt/asm-amd64-x86.h>
43	#endif
44	#include <iprt/ctype.h>
45	#include <iprt/mem.h>
46	#include <iprt/string.h>
47	#include <iprt/x86-helpers.h>
48	#if defined(RT_ARCH_ARM64) \|\| defined(VBOX_VMM_TARGET_ARMV8)
49	# include <iprt/armv8.h>
50	# if defined(RT_OS_LINUX)
51	# include <sys/auxv.h>
52	# endif
53	#endif
54
55
56	/*********************************************************************************************************************************
57	* Global Variables *
58	*********************************************************************************************************************************/
59	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
60	/**
61	* The intel pentium family.
62	*/
63	static const CPUMMICROARCH g_aenmIntelFamily06[] =
64	{
65	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
66	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
67	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
68	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
69	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
71	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
72	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
73	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
74	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
75	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
76	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
77	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
79	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
80	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
81	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
87	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
88	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
92	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
94	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
95	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
96	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
97	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
103	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
104	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
105	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
108	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
110	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
111	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
112	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
113	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
119	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
120	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
121	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
124	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
127	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
128	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
135	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
136	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
137	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
140	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
142	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
143	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
144	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
145	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
151	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
152	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
153	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
156	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
158	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
159	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
160	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
161	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
162	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
163	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
164	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
165	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
166	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
167	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
168	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
169	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
170	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
171	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
172	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
173	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
174	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
175	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
176	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
177	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
178	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
179	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
180	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
181	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
182	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
183	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
184	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
185	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
186	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
187	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
188	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
189	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
190	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
191	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
192	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
193	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
194	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
195	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
196	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
197	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
198	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
199	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
200	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
201	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
202	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
203	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
204	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
205	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
206	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
207	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
208	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
209	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
210	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
211	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
212	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
213	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
214	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
215	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
216	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
217	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
218	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
219	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
220	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
221	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
222	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
223	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
224	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
225	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
226	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
227	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
228	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
229	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
230	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
231	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
232	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
233	};
234	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
235
236
237	/**
238	* Figures out the (sub-)micro architecture given a bit of CPUID info.
239	*
240	* @returns Micro architecture.
241	* @param enmVendor The CPU vendor.
242	* @param bFamily The CPU family.
243	* @param bModel The CPU model.
244	* @param bStepping The CPU stepping.
245	*/
246	VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
247	uint8_t bModel, uint8_t bStepping)
248	{
249	if (enmVendor == CPUMCPUVENDOR_AMD)
250	{
251	switch (bFamily)
252	{
253	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
254	case 0x03: return kCpumMicroarch_AMD_Am386;
255	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
256	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
257	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
258	case 0x06:
259	switch (bModel)
260	{
261	case 0: return kCpumMicroarch_AMD_K7_Palomino;
262	case 1: return kCpumMicroarch_AMD_K7_Palomino;
263	case 2: return kCpumMicroarch_AMD_K7_Palomino;
264	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
265	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
266	case 6: return kCpumMicroarch_AMD_K7_Palomino;
267	case 7: return kCpumMicroarch_AMD_K7_Morgan;
268	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
269	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
270	}
271	return kCpumMicroarch_AMD_K7_Unknown;
272	case 0x0f:
273	/*
274	* This family is a friggin mess. Trying my best to make some
275	* sense out of it. Too much happened in the 0x0f family to
276	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
277	*
278	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
279	* cpu-world.com, and other places:
280	* - 130nm:
281	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
282	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
283	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
284	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
285	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
286	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
287	* - 90nm:
288	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
289	* - Oakville: 10FC0/DH-D0.
290	* - Georgetown: 10FC0/DH-D0.
291	* - Sonora: 10FC0/DH-D0.
292	* - Venus: 20F71/SH-E4
293	* - Troy: 20F51/SH-E4
294	* - Athens: 20F51/SH-E4
295	* - San Diego: 20F71/SH-E4.
296	* - Lancaster: 20F42/SH-E5
297	* - Newark: 20F42/SH-E5.
298	* - Albany: 20FC2/DH-E6.
299	* - Roma: 20FC2/DH-E6.
300	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
301	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
302	* - 90nm introducing Dual core:
303	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
304	* - Italy: 20F10/JH-E1, 20F12/JH-E6
305	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
306	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
307	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
308	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
309	* - Santa Ana: 40F32/JH-F2, /-F3
310	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
311	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
312	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
313	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
314	* - Keene: 40FC2/DH-F2.
315	* - Richmond: 40FC2/DH-F2
316	* - Taylor: 40F82/BH-F2
317	* - Trinidad: 40F82/BH-F2
318	*
319	* - 65nm:
320	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
321	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
322	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
323	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
324	* - Sherman: /-G1, 70FC2/DH-G2.
325	* - Huron: 70FF2/DH-G2.
326	*/
327	if (bModel < 0x10)
328	return kCpumMicroarch_AMD_K8_130nm;
329	if (bModel >= 0x60 && bModel < 0x80)
330	return kCpumMicroarch_AMD_K8_65nm;
331	if (bModel >= 0x40)
332	return kCpumMicroarch_AMD_K8_90nm_AMDV;
333	switch (bModel)
334	{
335	case 0x21:
336	case 0x23:
337	case 0x2b:
338	case 0x2f:
339	case 0x37:
340	case 0x3f:
341	return kCpumMicroarch_AMD_K8_90nm_DualCore;
342	}
343	return kCpumMicroarch_AMD_K8_90nm;
344	case 0x10:
345	return kCpumMicroarch_AMD_K10;
346	case 0x11:
347	return kCpumMicroarch_AMD_K10_Lion;
348	case 0x12:
349	return kCpumMicroarch_AMD_K10_Llano;
350	case 0x14:
351	return kCpumMicroarch_AMD_Bobcat;
352	case 0x15:
353	switch (bModel)
354	{
355	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
356	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
357	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
358	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
359	case 0x11: /* ?? */
360	case 0x12: /* ?? */
361	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
362	}
363	return kCpumMicroarch_AMD_15h_Unknown;
364	case 0x16:
365	return kCpumMicroarch_AMD_Jaguar;
366	case 0x17:
367	return kCpumMicroarch_AMD_Zen_Ryzen;
368	}
369	return kCpumMicroarch_AMD_Unknown;
370	}
371
372	if (enmVendor == CPUMCPUVENDOR_INTEL)
373	{
374	switch (bFamily)
375	{
376	case 3:
377	return kCpumMicroarch_Intel_80386;
378	case 4:
379	return kCpumMicroarch_Intel_80486;
380	case 5:
381	return kCpumMicroarch_Intel_P5;
382	case 6:
383	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
384	{
385	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
386	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
387	{
388	if (bStepping >= 0xa && bStepping <= 0xc)
389	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
390	else if (bStepping >= 0xc)
391	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
392	}
393	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
394	&& bModel == 0x55
395	&& bStepping >= 5)
396	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
397	return enmMicroArch;
398	}
399	return kCpumMicroarch_Intel_Atom_Unknown;
400	case 15:
401	switch (bModel)
402	{
403	case 0: return kCpumMicroarch_Intel_NB_Willamette;
404	case 1: return kCpumMicroarch_Intel_NB_Willamette;
405	case 2: return kCpumMicroarch_Intel_NB_Northwood;
406	case 3: return kCpumMicroarch_Intel_NB_Prescott;
407	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
408	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
409	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
410	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
411	default: return kCpumMicroarch_Intel_NB_Unknown;
412	}
413	break;
414	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
415	case 0:
416	return kCpumMicroarch_Intel_8086;
417	case 1:
418	return kCpumMicroarch_Intel_80186;
419	case 2:
420	return kCpumMicroarch_Intel_80286;
421	}
422	return kCpumMicroarch_Intel_Unknown;
423	}
424
425	if (enmVendor == CPUMCPUVENDOR_VIA)
426	{
427	switch (bFamily)
428	{
429	case 5:
430	switch (bModel)
431	{
432	case 1: return kCpumMicroarch_Centaur_C6;
433	case 4: return kCpumMicroarch_Centaur_C6;
434	case 8: return kCpumMicroarch_Centaur_C2;
435	case 9: return kCpumMicroarch_Centaur_C3;
436	}
437	break;
438
439	case 6:
440	switch (bModel)
441	{
442	case 5: return kCpumMicroarch_VIA_C3_M2;
443	case 6: return kCpumMicroarch_VIA_C3_C5A;
444	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
445	case 8: return kCpumMicroarch_VIA_C3_C5N;
446	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
447	case 10: return kCpumMicroarch_VIA_C7_C5J;
448	case 15: return kCpumMicroarch_VIA_Isaiah;
449	}
450	break;
451	}
452	return kCpumMicroarch_VIA_Unknown;
453	}
454
455	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
456	{
457	switch (bFamily)
458	{
459	case 6:
460	case 7:
461	return kCpumMicroarch_Shanghai_Wudaokou;
462	default:
463	break;
464	}
465	return kCpumMicroarch_Shanghai_Unknown;
466	}
467
468	if (enmVendor == CPUMCPUVENDOR_CYRIX)
469	{
470	switch (bFamily)
471	{
472	case 4:
473	switch (bModel)
474	{
475	case 9: return kCpumMicroarch_Cyrix_5x86;
476	}
477	break;
478
479	case 5:
480	switch (bModel)
481	{
482	case 2: return kCpumMicroarch_Cyrix_M1;
483	case 4: return kCpumMicroarch_Cyrix_MediaGX;
484	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
485	}
486	break;
487
488	case 6:
489	switch (bModel)
490	{
491	case 0: return kCpumMicroarch_Cyrix_M2;
492	}
493	break;
494
495	}
496	return kCpumMicroarch_Cyrix_Unknown;
497	}
498
499	if (enmVendor == CPUMCPUVENDOR_HYGON)
500	{
501	switch (bFamily)
502	{
503	case 0x18:
504	return kCpumMicroarch_Hygon_Dhyana;
505	default:
506	break;
507	}
508	return kCpumMicroarch_Hygon_Unknown;
509	}
510
511	return kCpumMicroarch_Unknown;
512	}
513
514	#endif /* if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
515
516
517
518	/**
519	* Translates a microarchitecture enum value to the corresponding string
520	* constant.
521	*
522	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
523	* NULL if the value is invalid.
524	*
525	* @param enmMicroarch The enum value to convert.
526	*/
527	VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch)
528	{
529	switch (enmMicroarch)
530	{
531	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
532	CASE_RET_STR(kCpumMicroarch_Intel_8086);
533	CASE_RET_STR(kCpumMicroarch_Intel_80186);
534	CASE_RET_STR(kCpumMicroarch_Intel_80286);
535	CASE_RET_STR(kCpumMicroarch_Intel_80386);
536	CASE_RET_STR(kCpumMicroarch_Intel_80486);
537	CASE_RET_STR(kCpumMicroarch_Intel_P5);
538
539	CASE_RET_STR(kCpumMicroarch_Intel_P6);
540	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
541	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
542
543	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
544	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
546
547	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
549
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
558	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
559	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
560	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
561	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
562	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
563	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
564	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
565	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
566	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
567	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
568
569	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
570	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
571	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
572	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
573	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
574	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
575	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
576	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
577
578	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
579	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
580	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
581	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
582	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
583
584	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
585	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
586	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
587	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
588	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
589	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
590	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
591
592	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
593
594	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
595	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
596	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
597	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
598	CASE_RET_STR(kCpumMicroarch_AMD_K5);
599	CASE_RET_STR(kCpumMicroarch_AMD_K6);
600
601	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
602	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
603	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
604	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
605	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
606	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
607	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
608
609	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
610	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
611	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
612	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
613	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
614
615	CASE_RET_STR(kCpumMicroarch_AMD_K10);
616	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
617	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
618	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
619	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
620
621	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
622	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
623	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
624	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
625	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
626
627	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
628
629	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
630
631	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
632
633	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
634	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
635
636	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
637	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
638	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
639	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
640	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
641	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
642	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
643	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
644	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
645	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
646	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
647	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
648	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
649
650	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
651	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
652
653	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
654	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
655	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
656	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
657	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
658	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
659
660	CASE_RET_STR(kCpumMicroarch_NEC_V20);
661	CASE_RET_STR(kCpumMicroarch_NEC_V30);
662
663	CASE_RET_STR(kCpumMicroarch_Apple_M1);
664	CASE_RET_STR(kCpumMicroarch_Apple_M2);
665
666	CASE_RET_STR(kCpumMicroarch_Unknown);
667
668	#undef CASE_RET_STR
669	case kCpumMicroarch_Invalid:
670	case kCpumMicroarch_Intel_End:
671	case kCpumMicroarch_Intel_Core2_End:
672	case kCpumMicroarch_Intel_Core7_End:
673	case kCpumMicroarch_Intel_Atom_End:
674	case kCpumMicroarch_Intel_P6_Core_Atom_End:
675	case kCpumMicroarch_Intel_Phi_End:
676	case kCpumMicroarch_Intel_NB_End:
677	case kCpumMicroarch_AMD_K7_End:
678	case kCpumMicroarch_AMD_K8_End:
679	case kCpumMicroarch_AMD_15h_End:
680	case kCpumMicroarch_AMD_16h_End:
681	case kCpumMicroarch_AMD_Zen_End:
682	case kCpumMicroarch_AMD_End:
683	case kCpumMicroarch_Hygon_End:
684	case kCpumMicroarch_VIA_End:
685	case kCpumMicroarch_Shanghai_End:
686	case kCpumMicroarch_Cyrix_End:
687	case kCpumMicroarch_NEC_End:
688	case kCpumMicroarch_Apple_End:
689	case kCpumMicroarch_32BitHack:
690	break;
691	/* no default! */
692	}
693
694	return NULL;
695	}
696
697	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
698
699	/**
700	* Gets a matching leaf in the CPUID leaf array.
701	*
702	* @returns Pointer to the matching leaf, or NULL if not found.
703	* @param paLeaves The CPUID leaves to search. This is sorted.
704	* @param cLeaves The number of leaves in the array.
705	* @param uLeaf The leaf to locate.
706	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
707	*/
708	PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
709	{
710	/* Lazy bird does linear lookup here since this is only used for the
711	occational CPUID overrides. */
712	for (uint32_t i = 0; i < cLeaves; i++)
713	if ( paLeaves[i].uLeaf == uLeaf
714	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
715	return &paLeaves[i];
716	return NULL;
717	}
718
719
720	/**
721	* Ensures that the CPUID leaf array can hold one more leaf.
722	*
723	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
724	* failure.
725	* @param pVM The cross context VM structure. If NULL, use
726	* the process heap, otherwise the VM's hyper heap.
727	* @param ppaLeaves Pointer to the variable holding the array pointer
728	* (input/output).
729	* @param cLeaves The current array size.
730	*
731	* @remarks This function will automatically update the R0 and RC pointers when
732	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
733	* be the corresponding VM's CPUID arrays (which is asserted).
734	*/
735	PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
736	{
737	/*
738	* If pVM is not specified, we're on the regular heap and can waste a
739	* little space to speed things up.
740	*/
741	uint32_t cAllocated;
742	if (!pVM)
743	{
744	cAllocated = RT_ALIGN(cLeaves, 16);
745	if (cLeaves + 1 > cAllocated)
746	{
747	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
748	if (pvNew)
749	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
750	else
751	{
752	RTMemFree(*ppaLeaves);
753	*ppaLeaves = NULL;
754	}
755	}
756	}
757	/*
758	* Otherwise, we're on the hyper heap and are probably just inserting
759	* one or two leaves and should conserve space.
760	*/
761	else
762	{
763	# ifdef IN_VBOX_CPU_REPORT
764	AssertReleaseFailed();
765	# else
766	# ifdef IN_RING3
767	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
768	Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
769	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
770
771	if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
772	{ }
773	else
774	# endif
775	{
776	*ppaLeaves = NULL;
777	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
778	}
779	# endif
780	}
781	return *ppaLeaves;
782	}
783
784
785	# ifdef VBOX_STRICT
786	/**
787	* Checks that we've updated the CPUID leaves array correctly.
788	*
789	* This is a no-op in non-strict builds.
790	*
791	* @param paLeaves The leaves array.
792	* @param cLeaves The number of leaves.
793	*/
794	void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
795	{
796	for (uint32_t i = 1; i < cLeaves; i++)
797	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
798	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
799	else
800	{
801	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
802	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
803	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
804	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
805	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
806	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
807	}
808	}
809	# endif
810
811	#endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
812
813	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
814
815	/**
816	* Append a CPUID leaf or sub-leaf.
817	*
818	* ASSUMES linear insertion order, so we'll won't need to do any searching or
819	* replace anything. Use cpumR3CpuIdInsert() for those cases.
820	*
821	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
822	* the caller need do no more work.
823	* @param ppaLeaves Pointer to the pointer to the array of sorted
824	* CPUID leaves and sub-leaves.
825	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
826	* @param uLeaf The leaf we're adding.
827	* @param uSubLeaf The sub-leaf number.
828	* @param fSubLeafMask The sub-leaf mask.
829	* @param uEax The EAX value.
830	* @param uEbx The EBX value.
831	* @param uEcx The ECX value.
832	* @param uEdx The EDX value.
833	* @param fFlags The flags.
834	*/
835	static int cpumCollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
836	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
837	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
838	{
839	if (!cpumCpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
840	return VERR_NO_MEMORY;
841
842	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
843	Assert( *pcLeaves == 0
844	\|\| pNew[-1].uLeaf < uLeaf
845	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
846
847	pNew->uLeaf = uLeaf;
848	pNew->uSubLeaf = uSubLeaf;
849	pNew->fSubLeafMask = fSubLeafMask;
850	pNew->uEax = uEax;
851	pNew->uEbx = uEbx;
852	pNew->uEcx = uEcx;
853	pNew->uEdx = uEdx;
854	pNew->fFlags = fFlags;
855
856	*pcLeaves += 1;
857	return VINF_SUCCESS;
858	}
859
860
861	/**
862	* Checks if ECX make a difference when reading a given CPUID leaf.
863	*
864	* @returns @c true if it does, @c false if it doesn't.
865	* @param uLeaf The leaf we're reading.
866	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
867	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
868	* final sub-leaf (for leaf 0xb only).
869	*/
870	static bool cpumIsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
871	{
872	*pfFinalEcxUnchanged = false;
873
874	uint32_t auCur[4];
875	uint32_t auPrev[4];
876	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
877
878	/* Look for sub-leaves. */
879	uint32_t uSubLeaf = 1;
880	for (;;)
881	{
882	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
883	if (memcmp(auCur, auPrev, sizeof(auCur)))
884	break;
885
886	/* Advance / give up. */
887	uSubLeaf++;
888	if (uSubLeaf >= 64)
889	{
890	*pcSubLeaves = 1;
891	return false;
892	}
893	}
894
895	/* Count sub-leaves. */
896	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : uLeaf == 7 ? 2 : 0;
897	uint32_t cRepeats = 0;
898	uSubLeaf = 0;
899	for (;;)
900	{
901	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
902
903	/* Figuring out when to stop isn't entirely straight forward as we need
904	to cover undocumented behavior up to a point and implementation shortcuts. */
905
906	/* 1. Look for more than 4 repeating value sets. */
907	if ( auCur[0] == auPrev[0]
908	&& auCur[1] == auPrev[1]
909	&& ( auCur[2] == auPrev[2]
910	\|\| ( auCur[2] == uSubLeaf
911	&& auPrev[2] == uSubLeaf - 1) )
912	&& auCur[3] == auPrev[3])
913	{
914	if ( uLeaf != 0xd
915	\|\| uSubLeaf >= 64
916	\|\| ( auCur[0] == 0
917	&& auCur[1] == 0
918	&& auCur[2] == 0
919	&& auCur[3] == 0
920	&& auPrev[2] == 0) )
921	cRepeats++;
922	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
923	break;
924	}
925	else
926	cRepeats = 0;
927
928	/* 2. Look for zero values. */
929	if ( auCur[0] == 0
930	&& auCur[1] == 0
931	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
932	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
933	&& uSubLeaf >= cMinLeaves)
934	{
935	cRepeats = 0;
936	break;
937	}
938
939	/* 3. Leaf 0xb level type 0 check. */
940	if ( uLeaf == 0xb
941	&& (auCur[2] & 0xff00) == 0
942	&& (auPrev[2] & 0xff00) == 0)
943	{
944	cRepeats = 0;
945	break;
946	}
947
948	/* 99. Give up. */
949	if (uSubLeaf >= 128)
950	{
951	# ifndef IN_VBOX_CPU_REPORT
952	/* Ok, limit it according to the documentation if possible just to
953	avoid annoying users with these detection issues. */
954	uint32_t cDocLimit = UINT32_MAX;
955	if (uLeaf == 0x4)
956	cDocLimit = 4;
957	else if (uLeaf == 0x7)
958	cDocLimit = 1;
959	else if (uLeaf == 0xd)
960	cDocLimit = 63;
961	else if (uLeaf == 0xf)
962	cDocLimit = 2;
963	if (cDocLimit != UINT32_MAX)
964	{
965	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
966	*pcSubLeaves = cDocLimit + 3;
967	return true;
968	}
969	# endif
970	*pcSubLeaves = UINT32_MAX;
971	return true;
972	}
973
974	/* Advance. */
975	uSubLeaf++;
976	memcpy(auPrev, auCur, sizeof(auCur));
977	}
978
979	/* Standard exit. */
980	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
981	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
982	if (*pcSubLeaves == 0)
983	*pcSubLeaves = 1;
984	return true;
985	}
986
987
988	/**
989	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
990	*
991	* @returns VBox status code.
992	* @param ppaLeaves Where to return the array pointer on success.
993	* Use RTMemFree to release.
994	* @param pcLeaves Where to return the size of the array on
995	* success.
996	*/
997	VMMDECL(int) CPUMCpuIdCollectLeavesFromX86Host(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
998	{
999	*ppaLeaves = NULL;
1000	*pcLeaves = 0;
1001
1002	/*
1003	* Try out various candidates. This must be sorted!
1004	*/
1005	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1006	{
1007	{ UINT32_C(0x00000000), false },
1008	{ UINT32_C(0x10000000), false },
1009	{ UINT32_C(0x20000000), false },
1010	{ UINT32_C(0x30000000), false },
1011	{ UINT32_C(0x40000000), false },
1012	{ UINT32_C(0x50000000), false },
1013	{ UINT32_C(0x60000000), false },
1014	{ UINT32_C(0x70000000), false },
1015	{ UINT32_C(0x80000000), false },
1016	{ UINT32_C(0x80860000), false },
1017	{ UINT32_C(0x8ffffffe), true },
1018	{ UINT32_C(0x8fffffff), true },
1019	{ UINT32_C(0x90000000), false },
1020	{ UINT32_C(0xa0000000), false },
1021	{ UINT32_C(0xb0000000), false },
1022	{ UINT32_C(0xc0000000), false },
1023	{ UINT32_C(0xd0000000), false },
1024	{ UINT32_C(0xe0000000), false },
1025	{ UINT32_C(0xf0000000), false },
1026	};
1027
1028	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1029	{
1030	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1031	uint32_t uEax, uEbx, uEcx, uEdx;
1032	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1033
1034	/*
1035	* Does EAX look like a typical leaf count value?
1036	*/
1037	if ( uEax > uLeaf
1038	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1039	{
1040	/* Yes, dump them. */
1041	uint32_t cLeaves = uEax - uLeaf + 1;
1042	while (cLeaves-- > 0)
1043	{
1044	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1045
1046	uint32_t fFlags = 0;
1047
1048	/* There are currently three known leaves containing an APIC ID
1049	that needs EMT specific attention */
1050	if (uLeaf == 1)
1051	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1052	else if (uLeaf == 0xb && uEcx != 0)
1053	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1054	else if ( uLeaf == UINT32_C(0x8000001e)
1055	&& ( uEax
1056	\|\| uEbx
1057	\|\| uEdx
1058	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1059	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1060	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1061
1062	/* The APIC bit is per-VCpu and needs flagging. */
1063	if (uLeaf == 1)
1064	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1065	else if ( uLeaf == UINT32_C(0x80000001)
1066	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1067	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1068	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1069	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1070
1071	/* Check three times here to reduce the chance of CPU migration
1072	resulting in false positives with things like the APIC ID. */
1073	uint32_t cSubLeaves;
1074	bool fFinalEcxUnchanged;
1075	if ( cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1076	&& cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1077	&& cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1078	{
1079	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1080	{
1081	/* This shouldn't happen. But in case it does, file all
1082	relevant details in the release log. */
1083	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1084	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1085	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1086	{
1087	uint32_t auTmp[4];
1088	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1089	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1090	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1091	}
1092	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1093	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1094	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1095	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1096	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1097	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1098	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1099	}
1100
1101	if (fFinalEcxUnchanged)
1102	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1103
1104	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1105	{
1106	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1107	int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1108	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1109	if (RT_FAILURE(rc))
1110	return rc;
1111	}
1112	}
1113	else
1114	{
1115	int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1116	if (RT_FAILURE(rc))
1117	return rc;
1118	}
1119
1120	/* next */
1121	uLeaf++;
1122	}
1123	}
1124	/*
1125	* Special CPUIDs needs special handling as they don't follow the
1126	* leaf count principle used above.
1127	*/
1128	else if (s_aCandidates[iOuter].fSpecial)
1129	{
1130	bool fKeep = false;
1131	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1132	fKeep = true;
1133	else if ( uLeaf == 0x8fffffff
1134	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1135	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1136	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1137	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1138	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1139	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1140	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1141	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1142	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1143	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1144	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1145	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1146	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1147	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1148	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1149	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1150	fKeep = true;
1151	if (fKeep)
1152	{
1153	int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1154	if (RT_FAILURE(rc))
1155	return rc;
1156	}
1157	}
1158	}
1159
1160	# ifdef VBOX_STRICT
1161	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
1162	# endif
1163	return VINF_SUCCESS;
1164	}
1165
1166	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1167
1168	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
1169	/**
1170	* Detect the CPU vendor give n the
1171	*
1172	* @returns The vendor.
1173	* @param uEAX EAX from CPUID(0).
1174	* @param uEBX EBX from CPUID(0).
1175	* @param uECX ECX from CPUID(0).
1176	* @param uEDX EDX from CPUID(0).
1177	*/
1178	VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1179	{
1180	if (RTX86IsValidStdRange(uEAX))
1181	{
1182	if (RTX86IsAmdCpu(uEBX, uECX, uEDX))
1183	return CPUMCPUVENDOR_AMD;
1184
1185	if (RTX86IsIntelCpu(uEBX, uECX, uEDX))
1186	return CPUMCPUVENDOR_INTEL;
1187
1188	if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX))
1189	return CPUMCPUVENDOR_VIA;
1190
1191	if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX))
1192	return CPUMCPUVENDOR_SHANGHAI;
1193
1194	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1195	&& uECX == UINT32_C(0x64616574)
1196	&& uEDX == UINT32_C(0x736E4978))
1197	return CPUMCPUVENDOR_CYRIX;
1198
1199	if (RTX86IsHygonCpu(uEBX, uECX, uEDX))
1200	return CPUMCPUVENDOR_HYGON;
1201
1202	/* "Geode by NSC", example: family 5, model 9. */
1203
1204	/** @todo detect the other buggers... */
1205	}
1206
1207	return CPUMCPUVENDOR_UNKNOWN;
1208	}
1209	#endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
1210
1211
1212	/**
1213	* Translates a CPU vendor enum value into the corresponding string constant.
1214	*
1215	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1216	* value name. This can be useful when generating code.
1217	*
1218	* @returns Read only name string.
1219	* @param enmVendor The CPU vendor value.
1220	*/
1221	VMMDECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor)
1222	{
1223	switch (enmVendor)
1224	{
1225	case CPUMCPUVENDOR_INTEL: return "INTEL";
1226	case CPUMCPUVENDOR_AMD: return "AMD";
1227	case CPUMCPUVENDOR_VIA: return "VIA";
1228	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1229	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1230	case CPUMCPUVENDOR_HYGON: return "HYGON";
1231	case CPUMCPUVENDOR_APPLE: return "APPLE";
1232	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1233
1234	case CPUMCPUVENDOR_INVALID:
1235	case CPUMCPUVENDOR_32BIT_HACK:
1236	break;
1237	}
1238	return "Invalid-cpu-vendor";
1239	}
1240
1241	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
1242
1243	static PCCPUMCPUIDLEAF cpumCpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1244	{
1245	/* Could do binary search, doing linear now because I'm lazy. */
1246	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1247	while (cLeaves-- > 0)
1248	{
1249	if (pLeaf->uLeaf == uLeaf)
1250	return pLeaf;
1251	pLeaf++;
1252	}
1253	return NULL;
1254	}
1255
1256
1257	static PCCPUMCPUIDLEAF cpumCpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1258	{
1259	PCCPUMCPUIDLEAF pLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1260	if ( !pLeaf
1261	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1262	return pLeaf;
1263
1264	/* Linear sub-leaf search. Lazy as usual. */
1265	cLeaves -= pLeaf - paLeaves;
1266	while ( cLeaves-- > 0
1267	&& pLeaf->uLeaf == uLeaf)
1268	{
1269	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1270	return pLeaf;
1271	pLeaf++;
1272	}
1273
1274	return NULL;
1275	}
1276
1277
1278	static void cpumExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, CPUMFEATURESX86 *pFeatures)
1279	{
1280	Assert(pVmxMsrs);
1281	Assert(pFeatures);
1282	Assert(pFeatures->fVmx);
1283
1284	/* Basic information. */
1285	bool const fVmxTrueMsrs = RT_BOOL(pVmxMsrs->u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
1286	{
1287	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1288	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1289	}
1290
1291	/* Pin-based VM-execution controls. */
1292	{
1293	uint32_t const fPinCtls = fVmxTrueMsrs ? pVmxMsrs->TruePinCtls.n.allowed1 : pVmxMsrs->PinCtls.n.allowed1;
1294	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1295	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1296	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1297	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1298	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1299	}
1300
1301	/* Processor-based VM-execution controls. */
1302	{
1303	uint32_t const fProcCtls = fVmxTrueMsrs ? pVmxMsrs->TrueProcCtls.n.allowed1 : pVmxMsrs->ProcCtls.n.allowed1;
1304	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1305	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1306	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1307	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1308	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1309	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1310	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1311	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1312	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1313	pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1314	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1315	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1316	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1317	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1318	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1319	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1320	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1321	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1322	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1323	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1324	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1325	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1326	}
1327
1328	/* Secondary processor-based VM-execution controls. */
1329	{
1330	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1331	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1332	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1333	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1334	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1335	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1336	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1337	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1338	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1339	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1340	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1341	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1342	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1343	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1344	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1345	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1346	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1347	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1348	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1349	pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1350	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1351	pFeatures->fVmxPasidTranslate = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PASID_TRANSLATE);
1352	pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1353	pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1354	pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1355	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1356	pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1357	pFeatures->fVmxPconfig = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PCONFIG);
1358	pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1359	pFeatures->fVmxBusLockDetect = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_BUS_LOCK_DETECT);
1360	pFeatures->fVmxInstrTimeout = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INSTR_TIMEOUT);
1361	}
1362
1363	/* Tertiary processor-based VM-execution controls. */
1364	{
1365	uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1366	pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1367	pFeatures->fVmxHlat = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_HLAT);
1368	pFeatures->fVmxEptPagingWrite = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_EPT_PAGING_WRITE);
1369	pFeatures->fVmxGstPagingVerify = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_GST_PAGING_VERIFY);
1370	pFeatures->fVmxIpiVirt = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_IPI_VIRT);
1371	pFeatures->fVmxVirtSpecCtrl = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_VIRT_SPEC_CTRL);
1372	}
1373
1374	/* VM-exit controls. */
1375	{
1376	uint32_t const fExitCtls = fVmxTrueMsrs ? pVmxMsrs->TrueExitCtls.n.allowed1 : pVmxMsrs->ExitCtls.n.allowed1;
1377	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1378	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1379	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1380	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1381	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1382	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1383	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1384	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1385	pFeatures->fVmxSecondaryExitCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_USE_SECONDARY_CTLS);
1386	}
1387
1388	/* VM-entry controls. */
1389	{
1390	uint32_t const fEntryCtls = fVmxTrueMsrs ? pVmxMsrs->TrueEntryCtls.n.allowed1 : pVmxMsrs->EntryCtls.n.allowed1;
1391	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1392	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1393	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1394	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1395	}
1396
1397	/* Miscellaneous data. */
1398	{
1399	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1400	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1401	pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1402	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1403	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1404	}
1405	}
1406
1407
1408	void cpumCpuIdExplodeFeaturesX86SetSummaryBits(CPUMFEATURESX86 *pFeatures)
1409	{
1410	/* Summary or all bits indicating the presence of the IA32_SPEC_CTRL MSR. */
1411	pFeatures->fSpecCtrlMsr = pFeatures->fIbrs
1412	\| pFeatures->fStibp
1413	\| pFeatures->fSsbd
1414	\| pFeatures->fPsfd
1415	\| pFeatures->fIpredCtrl
1416	\| pFeatures->fRrsbaCtrl
1417	\| pFeatures->fDdpdU
1418	\| pFeatures->fBhiCtrl
1419	;
1420	}
1421
1422
1423	int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, CPUMFEATURESX86 *pFeatures)
1424	{
1425	Assert(pMsrs);
1426	RT_ZERO(*pFeatures);
1427	if (cLeaves >= 2)
1428	{
1429	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1430	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1431	PCCPUMCPUIDLEAF const pStd0Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1432	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1433	PCCPUMCPUIDLEAF const pStd1Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1434	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1435
1436	pFeatures->enmCpuVendor = CPUMCpuIdDetectX86VendorEx(pStd0Leaf->uEax,
1437	pStd0Leaf->uEbx,
1438	pStd0Leaf->uEcx,
1439	pStd0Leaf->uEdx);
1440	pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax);
1441	pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1442	pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax);
1443	pFeatures->enmMicroarch = CPUMCpuIdDetermineX86MicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1444	pFeatures->uFamily,
1445	pFeatures->uModel,
1446	pFeatures->uStepping);
1447
1448	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1449	if (pExtLeaf8)
1450	{
1451	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1452	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1453	}
1454	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1455	{
1456	pFeatures->cMaxPhysAddrWidth = 36;
1457	pFeatures->cMaxLinearAddrWidth = 36;
1458	}
1459	else
1460	{
1461	pFeatures->cMaxPhysAddrWidth = 32;
1462	pFeatures->cMaxLinearAddrWidth = 32;
1463	}
1464
1465	/* Standard features. */
1466	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1467	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1468	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1469	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1470	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1471	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1472	pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1473	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1474	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1475	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1476	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1477	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1478	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1479	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1480	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1481	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1482	pFeatures->fFma = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_FMA);
1483	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1484	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1485	pFeatures->fAesNi = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AES);
1486	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1487	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1488	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1489	pFeatures->fMtrr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MTRR);
1490	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1491	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1492	pFeatures->fCmpXchg8b = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CX8);
1493	pFeatures->fCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1494	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1495	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1496	pFeatures->fPopCnt = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_POPCNT);
1497	pFeatures->fRdRand = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_RDRAND);
1498	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1499	pFeatures->fPclMul = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
1500	pFeatures->fMovBe = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MOVBE);
1501	pFeatures->fF16c = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_F16C);
1502	if (pFeatures->fVmx)
1503	cpumExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1504
1505	/* Structured extended features. */
1506	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1507	if (pSxfLeaf0)
1508	{
1509	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1510	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1511	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1512	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1513	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1514	pFeatures->fBmi1 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI1);
1515	pFeatures->fBmi2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1516	pFeatures->fRdSeed = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_RDSEED);
1517	pFeatures->fHle = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_HLE);
1518	pFeatures->fRtm = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_RTM);
1519	pFeatures->fSha = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA);
1520	pFeatures->fAdx = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_ADX);
1521
1522	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1523	pFeatures->fIbrs = pFeatures->fIbpb;
1524	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1525	pFeatures->fSsbd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_SSBD);
1526	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1527	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1528	pFeatures->fCoreCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_CORECAP);
1529	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1530	}
1531	PCCPUMCPUIDLEAF const pSxfLeaf2 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 7, 2);
1532	if (pSxfLeaf2)
1533	{
1534	pFeatures->fPsfd = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_PSFD);
1535	pFeatures->fIpredCtrl = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL);
1536	pFeatures->fRrsbaCtrl = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL);
1537	pFeatures->fDdpdU = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U);
1538	pFeatures->fBhiCtrl = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL);
1539	pFeatures->fMcdtNo = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO);
1540	pFeatures->fUcLockDis = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS);
1541	pFeatures->fMonitorMitgNo = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO);
1542	}
1543
1544	/* MWAIT/MONITOR leaf. */
1545	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 5);
1546	if (pMWaitLeaf)
1547	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1548	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1549
1550	/* Extended features. */
1551	PCCPUMCPUIDLEAF const pExtLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1552	if (pExtLeaf)
1553	{
1554	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1555	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1556	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1557	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1558	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1559	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1560	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1561	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1562	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1563	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1564	pFeatures->fAbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_ABM);
1565	}
1566
1567	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1568	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1569
1570	if ( pExtLeaf
1571	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1572	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1573	{
1574	/* AMD features. */
1575	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1576	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1577	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1578	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1579	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1580	pFeatures->fPge \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
1581	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1582	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1583	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1584	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1585	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1586	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1587	pFeatures->fTbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_TBM);
1588	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1589
1590	if (pExtLeaf8)
1591	{
1592	pFeatures->fIbpb \|= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1593	pFeatures->fIbrs \|= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBRS);
1594	pFeatures->fStibp \|= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_STIBP);
1595	pFeatures->fSsbd \|= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD);
1596	pFeatures->fPsfd \|= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_PSFD);
1597	}
1598
1599	PCCPUMCPUIDLEAF pExtLeaf21 = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000021);
1600	if (pExtLeaf21)
1601	{
1602	/** @todo IBPB_BRTYPE is implied on Zen 1 & 2.
1603	* https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf */
1604	}
1605
1606	if (pFeatures->fSvm)
1607	{
1608	PCCPUMCPUIDLEAF pSvmLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1609	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1610	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1611	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1612	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1613	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1614	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1615	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1616	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1617	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1618	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1619	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1620	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1621	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1622	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1623	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
1624	pFeatures->fSvmX2Avic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_X2AVIC);
1625	pFeatures->fSvmSSSCheck = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SSSCHECK);
1626	pFeatures->fSvmSpecCtrl = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL);
1627	pFeatures->fSvmRoGpt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_ROGPT);
1628	pFeatures->fSvmHostMceOverride = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE);
1629	pFeatures->fSvmTlbiCtl = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TLBICTL);
1630	pFeatures->fSvmVNmi = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VNMI);
1631	pFeatures->fSvmIbsVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT);
1632	pFeatures->fSvmExtLvtAvicAccessChg = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG);
1633	pFeatures->fSvmNstVirtVmcbAddrChk = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK);
1634	pFeatures->fSvmBusLockThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD);
1635	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1636	}
1637	}
1638
1639	/*
1640	* Quirks.
1641	*/
1642	pFeatures->fLeakyFxSR = pExtLeaf
1643	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1644	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1645	&& pFeatures->uFamily >= 6 /* K7 and up */)
1646	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
1647
1648	/*
1649	* Max extended (/FPU) state.
1650	*/
1651	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1652	if (pFeatures->fXSaveRstor)
1653	{
1654	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1655	if (pXStateLeaf0)
1656	{
1657	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1658	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1659	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1660	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1661	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1662	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1663	{
1664	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1665
1666	/* (paranoia:) */
1667	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1668	if ( pXStateLeaf1
1669	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1670	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1671	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1672	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1673	}
1674	else
1675	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1676	pFeatures->fXSaveRstor = 0);
1677	}
1678	else
1679	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1680	pFeatures->fXSaveRstor = 0);
1681	}
1682
1683	/*
1684	* Enable or disable VEX support depending on whether it's needed. Note that AVX,
1685	* BMI1, and BMI2 all use VEX encoding but are theoretically independent of each other.
1686	*/
1687	pFeatures->fVex = pFeatures->fAvx \| pFeatures->fBmi1 \| pFeatures->fBmi2;
1688	}
1689	else
1690	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1691
1692	cpumCpuIdExplodeFeaturesX86SetSummaryBits(pFeatures);
1693	return VINF_SUCCESS;
1694	}
1695
1696
1697	/**
1698	* Helper for extracting feature bits from IA32_ARCH_CAPABILITIES.
1699	*/
1700	void cpumCpuIdExplodeArchCapabilities(CPUMFEATURESX86 *pFeatures, bool fHasArchCap, uint64_t fArchVal)
1701	{
1702	Assert(fHasArchCap \|\| fArchVal == 0);
1703	pFeatures->fArchCap = fHasArchCap;
1704	pFeatures->fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
1705	pFeatures->fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
1706	pFeatures->fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
1707	pFeatures->fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
1708	pFeatures->fArchSsbNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_SSB_NO);
1709	pFeatures->fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
1710	pFeatures->fArchIfPschangeMscNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO);
1711	pFeatures->fArchTsxCtrl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_TSX_CTRL);
1712	pFeatures->fArchTaaNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_TAA_NO);
1713	pFeatures->fArchMiscPackageCtrls = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS);
1714	pFeatures->fArchEnergyFilteringCtl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL);
1715	pFeatures->fArchDoitm = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_DOITM);
1716	pFeatures->fArchSbdrSsdpNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO);
1717	pFeatures->fArchFbsdpNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_FBSDP_NO);
1718	pFeatures->fArchPsdpNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_PSDP_NO);
1719	pFeatures->fArchFbClear = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_FB_CLEAR);
1720	pFeatures->fArchFbClearCtrl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL);
1721	pFeatures->fArchRrsba = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RRSBA);
1722	pFeatures->fArchBhiNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_BHI_NO);
1723	pFeatures->fArchXapicDisableStatus = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS);
1724	pFeatures->fArchOverclockingStatus = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS);
1725	pFeatures->fArchPbrsbNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_PBRSB_NO);
1726	pFeatures->fArchGdsCtrl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_GDS_CTRL);
1727	pFeatures->fArchGdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_GDS_NO);
1728	pFeatures->fArchRfdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RFDS_NO);
1729	pFeatures->fArchRfdsClear = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RFDS_CLEAR);
1730	pFeatures->fArchIgnUmonitorSupport = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IGN_UMONITOR_SUPPORT);
1731	pFeatures->fArchMonUmonMitigSupport= RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MON_UMON_MITIG_SUPPORT);
1732	}
1733
1734
1735	# if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
1736	/**
1737	* Sets the guest IA32_ARCH_CAPABILITIES value and associated feature bits.
1738	*/
1739	void cpumCpuIdSetGuestArchCapabilities(PVMCC pVM, bool fHasArchCap, uint64_t fArchVal, bool fHasIbrs)
1740	{
1741	if (!fHasArchCap)
1742	fArchVal = 0;
1743	else if (!fHasIbrs)
1744	fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
1745	fArchVal &= ~( RT_BIT_64(9)
1746	\| MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS
1747	\| MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL
1748	\| MSR_IA32_ARCH_CAP_F_DOITM
1749	\| RT_BIT_64(16)
1750	\| RT_BIT_64(22)
1751	\| MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL
1752	/** @todo mask off MSR_IA32_ARCH_CAP_F_RRSBA ? */
1753	\| MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS
1754	\| MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS /** @todo expose IA32_OVERCLOCKING_STATUS */
1755	\| MSR_IA32_ARCH_CAP_F_GDS_CTRL
1756	\| MSR_IA32_ARCH_CAP_F_IGN_UMONITOR_SUPPORT
1757	\| MSR_IA32_ARCH_CAP_F_MON_UMON_MITIG_SUPPORT
1758	\| ~(RT_BIT_64(31) - 1U)
1759	);
1760	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
1761
1762	cpumCpuIdExplodeArchCapabilities(&pVM->cpum.s.GuestFeatures, fHasArchCap, fArchVal);
1763	LogRel(("CPUM: Guest IA32_ARCH_CAPABILITIES = %#RX64\n", fArchVal));
1764	}
1765	# endif
1766
1767
1768	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1769	/**
1770	* Sets host & guest feature bits & MSRs related to IA32_ARCH_CAPABILITIES.
1771	*
1772	* ASSUMES this is called after the basic guest features has been exploded.
1773	*/
1774	VMM_INT_DECL(void) CPUMCpuIdApplyX86HostArchCapabilities(PVMCC pVM, bool fHasArchCap, uint64_t fHostArchVal)
1775	{
1776	cpumCpuIdExplodeArchCapabilities(const_cast<CPUMFEATURESX86 *>(&pVM->cpum.s.HostFeatures.s), fHasArchCap, fHostArchVal);
1777	LogRel(("CPUM: Host IA32_ARCH_CAPABILITIES = %#RX64\n", fHostArchVal));
1778
1779	# if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
1780	# ifdef VBOX_VMM_TARGET_AGNOSTIC
1781	/** @todo arm on x86: check VM target. */
1782	# endif
1783	cpumCpuIdSetGuestArchCapabilities(pVM, fHasArchCap && pVM->cpum.s.GuestFeatures.fArchCap,
1784	fHostArchVal, pVM->cpum.s.GuestFeatures.fIbrs);
1785	# endif
1786	}
1787	# endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) */
1788
1789	#endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
1790
1791	#if defined(RT_ARCH_ARM64)
1792	/**
1793	* Collects the ID registers from an ARMv8 host.
1794	*
1795	* This isn't trivial an all hosts when running in userland and there is no
1796	* support driver handy.
1797	*/
1798	VMMDECL(int) CPUMCpuIdCollectIdRegistersFromArmV8Host(PCPUMARMV8IDREGS pIdRegs)
1799	{
1800	# ifdef _MSC_VER
1801	# define READ_SYS_REG(a_u64Dst, a_SysRegName) do { \
1802	(a_u64Dst) = (uint64_t)_ReadStatusReg(RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName) & 0x7fff); \
1803	} while (0)
1804	# else
1805	# define READ_SYS_REG(a_u64Dst, a_SysRegName) do { \
1806	__asm__ __volatile__ ("mrs %0, " #a_SysRegName : "=r" (a_u64Dst)); \
1807	} while (0)
1808	# endif
1809
1810	RT_ZERO(*pIdRegs);
1811
1812	/*
1813	* CTR_EL0 can be trapped when executed in L0 (SCTLR_EL0.UCT) and macOS
1814	* & Windows does so by default. Linux OTOH typically exposes all the
1815	* feature registers to user land with some sanitizing.
1816	*/
1817	# if !defined(IN_RING3) \|\| defined(RT_OS_LINUX)
1818	READ_SYS_REG(pIdRegs->u64RegCtrEl0, CTR_EL0);
1819	# endif
1820	READ_SYS_REG(pIdRegs->u64RegDczidEl0, DCZID_EL0);
1821
1822	# if defined(IN_RING0) \|\| defined(RT_OS_LINUX)
1823	# ifdef IN_RING3
1824	if (getauxval(AT_HWCAP) & HWCAP_CPUID)
1825	# endif
1826	{
1827	READ_SYS_REG(pIdRegs->u64RegIdAa64Pfr0El1, ID_AA64PFR0_EL1);
1828	READ_SYS_REG(pIdRegs->u64RegIdAa64Pfr1El1, ID_AA64PFR1_EL1);
1829	READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr0El1, ID_AA64DFR0_EL1);
1830	READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr1El1, ID_AA64DFR1_EL1);
1831	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr2El1, ID_AA64DFR2_EL1);
1832	READ_SYS_REG(pIdRegs->u64RegIdAa64Afr0El1, ID_AA64AFR0_EL1);
1833	READ_SYS_REG(pIdRegs->u64RegIdAa64Afr1El1, ID_AA64AFR1_EL1);
1834	READ_SYS_REG(pIdRegs->u64RegIdAa64Isar0El1, ID_AA64ISAR0_EL1);
1835	READ_SYS_REG(pIdRegs->u64RegIdAa64Isar1El1, ID_AA64ISAR1_EL1);
1836	READ_SYS_REG(pIdRegs->u64RegIdAa64Isar2El1, ID_AA64ISAR2_EL1);
1837	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Isar3El1, ID_AA64ISAR3_EL1);
1838	READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr0El1, ID_AA64MMFR0_EL1);
1839	READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr1El1, ID_AA64MMFR1_EL1);
1840	READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr2El1, ID_AA64MMFR2_EL1);
1841	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr3El1, ID_AA64MMFR3_EL1);
1842	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr4El1, ID_AA64MMFR4_EL1);
1843	READ_SYS_REG(pIdRegs->u64RegClidrEl1, CLIDR_EL1);
1844
1845	/// @todo READ_SYS_REG(pIdRegs->uMainIdRegEl1, MIDR_EL1);
1846	/// @todo READ_SYS_REG(pIdRegs->uMpIdRegEl1, MPIDR_EL1);
1847	/// @todo READ_SYS_REG(pIdRegs->uRevIdRegEl1, REVIDR_EL1);
1848	return VINF_SUCCESS;
1849	}
1850	# endif
1851	# ifndef IN_RING0
1852	/** @todo On darwin we should just cache the information (CPU DB) and figure
1853	* out which Apple Mx we're running on. */
1854	/** @todo Make the info available via the support driver... */
1855	return VINF_SUCCESS;
1856	# endif
1857	}
1858	#endif /* defined(RT_ARCH_ARM64) */
1859
1860	#if defined(RT_ARCH_ARM64) \|\| defined(VBOX_VMM_TARGET_ARMV8)
1861	/**
1862	* Explode the CPU features from the given ID registers.
1863	*
1864	* @returns VBox status code.
1865	* @param pIdRegs The ID registers to explode the features from.
1866	* @param pFeatures Where to store the features to.
1867	*/
1868	int cpumCpuIdExplodeFeaturesArmV8(PCCPUMARMV8IDREGS pIdRegs, CPUMFEATURESARMV8 *pFeatures)
1869	{
1870	uint64_t u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1;
1871
1872	static uint8_t s_aPaRange[] = { 32, 36, 40, 42, 44, 48, 52 };
1873	AssertLogRelMsgReturn(RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE) < RT_ELEMENTS(s_aPaRange),
1874	("CPUM: Invalid/Unsupported PARange value in ID_AA64MMFR0_EL1 register: %u\n",
1875	RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)),
1876	VERR_CPUM_IPE_1);
1877
1878	pFeatures->cMaxPhysAddrWidth = s_aPaRange[RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)];
1879	pFeatures->fTGran4K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN4) != ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL;
1880	pFeatures->fTGran16K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN16) != ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL;
1881	pFeatures->fTGran64K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN64) != ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL;
1882
1883	/* ID_AA64ISAR0_EL1 features. */
1884	u64IdReg = pIdRegs->u64RegIdAa64Isar0El1;
1885	pFeatures->fAes = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED;
1886	pFeatures->fPmull = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL;
1887	pFeatures->fSha1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA1) >= ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED;
1888	pFeatures->fSha256 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256;
1889	pFeatures->fSha512 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512;
1890	pFeatures->fCrc32 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_CRC32) >= ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED;
1891	pFeatures->fLse = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_ATOMIC) >= ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED;
1892	pFeatures->fTme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TME) >= ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED;
1893	pFeatures->fRdm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RDM) >= ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED;
1894	pFeatures->fSha3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA3) >= ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED;
1895	pFeatures->fSm3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM3) >= ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED;
1896	pFeatures->fSm4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM4) >= ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED;
1897	pFeatures->fDotProd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_DP) >= ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED;
1898	pFeatures->fFhm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_FHM) >= ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED;
1899	pFeatures->fFlagM = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED;
1900	pFeatures->fFlagM2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2;
1901	pFeatures->fTlbios = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED;
1902	pFeatures->fTlbirange = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE;
1903	pFeatures->fRng = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RNDR) >= ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED;
1904
1905	/* ID_AA64ISAR1_EL1 features. */
1906	u64IdReg = pIdRegs->u64RegIdAa64Isar1El1;
1907	pFeatures->fDpb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED;
1908	pFeatures->fDpb2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2;
1909
1910	/* PAuth using QARMA5. */
1911	pFeatures->fPacQarma5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) != ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL;
1912	if (pFeatures->fPacQarma5)
1913	{
1914	pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH;
1915	pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC;
1916	pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2;
1917	pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC;
1918	pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE;
1919	}
1920
1921	/* PAuth using implementation defined algorithm. */
1922	pFeatures->fPacImp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) != ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL;
1923	if (pFeatures->fPacQarma5)
1924	{
1925	pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH;
1926	pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC;
1927	pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2;
1928	pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC;
1929	pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE;
1930	}
1931
1932	pFeatures->fJscvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FJCVTZS) >= ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED;
1933	pFeatures->fFcma = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FCMA) >= ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED;
1934	pFeatures->fLrcpc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED;
1935	pFeatures->fLrcpc2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2;
1936	pFeatures->fFrintts = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FRINTTS) >= ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED;
1937	pFeatures->fSb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SB) >= ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED;
1938	pFeatures->fSpecres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SPECRES) >= ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED;
1939	pFeatures->fBf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16;
1940	pFeatures->fEbf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16;
1941	pFeatures->fDgh = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DGH) >= ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED;
1942	pFeatures->fI8mm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_I8MM) >= ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED;
1943	pFeatures->fXs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_XS) >= ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED;
1944	pFeatures->fLs64 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED;
1945	pFeatures->fLs64V = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V;
1946	pFeatures->fLs64Accdata = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA;
1947
1948	/* ID_AA64ISAR2_EL1 features. */
1949	u64IdReg = pIdRegs->u64RegIdAa64Isar2El1;
1950	pFeatures->fWfxt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_WFXT) >= ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED;
1951	pFeatures->fRpres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_RPRES) >= ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED;
1952
1953	/* PAuth using QARMA3. */
1954	pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_GPA3) >= ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED;
1955	pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) != ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL;
1956	if (pFeatures->fPacQarma5)
1957	{
1958	pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH;
1959	pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC;
1960	pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2;
1961	pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC;
1962	pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE;
1963	}
1964
1965	pFeatures->fMops = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_MOPS) >= ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED;
1966	pFeatures->fHbc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_BC) >= ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED;
1967	pFeatures->fConstPacField = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_PACFRAC) >= ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE;
1968
1969	/* ID_AA64PFR0_EL1 */
1970	u64IdReg = pIdRegs->u64RegIdAa64Pfr0El1;
1971	/* The FP and AdvSIMD field must have the same value. */
1972	Assert(RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD));
1973	pFeatures->fFp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) != ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL;
1974	pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP;
1975	pFeatures->fAdvSimd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) != ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL;
1976	pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) == ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP;
1977	pFeatures->fRas = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED;
1978	pFeatures->fRasV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_V1P1;
1979	pFeatures->fSve = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SVE) >= ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED;
1980	pFeatures->fSecEl2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SEL2) >= ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED;
1981	pFeatures->fAmuV1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1;
1982	pFeatures->fAmuV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1P1;
1983	pFeatures->fDit = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_DIT) >= ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED;
1984	pFeatures->fRme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RME) >= ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED;
1985	pFeatures->fCsv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED;
1986	pFeatures->fCsv2v3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED;
1987
1988	/* ID_AA64PFR1_EL1 */
1989	u64IdReg = pIdRegs->u64RegIdAa64Pfr1El1;
1990	pFeatures->fBti = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_BT) >= ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED;
1991	pFeatures->fSsbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED;
1992	pFeatures->fSsbs2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS;
1993	pFeatures->fMte = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY;
1994	pFeatures->fMte2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL;
1995	pFeatures->fMte3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK;
1996	/** @todo RAS_frac, MPAM_frac, CSV2_frac. */
1997	pFeatures->fSme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED;
1998	pFeatures->fSme2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SME2;
1999	pFeatures->fRngTrap = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_RNDRTRAP) >= ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED;
2000	pFeatures->fNmi = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_NMI) >= ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED;
2001
2002	/* ID_AA64MMFR0_EL1 */
2003	u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1;
2004	pFeatures->fExs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_EXS) >= ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED;
2005	pFeatures->fFgt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_FGT) >= ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED;
2006	pFeatures->fEcv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_ECV) >= ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED;
2007
2008	/* ID_AA64MMFR1_EL1 */
2009	u64IdReg = pIdRegs->u64RegIdAa64Mmfr1El1;
2010	pFeatures->fHafdbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HAFDBS) >= ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED;
2011	pFeatures->fVmid16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VMIDBITS) >= ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16;
2012	pFeatures->fVhe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VHE) >= ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED;
2013	pFeatures->fHpds = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED;
2014	pFeatures->fHpds2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2;
2015	pFeatures->fLor = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_LO) >= ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED;
2016	pFeatures->fPan = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED;
2017	pFeatures->fPan2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2;
2018	pFeatures->fPan3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3;
2019	pFeatures->fXnx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_XNX) >= ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED;
2020	pFeatures->fTwed = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TWED) >= ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED;
2021	pFeatures->fEts2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_ETS) >= ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED;
2022	pFeatures->fHcx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HCX) >= ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED;
2023	pFeatures->fAfp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_AFP) >= ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED;
2024	pFeatures->fNTlbpa = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_NTLBPA) >= ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY;
2025	pFeatures->fTidcp1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TIDCP1) >= ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED;
2026	pFeatures->fCmow = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_CMOW) >= ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED;
2027
2028	/* ID_AA64MMFR2_EL1 */
2029	u64IdReg = pIdRegs->u64RegIdAa64Mmfr2El1;
2030	pFeatures->fTtcnp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CNP) >= ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED;
2031	pFeatures->fUao = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_UAO) >= ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED;
2032	pFeatures->fLsmaoc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_LSM) >= ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED;
2033	pFeatures->fIesb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IESB) >= ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED;
2034	pFeatures->fLva = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_VARANGE) >= ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN;
2035	pFeatures->fCcidx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CCIDX) >= ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT;
2036	pFeatures->fNv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED;
2037	pFeatures->fNv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2;
2038	pFeatures->fTtst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_ST) >= ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED;
2039	pFeatures->fLse2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_AT) >= ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED;
2040	pFeatures->fIdst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IDS) >= ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H;
2041	pFeatures->fS2Fwb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_FWB) >= ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED;
2042	pFeatures->fTtl = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_TTL) >= ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED;
2043	pFeatures->fEvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_EVT) >= ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED;
2044	pFeatures->fE0Pd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_E0PD) >= ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED;
2045
2046	/* ID_AA64DFR0_EL1 */
2047	u64IdReg = pIdRegs->u64RegIdAa64Dfr0El1;
2048	pFeatures->fDebugV8p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE;
2049	pFeatures->fDebugV8p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2;
2050	pFeatures->fDebugV8p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4;
2051	pFeatures->fDebugV8p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8;
2052	pFeatures->fPmuV3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3;
2053	pFeatures->fPmuV3p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1;
2054	pFeatures->fPmuV3p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4;
2055	pFeatures->fPmuV3p5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5;
2056	pFeatures->fPmuV3p7 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7;
2057	pFeatures->fPmuV3p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8;
2058	pFeatures->fSpe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED;
2059	pFeatures->fSpeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1;
2060	pFeatures->fSpeV1p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2;
2061	pFeatures->fSpeV1p3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3;
2062	pFeatures->fDoubleLock = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK) == ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED;
2063	pFeatures->fTrf = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEFILT) >= ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED;
2064	pFeatures->fTrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER) >= ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED;
2065	pFeatures->fMtPmu = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_MTPMU) == ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED;
2066	pFeatures->fBrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED;
2067	pFeatures->fBrbeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1;
2068	pFeatures->fHpmn0 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_HPMN0) >= ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED;
2069
2070	return VINF_SUCCESS;
2071	}
2072	#endif /* defined(RT_ARCH_ARM64) \|\| defined(VBOX_VMM_TARGET_ARMV8) */
2073

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source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp

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