TRPM.cpp@ 25816

最後變更在這個檔案從25816是 25816,由 vboxsync 提交於 15 年前
CPU hotplug: Merge the first patch. Resets a CPU state if a CPU was removed from the VM
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行
1	/* $Id: TRPM.cpp 25816 2010-01-13 21:05:35Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_trpm TRPM - The Trap Monitor
23	*
24	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
25	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
26	* hardware assisted mode.
27	*
28	* Note first, the following will use trap as a collective term for faults,
29	* aborts and traps.
30	*
31	* @see grp_trpm
32	*
33	*
34	* @section sec_trpm_rc Raw-Mode Context
35	*
36	* When executing in the raw-mode context, TRPM will be managing the IDT and
37	* processing all traps and interrupts. It will also monitor the guest IDT
38	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
39	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
40	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
41	*
42	* External interrupts will be forwarded to the host context by the quickest
43	* possible route where they will be reasserted. The other events will be
44	* categorized into virtualization traps, genuine guest traps and hypervisor
45	* traps. The latter group may be recoverable depending on when they happen and
46	* whether there is a handler for it, otherwise it will cause a guru meditation.
47	*
48	* TRPM disgishishes the between the first two (virt and guest traps) and the
49	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
50	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
51	* dispatcher tables, one ad-hoc for one time traps registered via
52	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
53	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
54	*
55	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
56	* part), will call up the other VMM sub-systems depending on what it things
57	* happens. The two most busy traps are page faults (\#PF) and general
58	* protection fault/trap (\#GP).
59	*
60	* Before resuming guest code after having taken a virtualization trap or
61	* injected a guest trap, TRPM will check for pending forced action and
62	* every now and again let TM check for timed out timers. This allows code that
63	* is being executed as part of virtualization traps to signal ring-3 exits,
64	* page table resyncs and similar without necessarily using the status code. It
65	* also make sure we're more responsive to timers and requests from other
66	* threads (necessarily running on some different core/cpu in most cases).
67	*
68	*
69	* @section sec_trpm_all All Contexts
70	*
71	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
72	* in raw-mode and when in hardware assisted mode. See TRPMInject().
73	*
74	*/
75
76	/*******************************************************************************
77	* Header Files *
78	*******************************************************************************/
79	#define LOG_GROUP LOG_GROUP_TRPM
80	#include <VBox/trpm.h>
81	#include <VBox/cpum.h>
82	#include <VBox/selm.h>
83	#include <VBox/ssm.h>
84	#include <VBox/pdmapi.h>
85	#include <VBox/pgm.h>
86	#include <VBox/dbgf.h>
87	#include <VBox/mm.h>
88	#include <VBox/stam.h>
89	#include <VBox/csam.h>
90	#include <VBox/patm.h>
91	#include "TRPMInternal.h"
92	#include <VBox/vm.h>
93	#include <VBox/em.h>
94	#include <VBox/rem.h>
95	#include <VBox/hwaccm.h>
96
97	#include <VBox/err.h>
98	#include <VBox/param.h>
99	#include <VBox/log.h>
100	#include <iprt/assert.h>
101	#include <iprt/asm.h>
102	#include <iprt/string.h>
103	#include <iprt/alloc.h>
104
105
106	/*******************************************************************************
107	* Structures and Typedefs *
108	*******************************************************************************/
109	/**
110	* Trap handler function.
111	* @todo need to specialize this as we go along.
112	*/
113	typedef enum TRPMHANDLER
114	{
115	/** Generic Interrupt handler. */
116	TRPM_HANDLER_INT = 0,
117	/** Generic Trap handler. */
118	TRPM_HANDLER_TRAP,
119	/** Trap 8 (\#DF) handler. */
120	TRPM_HANDLER_TRAP_08,
121	/** Trap 12 (\#MC) handler. */
122	TRPM_HANDLER_TRAP_12,
123	/** Max. */
124	TRPM_HANDLER_MAX
125	} TRPMHANDLER, *PTRPMHANDLER;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** Preinitialized IDT.
132	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133	* will use to pick the right address. The u16SegSel is always VMM CS.
134	*/
135	static VBOXIDTE_GENERIC g_aIdt[256] =
136	{
137	/* special trap handler - still, this is an interrupt gate not a trap gate... */
138	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139	/* generic trap handler. */
140	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141	/* special interrupt handler. */
142	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143	/* generic interrupt handler. */
144	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145	/* special task gate IDT entry (for critical exceptions like #DF). */
146	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147	/* draft, fixme later when the handler is written. */
148	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150	/* N - M M - T - C - D i */
151	/* o - n o - y - o - e p */
152	/* - e n - p - d - s t */
153	/* - i - e - e - c . */
154	/* - c - - - r */
155	/* ============================================================= */
156	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158	#ifdef VBOX_WITH_NMI
159	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160	#else
161	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162	#endif
163	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416	#undef IDTE_TRAP
417	#undef IDTE_TRAP_GEN
418	#undef IDTE_INT
419	#undef IDTE_INT_GEN
420	#undef IDTE_TASK
421	#undef IDTE_UNUSED
422	#undef IDTE_RESERVED
423	};
424
425
426	/** Enable or disable tracking of Guest's IDT. */
427	#define TRPM_TRACK_GUEST_IDT_CHANGES
428
429	/** Enable or disable tracking of Shadow IDT. */
430	#define TRPM_TRACK_SHADOW_IDT_CHANGES
431
432	/** TRPM saved state version. */
433	#define TRPM_SAVED_STATE_VERSION 9
434	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
435
436
437	/*******************************************************************************
438	* Internal Functions *
439	*******************************************************************************/
440	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
441	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
442	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
443
444
445	/**
446	* Initializes the Trap Manager
447	*
448	* @returns VBox status code.
449	* @param pVM The VM to operate on.
450	*/
451	VMMR3DECL(int) TRPMR3Init(PVM pVM)
452	{
453	LogFlow(("TRPMR3Init\n"));
454
455	/*
456	* Assert sizes and alignments.
457	*/
458	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
459	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
460	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
461	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
462
463	/*
464	* Initialize members.
465	*/
466	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
467	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
468
469	for (VMCPUID i = 0; i < pVM->cCpus; i++)
470	{
471	PVMCPU pVCpu = &pVM->aCpus[i];
472
473	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
474	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
475	pVCpu->trpm.s.uActiveVector = ~0;
476	}
477
478	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
479	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
480	pVM->trpm.s.fDisableMonitoring = false;
481	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
482
483	/*
484	* Read the configuration (if any).
485	*/
486	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
487	if (pTRPMNode)
488	{
489	bool f;
490	int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
491	if (RT_SUCCESS(rc))
492	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
493	}
494
495	/* write config summary to log */
496	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
497	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
498
499	/*
500	* Initialize the IDT.
501	* The handler addresses will be set in the TRPMR3Relocate() function.
502	*/
503	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
504	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
505
506	/*
507	* Register the saved state data unit.
508	*/
509	int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
510	NULL, NULL, NULL,
511	NULL, trpmR3Save, NULL,
512	NULL, trpmR3Load, NULL);
513	if (RT_FAILURE(rc))
514	return rc;
515
516	/*
517	* Statistics.
518	*/
519	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
520	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
521	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
522
523	/* traps */
524	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
525	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
526	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
527	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
528	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
529	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
530	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
531	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
532	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
533	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
534	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
535	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segemnt not present.");
536	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
537	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
538	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
539	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
540	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
541	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
542	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
543	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
544
545	#ifdef VBOX_WITH_STATISTICS
546	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 255, 8, MM_TAG_STAM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
547	AssertRCReturn(rc, rc);
548	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
549	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
550	for (unsigned i = 0; i < 255; i++)
551	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
552	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
553	#endif
554
555	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
556	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
557	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
558	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
559	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
560	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
561
562	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
563	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
564
565	/*
566	* Default action when entering raw mode for the first time
567	*/
568	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
569	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
570	return 0;
571	}
572
573
574	/**
575	* Applies relocations to data and code managed by this component.
576	*
577	* This function will be called at init and whenever the VMM need
578	* to relocate itself inside the GC.
579	*
580	* @param pVM The VM handle.
581	* @param offDelta Relocation delta relative to old location.
582	*/
583	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
584	{
585	/* Only applies to raw mode which supports only 1 VCPU. */
586	PVMCPU pVCpu = &pVM->aCpus[0];
587
588	LogFlow(("TRPMR3Relocate\n"));
589	/*
590	* Get the trap handler addresses.
591	*
592	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
593	* would make init order impossible if we should assert the presence of these
594	* exports in TRPMR3Init().
595	*/
596	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX] = {0};
597	int rc;
598	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
599	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
600
601	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
602	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
603
604	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
605	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
606
607	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
608	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
609
610	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
611
612	/*
613	* Iterate the idt and set the addresses.
614	*/
615	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
616	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
617	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
618	{
619	if ( pIdte->Gen.u1Present
620	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
621	)
622	{
623	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
624	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
625	switch (pIdteTemplate->u16OffsetLow)
626	{
627	/*
628	* Generic handlers have different entrypoints for each possible
629	* vector number. These entrypoints makes a sort of an array with
630	* 8 byte entries where the vector number is the index.
631	* See TRPMGCHandlersA.asm for details.
632	*/
633	case TRPM_HANDLER_INT:
634	case TRPM_HANDLER_TRAP:
635	Offset += i * 8;
636	break;
637	case TRPM_HANDLER_TRAP_12:
638	break;
639	case TRPM_HANDLER_TRAP_08:
640	/* Handle #DF Task Gate in special way. */
641	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
642	pIdte->Gen.u16OffsetLow = 0;
643	pIdte->Gen.u16OffsetHigh = 0;
644	SELMSetTrap8EIP(pVM, Offset);
645	continue;
646	}
647	/* (non-task gates only ) */
648	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
649	pIdte->Gen.u16OffsetHigh = Offset >> 16;
650	pIdte->Gen.u16SegSel = SelCS;
651	}
652	}
653
654	/*
655	* Update IDTR (limit is including!).
656	*/
657	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
658
659	if (!pVM->trpm.s.fDisableMonitoring)
660	{
661	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
662	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
663	{
664	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
665	AssertRC(rc);
666	}
667	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
668	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
669	0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
670	AssertRC(rc);
671	#endif
672	}
673
674	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
675	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
676	{
677	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
678	{
679	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
680	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
681	}
682
683	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
684	{
685	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
686	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
687
688	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
689	pHandler += offDelta;
690
691	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
692	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
693	}
694	}
695
696	#ifdef VBOX_WITH_STATISTICS
697	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
698	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
699	#endif
700	}
701
702
703	/**
704	* Terminates the Trap Manager
705	*
706	* @returns VBox status code.
707	* @param pVM The VM to operate on.
708	*/
709	VMMR3DECL(int) TRPMR3Term(PVM pVM)
710	{
711	NOREF(pVM);
712	return 0;
713	}
714
715	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
716	{
717	pVCpu->trpm.s.uActiveVector = ~0;
718	}
719
720	/**
721	* The VM is being reset.
722	*
723	* For the TRPM component this means that any IDT write monitors
724	* needs to be removed, any pending trap cleared, and the IDT reset.
725	*
726	* @param pVM VM handle.
727	*/
728	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
729	{
730	/*
731	* Deregister any virtual handlers.
732	*/
733	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
734	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
735	{
736	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
737	{
738	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
739	AssertRC(rc);
740	}
741	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
742	}
743	pVM->trpm.s.GuestIdtr.cbIdt = 0;
744	#endif
745
746	/*
747	* Reinitialize other members calling the relocator to get things right.
748	*/
749	for (VMCPUID i = 0; i < pVM->cCpus; i++)
750	{
751	PVMCPU pVCpu = &pVM->aCpus[i];
752	TRPMR3ResetCpu(pVCpu);
753	}
754	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
755	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
756	TRPMR3Relocate(pVM, 0);
757
758	/*
759	* Default action when entering raw mode for the first time
760	*/
761	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
762	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
763	}
764
765
766	/**
767	* Execute state save operation.
768	*
769	* @returns VBox status code.
770	* @param pVM VM Handle.
771	* @param pSSM SSM operation handle.
772	*/
773	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
774	{
775	PTRPM pTrpm = &pVM->trpm.s;
776	LogFlow(("trpmR3Save:\n"));
777
778	/*
779	* Active and saved traps.
780	*/
781	for (VMCPUID i = 0; i < pVM->cCpus; i++)
782	{
783	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
784	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
785	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
786	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
787	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
788	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
789	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
790	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
791	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
792	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
793	}
794	SSMR3PutBool(pSSM, pTrpm->fDisableMonitoring);
795	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
796	SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT));
797	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
798	SSMR3PutU32(pSSM, ~0); /* separator. */
799
800	/*
801	* Save any trampoline gates.
802	*/
803	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
804	{
805	if (pTrpm->aGuestTrapHandler[iTrap])
806	{
807	SSMR3PutU32(pSSM, iTrap);
808	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
809	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
810	}
811	}
812
813	return SSMR3PutU32(pSSM, ~0); /* terminator */
814	}
815
816
817	/**
818	* Execute state load operation.
819	*
820	* @returns VBox status code.
821	* @param pVM VM Handle.
822	* @param pSSM SSM operation handle.
823	* @param uVersion Data layout version.
824	* @param uPass The data pass.
825	*/
826	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
827	{
828	LogFlow(("trpmR3Load:\n"));
829	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
830
831	/*
832	* Validate version.
833	*/
834	if ( uVersion != TRPM_SAVED_STATE_VERSION
835	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
836	{
837	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
838	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
839	}
840
841	/*
842	* Call the reset function to kick out any handled gates and other potential trouble.
843	*/
844	TRPMR3Reset(pVM);
845
846	/*
847	* Active and saved traps.
848	*/
849	PTRPM pTrpm = &pVM->trpm.s;
850
851	if (uVersion == TRPM_SAVED_STATE_VERSION)
852	{
853	for (VMCPUID i = 0; i < pVM->cCpus; i++)
854	{
855	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
856	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
857	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
858	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
859	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
860	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
861	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
862	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
863	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
864	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
865	}
866
867	SSMR3GetBool(pSSM, &pVM->trpm.s.fDisableMonitoring);
868	}
869	else
870	{
871	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
872	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
873	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
874	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
875	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
876	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
877	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
878	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
879	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
880	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
881
882	RTGCUINT fDisableMonitoring;
883	SSMR3GetGCUInt(pSSM, &fDisableMonitoring);
884	pTrpm->fDisableMonitoring = !!fDisableMonitoring;
885	}
886
887	RTUINT fSyncIDT;
888	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
889	if (RT_FAILURE(rc))
890	return rc;
891	if (fSyncIDT & ~1)
892	{
893	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
894	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
895	}
896	if (fSyncIDT)
897	{
898	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
899	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
900	}
901	/* else: cleared by reset call above. */
902
903	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
904
905	/* check the separator */
906	uint32_t u32Sep;
907	rc = SSMR3GetU32(pSSM, &u32Sep);
908	if (RT_FAILURE(rc))
909	return rc;
910	if (u32Sep != (uint32_t)~0)
911	{
912	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
913	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
914	}
915
916	/*
917	* Restore any trampoline gates.
918	*/
919	for (;;)
920	{
921	/* gate number / terminator */
922	uint32_t iTrap;
923	rc = SSMR3GetU32(pSSM, &iTrap);
924	if (RT_FAILURE(rc))
925	return rc;
926	if (iTrap == (uint32_t)~0)
927	break;
928	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
929	\|\| pTrpm->aGuestTrapHandler[iTrap])
930	{
931	AssertMsgFailed(("iTrap=%#x\n", iTrap));
932	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
933	}
934
935	/* restore the IDT entry. */
936	RTGCPTR GCPtrHandler;
937	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
938	VBOXIDTE Idte;
939	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
940	if (RT_FAILURE(rc))
941	return rc;
942	Assert(GCPtrHandler);
943	pTrpm->aIdt[iTrap] = Idte;
944	}
945
946	return VINF_SUCCESS;
947	}
948
949
950	/**
951	* Check if gate handlers were updated
952	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
953	*
954	* @returns VBox status code.
955	* @param pVM The VM handle.
956	* @param pVCpu The VMCPU handle.
957	*/
958	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
959	{
960	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
961	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
962	int rc;
963
964	if (pVM->trpm.s.fDisableMonitoring)
965	{
966	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
967	return VINF_SUCCESS; /* Nothing to do */
968	}
969
970	if (fRawRing0 && CSAMIsEnabled(pVM))
971	{
972	/* Clear all handlers */
973	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
974	/** @todo inefficient, but simple */
975	for (unsigned iGate = 0; iGate < 256; iGate++)
976	trpmClearGuestTrapHandler(pVM, iGate);
977
978	/* Scan them all (only the first time) */
979	CSAMR3CheckGates(pVM, 0, 256);
980	}
981
982	/*
983	* Get the IDTR.
984	*/
985	VBOXIDTR IDTR;
986	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
987	if (!IDTR.cbIdt)
988	{
989	Log(("No IDT entries...\n"));
990	return DBGFSTOP(pVM);
991	}
992
993	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
994	/*
995	* Check if Guest's IDTR has changed.
996	*/
997	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
998	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
999	{
1000	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1001	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1002	{
1003	/*
1004	* [Re]Register write virtual handler for guest's IDT.
1005	*/
1006	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1007	{
1008	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1009	AssertRCReturn(rc, rc);
1010	}
1011	/* limit is including */
1012	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1013	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1014
1015	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1016	{
1017	/* Could be a conflict with CSAM */
1018	CSAMR3RemovePage(pVM, IDTR.pIdt);
1019	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1020	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1021
1022	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1023	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1024	}
1025
1026	AssertRCReturn(rc, rc);
1027	}
1028
1029	/* Update saved Guest IDTR. */
1030	pVM->trpm.s.GuestIdtr = IDTR;
1031	}
1032	#endif
1033
1034	/*
1035	* Sync the interrupt gate.
1036	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1037	*/
1038	X86DESC Idte3;
1039	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1040	if (RT_FAILURE(rc))
1041	{
1042	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1043	return DBGFSTOP(pVM);
1044	}
1045	AssertRCReturn(rc, rc);
1046	if (fRawRing0)
1047	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1048	else
1049	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1050
1051	/*
1052	* Clear the FF and we're done.
1053	*/
1054	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1055	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1056	return VINF_SUCCESS;
1057	}
1058
1059
1060	/**
1061	* Disable IDT monitoring and syncing
1062	*
1063	* @param pVM The VM to operate on.
1064	*/
1065	VMMR3DECL(void) TRPMR3DisableMonitoring(PVM pVM)
1066	{
1067	/*
1068	* Deregister any virtual handlers.
1069	*/
1070	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1071	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1072	{
1073	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1074	{
1075	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1076	AssertRC(rc);
1077	}
1078	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
1079	}
1080	pVM->trpm.s.GuestIdtr.cbIdt = 0;
1081	#endif
1082
1083	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
1084	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
1085	{
1086	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
1087	AssertRC(rc);
1088	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
1089	}
1090	#endif
1091
1092	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
1093	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1094
1095	pVM->trpm.s.fDisableMonitoring = true;
1096	}
1097
1098
1099	/**
1100	* \#PF Handler callback for virtual access handler ranges.
1101	*
1102	* Important to realize that a physical page in a range can have aliases, and
1103	* for ALL and WRITE handlers these will also trigger.
1104	*
1105	* @returns VINF_SUCCESS if the handler have carried out the operation.
1106	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1107	* @param pVM VM Handle.
1108	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1109	* @param pvPtr The HC mapping of that address.
1110	* @param pvBuf What the guest is reading/writing.
1111	* @param cbBuf How much it's reading/writing.
1112	* @param enmAccessType The access type.
1113	* @param pvUser User argument.
1114	*/
1115	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1116	{
1117	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1118	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1119	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1120	return VINF_PGM_HANDLER_DO_DEFAULT;
1121	}
1122
1123
1124	/**
1125	* Clear passthrough interrupt gate handler (reset to default handler)
1126	*
1127	* @returns VBox status code.
1128	* @param pVM The VM to operate on.
1129	* @param iTrap Trap/interrupt gate number.
1130	*/
1131	VMMR3DECL(int) trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1132	{
1133	/* Only applies to raw mode which supports only 1 VCPU. */
1134	PVMCPU pVCpu = &pVM->aCpus[0];
1135
1136	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1137	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1138	int rc;
1139
1140	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1141
1142	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1143	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1144
1145	if ( iTrap < TRPM_HANDLER_INT_BASE
1146	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1147	{
1148	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1149	return VERR_INVALID_PARAMETER;
1150	}
1151	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1152
1153	/* Unmark it for relocation purposes. */
1154	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1155
1156	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1157	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1158	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1159	if (pIdte->Gen.u1Present)
1160	{
1161	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1162	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1163	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1164
1165	/*
1166	* Generic handlers have different entrypoints for each possible
1167	* vector number. These entrypoints make a sort of an array with
1168	* 8 byte entries where the vector number is the index.
1169	* See TRPMGCHandlersA.asm for details.
1170	*/
1171	Offset += iTrap * 8;
1172
1173	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1174	{
1175	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1176	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1177	pIdte->Gen.u16SegSel = SelCS;
1178	}
1179	}
1180
1181	return VINF_SUCCESS;
1182	}
1183
1184
1185	/**
1186	* Check if address is a gate handler (interrupt or trap).
1187	*
1188	* @returns gate nr or ~0 is not found
1189	*
1190	* @param pVM VM handle.
1191	* @param GCPtr GC address to check.
1192	*/
1193	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1194	{
1195	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1196	{
1197	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1198	return iTrap;
1199
1200	/* redundant */
1201	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1202	{
1203	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1204	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1205
1206	if (pHandler == GCPtr)
1207	return iTrap;
1208	}
1209	}
1210	return ~0;
1211	}
1212
1213
1214	/**
1215	* Get guest trap/interrupt gate handler
1216	*
1217	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1218	* @param pVM The VM to operate on.
1219	* @param iTrap Interrupt/trap number.
1220	*/
1221	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1222	{
1223	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1224
1225	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1226	}
1227
1228
1229	/**
1230	* Set guest trap/interrupt gate handler
1231	* Used for setting up trap gates used for kernel calls.
1232	*
1233	* @returns VBox status code.
1234	* @param pVM The VM to operate on.
1235	* @param iTrap Interrupt/trap number.
1236	* @param pHandler GC handler pointer
1237	*/
1238	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1239	{
1240	/* Only valid in raw mode which implies 1 VCPU */
1241	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1242	PVMCPU pVCpu = &pVM->aCpus[0];
1243
1244	/*
1245	* Validate.
1246	*/
1247	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1248	{
1249	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1250	return VERR_INVALID_PARAMETER;
1251	}
1252
1253	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1254
1255	uint16_t cbIDT;
1256	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1257	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1258	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1259
1260	if (pHandler == TRPM_INVALID_HANDLER)
1261	{
1262	/* clear trap handler */
1263	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1264	return trpmClearGuestTrapHandler(pVM, iTrap);
1265	}
1266
1267	/*
1268	* Read the guest IDT entry.
1269	*/
1270	VBOXIDTE GuestIdte;
1271	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1272	if (RT_FAILURE(rc))
1273	{
1274	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1275	return rc;
1276	}
1277
1278	if (EMIsRawRing0Enabled(pVM))
1279	{
1280	/*
1281	* Only replace handlers for which we are 100% certain there won't be
1282	* any host interrupts.
1283	*
1284	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1285	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1286	*
1287	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1288	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1289	* and will therefor never assign hardware interrupts to 0x80.
1290	*
1291	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1292	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1293	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1294	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1295	* defect #3604.
1296	*
1297	* PORTME - Check if your host keeps any of these gates free from hw ints.
1298	*
1299	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1300	*/
1301	/** @todo handle those dependencies better! */
1302	/** @todo Solve this in a proper manner. see defect #1186 */
1303	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1304	if (iTrap == 0x2E)
1305	#elif defined(RT_OS_LINUX)
1306	if (iTrap == 0x80)
1307	#else
1308	if (0)
1309	#endif
1310	{
1311	if ( GuestIdte.Gen.u1Present
1312	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1313	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1314	&& GuestIdte.Gen.u2DPL == 3)
1315	{
1316	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1317
1318	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1319	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1320	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1321	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1322	*pIdte = GuestIdte;
1323
1324	/* Mark it for relocation purposes. */
1325	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1326
1327	/* Also store it in our guest trap array. */
1328	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1329
1330	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1331	return VINF_SUCCESS;
1332	}
1333	/* ok, let's try to install a trampoline handler then. */
1334	}
1335	}
1336
1337	if ( GuestIdte.Gen.u1Present
1338	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1339	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1340	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1341	{
1342	/*
1343	* Save handler which can be used for a trampoline call inside the GC
1344	*/
1345	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1346	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1347	return VINF_SUCCESS;
1348	}
1349	return VERR_INVALID_PARAMETER;
1350	}
1351
1352
1353	/**
1354	* Check if address is a gate handler (interrupt/trap/task/anything).
1355	*
1356	* @returns True is gate handler, false if not.
1357	*
1358	* @param pVM VM handle.
1359	* @param GCPtr GC address to check.
1360	*/
1361	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1362	{
1363	/* Only valid in raw mode which implies 1 VCPU */
1364	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1365	PVMCPU pVCpu = &pVM->aCpus[0];
1366
1367	/*
1368	* Read IDTR and calc last entry.
1369	*/
1370	uint16_t cbIDT;
1371	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1372	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1373	if (!cEntries)
1374	return false;
1375	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1376
1377	/*
1378	* Outer loop: interate pages.
1379	*/
1380	while (GCPtrIDTE <= GCPtrIDTELast)
1381	{
1382	/*
1383	* Convert this page to a HC address.
1384	* (This function checks for not-present pages.)
1385	*/
1386	PCVBOXIDTE pIDTE;
1387	PGMPAGEMAPLOCK Lock;
1388	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1389	if (RT_SUCCESS(rc))
1390	{
1391	/*
1392	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1393	* N.B. Member of the Flat Earth Society...
1394	*/
1395	while (GCPtrIDTE <= GCPtrIDTELast)
1396	{
1397	if (pIDTE->Gen.u1Present)
1398	{
1399	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1400	if (GCPtr == GCPtrHandler)
1401	{
1402	PGMPhysReleasePageMappingLock(pVM, &Lock);
1403	return true;
1404	}
1405	}
1406
1407	/* next entry */
1408	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1409	{
1410	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1411	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1412	GCPtrIDTE += sizeof(VBOXIDTE);
1413	break;
1414	}
1415	GCPtrIDTE += sizeof(VBOXIDTE);
1416	pIDTE++;
1417	}
1418	PGMPhysReleasePageMappingLock(pVM, &Lock);
1419	}
1420	else
1421	{
1422	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1423	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1424	return false;
1425	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1426	}
1427	}
1428	return false;
1429	}
1430
1431
1432	/**
1433	* Inject event (such as external irq or trap)
1434	*
1435	* @returns VBox status code.
1436	* @param pVM The VM to operate on.
1437	* @param pVCpu The VMCPU to operate on.
1438	* @param enmEvent Trpm event type
1439	*/
1440	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1441	{
1442	PCPUMCTX pCtx;
1443	int rc;
1444
1445	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1446	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
1447	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1448
1449	/* Currently only useful for external hardware interrupts. */
1450	Assert(enmEvent == TRPM_HARDWARE_INT);
1451
1452	if (REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ)
1453	{
1454	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1455
1456	# ifdef LOG_ENABLED
1457	DBGFR3InfoLog(pVM, "cpumguest", "TRPMInject");
1458	DBGFR3DisasInstrCurrentLog(pVCpu, "TRPMInject");
1459	# endif
1460
1461	uint8_t u8Interrupt;
1462	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1463	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1464	if (RT_SUCCESS(rc))
1465	{
1466	if (HWACCMIsEnabled(pVM))
1467	{
1468	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1469	AssertRC(rc);
1470	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1471	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM;
1472	}
1473	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1474	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1475	{
1476	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1477	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1478	}
1479
1480	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1481	{
1482	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1483	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1484	if (rc == VINF_SUCCESS)
1485	{
1486	/* There's a handler -> let's execute it in raw mode */
1487	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1488	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1489	{
1490	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1491
1492	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1493	return VINF_EM_RESCHEDULE_RAW;
1494	}
1495	}
1496	}
1497	else
1498	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1499	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1500	}
1501	else
1502	{
1503	AssertRC(rc);
1504	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1505	}
1506	#else
1507	if (HWACCMR3IsActive(pVM))
1508	{
1509	uint8_t u8Interrupt;
1510	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1511	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1512	if (RT_SUCCESS(rc))
1513	{
1514	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
1515	AssertRC(rc);
1516	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1517	return VINF_EM_RESCHEDULE_HWACC;
1518	}
1519	}
1520	else
1521	AssertRC(rc);
1522	#endif
1523	}
1524	/** @todo check if it's safe to translate the patch address to the original guest address.
1525	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1526	*/
1527	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1528
1529	/* Fall back to the recompiler */
1530	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1531	}
1532

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source: vbox/trunk/src/VBox/VMM/TRPM.cpp@ 25816

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