PGMInternal.h@ 16174

最後變更在這個檔案從16174是 16172,由 vboxsync 提交於 16 年前
Moved amd64 paging data to unified shadow paging section.
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1	/* $Id: PGMInternal.h 16172 2009-01-22 15:09:31Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43
44
45	/** @defgroup grp_pgm_int Internals
46	* @ingroup grp_pgm
47	* @internal
48	* @{
49	*/
50
51
52	/** @name PGM Compile Time Config
53	* @{
54	*/
55
56	/**
57	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58	* Comment it if it will break something.
59	*/
60	#define PGM_OUT_OF_SYNC_IN_GC
61
62	/**
63	* Check and skip global PDEs for non-global flushes
64	*/
65	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67	/**
68	* Sync N pages instead of a whole page table
69	*/
70	#define PGM_SYNC_N_PAGES
71
72	/**
73	* Number of pages to sync during a page fault
74	*
75	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77	*/
78	#define PGM_SYNC_NR_PAGES 8
79
80	/**
81	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82	*/
83	#define PGM_MAX_PHYSCACHE_ENTRIES 64
84	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86	/**
87	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88	*/
89	#define PGM_PHYSMEMACCESS_CACHING
90
91	/** @def PGMPOOL_WITH_CACHE
92	* Enable agressive caching using the page pool.
93	*
94	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95	*/
96	#define PGMPOOL_WITH_CACHE
97
98	/** @def PGMPOOL_WITH_MIXED_PT_CR3
99	* When defined, we'll deal with 'uncachable' pages.
100	*/
101	#ifdef PGMPOOL_WITH_CACHE
102	# define PGMPOOL_WITH_MIXED_PT_CR3
103	#endif
104
105	/** @def PGMPOOL_WITH_MONITORING
106	* Monitor the guest pages which are shadowed.
107	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108	* be enabled as well.
109	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110	*/
111	#ifdef PGMPOOL_WITH_CACHE
112	# define PGMPOOL_WITH_MONITORING
113	#endif
114
115	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116	* Tracking the of shadow pages mapping guest physical pages.
117	*
118	* This is very expensive, the current cache prototype is trying to figure out
119	* whether it will be acceptable with an agressive caching policy.
120	*/
121	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
122	# define PGMPOOL_WITH_GCPHYS_TRACKING
123	#endif
124
125	/** @def PGMPOOL_WITH_USER_TRACKING
126	* Tracking users of shadow pages. This is required for the linking of shadow page
127	* tables and physical guest addresses.
128	*/
129	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
130	# define PGMPOOL_WITH_USER_TRACKING
131	#endif
132
133	/** @def PGMPOOL_CFG_MAX_GROW
134	* The maximum number of pages to add to the pool in one go.
135	*/
136	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
140	*/
141	#ifdef VBOX_STRICT
142	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143	#endif
144	/** @} */
145
146
147	/** @name PDPT and PML4 flags.
148	* These are placed in the three bits available for system programs in
149	* the PDPT and PML4 entries.
150	* @{ */
151	/** The entry is a permanent one and it's must always be present.
152	* Never free such an entry. */
153	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154	/** Mapping (hypervisor allocated pagetable). */
155	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156	/** @} */
157
158	/** @name Page directory flags.
159	* These are placed in the three bits available for system programs in
160	* the page directory entries.
161	* @{ */
162	/** Mapping (hypervisor allocated pagetable). */
163	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164	/** Made read-only to facilitate dirty bit tracking. */
165	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166	/** @} */
167
168	/** @name Page flags.
169	* These are placed in the three bits available for system programs in
170	* the page entries.
171	* @{ */
172	/** Made read-only to facilitate dirty bit tracking. */
173	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176	/** Scanned and approved by CSAM (tm).
177	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
178	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180	#endif
181	/** @} */
182
183	/** @name Defines used to indicate the shadow and guest paging in the templates.
184	* @{ */
185	#define PGM_TYPE_REAL 1
186	#define PGM_TYPE_PROT 2
187	#define PGM_TYPE_32BIT 3
188	#define PGM_TYPE_PAE 4
189	#define PGM_TYPE_AMD64 5
190	#define PGM_TYPE_NESTED 6
191	#define PGM_TYPE_EPT 7
192	#define PGM_TYPE_MAX PGM_TYPE_EPT
193	/** @} */
194
195	/** Macro for checking if the guest is using paging.
196	* @param uGstType PGM_TYPE_*
197	* @param uShwType PGM_TYPE_*
198	* @remark ASSUMES certain order of the PGM_TYPE_* values.
199	*/
200	#define PGM_WITH_PAGING(uGstType, uShwType) \
201	( (uGstType) >= PGM_TYPE_32BIT \
202	&& (uShwType) != PGM_TYPE_NESTED \
203	&& (uShwType) != PGM_TYPE_EPT)
204
205	/** Macro for checking if the guest supports the NX bit.
206	* @param uGstType PGM_TYPE_*
207	* @param uShwType PGM_TYPE_*
208	* @remark ASSUMES certain order of the PGM_TYPE_* values.
209	*/
210	#define PGM_WITH_NX(uGstType, uShwType) \
211	( (uGstType) >= PGM_TYPE_PAE \
212	&& (uShwType) != PGM_TYPE_NESTED \
213	&& (uShwType) != PGM_TYPE_EPT)
214
215
216	/** @def PGM_HCPHYS_2_PTR
217	* Maps a HC physical page pool address to a virtual address.
218	*
219	* @returns VBox status code.
220	* @param pVM The VM handle.
221	* @param HCPhys The HC physical address to map to a virtual one.
222	* @param ppv Where to store the virtual address. No need to cast this.
223	*
224	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
225	* small page window employeed by that function. Be careful.
226	* @remark There is no need to assert on the result.
227	*/
228	#ifdef IN_RC
229	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
230	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
231	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
232	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
233	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
234	#else
235	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
236	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
237	#endif
238
239	/** @def PGM_HCPHYS_2_PTR_BY_PGM
240	* Maps a HC physical page pool address to a virtual address.
241	*
242	* @returns VBox status code.
243	* @param pPGM The PGM instance data.
244	* @param HCPhys The HC physical address to map to a virtual one.
245	* @param ppv Where to store the virtual address. No need to cast this.
246	*
247	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
248	* small page window employeed by that function. Be careful.
249	* @remark There is no need to assert on the result.
250	*/
251	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
252	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
253	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
254	#else
255	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
256	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
257	#endif
258
259	/** @def PGM_GCPHYS_2_PTR
260	* Maps a GC physical page address to a virtual address.
261	*
262	* @returns VBox status code.
263	* @param pVM The VM handle.
264	* @param GCPhys The GC physical address to map to a virtual one.
265	* @param ppv Where to store the virtual address. No need to cast this.
266	*
267	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
268	* small page window employeed by that function. Be careful.
269	* @remark There is no need to assert on the result.
270	*/
271	#ifdef IN_RC
272	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
273	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
274	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
275	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
276	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
277	#else
278	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
279	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
280	#endif
281
282	/** @def PGM_GCPHYS_2_PTR_BY_PGM
283	* Maps a GC physical page address to a virtual address.
284	*
285	* @returns VBox status code.
286	* @param pPGM Pointer to the PGM instance data.
287	* @param GCPhys The GC physical address to map to a virtual one.
288	* @param ppv Where to store the virtual address. No need to cast this.
289	*
290	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
291	* small page window employeed by that function. Be careful.
292	* @remark There is no need to assert on the result.
293	*/
294	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
295	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
296	pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
297	#else
298	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
299	PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
300	#endif
301
302	/** @def PGM_GCPHYS_2_PTR_EX
303	* Maps a unaligned GC physical page address to a virtual address.
304	*
305	* @returns VBox status code.
306	* @param pVM The VM handle.
307	* @param GCPhys The GC physical address to map to a virtual one.
308	* @param ppv Where to store the virtual address. No need to cast this.
309	*
310	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
311	* small page window employeed by that function. Be careful.
312	* @remark There is no need to assert on the result.
313	*/
314	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
315	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
316	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
317	#else
318	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
319	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
320	#endif
321
322	/** @def PGM_INVL_PG
323	* Invalidates a page when in GC does nothing in HC.
324	*
325	* @param GCVirt The virtual address of the page to invalidate.
326	*/
327	#ifdef IN_RC
328	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
329	#elif defined(IN_RING0)
330	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
331	#else
332	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
333	#endif
334
335	/** @def PGM_INVL_BIG_PG
336	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
337	*
338	* @param GCVirt The virtual address within the page directory to invalidate.
339	*/
340	#ifdef IN_RC
341	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
342	#elif defined(IN_RING0)
343	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
344	#else
345	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
346	#endif
347
348	/** @def PGM_INVL_GUEST_TLBS()
349	* Invalidates all guest TLBs.
350	*/
351	#ifdef IN_RC
352	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
353	#elif defined(IN_RING0)
354	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
355	#else
356	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
357	#endif
358
359
360	/**
361	* Structure for tracking GC Mappings.
362	*
363	* This structure is used by linked list in both GC and HC.
364	*/
365	typedef struct PGMMAPPING
366	{
367	/** Pointer to next entry. */
368	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
369	/** Pointer to next entry. */
370	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
371	/** Pointer to next entry. */
372	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
373	#if GC_ARCH_BITS == 64
374	RTRCPTR padding0;
375	#endif
376	/** Start Virtual address. */
377	RTGCPTR GCPtr;
378	/** Last Virtual address (inclusive). */
379	RTGCPTR GCPtrLast;
380	/** Range size (bytes). */
381	RTGCPTR cb;
382	/** Pointer to relocation callback function. */
383	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
384	/** User argument to the callback. */
385	R3PTRTYPE(void *) pvUser;
386	/** Mapping description / name. For easing debugging. */
387	R3PTRTYPE(const char *) pszDesc;
388	/** Number of page tables. */
389	RTUINT cPTs;
390	#if HC_ARCH_BITS != GC_ARCH_BITS \|\| GC_ARCH_BITS == 64
391	RTUINT uPadding1; /*< Alignment padding. /
392	#endif
393	/** Array of page table mapping data. Each entry
394	* describes one page table. The array can be longer
395	* than the declared length.
396	*/
397	struct
398	{
399	/** The HC physical address of the page table. */
400	RTHCPHYS HCPhysPT;
401	/** The HC physical address of the first PAE page table. */
402	RTHCPHYS HCPhysPaePT0;
403	/** The HC physical address of the second PAE page table. */
404	RTHCPHYS HCPhysPaePT1;
405	/** The HC virtual address of the 32-bit page table. */
406	R3PTRTYPE(PX86PT) pPTR3;
407	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
408	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
409	/** The GC virtual address of the 32-bit page table. */
410	RCPTRTYPE(PX86PT) pPTRC;
411	/** The GC virtual address of the two PAE page table. */
412	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
413	/** The GC virtual address of the 32-bit page table. */
414	R0PTRTYPE(PX86PT) pPTR0;
415	/** The GC virtual address of the two PAE page table. */
416	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
417	} aPTs[1];
418	} PGMMAPPING;
419	/** Pointer to structure for tracking GC Mappings. */
420	typedef struct PGMMAPPING *PPGMMAPPING;
421
422
423	/**
424	* Physical page access handler structure.
425	*
426	* This is used to keep track of physical address ranges
427	* which are being monitored in some kind of way.
428	*/
429	typedef struct PGMPHYSHANDLER
430	{
431	AVLROGCPHYSNODECORE Core;
432	/** Access type. */
433	PGMPHYSHANDLERTYPE enmType;
434	/** Number of pages to update. */
435	uint32_t cPages;
436	/** Pointer to R3 callback function. */
437	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
438	/** User argument for R3 handlers. */
439	R3PTRTYPE(void *) pvUserR3;
440	/** Pointer to R0 callback function. */
441	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
442	/** User argument for R0 handlers. */
443	R0PTRTYPE(void *) pvUserR0;
444	/** Pointer to GC callback function. */
445	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
446	/** User argument for RC handlers. */
447	RCPTRTYPE(void *) pvUserRC;
448	/** Description / Name. For easing debugging. */
449	R3PTRTYPE(const char *) pszDesc;
450	#ifdef VBOX_WITH_STATISTICS
451	/** Profiling of this handler. */
452	STAMPROFILE Stat;
453	#endif
454	} PGMPHYSHANDLER;
455	/** Pointer to a physical page access handler structure. */
456	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
457
458
459	/**
460	* Cache node for the physical addresses covered by a virtual handler.
461	*/
462	typedef struct PGMPHYS2VIRTHANDLER
463	{
464	/** Core node for the tree based on physical ranges. */
465	AVLROGCPHYSNODECORE Core;
466	/** Offset from this struct to the PGMVIRTHANDLER structure. */
467	int32_t offVirtHandler;
468	/** Offset of the next alias relative to this one.
469	* Bit 0 is used for indicating whether we're in the tree.
470	* Bit 1 is used for indicating that we're the head node.
471	*/
472	int32_t offNextAlias;
473	} PGMPHYS2VIRTHANDLER;
474	/** Pointer to a phys to virtual handler structure. */
475	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
476
477	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
478	* node is in the tree. */
479	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
480	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
481	* node is in the head of an alias chain.
482	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
483	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
484	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
485	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
486
487
488	/**
489	* Virtual page access handler structure.
490	*
491	* This is used to keep track of virtual address ranges
492	* which are being monitored in some kind of way.
493	*/
494	typedef struct PGMVIRTHANDLER
495	{
496	/** Core node for the tree based on virtual ranges. */
497	AVLROGCPTRNODECORE Core;
498	/** Size of the range (in bytes). */
499	RTGCPTR cb;
500	/** Number of cache pages. */
501	uint32_t cPages;
502	/** Access type. */
503	PGMVIRTHANDLERTYPE enmType;
504	/** Pointer to the RC callback function. */
505	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
506	#if HC_ARCH_BITS == 64
507	RTRCPTR padding;
508	#endif
509	/** Pointer to the R3 callback function for invalidation. */
510	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
511	/** Pointer to the R3 callback function. */
512	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
513	/** Description / Name. For easing debugging. */
514	R3PTRTYPE(const char *) pszDesc;
515	#ifdef VBOX_WITH_STATISTICS
516	/** Profiling of this handler. */
517	STAMPROFILE Stat;
518	#endif
519	/** Array of cached physical addresses for the monitored ranged. */
520	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
521	} PGMVIRTHANDLER;
522	/** Pointer to a virtual page access handler structure. */
523	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
524
525
526	/**
527	* Page type.
528	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
529	* @todo convert to \#defines.
530	*/
531	typedef enum PGMPAGETYPE
532	{
533	/** The usual invalid zero entry. */
534	PGMPAGETYPE_INVALID = 0,
535	/** RAM page. (RWX) */
536	PGMPAGETYPE_RAM,
537	/** MMIO2 page. (RWX) */
538	PGMPAGETYPE_MMIO2,
539	/** Shadowed ROM. (RWX) */
540	PGMPAGETYPE_ROM_SHADOW,
541	/** ROM page. (R-X) */
542	PGMPAGETYPE_ROM,
543	/** MMIO page. (---) */
544	PGMPAGETYPE_MMIO,
545	/** End of valid entries. */
546	PGMPAGETYPE_END
547	} PGMPAGETYPE;
548	AssertCompile(PGMPAGETYPE_END < 7);
549
550	/** @name Page type predicates.
551	* @{ */
552	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
553	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
554	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
555	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
556	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
557	/** @} */
558
559
560	/**
561	* A Physical Guest Page tracking structure.
562	*
563	* The format of this structure is complicated because we have to fit a lot
564	* of information into as few bits as possible. The format is also subject
565	* to change (there is one comming up soon). Which means that for we'll be
566	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
567	* accessess to the structure.
568	*/
569	typedef struct PGMPAGE
570	{
571	/** The physical address and a whole lot of other stuff. All bits are used! */
572	RTHCPHYS HCPhys;
573	/** The page state. */
574	uint32_t u2StateX : 2;
575	/** Flag indicating that a write monitored page was written to when set. */
576	uint32_t fWrittenToX : 1;
577	/** For later. */
578	uint32_t fSomethingElse : 1;
579	/** The Page ID.
580	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
581	* The HCPhys will be 100% static. */
582	uint32_t idPageX : 28;
583	/** The page type (PGMPAGETYPE). */
584	uint32_t u3Type : 3;
585	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
586	uint32_t u2HandlerPhysStateX : 2;
587	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
588	uint32_t u2HandlerVirtStateX : 2;
589	uint32_t u29B : 25;
590	} PGMPAGE;
591	AssertCompileSize(PGMPAGE, 16);
592	/** Pointer to a physical guest page. */
593	typedef PGMPAGE *PPGMPAGE;
594	/** Pointer to a const physical guest page. */
595	typedef const PGMPAGE *PCPGMPAGE;
596	/** Pointer to a physical guest page pointer. */
597	typedef PPGMPAGE *PPPGMPAGE;
598
599
600	/**
601	* Clears the page structure.
602	* @param pPage Pointer to the physical guest page tracking structure.
603	*/
604	#define PGM_PAGE_CLEAR(pPage) \
605	do { \
606	(pPage)->HCPhys = 0; \
607	(pPage)->u2StateX = 0; \
608	(pPage)->fWrittenToX = 0; \
609	(pPage)->fSomethingElse = 0; \
610	(pPage)->idPageX = 0; \
611	(pPage)->u3Type = 0; \
612	(pPage)->u29B = 0; \
613	} while (0)
614
615	/**
616	* Initializes the page structure.
617	* @param pPage Pointer to the physical guest page tracking structure.
618	*/
619	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
620	do { \
621	(pPage)->HCPhys = (_HCPhys); \
622	(pPage)->u2StateX = (_uState); \
623	(pPage)->fWrittenToX = 0; \
624	(pPage)->fSomethingElse = 0; \
625	(pPage)->idPageX = (_idPage); \
626	/(pPage)->u3Type = (_uType); - later / \
627	PGM_PAGE_SET_TYPE(pPage, _uType); \
628	(pPage)->u29B = 0; \
629	} while (0)
630
631	/**
632	* Initializes the page structure of a ZERO page.
633	* @param pPage Pointer to the physical guest page tracking structure.
634	*/
635	#ifdef VBOX_WITH_NEW_PHYS_CODE
636	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
637	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
638	#else
639	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
640	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
641	#endif
642	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
643	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
644	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
645
646
647	/** @name The Page state, PGMPAGE::u2StateX.
648	* @{ */
649	/** The zero page.
650	* This is a per-VM page that's never ever mapped writable. */
651	#define PGM_PAGE_STATE_ZERO 0
652	/** A allocated page.
653	* This is a per-VM page allocated from the page pool (or wherever
654	* we get MMIO2 pages from if the type is MMIO2).
655	*/
656	#define PGM_PAGE_STATE_ALLOCATED 1
657	/** A allocated page that's being monitored for writes.
658	* The shadow page table mappings are read-only. When a write occurs, the
659	* fWrittenTo member is set, the page remapped as read-write and the state
660	* moved back to allocated. */
661	#define PGM_PAGE_STATE_WRITE_MONITORED 2
662	/** The page is shared, aka. copy-on-write.
663	* This is a page that's shared with other VMs. */
664	#define PGM_PAGE_STATE_SHARED 3
665	/** @} */
666
667
668	/**
669	* Gets the page state.
670	* @returns page state (PGM_PAGE_STATE_*).
671	* @param pPage Pointer to the physical guest page tracking structure.
672	*/
673	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
674
675	/**
676	* Sets the page state.
677	* @param pPage Pointer to the physical guest page tracking structure.
678	* @param _uState The new page state.
679	*/
680	#define PGM_PAGE_SET_STATE(pPage, _uState) \
681	do { (pPage)->u2StateX = (_uState); } while (0)
682
683
684	/**
685	* Gets the host physical address of the guest page.
686	* @returns host physical address (RTHCPHYS).
687	* @param pPage Pointer to the physical guest page tracking structure.
688	*/
689	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
690
691	/**
692	* Sets the host physical address of the guest page.
693	* @param pPage Pointer to the physical guest page tracking structure.
694	* @param _HCPhys The new host physical address.
695	*/
696	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
697	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
698	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
699
700	/**
701	* Get the Page ID.
702	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
703	* @param pPage Pointer to the physical guest page tracking structure.
704	*/
705	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
706	/* later:
707	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
708	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
709	*/
710	/**
711	* Sets the Page ID.
712	* @param pPage Pointer to the physical guest page tracking structure.
713	*/
714	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
715	/* later:
716	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
717	\| ((_idPage) & 0xfff) \
718	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
719	*/
720
721	/**
722	* Get the Chunk ID.
723	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
724	* @param pPage Pointer to the physical guest page tracking structure.
725	*/
726	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
727	/* later:
728	#if GMM_CHUNKID_SHIFT == 12
729	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
730	#elif GMM_CHUNKID_SHIFT > 12
731	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
732	#elif GMM_CHUNKID_SHIFT < 12
733	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
734	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
735	#else
736	# error "GMM_CHUNKID_SHIFT isn't defined or something."
737	#endif
738	*/
739
740	/**
741	* Get the index of the page within the allocaiton chunk.
742	* @returns The page index.
743	* @param pPage Pointer to the physical guest page tracking structure.
744	*/
745	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
746	/* later:
747	#if GMM_CHUNKID_SHIFT <= 12
748	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
749	#else
750	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
751	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
752	#endif
753	*/
754
755
756	/**
757	* Gets the page type.
758	* @returns The page type.
759	* @param pPage Pointer to the physical guest page tracking structure.
760	*/
761	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
762
763	/**
764	* Sets the page type.
765	* @param pPage Pointer to the physical guest page tracking structure.
766	* @param _enmType The new page type (PGMPAGETYPE).
767	*/
768	#ifdef VBOX_WITH_NEW_PHYS_CODE
769	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
770	do { (pPage)->u3Type = (_enmType); } while (0)
771	#else
772	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
773	do { \
774	(pPage)->u3Type = (_enmType); \
775	if ((_enmType) == PGMPAGETYPE_ROM) \
776	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
777	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
778	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
779	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
780	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
781	} while (0)
782	#endif
783
784
785	/**
786	* Checks if the page is 'reserved'.
787	* @returns true/false.
788	* @param pPage Pointer to the physical guest page tracking structure.
789	*/
790	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
791
792	/**
793	* Checks if the page is marked for MMIO.
794	* @returns true/false.
795	* @param pPage Pointer to the physical guest page tracking structure.
796	*/
797	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
798
799	/**
800	* Checks if the page is backed by the ZERO page.
801	* @returns true/false.
802	* @param pPage Pointer to the physical guest page tracking structure.
803	*/
804	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
805
806	/**
807	* Checks if the page is backed by a SHARED page.
808	* @returns true/false.
809	* @param pPage Pointer to the physical guest page tracking structure.
810	*/
811	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
812
813
814	/**
815	* Marks the paget as written to (for GMM change monitoring).
816	* @param pPage Pointer to the physical guest page tracking structure.
817	*/
818	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
819
820	/**
821	* Clears the written-to indicator.
822	* @param pPage Pointer to the physical guest page tracking structure.
823	*/
824	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
825
826	/**
827	* Checks if the page was marked as written-to.
828	* @returns true/false.
829	* @param pPage Pointer to the physical guest page tracking structure.
830	*/
831	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
832
833
834	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
835	*
836	* @remarks The values are assigned in order of priority, so we can calculate
837	* the correct state for a page with different handlers installed.
838	* @{ */
839	/** No handler installed. */
840	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
841	/** Monitoring is temporarily disabled. */
842	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
843	/** Write access is monitored. */
844	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
845	/** All access is monitored. */
846	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
847	/** @} */
848
849	/**
850	* Gets the physical access handler state of a page.
851	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
852	* @param pPage Pointer to the physical guest page tracking structure.
853	*/
854	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
855
856	/**
857	* Sets the physical access handler state of a page.
858	* @param pPage Pointer to the physical guest page tracking structure.
859	* @param _uState The new state value.
860	*/
861	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
862	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
863
864	/**
865	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
866	* @returns true/false
867	* @param pPage Pointer to the physical guest page tracking structure.
868	*/
869	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
870
871	/**
872	* Checks if the page has any active physical access handlers.
873	* @returns true/false
874	* @param pPage Pointer to the physical guest page tracking structure.
875	*/
876	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
877
878
879	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
880	*
881	* @remarks The values are assigned in order of priority, so we can calculate
882	* the correct state for a page with different handlers installed.
883	* @{ */
884	/** No handler installed. */
885	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
886	/* 1 is reserved so the lineup is identical with the physical ones. */
887	/** Write access is monitored. */
888	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
889	/** All access is monitored. */
890	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
891	/** @} */
892
893	/**
894	* Gets the virtual access handler state of a page.
895	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
896	* @param pPage Pointer to the physical guest page tracking structure.
897	*/
898	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
899
900	/**
901	* Sets the virtual access handler state of a page.
902	* @param pPage Pointer to the physical guest page tracking structure.
903	* @param _uState The new state value.
904	*/
905	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
906	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
907
908	/**
909	* Checks if the page has any virtual access handlers.
910	* @returns true/false
911	* @param pPage Pointer to the physical guest page tracking structure.
912	*/
913	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
914
915	/**
916	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
917	* virtual handlers.
918	* @returns true/false
919	* @param pPage Pointer to the physical guest page tracking structure.
920	*/
921	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
922
923
924
925	/**
926	* Checks if the page has any access handlers, including temporarily disabled ones.
927	* @returns true/false
928	* @param pPage Pointer to the physical guest page tracking structure.
929	*/
930	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
931	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
932	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
933
934	/**
935	* Checks if the page has any active access handlers.
936	* @returns true/false
937	* @param pPage Pointer to the physical guest page tracking structure.
938	*/
939	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
940	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
941	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
942
943	/**
944	* Checks if the page has any active access handlers catching all accesses.
945	* @returns true/false
946	* @param pPage Pointer to the physical guest page tracking structure.
947	*/
948	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
949	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
950	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
951
952
953	/**
954	* Ram range for GC Phys to HC Phys conversion.
955	*
956	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
957	* conversions too, but we'll let MM handle that for now.
958	*
959	* This structure is used by linked lists in both GC and HC.
960	*/
961	typedef struct PGMRAMRANGE
962	{
963	/** Pointer to the next RAM range - for R3. */
964	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
965	/** Pointer to the next RAM range - for R0. */
966	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
967	/** Pointer to the next RAM range - for RC. */
968	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
969	/** Pointer alignment. */
970	RTRCPTR RCPtrAlignment;
971	/** Start of the range. Page aligned. */
972	RTGCPHYS GCPhys;
973	/** Last address in the range (inclusive). Page aligned (-1). */
974	RTGCPHYS GCPhysLast;
975	/** Size of the range. (Page aligned of course). */
976	RTGCPHYS cb;
977	/** MM_RAM_* flags */
978	uint32_t fFlags;
979	uint32_t u32Alignment; /*< alignment. /
980	#ifndef VBOX_WITH_NEW_PHYS_CODE
981	/** R3 virtual lookup ranges for chunks.
982	* Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
983	* @remarks This is occationally accessed from ring-0!! (not darwin) */
984	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985	R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
986	# else
987	R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
988	# endif
989	#endif
990	/** Start of the HC mapping of the range. This is only used for MMIO2. */
991	R3PTRTYPE(void *) pvR3;
992	/** The range description. */
993	R3PTRTYPE(const char *) pszDesc;
994
995	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
996	#ifdef VBOX_WITH_NEW_PHYS_CODE
997	uint32_t au32Reserved[2];
998	#elif HC_ARCH_BITS == 32
999	uint32_t au32Reserved[1];
1000	#endif
1001
1002	/** Array of physical guest page tracking structures. */
1003	PGMPAGE aPages[1];
1004	} PGMRAMRANGE;
1005	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1006	typedef PGMRAMRANGE *PPGMRAMRANGE;
1007
1008	/** Return hc ptr corresponding to the ram range and physical offset */
1009	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1010	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1011	: (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1012
1013	/**
1014	* Per page tracking structure for ROM image.
1015	*
1016	* A ROM image may have a shadow page, in which case we may have
1017	* two pages backing it. This structure contains the PGMPAGE for
1018	* both while PGMRAMRANGE have a copy of the active one. It is
1019	* important that these aren't out of sync in any regard other
1020	* than page pool tracking data.
1021	*/
1022	typedef struct PGMROMPAGE
1023	{
1024	/** The page structure for the virgin ROM page. */
1025	PGMPAGE Virgin;
1026	/** The page structure for the shadow RAM page. */
1027	PGMPAGE Shadow;
1028	/** The current protection setting. */
1029	PGMROMPROT enmProt;
1030	/** Pad the structure size to a multiple of 8. */
1031	uint32_t u32Padding;
1032	} PGMROMPAGE;
1033	/** Pointer to a ROM page tracking structure. */
1034	typedef PGMROMPAGE *PPGMROMPAGE;
1035
1036
1037	/**
1038	* A registered ROM image.
1039	*
1040	* This is needed to keep track of ROM image since they generally
1041	* intrude into a PGMRAMRANGE. It also keeps track of additional
1042	* info like the two page sets (read-only virgin and read-write shadow),
1043	* the current state of each page.
1044	*
1045	* Because access handlers cannot easily be executed in a different
1046	* context, the ROM ranges needs to be accessible and in all contexts.
1047	*/
1048	typedef struct PGMROMRANGE
1049	{
1050	/** Pointer to the next range - R3. */
1051	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1052	/** Pointer to the next range - R0. */
1053	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1054	/** Pointer to the next range - RC. */
1055	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1056	/** Pointer alignment */
1057	RTRCPTR GCPtrAlignment;
1058	/** Address of the range. */
1059	RTGCPHYS GCPhys;
1060	/** Address of the last byte in the range. */
1061	RTGCPHYS GCPhysLast;
1062	/** Size of the range. */
1063	RTGCPHYS cb;
1064	/** The flags (PGMPHYS_ROM_FLAG_). /
1065	uint32_t fFlags;
1066	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1067	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1068	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1069	* This is used for strictness checks. */
1070	R3PTRTYPE(const void *) pvOriginal;
1071	/** The ROM description. */
1072	R3PTRTYPE(const char *) pszDesc;
1073	/** The per page tracking structures. */
1074	PGMROMPAGE aPages[1];
1075	} PGMROMRANGE;
1076	/** Pointer to a ROM range. */
1077	typedef PGMROMRANGE *PPGMROMRANGE;
1078
1079
1080	/**
1081	* A registered MMIO2 (= Device RAM) range.
1082	*
1083	* There are a few reason why we need to keep track of these
1084	* registrations. One of them is the deregistration & cleanup
1085	* stuff, while another is that the PGMRAMRANGE associated with
1086	* such a region may have to be removed from the ram range list.
1087	*
1088	* Overlapping with a RAM range has to be 100% or none at all. The
1089	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1090	* meditation will be raised if a partial overlap or an overlap of
1091	* ROM pages is encountered. On an overlap we will free all the
1092	* existing RAM pages and put in the ram range pages instead.
1093	*/
1094	typedef struct PGMMMIO2RANGE
1095	{
1096	/** The owner of the range. (a device) */
1097	PPDMDEVINSR3 pDevInsR3;
1098	/** Pointer to the ring-3 mapping of the allocation. */
1099	RTR3PTR pvR3;
1100	/** Pointer to the next range - R3. */
1101	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1102	/** Whether it's mapped or not. */
1103	bool fMapped;
1104	/** Whether it's overlapping or not. */
1105	bool fOverlapping;
1106	/** The PCI region number.
1107	* @remarks This ASSUMES that nobody will ever really need to have multiple
1108	* PCI devices with matching MMIO region numbers on a single device. */
1109	uint8_t iRegion;
1110	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1111	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1112	/** The associated RAM range. */
1113	PGMRAMRANGE RamRange;
1114	} PGMMMIO2RANGE;
1115	/** Pointer to a MMIO2 range. */
1116	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1117
1118
1119
1120
1121	/**
1122	* PGMPhysRead/Write cache entry
1123	*/
1124	typedef struct PGMPHYSCACHEENTRY
1125	{
1126	/** R3 pointer to physical page. */
1127	R3PTRTYPE(uint8_t *) pbR3;
1128	/** GC Physical address for cache entry */
1129	RTGCPHYS GCPhys;
1130	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1131	RTGCPHYS u32Padding0; /*< alignment padding. /
1132	#endif
1133	} PGMPHYSCACHEENTRY;
1134
1135	/**
1136	* PGMPhysRead/Write cache to reduce REM memory access overhead
1137	*/
1138	typedef struct PGMPHYSCACHE
1139	{
1140	/** Bitmap of valid cache entries */
1141	uint64_t aEntries;
1142	/** Cache entries */
1143	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1144	} PGMPHYSCACHE;
1145
1146
1147	/** Pointer to an allocation chunk ring-3 mapping. */
1148	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1149	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1150	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1151
1152	/**
1153	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1154	*
1155	* The primary tree (Core) uses the chunk id as key.
1156	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1157	*/
1158	typedef struct PGMCHUNKR3MAP
1159	{
1160	/** The key is the chunk id. */
1161	AVLU32NODECORE Core;
1162	/** The key is the ageing sequence number. */
1163	AVLLU32NODECORE AgeCore;
1164	/** The current age thingy. */
1165	uint32_t iAge;
1166	/** The current reference count. */
1167	uint32_t volatile cRefs;
1168	/** The current permanent reference count. */
1169	uint32_t volatile cPermRefs;
1170	/** The mapping address. */
1171	void *pv;
1172	} PGMCHUNKR3MAP;
1173
1174	/**
1175	* Allocation chunk ring-3 mapping TLB entry.
1176	*/
1177	typedef struct PGMCHUNKR3MAPTLBE
1178	{
1179	/** The chunk id. */
1180	uint32_t volatile idChunk;
1181	#if HC_ARCH_BITS == 64
1182	uint32_t u32Padding; /*< alignment padding. /
1183	#endif
1184	/** The chunk map. */
1185	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1186	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1187	#else
1188	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1189	#endif
1190	} PGMCHUNKR3MAPTLBE;
1191	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1192	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1193
1194	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1195	* @remark Must be a power of two value. */
1196	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1197
1198	/**
1199	* Allocation chunk ring-3 mapping TLB.
1200	*
1201	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1202	* At first glance this might look kinda odd since AVL trees are
1203	* supposed to give the most optimial lookup times of all trees
1204	* due to their balancing. However, take a tree with 1023 nodes
1205	* in it, that's 10 levels, meaning that most searches has to go
1206	* down 9 levels before they find what they want. This isn't fast
1207	* compared to a TLB hit. There is the factor of cache misses,
1208	* and of course the problem with trees and branch prediction.
1209	* This is why we use TLBs in front of most of the trees.
1210	*
1211	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1212	* difficult when we switch to the new inlined AVL trees (from kStuff).
1213	*/
1214	typedef struct PGMCHUNKR3MAPTLB
1215	{
1216	/** The TLB entries. */
1217	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1218	} PGMCHUNKR3MAPTLB;
1219
1220	/**
1221	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1222	* @returns Chunk TLB index.
1223	* @param idChunk The Chunk ID.
1224	*/
1225	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1226
1227
1228	/**
1229	* Ring-3 guest page mapping TLB entry.
1230	* @remarks used in ring-0 as well at the moment.
1231	*/
1232	typedef struct PGMPAGER3MAPTLBE
1233	{
1234	/** Address of the page. */
1235	RTGCPHYS volatile GCPhys;
1236	/** The guest page. */
1237	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1238	R3PTRTYPE(PPGMPAGE) volatile pPage;
1239	#else
1240	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1241	#endif
1242	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1243	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1244	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1245	#else
1246	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1247	#endif
1248	/** The address */
1249	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1250	R3PTRTYPE(void *) volatile pv;
1251	#else
1252	R3R0PTRTYPE(void *) volatile pv;
1253	#endif
1254	#if HC_ARCH_BITS == 32
1255	uint32_t u32Padding; /*< alignment padding. /
1256	#endif
1257	} PGMPAGER3MAPTLBE;
1258	/** Pointer to an entry in the HC physical TLB. */
1259	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1260
1261
1262	/** The number of entries in the ring-3 guest page mapping TLB.
1263	* @remarks The value must be a power of two. */
1264	#define PGM_PAGER3MAPTLB_ENTRIES 64
1265
1266	/**
1267	* Ring-3 guest page mapping TLB.
1268	* @remarks used in ring-0 as well at the moment.
1269	*/
1270	typedef struct PGMPAGER3MAPTLB
1271	{
1272	/** The TLB entries. */
1273	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1274	} PGMPAGER3MAPTLB;
1275	/** Pointer to the ring-3 guest page mapping TLB. */
1276	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1277
1278	/**
1279	* Calculates the index of the TLB entry for the specified guest page.
1280	* @returns Physical TLB index.
1281	* @param GCPhys The guest physical address.
1282	*/
1283	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1284
1285
1286	/**
1287	* Mapping cache usage set entry.
1288	*
1289	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1290	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1291	* cache. If it's extended to include ring-3, well, then something will
1292	* have be changed here...
1293	*/
1294	typedef struct PGMMAPSETENTRY
1295	{
1296	/** The mapping cache index. */
1297	uint16_t iPage;
1298	/** The number of references.
1299	* The max is UINT16_MAX - 1. */
1300	uint16_t cRefs;
1301	/** Pointer to the page. */
1302	RTR0PTR pvPage;
1303	/** The physical address for this entry. */
1304	RTHCPHYS HCPhys;
1305	} PGMMAPSETENTRY;
1306	/** Pointer to a mapping cache usage set entry. */
1307	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1308
1309	/**
1310	* Mapping cache usage set.
1311	*
1312	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1313	* done during exits / traps. The set is
1314	*/
1315	typedef struct PGMMAPSET
1316	{
1317	/** The number of occupied entries.
1318	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1319	* dynamic mappings. */
1320	uint32_t cEntries;
1321	/** The start of the current subset.
1322	* This is UINT32_MAX if no subset is currently open. */
1323	uint32_t iSubset;
1324	/** The index of the current CPU, only valid if the set is open. */
1325	int32_t iCpu;
1326	/** The entries. */
1327	PGMMAPSETENTRY aEntries[64];
1328	/** HCPhys -> iEntry fast lookup table.
1329	* Use PGMMAPSET_HASH for hashing.
1330	* The entries may or may not be valid, check against cEntries. */
1331	uint8_t aiHashTable[128];
1332	} PGMMAPSET;
1333	/** Pointer to the mapping cache set. */
1334	typedef PGMMAPSET *PPGMMAPSET;
1335
1336	/** PGMMAPSET::cEntries value for a closed set. */
1337	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1338
1339	/** Hash function for aiHashTable. */
1340	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1341
1342	/** The max fill size (strict builds). */
1343	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1344
1345
1346	/** @name Context neutrual page mapper TLB.
1347	*
1348	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1349	* code is writting in a kind of context neutrual way. Time will show whether
1350	* this actually makes sense or not...
1351	*
1352	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1353	* context ends up using a global mapping cache on some platforms
1354	* (darwin).
1355	*
1356	* @{ */
1357	/** @typedef PPGMPAGEMAPTLB
1358	* The page mapper TLB pointer type for the current context. */
1359	/** @typedef PPGMPAGEMAPTLB
1360	* The page mapper TLB entry pointer type for the current context. */
1361	/** @typedef PPGMPAGEMAPTLB
1362	* The page mapper TLB entry pointer pointer type for the current context. */
1363	/** @def PGM_PAGEMAPTLB_ENTRIES
1364	* The number of TLB entries in the page mapper TLB for the current context. */
1365	/** @def PGM_PAGEMAPTLB_IDX
1366	* Calculate the TLB index for a guest physical address.
1367	* @returns The TLB index.
1368	* @param GCPhys The guest physical address. */
1369	/** @typedef PPGMPAGEMAP
1370	* Pointer to a page mapper unit for current context. */
1371	/** @typedef PPPGMPAGEMAP
1372	* Pointer to a page mapper unit pointer for current context. */
1373	#ifdef IN_RC
1374	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1375	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1376	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1377	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1378	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1379	typedef void * PPGMPAGEMAP;
1380	typedef void ** PPPGMPAGEMAP;
1381	//#elif IN_RING0
1382	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1383	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1384	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1385	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1386	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1387	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1388	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1389	#else
1390	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1391	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1392	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1393	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1394	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1395	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1396	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1397	#endif
1398	/** @} */
1399
1400
1401	/** @name PGM Pool Indexes.
1402	* Aka. the unique shadow page identifier.
1403	* @{ */
1404	/** NIL page pool IDX. */
1405	#define NIL_PGMPOOL_IDX 0
1406	/** The first normal index. */
1407	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1408	/** Page directory (32-bit root). */
1409	#define PGMPOOL_IDX_PD 1
1410	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1411	/** Page directory (32-bit root). */
1412	#define PGMPOOL_IDX_PD 1
1413	/** Page Directory Pointer Table (PAE root). */
1414	#define PGMPOOL_IDX_PDPT 2
1415	/** AMD64 CR3 level index.*/
1416	#define PGMPOOL_IDX_AMD64_CR3 3
1417	/** Nested paging root.*/
1418	#define PGMPOOL_IDX_NESTED_ROOT 4
1419	/** The first normal index. */
1420	#define PGMPOOL_IDX_FIRST 5
1421	#else
1422	/** The extended PAE page directory (2048 entries, works as root currently). */
1423	#define PGMPOOL_IDX_PAE_PD 2
1424	/** PAE Page Directory Table 0. */
1425	#define PGMPOOL_IDX_PAE_PD_0 3
1426	/** PAE Page Directory Table 1. */
1427	#define PGMPOOL_IDX_PAE_PD_1 4
1428	/** PAE Page Directory Table 2. */
1429	#define PGMPOOL_IDX_PAE_PD_2 5
1430	/** PAE Page Directory Table 3. */
1431	#define PGMPOOL_IDX_PAE_PD_3 6
1432	/** Page Directory Pointer Table (PAE root, not currently used). */
1433	#define PGMPOOL_IDX_PDPT 7
1434	/** AMD64 CR3 level index.*/
1435	#define PGMPOOL_IDX_AMD64_CR3 8
1436	/** Nested paging root.*/
1437	#define PGMPOOL_IDX_NESTED_ROOT 9
1438	/** The first normal index. */
1439	#define PGMPOOL_IDX_FIRST 10
1440	#endif
1441	/** The last valid index. (inclusive, 14 bits) */
1442	#define PGMPOOL_IDX_LAST 0x3fff
1443	/** @} */
1444
1445	/** The NIL index for the parent chain. */
1446	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1447
1448	/**
1449	* Node in the chain linking a shadowed page to it's parent (user).
1450	*/
1451	#pragma pack(1)
1452	typedef struct PGMPOOLUSER
1453	{
1454	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1455	uint16_t iNext;
1456	/** The user page index. */
1457	uint16_t iUser;
1458	/** Index into the user table. */
1459	uint32_t iUserTable;
1460	} PGMPOOLUSER, *PPGMPOOLUSER;
1461	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1462	#pragma pack()
1463
1464
1465	/** The NIL index for the phys ext chain. */
1466	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1467
1468	/**
1469	* Node in the chain of physical cross reference extents.
1470	*/
1471	#pragma pack(1)
1472	typedef struct PGMPOOLPHYSEXT
1473	{
1474	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1475	uint16_t iNext;
1476	/** The user page index. */
1477	uint16_t aidx[3];
1478	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1479	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1480	#pragma pack()
1481
1482
1483	/**
1484	* The kind of page that's being shadowed.
1485	*/
1486	typedef enum PGMPOOLKIND
1487	{
1488	/** The virtual invalid 0 entry. */
1489	PGMPOOLKIND_INVALID = 0,
1490	/** The entry is free (=unused). */
1491	PGMPOOLKIND_FREE,
1492
1493	/** Shw: 32-bit page table; Gst: no paging */
1494	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1495	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1496	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1497	/** Shw: 32-bit page table; Gst: 4MB page. */
1498	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1499	/** Shw: PAE page table; Gst: no paging */
1500	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1501	/** Shw: PAE page table; Gst: 32-bit page table. */
1502	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1503	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1504	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1505	/** Shw: PAE page table; Gst: PAE page table. */
1506	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1507	/** Shw: PAE page table; Gst: 2MB page. */
1508	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1509
1510	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1511	PGMPOOLKIND_32BIT_PD,
1512	/** Shw: 32-bit page directory. Gst: real mode. */
1513	PGMPOOLKIND_32BIT_PD_PHYS_REAL,
1514	/** Shw: 32-bit page directory. Gst: protected mode without paging. */
1515	PGMPOOLKIND_32BIT_PD_PHYS_PROT,
1516	/** Shw: PAE page directory; Gst: 32-bit page directory. */
1517	PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1518	/** Shw: PAE page directory; Gst: PAE page directory. */
1519	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1520	/** Shw: PAE page directory; Gst: real mode. */
1521	PGMPOOLKIND_PAE_PD_PHYS_REAL,
1522	/** Shw: PAE page directory; Gst: protected mode without paging. */
1523	PGMPOOLKIND_PAE_PD_PHYS_PROT,
1524
1525	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1526	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1527	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1528	PGMPOOLKIND_PAE_PDPT,
1529
1530	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1531	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1532	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1533	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1534	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1535	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1536	/** Shw: 64-bit page directory table; Gst: no paging */
1537	PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1538
1539	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1540	PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1541
1542	/** Shw: EPT page directory pointer table; Gst: no paging */
1543	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1544	/** Shw: EPT page directory table; Gst: no paging */
1545	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1546	/** Shw: EPT page table; Gst: no paging */
1547	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1548
1549	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1550	/** Shw: Root 32-bit page directory. */
1551	PGMPOOLKIND_ROOT_32BIT_PD,
1552	/** Shw: Root PAE page directory */
1553	PGMPOOLKIND_ROOT_PAE_PD,
1554	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1555	PGMPOOLKIND_ROOT_PDPT,
1556	#endif
1557	/** Shw: Root Nested paging table. */
1558	PGMPOOLKIND_ROOT_NESTED,
1559
1560	/** The last valid entry. */
1561	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1562	} PGMPOOLKIND;
1563
1564
1565	/**
1566	* The tracking data for a page in the pool.
1567	*/
1568	typedef struct PGMPOOLPAGE
1569	{
1570	/** AVL node code with the (R3) physical address of this page. */
1571	AVLOHCPHYSNODECORE Core;
1572	/** Pointer to the R3 mapping of the page. */
1573	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1574	R3PTRTYPE(void *) pvPageR3;
1575	#else
1576	R3R0PTRTYPE(void *) pvPageR3;
1577	#endif
1578	/** The guest physical address. */
1579	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1580	uint32_t Alignment0;
1581	#endif
1582	RTGCPHYS GCPhys;
1583	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1584	uint8_t enmKind;
1585	uint8_t bPadding;
1586	/** The index of this page. */
1587	uint16_t idx;
1588	/** The next entry in the list this page currently resides in.
1589	* It's either in the free list or in the GCPhys hash. */
1590	uint16_t iNext;
1591	#ifdef PGMPOOL_WITH_USER_TRACKING
1592	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1593	uint16_t iUserHead;
1594	/** The number of present entries. */
1595	uint16_t cPresent;
1596	/** The first entry in the table which is present. */
1597	uint16_t iFirstPresent;
1598	#endif
1599	#ifdef PGMPOOL_WITH_MONITORING
1600	/** The number of modifications to the monitored page. */
1601	uint16_t cModifications;
1602	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1603	uint16_t iModifiedNext;
1604	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1605	uint16_t iModifiedPrev;
1606	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1607	uint16_t iMonitoredNext;
1608	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1609	uint16_t iMonitoredPrev;
1610	#endif
1611	#ifdef PGMPOOL_WITH_CACHE
1612	/** The next page in the age list. */
1613	uint16_t iAgeNext;
1614	/** The previous page in the age list. */
1615	uint16_t iAgePrev;
1616	#endif /* PGMPOOL_WITH_CACHE */
1617	/** Used to indicate that the page is zeroed. */
1618	bool fZeroed;
1619	/** Used to indicate that a PT has non-global entries. */
1620	bool fSeenNonGlobal;
1621	/** Used to indicate that we're monitoring writes to the guest page. */
1622	bool fMonitored;
1623	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1624	* (All pages are in the age list.) */
1625	bool fCached;
1626	/** This is used by the R3 access handlers when invoked by an async thread.
1627	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1628	bool volatile fReusedFlushPending;
1629	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1630	* In these cases the access handler acts differently and will check
1631	* for mapping conflicts like the normal CR3 handler.
1632	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1633	* replaced by a list of pages which share access handler.
1634	*/
1635	bool fCR3Mix;
1636	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1637
1638
1639	#ifdef PGMPOOL_WITH_CACHE
1640	/** The hash table size. */
1641	# define PGMPOOL_HASH_SIZE 0x40
1642	/** The hash function. */
1643	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1644	#endif
1645
1646
1647	/**
1648	* The shadow page pool instance data.
1649	*
1650	* It's all one big allocation made at init time, except for the
1651	* pages that is. The user nodes follows immediatly after the
1652	* page structures.
1653	*/
1654	typedef struct PGMPOOL
1655	{
1656	/** The VM handle - R3 Ptr. */
1657	PVMR3 pVMR3;
1658	/** The VM handle - R0 Ptr. */
1659	PVMR0 pVMR0;
1660	/** The VM handle - RC Ptr. */
1661	PVMRC pVMRC;
1662	/** The max pool size. This includes the special IDs. */
1663	uint16_t cMaxPages;
1664	/** The current pool size. */
1665	uint16_t cCurPages;
1666	/** The head of the free page list. */
1667	uint16_t iFreeHead;
1668	/* Padding. */
1669	uint16_t u16Padding;
1670	#ifdef PGMPOOL_WITH_USER_TRACKING
1671	/** Head of the chain of free user nodes. */
1672	uint16_t iUserFreeHead;
1673	/** The number of user nodes we've allocated. */
1674	uint16_t cMaxUsers;
1675	/** The number of present page table entries in the entire pool. */
1676	uint32_t cPresent;
1677	/** Pointer to the array of user nodes - RC pointer. */
1678	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1679	/** Pointer to the array of user nodes - R3 pointer. */
1680	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1681	/** Pointer to the array of user nodes - R0 pointer. */
1682	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1683	#endif /* PGMPOOL_WITH_USER_TRACKING */
1684	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1685	/** Head of the chain of free phys ext nodes. */
1686	uint16_t iPhysExtFreeHead;
1687	/** The number of user nodes we've allocated. */
1688	uint16_t cMaxPhysExts;
1689	/** Pointer to the array of physical xref extent - RC pointer. */
1690	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1691	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1692	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1693	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1694	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1695	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1696	#ifdef PGMPOOL_WITH_CACHE
1697	/** Hash table for GCPhys addresses. */
1698	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1699	/** The head of the age list. */
1700	uint16_t iAgeHead;
1701	/** The tail of the age list. */
1702	uint16_t iAgeTail;
1703	/** Set if the cache is enabled. */
1704	bool fCacheEnabled;
1705	#endif /* PGMPOOL_WITH_CACHE */
1706	#ifdef PGMPOOL_WITH_MONITORING
1707	/** Head of the list of modified pages. */
1708	uint16_t iModifiedHead;
1709	/** The current number of modified pages. */
1710	uint16_t cModifiedPages;
1711	/** Access handler, RC. */
1712	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1713	/** Access handler, R0. */
1714	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1715	/** Access handler, R3. */
1716	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1717	/** The access handler description (HC ptr). */
1718	R3PTRTYPE(const char *) pszAccessHandler;
1719	#endif /* PGMPOOL_WITH_MONITORING */
1720	/** The number of pages currently in use. */
1721	uint16_t cUsedPages;
1722	#ifdef VBOX_WITH_STATISTICS
1723	/** The high wather mark for cUsedPages. */
1724	uint16_t cUsedPagesHigh;
1725	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1726	/** Profiling pgmPoolAlloc(). */
1727	STAMPROFILEADV StatAlloc;
1728	/** Profiling pgmPoolClearAll(). */
1729	STAMPROFILE StatClearAll;
1730	/** Profiling pgmPoolFlushAllInt(). */
1731	STAMPROFILE StatFlushAllInt;
1732	/** Profiling pgmPoolFlushPage(). */
1733	STAMPROFILE StatFlushPage;
1734	/** Profiling pgmPoolFree(). */
1735	STAMPROFILE StatFree;
1736	/** Profiling time spent zeroing pages. */
1737	STAMPROFILE StatZeroPage;
1738	# ifdef PGMPOOL_WITH_USER_TRACKING
1739	/** Profiling of pgmPoolTrackDeref. */
1740	STAMPROFILE StatTrackDeref;
1741	/** Profiling pgmTrackFlushGCPhysPT. */
1742	STAMPROFILE StatTrackFlushGCPhysPT;
1743	/** Profiling pgmTrackFlushGCPhysPTs. */
1744	STAMPROFILE StatTrackFlushGCPhysPTs;
1745	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1746	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1747	/** Number of times we've been out of user records. */
1748	STAMCOUNTER StatTrackFreeUpOneUser;
1749	# endif
1750	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1751	/** Profiling deref activity related tracking GC physical pages. */
1752	STAMPROFILE StatTrackDerefGCPhys;
1753	/** Number of linear searches for a HCPhys in the ram ranges. */
1754	STAMCOUNTER StatTrackLinearRamSearches;
1755	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1756	STAMCOUNTER StamTrackPhysExtAllocFailures;
1757	# endif
1758	# ifdef PGMPOOL_WITH_MONITORING
1759	/** Profiling the RC/R0 access handler. */
1760	STAMPROFILE StatMonitorRZ;
1761	/** Times we've failed interpreting the instruction. */
1762	STAMCOUNTER StatMonitorRZEmulateInstr;
1763	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1764	STAMPROFILE StatMonitorRZFlushPage;
1765	/** Times we've detected fork(). */
1766	STAMCOUNTER StatMonitorRZFork;
1767	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1768	STAMPROFILE StatMonitorRZHandled;
1769	/** Times we've failed interpreting a patch code instruction. */
1770	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1771	/** Times we've failed interpreting a patch code instruction during flushing. */
1772	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1773	/** The number of times we've seen rep prefixes we can't handle. */
1774	STAMCOUNTER StatMonitorRZRepPrefix;
1775	/** Profiling the REP STOSD cases we've handled. */
1776	STAMPROFILE StatMonitorRZRepStosd;
1777
1778	/** Profiling the R3 access handler. */
1779	STAMPROFILE StatMonitorR3;
1780	/** Times we've failed interpreting the instruction. */
1781	STAMCOUNTER StatMonitorR3EmulateInstr;
1782	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1783	STAMPROFILE StatMonitorR3FlushPage;
1784	/** Times we've detected fork(). */
1785	STAMCOUNTER StatMonitorR3Fork;
1786	/** Profiling the R3 access we've handled (except REP STOSD). */
1787	STAMPROFILE StatMonitorR3Handled;
1788	/** The number of times we've seen rep prefixes we can't handle. */
1789	STAMCOUNTER StatMonitorR3RepPrefix;
1790	/** Profiling the REP STOSD cases we've handled. */
1791	STAMPROFILE StatMonitorR3RepStosd;
1792	/** The number of times we're called in an async thread an need to flush. */
1793	STAMCOUNTER StatMonitorR3Async;
1794	/** The high wather mark for cModifiedPages. */
1795	uint16_t cModifiedPagesHigh;
1796	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1797	# endif
1798	# ifdef PGMPOOL_WITH_CACHE
1799	/** The number of cache hits. */
1800	STAMCOUNTER StatCacheHits;
1801	/** The number of cache misses. */
1802	STAMCOUNTER StatCacheMisses;
1803	/** The number of times we've got a conflict of 'kind' in the cache. */
1804	STAMCOUNTER StatCacheKindMismatches;
1805	/** Number of times we've been out of pages. */
1806	STAMCOUNTER StatCacheFreeUpOne;
1807	/** The number of cacheable allocations. */
1808	STAMCOUNTER StatCacheCacheable;
1809	/** The number of uncacheable allocations. */
1810	STAMCOUNTER StatCacheUncacheable;
1811	# endif
1812	#elif HC_ARCH_BITS == 64
1813	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1814	#endif
1815	/** The AVL tree for looking up a page by its HC physical address. */
1816	AVLOHCPHYSTREE HCPhysTree;
1817	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1818	/** Array of pages. (cMaxPages in length)
1819	* The Id is the index into thist array.
1820	*/
1821	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1822	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1823
1824
1825	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1826	DECLINLINE(void *) pgmPoolMapPageInlined(PVM pVM, PPGMPOOLPAGE pPage);
1827	#endif
1828
1829	/** @def PGMPOOL_PAGE_2_PTR
1830	* Maps a pool page pool into the current context.
1831	*
1832	* @returns VBox status code.
1833	* @param pVM The VM handle.
1834	* @param pPage The pool page.
1835	*
1836	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1837	* small page window employeed by that function. Be careful.
1838	* @remark There is no need to assert on the result.
1839	*/
1840	#if defined(IN_RC)
1841	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1842	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1843	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1844	#elif defined(VBOX_STRICT)
1845	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1846	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1847	{
1848	Assert(pPage->pvPageR3);
1849	return pPage->pvPageR3;
1850	}
1851	#else
1852	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1853	#endif
1854
1855	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1856	* Maps a pool page pool into the current context.
1857	*
1858	* @returns VBox status code.
1859	* @param pPGM Pointer to the PGM instance data.
1860	* @param pPage The pool page.
1861	*
1862	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1863	* small page window employeed by that function. Be careful.
1864	* @remark There is no need to assert on the result.
1865	*/
1866	#if defined(IN_RC)
1867	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1868	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1869	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1870	#else
1871	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1872	#endif
1873
1874
1875
1876	/**
1877	* Trees are using self relative offsets as pointers.
1878	* So, all its data, including the root pointer, must be in the heap for HC and GC
1879	* to have the same layout.
1880	*/
1881	typedef struct PGMTREES
1882	{
1883	/** Physical access handlers (AVL range+offsetptr tree). */
1884	AVLROGCPHYSTREE PhysHandlers;
1885	/** Virtual access handlers (AVL range + GC ptr tree). */
1886	AVLROGCPTRTREE VirtHandlers;
1887	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1888	AVLROGCPHYSTREE PhysToVirtHandlers;
1889	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1890	AVLROGCPTRTREE HyperVirtHandlers;
1891	} PGMTREES;
1892	/** Pointer to PGM trees. */
1893	typedef PGMTREES *PPGMTREES;
1894
1895
1896	/** @name Paging mode macros
1897	* @{ */
1898	#ifdef IN_RC
1899	# define PGM_CTX(a,b) a##RC##b
1900	# define PGM_CTX_STR(a,b) a "GC" b
1901	# define PGM_CTX_DECL(type) VMMRCDECL(type)
1902	#else
1903	# ifdef IN_RING3
1904	# define PGM_CTX(a,b) a##R3##b
1905	# define PGM_CTX_STR(a,b) a "R3" b
1906	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1907	# else
1908	# define PGM_CTX(a,b) a##R0##b
1909	# define PGM_CTX_STR(a,b) a "R0" b
1910	# define PGM_CTX_DECL(type) VMMDECL(type)
1911	# endif
1912	#endif
1913
1914	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1915	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1916	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1917	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1918	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1919	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1920	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1921	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1922	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1923	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1924	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1925	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1926	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1927	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1928	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1929	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1930	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1931
1932	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1933	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1934	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1935	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1936	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1937	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1938	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1939	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1940	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1941	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1942	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1943	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1944	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1945	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1946	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1947	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1948	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1949
1950	/* Shw_Gst */
1951	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1952	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1953	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1954	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1955	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1956	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1957	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1958	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1959	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1960	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1961	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1962	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1963	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1964	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1965	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1966	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1967	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1968	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1969	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1970
1971	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1972	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1973	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1974	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1975	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1976	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1977	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1978	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1979	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1980	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1981	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1982	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1983	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1984	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1985	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1986	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1987	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1988	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1989	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1990	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1991	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1992	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1993	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1994	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1995	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1996	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1997	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1998	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1999	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2000	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2001	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2002	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2003	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2004	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2005	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2006	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2007	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2008
2009	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2010	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2011	/** @} */
2012
2013	/**
2014	* Data for each paging mode.
2015	*/
2016	typedef struct PGMMODEDATA
2017	{
2018	/** The guest mode type. */
2019	uint32_t uGstType;
2020	/** The shadow mode type. */
2021	uint32_t uShwType;
2022
2023	/** @name Function pointers for Shadow paging.
2024	* @{
2025	*/
2026	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2027	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2028	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2029	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2030
2031	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2032	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2033
2034	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2035	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2036	/** @} */
2037
2038	/** @name Function pointers for Guest paging.
2039	* @{
2040	*/
2041	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2042	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2043	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2044	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2045	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2046	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2047	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2048	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2049	#endif
2050	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2051	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2052	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2053	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2054	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2055	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2056	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2057	#endif
2058	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2059	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2060	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2061	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2062	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2063	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2064	#endif
2065	DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2066	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2067	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2068	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2069	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2070	#endif
2071	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2072	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2073	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2074	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2075	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2076	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2077	#endif
2078	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2079	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2080	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2081	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2082	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2083	#endif
2084	/** @} */
2085
2086	/** @name Function pointers for Both Shadow and Guest paging.
2087	* @{
2088	*/
2089	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2090	/* no pfnR3BthTrap0eHandler */
2091	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2092	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2093	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2094	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2095	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2096	#ifdef VBOX_STRICT
2097	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2098	#endif
2099
2100	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2101	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2102	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2103	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2104	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2105	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2106	#ifdef VBOX_STRICT
2107	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2108	#endif
2109
2110	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2111	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2112	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2113	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2114	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2115	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2116	#ifdef VBOX_STRICT
2117	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2118	#endif
2119	/** @} */
2120	} PGMMODEDATA, *PPGMMODEDATA;
2121
2122
2123
2124	/**
2125	* Converts a PGM pointer into a VM pointer.
2126	* @returns Pointer to the VM structure the PGM is part of.
2127	* @param pPGM Pointer to PGM instance data.
2128	*/
2129	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2130
2131	/**
2132	* PGM Data (part of VM)
2133	*/
2134	typedef struct PGM
2135	{
2136	/** Offset to the VM structure. */
2137	RTINT offVM;
2138	/** Offset of the PGMCPU structure relative to VMCPU. */
2139	int32_t offVCpu;
2140	/** Alignment padding. */
2141	int32_t i32Alignment;
2142
2143	/*
2144	* This will be redefined at least two more times before we're done, I'm sure.
2145	* The current code is only to get on with the coding.
2146	* - 2004-06-10: initial version, bird.
2147	* - 2004-07-02: 1st time, bird.
2148	* - 2004-10-18: 2nd time, bird.
2149	* - 2005-07-xx: 3rd time, bird.
2150	*/
2151
2152	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2153	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2154	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2155	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2156
2157	/** The host paging mode. (This is what SUPLib reports.) */
2158	SUPPAGINGMODE enmHostMode;
2159	/** The shadow paging mode. */
2160	PGMMODE enmShadowMode;
2161	/** The guest paging mode. */
2162	PGMMODE enmGuestMode;
2163
2164	/** The current physical address representing in the guest CR3 register. */
2165	RTGCPHYS GCPhysCR3;
2166	/** Pointer to the 5 page CR3 content mapping.
2167	* The first page is always the CR3 (in some form) while the 4 other pages
2168	* are used of the PDs in PAE mode. */
2169	RTGCPTR GCPtrCR3Mapping;
2170	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2171	uint32_t u32Alignment;
2172	#endif
2173	/** The physical address of the currently monitored guest CR3 page.
2174	* When this value is NIL_RTGCPHYS no page is being monitored. */
2175	RTGCPHYS GCPhysGstCR3Monitored;
2176
2177	/** @name 32-bit Guest Paging.
2178	* @{ */
2179	/** The guest's page directory, R3 pointer. */
2180	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2181	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2182	/** The guest's page directory, R0 pointer. */
2183	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2184	#endif
2185	/** The guest's page directory, static RC mapping. */
2186	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2187	/** @} */
2188
2189	/** @name PAE Guest Paging.
2190	* @{ */
2191	/** The guest's page directory pointer table, static RC mapping. */
2192	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2193	/** The guest's page directory pointer table, R3 pointer. */
2194	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2195	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2196	/** The guest's page directory pointer table, R0 pointer. */
2197	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2198	#endif
2199
2200	/** The guest's page directories, R3 pointers.
2201	* These are individual pointers and don't have to be adjecent.
2202	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2203	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2204	/** The guest's page directories, R0 pointers.
2205	* Same restrictions as apGstPaePDsR3. */
2206	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2207	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2208	#endif
2209	/** The guest's page directories, static GC mapping.
2210	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2211	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2212	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2213	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2214	RTGCPHYS aGCPhysGstPaePDs[4];
2215	/** The physical addresses of the monitored guest page directories (PAE). */
2216	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2217	/** @} */
2218
2219	/** @name AMD64 Guest Paging.
2220	* @{ */
2221	/** The guest's page directory pointer table, R3 pointer. */
2222	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2223	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2224	/** The guest's page directory pointer table, R0 pointer. */
2225	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2226	#endif
2227	/** @} */
2228
2229	/** @name Shadow paging
2230	* @{ */
2231	/** The root page table - R3 Ptr. */
2232	R3PTRTYPE(void *) pShwRootR3;
2233	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2234	/** The root page table - R0 Ptr. */
2235	R0PTRTYPE(void *) pShwRootR0;
2236	# endif
2237	/** The Physical Address (HC) of the current active shadow CR3. */
2238	RTHCPHYS HCPhysShwCR3;
2239	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2240	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2241	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2242	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2243	/** Pointer to the page of the current active CR3 - RC Ptr. */
2244	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2245	# if HC_ARCH_BITS == 64
2246	RTRCPTR alignment6; /*< structure size alignment. /
2247	# endif
2248	/** @} */
2249	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2250	/** @name 32-bit Shadow Paging
2251	* @{ */
2252	/** The 32-Bit PD - R3 Ptr. */
2253	R3PTRTYPE(PX86PD) pShw32BitPdR3;
2254	/** The 32-Bit PD - R0 Ptr. */
2255	R0PTRTYPE(PX86PD) pShw32BitPdR0;
2256	/** The 32-Bit PD - RC Ptr. */
2257	RCPTRTYPE(PX86PD) pShw32BitPdRC;
2258	# if HC_ARCH_BITS == 64
2259	uint32_t u32Padding1; /*< alignment padding. /
2260	# endif
2261	/** The Physical Address (HC) of the 32-Bit PD. */
2262	RTHCPHYS HCPhysShw32BitPD;
2263	/** @} */
2264
2265	/** @name PAE Shadow Paging
2266	* @{ */
2267	/** The four PDs for the low 4GB - R3 Ptr.
2268	* Even though these are 4 pointers, what they point at is a single table.
2269	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2270	R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2271	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2272	/** The four PDs for the low 4GB - R0 Ptr.
2273	* Same kind of mapping as apHCPaePDs. */
2274	R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2275	# endif
2276	/** The four PDs for the low 4GB - RC Ptr.
2277	* Same kind of mapping as apHCPaePDs. */
2278	RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2279	/** The Physical Address (HC) of the four PDs for the low 4GB.
2280	* These are NOT 4 contiguous pages. */
2281	RTHCPHYS aHCPhysPaePDs[4];
2282	/** The Physical Address (HC) of the PAE PDPT. */
2283	RTHCPHYS HCPhysShwPaePdpt;
2284	/** The PAE PDPT - R3 Ptr. */
2285	R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2286	/** The PAE PDPT - R0 Ptr. */
2287	R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2288	/** The PAE PDPT - RC Ptr. */
2289	RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2290	/** @} */
2291	# if HC_ARCH_BITS == 64
2292	RTRCPTR alignment5; /*< structure size alignment. /
2293	# endif
2294
2295	/** @name Nested Shadow Paging
2296	* @{ */
2297	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2298	RTR3PTR pShwNestedRootR3;
2299	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2300	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2301	RTR0PTR pShwNestedRootR0;
2302	# endif
2303	/** The Physical Address (HC) of the nested paging root. */
2304	RTHCPHYS HCPhysShwNestedRoot;
2305	#endif
2306	/** @} */
2307
2308	/** @name Function pointers for Shadow paging.
2309	* @{
2310	*/
2311	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2312	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2313	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2314	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2315
2316	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2317	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2318
2319	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2320	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2321
2322	/** @} */
2323
2324	/** @name Function pointers for Guest paging.
2325	* @{
2326	*/
2327	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2328	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2329	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2330	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2331	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2332	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2333	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2334	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2335	#endif
2336	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2337	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2338	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2339	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2340	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2341	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2342	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2343	#endif
2344	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2345	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2346	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2347	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2348	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2349	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2350	#endif
2351	DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2352	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2353	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2354	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2355	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2356	#endif
2357	#if HC_ARCH_BITS == 64
2358	RTRCPTR alignment3; /*< structure size alignment. /
2359	#endif
2360
2361	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2362	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2363	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2364	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2365	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2366	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2367	#endif
2368	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2369	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2370	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2371	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2372	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2373	#endif
2374	/** @} */
2375
2376	/** @name Function pointers for Both Shadow and Guest paging.
2377	* @{
2378	*/
2379	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2380	/* no pfnR3BthTrap0eHandler */
2381	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2382	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2383	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2384	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2385	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2386	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2387
2388	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2389	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2390	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2391	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2392	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2393	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2394	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2395
2396	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2397	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2398	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2399	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2400	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2401	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2402	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2403	#if HC_ARCH_BITS == 64
2404	RTRCPTR alignment2; /*< structure size alignment. /
2405	#endif
2406	/** @} */
2407
2408	/** Pointer to SHW+GST mode data (function pointers).
2409	* The index into this table is made up from */
2410	R3PTRTYPE(PPGMMODEDATA) paModeData;
2411
2412	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2413	* This is sorted by physical address and contains no overlapping ranges. */
2414	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2415	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2416	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2417	/** RC pointer corresponding to PGM::pRamRangesR3. */
2418	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2419	/** The configured RAM size. */
2420	RTUINT cbRamSize;
2421
2422	/** Pointer to the list of ROM ranges - for R3.
2423	* This is sorted by physical address and contains no overlapping ranges. */
2424	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2425	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2426	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2427	/** RC pointer corresponding to PGM::pRomRangesR3. */
2428	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2429	/** Alignment padding. */
2430	RTRCPTR GCPtrPadding2;
2431
2432	/** Pointer to the list of MMIO2 ranges - for R3.
2433	* Registration order. */
2434	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2435
2436	/** PGM offset based trees - R3 Ptr. */
2437	R3PTRTYPE(PPGMTREES) pTreesR3;
2438	/** PGM offset based trees - R0 Ptr. */
2439	R0PTRTYPE(PPGMTREES) pTreesR0;
2440	/** PGM offset based trees - RC Ptr. */
2441	RCPTRTYPE(PPGMTREES) pTreesRC;
2442
2443	/** Linked list of GC mappings - for RC.
2444	* The list is sorted ascending on address.
2445	*/
2446	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2447	/** Linked list of GC mappings - for HC.
2448	* The list is sorted ascending on address.
2449	*/
2450	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2451	/** Linked list of GC mappings - for R0.
2452	* The list is sorted ascending on address.
2453	*/
2454	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2455
2456	/** If set no conflict checks are required. (boolean) */
2457	bool fMappingsFixed;
2458	/** If set, then no mappings are put into the shadow page table. (boolean) */
2459	bool fDisableMappings;
2460	/** Size of fixed mapping */
2461	uint32_t cbMappingFixed;
2462	/** Base address (GC) of fixed mapping */
2463	RTGCPTR GCPtrMappingFixed;
2464	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2465	uint32_t u32Padding0; /*< alignment padding. /
2466	#endif
2467
2468
2469	/** @name Intermediate Context
2470	* @{ */
2471	/** Pointer to the intermediate page directory - Normal. */
2472	R3PTRTYPE(PX86PD) pInterPD;
2473	/** Pointer to the intermedate page tables - Normal.
2474	* There are two page tables, one for the identity mapping and one for
2475	* the host context mapping (of the core code). */
2476	R3PTRTYPE(PX86PT) apInterPTs[2];
2477	/** Pointer to the intermedate page tables - PAE. */
2478	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2479	/** Pointer to the intermedate page directory - PAE. */
2480	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2481	/** Pointer to the intermedate page directory - PAE. */
2482	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2483	/** Pointer to the intermedate page-map level 4 - AMD64. */
2484	R3PTRTYPE(PX86PML4) pInterPaePML4;
2485	/** Pointer to the intermedate page directory - AMD64. */
2486	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2487	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2488	RTHCPHYS HCPhysInterPD;
2489	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2490	RTHCPHYS HCPhysInterPaePDPT;
2491	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2492	RTHCPHYS HCPhysInterPaePML4;
2493	/** @} */
2494
2495	/** Base address of the dynamic page mapping area.
2496	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2497	*/
2498	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2499	/** The index of the last entry used in the dynamic page mapping area. */
2500	RTUINT iDynPageMapLast;
2501	/** Cache containing the last entries in the dynamic page mapping area.
2502	* The cache size is covering half of the mapping area. */
2503	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2504
2505	/** The address of the ring-0 mapping cache if we're making use of it. */
2506	RTR0PTR pvR0DynMapUsed;
2507	#if HC_ARCH_BITS == 32
2508	RTR0PTR R0PtrPadding0; /*< Alignment. /
2509	#endif
2510
2511
2512	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2513	RTGCPHYS GCPhys4MBPSEMask;
2514
2515	/** A20 gate mask.
2516	* Our current approach to A20 emulation is to let REM do it and don't bother
2517	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2518	* But whould need arrise, we'll subject physical addresses to this mask. */
2519	RTGCPHYS GCPhysA20Mask;
2520	/** A20 gate state - boolean! */
2521	RTUINT fA20Enabled;
2522
2523	/** What needs syncing (PGM_SYNC_*).
2524	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2525	* PGMFlushTLB, and PGMR3Load. */
2526	RTUINT fSyncFlags;
2527
2528	/** PGM critical section.
2529	* This protects the physical & virtual access handlers, ram ranges,
2530	* and the page flag updating (some of it anyway).
2531	*/
2532	PDMCRITSECT CritSect;
2533
2534	/** Shadow Page Pool - R3 Ptr. */
2535	R3PTRTYPE(PPGMPOOL) pPoolR3;
2536	/** Shadow Page Pool - R0 Ptr. */
2537	R0PTRTYPE(PPGMPOOL) pPoolR0;
2538	/** Shadow Page Pool - RC Ptr. */
2539	RCPTRTYPE(PPGMPOOL) pPoolRC;
2540
2541	/** We're not in a state which permits writes to guest memory.
2542	* (Only used in strict builds.) */
2543	bool fNoMorePhysWrites;
2544
2545	/** Flush the cache on the next access. */
2546	bool fPhysCacheFlushPending;
2547	/** @todo r=bird: Fix member names!*/
2548	/** PGMPhysRead cache */
2549	PGMPHYSCACHE pgmphysreadcache;
2550	/** PGMPhysWrite cache */
2551	PGMPHYSCACHE pgmphyswritecache;
2552
2553	/**
2554	* Data associated with managing the ring-3 mappings of the allocation chunks.
2555	*/
2556	struct
2557	{
2558	/** The chunk tree, ordered by chunk id. */
2559	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2560	R3PTRTYPE(PAVLU32NODECORE) pTree;
2561	#else
2562	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2563	#endif
2564	/** The chunk mapping TLB. */
2565	PGMCHUNKR3MAPTLB Tlb;
2566	/** The number of mapped chunks. */
2567	uint32_t c;
2568	/** The maximum number of mapped chunks.
2569	* @cfgm PGM/MaxRing3Chunks */
2570	uint32_t cMax;
2571	/** The chunk age tree, ordered by ageing sequence number. */
2572	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2573	/** The current time. */
2574	uint32_t iNow;
2575	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2576	uint32_t AgeingCountdown;
2577	} ChunkR3Map;
2578
2579	/**
2580	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2581	*/
2582	PGMPAGER3MAPTLB PhysTlbHC;
2583
2584	/** @name The zero page.
2585	* @{ */
2586	/** The host physical address of the zero page. */
2587	RTHCPHYS HCPhysZeroPg;
2588	/** The ring-3 mapping of the zero page. */
2589	RTR3PTR pvZeroPgR3;
2590	/** The ring-0 mapping of the zero page. */
2591	RTR0PTR pvZeroPgR0;
2592	/** The GC mapping of the zero page. */
2593	RTGCPTR pvZeroPgGC;
2594	#if GC_ARCH_BITS != 32
2595	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2596	#endif
2597	/** @}*/
2598
2599	/** The number of handy pages. */
2600	uint32_t cHandyPages;
2601	/**
2602	* Array of handy pages.
2603	*
2604	* This array is used in a two way communication between pgmPhysAllocPage
2605	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2606	* an intermediary.
2607	*
2608	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2609	* (The current size of 32 pages, means 128 KB of handy memory.)
2610	*/
2611	GMMPAGEDESC aHandyPages[32];
2612
2613	/** @name Release Statistics
2614	* @{ */
2615	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2616	uint32_t cPrivatePages; /*< The number of private pages. /
2617	uint32_t cSharedPages; /*< The number of shared pages. /
2618	uint32_t cZeroPages; /*< The number of zero backed pages. /
2619	/** The number of times the guest has switched mode since last reset or statistics reset. */
2620	STAMCOUNTER cGuestModeChanges;
2621	/** @} */
2622
2623	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2624	/** RC: Which statistic this \#PF should be attributed to. */
2625	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2626	RTRCPTR padding0;
2627	/** R0: Which statistic this \#PF should be attributed to. */
2628	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2629	RTR0PTR padding1;
2630
2631	/* Common */
2632	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2633	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2634	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2635	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2636	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2637	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2638	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2639	# endif
2640	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2641	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2642
2643	/* R3 only: */
2644	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2645	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2646	STAMCOUNTER StatR3GuestPDWrite; /*< R3: The total number of times pgmHCGuestPDWriteHandler() was called. /
2647	STAMCOUNTER StatR3GuestPDWriteConflict; /*< R3: The number of times GuestPDWriteContlict() detected a conflict. /
2648	STAMCOUNTER StatR3DynRamTotal; /*< R3: Allocated MBs of guest ram /
2649	STAMCOUNTER StatR3DynRamGrow; /*< R3: Nr of pgmr3PhysGrowRange calls. /
2650
2651	/* R0 only: */
2652	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2653	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2654	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2655	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2656	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2657	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2658	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2659	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2660	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2661	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2662	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2663	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2664	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2665	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2666	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2667	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2668	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2669	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2670	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2671	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2672	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2673	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2674	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2675	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2676	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2677	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
2678
2679	/* RC only: */
2680	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache hits /
2681	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache misses /
2682	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2683	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2684
2685	/* RZ only: */
2686	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2687	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2688	STAMPROFILE StatRZTrap0eTimeSyncPT;
2689	STAMPROFILE StatRZTrap0eTimeMapping;
2690	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2691	STAMPROFILE StatRZTrap0eTimeHandlers;
2692	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2693	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2694	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2695	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2696	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2697	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2698	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2699	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2700	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2701	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2702	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2703	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2704	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2705	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2706	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2707	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2708	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2709	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2710	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2711	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2712	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2713	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2714	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2715	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2716	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2717	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2718	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2719	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2720	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2721	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2722	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2723	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2724	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2725	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2726	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2727	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2728	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2729	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2730	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2731	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2732	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2733	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2734	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2735
2736	/* HC - R3 and (maybe) R0: */
2737
2738	/* RZ & R3: */
2739	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2740	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2741	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2742	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2743	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2744	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2745	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2746	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2747	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2748	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2749	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2750	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2751	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2752	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2753	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2754	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2755	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2756	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2757	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2758	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2759	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2760	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2761	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2762	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2763	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2764	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2765	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2766	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2767	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2768	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2769	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2770	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2771	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2772	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2773	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2774	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2775	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2776	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2777	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2778	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2779	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2780	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2781	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2782	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2783	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2784	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2785	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2786	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2787	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2788	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2789	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2790	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2791	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2792	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2793
2794	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2795	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2796	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2797	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2798	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2799	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2800	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2801	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2802	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2803	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2804	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2805	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2806	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2807	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2808	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2809	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2810	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2811	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2812	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2813	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2814	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2815	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2816	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2817	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2818	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2819	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2820	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2821	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2822	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2823	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2824	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2825	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2826	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2827	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2828	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2829	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2830	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2831	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2832	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2833	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2834	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2835	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2836	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2837	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2838	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2839	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2840	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2841	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2842	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2843	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2844	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2845	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2846	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2847	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2848	#endif /* VBOX_WITH_STATISTICS */
2849	} PGM;
2850	/** Pointer to the PGM instance data. */
2851	typedef PGM *PPGM;
2852
2853
2854	/**
2855	* PGMCPU Data (part of VMCPU).
2856	*/
2857	typedef struct PGMCPU
2858	{
2859	/** Offset to the VMCPU structure. */
2860	RTINT offVMCPU;
2861	/** Automatically tracked physical memory mapping set.
2862	* Ring-0 and strict raw-mode builds. */
2863	PGMMAPSET AutoSet;
2864	} PGMCPU;
2865	/** Pointer to the per-cpu PGM data. */
2866	typedef PGMCPU *PPGMCPU;
2867
2868
2869	/** @name PGM::fSyncFlags Flags
2870	* @{
2871	*/
2872	/** Updates the virtual access handler state bit in PGMPAGE. */
2873	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2874	/** Always sync CR3. */
2875	#define PGM_SYNC_ALWAYS RT_BIT(1)
2876	/** Check monitoring on next CR3 (re)load and invalidate page. */
2877	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2878	/** Check guest mapping in SyncCR3. */
2879	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2880	/** Clear the page pool (a light weight flush). */
2881	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2882	/** @} */
2883
2884
2885	__BEGIN_DECLS
2886
2887	int pgmLock(PVM pVM);
2888	void pgmUnlock(PVM pVM);
2889
2890	VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2891	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2892
2893	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2894	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2895	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2896	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2897	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2898
2899	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2900	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2901	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2902	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2903	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2904	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2905	#else
2906	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2907	#endif
2908	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2909
2910
2911	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2912	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2913	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2914	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2915	#ifdef IN_RING3
2916	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2917	int pgmR3PhysRamReset(PVM pVM);
2918	int pgmR3PhysRomReset(PVM pVM);
2919	# ifndef VBOX_WITH_NEW_PHYS_CODE
2920	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2921	# endif
2922
2923	int pgmR3PoolInit(PVM pVM);
2924	void pgmR3PoolRelocate(PVM pVM);
2925	void pgmR3PoolReset(PVM pVM);
2926
2927	#endif /* IN_RING3 */
2928	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2929	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2930	#endif
2931	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2932	void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
2933	#endif
2934	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2935	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2936	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2937	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2938	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2939	void pgmPoolFlushAll(PVM pVM);
2940	void pgmPoolClearAll(PVM pVM);
2941	int pgmPoolSyncCR3(PVM pVM);
2942	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2943	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2944	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2945	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2946	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2947	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2948	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2949	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2950	#ifdef PGMPOOL_WITH_MONITORING
2951	# ifdef IN_RING3
2952	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2953	# else
2954	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2955	# endif
2956	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2957	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2958	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2959	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2960	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2961	#endif
2962
2963	__END_DECLS
2964
2965
2966	/**
2967	* Gets the PGMRAMRANGE structure for a guest page.
2968	*
2969	* @returns Pointer to the RAM range on success.
2970	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2971	*
2972	* @param pPGM PGM handle.
2973	* @param GCPhys The GC physical address.
2974	*/
2975	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2976	{
2977	/*
2978	* Optimize for the first range.
2979	*/
2980	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2981	RTGCPHYS off = GCPhys - pRam->GCPhys;
2982	if (RT_UNLIKELY(off >= pRam->cb))
2983	{
2984	do
2985	{
2986	pRam = pRam->CTX_SUFF(pNext);
2987	if (RT_UNLIKELY(!pRam))
2988	break;
2989	off = GCPhys - pRam->GCPhys;
2990	} while (off >= pRam->cb);
2991	}
2992	return pRam;
2993	}
2994
2995
2996	/**
2997	* Gets the PGMPAGE structure for a guest page.
2998	*
2999	* @returns Pointer to the page on success.
3000	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3001	*
3002	* @param pPGM PGM handle.
3003	* @param GCPhys The GC physical address.
3004	*/
3005	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3006	{
3007	/*
3008	* Optimize for the first range.
3009	*/
3010	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3011	RTGCPHYS off = GCPhys - pRam->GCPhys;
3012	if (RT_UNLIKELY(off >= pRam->cb))
3013	{
3014	do
3015	{
3016	pRam = pRam->CTX_SUFF(pNext);
3017	if (RT_UNLIKELY(!pRam))
3018	return NULL;
3019	off = GCPhys - pRam->GCPhys;
3020	} while (off >= pRam->cb);
3021	}
3022	return &pRam->aPages[off >> PAGE_SHIFT];
3023	}
3024
3025
3026	/**
3027	* Gets the PGMPAGE structure for a guest page.
3028	*
3029	* Old Phys code: Will make sure the page is present.
3030	*
3031	* @returns VBox status code.
3032	* @retval VINF_SUCCESS and a valid *ppPage on success.
3033	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3034	*
3035	* @param pPGM PGM handle.
3036	* @param GCPhys The GC physical address.
3037	* @param ppPage Where to store the page poitner on success.
3038	*/
3039	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3040	{
3041	/*
3042	* Optimize for the first range.
3043	*/
3044	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3045	RTGCPHYS off = GCPhys - pRam->GCPhys;
3046	if (RT_UNLIKELY(off >= pRam->cb))
3047	{
3048	do
3049	{
3050	pRam = pRam->CTX_SUFF(pNext);
3051	if (RT_UNLIKELY(!pRam))
3052	{
3053	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3054	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3055	}
3056	off = GCPhys - pRam->GCPhys;
3057	} while (off >= pRam->cb);
3058	}
3059	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3060	#ifndef VBOX_WITH_NEW_PHYS_CODE
3061
3062	/*
3063	* Make sure it's present.
3064	*/
3065	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3066	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3067	{
3068	#ifdef IN_RING3
3069	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3070	#else
3071	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3072	#endif
3073	if (RT_FAILURE(rc))
3074	{
3075	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3076	return rc;
3077	}
3078	Assert(rc == VINF_SUCCESS);
3079	}
3080	#endif
3081	return VINF_SUCCESS;
3082	}
3083
3084
3085
3086
3087	/**
3088	* Gets the PGMPAGE structure for a guest page.
3089	*
3090	* Old Phys code: Will make sure the page is present.
3091	*
3092	* @returns VBox status code.
3093	* @retval VINF_SUCCESS and a valid *ppPage on success.
3094	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3095	*
3096	* @param pPGM PGM handle.
3097	* @param GCPhys The GC physical address.
3098	* @param ppPage Where to store the page poitner on success.
3099	* @param ppRamHint Where to read and store the ram list hint.
3100	* The caller initializes this to NULL before the call.
3101	*/
3102	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3103	{
3104	RTGCPHYS off;
3105	PPGMRAMRANGE pRam = *ppRamHint;
3106	if ( !pRam
3107	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3108	{
3109	pRam = pPGM->CTX_SUFF(pRamRanges);
3110	off = GCPhys - pRam->GCPhys;
3111	if (RT_UNLIKELY(off >= pRam->cb))
3112	{
3113	do
3114	{
3115	pRam = pRam->CTX_SUFF(pNext);
3116	if (RT_UNLIKELY(!pRam))
3117	{
3118	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3119	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3120	}
3121	off = GCPhys - pRam->GCPhys;
3122	} while (off >= pRam->cb);
3123	}
3124	*ppRamHint = pRam;
3125	}
3126	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3127	#ifndef VBOX_WITH_NEW_PHYS_CODE
3128
3129	/*
3130	* Make sure it's present.
3131	*/
3132	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3133	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3134	{
3135	#ifdef IN_RING3
3136	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3137	#else
3138	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3139	#endif
3140	if (RT_FAILURE(rc))
3141	{
3142	ppPage = NULL; / Shut up annoying smart ass. */
3143	return rc;
3144	}
3145	Assert(rc == VINF_SUCCESS);
3146	}
3147	#endif
3148	return VINF_SUCCESS;
3149	}
3150
3151
3152	/**
3153	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3154	*
3155	* @returns Pointer to the page on success.
3156	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3157	*
3158	* @param pPGM PGM handle.
3159	* @param GCPhys The GC physical address.
3160	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3161	*/
3162	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3163	{
3164	/*
3165	* Optimize for the first range.
3166	*/
3167	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3168	RTGCPHYS off = GCPhys - pRam->GCPhys;
3169	if (RT_UNLIKELY(off >= pRam->cb))
3170	{
3171	do
3172	{
3173	pRam = pRam->CTX_SUFF(pNext);
3174	if (RT_UNLIKELY(!pRam))
3175	return NULL;
3176	off = GCPhys - pRam->GCPhys;
3177	} while (off >= pRam->cb);
3178	}
3179	*ppRam = pRam;
3180	return &pRam->aPages[off >> PAGE_SHIFT];
3181	}
3182
3183
3184	/**
3185	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3186	*
3187	* @returns Pointer to the page on success.
3188	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3189	*
3190	* @param pPGM PGM handle.
3191	* @param GCPhys The GC physical address.
3192	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3193	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3194	*/
3195	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3196	{
3197	/*
3198	* Optimize for the first range.
3199	*/
3200	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3201	RTGCPHYS off = GCPhys - pRam->GCPhys;
3202	if (RT_UNLIKELY(off >= pRam->cb))
3203	{
3204	do
3205	{
3206	pRam = pRam->CTX_SUFF(pNext);
3207	if (RT_UNLIKELY(!pRam))
3208	{
3209	ppRam = NULL; / Shut up silly GCC warnings. */
3210	ppPage = NULL; / ditto */
3211	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3212	}
3213	off = GCPhys - pRam->GCPhys;
3214	} while (off >= pRam->cb);
3215	}
3216	*ppRam = pRam;
3217	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3218	#ifndef VBOX_WITH_NEW_PHYS_CODE
3219
3220	/*
3221	* Make sure it's present.
3222	*/
3223	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3224	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3225	{
3226	#ifdef IN_RING3
3227	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3228	#else
3229	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3230	#endif
3231	if (RT_FAILURE(rc))
3232	{
3233	ppPage = NULL; / Shut up silly GCC warnings. */
3234	ppPage = NULL; / ditto */
3235	return rc;
3236	}
3237	Assert(rc == VINF_SUCCESS);
3238
3239	}
3240	#endif
3241	return VINF_SUCCESS;
3242	}
3243
3244
3245	/**
3246	* Convert GC Phys to HC Phys.
3247	*
3248	* @returns VBox status.
3249	* @param pPGM PGM handle.
3250	* @param GCPhys The GC physical address.
3251	* @param pHCPhys Where to store the corresponding HC physical address.
3252	*
3253	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3254	* Avoid when writing new code!
3255	*/
3256	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3257	{
3258	PPGMPAGE pPage;
3259	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3260	if (RT_FAILURE(rc))
3261	return rc;
3262	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3263	return VINF_SUCCESS;
3264	}
3265
3266	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3267
3268	/**
3269	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3270	* optimizes access to pages already in the set.
3271	*
3272	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3273	* @param pPGM Pointer to the PVM instance data.
3274	* @param HCPhys The physical address of the page.
3275	* @param ppv Where to store the mapping address.
3276	*/
3277	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3278	{
3279	STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3280	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3281	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3282	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3283
3284	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3285	unsigned iEntry = pSet->aiHashTable[iHash];
3286	if ( iEntry < pSet->cEntries
3287	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3288	{
3289	*ppv = pSet->aEntries[iEntry].pvPage;
3290	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3291	}
3292	else
3293	{
3294	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3295	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3296	}
3297
3298	STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3299	return VINF_SUCCESS;
3300	}
3301
3302
3303	/**
3304	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3305	* access to pages already in the set.
3306	*
3307	* @returns See PGMDynMapGCPage.
3308	* @param pPGM Pointer to the PVM instance data.
3309	* @param HCPhys The physical address of the page.
3310	* @param ppv Where to store the mapping address.
3311	*/
3312	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3313	{
3314	STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3315	Assert(!(GCPhys & PAGE_OFFSET_MASK));
3316
3317	/*
3318	* Get the ram range.
3319	*/
3320	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3321	RTGCPHYS off = GCPhys - pRam->GCPhys;
3322	if (RT_UNLIKELY(off >= pRam->cb
3323	/** @todo \|\| page state stuff */))
3324	{
3325	/* This case is not counted into StatR0DynMapGCPageInl. */
3326	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3327	return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3328	}
3329
3330	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3331	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3332
3333	/*
3334	* pgmR0DynMapHCPageInlined with out stats.
3335	*/
3336	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3337	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3338	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3339
3340	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3341	unsigned iEntry = pSet->aiHashTable[iHash];
3342	if ( iEntry < pSet->cEntries
3343	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3344	{
3345	*ppv = pSet->aEntries[iEntry].pvPage;
3346	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3347	}
3348	else
3349	{
3350	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3351	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3352	}
3353
3354	STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3355	return VINF_SUCCESS;
3356	}
3357
3358	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3359
3360	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
3361	/**
3362	* Temporarily maps one host page specified by HC physical address, returning
3363	* pointer within the page.
3364	*
3365	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3366	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3367	*
3368	* @returns The address corresponding to HCPhys.
3369	* @param pPGM Pointer to the PVM instance data.
3370	* @param HCPhys HC Physical address of the page.
3371	*/
3372	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3373	{
3374	void *pv;
3375	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3376	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3377	# else
3378	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3379	# endif
3380	pv = (void *)((uintptr_t)pv \| (HCPhys & PAGE_OFFSET_MASK));
3381	return pv;
3382	}
3383	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3384
3385
3386	#ifndef IN_RC
3387	/**
3388	* Queries the Physical TLB entry for a physical guest page,
3389	* attemting to load the TLB entry if necessary.
3390	*
3391	* @returns VBox status code.
3392	* @retval VINF_SUCCESS on success
3393	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3394	* @param pPGM The PGM instance handle.
3395	* @param GCPhys The address of the guest page.
3396	* @param ppTlbe Where to store the pointer to the TLB entry.
3397	*/
3398
3399	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3400	{
3401	int rc;
3402	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3403	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3404	{
3405	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3406	rc = VINF_SUCCESS;
3407	}
3408	else
3409	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3410	*ppTlbe = pTlbe;
3411	return rc;
3412	}
3413	#endif /* !IN_RC */
3414
3415	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3416
3417	# ifndef VBOX_WITH_NEW_PHYS_CODE
3418	/**
3419	* Convert GC Phys to HC Virt.
3420	*
3421	* @returns VBox status.
3422	* @param pPGM PGM handle.
3423	* @param GCPhys The GC physical address.
3424	* @param pHCPtr Where to store the corresponding HC virtual address.
3425	*
3426	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3427	* pgmPoolMonitorGCPtr2CCPtr.
3428	*/
3429	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3430	{
3431	PPGMRAMRANGE pRam;
3432	PPGMPAGE pPage;
3433	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3434	if (RT_FAILURE(rc))
3435	{
3436	pHCPtr = 0; / Shut up silly GCC warnings. */
3437	return rc;
3438	}
3439	RTGCPHYS off = GCPhys - pRam->GCPhys;
3440
3441	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3442	{
3443	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3444	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3445	return VINF_SUCCESS;
3446	}
3447	if (pRam->pvR3)
3448	{
3449	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3450	return VINF_SUCCESS;
3451	}
3452	pHCPtr = 0; / Shut up silly GCC warnings. */
3453	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3454	}
3455	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3456	#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3457
3458	/**
3459	* Convert GC Phys to HC Virt and HC Phys.
3460	*
3461	* @returns VBox status.
3462	* @param pPGM PGM handle.
3463	* @param GCPhys The GC physical address.
3464	* @param pHCPtr Where to store the corresponding HC virtual address.
3465	* @param pHCPhys Where to store the HC Physical address and its flags.
3466	*
3467	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3468	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3469	*/
3470	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3471	{
3472	PPGMRAMRANGE pRam;
3473	PPGMPAGE pPage;
3474	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3475	if (RT_FAILURE(rc))
3476	{
3477	pHCPtr = 0; / Shut up crappy GCC warnings */
3478	pHCPhys = 0; / ditto */
3479	return rc;
3480	}
3481	RTGCPHYS off = GCPhys - pRam->GCPhys;
3482
3483	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3484	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3485	{
3486	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3487	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3488	PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3489	*pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3490	#else
3491	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3492	#endif
3493	return VINF_SUCCESS;
3494	}
3495	if (pRam->pvR3)
3496	{
3497	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3498	return VINF_SUCCESS;
3499	}
3500	*pHCPtr = 0;
3501	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3502	}
3503
3504
3505	/**
3506	* Clears flags associated with a RAM address.
3507	*
3508	* @returns VBox status code.
3509	* @param pPGM PGM handle.
3510	* @param GCPhys Guest context physical address.
3511	* @param fFlags fFlags to clear. (Bits 0-11.)
3512	*/
3513	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3514	{
3515	PPGMPAGE pPage;
3516	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3517	if (RT_FAILURE(rc))
3518	return rc;
3519
3520	fFlags &= ~X86_PTE_PAE_PG_MASK;
3521	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3522	return VINF_SUCCESS;
3523	}
3524
3525
3526	/**
3527	* Clears flags associated with a RAM address.
3528	*
3529	* @returns VBox status code.
3530	* @param pPGM PGM handle.
3531	* @param GCPhys Guest context physical address.
3532	* @param fFlags fFlags to clear. (Bits 0-11.)
3533	* @param ppRamHint Where to read and store the ram list hint.
3534	* The caller initializes this to NULL before the call.
3535	*/
3536	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3537	{
3538	PPGMPAGE pPage;
3539	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3540	if (RT_FAILURE(rc))
3541	return rc;
3542
3543	fFlags &= ~X86_PTE_PAE_PG_MASK;
3544	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3545	return VINF_SUCCESS;
3546	}
3547
3548
3549	/**
3550	* Sets (bitwise OR) flags associated with a RAM address.
3551	*
3552	* @returns VBox status code.
3553	* @param pPGM PGM handle.
3554	* @param GCPhys Guest context physical address.
3555	* @param fFlags fFlags to set clear. (Bits 0-11.)
3556	*/
3557	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3558	{
3559	PPGMPAGE pPage;
3560	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3561	if (RT_FAILURE(rc))
3562	return rc;
3563
3564	fFlags &= ~X86_PTE_PAE_PG_MASK;
3565	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3566	return VINF_SUCCESS;
3567	}
3568
3569
3570	/**
3571	* Sets (bitwise OR) flags associated with a RAM address.
3572	*
3573	* @returns VBox status code.
3574	* @param pPGM PGM handle.
3575	* @param GCPhys Guest context physical address.
3576	* @param fFlags fFlags to set clear. (Bits 0-11.)
3577	* @param ppRamHint Where to read and store the ram list hint.
3578	* The caller initializes this to NULL before the call.
3579	*/
3580	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3581	{
3582	PPGMPAGE pPage;
3583	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3584	if (RT_FAILURE(rc))
3585	return rc;
3586
3587	fFlags &= ~X86_PTE_PAE_PG_MASK;
3588	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3589	return VINF_SUCCESS;
3590	}
3591
3592
3593	/**
3594	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3595	* Takes PSE-36 into account.
3596	*
3597	* @returns guest physical address
3598	* @param pPGM Pointer to the PGM instance data.
3599	* @param Pde Guest Pde
3600	*/
3601	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3602	{
3603	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3604	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3605
3606	return GCPhys & pPGM->GCPhys4MBPSEMask;
3607	}
3608
3609
3610	/**
3611	* Gets the page directory entry for the specified address (32-bit paging).
3612	*
3613	* @returns The page directory entry in question.
3614	* @param pPGM Pointer to the PGM instance data.
3615	* @param GCPtr The address.
3616	*/
3617	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3618	{
3619	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3620	PCX86PD pGuestPD = 0;
3621	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3622	if (RT_FAILURE(rc))
3623	{
3624	X86PDE ZeroPde = {0};
3625	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3626	}
3627	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3628	#else
3629	return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3630	#endif
3631	}
3632
3633
3634	/**
3635	* Gets the address of a specific page directory entry (32-bit paging).
3636	*
3637	* @returns Pointer the page directory entry in question.
3638	* @param pPGM Pointer to the PGM instance data.
3639	* @param GCPtr The address.
3640	*/
3641	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3642	{
3643	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3644	PX86PD pGuestPD = 0;
3645	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3646	AssertRCReturn(rc, 0);
3647	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3648	#else
3649	return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3650	#endif
3651	}
3652
3653
3654	/**
3655	* Gets the address the guest page directory (32-bit paging).
3656	*
3657	* @returns Pointer the page directory entry in question.
3658	* @param pPGM Pointer to the PGM instance data.
3659	*/
3660	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3661	{
3662	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3663	PX86PD pGuestPD = 0;
3664	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3665	AssertRCReturn(rc, 0);
3666	return pGuestPD;
3667	#else
3668	return pPGM->CTX_SUFF(pGst32BitPd);
3669	#endif
3670	}
3671
3672
3673	/**
3674	* Gets the guest page directory pointer table.
3675	*
3676	* @returns Pointer to the page directory in question.
3677	* @returns NULL if the page directory is not present or on an invalid page.
3678	* @param pPGM Pointer to the PGM instance data.
3679	*/
3680	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3681	{
3682	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3683	PX86PDPT pGuestPDPT = 0;
3684	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3685	AssertRCReturn(rc, 0);
3686	return pGuestPDPT;
3687	#else
3688	return pPGM->CTX_SUFF(pGstPaePdpt);
3689	#endif
3690	}
3691
3692
3693	/**
3694	* Gets the guest page directory pointer table entry for the specified address.
3695	*
3696	* @returns Pointer to the page directory in question.
3697	* @returns NULL if the page directory is not present or on an invalid page.
3698	* @param pPGM Pointer to the PGM instance data.
3699	* @param GCPtr The address.
3700	*/
3701	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3702	{
3703	AssertGCPtr32(GCPtr);
3704
3705	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3706	PX86PDPT pGuestPDPT = 0;
3707	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3708	AssertRCReturn(rc, 0);
3709	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3710	#else
3711	return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3712	#endif
3713	}
3714
3715
3716	/**
3717	* Gets the page directory for the specified address.
3718	*
3719	* @returns Pointer to the page directory in question.
3720	* @returns NULL if the page directory is not present or on an invalid page.
3721	* @param pPGM Pointer to the PGM instance data.
3722	* @param GCPtr The address.
3723	*/
3724	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3725	{
3726	AssertGCPtr32(GCPtr);
3727
3728	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3729	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3730	AssertReturn(pGuestPDPT, 0);
3731	#else
3732	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3733	#endif
3734	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3735	if (pGuestPDPT->a[iPdPt].n.u1Present)
3736	{
3737	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3738	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3739	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3740	#endif
3741
3742	/* cache is out-of-sync. */
3743	PX86PDPAE pPD;
3744	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3745	if (RT_SUCCESS(rc))
3746	return pPD;
3747	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3748	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3749	}
3750	return NULL;
3751	}
3752
3753
3754	/**
3755	* Gets the page directory entry for the specified address.
3756	*
3757	* @returns Pointer to the page directory entry in question.
3758	* @returns NULL if the page directory is not present or on an invalid page.
3759	* @param pPGM Pointer to the PGM instance data.
3760	* @param GCPtr The address.
3761	*/
3762	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3763	{
3764	AssertGCPtr32(GCPtr);
3765
3766	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3767	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3768	AssertReturn(pGuestPDPT, 0);
3769	#else
3770	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3771	#endif
3772	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3773	if (pGuestPDPT->a[iPdPt].n.u1Present)
3774	{
3775	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3776	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3777	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3778	return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3779	#endif
3780
3781	/* The cache is out-of-sync. */
3782	PX86PDPAE pPD;
3783	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3784	if (RT_SUCCESS(rc))
3785	return &pPD->a[iPD];
3786	AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3787	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3788	}
3789	return NULL;
3790	}
3791
3792
3793	/**
3794	* Gets the page directory entry for the specified address.
3795	*
3796	* @returns The page directory entry in question.
3797	* @returns A non-present entry if the page directory is not present or on an invalid page.
3798	* @param pPGM Pointer to the PGM instance data.
3799	* @param GCPtr The address.
3800	*/
3801	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3802	{
3803	AssertGCPtr32(GCPtr);
3804
3805	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3806	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3807	if (RT_LIKELY(pGuestPDPT))
3808	#else
3809	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3810	#endif
3811	{
3812	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3813	if (pGuestPDPT->a[iPdPt].n.u1Present)
3814	{
3815	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3816	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3817	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3818	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3819	#endif
3820
3821	/* cache is out-of-sync. */
3822	PX86PDPAE pPD;
3823	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3824	if (RT_SUCCESS(rc))
3825	return pPD->a[iPD];
3826	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3827	}
3828	}
3829	X86PDEPAE ZeroPde = {0};
3830	return ZeroPde;
3831	}
3832
3833
3834	/**
3835	* Gets the page directory pointer table entry for the specified address
3836	* and returns the index into the page directory
3837	*
3838	* @returns Pointer to the page directory in question.
3839	* @returns NULL if the page directory is not present or on an invalid page.
3840	* @param pPGM Pointer to the PGM instance data.
3841	* @param GCPtr The address.
3842	* @param piPD Receives the index into the returned page directory
3843	* @param pPdpe Receives the page directory pointer entry. Optional.
3844	*/
3845	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3846	{
3847	AssertGCPtr32(GCPtr);
3848
3849	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3850	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3851	AssertReturn(pGuestPDPT, 0);
3852	#else
3853	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3854	#endif
3855	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3856	if (pPdpe)
3857	*pPdpe = pGuestPDPT->a[iPdPt];
3858	if (pGuestPDPT->a[iPdPt].n.u1Present)
3859	{
3860	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3861	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3862	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3863	{
3864	*piPD = iPD;
3865	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3866	}
3867	#endif
3868
3869	/* cache is out-of-sync. */
3870	PX86PDPAE pPD;
3871	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3872	if (RT_SUCCESS(rc))
3873	{
3874	*piPD = iPD;
3875	return pPD;
3876	}
3877	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3878	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3879	}
3880	return NULL;
3881	}
3882
3883	#ifndef IN_RC
3884
3885	/**
3886	* Gets the page map level-4 pointer for the guest.
3887	*
3888	* @returns Pointer to the PML4 page.
3889	* @param pPGM Pointer to the PGM instance data.
3890	*/
3891	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3892	{
3893	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3894	PX86PML4 pGuestPml4;
3895	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3896	AssertRCReturn(rc, NULL);
3897	return pGuestPml4;
3898	#else
3899	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3900	return pPGM->CTX_SUFF(pGstAmd64Pml4);
3901	#endif
3902	}
3903
3904
3905	/**
3906	* Gets the pointer to a page map level-4 entry.
3907	*
3908	* @returns Pointer to the PML4 entry.
3909	* @param pPGM Pointer to the PGM instance data.
3910	* @param iPml4 The index.
3911	*/
3912	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3913	{
3914	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3915	PX86PML4 pGuestPml4;
3916	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3917	AssertRCReturn(rc, NULL);
3918	return &pGuestPml4->a[iPml4];
3919	#else
3920	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3921	return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3922	#endif
3923	}
3924
3925
3926	/**
3927	* Gets a page map level-4 entry.
3928	*
3929	* @returns The PML4 entry.
3930	* @param pPGM Pointer to the PGM instance data.
3931	* @param iPml4 The index.
3932	*/
3933	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3934	{
3935	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3936	PX86PML4 pGuestPml4;
3937	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3938	if (RT_FAILURE(rc))
3939	{
3940	X86PML4E ZeroPml4e = {0};
3941	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3942	}
3943	return pGuestPml4->a[iPml4];
3944	#else
3945	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3946	return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3947	#endif
3948	}
3949
3950
3951	/**
3952	* Gets the page directory pointer entry for the specified address.
3953	*
3954	* @returns Pointer to the page directory pointer entry in question.
3955	* @returns NULL if the page directory is not present or on an invalid page.
3956	* @param pPGM Pointer to the PGM instance data.
3957	* @param GCPtr The address.
3958	* @param ppPml4e Page Map Level-4 Entry (out)
3959	*/
3960	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3961	{
3962	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3963	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3964	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3965	if (pPml4e->n.u1Present)
3966	{
3967	PX86PDPT pPdpt;
3968	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3969	AssertRCReturn(rc, NULL);
3970
3971	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3972	return &pPdpt->a[iPdPt];
3973	}
3974	return NULL;
3975	}
3976
3977
3978	/**
3979	* Gets the page directory entry for the specified address.
3980	*
3981	* @returns The page directory entry in question.
3982	* @returns A non-present entry if the page directory is not present or on an invalid page.
3983	* @param pPGM Pointer to the PGM instance data.
3984	* @param GCPtr The address.
3985	* @param ppPml4e Page Map Level-4 Entry (out)
3986	* @param pPdpe Page directory pointer table entry (out)
3987	*/
3988	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3989	{
3990	X86PDEPAE ZeroPde = {0};
3991	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3992	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3993	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3994	if (pPml4e->n.u1Present)
3995	{
3996	PCX86PDPT pPdptTemp;
3997	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3998	AssertRCReturn(rc, ZeroPde);
3999
4000	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4001	*pPdpe = pPdptTemp->a[iPdPt];
4002	if (pPdptTemp->a[iPdPt].n.u1Present)
4003	{
4004	PCX86PDPAE pPD;
4005	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4006	AssertRCReturn(rc, ZeroPde);
4007
4008	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4009	return pPD->a[iPD];
4010	}
4011	}
4012
4013	return ZeroPde;
4014	}
4015
4016
4017	/**
4018	* Gets the page directory entry for the specified address.
4019	*
4020	* @returns The page directory entry in question.
4021	* @returns A non-present entry if the page directory is not present or on an invalid page.
4022	* @param pPGM Pointer to the PGM instance data.
4023	* @param GCPtr The address.
4024	*/
4025	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4026	{
4027	X86PDEPAE ZeroPde = {0};
4028	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4029	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4030	if (pGuestPml4->a[iPml4].n.u1Present)
4031	{
4032	PCX86PDPT pPdptTemp;
4033	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4034	AssertRCReturn(rc, ZeroPde);
4035
4036	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4037	if (pPdptTemp->a[iPdPt].n.u1Present)
4038	{
4039	PCX86PDPAE pPD;
4040	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4041	AssertRCReturn(rc, ZeroPde);
4042
4043	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4044	return pPD->a[iPD];
4045	}
4046	}
4047	return ZeroPde;
4048	}
4049
4050
4051	/**
4052	* Gets the page directory entry for the specified address.
4053	*
4054	* @returns Pointer to the page directory entry in question.
4055	* @returns NULL if the page directory is not present or on an invalid page.
4056	* @param pPGM Pointer to the PGM instance data.
4057	* @param GCPtr The address.
4058	*/
4059	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4060	{
4061	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4062	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4063	if (pGuestPml4->a[iPml4].n.u1Present)
4064	{
4065	PCX86PDPT pPdptTemp;
4066	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4067	AssertRCReturn(rc, NULL);
4068
4069	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4070	if (pPdptTemp->a[iPdPt].n.u1Present)
4071	{
4072	PX86PDPAE pPD;
4073	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4074	AssertRCReturn(rc, NULL);
4075
4076	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4077	return &pPD->a[iPD];
4078	}
4079	}
4080	return NULL;
4081	}
4082
4083
4084	/**
4085	* Gets the GUEST page directory pointer for the specified address.
4086	*
4087	* @returns The page directory in question.
4088	* @returns NULL if the page directory is not present or on an invalid page.
4089	* @param pPGM Pointer to the PGM instance data.
4090	* @param GCPtr The address.
4091	* @param ppPml4e Page Map Level-4 Entry (out)
4092	* @param pPdpe Page directory pointer table entry (out)
4093	* @param piPD Receives the index into the returned page directory
4094	*/
4095	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4096	{
4097	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4098	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4099	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4100	if (pPml4e->n.u1Present)
4101	{
4102	PCX86PDPT pPdptTemp;
4103	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4104	AssertRCReturn(rc, NULL);
4105
4106	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4107	*pPdpe = pPdptTemp->a[iPdPt];
4108	if (pPdptTemp->a[iPdPt].n.u1Present)
4109	{
4110	PX86PDPAE pPD;
4111	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4112	AssertRCReturn(rc, NULL);
4113
4114	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4115	return pPD;
4116	}
4117	}
4118	return 0;
4119	}
4120
4121	#endif /* !IN_RC */
4122
4123
4124	/**
4125	* Gets the shadow page directory, 32-bit.
4126	*
4127	* @returns Pointer to the shadow 32-bit PD.
4128	* @param pPGM Pointer to the PGM instance data.
4129	*/
4130	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4131	{
4132	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4133	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4134	#else
4135	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4136	PX86PD pShwPd;
4137	Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4138	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4139	AssertRCReturn(rc, NULL);
4140	return pShwPd;
4141	# else
4142	return pPGM->CTX_SUFF(pShw32BitPd);
4143	# endif
4144	#endif
4145	}
4146
4147
4148	/**
4149	* Gets the shadow page directory entry for the specified address, 32-bit.
4150	*
4151	* @returns Shadow 32-bit PDE.
4152	* @param pPGM Pointer to the PGM instance data.
4153	* @param GCPtr The address.
4154	*/
4155	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4156	{
4157	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4158
4159	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4160	if (!pShwPde)
4161	{
4162	X86PDE ZeroPde = {0};
4163	return ZeroPde;
4164	}
4165	return pShwPde->a[iPd];
4166	}
4167
4168
4169	/**
4170	* Gets the pointer to the shadow page directory entry for the specified
4171	* address, 32-bit.
4172	*
4173	* @returns Pointer to the shadow 32-bit PDE.
4174	* @param pPGM Pointer to the PGM instance data.
4175	* @param GCPtr The address.
4176	*/
4177	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4178	{
4179	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4180
4181	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4182	AssertReturn(pPde, NULL);
4183	return &pPde->a[iPd];
4184	}
4185
4186
4187	/**
4188	* Gets the shadow page pointer table, PAE.
4189	*
4190	* @returns Pointer to the shadow PAE PDPT.
4191	* @param pPGM Pointer to the PGM instance data.
4192	*/
4193	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4194	{
4195	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4196	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4197	#else
4198	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4199	PX86PDPT pShwPdpt;
4200	Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4201	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4202	AssertRCReturn(rc, 0);
4203	return pShwPdpt;
4204	# else
4205	return pPGM->CTX_SUFF(pShwPaePdpt);
4206	# endif
4207	#endif
4208	}
4209
4210
4211	/**
4212	* Gets the shadow page directory for the specified address, PAE.
4213	*
4214	* @returns Pointer to the shadow PD.
4215	* @param pPGM Pointer to the PGM instance data.
4216	* @param GCPtr The address.
4217	*/
4218	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4219	{
4220	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4221	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4222	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4223
4224	/* Fetch the pgm pool shadow descriptor. */
4225	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4226	AssertReturn(pShwPde, NULL);
4227
4228	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4229	#else
4230	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4231	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4232	PX86PDPAE pPD;
4233	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4234	AssertRCReturn(rc, 0);
4235	return pPD;
4236	# else
4237	PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4238	Assert(pPD);
4239	return pPD;
4240	# endif
4241	#endif
4242	}
4243
4244
4245	/**
4246	* Gets the shadow page directory entry, PAE.
4247	*
4248	* @returns PDE.
4249	* @param pPGM Pointer to the PGM instance data.
4250	* @param GCPtr The address.
4251	*/
4252	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4253	{
4254	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4255
4256	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4257	if (!pShwPde)
4258	{
4259	X86PDEPAE ZeroPde = {0};
4260	return ZeroPde;
4261	}
4262	return pShwPde->a[iPd];
4263	}
4264
4265
4266	/**
4267	* Gets the pointer to the shadow page directory entry for an address, PAE.
4268	*
4269	* @returns Pointer to the PDE.
4270	* @param pPGM Pointer to the PGM instance data.
4271	* @param GCPtr The address.
4272	*/
4273	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4274	{
4275	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4276
4277	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4278	AssertReturn(pPde, NULL);
4279	return &pPde->a[iPd];
4280	}
4281
4282	#ifndef IN_RC
4283
4284	/**
4285	* Gets the shadow page map level-4 pointer.
4286	*
4287	* @returns Pointer to the shadow PML4.
4288	* @param pPGM Pointer to the PGM instance data.
4289	*/
4290	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4291	{
4292	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4293	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4294	#else
4295	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4296	PX86PML4 pShwPml4;
4297	Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
4298	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePml4, &pShwPml4);
4299	AssertRCReturn(rc, 0);
4300	return pShwPml4;
4301	# else
4302	Assert(pPGM->CTX_SUFF(pShwRoot));
4303	return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4304	# endif
4305	#endif
4306	}
4307
4308
4309	/**
4310	* Gets the shadow page map level-4 entry for the specified address.
4311	*
4312	* @returns The entry.
4313	* @param pPGM Pointer to the PGM instance data.
4314	* @param GCPtr The address.
4315	*/
4316	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4317	{
4318	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4319	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4320
4321	if (!pShwPml4)
4322	{
4323	X86PML4E ZeroPml4e = {0};
4324	return ZeroPml4e;
4325	}
4326	return pShwPml4->a[iPml4];
4327	}
4328
4329
4330	/**
4331	* Gets the pointer to the specified shadow page map level-4 entry.
4332	*
4333	* @returns The entry.
4334	* @param pPGM Pointer to the PGM instance data.
4335	* @param iPml4 The PML4 index.
4336	*/
4337	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4338	{
4339	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4340	if (!pShwPml4)
4341	return NULL;
4342	return &pShwPml4->a[iPml4];
4343	}
4344
4345
4346	/**
4347	* Gets the GUEST page directory pointer for the specified address.
4348	*
4349	* @returns The page directory in question.
4350	* @returns NULL if the page directory is not present or on an invalid page.
4351	* @param pPGM Pointer to the PGM instance data.
4352	* @param GCPtr The address.
4353	* @param piPD Receives the index into the returned page directory
4354	*/
4355	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4356	{
4357	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4358	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4359	if (pGuestPml4->a[iPml4].n.u1Present)
4360	{
4361	PCX86PDPT pPdptTemp;
4362	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4363	AssertRCReturn(rc, NULL);
4364
4365	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4366	if (pPdptTemp->a[iPdPt].n.u1Present)
4367	{
4368	PX86PDPAE pPD;
4369	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4370	AssertRCReturn(rc, NULL);
4371
4372	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4373	return pPD;
4374	}
4375	}
4376	return NULL;
4377	}
4378
4379	#endif /* !IN_RC */
4380
4381	/**
4382	* Checks if any of the specified page flags are set for the given page.
4383	*
4384	* @returns true if any of the flags are set.
4385	* @returns false if all the flags are clear.
4386	* @param pPGM PGM handle.
4387	* @param GCPhys The GC physical address.
4388	* @param fFlags The flags to check for.
4389	*/
4390	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4391	{
4392	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4393	return pPage
4394	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4395	}
4396
4397
4398	/**
4399	* Gets the page state for a physical handler.
4400	*
4401	* @returns The physical handler page state.
4402	* @param pCur The physical handler in question.
4403	*/
4404	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4405	{
4406	switch (pCur->enmType)
4407	{
4408	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4409	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4410
4411	case PGMPHYSHANDLERTYPE_MMIO:
4412	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4413	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4414
4415	default:
4416	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4417	}
4418	}
4419
4420
4421	/**
4422	* Gets the page state for a virtual handler.
4423	*
4424	* @returns The virtual handler page state.
4425	* @param pCur The virtual handler in question.
4426	* @remarks This should never be used on a hypervisor access handler.
4427	*/
4428	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4429	{
4430	switch (pCur->enmType)
4431	{
4432	case PGMVIRTHANDLERTYPE_WRITE:
4433	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4434	case PGMVIRTHANDLERTYPE_ALL:
4435	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4436	default:
4437	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4438	}
4439	}
4440
4441
4442	/**
4443	* Clears one physical page of a virtual handler
4444	*
4445	* @param pPGM Pointer to the PGM instance.
4446	* @param pCur Virtual handler structure
4447	* @param iPage Physical page index
4448	*
4449	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4450	* need to care about other handlers in the same page.
4451	*/
4452	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4453	{
4454	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4455
4456	/*
4457	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4458	*/
4459	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4460	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4461	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4462	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4463	#endif
4464	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4465	{
4466	/* We're the head of the alias chain. */
4467	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4468	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4469	AssertReleaseMsg(pRemove != NULL,
4470	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4471	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4472	AssertReleaseMsg(pRemove == pPhys2Virt,
4473	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4474	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4475	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4476	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4477	#endif
4478	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4479	{
4480	/* Insert the next list in the alias chain into the tree. */
4481	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4482	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4483	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4484	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4485	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4486	#endif
4487	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4488	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4489	AssertRelease(fRc);
4490	}
4491	}
4492	else
4493	{
4494	/* Locate the previous node in the alias chain. */
4495	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4496	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4497	AssertReleaseMsg(pPrev != pPhys2Virt,
4498	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4499	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4500	#endif
4501	for (;;)
4502	{
4503	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4504	if (pNext == pPhys2Virt)
4505	{
4506	/* unlink. */
4507	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4508	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4509	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4510	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4511	else
4512	{
4513	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4514	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4515	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4516	}
4517	break;
4518	}
4519
4520	/* next */
4521	if (pNext == pPrev)
4522	{
4523	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4524	AssertReleaseMsg(pNext != pPrev,
4525	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4526	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4527	#endif
4528	break;
4529	}
4530	pPrev = pNext;
4531	}
4532	}
4533	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4534	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4535	pPhys2Virt->offNextAlias = 0;
4536	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4537
4538	/*
4539	* Clear the ram flags for this page.
4540	*/
4541	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4542	AssertReturnVoid(pPage);
4543	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4544	}
4545
4546
4547	/**
4548	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4549	*
4550	* @returns Pointer to the shadow page structure.
4551	* @param pPool The pool.
4552	* @param HCPhys The HC physical address of the shadow page.
4553	*/
4554	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4555	{
4556	/*
4557	* Look up the page.
4558	*/
4559	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4560	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4561	return pPage;
4562	}
4563
4564
4565	/**
4566	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4567	*
4568	* @returns Pointer to the shadow page structure.
4569	* @param pPool The pool.
4570	* @param idx The pool page index.
4571	*/
4572	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4573	{
4574	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4575	return &pPool->aPages[idx];
4576	}
4577
4578
4579	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4580	/**
4581	* Clear references to guest physical memory.
4582	*
4583	* @param pPool The pool.
4584	* @param pPoolPage The pool page.
4585	* @param pPhysPage The physical guest page tracking structure.
4586	*/
4587	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4588	{
4589	/*
4590	* Just deal with the simple case here.
4591	*/
4592	# ifdef LOG_ENABLED
4593	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4594	# endif
4595	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4596	if (cRefs == 1)
4597	{
4598	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4599	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4600	}
4601	else
4602	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4603	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4604	}
4605	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4606
4607
4608	#ifdef PGMPOOL_WITH_CACHE
4609	/**
4610	* Moves the page to the head of the age list.
4611	*
4612	* This is done when the cached page is used in one way or another.
4613	*
4614	* @param pPool The pool.
4615	* @param pPage The cached page.
4616	* @todo inline in PGMInternal.h!
4617	*/
4618	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4619	{
4620	/*
4621	* Move to the head of the age list.
4622	*/
4623	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4624	{
4625	/* unlink */
4626	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4627	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4628	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4629	else
4630	pPool->iAgeTail = pPage->iAgePrev;
4631
4632	/* insert at head */
4633	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4634	pPage->iAgeNext = pPool->iAgeHead;
4635	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4636	pPool->iAgeHead = pPage->idx;
4637	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4638	}
4639	}
4640	#endif /* PGMPOOL_WITH_CACHE */
4641
4642
4643	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4644	/**
4645	* Maps the page into current context (RC and maybe R0).
4646	*
4647	* @returns pointer to the mapping.
4648	* @param pVM Pointer to the PGM instance data.
4649	* @param pPage The page.
4650	*/
4651	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
4652	{
4653	if (pPage->idx >= PGMPOOL_IDX_FIRST)
4654	{
4655	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
4656	void *pv;
4657	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4658	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
4659	# else
4660	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
4661	# endif
4662	return pv;
4663	}
4664	return pgmPoolMapPageFallback(pPGM, pPage);
4665	}
4666	#endif
4667
4668
4669	/**
4670	* Tells if mappings are to be put into the shadow page table or not
4671	*
4672	* @returns boolean result
4673	* @param pVM VM handle.
4674	*/
4675
4676	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4677	{
4678	#ifdef IN_RING0
4679	/* There are no mappings in VT-x and AMD-V mode. */
4680	Assert(pPGM->fDisableMappings);
4681	return false;
4682	#else
4683	return !pPGM->fDisableMappings;
4684	#endif
4685	}
4686
4687	/** @} */
4688
4689	#endif
4690

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 16174

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