HWACCMInternal.h@ 23366

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Wait for the target VCPU to finish its world switch.
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1	/* $Id: HWACCMInternal.h 23366 2009-09-28 12:31:50Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36	#include <iprt/avl.h>
37
38	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
39	/* Enable 64 bits guest support. */
40	# define VBOX_ENABLE_64_BITS_GUESTS
41	#endif
42
43	#define VMX_USE_CACHED_VMCS_ACCESSES
44	#define HWACCM_VMX_EMULATE_REALMODE
45	#define HWACCM_VTX_WITH_EPT
46	#define HWACCM_VTX_WITH_VPID
47
48
49	#if 0
50	/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
51	* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
52	* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
53	*
54	* Note: change the assembly files when enabling this! (remove the manual auto load/save)
55	*/
56	#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
57	#endif
58
59	RT_C_DECLS_BEGIN
60
61
62	/** @defgroup grp_hwaccm_int Internal
63	* @ingroup grp_hwaccm
64	* @internal
65	* @{
66	*/
67
68
69	/** Maximum number of exit reason statistics counters. */
70	#define MAX_EXITREASON_STAT 0x100
71	#define MASK_EXITREASON_STAT 0xff
72	#define MASK_INJECT_IRQ_STAT 0xff
73
74	/** @name Changed flags
75	* These flags are used to keep track of which important registers that
76	* have been changed since last they were reset.
77	* @{
78	*/
79	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
80	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
81	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
82	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
83	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
84	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
85	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
86	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
87	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
88	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
89	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
90	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
91
92	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_FPU \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_HOST_CONTEXT)
104
105	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
106	\| HWACCM_CHANGED_GUEST_CR0 \
107	\| HWACCM_CHANGED_GUEST_CR3 \
108	\| HWACCM_CHANGED_GUEST_CR4 \
109	\| HWACCM_CHANGED_GUEST_GDTR \
110	\| HWACCM_CHANGED_GUEST_IDTR \
111	\| HWACCM_CHANGED_GUEST_LDTR \
112	\| HWACCM_CHANGED_GUEST_TR \
113	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
114	\| HWACCM_CHANGED_GUEST_DEBUG \
115	\| HWACCM_CHANGED_GUEST_FPU)
116
117	/** @} */
118
119	/** @name Intercepted traps
120	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
121	* Currently #NM and #PF only
122	*/
123	#ifdef VBOX_STRICT
124	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
125	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
126	#else
127	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
128	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
129	#endif
130	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
131	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
132	/** @} */
133
134
135	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
136	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
137
138	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
139	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
140	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
141	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
142	/** Total guest mapped memory needed. */
143	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
144
145	/* Enable for TPR guest patching. */
146	#define VBOX_HWACCM_WITH_GUEST_PATCHING
147
148	/** HWACCM SSM version
149	*/
150	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
151	#define HWACCM_SSM_VERSION 5
152	#define HWACCM_SSM_VERSION_NO_PATCHING 4
153	#else
154	#define HWACCM_SSM_VERSION 4
155	#define HWACCM_SSM_VERSION_NO_PATCHING 4
156	#endif
157	#define HWACCM_SSM_VERSION_2_0_X 3
158
159	/* Per-cpu information. (host) */
160	typedef struct
161	{
162	RTCPUID idCpu;
163
164	RTR0MEMOBJ pMemObj;
165	/* Current ASID (AMD-V)/VPID (Intel) */
166	uint32_t uCurrentASID;
167	/* TLB flush count */
168	uint32_t cTLBFlushes;
169
170	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
171	bool fFlushTLB;
172
173	/** Configured for VT-x or AMD-V. */
174	bool fConfigured;
175
176	/** In use by our code. (for power suspend) */
177	volatile bool fInUse;
178	} HWACCM_CPUINFO;
179	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181	/* VT-x capability qword. */
182	typedef union
183	{
184	struct
185	{
186	uint32_t disallowed0;
187	uint32_t allowed1;
188	} n;
189	uint64_t u;
190	} VMX_CAPABILITY;
191
192	typedef enum
193	{
194	HWACCMPENDINGIO_INVALID = 0,
195	HWACCMPENDINGIO_PORT_READ,
196	HWACCMPENDINGIO_PORT_WRITE,
197	HWACCMPENDINGIO_STRING_READ,
198	HWACCMPENDINGIO_STRING_WRITE,
199	/** The usual 32-bit paranoia. */
200	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
201	} HWACCMPENDINGIO;
202
203
204	typedef enum
205	{
206	HWACCMTPRINSTR_INVALID,
207	HWACCMTPRINSTR_READ,
208	HWACCMTPRINSTR_READ_SHR4,
209	HWACCMTPRINSTR_WRITE_REG,
210	HWACCMTPRINSTR_WRITE_IMM,
211	HWACCMTPRINSTR_JUMP_REPLACEMENT,
212	/** The usual 32-bit paranoia. */
213	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
214	} HWACCMTPRINSTR;
215
216	typedef struct
217	{
218	/** The key is the address of patched instruction. (32 bits GC ptr) */
219	AVLOU32NODECORE Core;
220	/** Original opcode. */
221	uint8_t aOpcode[16];
222	/** Instruction size. */
223	uint32_t cbOp;
224	/** Replacement opcode. */
225	uint8_t aNewOpcode[16];
226	/** Replacement instruction size. */
227	uint32_t cbNewOp;
228	/** Instruction type. */
229	HWACCMTPRINSTR enmType;
230	/** Source operand. */
231	uint32_t uSrcOperand;
232	/** Destination operand. */
233	uint32_t uDstOperand;
234	/** Number of times the instruction caused a fault. */
235	uint32_t cFaults;
236	/** Patch address of the jump replacement. */
237	RTGCPTR32 pJumpTarget;
238	} HWACCMTPRPATCH;
239	/** Pointer to HWACCMTPRPATCH. */
240	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
241
242	/**
243	* Switcher function, HC to RC.
244	*
245	* @param pVM The VM handle.
246	* @returns Return code indicating the action to take.
247	*/
248	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
249	/** Pointer to switcher function. */
250	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
251
252	/**
253	* HWACCM VM Instance data.
254	* Changes to this must checked against the padding of the cfgm union in VM!
255	*/
256	typedef struct HWACCM
257	{
258	/** Set when we've initialized VMX or SVM. */
259	bool fInitialized;
260
261	/** Set when hardware acceleration is allowed. */
262	bool fAllowed;
263
264	/** Set if nested paging is enabled. */
265	bool fNestedPaging;
266
267	/** Set if nested paging is allowed. */
268	bool fAllowNestedPaging;
269
270	/** Set if we can support 64-bit guests or not. */
271	bool fAllow64BitGuests;
272
273	/** Set if an IO-APIC is configured for this VM. */
274	bool fHasIoApic;
275
276	/** Set when TPR patching is allowed. */
277	bool fTRPPatchingAllowed;
278
279	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
280	* naturally. */
281	bool padding[1];
282
283	/** And mask for copying register contents. */
284	uint64_t u64RegisterMask;
285
286	/** Maximum ASID allowed. */
287	RTUINT uMaxASID;
288
289	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
290	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
291	uint32_t cMaxResumeLoops;
292
293	/** Guest allocated memory for patching purposes. */
294	RTGCPTR pGuestPatchMem;
295	/** Current free pointer inside the patch block. */
296	RTGCPTR pFreeGuestPatchMem;
297	/** Size of the guest patch memory block. */
298	uint32_t cbGuestPatchMem;
299	uint32_t uPadding1;
300
301	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
302	/** 32 to 64 bits switcher entrypoint. */
303	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
304
305	/* AMD-V 64 bits vmrun handler */
306	RTRCPTR pfnSVMGCVMRun64;
307
308	/* VT-x 64 bits vmlaunch handler */
309	RTRCPTR pfnVMXGCStartVM64;
310
311	/* RC handler to setup the 64 bits FPU state. */
312	RTRCPTR pfnSaveGuestFPU64;
313
314	/* RC handler to setup the 64 bits debug state. */
315	RTRCPTR pfnSaveGuestDebug64;
316
317	/* Test handler */
318	RTRCPTR pfnTest64;
319
320	RTRCPTR uAlignment[2];
321	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
322	uint32_t u32Alignment[1]; */
323	#endif
324
325	struct
326	{
327	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
328	bool fSupported;
329
330	/** Set when we've enabled VMX. */
331	bool fEnabled;
332
333	/** Set if VPID is supported. */
334	bool fVPID;
335
336	/** Set if VT-x VPID is allowed. */
337	bool fAllowVPID;
338
339	/** Virtual address of the TSS page used for real mode emulation. */
340	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
341
342	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
343	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
344
345	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
346	RTR0MEMOBJ pMemObjAPIC;
347	/** Physical address of the APIC physical page (serves for filtering accesses). */
348	RTHCPHYS pAPICPhys;
349	/** Virtual address of the APIC physical page (serves for filtering accesses). */
350	R0PTRTYPE(uint8_t *) pAPIC;
351
352	/** R0 memory object for the MSR entry load page (guest MSRs). */
353	RTR0MEMOBJ pMemObjMSREntryLoad;
354	/** Physical address of the MSR entry load page (guest MSRs). */
355	RTHCPHYS pMSREntryLoadPhys;
356	/** Virtual address of the MSR entry load page (guest MSRs). */
357	R0PTRTYPE(uint8_t *) pMSREntryLoad;
358
359	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
360	RTR0MEMOBJ pMemObjScratch;
361	RTHCPHYS pScratchPhys;
362	R0PTRTYPE(uint8_t *) pScratch;
363	#endif
364	/** R0 memory object for the MSR exit store page (guest MSRs). */
365	RTR0MEMOBJ pMemObjMSRExitStore;
366	/** Physical address of the MSR exit store page (guest MSRs). */
367	RTHCPHYS pMSRExitStorePhys;
368	/** Virtual address of the MSR exit store page (guest MSRs). */
369	R0PTRTYPE(uint8_t *) pMSRExitStore;
370
371	/** R0 memory object for the MSR exit load page (host MSRs). */
372	RTR0MEMOBJ pMemObjMSRExitLoad;
373	/** Physical address of the MSR exit load page (host MSRs). */
374	RTHCPHYS pMSRExitLoadPhys;
375	/** Virtual address of the MSR exit load page (host MSRs). */
376	R0PTRTYPE(uint8_t *) pMSRExitLoad;
377
378	/** Ring 0 handlers for VT-x. */
379	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
380
381	/** Host CR4 value (set by ring-0 VMX init) */
382	uint64_t hostCR4;
383
384	/** VMX MSR values */
385	struct
386	{
387	uint64_t feature_ctrl;
388	uint64_t vmx_basic_info;
389	VMX_CAPABILITY vmx_pin_ctls;
390	VMX_CAPABILITY vmx_proc_ctls;
391	VMX_CAPABILITY vmx_proc_ctls2;
392	VMX_CAPABILITY vmx_exit;
393	VMX_CAPABILITY vmx_entry;
394	uint64_t vmx_misc;
395	uint64_t vmx_cr0_fixed0;
396	uint64_t vmx_cr0_fixed1;
397	uint64_t vmx_cr4_fixed0;
398	uint64_t vmx_cr4_fixed1;
399	uint64_t vmx_vmcs_enum;
400	uint64_t vmx_eptcaps;
401	} msr;
402
403	/** Flush types for invept & invvpid; they depend on capabilities. */
404	VMX_FLUSH enmFlushPage;
405	VMX_FLUSH enmFlushContext;
406	} vmx;
407
408	struct
409	{
410	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
411	bool fSupported;
412	/** Set when we've enabled SVM. */
413	bool fEnabled;
414	/** Set if erratum 170 affects the AMD cpu. */
415	bool fAlwaysFlushTLB;
416	/** Set when TPR patching is active. */
417	bool fTPRPatchingActive;
418
419	/** R0 memory object for the IO bitmap (12kb). */
420	RTR0MEMOBJ pMemObjIOBitmap;
421	/** Physical address of the IO bitmap (12kb). */
422	RTHCPHYS pIOBitmapPhys;
423	/** Virtual address of the IO bitmap. */
424	R0PTRTYPE(void *) pIOBitmap;
425
426	/** SVM revision. */
427	uint32_t u32Rev;
428
429	/** SVM feature bits from cpuid 0x8000000a */
430	uint32_t u32Features;
431
432	/**
433	* AVL tree with all patches (active or disabled) sorted by guest instruction address
434	*/
435	AVLOU32TREE PatchTree;
436	uint32_t cPatches;
437	HWACCMTPRPATCH aPatches[64];
438	} svm;
439
440	struct
441	{
442	uint32_t u32AMDFeatureECX;
443	uint32_t u32AMDFeatureEDX;
444	} cpuid;
445
446	/** Saved error from detection */
447	int32_t lLastError;
448
449	/** HWACCMR0Init was run */
450	bool fHWACCMR0Init;
451	bool u8Alignment[7];
452
453	STAMCOUNTER StatTPRPatchSuccess;
454	STAMCOUNTER StatTPRPatchFailure;
455	STAMCOUNTER StatTPRReplaceSuccess;
456	STAMCOUNTER StatTPRReplaceFailure;
457	} HWACCM;
458	/** Pointer to HWACCM VM instance data. */
459	typedef HWACCM *PHWACCM;
460
461	/* Maximum number of cached entries. */
462	#define VMCSCACHE_MAX_ENTRY 128
463
464	/* Structure for storing read and write VMCS actions. */
465	typedef struct VMCSCACHE
466	{
467	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
468	/* Magic marker for searching in crash dumps. */
469	uint8_t aMagic[16];
470	uint64_t uMagic;
471	uint64_t u64TimeEntry;
472	uint64_t u64TimeSwitch;
473	uint64_t cResume;
474	uint64_t interPD;
475	uint64_t pSwitcher;
476	uint32_t uPos;
477	uint32_t idCpu;
478	#endif
479	/* CR2 is saved here for EPT syncing. */
480	uint64_t cr2;
481	struct
482	{
483	uint32_t cValidEntries;
484	uint32_t uAlignment;
485	uint32_t aField[VMCSCACHE_MAX_ENTRY];
486	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
487	} Write;
488	struct
489	{
490	uint32_t cValidEntries;
491	uint32_t uAlignment;
492	uint32_t aField[VMCSCACHE_MAX_ENTRY];
493	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
494	} Read;
495	#ifdef DEBUG
496	struct
497	{
498	RTHCPHYS pPageCpuPhys;
499	RTHCPHYS pVMCSPhys;
500	RTGCPTR pCache;
501	RTGCPTR pCtx;
502	} TestIn;
503	struct
504	{
505	RTHCPHYS pVMCSPhys;
506	RTGCPTR pCache;
507	RTGCPTR pCtx;
508	uint64_t eflags;
509	uint64_t cr8;
510	} TestOut;
511	struct
512	{
513	uint64_t param1;
514	uint64_t param2;
515	uint64_t param3;
516	uint64_t param4;
517	} ScratchPad;
518	#endif
519	} VMCSCACHE;
520	/** Pointer to VMCSCACHE. */
521	typedef VMCSCACHE *PVMCSCACHE;
522
523	/** VMX StartVM function. */
524	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
525	/** Pointer to a VMX StartVM function. */
526	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
527
528	/** SVM VMRun function. */
529	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
530	/** Pointer to a SVM VMRun function. */
531	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
532
533	/**
534	* HWACCM VMCPU Instance data.
535	*/
536	typedef struct HWACCMCPU
537	{
538	/** Old style FPU reporting trap mask override performed (optimization) */
539	bool fFPUOldStyleOverride;
540
541	/** Set if we don't have to flush the TLB on VM entry. */
542	bool fResumeVM;
543
544	/** Set if we need to flush the TLB during the world switch. */
545	bool fForceTLBFlush;
546
547	/** Set when we're using VT-x or AMD-V at that moment. */
548	bool fActive;
549
550	/** Set when the TLB has been checked until we return from the world switch. */
551	volatile uint8_t fCheckedTLBFlush;
552	uint8_t bAlignment[3];
553
554	/** HWACCM_CHANGED_* flags. */
555	RTUINT fContextUseFlags;
556
557	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
558	RTCPUID idLastCpu;
559
560	/** TLB flush count */
561	RTUINT cTLBFlushes;
562
563	/** Current ASID in use by the VM */
564	RTUINT uCurrentASID;
565
566	/** World switch exit counter. */
567	volatile uint32_t cWorldSwitchExit;
568
569	struct
570	{
571	/** Physical address of the VM control structure (VMCS). */
572	RTHCPHYS pVMCSPhys;
573	/** R0 memory object for the VM control structure (VMCS). */
574	RTR0MEMOBJ pMemObjVMCS;
575	/** Virtual address of the VM control structure (VMCS). */
576	R0PTRTYPE(void *) pVMCS;
577
578	/** Ring 0 handlers for VT-x. */
579	PFNHWACCMVMXSTARTVM pfnStartVM;
580
581	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
582	uint64_t proc_ctls;
583
584	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
585	uint64_t proc_ctls2;
586
587	/** Physical address of the virtual APIC page for TPR caching. */
588	RTHCPHYS pVAPICPhys;
589	/** R0 memory object for the virtual APIC page for TPR caching. */
590	RTR0MEMOBJ pMemObjVAPIC;
591	/** Virtual address of the virtual APIC page for TPR caching. */
592	R0PTRTYPE(uint8_t *) pVAPIC;
593
594	/** Current CR0 mask. */
595	uint64_t cr0_mask;
596	/** Current CR4 mask. */
597	uint64_t cr4_mask;
598
599	/** Current EPTP. */
600	RTHCPHYS GCPhysEPTP;
601
602	/** Physical address of the MSR bitmap (1 page). */
603	RTHCPHYS pMSRBitmapPhys;
604	/** R0 memory object for the MSR bitmap (1 page). */
605	RTR0MEMOBJ pMemObjMSRBitmap;
606	/** Virtual address of the MSR bitmap (1 page). */
607	R0PTRTYPE(uint8_t *) pMSRBitmap;
608
609	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
610	/** Physical address of the guest MSR load area (1 page). */
611	RTHCPHYS pGuestMSRPhys;
612	/** R0 memory object for the guest MSR load area (1 page). */
613	RTR0MEMOBJ pMemObjGuestMSR;
614	/** Virtual address of the guest MSR load area (1 page). */
615	R0PTRTYPE(uint8_t *) pGuestMSR;
616
617	/** Physical address of the MSR load area (1 page). */
618	RTHCPHYS pHostMSRPhys;
619	/** R0 memory object for the MSR load area (1 page). */
620	RTR0MEMOBJ pMemObjHostMSR;
621	/** Virtual address of the MSR load area (1 page). */
622	R0PTRTYPE(uint8_t *) pHostMSR;
623	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
624
625	/* Number of automatically loaded/restored MSRs. */
626	uint32_t cCachedMSRs;
627	uint32_t uAlignement;
628
629	/* Last use TSC offset value. (cached) */
630	uint64_t u64TSCOffset;
631
632	/** VMCS cache. */
633	VMCSCACHE VMCSCache;
634
635	/** Real-mode emulation state. */
636	struct
637	{
638	X86EFLAGS eflags;
639	uint32_t fValid;
640	} RealMode;
641
642	struct
643	{
644	uint64_t u64VMCSPhys;
645	uint32_t ulVMCSRevision;
646	uint32_t ulInstrError;
647	uint32_t ulExitReason;
648	RTCPUID idEnteredCpu;
649	RTCPUID idCurrentCpu;
650	uint32_t padding;
651	} lasterror;
652
653	/** The last seen guest paging mode (by VT-x). */
654	PGMMODE enmLastSeenGuestMode;
655	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
656	PGMMODE enmCurrGuestMode;
657	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
658	PGMMODE enmPrevGuestMode;
659	} vmx;
660
661	struct
662	{
663	/** R0 memory object for the host VM control block (VMCB). */
664	RTR0MEMOBJ pMemObjVMCBHost;
665	/** Physical address of the host VM control block (VMCB). */
666	RTHCPHYS pVMCBHostPhys;
667	/** Virtual address of the host VM control block (VMCB). */
668	R0PTRTYPE(void *) pVMCBHost;
669
670	/** R0 memory object for the VM control block (VMCB). */
671	RTR0MEMOBJ pMemObjVMCB;
672	/** Physical address of the VM control block (VMCB). */
673	RTHCPHYS pVMCBPhys;
674	/** Virtual address of the VM control block (VMCB). */
675	R0PTRTYPE(void *) pVMCB;
676
677	/** Ring 0 handlers for VT-x. */
678	PFNHWACCMSVMVMRUN pfnVMRun;
679
680	/** R0 memory object for the MSR bitmap (8kb). */
681	RTR0MEMOBJ pMemObjMSRBitmap;
682	/** Physical address of the MSR bitmap (8kb). */
683	RTHCPHYS pMSRBitmapPhys;
684	/** Virtual address of the MSR bitmap. */
685	R0PTRTYPE(void *) pMSRBitmap;
686	} svm;
687
688	/** Event injection state. */
689	struct
690	{
691	uint32_t fPending;
692	uint32_t errCode;
693	uint64_t intInfo;
694	} Event;
695
696	/** IO Block emulation state. */
697	struct
698	{
699	bool fEnabled;
700	uint8_t u8Align[7];
701
702	/** RIP at the start of the io code we wish to emulate in the recompiler. */
703	RTGCPTR GCPtrFunctionEip;
704
705	uint64_t cr0;
706	} EmulateIoBlock;
707
708	struct
709	{
710	/* Pending IO operation type. */
711	HWACCMPENDINGIO enmType;
712	uint32_t uPadding;
713	RTGCPTR GCPtrRip;
714	RTGCPTR GCPtrRipNext;
715	union
716	{
717	struct
718	{
719	unsigned uPort;
720	unsigned uAndVal;
721	unsigned cbSize;
722	} Port;
723	uint64_t aRaw[2];
724	} s;
725	} PendingIO;
726
727	/** Currenty shadow paging mode. */
728	PGMMODE enmShadowMode;
729
730	/** The CPU ID of the CPU currently owning the VMCS. Set in
731	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
732	RTCPUID idEnteredCpu;
733
734	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
735	struct
736	{
737	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
738	unsigned cPages;
739	} TlbShootdown;
740
741	/** For saving stack space, the disassembler state is allocated here instead of
742	* on the stack.
743	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
744	union
745	{
746	/** The disassembler scratch space. */
747	DISCPUSTATE DisState;
748	/** Padding. */
749	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
750	};
751
752	RTUINT padding2[1];
753
754	STAMPROFILEADV StatEntry;
755	STAMPROFILEADV StatExit1;
756	STAMPROFILEADV StatExit2;
757	#if 1 /* temporary for tracking down darwin issues. */
758	STAMPROFILEADV StatExit2Sub1;
759	STAMPROFILEADV StatExit2Sub2;
760	STAMPROFILEADV StatExit2Sub3;
761	#endif
762	STAMPROFILEADV StatInGC;
763
764	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
765	STAMPROFILEADV StatWorldSwitch3264;
766	#endif
767	STAMPROFILEADV StatSpinPoke;
768	STAMPROFILEADV StatSpinPokeFailed;
769
770	STAMCOUNTER StatIntInject;
771
772	STAMCOUNTER StatExitShadowNM;
773	STAMCOUNTER StatExitGuestNM;
774	STAMCOUNTER StatExitShadowPF;
775	STAMCOUNTER StatExitGuestPF;
776	STAMCOUNTER StatExitGuestUD;
777	STAMCOUNTER StatExitGuestSS;
778	STAMCOUNTER StatExitGuestNP;
779	STAMCOUNTER StatExitGuestGP;
780	STAMCOUNTER StatExitGuestDE;
781	STAMCOUNTER StatExitGuestDB;
782	STAMCOUNTER StatExitGuestMF;
783	STAMCOUNTER StatExitInvpg;
784	STAMCOUNTER StatExitInvd;
785	STAMCOUNTER StatExitCpuid;
786	STAMCOUNTER StatExitRdtsc;
787	STAMCOUNTER StatExitRdpmc;
788	STAMCOUNTER StatExitCli;
789	STAMCOUNTER StatExitSti;
790	STAMCOUNTER StatExitPushf;
791	STAMCOUNTER StatExitPopf;
792	STAMCOUNTER StatExitIret;
793	STAMCOUNTER StatExitInt;
794	STAMCOUNTER StatExitCRxWrite[16];
795	STAMCOUNTER StatExitCRxRead[16];
796	STAMCOUNTER StatExitDRxWrite;
797	STAMCOUNTER StatExitDRxRead;
798	STAMCOUNTER StatExitRdmsr;
799	STAMCOUNTER StatExitWrmsr;
800	STAMCOUNTER StatExitCLTS;
801	STAMCOUNTER StatExitHlt;
802	STAMCOUNTER StatExitMwait;
803	STAMCOUNTER StatExitLMSW;
804	STAMCOUNTER StatExitIOWrite;
805	STAMCOUNTER StatExitIORead;
806	STAMCOUNTER StatExitIOStringWrite;
807	STAMCOUNTER StatExitIOStringRead;
808	STAMCOUNTER StatExitIrqWindow;
809	STAMCOUNTER StatExitMaxResume;
810	STAMCOUNTER StatExitPreemptPending;
811	STAMCOUNTER StatIntReinject;
812	STAMCOUNTER StatPendingHostIrq;
813
814	STAMCOUNTER StatFlushPageManual;
815	STAMCOUNTER StatFlushPhysPageManual;
816	STAMCOUNTER StatFlushTLBManual;
817	STAMCOUNTER StatFlushPageInvlpg;
818	STAMCOUNTER StatFlushTLBWorldSwitch;
819	STAMCOUNTER StatNoFlushTLBWorldSwitch;
820	STAMCOUNTER StatFlushTLBCRxChange;
821	STAMCOUNTER StatFlushASID;
822	STAMCOUNTER StatFlushTLBInvlpga;
823	STAMCOUNTER StatTlbShootdown;
824	STAMCOUNTER StatTlbShootdownFlush;
825
826	STAMCOUNTER StatSwitchGuestIrq;
827	STAMCOUNTER StatSwitchToR3;
828
829	STAMCOUNTER StatTSCOffset;
830	STAMCOUNTER StatTSCIntercept;
831	STAMCOUNTER StatTSCInterceptOverFlow;
832
833	STAMCOUNTER StatExitReasonNPF;
834	STAMCOUNTER StatDRxArmed;
835	STAMCOUNTER StatDRxContextSwitch;
836	STAMCOUNTER StatDRxIOCheck;
837
838
839	#ifdef VBOX_WITH_STATISTICS
840	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
841	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
842	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
843	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
844	#endif
845	} HWACCMCPU;
846	/** Pointer to HWACCM VM instance data. */
847	typedef HWACCMCPU *PHWACCMCPU;
848
849
850	#ifdef IN_RING0
851
852	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
853	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
854
855
856	#ifdef VBOX_STRICT
857	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
858	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
859	#else
860	# define HWACCMDumpRegs(a, b ,c) do { } while (0)
861	# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
862	#endif
863
864	/* Dummy callback handlers. */
865	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
866	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
867	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
868	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
869	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
870	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
871	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
872	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
873	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
874	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
875
876	# ifdef VBOX_WITH_KERNEL_USING_XMM
877	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
878	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
879	# endif
880
881	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
882	/**
883	* Gets 64-bit GDTR and IDTR on darwin.
884	* @param pGdtr Where to store the 64-bit GDTR.
885	* @param pIdtr Where to store the 64-bit IDTR.
886	*/
887	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
888
889	/**
890	* Gets 64-bit CR3 on darwin.
891	* @returns CR3
892	*/
893	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
894	# endif
895
896	#endif /* IN_RING0 */
897
898	/** @} */
899
900	RT_C_DECLS_END
901
902	#endif
903

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 23366

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