HWACCMInternal.h@ 22173

最後變更在這個檔案從22173是 22079,由 vboxsync 提交於 16 年前
Back to manual msr save and restore.
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1	/* $Id: HWACCMInternal.h 22079 2009-08-07 16:26:25Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36	#include <iprt/avl.h>
37
38	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
39	/* Enable 64 bits guest support. */
40	# define VBOX_ENABLE_64_BITS_GUESTS
41	#endif
42
43	#define VMX_USE_CACHED_VMCS_ACCESSES
44	#define HWACCM_VMX_EMULATE_REALMODE
45	#define HWACCM_VTX_WITH_EPT
46	#define HWACCM_VTX_WITH_VPID
47
48
49	#if 0
50	/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
51	* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
52	* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
53	*
54	* Note: change the assembly files when enabling this! (remove the manual auto load/save)
55	*/
56	#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
57	#endif
58
59	RT_C_DECLS_BEGIN
60
61
62	/** @defgroup grp_hwaccm_int Internal
63	* @ingroup grp_hwaccm
64	* @internal
65	* @{
66	*/
67
68
69	/** Maximum number of exit reason statistics counters. */
70	#define MAX_EXITREASON_STAT 0x100
71	#define MASK_EXITREASON_STAT 0xff
72	#define MASK_INJECT_IRQ_STAT 0xff
73
74	/** @name Changed flags
75	* These flags are used to keep track of which important registers that
76	* have been changed since last they were reset.
77	* @{
78	*/
79	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
80	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
81	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
82	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
83	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
84	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
85	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
86	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
87	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
88	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
89	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
90	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
91
92	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_FPU \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_HOST_CONTEXT)
104
105	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
106	\| HWACCM_CHANGED_GUEST_CR0 \
107	\| HWACCM_CHANGED_GUEST_CR3 \
108	\| HWACCM_CHANGED_GUEST_CR4 \
109	\| HWACCM_CHANGED_GUEST_GDTR \
110	\| HWACCM_CHANGED_GUEST_IDTR \
111	\| HWACCM_CHANGED_GUEST_LDTR \
112	\| HWACCM_CHANGED_GUEST_TR \
113	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
114	\| HWACCM_CHANGED_GUEST_DEBUG \
115	\| HWACCM_CHANGED_GUEST_FPU)
116
117	/** @} */
118
119	/** @name Intercepted traps
120	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
121	* Currently #NM and #PF only
122	*/
123	#ifdef VBOX_STRICT
124	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
125	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
126	#else
127	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
128	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
129	#endif
130	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
131	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
132	/** @} */
133
134
135	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
136	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
137
138	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
139	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
140	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
141	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
142	/** Total guest mapped memory needed. */
143	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
144
145	/* Enable for TPR guest patching. */
146	//#define VBOX_HWACCM_WITH_GUEST_PATCHING
147
148	/** HWACCM SSM version
149	*/
150	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
151	#define HWACCM_SSM_VERSION 5
152	#define HWACCM_SSM_VERSION_NO_PATCHING 4
153	#else
154	#define HWACCM_SSM_VERSION 4
155	#define HWACCM_SSM_VERSION_NO_PATCHING 4
156	#endif
157	#define HWACCM_SSM_VERSION_2_0_X 3
158
159	/* Per-cpu information. (host) */
160	typedef struct
161	{
162	RTCPUID idCpu;
163
164	RTR0MEMOBJ pMemObj;
165	/* Current ASID (AMD-V)/VPID (Intel) */
166	uint32_t uCurrentASID;
167	/* TLB flush count */
168	uint32_t cTLBFlushes;
169
170	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
171	bool fFlushTLB;
172
173	/** Configured for VT-x or AMD-V. */
174	bool fConfigured;
175
176	/** In use by our code. (for power suspend) */
177	volatile bool fInUse;
178	} HWACCM_CPUINFO;
179	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181	/* VT-x capability qword. */
182	typedef union
183	{
184	struct
185	{
186	uint32_t disallowed0;
187	uint32_t allowed1;
188	} n;
189	uint64_t u;
190	} VMX_CAPABILITY;
191
192	typedef enum
193	{
194	HWACCMPENDINGIO_INVALID = 0,
195	HWACCMPENDINGIO_PORT_READ,
196	HWACCMPENDINGIO_PORT_WRITE,
197	HWACCMPENDINGIO_STRING_READ,
198	HWACCMPENDINGIO_STRING_WRITE,
199	/** The usual 32-bit paranoia. */
200	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
201	} HWACCMPENDINGIO;
202
203
204	typedef enum
205	{
206	HWACCMTPRINSTR_INVALID,
207	HWACCMTPRINSTR_READ,
208	HWACCMTPRINSTR_READ_SHR4,
209	HWACCMTPRINSTR_WRITE_REG,
210	HWACCMTPRINSTR_WRITE_IMM,
211	HWACCMTPRINSTR_JUMP_REPLACEMENT,
212	/** The usual 32-bit paranoia. */
213	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
214	} HWACCMTPRINSTR;
215
216	typedef struct
217	{
218	/** The key is the address of patched instruction. (32 bits GC ptr) */
219	AVLOU32NODECORE Core;
220	/** Original opcode. */
221	uint8_t aOpcode[16];
222	/** Instruction size. */
223	uint32_t cbOp;
224	/** Replacement opcode. */
225	uint8_t aNewOpcode[16];
226	/** Replacement instruction size. */
227	uint32_t cbNewOp;
228	/** Instruction type. */
229	HWACCMTPRINSTR enmType;
230	/** Source operand. */
231	uint32_t uSrcOperand;
232	/** Destination operand. */
233	uint32_t uDstOperand;
234	/** Number of times the instruction caused a fault. */
235	uint32_t cFaults;
236	/** Patch address of the jump replacement. */
237	RTGCPTR32 pJumpTarget;
238	} HWACCMTPRPATCH;
239	/** Pointer to HWACCMTPRPATCH. */
240	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
241
242	/**
243	* Switcher function, HC to RC.
244	*
245	* @param pVM The VM handle.
246	* @returns Return code indicating the action to take.
247	*/
248	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
249	/** Pointer to switcher function. */
250	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
251
252	/**
253	* HWACCM VM Instance data.
254	* Changes to this must checked against the padding of the cfgm union in VM!
255	*/
256	typedef struct HWACCM
257	{
258	/** Set when we've initialized VMX or SVM. */
259	bool fInitialized;
260
261	/** Set when hardware acceleration is allowed. */
262	bool fAllowed;
263
264	/** Set if nested paging is enabled. */
265	bool fNestedPaging;
266
267	/** Set if nested paging is allowed. */
268	bool fAllowNestedPaging;
269
270	/** Set if we can support 64-bit guests or not. */
271	bool fAllow64BitGuests;
272
273	/** Set if an IO-APIC is configured for this VM. */
274	bool fHasIoApic;
275
276	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
277	* naturally. */
278	bool padding[2];
279
280	/** And mask for copying register contents. */
281	uint64_t u64RegisterMask;
282
283	/** Maximum ASID allowed. */
284	RTUINT uMaxASID;
285
286	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
287	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
288	uint32_t cMaxResumeLoops;
289
290	/** Guest allocated memory for patching purposes. */
291	RTGCPTR pGuestPatchMem;
292	/** Current free pointer inside the patch block. */
293	RTGCPTR pFreeGuestPatchMem;
294	/** Size of the guest patch memory block. */
295	uint32_t cbGuestPatchMem;
296	uint32_t uPadding1;
297
298	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
299	/** 32 to 64 bits switcher entrypoint. */
300	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
301
302	/* AMD-V 64 bits vmrun handler */
303	RTRCPTR pfnSVMGCVMRun64;
304
305	/* VT-x 64 bits vmlaunch handler */
306	RTRCPTR pfnVMXGCStartVM64;
307
308	/* RC handler to setup the 64 bits FPU state. */
309	RTRCPTR pfnSaveGuestFPU64;
310
311	/* RC handler to setup the 64 bits debug state. */
312	RTRCPTR pfnSaveGuestDebug64;
313
314	/* Test handler */
315	RTRCPTR pfnTest64;
316
317	RTRCPTR uAlignment[2];
318	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
319	uint32_t u32Alignment[1]; */
320	#endif
321
322	struct
323	{
324	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
325	bool fSupported;
326
327	/** Set when we've enabled VMX. */
328	bool fEnabled;
329
330	/** Set if VPID is supported. */
331	bool fVPID;
332
333	/** Set if VT-x VPID is allowed. */
334	bool fAllowVPID;
335
336	/** Virtual address of the TSS page used for real mode emulation. */
337	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
338
339	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
340	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
341
342	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
343	RTR0MEMOBJ pMemObjAPIC;
344	/** Physical address of the APIC physical page (serves for filtering accesses). */
345	RTHCPHYS pAPICPhys;
346	/** Virtual address of the APIC physical page (serves for filtering accesses). */
347	R0PTRTYPE(uint8_t *) pAPIC;
348
349	/** R0 memory object for the MSR entry load page (guest MSRs). */
350	RTR0MEMOBJ pMemObjMSREntryLoad;
351	/** Physical address of the MSR entry load page (guest MSRs). */
352	RTHCPHYS pMSREntryLoadPhys;
353	/** Virtual address of the MSR entry load page (guest MSRs). */
354	R0PTRTYPE(uint8_t *) pMSREntryLoad;
355
356	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
357	RTR0MEMOBJ pMemObjScratch;
358	RTHCPHYS pScratchPhys;
359	R0PTRTYPE(uint8_t *) pScratch;
360	#endif
361	/** R0 memory object for the MSR exit store page (guest MSRs). */
362	RTR0MEMOBJ pMemObjMSRExitStore;
363	/** Physical address of the MSR exit store page (guest MSRs). */
364	RTHCPHYS pMSRExitStorePhys;
365	/** Virtual address of the MSR exit store page (guest MSRs). */
366	R0PTRTYPE(uint8_t *) pMSRExitStore;
367
368	/** R0 memory object for the MSR exit load page (host MSRs). */
369	RTR0MEMOBJ pMemObjMSRExitLoad;
370	/** Physical address of the MSR exit load page (host MSRs). */
371	RTHCPHYS pMSRExitLoadPhys;
372	/** Virtual address of the MSR exit load page (host MSRs). */
373	R0PTRTYPE(uint8_t *) pMSRExitLoad;
374
375	/** Ring 0 handlers for VT-x. */
376	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
377
378	/** Host CR4 value (set by ring-0 VMX init) */
379	uint64_t hostCR4;
380
381	/** VMX MSR values */
382	struct
383	{
384	uint64_t feature_ctrl;
385	uint64_t vmx_basic_info;
386	VMX_CAPABILITY vmx_pin_ctls;
387	VMX_CAPABILITY vmx_proc_ctls;
388	VMX_CAPABILITY vmx_proc_ctls2;
389	VMX_CAPABILITY vmx_exit;
390	VMX_CAPABILITY vmx_entry;
391	uint64_t vmx_misc;
392	uint64_t vmx_cr0_fixed0;
393	uint64_t vmx_cr0_fixed1;
394	uint64_t vmx_cr4_fixed0;
395	uint64_t vmx_cr4_fixed1;
396	uint64_t vmx_vmcs_enum;
397	uint64_t vmx_eptcaps;
398	} msr;
399
400	/** Flush types for invept & invvpid; they depend on capabilities. */
401	VMX_FLUSH enmFlushPage;
402	VMX_FLUSH enmFlushContext;
403	} vmx;
404
405	struct
406	{
407	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
408	bool fSupported;
409	/** Set when we've enabled SVM. */
410	bool fEnabled;
411	/** Set if erratum 170 affects the AMD cpu. */
412	bool fAlwaysFlushTLB;
413	/** Set when TPR patching is active. */
414	bool fTPRPatchingActive;
415
416	/** R0 memory object for the IO bitmap (12kb). */
417	RTR0MEMOBJ pMemObjIOBitmap;
418	/** Physical address of the IO bitmap (12kb). */
419	RTHCPHYS pIOBitmapPhys;
420	/** Virtual address of the IO bitmap. */
421	R0PTRTYPE(void *) pIOBitmap;
422
423	/** SVM revision. */
424	uint32_t u32Rev;
425
426	/** SVM feature bits from cpuid 0x8000000a */
427	uint32_t u32Features;
428
429	/**
430	* AVL tree with all patches (active or disabled) sorted by guest instruction address
431	*/
432	AVLOU32TREE PatchTree;
433	uint32_t cPatches;
434	HWACCMTPRPATCH aPatches[64];
435	} svm;
436
437	struct
438	{
439	uint32_t u32AMDFeatureECX;
440	uint32_t u32AMDFeatureEDX;
441	} cpuid;
442
443	/** Saved error from detection */
444	int32_t lLastError;
445
446	/** HWACCMR0Init was run */
447	bool fHWACCMR0Init;
448	bool u8Alignment[7];
449
450	STAMCOUNTER StatTPRPatchSuccess;
451	STAMCOUNTER StatTPRPatchFailure;
452	STAMCOUNTER StatTPRReplaceSuccess;
453	STAMCOUNTER StatTPRReplaceFailure;
454	} HWACCM;
455	/** Pointer to HWACCM VM instance data. */
456	typedef HWACCM *PHWACCM;
457
458	/* Maximum number of cached entries. */
459	#define VMCSCACHE_MAX_ENTRY 128
460
461	/* Structure for storing read and write VMCS actions. */
462	typedef struct VMCSCACHE
463	{
464	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
465	/* Magic marker for searching in crash dumps. */
466	uint8_t aMagic[16];
467	uint64_t uMagic;
468	uint64_t u64TimeEntry;
469	uint64_t u64TimeSwitch;
470	uint64_t cResume;
471	uint64_t interPD;
472	uint64_t pSwitcher;
473	uint32_t uPos;
474	uint32_t idCpu;
475	#endif
476	/* CR2 is saved here for EPT syncing. */
477	uint64_t cr2;
478	struct
479	{
480	uint32_t cValidEntries;
481	uint32_t uAlignment;
482	uint32_t aField[VMCSCACHE_MAX_ENTRY];
483	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
484	} Write;
485	struct
486	{
487	uint32_t cValidEntries;
488	uint32_t uAlignment;
489	uint32_t aField[VMCSCACHE_MAX_ENTRY];
490	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
491	} Read;
492	#ifdef DEBUG
493	struct
494	{
495	RTHCPHYS pPageCpuPhys;
496	RTHCPHYS pVMCSPhys;
497	RTGCPTR pCache;
498	RTGCPTR pCtx;
499	} TestIn;
500	struct
501	{
502	RTHCPHYS pVMCSPhys;
503	RTGCPTR pCache;
504	RTGCPTR pCtx;
505	uint64_t eflags;
506	uint64_t cr8;
507	} TestOut;
508	struct
509	{
510	uint64_t param1;
511	uint64_t param2;
512	uint64_t param3;
513	uint64_t param4;
514	} ScratchPad;
515	#endif
516	} VMCSCACHE;
517	/** Pointer to VMCSCACHE. */
518	typedef VMCSCACHE *PVMCSCACHE;
519
520	/** VMX StartVM function. */
521	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
522	/** Pointer to a VMX StartVM function. */
523	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
524
525	/** SVM VMRun function. */
526	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
527	/** Pointer to a SVM VMRun function. */
528	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
529
530	/**
531	* HWACCM VMCPU Instance data.
532	*/
533	typedef struct HWACCMCPU
534	{
535	/** Old style FPU reporting trap mask override performed (optimization) */
536	bool fFPUOldStyleOverride;
537
538	/** Set if we don't have to flush the TLB on VM entry. */
539	bool fResumeVM;
540
541	/** Set if we need to flush the TLB during the world switch. */
542	bool fForceTLBFlush;
543
544	/** Set when we're using VT-x or AMD-V at that moment. */
545	bool fActive;
546
547	/** HWACCM_CHANGED_* flags. */
548	RTUINT fContextUseFlags;
549
550	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
551	RTCPUID idLastCpu;
552
553	/* TLB flush count */
554	RTUINT cTLBFlushes;
555
556	/* Current ASID in use by the VM */
557	RTUINT uCurrentASID;
558
559	struct
560	{
561	/** Physical address of the VM control structure (VMCS). */
562	RTHCPHYS pVMCSPhys;
563	/** R0 memory object for the VM control structure (VMCS). */
564	RTR0MEMOBJ pMemObjVMCS;
565	/** Virtual address of the VM control structure (VMCS). */
566	R0PTRTYPE(void *) pVMCS;
567
568	/** Ring 0 handlers for VT-x. */
569	PFNHWACCMVMXSTARTVM pfnStartVM;
570
571	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
572	uint64_t proc_ctls;
573
574	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
575	uint64_t proc_ctls2;
576
577	/** Physical address of the virtual APIC page for TPR caching. */
578	RTHCPHYS pVAPICPhys;
579	/** R0 memory object for the virtual APIC page for TPR caching. */
580	RTR0MEMOBJ pMemObjVAPIC;
581	/** Virtual address of the virtual APIC page for TPR caching. */
582	R0PTRTYPE(uint8_t *) pVAPIC;
583
584	/** Current CR0 mask. */
585	uint64_t cr0_mask;
586	/** Current CR4 mask. */
587	uint64_t cr4_mask;
588
589	/** Current EPTP. */
590	RTHCPHYS GCPhysEPTP;
591
592	/** Physical address of the MSR bitmap (1 page). */
593	RTHCPHYS pMSRBitmapPhys;
594	/** R0 memory object for the MSR bitmap (1 page). */
595	RTR0MEMOBJ pMemObjMSRBitmap;
596	/** Virtual address of the MSR bitmap (1 page). */
597	R0PTRTYPE(uint8_t *) pMSRBitmap;
598
599	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
600	/** Physical address of the guest MSR load area (1 page). */
601	RTHCPHYS pGuestMSRPhys;
602	/** R0 memory object for the guest MSR load area (1 page). */
603	RTR0MEMOBJ pMemObjGuestMSR;
604	/** Virtual address of the guest MSR load area (1 page). */
605	R0PTRTYPE(uint8_t *) pGuestMSR;
606
607	/** Physical address of the MSR load area (1 page). */
608	RTHCPHYS pHostMSRPhys;
609	/** R0 memory object for the MSR load area (1 page). */
610	RTR0MEMOBJ pMemObjHostMSR;
611	/** Virtual address of the MSR load area (1 page). */
612	R0PTRTYPE(uint8_t *) pHostMSR;
613	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
614
615	/* Number of automatically loaded/restored MSRs. */
616	uint32_t cCachedMSRs;
617	uint32_t uAlignement;
618
619	/** VMCS cache. */
620	VMCSCACHE VMCSCache;
621
622	/** Real-mode emulation state. */
623	struct
624	{
625	X86EFLAGS eflags;
626	uint32_t fValid;
627	} RealMode;
628
629	struct
630	{
631	uint64_t u64VMCSPhys;
632	uint32_t ulVMCSRevision;
633	uint32_t ulInstrError;
634	uint32_t ulExitReason;
635	RTCPUID idEnteredCpu;
636	RTCPUID idCurrentCpu;
637	uint32_t padding;
638	} lasterror;
639
640	/** The last seen guest paging mode (by VT-x). */
641	PGMMODE enmLastSeenGuestMode;
642	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
643	PGMMODE enmCurrGuestMode;
644	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
645	PGMMODE enmPrevGuestMode;
646	} vmx;
647
648	struct
649	{
650	/** R0 memory object for the host VM control block (VMCB). */
651	RTR0MEMOBJ pMemObjVMCBHost;
652	/** Physical address of the host VM control block (VMCB). */
653	RTHCPHYS pVMCBHostPhys;
654	/** Virtual address of the host VM control block (VMCB). */
655	R0PTRTYPE(void *) pVMCBHost;
656
657	/** R0 memory object for the VM control block (VMCB). */
658	RTR0MEMOBJ pMemObjVMCB;
659	/** Physical address of the VM control block (VMCB). */
660	RTHCPHYS pVMCBPhys;
661	/** Virtual address of the VM control block (VMCB). */
662	R0PTRTYPE(void *) pVMCB;
663
664	/** Ring 0 handlers for VT-x. */
665	PFNHWACCMSVMVMRUN pfnVMRun;
666
667	/** R0 memory object for the MSR bitmap (8kb). */
668	RTR0MEMOBJ pMemObjMSRBitmap;
669	/** Physical address of the MSR bitmap (8kb). */
670	RTHCPHYS pMSRBitmapPhys;
671	/** Virtual address of the MSR bitmap. */
672	R0PTRTYPE(void *) pMSRBitmap;
673	} svm;
674
675	/** Event injection state. */
676	struct
677	{
678	uint32_t fPending;
679	uint32_t errCode;
680	uint64_t intInfo;
681	} Event;
682
683	/** IO Block emulation state. */
684	struct
685	{
686	bool fEnabled;
687	uint8_t u8Align[7];
688
689	/** RIP at the start of the io code we wish to emulate in the recompiler. */
690	RTGCPTR GCPtrFunctionEip;
691
692	uint64_t cr0;
693	} EmulateIoBlock;
694
695	struct
696	{
697	/* Pending IO operation type. */
698	HWACCMPENDINGIO enmType;
699	uint32_t uPadding;
700	RTGCPTR GCPtrRip;
701	RTGCPTR GCPtrRipNext;
702	union
703	{
704	struct
705	{
706	unsigned uPort;
707	unsigned uAndVal;
708	unsigned cbSize;
709	} Port;
710	uint64_t aRaw[2];
711	} s;
712	} PendingIO;
713
714	/** Currenty shadow paging mode. */
715	PGMMODE enmShadowMode;
716
717	/** The CPU ID of the CPU currently owning the VMCS. Set in
718	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
719	RTCPUID idEnteredCpu;
720
721	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
722	struct
723	{
724	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
725	unsigned cPages;
726	} TlbShootdown;
727
728	/** For saving stack space, the disassembler state is allocated here instead of
729	* on the stack.
730	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
731	union
732	{
733	/** The disassembler scratch space. */
734	DISCPUSTATE DisState;
735	/** Padding. */
736	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
737	};
738
739	RTUINT padding2[1];
740
741	STAMPROFILEADV StatEntry;
742	STAMPROFILEADV StatExit1;
743	STAMPROFILEADV StatExit2;
744	#if 1 /* temporary for tracking down darwin issues. */
745	STAMPROFILEADV StatExit2Sub1;
746	STAMPROFILEADV StatExit2Sub2;
747	STAMPROFILEADV StatExit2Sub3;
748	#endif
749	STAMPROFILEADV StatInGC;
750
751	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
752	STAMPROFILEADV StatWorldSwitch3264;
753	#endif
754
755	STAMCOUNTER StatIntInject;
756
757	STAMCOUNTER StatExitShadowNM;
758	STAMCOUNTER StatExitGuestNM;
759	STAMCOUNTER StatExitShadowPF;
760	STAMCOUNTER StatExitGuestPF;
761	STAMCOUNTER StatExitGuestUD;
762	STAMCOUNTER StatExitGuestSS;
763	STAMCOUNTER StatExitGuestNP;
764	STAMCOUNTER StatExitGuestGP;
765	STAMCOUNTER StatExitGuestDE;
766	STAMCOUNTER StatExitGuestDB;
767	STAMCOUNTER StatExitGuestMF;
768	STAMCOUNTER StatExitInvpg;
769	STAMCOUNTER StatExitInvd;
770	STAMCOUNTER StatExitCpuid;
771	STAMCOUNTER StatExitRdtsc;
772	STAMCOUNTER StatExitRdpmc;
773	STAMCOUNTER StatExitCli;
774	STAMCOUNTER StatExitSti;
775	STAMCOUNTER StatExitPushf;
776	STAMCOUNTER StatExitPopf;
777	STAMCOUNTER StatExitIret;
778	STAMCOUNTER StatExitInt;
779	STAMCOUNTER StatExitCRxWrite[16];
780	STAMCOUNTER StatExitCRxRead[16];
781	STAMCOUNTER StatExitDRxWrite;
782	STAMCOUNTER StatExitDRxRead;
783	STAMCOUNTER StatExitRdmsr;
784	STAMCOUNTER StatExitWrmsr;
785	STAMCOUNTER StatExitCLTS;
786	STAMCOUNTER StatExitHlt;
787	STAMCOUNTER StatExitMwait;
788	STAMCOUNTER StatExitLMSW;
789	STAMCOUNTER StatExitIOWrite;
790	STAMCOUNTER StatExitIORead;
791	STAMCOUNTER StatExitIOStringWrite;
792	STAMCOUNTER StatExitIOStringRead;
793	STAMCOUNTER StatExitIrqWindow;
794	STAMCOUNTER StatExitMaxResume;
795	STAMCOUNTER StatExitPreemptPending;
796	STAMCOUNTER StatIntReinject;
797	STAMCOUNTER StatPendingHostIrq;
798
799	STAMCOUNTER StatFlushPageManual;
800	STAMCOUNTER StatFlushPhysPageManual;
801	STAMCOUNTER StatFlushTLBManual;
802	STAMCOUNTER StatFlushPageInvlpg;
803	STAMCOUNTER StatFlushTLBWorldSwitch;
804	STAMCOUNTER StatNoFlushTLBWorldSwitch;
805	STAMCOUNTER StatFlushTLBCRxChange;
806	STAMCOUNTER StatFlushASID;
807	STAMCOUNTER StatFlushTLBInvlpga;
808	STAMCOUNTER StatTlbShootdown;
809	STAMCOUNTER StatTlbShootdownFlush;
810
811	STAMCOUNTER StatSwitchGuestIrq;
812	STAMCOUNTER StatSwitchToR3;
813
814	STAMCOUNTER StatTSCOffset;
815	STAMCOUNTER StatTSCIntercept;
816
817	STAMCOUNTER StatExitReasonNPF;
818	STAMCOUNTER StatDRxArmed;
819	STAMCOUNTER StatDRxContextSwitch;
820	STAMCOUNTER StatDRxIOCheck;
821
822
823	#ifdef VBOX_WITH_STATISTICS
824	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
825	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
826	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
827	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
828	#endif
829	} HWACCMCPU;
830	/** Pointer to HWACCM VM instance data. */
831	typedef HWACCMCPU *PHWACCMCPU;
832
833
834	#ifdef IN_RING0
835
836	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
837	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
838
839
840	#ifdef VBOX_STRICT
841	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
842	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
843	#else
844	#define HWACCMDumpRegs(a, b ,c) do { } while (0)
845	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
846	#endif
847
848	/* Dummy callback handlers. */
849	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
850	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
851	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
852	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
853	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
854	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
855	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
856	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
857	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
858	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
859
860	# ifdef VBOX_WITH_KERNEL_USING_XMM
861	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
862	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
863	# endif
864
865	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
866	/**
867	* Gets 64-bit GDTR and IDTR on darwin.
868	* @param pGdtr Where to store the 64-bit GDTR.
869	* @param pIdtr Where to store the 64-bit IDTR.
870	*/
871	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
872
873	/**
874	* Gets 64-bit CR3 on darwin.
875	* @returns CR3
876	*/
877	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
878	# endif
879
880	#endif /* IN_RING0 */
881
882	/** @} */
883
884	RT_C_DECLS_END
885
886	#endif
887

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 22173

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