CPUM.cpp@ 26646

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CPUM: better topology info for Intel CPUs
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1	/* $Id: CPUM.cpp 26646 2010-02-19 12:29:28Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/mm.h>
46	#include <VBox/selm.h>
47	#include <VBox/dbgf.h>
48	#include <VBox/patm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/ssm.h>
51	#include "CPUMInternal.h"
52	#include <VBox/vm.h>
53
54	#include <VBox/param.h>
55	#include <VBox/dis.h>
56	#include <VBox/err.h>
57	#include <VBox/log.h>
58	#include <iprt/assert.h>
59	#include <iprt/asm.h>
60	#include <iprt/string.h>
61	#include <iprt/mp.h>
62	#include <iprt/cpuset.h>
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	/** The current saved state version. */
69	#define CPUM_SAVED_STATE_VERSION 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatability. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detech the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	/*
232	* Initialize the Guest CPUID state.
233	*/
234	rc = cpumR3CpuIdInit(pVM);
235	if (RT_FAILURE(rc))
236	return rc;
237	CPUMR3Reset(pVM);
238	return VINF_SUCCESS;
239	}
240
241
242	/**
243	* Initializes the per-VCPU CPUM.
244	*
245	* @returns VBox status code.
246	* @param pVM The VM to operate on.
247	*/
248	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
249	{
250	LogFlow(("CPUMR3InitCPU\n"));
251	return VINF_SUCCESS;
252	}
253
254
255	/**
256	* Detect the CPU vendor give n the
257	*
258	* @returns The vendor.
259	* @param uEAX EAX from CPUID(0).
260	* @param uEBX EBX from CPUID(0).
261	* @param uECX ECX from CPUID(0).
262	* @param uEDX EDX from CPUID(0).
263	*/
264	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
265	{
266	if ( uEAX >= 1
267	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
268	&& uECX == X86_CPUID_VENDOR_AMD_ECX
269	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
270	return CPUMCPUVENDOR_AMD;
271
272	if ( uEAX >= 1
273	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
274	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
275	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
276	return CPUMCPUVENDOR_INTEL;
277
278	/** @todo detect the other buggers... */
279	return CPUMCPUVENDOR_UNKNOWN;
280	}
281
282
283	/**
284	* Fetches overrides for a CPUID leaf.
285	*
286	* @returns VBox status code.
287	* @param pLeaf The leaf to load the overrides into.
288	* @param pCfgNode The CFGM node containing the overrides
289	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
290	* @param iLeaf The CPUID leaf number.
291	*/
292	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
293	{
294	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
295	if (pLeafNode)
296	{
297	uint32_t u32;
298	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
299	if (RT_SUCCESS(rc))
300	pLeaf->eax = u32;
301	else
302	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
303
304	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
305	if (RT_SUCCESS(rc))
306	pLeaf->ebx = u32;
307	else
308	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
309
310	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
311	if (RT_SUCCESS(rc))
312	pLeaf->ecx = u32;
313	else
314	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
315
316	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
317	if (RT_SUCCESS(rc))
318	pLeaf->edx = u32;
319	else
320	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
321
322	}
323	return VINF_SUCCESS;
324	}
325
326
327	/**
328	* Load the overrides for a set of CPUID leafs.
329	*
330	* @returns VBox status code.
331	* @param paLeafs The leaf array.
332	* @param cLeafs The number of leafs.
333	* @param uStart The start leaf number.
334	* @param pCfgNode The CFGM node containing the overrides
335	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
336	*/
337	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
338	{
339	for (uint32_t i = 0; i < cLeafs; i++)
340	{
341	int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
342	if (RT_FAILURE(rc))
343	return rc;
344	}
345
346	return VINF_SUCCESS;
347	}
348
349	/**
350	* Init a set of host CPUID leafs.
351	*
352	* @returns VBox status code.
353	* @param paLeafs The leaf array.
354	* @param cLeafs The number of leafs.
355	* @param uStart The start leaf number.
356	* @param pCfgNode The /CPUM/HostCPUID/ node.
357	*/
358	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
359	{
360	/* Using the ECX variant for all of them can't hurt... */
361	for (uint32_t i = 0; i < cLeafs; i++)
362	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
363
364	/* Load CPUID leaf override; we currently don't care if the caller
365	specifies features the host CPU doesn't support. */
366	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
367	}
368
369
370	/**
371	* Initializes the emulated CPU's cpuid information.
372	*
373	* @returns VBox status code.
374	* @param pVM The VM to operate on.
375	*/
376	static int cpumR3CpuIdInit(PVM pVM)
377	{
378	PCPUM pCPUM = &pVM->cpum.s;
379	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
380	uint32_t i;
381	int rc;
382
383	/*
384	* Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
385	*/
386	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
387	* Overrides the host CPUID leaf values used for calculating the guest CPUID
388	* leafs. This can be used to preserve the CPUID values when moving a VM to
389	* a different machine. Another use is restricting (or extending) the
390	* feature set exposed to the guest. */
391	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
392	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
393	AssertRCReturn(rc, rc);
394	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
395	AssertRCReturn(rc, rc);
396	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
397	AssertRCReturn(rc, rc);
398
399	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
400	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
401
402	/*
403	* Only report features we can support.
404	*/
405	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
406	\| X86_CPUID_FEATURE_EDX_VME
407	\| X86_CPUID_FEATURE_EDX_DE
408	\| X86_CPUID_FEATURE_EDX_PSE
409	\| X86_CPUID_FEATURE_EDX_TSC
410	\| X86_CPUID_FEATURE_EDX_MSR
411	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
412	\| X86_CPUID_FEATURE_EDX_MCE
413	\| X86_CPUID_FEATURE_EDX_CX8
414	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
415	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
416	//\| X86_CPUID_FEATURE_EDX_SEP
417	\| X86_CPUID_FEATURE_EDX_MTRR
418	\| X86_CPUID_FEATURE_EDX_PGE
419	\| X86_CPUID_FEATURE_EDX_MCA
420	\| X86_CPUID_FEATURE_EDX_CMOV
421	\| X86_CPUID_FEATURE_EDX_PAT
422	\| X86_CPUID_FEATURE_EDX_PSE36
423	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
424	\| X86_CPUID_FEATURE_EDX_CLFSH
425	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
426	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
427	\| X86_CPUID_FEATURE_EDX_MMX
428	\| X86_CPUID_FEATURE_EDX_FXSR
429	\| X86_CPUID_FEATURE_EDX_SSE
430	\| X86_CPUID_FEATURE_EDX_SSE2
431	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
432	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
433	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
434	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
435	\| 0;
436	pCPUM->aGuestCpuIdStd[1].ecx &= 0
437	\| X86_CPUID_FEATURE_ECX_SSE3
438	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
439	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
440	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
441	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
442	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
443	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
444	\| X86_CPUID_FEATURE_ECX_SSSE3
445	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
446	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
447	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
448	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
449	/* ECX Bit 21 - x2APIC support - not yet. */
450	// \| X86_CPUID_FEATURE_ECX_X2APIC
451	/* ECX Bit 23 - POPCNT instruction. */
452	//\| X86_CPUID_FEATURE_ECX_POPCNT
453	\| 0;
454
455	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
456	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
457	\| X86_CPUID_AMD_FEATURE_EDX_VME
458	\| X86_CPUID_AMD_FEATURE_EDX_DE
459	\| X86_CPUID_AMD_FEATURE_EDX_PSE
460	\| X86_CPUID_AMD_FEATURE_EDX_TSC
461	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
462	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
463	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
464	\| X86_CPUID_AMD_FEATURE_EDX_CX8
465	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
466	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
467	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
468	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
469	\| X86_CPUID_AMD_FEATURE_EDX_PGE
470	\| X86_CPUID_AMD_FEATURE_EDX_MCA
471	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
472	\| X86_CPUID_AMD_FEATURE_EDX_PAT
473	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
474	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
475	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
476	\| X86_CPUID_AMD_FEATURE_EDX_MMX
477	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
478	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
479	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
480	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
481	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
482	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
483	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
484	\| 0;
485	pCPUM->aGuestCpuIdExt[1].ecx &= 0
486	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
487	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
488	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
489	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
490	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
491	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
492	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
493	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
494	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
495	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
496	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
497	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
498	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
499	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
500	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
501	\| 0;
502
503	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
504	if (pCPUM->fSyntheticCpu)
505	{
506	const char szVendor[13] = "VirtualBox ";
507	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
508
509	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
510
511	/* Limit the nr of standard leaves; 5 for monitor/mwait */
512	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
513
514	/* 0: Vendor */
515	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
516	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
517	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
518
519	/* 1.eax: Version information. family : model : stepping */
520	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
521
522	/* Leaves 2 - 4 are Intel only - zero them out */
523	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
524	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
525	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
526
527	/* Leaf 5 = monitor/mwait */
528
529	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
530	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
531	/* AMD only - set to zero. */
532	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
533
534	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
535	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
536
537	/* 0x800000002-4: Processor Name String Identifier. */
538	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
539	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
540	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
541	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
542	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
543	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
544	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
545	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
546	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
547	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
548	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
549	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
550
551	/* 0x800000005-7 - reserved -> zero */
552	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
553	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
554	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
555
556	/* 0x800000008: only the max virtual and physical address size. */
557	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
558	}
559
560	/*
561	* Hide HTT, multicode, SMP, whatever.
562	* (APIC-ID := 0 and #LogCpus := 0)
563	*/
564	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
565	#ifdef VBOX_WITH_MULTI_CORE
566	if (pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC)
567	{
568	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
569	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
570	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
571	}
572	#endif
573
574	/* Cpuid 2:
575	* Intel: Cache and TLB information
576	* AMD: Reserved
577	* Safe to expose
578	*/
579
580	/* Cpuid 3:
581	* Intel: EAX, EBX - reserved
582	* ECX, EDX - Processor Serial Number if available, otherwise reserved
583	* AMD: Reserved
584	* Safe to expose
585	*/
586	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
587	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
588
589	/* Cpuid 4:
590	* Intel: Deterministic Cache Parameters Leaf
591	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
592	* AMD: Reserved
593	* Safe to expose, except for EAX:
594	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
595	* Bits 31-26: Maximum number of processor cores in this physical package**
596	* Note: These SMP values are constant regardless of ECX
597	*/
598	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
599	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
600	#ifdef VBOX_WITH_MULTI_CORE
601	if ( pVM->cCpus > 1
602	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
603	{
604	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
605	/* One logical processor with possibly multiple cores. */
606	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
607	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
608	}
609	#endif
610
611	/* Cpuid 5: Monitor/mwait Leaf
612	* Intel: ECX, EDX - reserved
613	* EAX, EBX - Smallest and largest monitor line size
614	* AMD: EDX - reserved
615	* EAX, EBX - Smallest and largest monitor line size
616	* ECX - extensions (ignored for now)
617	* Safe to expose
618	*/
619	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
620	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
621
622	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
623
624	/*
625	* Determine the default.
626	*
627	* Intel returns values of the highest standard function, while AMD
628	* returns zeros. VIA on the other hand seems to returning nothing or
629	* perhaps some random garbage, we don't try to duplicate this behavior.
630	*/
631	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
632	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
633	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
634
635	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
636	* Safe to pass on to the guest.
637	*
638	* Intel: 0x800000005 reserved
639	* 0x800000006 L2 cache information
640	* AMD: 0x800000005 L1 cache information
641	* 0x800000006 L2/L3 cache information
642	*/
643
644	/* Cpuid 0x800000007:
645	* AMD: EAX, EBX, ECX - reserved
646	* EDX: Advanced Power Management Information
647	* Intel: Reserved
648	*/
649	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
650	{
651	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
652
653	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
654
655	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
656	{
657	/* Only expose the TSC invariant capability bit to the guest. */
658	pCPUM->aGuestCpuIdExt[7].edx &= 0
659	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
660	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
661	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
662	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
663	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
664	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
665	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
666	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
667	#if 1
668	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
669	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
670	*/
671	#else
672	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
673	#endif
674	\| 0;
675	}
676	else
677	pCPUM->aGuestCpuIdExt[7].edx = 0;
678	}
679
680	/* Cpuid 0x800000008:
681	* AMD: EBX, EDX - reserved
682	* EAX: Virtual/Physical address Size
683	* ECX: Number of cores + APICIdCoreIdSize
684	* Intel: EAX: Virtual/Physical address Size
685	* EBX, ECX, EDX - reserved
686	*/
687	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
688	{
689	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
690	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
691	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
692	* NC (0-7) Number of cores; 0 equals 1 core */
693	pCPUM->aGuestCpuIdExt[8].ecx = 0;
694	#ifdef VBOX_WITH_MULTI_CORE
695	if ( pVM->cCpus > 1
696	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
697	{
698	/* Legacy method to determine the number of cores. */
699	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
700	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
701
702	}
703	#endif
704	}
705
706	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
707	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
708	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
709	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
710	*/
711	bool fNt4LeafLimit;
712	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
713	if (fNt4LeafLimit)
714	pCPUM->aGuestCpuIdStd[0].eax = 3;
715
716	/*
717	* Limit it the number of entries and fill the remaining with the defaults.
718	*
719	* The limits are masking off stuff about power saving and similar, this
720	* is perhaps a bit crudely done as there is probably some relatively harmless
721	* info too in these leaves (like words about having a constant TSC).
722	*/
723	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
724	pCPUM->aGuestCpuIdStd[0].eax = 5;
725
726	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
727	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
728
729	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
730	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
731	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
732	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
733	: 0;
734	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
735	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
736
737	/*
738	* Centaur stuff (VIA).
739	*
740	* The important part here (we think) is to make sure the 0xc0000000
741	* function returns 0xc0000001. As for the features, we don't currently
742	* let on about any of those... 0xc0000002 seems to be some
743	* temperature/hz/++ stuff, include it as well (static).
744	*/
745	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
746	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
747	{
748	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
749	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
750	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
751	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
752	i++)
753	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
754	}
755	else
756	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
757	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
758
759
760	/*
761	* Load CPUID overrides from configuration.
762	* Note: Kind of redundant now, but allows unchanged overrides
763	*/
764	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
765	* Overrides the CPUID leaf values. */
766	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
767	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
768	AssertRCReturn(rc, rc);
769	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
770	AssertRCReturn(rc, rc);
771	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
772	AssertRCReturn(rc, rc);
773
774	/*
775	* Check if PAE was explicitely enabled by the user.
776	*/
777	bool fEnable;
778	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
779	if (fEnable)
780	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
781
782	/*
783	* Log the cpuid and we're good.
784	*/
785	RTCPUSET OnlineSet;
786	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
787	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
788	LogRel(("*********************** CPUID dump **********************\n"));
789	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
790	LogRel(("\n"));
791	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
792	LogRel(("****************** End of CPUID dump ********************\n"));
793	return VINF_SUCCESS;
794	}
795
796
797
798
799	/**
800	* Applies relocations to data and code managed by this
801	* component. This function will be called at init and
802	* whenever the VMM need to relocate it self inside the GC.
803	*
804	* The CPUM will update the addresses used by the switcher.
805	*
806	* @param pVM The VM.
807	*/
808	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
809	{
810	LogFlow(("CPUMR3Relocate\n"));
811	for (VMCPUID i = 0; i < pVM->cCpus; i++)
812	{
813	/*
814	* Switcher pointers.
815	*/
816	PVMCPU pVCpu = &pVM->aCpus[i];
817	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
818	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
819	}
820	}
821
822
823	/**
824	* Terminates the CPUM.
825	*
826	* Termination means cleaning up and freeing all resources,
827	* the VM it self is at this point powered off or suspended.
828	*
829	* @returns VBox status code.
830	* @param pVM The VM to operate on.
831	*/
832	VMMR3DECL(int) CPUMR3Term(PVM pVM)
833	{
834	CPUMR3TermCPU(pVM);
835	return 0;
836	}
837
838
839	/**
840	* Terminates the per-VCPU CPUM.
841	*
842	* Termination means cleaning up and freeing all resources,
843	* the VM it self is at this point powered off or suspended.
844	*
845	* @returns VBox status code.
846	* @param pVM The VM to operate on.
847	*/
848	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
849	{
850	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
851	for (VMCPUID i = 0; i < pVM->cCpus; i++)
852	{
853	PVMCPU pVCpu = &pVM->aCpus[i];
854	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
855
856	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
857	pVCpu->cpum.s.uMagic = 0;
858	pCtx->dr[5] = 0;
859	}
860	#endif
861	return 0;
862	}
863
864
865	/**
866	* Resets a virtual CPU.
867	*
868	* Used by CPUMR3Reset and CPU hot plugging.
869	*
870	* @param pVCpu The virtual CPU handle.
871	*/
872	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
873	{
874	/** @todo anything different for VCPU > 0? */
875	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
876
877	/*
878	* Initialize everything to ZERO first.
879	*/
880	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
881	memset(pCtx, 0, sizeof(*pCtx));
882	pVCpu->cpum.s.fUseFlags = fUseFlags;
883
884	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
885	pCtx->eip = 0x0000fff0;
886	pCtx->edx = 0x00000600; /* P6 processor */
887	pCtx->eflags.Bits.u1Reserved0 = 1;
888
889	pCtx->cs = 0xf000;
890	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
891	pCtx->csHid.u32Limit = 0x0000ffff;
892	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
893	pCtx->csHid.Attr.n.u1Present = 1;
894	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
895
896	pCtx->dsHid.u32Limit = 0x0000ffff;
897	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
898	pCtx->dsHid.Attr.n.u1Present = 1;
899	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
900
901	pCtx->esHid.u32Limit = 0x0000ffff;
902	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
903	pCtx->esHid.Attr.n.u1Present = 1;
904	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
905
906	pCtx->fsHid.u32Limit = 0x0000ffff;
907	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
908	pCtx->fsHid.Attr.n.u1Present = 1;
909	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
910
911	pCtx->gsHid.u32Limit = 0x0000ffff;
912	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
913	pCtx->gsHid.Attr.n.u1Present = 1;
914	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
915
916	pCtx->ssHid.u32Limit = 0x0000ffff;
917	pCtx->ssHid.Attr.n.u1Present = 1;
918	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
919	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
920
921	pCtx->idtr.cbIdt = 0xffff;
922	pCtx->gdtr.cbGdt = 0xffff;
923
924	pCtx->ldtrHid.u32Limit = 0xffff;
925	pCtx->ldtrHid.Attr.n.u1Present = 1;
926	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
927
928	pCtx->trHid.u32Limit = 0xffff;
929	pCtx->trHid.Attr.n.u1Present = 1;
930	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
931
932	pCtx->dr[6] = X86_DR6_INIT_VAL;
933	pCtx->dr[7] = X86_DR7_INIT_VAL;
934
935	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
936	pCtx->fpu.FCW = 0x37f;
937
938	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
939	pCtx->fpu.MXCSR = 0x1F80;
940
941	/* Init PAT MSR */
942	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
943
944	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
945	* The Intel docs don't mention it.
946	*/
947	pCtx->msrEFER = 0;
948	}
949
950
951	/**
952	* Resets the CPU.
953	*
954	* @returns VINF_SUCCESS.
955	* @param pVM The VM handle.
956	*/
957	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
958	{
959	for (VMCPUID i = 0; i < pVM->cCpus; i++)
960	{
961	CPUMR3ResetCpu(&pVM->aCpus[i]);
962
963	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
964	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
965
966	/* Magic marker for searching in crash dumps. */
967	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
968	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
969	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
970	#endif
971	}
972	}
973
974
975	/**
976	* Called both in pass 0 and the final pass.
977	*
978	* @param pVM The VM handle.
979	* @param pSSM The saved state handle.
980	*/
981	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
982	{
983	/*
984	* Save all the CPU ID leaves here so we can check them for compatability
985	* upon loading.
986	*/
987	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
988	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
989
990	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
991	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
992
993	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
994	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
995
996	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
997
998	/*
999	* Save a good portion of the raw CPU IDs as well as they may come in
1000	* handy when validating features for raw mode.
1001	*/
1002	CPUMCPUID aRawStd[16];
1003	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1004	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1005	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1006	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1007
1008	CPUMCPUID aRawExt[32];
1009	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1010	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1011	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1012	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1013	}
1014
1015
1016	/**
1017	* Loads the CPU ID leaves saved by pass 0.
1018	*
1019	* @returns VBox status code.
1020	* @param pVM The VM handle.
1021	* @param pSSM The saved state handle.
1022	* @param uVersion The format version.
1023	*/
1024	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1025	{
1026	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1027
1028	/*
1029	* Define a bunch of macros for simplifying the code.
1030	*/
1031	/* Generic expression + failure message. */
1032	#define CPUID_CHECK_RET(expr, fmt) \
1033	do { \
1034	if (!(expr)) \
1035	{ \
1036	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1037	if (fStrictCpuIdChecks) \
1038	{ \
1039	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1040	RTStrFree(pszMsg); \
1041	return rcCpuid; \
1042	} \
1043	LogRel(("CPUM: %s\n", pszMsg)); \
1044	RTStrFree(pszMsg); \
1045	} \
1046	} while (0)
1047	#define CPUID_CHECK_WRN(expr, fmt) \
1048	do { \
1049	if (!(expr)) \
1050	LogRel(fmt); \
1051	} while (0)
1052
1053	/* For comparing two values and bitch if they differs. */
1054	#define CPUID_CHECK2_RET(what, host, saved) \
1055	do { \
1056	if ((host) != (saved)) \
1057	{ \
1058	if (fStrictCpuIdChecks) \
1059	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1060	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1061	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1062	} \
1063	} while (0)
1064	#define CPUID_CHECK2_WRN(what, host, saved) \
1065	do { \
1066	if ((host) != (saved)) \
1067	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1068	} while (0)
1069
1070	/* For checking raw cpu features (raw mode). */
1071	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1072	do { \
1073	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1074	{ \
1075	if (fStrictCpuIdChecks) \
1076	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1077	N_(#bit " mismatch: host=%d saved=%d"), \
1078	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1079	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1080	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1081	} \
1082	} while (0)
1083	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1084	do { \
1085	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1086	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1087	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1088	} while (0)
1089	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1090
1091	/* For checking guest features. */
1092	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1093	do { \
1094	if ( (aGuestCpuId##set [1].reg & bit) \
1095	&& !(aHostRaw##set [1].reg & bit) \
1096	&& !(aHostOverride##set [1].reg & bit) \
1097	&& !(aGuestOverride##set [1].reg & bit) \
1098	) \
1099	{ \
1100	if (fStrictCpuIdChecks) \
1101	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1102	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1103	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1104	} \
1105	} while (0)
1106	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1107	do { \
1108	if ( (aGuestCpuId##set [1].reg & bit) \
1109	&& !(aHostRaw##set [1].reg & bit) \
1110	&& !(aHostOverride##set [1].reg & bit) \
1111	&& !(aGuestOverride##set [1].reg & bit) \
1112	) \
1113	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1114	} while (0)
1115	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1116	do { \
1117	if ( (aGuestCpuId##set [1].reg & bit) \
1118	&& !(aHostRaw##set [1].reg & bit) \
1119	&& !(aHostOverride##set [1].reg & bit) \
1120	&& !(aGuestOverride##set [1].reg & bit) \
1121	) \
1122	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1123	} while (0)
1124	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1125
1126	/* For checking guest features if AMD guest CPU. */
1127	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1128	do { \
1129	if ( (aGuestCpuId##set [1].reg & bit) \
1130	&& fGuestAmd \
1131	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1132	&& !(aHostOverride##set [1].reg & bit) \
1133	&& !(aGuestOverride##set [1].reg & bit) \
1134	) \
1135	{ \
1136	if (fStrictCpuIdChecks) \
1137	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1138	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1139	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1140	} \
1141	} while (0)
1142	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1143	do { \
1144	if ( (aGuestCpuId##set [1].reg & bit) \
1145	&& fGuestAmd \
1146	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1147	&& !(aHostOverride##set [1].reg & bit) \
1148	&& !(aGuestOverride##set [1].reg & bit) \
1149	) \
1150	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1151	} while (0)
1152	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1153	do { \
1154	if ( (aGuestCpuId##set [1].reg & bit) \
1155	&& fGuestAmd \
1156	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1157	&& !(aHostOverride##set [1].reg & bit) \
1158	&& !(aGuestOverride##set [1].reg & bit) \
1159	) \
1160	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1161	} while (0)
1162	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1163
1164	/* For checking AMD features which have a corresponding bit in the standard
1165	range. (Intel defines very few bits in the extended feature sets.) */
1166	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1167	do { \
1168	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1169	&& !(fHostAmd \
1170	? aHostRawExt[1].reg & (ExtBit) \
1171	: aHostRawStd[1].reg & (StdBit)) \
1172	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1173	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1174	) \
1175	{ \
1176	if (fStrictCpuIdChecks) \
1177	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1178	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1179	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1180	} \
1181	} while (0)
1182	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1183	do { \
1184	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1185	&& !(fHostAmd \
1186	? aHostRawExt[1].reg & (ExtBit) \
1187	: aHostRawStd[1].reg & (StdBit)) \
1188	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1189	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1190	) \
1191	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1192	} while (0)
1193	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1194	do { \
1195	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1196	&& !(fHostAmd \
1197	? aHostRawExt[1].reg & (ExtBit) \
1198	: aHostRawStd[1].reg & (StdBit)) \
1199	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1200	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1201	) \
1202	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1203	} while (0)
1204	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1205
1206	/*
1207	* Load them into stack buffers first.
1208	*/
1209	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1210	uint32_t cGuestCpuIdStd;
1211	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1212	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1213	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1214	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1215
1216	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1217	uint32_t cGuestCpuIdExt;
1218	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1219	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1220	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1221	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1222
1223	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1224	uint32_t cGuestCpuIdCentaur;
1225	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1226	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1227	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1228	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1229
1230	CPUMCPUID GuestCpuIdDef;
1231	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1232	AssertRCReturn(rc, rc);
1233
1234	CPUMCPUID aRawStd[16];
1235	uint32_t cRawStd;
1236	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1237	if (cRawStd > RT_ELEMENTS(aRawStd))
1238	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1239	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1240
1241	CPUMCPUID aRawExt[32];
1242	uint32_t cRawExt;
1243	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1244	if (cRawExt > RT_ELEMENTS(aRawExt))
1245	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1246	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1247	AssertRCReturn(rc, rc);
1248
1249	/*
1250	* Note that we support restoring less than the current amount of standard
1251	* leaves because we've been allowed more is newer version of VBox.
1252	*
1253	* So, pad new entries with the default.
1254	*/
1255	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1256	aGuestCpuIdStd[i] = GuestCpuIdDef;
1257
1258	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1259	aGuestCpuIdExt[i] = GuestCpuIdDef;
1260
1261	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1262	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1263
1264	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1265	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1266
1267	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1268	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1269
1270	/*
1271	* Get the raw CPU IDs for the current host.
1272	*/
1273	CPUMCPUID aHostRawStd[16];
1274	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1275	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1276
1277	CPUMCPUID aHostRawExt[32];
1278	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1279	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1280
1281	/*
1282	* Get the host and guest overrides so we don't reject the state because
1283	* some feature was enabled thru these interfaces.
1284	* Note! We currently only need the feature leafs, so skip rest.
1285	*/
1286	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1287	CPUMCPUID aGuestOverrideStd[2];
1288	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1289	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1290
1291	CPUMCPUID aGuestOverrideExt[2];
1292	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1293	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1294
1295	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1296	CPUMCPUID aHostOverrideStd[2];
1297	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1298	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1299
1300	CPUMCPUID aHostOverrideExt[2];
1301	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1302	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1303
1304	/*
1305	* This can be skipped.
1306	*/
1307	bool fStrictCpuIdChecks;
1308	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1309
1310
1311
1312	/*
1313	* For raw-mode we'll require that the CPUs are very similar since we don't
1314	* intercept CPUID instructions for user mode applications.
1315	*/
1316	if (!HWACCMIsEnabled(pVM))
1317	{
1318	/* CPUID(0) */
1319	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1320	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1321	&& aHostRawStd[0].edx == aRawStd[0].edx,
1322	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1323	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1324	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1325	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1326	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1327	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1328
1329	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1330
1331	/* CPUID(1).eax */
1332	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1333	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1334	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1335
1336	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1337	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1338	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1339
1340	/* CPUID(1).ecx */
1341	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1342	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1343	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1344	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1345	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1346	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1347	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1348	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1349	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1350	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1351	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1352	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1353	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1354	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1355	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1356	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1357	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1358	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1359	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1360	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1361	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1362	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1363	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1364	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1365	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1366	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1367	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1368	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1369	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1370	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1371	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1372	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1373
1374	/* CPUID(1).edx */
1375	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1376	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1377	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1378	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1379	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1380	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1381	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1382	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1383	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1384	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1385	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1386	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1387	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1388	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1389	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1390	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1391	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1392	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1393	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1394	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1395	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1396	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1397	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1398	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1399	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1400	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1401	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1402	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1403	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1404	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1405	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1406	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1407
1408	/* CPUID(2) - config, mostly about caches. ignore. */
1409	/* CPUID(3) - processor serial number. ignore. */
1410	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1411	/* CPUID(5) - mwait/monitor config. ignore. */
1412	/* CPUID(6) - power management. ignore. */
1413	/* CPUID(7) - ???. ignore. */
1414	/* CPUID(8) - ???. ignore. */
1415	/* CPUID(9) - DCA. ignore for now. */
1416	/* CPUID(a) - PeMo info. ignore for now. */
1417	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1418
1419	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1420	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1421	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1422	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1423	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1424	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1425	{
1426	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1427	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1428	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1429	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1430	}
1431
1432	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1433	Note! Intel have/is marking many of the fields here as reserved. We
1434	will verify them as if it's an AMD CPU. */
1435	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1436	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1437	(N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1438	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1439	{
1440	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1441	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1442	&& aHostRawExt[0].edx == aRawExt[0].edx,
1443	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1444	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1445	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1446	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1447
1448	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1449	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1450	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1451	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1452	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1453	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1454
1455	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1456	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1457	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1458	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1459
1460	/* CPUID(0x80000001).ecx */
1461	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1462	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1463	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1464	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1465	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1466	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1467	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1468	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1469	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1470	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1471	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1472	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1473	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1474	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1475	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1476	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1477	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1478	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1479	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1480	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1481	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1482	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1483	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1484	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1485	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1486	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1487	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1488	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1489	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1490	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1491	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1492	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1493
1494	/* CPUID(0x80000001).edx */
1495	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1496	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1497	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1498	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1499	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1500	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1501	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1502	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1503	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1504	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1505	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1506	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1507	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1508	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1509	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1510	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1511	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1512	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1513	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1514	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1515	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1516	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1517	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1518	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1519	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1520	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1521	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1522	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1523	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1524	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1525	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1526	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1527
1528	/** @todo verify the rest as well. */
1529	}
1530	}
1531
1532
1533
1534	/*
1535	* Verify that we can support the features already exposed to the guest on
1536	* this host.
1537	*
1538	* Most of the features we're emulating requires intercepting instruction
1539	* and doing it the slow way, so there is no need to warn when they aren't
1540	* present in the host CPU. Thus we use IGN instead of EMU on these.
1541	*
1542	* Trailing comments:
1543	* "EMU" - Possible to emulate, could be lots of work and very slow.
1544	* "EMU?" - Can this be emulated?
1545	*/
1546	/* CPUID(1).ecx */
1547	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1548	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1549	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1550	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1551	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1552	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1553	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1554	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1555	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1556	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1557	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1558	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1559	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1560	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1561	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1562	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1563	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1564	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1565	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1566	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1567	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1568	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1569	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1570	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1571	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1572	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1573	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1574	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1575	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1576	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1577	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1578	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1579
1580	/* CPUID(1).edx */
1581	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1582	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1583	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1584	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1585	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1586	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1587	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1588	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1589	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1590	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1591	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1592	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1593	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1594	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1595	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1596	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1597	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1598	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1599	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1600	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1601	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1602	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1603	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1604	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1605	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1606	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1607	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1608	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1609	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1610	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1611	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1612	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1613
1614	/* CPUID(0x80000000). */
1615	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1616	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1617	{
1618	/** @todo deal with no 0x80000001 on the host. */
1619	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1620	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1621
1622	/* CPUID(0x80000001).ecx */
1623	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1624	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1625	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1626	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1627	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1628	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1629	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1630	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1631	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1632	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1633	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1634	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1635	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1636	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1637	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1638	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1639	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1640	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1641	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1642	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1643	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1644	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1645	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1646	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1647	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1648	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1649	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1650	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1651	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1652	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1653	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1654	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1655
1656	/* CPUID(0x80000001).edx */
1657	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1658	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1659	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1660	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1661	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1662	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1663	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1664	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1665	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1666	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1667	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1668	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1669	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1670	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1671	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1672	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1673	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1674	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1675	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1676	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1677	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1678	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1679	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1680	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1681	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1682	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1683	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1684	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1685	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1686	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1687	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1688	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1689	}
1690
1691	/*
1692	* We're good, commit the CPU ID leaves.
1693	*/
1694	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1695	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1696	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1697	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1698
1699	#undef CPUID_CHECK_RET
1700	#undef CPUID_CHECK_WRN
1701	#undef CPUID_CHECK2_RET
1702	#undef CPUID_CHECK2_WRN
1703	#undef CPUID_RAW_FEATURE_RET
1704	#undef CPUID_RAW_FEATURE_WRN
1705	#undef CPUID_RAW_FEATURE_IGN
1706	#undef CPUID_GST_FEATURE_RET
1707	#undef CPUID_GST_FEATURE_WRN
1708	#undef CPUID_GST_FEATURE_EMU
1709	#undef CPUID_GST_FEATURE_IGN
1710	#undef CPUID_GST_FEATURE2_RET
1711	#undef CPUID_GST_FEATURE2_WRN
1712	#undef CPUID_GST_FEATURE2_EMU
1713	#undef CPUID_GST_FEATURE2_IGN
1714	#undef CPUID_GST_AMD_FEATURE_RET
1715	#undef CPUID_GST_AMD_FEATURE_WRN
1716	#undef CPUID_GST_AMD_FEATURE_EMU
1717	#undef CPUID_GST_AMD_FEATURE_IGN
1718
1719	return VINF_SUCCESS;
1720	}
1721
1722
1723	/**
1724	* Pass 0 live exec callback.
1725	*
1726	* @returns VINF_SSM_DONT_CALL_AGAIN.
1727	* @param pVM The VM handle.
1728	* @param pSSM The saved state handle.
1729	* @param uPass The pass (0).
1730	*/
1731	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1732	{
1733	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1734	cpumR3SaveCpuId(pVM, pSSM);
1735	return VINF_SSM_DONT_CALL_AGAIN;
1736	}
1737
1738
1739	/**
1740	* Execute state save operation.
1741	*
1742	* @returns VBox status code.
1743	* @param pVM VM Handle.
1744	* @param pSSM SSM operation handle.
1745	*/
1746	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1747	{
1748	/*
1749	* Save.
1750	*/
1751	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1752	{
1753	PVMCPU pVCpu = &pVM->aCpus[i];
1754
1755	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1756	}
1757
1758	SSMR3PutU32(pSSM, pVM->cCpus);
1759	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1760	{
1761	PVMCPU pVCpu = &pVM->aCpus[i];
1762
1763	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1764	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1765	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1766	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1767	}
1768
1769	cpumR3SaveCpuId(pVM, pSSM);
1770	return VINF_SUCCESS;
1771	}
1772
1773
1774	/**
1775	* Load a version 1.6 CPUMCTX structure.
1776	*
1777	* @returns VBox status code.
1778	* @param pVM VM Handle.
1779	* @param pCpumctx16 Version 1.6 CPUMCTX
1780	*/
1781	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1782	{
1783	#define CPUMCTX16_LOADREG(RegName) \
1784	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1785
1786	#define CPUMCTX16_LOADDRXREG(RegName) \
1787	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1788
1789	#define CPUMCTX16_LOADHIDREG(RegName) \
1790	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1791	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1792	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1793
1794	#define CPUMCTX16_LOADSEGREG(RegName) \
1795	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1796	CPUMCTX16_LOADHIDREG(RegName);
1797
1798	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1799
1800	CPUMCTX16_LOADREG(rax);
1801	CPUMCTX16_LOADREG(rbx);
1802	CPUMCTX16_LOADREG(rcx);
1803	CPUMCTX16_LOADREG(rdx);
1804	CPUMCTX16_LOADREG(rdi);
1805	CPUMCTX16_LOADREG(rsi);
1806	CPUMCTX16_LOADREG(rbp);
1807	CPUMCTX16_LOADREG(esp);
1808	CPUMCTX16_LOADREG(rip);
1809	CPUMCTX16_LOADREG(rflags);
1810
1811	CPUMCTX16_LOADSEGREG(cs);
1812	CPUMCTX16_LOADSEGREG(ds);
1813	CPUMCTX16_LOADSEGREG(es);
1814	CPUMCTX16_LOADSEGREG(fs);
1815	CPUMCTX16_LOADSEGREG(gs);
1816	CPUMCTX16_LOADSEGREG(ss);
1817
1818	CPUMCTX16_LOADREG(r8);
1819	CPUMCTX16_LOADREG(r9);
1820	CPUMCTX16_LOADREG(r10);
1821	CPUMCTX16_LOADREG(r11);
1822	CPUMCTX16_LOADREG(r12);
1823	CPUMCTX16_LOADREG(r13);
1824	CPUMCTX16_LOADREG(r14);
1825	CPUMCTX16_LOADREG(r15);
1826
1827	CPUMCTX16_LOADREG(cr0);
1828	CPUMCTX16_LOADREG(cr2);
1829	CPUMCTX16_LOADREG(cr3);
1830	CPUMCTX16_LOADREG(cr4);
1831
1832	CPUMCTX16_LOADDRXREG(0);
1833	CPUMCTX16_LOADDRXREG(1);
1834	CPUMCTX16_LOADDRXREG(2);
1835	CPUMCTX16_LOADDRXREG(3);
1836	CPUMCTX16_LOADDRXREG(4);
1837	CPUMCTX16_LOADDRXREG(5);
1838	CPUMCTX16_LOADDRXREG(6);
1839	CPUMCTX16_LOADDRXREG(7);
1840
1841	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1842	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1843	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1844	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1845
1846	CPUMCTX16_LOADREG(ldtr);
1847	CPUMCTX16_LOADREG(tr);
1848
1849	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1850
1851	CPUMCTX16_LOADREG(msrEFER);
1852	CPUMCTX16_LOADREG(msrSTAR);
1853	CPUMCTX16_LOADREG(msrPAT);
1854	CPUMCTX16_LOADREG(msrLSTAR);
1855	CPUMCTX16_LOADREG(msrCSTAR);
1856	CPUMCTX16_LOADREG(msrSFMASK);
1857	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1858
1859	CPUMCTX16_LOADHIDREG(ldtr);
1860	CPUMCTX16_LOADHIDREG(tr);
1861
1862	#undef CPUMCTX16_LOADSEGREG
1863	#undef CPUMCTX16_LOADHIDREG
1864	#undef CPUMCTX16_LOADDRXREG
1865	#undef CPUMCTX16_LOADREG
1866	}
1867
1868
1869	/**
1870	* @copydoc FNSSMINTLOADPREP
1871	*/
1872	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1873	{
1874	pVM->cpum.s.fPendingRestore = true;
1875	return VINF_SUCCESS;
1876	}
1877
1878
1879	/**
1880	* @copydoc FNSSMINTLOADEXEC
1881	*/
1882	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1883	{
1884	/*
1885	* Validate version.
1886	*/
1887	if ( uVersion != CPUM_SAVED_STATE_VERSION
1888	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1889	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1890	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1891	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1892	{
1893	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1894	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1895	}
1896
1897	if (uPass == SSM_PASS_FINAL)
1898	{
1899	/*
1900	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1901	* really old SSM file versions.)
1902	*/
1903	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1904	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1905	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1906	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1907
1908	/*
1909	* Restore.
1910	*/
1911	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1912	{
1913	PVMCPU pVCpu = &pVM->aCpus[i];
1914	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1915	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1916
1917	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1918	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1919	pVCpu->cpum.s.Hyper.esp = uESP;
1920	}
1921
1922	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1923	{
1924	CPUMCTX_VER1_6 cpumctx16;
1925	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1926	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1927
1928	/* Save the old cpumctx state into the new one. */
1929	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1930
1931	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1932	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1933	}
1934	else
1935	{
1936	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1937	{
1938	uint32_t cCpus;
1939	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1940	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1941	VERR_SSM_UNEXPECTED_DATA);
1942	}
1943	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1944	\|\| pVM->cCpus == 1,
1945	("cCpus=%u\n", pVM->cCpus),
1946	VERR_SSM_UNEXPECTED_DATA);
1947
1948	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1949	{
1950	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1951	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1952	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1953	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1954	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1955	}
1956	}
1957	}
1958
1959	pVM->cpum.s.fPendingRestore = false;
1960
1961	/*
1962	* Guest CPUIDs.
1963	*/
1964	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1965	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1966
1967	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1968	* actually required. */
1969
1970	/*
1971	* Restore the CPUID leaves.
1972	*
1973	* Note that we support restoring less than the current amount of standard
1974	* leaves because we've been allowed more is newer version of VBox.
1975	*/
1976	uint32_t cElements;
1977	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1978	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1979	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1980	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1981
1982	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1983	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1984	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1985	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1986
1987	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1988	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1989	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1990	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1991
1992	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1993
1994	/*
1995	* Check that the basic cpuid id information is unchanged.
1996	*/
1997	/** @todo we should check the 64 bits capabilities too! */
1998	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
1999	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2000	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2001	uint32_t au32CpuIdSaved[8];
2002	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2003	if (RT_SUCCESS(rc))
2004	{
2005	/* Ignore CPU stepping. */
2006	au32CpuId[4] &= 0xfffffff0;
2007	au32CpuIdSaved[4] &= 0xfffffff0;
2008
2009	/* Ignore APIC ID (AMD specs). */
2010	au32CpuId[5] &= ~0xff000000;
2011	au32CpuIdSaved[5] &= ~0xff000000;
2012
2013	/* Ignore the number of Logical CPUs (AMD specs). */
2014	au32CpuId[5] &= ~0x00ff0000;
2015	au32CpuIdSaved[5] &= ~0x00ff0000;
2016
2017	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2018	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2019	\| X86_CPUID_FEATURE_ECX_VMX
2020	\| X86_CPUID_FEATURE_ECX_SMX
2021	\| X86_CPUID_FEATURE_ECX_EST
2022	\| X86_CPUID_FEATURE_ECX_TM2
2023	\| X86_CPUID_FEATURE_ECX_CNTXID
2024	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2025	\| X86_CPUID_FEATURE_ECX_PDCM
2026	\| X86_CPUID_FEATURE_ECX_DCA
2027	\| X86_CPUID_FEATURE_ECX_X2APIC
2028	);
2029	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2030	\| X86_CPUID_FEATURE_ECX_VMX
2031	\| X86_CPUID_FEATURE_ECX_SMX
2032	\| X86_CPUID_FEATURE_ECX_EST
2033	\| X86_CPUID_FEATURE_ECX_TM2
2034	\| X86_CPUID_FEATURE_ECX_CNTXID
2035	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2036	\| X86_CPUID_FEATURE_ECX_PDCM
2037	\| X86_CPUID_FEATURE_ECX_DCA
2038	\| X86_CPUID_FEATURE_ECX_X2APIC
2039	);
2040
2041	/* Make sure we don't forget to update the masks when enabling
2042	* features in the future.
2043	*/
2044	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2045	( X86_CPUID_FEATURE_ECX_DTES64
2046	\| X86_CPUID_FEATURE_ECX_VMX
2047	\| X86_CPUID_FEATURE_ECX_SMX
2048	\| X86_CPUID_FEATURE_ECX_EST
2049	\| X86_CPUID_FEATURE_ECX_TM2
2050	\| X86_CPUID_FEATURE_ECX_CNTXID
2051	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2052	\| X86_CPUID_FEATURE_ECX_PDCM
2053	\| X86_CPUID_FEATURE_ECX_DCA
2054	\| X86_CPUID_FEATURE_ECX_X2APIC
2055	)));
2056	/* do the compare */
2057	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2058	{
2059	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2060	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2061	"Saved=%.*Rhxs\n"
2062	"Real =%.*Rhxs\n",
2063	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2064	sizeof(au32CpuId), au32CpuId));
2065	else
2066	{
2067	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2068	"Saved=%.*Rhxs\n"
2069	"Real =%.*Rhxs\n",
2070	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2071	sizeof(au32CpuId), au32CpuId));
2072	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2073	}
2074	}
2075	}
2076
2077	return rc;
2078	}
2079
2080
2081	/**
2082	* @copydoc FNSSMINTLOADPREP
2083	*/
2084	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2085	{
2086	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2087	return VINF_SUCCESS;
2088
2089	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2090	if (pVM->cpum.s.fPendingRestore)
2091	{
2092	LogRel(("CPUM: Missing state!\n"));
2093	return VERR_INTERNAL_ERROR_2;
2094	}
2095
2096	return VINF_SUCCESS;
2097	}
2098
2099
2100	/**
2101	* Checks if the CPUM state restore is still pending.
2102	*
2103	* @returns true / false.
2104	* @param pVM The VM handle.
2105	*/
2106	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2107	{
2108	return pVM->cpum.s.fPendingRestore;
2109	}
2110
2111
2112	/**
2113	* Formats the EFLAGS value into mnemonics.
2114	*
2115	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2116	* @param efl The EFLAGS value.
2117	*/
2118	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2119	{
2120	/*
2121	* Format the flags.
2122	*/
2123	static const struct
2124	{
2125	const char pszSet; const char pszClear; uint32_t fFlag;
2126	} s_aFlags[] =
2127	{
2128	{ "vip",NULL, X86_EFL_VIP },
2129	{ "vif",NULL, X86_EFL_VIF },
2130	{ "ac", NULL, X86_EFL_AC },
2131	{ "vm", NULL, X86_EFL_VM },
2132	{ "rf", NULL, X86_EFL_RF },
2133	{ "nt", NULL, X86_EFL_NT },
2134	{ "ov", "nv", X86_EFL_OF },
2135	{ "dn", "up", X86_EFL_DF },
2136	{ "ei", "di", X86_EFL_IF },
2137	{ "tf", NULL, X86_EFL_TF },
2138	{ "nt", "pl", X86_EFL_SF },
2139	{ "nz", "zr", X86_EFL_ZF },
2140	{ "ac", "na", X86_EFL_AF },
2141	{ "po", "pe", X86_EFL_PF },
2142	{ "cy", "nc", X86_EFL_CF },
2143	};
2144	char *psz = pszEFlags;
2145	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2146	{
2147	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2148	if (pszAdd)
2149	{
2150	strcpy(psz, pszAdd);
2151	psz += strlen(pszAdd);
2152	*psz++ = ' ';
2153	}
2154	}
2155	psz[-1] = '\0';
2156	}
2157
2158
2159	/**
2160	* Formats a full register dump.
2161	*
2162	* @param pVM VM Handle.
2163	* @param pCtx The context to format.
2164	* @param pCtxCore The context core to format.
2165	* @param pHlp Output functions.
2166	* @param enmType The dump type.
2167	* @param pszPrefix Register name prefix.
2168	*/
2169	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2170	{
2171	/*
2172	* Format the EFLAGS.
2173	*/
2174	uint32_t efl = pCtxCore->eflags.u32;
2175	char szEFlags[80];
2176	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2177
2178	/*
2179	* Format the registers.
2180	*/
2181	switch (enmType)
2182	{
2183	case CPUMDUMPTYPE_TERSE:
2184	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2185	pHlp->pfnPrintf(pHlp,
2186	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2187	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2188	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2189	"%sr14=%016RX64 %sr15=%016RX64\n"
2190	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2191	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2192	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2193	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2194	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2195	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2196	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2197	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2198	else
2199	pHlp->pfnPrintf(pHlp,
2200	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2201	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2202	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2203	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2204	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2205	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2206	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2207	break;
2208
2209	case CPUMDUMPTYPE_DEFAULT:
2210	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2211	pHlp->pfnPrintf(pHlp,
2212	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2213	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2214	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2215	"%sr14=%016RX64 %sr15=%016RX64\n"
2216	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2217	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2218	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2219	,
2220	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2221	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2222	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2223	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2224	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2225	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2226	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2227	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2228	else
2229	pHlp->pfnPrintf(pHlp,
2230	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2231	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2232	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2233	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2234	,
2235	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2236	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2237	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2238	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2239	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2240	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2241	break;
2242
2243	case CPUMDUMPTYPE_VERBOSE:
2244	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2245	pHlp->pfnPrintf(pHlp,
2246	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2247	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2248	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2249	"%sr14=%016RX64 %sr15=%016RX64\n"
2250	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2251	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2252	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2253	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2254	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2255	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2256	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2257	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2258	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2259	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2260	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2261	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2262	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2263	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2264	,
2265	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2266	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2267	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2268	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2269	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2270	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2271	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2272	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2273	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2274	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2275	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2276	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2277	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2278	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2279	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2280	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2281	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2282	else
2283	pHlp->pfnPrintf(pHlp,
2284	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2285	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2286	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2287	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2288	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2289	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2290	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2291	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2292	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2293	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2294	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2295	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2296	,
2297	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2298	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2299	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2300	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2301	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2302	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2303	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2304	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2305	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2306	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2307	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2308	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2309
2310	pHlp->pfnPrintf(pHlp,
2311	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2312	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2313	,
2314	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2315	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2316	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2317	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2318	);
2319	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2320	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2321	{
2322	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2323	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2324	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2325	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2326	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2327	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2328	/** @todo This isn't entirenly correct and needs more work! */
2329	pHlp->pfnPrintf(pHlp,
2330	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2331	pszPrefix, iST, pszPrefix, iFPR,
2332	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2333	uTag, chSign, iInteger, u64Fraction, uExponent);
2334	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2335	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2336	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2337	else
2338	pHlp->pfnPrintf(pHlp, "\n");
2339	}
2340	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2341	pHlp->pfnPrintf(pHlp,
2342	iXMM & 1
2343	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2344	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2345	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2346	pCtx->fpu.aXMM[iXMM].au32[3],
2347	pCtx->fpu.aXMM[iXMM].au32[2],
2348	pCtx->fpu.aXMM[iXMM].au32[1],
2349	pCtx->fpu.aXMM[iXMM].au32[0]);
2350	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2351	if (pCtx->fpu.au32RsrvdRest[i])
2352	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2353	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2354
2355	pHlp->pfnPrintf(pHlp,
2356	"%sEFER =%016RX64\n"
2357	"%sPAT =%016RX64\n"
2358	"%sSTAR =%016RX64\n"
2359	"%sCSTAR =%016RX64\n"
2360	"%sLSTAR =%016RX64\n"
2361	"%sSFMASK =%016RX64\n"
2362	"%sKERNELGSBASE =%016RX64\n",
2363	pszPrefix, pCtx->msrEFER,
2364	pszPrefix, pCtx->msrPAT,
2365	pszPrefix, pCtx->msrSTAR,
2366	pszPrefix, pCtx->msrCSTAR,
2367	pszPrefix, pCtx->msrLSTAR,
2368	pszPrefix, pCtx->msrSFMASK,
2369	pszPrefix, pCtx->msrKERNELGSBASE);
2370	break;
2371	}
2372	}
2373
2374
2375	/**
2376	* Display all cpu states and any other cpum info.
2377	*
2378	* @param pVM VM Handle.
2379	* @param pHlp The info helper functions.
2380	* @param pszArgs Arguments, ignored.
2381	*/
2382	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2383	{
2384	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2385	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2386	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2387	cpumR3InfoHost(pVM, pHlp, pszArgs);
2388	}
2389
2390
2391	/**
2392	* Parses the info argument.
2393	*
2394	* The argument starts with 'verbose', 'terse' or 'default' and then
2395	* continues with the comment string.
2396	*
2397	* @param pszArgs The pointer to the argument string.
2398	* @param penmType Where to store the dump type request.
2399	* @param ppszComment Where to store the pointer to the comment string.
2400	*/
2401	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2402	{
2403	if (!pszArgs)
2404	{
2405	*penmType = CPUMDUMPTYPE_DEFAULT;
2406	*ppszComment = "";
2407	}
2408	else
2409	{
2410	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2411	{
2412	pszArgs += 5;
2413	*penmType = CPUMDUMPTYPE_VERBOSE;
2414	}
2415	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2416	{
2417	pszArgs += 5;
2418	*penmType = CPUMDUMPTYPE_TERSE;
2419	}
2420	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2421	{
2422	pszArgs += 7;
2423	*penmType = CPUMDUMPTYPE_DEFAULT;
2424	}
2425	else
2426	*penmType = CPUMDUMPTYPE_DEFAULT;
2427	*ppszComment = RTStrStripL(pszArgs);
2428	}
2429	}
2430
2431
2432	/**
2433	* Display the guest cpu state.
2434	*
2435	* @param pVM VM Handle.
2436	* @param pHlp The info helper functions.
2437	* @param pszArgs Arguments, ignored.
2438	*/
2439	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2440	{
2441	CPUMDUMPTYPE enmType;
2442	const char *pszComment;
2443	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2444
2445	/* @todo SMP support! */
2446	PVMCPU pVCpu = VMMGetCpu(pVM);
2447	if (!pVCpu)
2448	pVCpu = &pVM->aCpus[0];
2449
2450	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2451
2452	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2453	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2454	}
2455
2456
2457	/**
2458	* Display the current guest instruction
2459	*
2460	* @param pVM VM Handle.
2461	* @param pHlp The info helper functions.
2462	* @param pszArgs Arguments, ignored.
2463	*/
2464	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2465	{
2466	char szInstruction[256];
2467	/* @todo SMP support! */
2468	PVMCPU pVCpu = VMMGetCpu(pVM);
2469	if (!pVCpu)
2470	pVCpu = &pVM->aCpus[0];
2471
2472	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2473	if (RT_SUCCESS(rc))
2474	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2475	}
2476
2477
2478	/**
2479	* Display the hypervisor cpu state.
2480	*
2481	* @param pVM VM Handle.
2482	* @param pHlp The info helper functions.
2483	* @param pszArgs Arguments, ignored.
2484	*/
2485	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2486	{
2487	CPUMDUMPTYPE enmType;
2488	const char *pszComment;
2489	/* @todo SMP */
2490	PVMCPU pVCpu = &pVM->aCpus[0];
2491
2492	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2493	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2494	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2495	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2496	}
2497
2498
2499	/**
2500	* Display the host cpu state.
2501	*
2502	* @param pVM VM Handle.
2503	* @param pHlp The info helper functions.
2504	* @param pszArgs Arguments, ignored.
2505	*/
2506	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2507	{
2508	CPUMDUMPTYPE enmType;
2509	const char *pszComment;
2510	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2511	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2512
2513	/*
2514	* Format the EFLAGS.
2515	*/
2516	/* @todo SMP */
2517	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2518	#if HC_ARCH_BITS == 32
2519	uint32_t efl = pCtx->eflags.u32;
2520	#else
2521	uint64_t efl = pCtx->rflags;
2522	#endif
2523	char szEFlags[80];
2524	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2525
2526	/*
2527	* Format the registers.
2528	*/
2529	#if HC_ARCH_BITS == 32
2530	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2531	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2532	# endif
2533	{
2534	pHlp->pfnPrintf(pHlp,
2535	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2536	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2537	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2538	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2539	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2540	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2541	,
2542	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2543	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2544	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2545	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2546	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2547	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2548	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2549	}
2550	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2551	else
2552	# endif
2553	#endif
2554	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2555	{
2556	pHlp->pfnPrintf(pHlp,
2557	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2558	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2559	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2560	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2561	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2562	"r14=%016RX64 r15=%016RX64\n"
2563	"iopl=%d %31s\n"
2564	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2565	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2566	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2567	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2568	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2569	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2570	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2571	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2572	,
2573	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2574	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2575	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2576	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2577	pCtx->r11, pCtx->r12, pCtx->r13,
2578	pCtx->r14, pCtx->r15,
2579	X86_EFL_GET_IOPL(efl), szEFlags,
2580	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2581	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2582	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2583	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2584	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2585	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2586	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2587	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2588	}
2589	#endif
2590	}
2591
2592
2593	/**
2594	* Get L1 cache / TLS associativity.
2595	*/
2596	static const char getCacheAss(unsigned u, char pszBuf)
2597	{
2598	if (u == 0)
2599	return "res0 ";
2600	if (u == 1)
2601	return "direct";
2602	if (u >= 256)
2603	return "???";
2604
2605	RTStrPrintf(pszBuf, 16, "%d way", u);
2606	return pszBuf;
2607	}
2608
2609
2610	/**
2611	* Get L2 cache soociativity.
2612	*/
2613	const char *getL2CacheAss(unsigned u)
2614	{
2615	switch (u)
2616	{
2617	case 0: return "off ";
2618	case 1: return "direct";
2619	case 2: return "2 way ";
2620	case 3: return "res3 ";
2621	case 4: return "4 way ";
2622	case 5: return "res5 ";
2623	case 6: return "8 way "; case 7: return "res7 ";
2624	case 8: return "16 way";
2625	case 9: return "res9 ";
2626	case 10: return "res10 ";
2627	case 11: return "res11 ";
2628	case 12: return "res12 ";
2629	case 13: return "res13 ";
2630	case 14: return "res14 ";
2631	case 15: return "fully ";
2632	default:
2633	return "????";
2634	}
2635	}
2636
2637
2638	/**
2639	* Display the guest CpuId leaves.
2640	*
2641	* @param pVM VM Handle.
2642	* @param pHlp The info helper functions.
2643	* @param pszArgs "terse", "default" or "verbose".
2644	*/
2645	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2646	{
2647	/*
2648	* Parse the argument.
2649	*/
2650	unsigned iVerbosity = 1;
2651	if (pszArgs)
2652	{
2653	pszArgs = RTStrStripL(pszArgs);
2654	if (!strcmp(pszArgs, "terse"))
2655	iVerbosity--;
2656	else if (!strcmp(pszArgs, "verbose"))
2657	iVerbosity++;
2658	}
2659
2660	/*
2661	* Start cracking.
2662	*/
2663	CPUMCPUID Host;
2664	CPUMCPUID Guest;
2665	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2666
2667	pHlp->pfnPrintf(pHlp,
2668	" RAW Standard CPUIDs\n"
2669	" Function eax ebx ecx edx\n");
2670	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2671	{
2672	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2673	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2674
2675	pHlp->pfnPrintf(pHlp,
2676	"Gst: %08x %08x %08x %08x %08x%s\n"
2677	"Hst: %08x %08x %08x %08x\n",
2678	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2679	i <= cStdMax ? "" : "*",
2680	Host.eax, Host.ebx, Host.ecx, Host.edx);
2681	}
2682
2683	/*
2684	* If verbose, decode it.
2685	*/
2686	if (iVerbosity)
2687	{
2688	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2689	pHlp->pfnPrintf(pHlp,
2690	"Name: %.04s%.04s%.04s\n"
2691	"Supports: 0-%x\n",
2692	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2693	}
2694
2695	/*
2696	* Get Features.
2697	*/
2698	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2699	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2700	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2701	if (cStdMax >= 1 && iVerbosity)
2702	{
2703	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2704	uint32_t uEAX = Guest.eax;
2705
2706	pHlp->pfnPrintf(pHlp,
2707	"Family: %d \tExtended: %d \tEffective: %d\n"
2708	"Model: %d \tExtended: %d \tEffective: %d\n"
2709	"Stepping: %d\n"
2710	"Type: %d\n"
2711	"APIC ID: %#04x\n"
2712	"Logical CPUs: %d\n"
2713	"CLFLUSH Size: %d\n"
2714	"Brand ID: %#04x\n",
2715	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2716	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2717	ASMGetCpuStepping(uEAX),
2718	(uEAX >> 12) & 3,
2719	(Guest.ebx >> 24) & 0xff,
2720	(Guest.ebx >> 16) & 0xff,
2721	(Guest.ebx >> 8) & 0xff,
2722	(Guest.ebx >> 0) & 0xff);
2723	if (iVerbosity == 1)
2724	{
2725	uint32_t uEDX = Guest.edx;
2726	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2727	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2728	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2729	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2730	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2731	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2732	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2733	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2734	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2735	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2736	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2737	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2738	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2739	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2740	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2741	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2742	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2743	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2744	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2745	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2746	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2747	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2748	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2749	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2750	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2751	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2752	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2753	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2754	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2755	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2756	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2757	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2758	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2759	pHlp->pfnPrintf(pHlp, "\n");
2760
2761	uint32_t uECX = Guest.ecx;
2762	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2763	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2764	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2765	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2766	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2767	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2768	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2769	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2770	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2771	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2772	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2773	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2774	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2775	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2776	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2777	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2778	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2779	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2780	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2781	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2782	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2783	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2784	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2785	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2786	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2787	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2788	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2789	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2790	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2791	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2792	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2793	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2794	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2795	pHlp->pfnPrintf(pHlp, "\n");
2796	}
2797	else
2798	{
2799	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2800
2801	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2802	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2803	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2804	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2805
2806	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2807	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2808	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2809	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2810	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2811	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2812	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2813	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2814	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2815	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2816	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2817	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2818	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2819	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2820	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2821	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2822	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2823	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2824	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2825	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2826	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2827	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2828	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2829	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2830	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2831	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2832	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2833	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2834	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2835	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2836	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2837	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2838	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2839
2840	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2841	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2842	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2843	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2844	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2845	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2846	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2847	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2848	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2849	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2850	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2851	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2852	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2853	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2854	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2855	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2856	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2857	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2858	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2859	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2860	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2861	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2862	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2863	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2864	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2865	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2866	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2867	}
2868	}
2869	if (cStdMax >= 2 && iVerbosity)
2870	{
2871	/** @todo */
2872	}
2873
2874	/*
2875	* Extended.
2876	* Implemented after AMD specs.
2877	*/
2878	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2879
2880	pHlp->pfnPrintf(pHlp,
2881	"\n"
2882	" RAW Extended CPUIDs\n"
2883	" Function eax ebx ecx edx\n");
2884	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2885	{
2886	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2887	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2888
2889	pHlp->pfnPrintf(pHlp,
2890	"Gst: %08x %08x %08x %08x %08x%s\n"
2891	"Hst: %08x %08x %08x %08x\n",
2892	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2893	i <= cExtMax ? "" : "*",
2894	Host.eax, Host.ebx, Host.ecx, Host.edx);
2895	}
2896
2897	/*
2898	* Understandable output
2899	*/
2900	if (iVerbosity)
2901	{
2902	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2903	pHlp->pfnPrintf(pHlp,
2904	"Ext Name: %.4s%.4s%.4s\n"
2905	"Ext Supports: 0x80000000-%#010x\n",
2906	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2907	}
2908
2909	if (iVerbosity && cExtMax >= 1)
2910	{
2911	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2912	uint32_t uEAX = Guest.eax;
2913	pHlp->pfnPrintf(pHlp,
2914	"Family: %d \tExtended: %d \tEffective: %d\n"
2915	"Model: %d \tExtended: %d \tEffective: %d\n"
2916	"Stepping: %d\n"
2917	"Brand ID: %#05x\n",
2918	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2919	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2920	ASMGetCpuStepping(uEAX),
2921	Guest.ebx & 0xfff);
2922
2923	if (iVerbosity == 1)
2924	{
2925	uint32_t uEDX = Guest.edx;
2926	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2927	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2928	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2929	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2930	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2931	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2932	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2933	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2934	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2935	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2936	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2937	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2938	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2939	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2940	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2941	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2942	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2943	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2944	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2945	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2946	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2947	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2948	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2949	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2950	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2951	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2952	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2953	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2954	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2955	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2956	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2957	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2958	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2959	pHlp->pfnPrintf(pHlp, "\n");
2960
2961	uint32_t uECX = Guest.ecx;
2962	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2963	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2964	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2965	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2966	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2967	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2968	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2969	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2970	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2971	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2972	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2973	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2974	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2975	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2976	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2977	for (unsigned iBit = 5; iBit < 32; iBit++)
2978	if (uECX & RT_BIT(iBit))
2979	pHlp->pfnPrintf(pHlp, " %d", iBit);
2980	pHlp->pfnPrintf(pHlp, "\n");
2981	}
2982	else
2983	{
2984	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2985
2986	uint32_t uEdxGst = Guest.edx;
2987	uint32_t uEdxHst = Host.edx;
2988	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2989	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2990	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2991	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2992	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2993	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2994	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2995	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2996	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2997	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2998	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2999	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3000	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3001	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3002	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3003	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3004	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3005	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3006	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3007	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3008	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3009	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3010	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3011	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3012	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3013	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3014	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3015	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3016	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3017	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3018	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3019	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3020	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3021
3022	uint32_t uEcxGst = Guest.ecx;
3023	uint32_t uEcxHst = Host.ecx;
3024	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3025	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3026	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3027	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3028	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3029	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3030	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3031	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3032	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3033	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3034	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3035	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3036	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3037	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3038	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3039	}
3040	}
3041
3042	if (iVerbosity && cExtMax >= 2)
3043	{
3044	char szString[443+1] = {0};
3045	uint32_t pu32 = (uint32_t )szString;
3046	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3047	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3048	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3049	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3050	if (cExtMax >= 3)
3051	{
3052	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3053	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3054	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3055	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3056	}
3057	if (cExtMax >= 4)
3058	{
3059	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3060	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3061	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3062	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3063	}
3064	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3065	}
3066
3067	if (iVerbosity && cExtMax >= 5)
3068	{
3069	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3070	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3071	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3072	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3073	char sz1[32];
3074	char sz2[32];
3075
3076	pHlp->pfnPrintf(pHlp,
3077	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3078	"TLB 2/4M Data: %s %3d entries\n",
3079	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3080	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3081	pHlp->pfnPrintf(pHlp,
3082	"TLB 4K Instr/Uni: %s %3d entries\n"
3083	"TLB 4K Data: %s %3d entries\n",
3084	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3085	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3086	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3087	"L1 Instr Cache Lines Per Tag: %d\n"
3088	"L1 Instr Cache Associativity: %s\n"
3089	"L1 Instr Cache Size: %d KB\n",
3090	(uEDX >> 0) & 0xff,
3091	(uEDX >> 8) & 0xff,
3092	getCacheAss((uEDX >> 16) & 0xff, sz1),
3093	(uEDX >> 24) & 0xff);
3094	pHlp->pfnPrintf(pHlp,
3095	"L1 Data Cache Line Size: %d bytes\n"
3096	"L1 Data Cache Lines Per Tag: %d\n"
3097	"L1 Data Cache Associativity: %s\n"
3098	"L1 Data Cache Size: %d KB\n",
3099	(uECX >> 0) & 0xff,
3100	(uECX >> 8) & 0xff,
3101	getCacheAss((uECX >> 16) & 0xff, sz1),
3102	(uECX >> 24) & 0xff);
3103	}
3104
3105	if (iVerbosity && cExtMax >= 6)
3106	{
3107	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3108	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3109	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3110
3111	pHlp->pfnPrintf(pHlp,
3112	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3113	"L2 TLB 2/4M Data: %s %4d entries\n",
3114	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3115	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3116	pHlp->pfnPrintf(pHlp,
3117	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3118	"L2 TLB 4K Data: %s %4d entries\n",
3119	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3120	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3121	pHlp->pfnPrintf(pHlp,
3122	"L2 Cache Line Size: %d bytes\n"
3123	"L2 Cache Lines Per Tag: %d\n"
3124	"L2 Cache Associativity: %s\n"
3125	"L2 Cache Size: %d KB\n",
3126	(uEDX >> 0) & 0xff,
3127	(uEDX >> 8) & 0xf,
3128	getL2CacheAss((uEDX >> 12) & 0xf),
3129	(uEDX >> 16) & 0xffff);
3130	}
3131
3132	if (iVerbosity && cExtMax >= 7)
3133	{
3134	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3135
3136	pHlp->pfnPrintf(pHlp, "APM Features: ");
3137	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3138	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3139	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3140	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3141	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3142	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3143	for (unsigned iBit = 6; iBit < 32; iBit++)
3144	if (uEDX & RT_BIT(iBit))
3145	pHlp->pfnPrintf(pHlp, " %d", iBit);
3146	pHlp->pfnPrintf(pHlp, "\n");
3147	}
3148
3149	if (iVerbosity && cExtMax >= 8)
3150	{
3151	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3152	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3153
3154	pHlp->pfnPrintf(pHlp,
3155	"Physical Address Width: %d bits\n"
3156	"Virtual Address Width: %d bits\n",
3157	(uEAX >> 0) & 0xff,
3158	(uEAX >> 8) & 0xff);
3159	pHlp->pfnPrintf(pHlp,
3160	"Physical Core Count: %d\n",
3161	(uECX >> 0) & 0xff);
3162	}
3163
3164
3165	/*
3166	* Centaur.
3167	*/
3168	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3169
3170	pHlp->pfnPrintf(pHlp,
3171	"\n"
3172	" RAW Centaur CPUIDs\n"
3173	" Function eax ebx ecx edx\n");
3174	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3175	{
3176	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3177	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3178
3179	pHlp->pfnPrintf(pHlp,
3180	"Gst: %08x %08x %08x %08x %08x%s\n"
3181	"Hst: %08x %08x %08x %08x\n",
3182	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3183	i <= cCentaurMax ? "" : "*",
3184	Host.eax, Host.ebx, Host.ecx, Host.edx);
3185	}
3186
3187	/*
3188	* Understandable output
3189	*/
3190	if (iVerbosity)
3191	{
3192	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3193	pHlp->pfnPrintf(pHlp,
3194	"Centaur Supports: 0xc0000000-%#010x\n",
3195	Guest.eax);
3196	}
3197
3198	if (iVerbosity && cCentaurMax >= 1)
3199	{
3200	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3201	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3202	uint32_t uEdxHst = Host.edx;
3203
3204	if (iVerbosity == 1)
3205	{
3206	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3207	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3208	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3209	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3210	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3211	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3212	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3213	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3214	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3215	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3216	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3217	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3218	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3219	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3220	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3221	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3222	for (unsigned iBit = 14; iBit < 32; iBit++)
3223	if (uEdxGst & RT_BIT(iBit))
3224	pHlp->pfnPrintf(pHlp, " %d", iBit);
3225	pHlp->pfnPrintf(pHlp, "\n");
3226	}
3227	else
3228	{
3229	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3230	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3231	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3232	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3233	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3234	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3235	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3236	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3237	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3238	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3239	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3240	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3241	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3242	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3243	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3244	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3245	for (unsigned iBit = 14; iBit < 32; iBit++)
3246	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3247	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3248	pHlp->pfnPrintf(pHlp, "\n");
3249	}
3250	}
3251	}
3252
3253
3254	/**
3255	* Structure used when disassembling and instructions in DBGF.
3256	* This is used so the reader function can get the stuff it needs.
3257	*/
3258	typedef struct CPUMDISASSTATE
3259	{
3260	/** Pointer to the CPU structure. */
3261	PDISCPUSTATE pCpu;
3262	/** The VM handle. */
3263	PVM pVM;
3264	/** The VMCPU handle. */
3265	PVMCPU pVCpu;
3266	/** Pointer to the first byte in the segemnt. */
3267	RTGCUINTPTR GCPtrSegBase;
3268	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3269	RTGCUINTPTR GCPtrSegEnd;
3270	/** The size of the segment minus 1. */
3271	RTGCUINTPTR cbSegLimit;
3272	/** Pointer to the current page - R3 Ptr. */
3273	void const *pvPageR3;
3274	/** Pointer to the current page - GC Ptr. */
3275	RTGCPTR pvPageGC;
3276	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3277	PGMPAGEMAPLOCK PageMapLock;
3278	/** Whether the PageMapLock is valid or not. */
3279	bool fLocked;
3280	/** 64 bits mode or not. */
3281	bool f64Bits;
3282	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3283
3284
3285	/**
3286	* Instruction reader.
3287	*
3288	* @returns VBox status code.
3289	* @param PtrSrc Address to read from.
3290	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3291	* @param pu8Dst Where to store the bytes.
3292	* @param cbRead Number of bytes to read.
3293	* @param uDisCpu Pointer to the disassembler cpu state.
3294	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3295	*/
3296	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3297	{
3298	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3299	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3300	Assert(cbRead > 0);
3301	for (;;)
3302	{
3303	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3304
3305	/* Need to update the page translation? */
3306	if ( !pState->pvPageR3
3307	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3308	{
3309	int rc = VINF_SUCCESS;
3310
3311	/* translate the address */
3312	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3313	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3314	&& !HWACCMIsEnabled(pState->pVM))
3315	{
3316	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3317	if (!pState->pvPageR3)
3318	rc = VERR_INVALID_POINTER;
3319	}
3320	else
3321	{
3322	/* Release mapping lock previously acquired. */
3323	if (pState->fLocked)
3324	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3325	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3326	pState->fLocked = RT_SUCCESS_NP(rc);
3327	}
3328	if (RT_FAILURE(rc))
3329	{
3330	pState->pvPageR3 = NULL;
3331	return rc;
3332	}
3333	}
3334
3335	/* check the segemnt limit */
3336	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3337	return VERR_OUT_OF_SELECTOR_BOUNDS;
3338
3339	/* calc how much we can read */
3340	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3341	if (!pState->f64Bits)
3342	{
3343	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3344	if (cb > cbSeg && cbSeg)
3345	cb = cbSeg;
3346	}
3347	if (cb > cbRead)
3348	cb = cbRead;
3349
3350	/* read and advance */
3351	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3352	cbRead -= cb;
3353	if (!cbRead)
3354	return VINF_SUCCESS;
3355	pu8Dst += cb;
3356	PtrSrc += cb;
3357	}
3358	}
3359
3360
3361	/**
3362	* Disassemble an instruction and return the information in the provided structure.
3363	*
3364	* @returns VBox status code.
3365	* @param pVM VM Handle
3366	* @param pVCpu VMCPU Handle
3367	* @param pCtx CPU context
3368	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3369	* @param pCpu Disassembly state
3370	* @param pszPrefix String prefix for logging (debug only)
3371	*
3372	*/
3373	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3374	{
3375	CPUMDISASSTATE State;
3376	int rc;
3377
3378	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3379	State.pCpu = pCpu;
3380	State.pvPageGC = 0;
3381	State.pvPageR3 = NULL;
3382	State.pVM = pVM;
3383	State.pVCpu = pVCpu;
3384	State.fLocked = false;
3385	State.f64Bits = false;
3386
3387	/*
3388	* Get selector information.
3389	*/
3390	if ( (pCtx->cr0 & X86_CR0_PE)
3391	&& pCtx->eflags.Bits.u1VM == 0)
3392	{
3393	if (CPUMAreHiddenSelRegsValid(pVM))
3394	{
3395	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3396	State.GCPtrSegBase = pCtx->csHid.u64Base;
3397	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3398	State.cbSegLimit = pCtx->csHid.u32Limit;
3399	pCpu->mode = (State.f64Bits)
3400	? CPUMODE_64BIT
3401	: pCtx->csHid.Attr.n.u1DefBig
3402	? CPUMODE_32BIT
3403	: CPUMODE_16BIT;
3404	}
3405	else
3406	{
3407	DBGFSELINFO SelInfo;
3408
3409	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3410	if (RT_FAILURE(rc))
3411	{
3412	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3413	return rc;
3414	}
3415
3416	/*
3417	* Validate the selector.
3418	*/
3419	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3420	if (RT_FAILURE(rc))
3421	{
3422	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3423	return rc;
3424	}
3425	State.GCPtrSegBase = SelInfo.GCPtrBase;
3426	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3427	State.cbSegLimit = SelInfo.cbLimit;
3428	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3429	}
3430	}
3431	else
3432	{
3433	/* real or V86 mode */
3434	pCpu->mode = CPUMODE_16BIT;
3435	State.GCPtrSegBase = pCtx->cs * 16;
3436	State.GCPtrSegEnd = 0xFFFFFFFF;
3437	State.cbSegLimit = 0xFFFFFFFF;
3438	}
3439
3440	/*
3441	* Disassemble the instruction.
3442	*/
3443	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3444	pCpu->apvUserData[0] = &State;
3445
3446	uint32_t cbInstr;
3447	#ifndef LOG_ENABLED
3448	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3449	if (RT_SUCCESS(rc))
3450	{
3451	#else
3452	char szOutput[160];
3453	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3454	if (RT_SUCCESS(rc))
3455	{
3456	/* log it */
3457	if (pszPrefix)
3458	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3459	else
3460	Log(("%s", szOutput));
3461	#endif
3462	rc = VINF_SUCCESS;
3463	}
3464	else
3465	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3466
3467	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3468	if (State.fLocked)
3469	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3470
3471	return rc;
3472	}
3473
3474	#ifdef DEBUG
3475
3476	/**
3477	* Disassemble an instruction and dump it to the log
3478	*
3479	* @returns VBox status code.
3480	* @param pVM VM Handle
3481	* @param pVCpu VMCPU Handle
3482	* @param pCtx CPU context
3483	* @param pc GC instruction pointer
3484	* @param pszPrefix String prefix for logging
3485	*
3486	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3487	*/
3488	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3489	{
3490	DISCPUSTATE Cpu;
3491	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3492	}
3493
3494
3495	/**
3496	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3497	*
3498	* @internal
3499	*/
3500	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3501	{
3502	/** @todo SMP support!! */
3503	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3504	}
3505
3506	#endif /* DEBUG */
3507
3508	/**
3509	* API for controlling a few of the CPU features found in CR4.
3510	*
3511	* Currently only X86_CR4_TSD is accepted as input.
3512	*
3513	* @returns VBox status code.
3514	*
3515	* @param pVM The VM handle.
3516	* @param fOr The CR4 OR mask.
3517	* @param fAnd The CR4 AND mask.
3518	*/
3519	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3520	{
3521	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3522	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3523
3524	pVM->cpum.s.CR4.OrMask &= fAnd;
3525	pVM->cpum.s.CR4.OrMask \|= fOr;
3526
3527	return VINF_SUCCESS;
3528	}
3529
3530
3531	/**
3532	* Gets a pointer to the array of standard CPUID leaves.
3533	*
3534	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3535	*
3536	* @returns Pointer to the standard CPUID leaves (read-only).
3537	* @param pVM The VM handle.
3538	* @remark Intended for PATM.
3539	*/
3540	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3541	{
3542	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3543	}
3544
3545
3546	/**
3547	* Gets a pointer to the array of extended CPUID leaves.
3548	*
3549	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3550	*
3551	* @returns Pointer to the extended CPUID leaves (read-only).
3552	* @param pVM The VM handle.
3553	* @remark Intended for PATM.
3554	*/
3555	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3556	{
3557	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3558	}
3559
3560
3561	/**
3562	* Gets a pointer to the array of centaur CPUID leaves.
3563	*
3564	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3565	*
3566	* @returns Pointer to the centaur CPUID leaves (read-only).
3567	* @param pVM The VM handle.
3568	* @remark Intended for PATM.
3569	*/
3570	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3571	{
3572	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3573	}
3574
3575
3576	/**
3577	* Gets a pointer to the default CPUID leaf.
3578	*
3579	* @returns Pointer to the default CPUID leaf (read-only).
3580	* @param pVM The VM handle.
3581	* @remark Intended for PATM.
3582	*/
3583	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3584	{
3585	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3586	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 26646

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