| 1 | ; $Id: feclearexcept.asm 96205 2022-08-14 23:40:55Z vboxsync $
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| 2 | ;; @file
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| 3 | ; IPRT - No-CRT feclearexcept - AMD64 & X86.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2022 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.alldomusa.eu.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 | ; The contents of this file may alternatively be used under the terms
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| 18 | ; of the Common Development and Distribution License Version 1.0
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| 19 | ; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | ; VirtualBox OSE distribution, in which case the provisions of the
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| 21 | ; CDDL are applicable instead of those of the GPL.
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| 22 | ;
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| 23 | ; You may elect to license modified versions of this file under the
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| 24 | ; terms and conditions of either the GPL or the CDDL or both.
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| 25 | ;
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| 26 |
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| 27 |
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| 28 | %define RT_ASM_WITH_SEH64
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| 29 | %include "iprt/asmdefs.mac"
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| 30 | %include "iprt/x86.mac"
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| 31 |
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| 32 |
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| 33 | BEGINCODE
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| 34 |
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| 35 | ;;
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| 36 | ; Sets the hardware rounding mode.
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| 37 | ;
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| 38 | ; @returns eax = 0 on success, non-zero on failure.
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| 39 | ; @param fXcpts 32-bit: [xBP+8] msc64: ecx gcc64: edi - X86_FSW_XCPT_MASK
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| 40 | ;
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| 41 | RT_NOCRT_BEGINPROC feclearexcept
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| 42 | push xBP
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| 43 | SEH64_PUSH_xBP
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| 44 | mov xBP, xSP
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| 45 | SEH64_SET_FRAME_xBP 0
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| 46 | sub xSP, 20h
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| 47 | SEH64_ALLOCATE_STACK 20h
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| 48 | SEH64_END_PROLOGUE
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| 49 |
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| 50 | ;
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| 51 | ; Load the parameter into ecx.
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| 52 | ;
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| 53 | %ifdef ASM_CALL64_GCC
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| 54 | mov ecx, edi
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| 55 | %elifdef RT_ARCH_X86
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| 56 | mov ecx, [xBP + xCB*2]
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| 57 | %endif
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| 58 | %if 0
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| 59 | and ecx, X86_FSW_XCPT_MASK
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| 60 | %else
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| 61 | or eax, -1
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| 62 | test ecx, ~X86_FSW_XCPT_MASK
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| 63 | jnz .return
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| 64 | %endif
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| 65 |
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| 66 | ; Make it into and AND mask suitable for clearing the specified exceptions.
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| 67 | not ecx
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| 68 |
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| 69 | ;
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| 70 | ; Make the changes.
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| 71 | ;
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| 72 |
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| 73 | ; Modify the x87 flags first (ecx preserved).
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| 74 | cmp ecx, X86_FSW_XCPT_MASK
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| 75 | jne .partial_mask
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| 76 | fnclex
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| 77 | jmp .do_sse
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| 78 |
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| 79 | .partial_mask:
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| 80 | fnstenv [xBP - 20h]
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| 81 | and word [xBP - 20h + 4], cx ; The FCW is at offset 4 in the 32-bit prot mode layout
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| 82 | fldenv [xBP - 20h] ; Recalculates the FSW.ES flag.
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| 83 | .do_sse:
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| 84 |
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| 85 | %ifdef RT_ARCH_X86
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| 86 | ; SSE supported (ecx preserved)?
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| 87 | extern NAME(rtNoCrtHasSse)
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| 88 | call NAME(rtNoCrtHasSse)
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| 89 | test al, al
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| 90 | jz .return_ok
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| 91 | %endif
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| 92 |
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| 93 | ; Modify the SSE flags (modifies ecx).
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| 94 | stmxcsr [xBP - 10h]
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| 95 | and [xBP - 10h], ecx
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| 96 | ldmxcsr [xBP - 10h]
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| 97 |
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| 98 | .return_ok:
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| 99 | xor eax, eax
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| 100 | .return:
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| 101 | leave
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| 102 | ret
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| 103 | ENDPROC RT_NOCRT(feclearexcept)
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| 104 |
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