ConsoleImplConfigX86.cpp@ 104516

最後變更在這個檔案從104516是 104516,由 vboxsync 提交於 11 月前
VMM/GCM,IEM,HM: Integrate GCM with IEM, extending it to cover the mesa drv situation and valid ring-0 IN instructions to same port. Untested. TODO: NEM. bugref:9735 bugref:10683
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 85.3 KB

行
1	/* $Id: ConsoleImplConfigX86.cpp 104516 2024-05-04 01:53:42Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits.
4	*
5	* @remark We've split out the code that the 64-bit VC++ v8 compiler finds
6	* problematic to optimize so we can disable optimizations and later,
7	* perhaps, find a real solution for it (like rewriting the code and
8	* to stop resemble a tonne of spaghetti).
9	*/
10
11	/*
12	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
13	*
14	* This file is part of VirtualBox base platform packages, as
15	* available from https://www.alldomusa.eu.org.
16	*
17	* This program is free software; you can redistribute it and/or
18	* modify it under the terms of the GNU General Public License
19	* as published by the Free Software Foundation, in version 3 of the
20	* License.
21	*
22	* This program is distributed in the hope that it will be useful, but
23	* WITHOUT ANY WARRANTY; without even the implied warranty of
24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25	* General Public License for more details.
26	*
27	* You should have received a copy of the GNU General Public License
28	* along with this program; if not, see <https://www.gnu.org/licenses>.
29	*
30	* SPDX-License-Identifier: GPL-3.0-only
31	*/
32
33
34	/*********************************************************************************************************************************
35	* Header Files *
36	*********************************************************************************************************************************/
37	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
38	#include "LoggingNew.h"
39
40	#include "ConsoleImpl.h"
41	#include "DisplayImpl.h"
42	#include "NvramStoreImpl.h"
43	#include "PlatformImpl.h"
44	#include "VMMDev.h"
45	#include "Global.h"
46	#ifdef VBOX_WITH_PCI_PASSTHROUGH
47	# include "PCIRawDevImpl.h"
48	#endif
49
50	// generated header
51	#include "SchemaDefs.h"
52
53	#include "AutoCaller.h"
54
55	#include <iprt/base64.h>
56	#include <iprt/buildconfig.h>
57	#include <iprt/ctype.h>
58	#include <iprt/dir.h>
59	#include <iprt/file.h>
60	#include <iprt/param.h>
61	#include <iprt/path.h>
62	#include <iprt/string.h>
63	#include <iprt/system.h>
64	#if 0 /* enable to play with lots of memory. */
65	# include <iprt/env.h>
66	#endif
67	#include <iprt/stream.h>
68
69	#include <iprt/http.h>
70	#include <iprt/socket.h>
71	#include <iprt/uri.h>
72
73	#include <VBox/vmm/vmmr3vtable.h>
74	#include <VBox/vmm/vmapi.h>
75	#include <VBox/err.h>
76	#include <VBox/param.h>
77	#include <VBox/settings.h> /* For MachineConfigFile::getHostDefaultAudioDriver(). */
78	#include <VBox/vmm/pdmapi.h> /* For PDMR3DriverAttach/PDMR3DriverDetach. */
79	#include <VBox/vmm/pdmusb.h> /* For PDMR3UsbCreateEmulatedDevice. */
80	#include <VBox/vmm/pdmdev.h> /* For PDMAPICMODE enum. */
81	#include <VBox/vmm/pdmstorageifs.h>
82	#include <VBox/version.h>
83
84	#include <VBox/com/com.h>
85	#include <VBox/com/string.h>
86	#include <VBox/com/array.h>
87
88	#include "NetworkServiceRunner.h"
89	#include "BusAssignmentManager.h"
90	#ifdef VBOX_WITH_EXTPACK
91	# include "ExtPackManagerImpl.h"
92	#endif
93
94
95	/*********************************************************************************************************************************
96	* Internal Functions *
97	*********************************************************************************************************************************/
98
99	/* Darwin compile kludge */
100	#undef PVM
101
102	/**
103	* @throws HRESULT on extra data retrival error.
104	*/
105	static int getSmcDeviceKey(IVirtualBox pVirtualBox, IMachine pMachine, Utf8Str pStrKey, bool pfGetKeyFromRealSMC)
106	{
107	*pfGetKeyFromRealSMC = false;
108
109	/*
110	* The extra data takes precedence (if non-zero).
111	*/
112	GetExtraDataBoth(pVirtualBox, pMachine, "VBoxInternal2/SmcDeviceKey", pStrKey);
113	if (pStrKey->isNotEmpty())
114	return VINF_SUCCESS;
115
116	#ifdef RT_OS_DARWIN
117
118	/*
119	* Work done in EFI/DevSmc
120	*/
121	*pfGetKeyFromRealSMC = true;
122	int vrc = VINF_SUCCESS;
123
124	#else
125	/*
126	* Is it apple hardware in bootcamp?
127	*/
128	/** @todo implement + test RTSYSDMISTR_MANUFACTURER on all hosts.
129	* Currently falling back on the product name. */
130	char szManufacturer[256];
131	szManufacturer[0] = '\0';
132	RTSystemQueryDmiString(RTSYSDMISTR_MANUFACTURER, szManufacturer, sizeof(szManufacturer));
133	if (szManufacturer[0] != '\0')
134	{
135	if ( !strcmp(szManufacturer, "Apple Computer, Inc.")
136	\|\| !strcmp(szManufacturer, "Apple Inc.")
137	)
138	*pfGetKeyFromRealSMC = true;
139	}
140	else
141	{
142	char szProdName[256];
143	szProdName[0] = '\0';
144	RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME, szProdName, sizeof(szProdName));
145	if ( ( !strncmp(szProdName, RT_STR_TUPLE("Mac"))
146	\|\| !strncmp(szProdName, RT_STR_TUPLE("iMac"))
147	\|\| !strncmp(szProdName, RT_STR_TUPLE("Xserve"))
148	)
149	&& !strchr(szProdName, ' ') /* no spaces */
150	&& RT_C_IS_DIGIT(szProdName[strlen(szProdName) - 1]) /* version number */
151	)
152	*pfGetKeyFromRealSMC = true;
153	}
154
155	int vrc = VINF_SUCCESS;
156	#endif
157
158	return vrc;
159	}
160
161
162	/*
163	* VC++ 8 / amd64 has some serious trouble with the next functions.
164	* As a temporary measure, we'll drop global optimizations.
165	*/
166	#if defined(_MSC_VER) && defined(RT_ARCH_AMD64)
167	# if _MSC_VER >= RT_MSC_VER_VC80 && _MSC_VER < RT_MSC_VER_VC100
168	# pragma optimize("g", off)
169	# endif
170	#endif
171
172	/** Helper that finds out the next HBA port used
173	*/
174	static LONG GetNextUsedPort(LONG aPortUsed[30], LONG lBaseVal, uint32_t u32Size)
175	{
176	LONG lNextPortUsed = 30;
177	for (size_t j = 0; j < u32Size; ++j)
178	{
179	if ( aPortUsed[j] > lBaseVal
180	&& aPortUsed[j] <= lNextPortUsed)
181	lNextPortUsed = aPortUsed[j];
182	}
183	return lNextPortUsed;
184	}
185
186	#define MAX_BIOS_LUN_COUNT 4
187
188	int Console::SetBiosDiskInfo(ComPtr<IMachine> pMachine, PCFGMNODE pCfg, PCFGMNODE pBiosCfg,
189	Bstr controllerName, const char * const s_apszBiosConfig[4])
190	{
191	RT_NOREF(pCfg);
192	HRESULT hrc;
193	#define MAX_DEVICES 30
194	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
195	#define VRC() AssertLogRelMsgReturn(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), vrc)
196
197	LONG lPortLUN[MAX_BIOS_LUN_COUNT];
198	LONG lPortUsed[MAX_DEVICES];
199	uint32_t u32HDCount = 0;
200
201	/* init to max value */
202	lPortLUN[0] = MAX_DEVICES;
203
204	com::SafeIfaceArray<IMediumAttachment> atts;
205	hrc = pMachine->GetMediumAttachmentsOfController(controllerName.raw(),
206	ComSafeArrayAsOutParam(atts)); H();
207	size_t uNumAttachments = atts.size();
208	if (uNumAttachments > MAX_DEVICES)
209	{
210	LogRel(("Number of Attachments > Max=%d.\n", uNumAttachments));
211	uNumAttachments = MAX_DEVICES;
212	}
213
214	/* Find the relevant ports/IDs, i.e the ones to which a HD is attached. */
215	for (size_t j = 0; j < uNumAttachments; ++j)
216	{
217	IMediumAttachment *pMediumAtt = atts[j];
218	LONG lPortNum = 0;
219	hrc = pMediumAtt->COMGETTER(Port)(&lPortNum); H();
220	if (SUCCEEDED(hrc))
221	{
222	DeviceType_T lType;
223	hrc = pMediumAtt->COMGETTER(Type)(&lType); H();
224	if (SUCCEEDED(hrc) && lType == DeviceType_HardDisk)
225	{
226	/* find min port number used for HD */
227	if (lPortNum < lPortLUN[0])
228	lPortLUN[0] = lPortNum;
229	lPortUsed[u32HDCount++] = lPortNum;
230	LogFlowFunc(("HD port Count=%d\n", u32HDCount));
231	}
232	}
233	}
234
235
236	/* Pick only the top 4 used HD Ports as CMOS doesn't have space
237	* to save details for all 30 ports
238	*/
239	uint32_t u32MaxPortCount = MAX_BIOS_LUN_COUNT;
240	if (u32HDCount < MAX_BIOS_LUN_COUNT)
241	u32MaxPortCount = u32HDCount;
242	for (size_t j = 1; j < u32MaxPortCount; j++)
243	lPortLUN[j] = GetNextUsedPort(lPortUsed, lPortLUN[j-1], u32HDCount);
244	if (pBiosCfg)
245	{
246	for (size_t j = 0; j < u32MaxPortCount; j++)
247	{
248	InsertConfigInteger(pBiosCfg, s_apszBiosConfig[j], lPortLUN[j]);
249	LogFlowFunc(("Top %d HBA ports = %s, %d\n", j, s_apszBiosConfig[j], lPortLUN[j]));
250	}
251	}
252	return VINF_SUCCESS;
253	}
254
255	#ifdef VBOX_WITH_PCI_PASSTHROUGH
256	HRESULT Console::i_attachRawPCIDevices(PUVM pUVM, BusAssignmentManager *pBusMgr, PCFGMNODE pDevices)
257	{
258	# ifndef VBOX_WITH_EXTPACK
259	RT_NOREF(pUVM);
260	# endif
261	HRESULT hrc = S_OK;
262	PCFGMNODE pInst, pCfg, pLunL0, pLunL1;
263
264	SafeIfaceArray<IPCIDeviceAttachment> assignments;
265	ComPtr<IMachine> aMachine = i_machine();
266
267	hrc = aMachine->COMGETTER(PCIDeviceAssignments)(ComSafeArrayAsOutParam(assignments));
268	if ( hrc != S_OK
269	\|\| assignments.size() < 1)
270	return hrc;
271
272	/*
273	* PCI passthrough is only available if the proper ExtPack is installed.
274	*
275	* Note. Configuring PCI passthrough here and providing messages about
276	* the missing extpack isn't exactly clean, but it is a necessary evil
277	* to patch over legacy compatability issues introduced by the new
278	* distribution model.
279	*/
280	# ifdef VBOX_WITH_EXTPACK
281	static const char *s_pszPCIRawExtPackName = "Oracle VM VirtualBox Extension Pack";
282	if (!mptrExtPackManager->i_isExtPackUsable(s_pszPCIRawExtPackName))
283	/* Always fatal! */
284	return pVMM->pfnVMR3SetError(pUVM, VERR_NOT_FOUND, RT_SRC_POS,
285	N_("Implementation of the PCI passthrough framework not found!\n"
286	"The VM cannot be started. To fix this problem, either "
287	"install the '%s' or disable PCI passthrough via VBoxManage"),
288	s_pszPCIRawExtPackName);
289	# endif
290
291	/* Now actually add devices */
292	PCFGMNODE pPCIDevs = NULL;
293
294	if (assignments.size() > 0)
295	{
296	InsertConfigNode(pDevices, "pciraw", &pPCIDevs);
297
298	PCFGMNODE pRoot = CFGMR3GetParent(pDevices); Assert(pRoot);
299
300	/* Tell PGM to tell GPCIRaw about guest mappings. */
301	CFGMR3InsertNode(pRoot, "PGM", NULL);
302	InsertConfigInteger(CFGMR3GetChild(pRoot, "PGM"), "PciPassThrough", 1);
303
304	/*
305	* Currently, using IOMMU needed for PCI passthrough
306	* requires RAM preallocation.
307	*/
308	/** @todo check if we can lift this requirement */
309	CFGMR3RemoveValue(pRoot, "RamPreAlloc");
310	InsertConfigInteger(pRoot, "RamPreAlloc", 1);
311	}
312
313	for (size_t iDev = 0; iDev < assignments.size(); iDev++)
314	{
315	ComPtr<IPCIDeviceAttachment> const assignment = assignments[iDev];
316
317	LONG host;
318	hrc = assignment->COMGETTER(HostAddress)(&host); H();
319	LONG guest;
320	hrc = assignment->COMGETTER(GuestAddress)(&guest); H();
321	Bstr bstrDevName;
322	hrc = assignment->COMGETTER(Name)(bstrDevName.asOutParam()); H();
323
324	InsertConfigNodeF(pPCIDevs, &pInst, "%d", iDev);
325	InsertConfigInteger(pInst, "Trusted", 1);
326
327	PCIBusAddress HostPCIAddress(host);
328	Assert(HostPCIAddress.valid());
329	InsertConfigNode(pInst, "Config", &pCfg);
330	InsertConfigString(pCfg, "DeviceName", bstrDevName);
331
332	InsertConfigInteger(pCfg, "DetachHostDriver", 1);
333	InsertConfigInteger(pCfg, "HostPCIBusNo", HostPCIAddress.miBus);
334	InsertConfigInteger(pCfg, "HostPCIDeviceNo", HostPCIAddress.miDevice);
335	InsertConfigInteger(pCfg, "HostPCIFunctionNo", HostPCIAddress.miFn);
336
337	PCIBusAddress GuestPCIAddress(guest);
338	Assert(GuestPCIAddress.valid());
339	hrc = pBusMgr->assignHostPCIDevice("pciraw", pInst, HostPCIAddress, GuestPCIAddress, true);
340	if (hrc != S_OK)
341	return hrc;
342
343	InsertConfigInteger(pCfg, "GuestPCIBusNo", GuestPCIAddress.miBus);
344	InsertConfigInteger(pCfg, "GuestPCIDeviceNo", GuestPCIAddress.miDevice);
345	InsertConfigInteger(pCfg, "GuestPCIFunctionNo", GuestPCIAddress.miFn);
346
347	/* the driver */
348	InsertConfigNode(pInst, "LUN#0", &pLunL0);
349	InsertConfigString(pLunL0, "Driver", "pciraw");
350	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
351
352	/* the Main driver */
353	InsertConfigString(pLunL1, "Driver", "MainPciRaw");
354	InsertConfigNode(pLunL1, "Config", &pCfg);
355	PCIRawDev *pMainDev = new PCIRawDev(this);
356	# error This is not allowed any more
357	InsertConfigInteger(pCfg, "Object", (uintptr_t)pMainDev);
358	}
359
360	return hrc;
361	}
362	#endif
363
364
365	/**
366	* Worker for configConstructor.
367	*
368	* @return VBox status code.
369	* @param pUVM The user mode VM handle.
370	* @param pVM The cross context VM handle.
371	* @param pVMM The VMM vtable.
372	* @param pAlock The automatic lock instance. This is for when we have
373	* to leave it in order to avoid deadlocks (ext packs and
374	* more).
375	*/
376	int Console::i_configConstructorX86(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
377	{
378	RT_NOREF(pVM /* when everything is disabled */);
379	ComPtr<IMachine> pMachine = i_machine();
380
381	int vrc;
382	HRESULT hrc;
383	Utf8Str strTmp;
384	Bstr bstr;
385
386	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
387
388	/*
389	* Get necessary objects and frequently used parameters.
390	*/
391	ComPtr<IVirtualBox> virtualBox;
392	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
393
394	ComPtr<IHost> host;
395	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
396
397	ComPtr<ISystemProperties> systemProperties;
398	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
399
400	ComPtr<IFirmwareSettings> firmwareSettings;
401	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
402
403	ComPtr<INvramStore> nvramStore;
404	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
405
406	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
407	RTUUID HardwareUuid;
408	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
409	AssertRCReturn(vrc, vrc);
410
411	ULONG cRamMBs;
412	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
413	#if 0 /* enable to play with lots of memory. */
414	if (RTEnvExist("VBOX_RAM_SIZE"))
415	cRamMBs = RTStrToUInt64(RTEnvGet("VBOX_RAM_SIZE"));
416	#endif
417	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
418	uint32_t cbRamHole = MM_RAM_HOLE_SIZE_DEFAULT;
419	uint64_t uMcfgBase = 0;
420	uint32_t cbMcfgLength = 0;
421
422	ParavirtProvider_T enmParavirtProvider;
423	hrc = pMachine->GetEffectiveParavirtProvider(&enmParavirtProvider); H();
424
425	Bstr strParavirtDebug;
426	hrc = pMachine->COMGETTER(ParavirtDebug)(strParavirtDebug.asOutParam()); H();
427
428	BOOL fIOAPIC;
429	uint32_t uIoApicPciAddress = NIL_PCIBDF;
430	hrc = firmwareSettings->COMGETTER(IOAPICEnabled)(&fIOAPIC); H();
431
432	ComPtr<IPlatform> platform;
433	pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
434
435	ChipsetType_T chipsetType;
436	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
437	if (chipsetType == ChipsetType_ICH9)
438	{
439	/* We'd better have 0x10000000 region, to cover 256 buses but this put
440	* too much load on hypervisor heap. Linux 4.8 currently complains with
441	* ``acpi PNP0A03:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f]
442	* only partially covers this bridge'' */
443	cbMcfgLength = 0x4000000; //0x10000000;
444	cbRamHole += cbMcfgLength;
445	uMcfgBase = _4G - cbRamHole;
446	}
447
448	/* Get the CPU profile name. */
449	Bstr bstrCpuProfile;
450	hrc = pMachine->COMGETTER(CPUProfile)(bstrCpuProfile.asOutParam()); H();
451
452	/* Get the X86 platform object. */
453	ComPtr<IPlatformX86> platformX86;
454	hrc = platform->COMGETTER(X86)(platformX86.asOutParam()); H();
455
456	/* Check if long mode is enabled. */
457	BOOL fIsGuest64Bit;
458	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_LongMode, &fIsGuest64Bit); H();
459
460	/*
461	* Figure out the IOMMU config.
462	*/
463	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
464	IommuType_T enmIommuType;
465	hrc = platform->COMGETTER(IommuType)(&enmIommuType); H();
466
467	/* Resolve 'automatic' type to an Intel or AMD IOMMU based on the host CPU. */
468	if (enmIommuType == IommuType_Automatic)
469	{
470	if ( bstrCpuProfile.startsWith("AMD")
471	\|\| bstrCpuProfile.startsWith("Quad-Core AMD")
472	\|\| bstrCpuProfile.startsWith("Hygon"))
473	enmIommuType = IommuType_AMD;
474	else if (bstrCpuProfile.startsWith("Intel"))
475	{
476	if ( bstrCpuProfile.equals("Intel 8086")
477	\|\| bstrCpuProfile.equals("Intel 80186")
478	\|\| bstrCpuProfile.equals("Intel 80286")
479	\|\| bstrCpuProfile.equals("Intel 80386")
480	\|\| bstrCpuProfile.equals("Intel 80486"))
481	enmIommuType = IommuType_None;
482	else
483	enmIommuType = IommuType_Intel;
484	}
485	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
486	else if (ASMIsAmdCpu())
487	enmIommuType = IommuType_AMD;
488	else if (ASMIsIntelCpu())
489	enmIommuType = IommuType_Intel;
490	# endif
491	else
492	{
493	/** @todo Should we handle other CPUs like Shanghai, VIA etc. here? */
494	LogRel(("WARNING! Unrecognized CPU type, IOMMU disabled.\n"));
495	enmIommuType = IommuType_None;
496	}
497	}
498
499	if (enmIommuType == IommuType_AMD)
500	{
501	# ifdef VBOX_WITH_IOMMU_AMD
502	/*
503	* Reserve the specific PCI address of the "SB I/O APIC" when using
504	* an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
505	*/
506	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
507	# else
508	LogRel(("WARNING! AMD IOMMU not supported, IOMMU disabled.\n"));
509	enmIommuType = IommuType_None;
510	# endif
511	}
512
513	if (enmIommuType == IommuType_Intel)
514	{
515	# ifdef VBOX_WITH_IOMMU_INTEL
516	/*
517	* Reserve a unique PCI address for the I/O APIC when using
518	* an Intel IOMMU. For convenience we use the same address as
519	* we do on AMD, see @bugref{9967#c13}.
520	*/
521	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
522	# else
523	LogRel(("WARNING! Intel IOMMU not supported, IOMMU disabled.\n"));
524	enmIommuType = IommuType_None;
525	# endif
526	}
527
528	if ( enmIommuType == IommuType_AMD
529	\|\| enmIommuType == IommuType_Intel)
530	{
531	if (chipsetType != ChipsetType_ICH9)
532	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
533	N_("IOMMU uses MSIs which requires the ICH9 chipset implementation."));
534	if (!fIOAPIC)
535	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
536	N_("IOMMU requires an I/O APIC for remapping interrupts."));
537	}
538	#else
539	IommuType_T const enmIommuType = IommuType_None;
540	#endif
541
542	/* Instantiate the bus assignment manager. */
543	Assert(enmIommuType != IommuType_Automatic);
544	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, enmIommuType);
545
546	ULONG cCpus = 1;
547	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
548
549	ULONG ulCpuExecutionCap = 100;
550	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
551
552	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
553	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
554
555	LogRel(("Guest architecture: x86\n"));
556
557	Bstr osTypeId;
558	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
559	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
560
561	APICMode_T apicMode;
562	hrc = firmwareSettings->COMGETTER(APICMode)(&apicMode); H();
563	uint32_t uFwAPIC;
564	switch (apicMode)
565	{
566	case APICMode_Disabled:
567	uFwAPIC = 0;
568	break;
569	case APICMode_APIC:
570	uFwAPIC = 1;
571	break;
572	case APICMode_X2APIC:
573	uFwAPIC = 2;
574	break;
575	default:
576	AssertMsgFailed(("Invalid APICMode=%d\n", apicMode));
577	uFwAPIC = 1;
578	break;
579	}
580
581	ComPtr<IGuestOSType> pGuestOSType;
582	virtualBox->GetGuestOSType(osTypeId.raw(), pGuestOSType.asOutParam());
583
584	BOOL fOsXGuest = FALSE;
585	BOOL fWinGuest = FALSE;
586	BOOL fOs2Guest = FALSE;
587	BOOL fW9xGuest = FALSE;
588	BOOL fDosGuest = FALSE;
589	if (pGuestOSType.isNotNull())
590	{
591	Bstr guestTypeFamilyId;
592	hrc = pGuestOSType->COMGETTER(FamilyId)(guestTypeFamilyId.asOutParam()); H();
593	fOsXGuest = guestTypeFamilyId == Bstr("MacOS");
594	fWinGuest = guestTypeFamilyId == Bstr("Windows");
595	fOs2Guest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("OS2"));
596	fW9xGuest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("Windows9")); /* Does not include Windows Me. */
597	fDosGuest = osTypeId.equals(GUEST_OS_ID_STR_X86("DOS")) \|\| osTypeId.equals(GUEST_OS_ID_STR_X86("Windows31"));
598	}
599
600	ComPtr<IPlatformProperties> platformProperties;
601	virtualBox->GetPlatformProperties(PlatformArchitecture_x86, platformProperties.asOutParam());
602
603	/*
604	* Get root node first.
605	* This is the only node in the tree.
606	*/
607	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
608	Assert(pRoot);
609
610	// catching throws from InsertConfigString and friends.
611	try
612	{
613
614	/*
615	* Set the root (and VMM) level values.
616	*/
617	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
618	InsertConfigString(pRoot, "Name", bstr);
619	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
620	InsertConfigInteger(pRoot, "RamSize", cbRam);
621	InsertConfigInteger(pRoot, "RamHoleSize", cbRamHole);
622	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
623	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
624	InsertConfigInteger(pRoot, "TimerMillies", 10);
625
626	BOOL fPageFusion = FALSE;
627	hrc = pMachine->COMGETTER(PageFusionEnabled)(&fPageFusion); H();
628	InsertConfigInteger(pRoot, "PageFusionAllowed", fPageFusion); /* boolean */
629
630	/* Not necessary, but makes sure this setting ends up in the release log. */
631	ULONG ulBalloonSize = 0;
632	hrc = pMachine->COMGETTER(MemoryBalloonSize)(&ulBalloonSize); H();
633	InsertConfigInteger(pRoot, "MemBalloonSize", ulBalloonSize);
634
635	/*
636	* EM values (before CPUM as it may need to set IemExecutesAll).
637	*/
638	PCFGMNODE pEM;
639	InsertConfigNode(pRoot, "EM", &pEM);
640
641	/* Triple fault behavior. */
642	BOOL fTripleFaultReset = false;
643	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_TripleFaultReset, &fTripleFaultReset); H();
644	InsertConfigInteger(pEM, "TripleFaultReset", fTripleFaultReset);
645
646	/*
647	* CPUM values.
648	*/
649	PCFGMNODE pCPUM;
650	InsertConfigNode(pRoot, "CPUM", &pCPUM);
651	PCFGMNODE pIsaExts;
652	InsertConfigNode(pCPUM, "IsaExts", &pIsaExts);
653
654	/* Host CPUID leaf overrides. */
655	for (uint32_t iOrdinal = 0; iOrdinal < _4K; iOrdinal++)
656	{
657	ULONG uLeaf, uSubLeaf, uEax, uEbx, uEcx, uEdx;
658	hrc = platformX86->GetCPUIDLeafByOrdinal(iOrdinal, &uLeaf, &uSubLeaf, &uEax, &uEbx, &uEcx, &uEdx);
659	if (hrc == E_INVALIDARG)
660	break;
661	H();
662	PCFGMNODE pLeaf;
663	InsertConfigNode(pCPUM, Utf8StrFmt("HostCPUID/%RX32", uLeaf).c_str(), &pLeaf);
664	/** @todo Figure out how to tell the VMM about uSubLeaf */
665	InsertConfigInteger(pLeaf, "eax", uEax);
666	InsertConfigInteger(pLeaf, "ebx", uEbx);
667	InsertConfigInteger(pLeaf, "ecx", uEcx);
668	InsertConfigInteger(pLeaf, "edx", uEdx);
669	}
670
671	/* We must limit CPUID count for Windows NT 4, as otherwise it stops
672	with error 0x3e (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED). */
673	if (osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4"))
674	{
675	LogRel(("Limiting CPUID leaf count for NT4 guests\n"));
676	InsertConfigInteger(pCPUM, "NT4LeafLimit", true);
677	}
678
679	if (fOsXGuest)
680	{
681	/* Expose extended MWAIT features to Mac OS X guests. */
682	LogRel(("Using MWAIT extensions\n"));
683	InsertConfigInteger(pIsaExts, "MWaitExtensions", true);
684
685	/* Fake the CPU family/model so the guest works. This is partly
686	because older mac releases really doesn't work on newer cpus,
687	and partly because mac os x expects more from systems with newer
688	cpus (MSRs, power features, whatever). */
689	uint32_t uMaxIntelFamilyModelStep = UINT32_MAX;
690	if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS")
691	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS"))
692	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482. */
693	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS106")
694	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS106"))
695	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */
696	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS107")
697	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS107"))
698	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
699	what is required here. */
700	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS108")
701	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS108"))
702	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
703	what is required here. */
704	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS109")
705	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS109"))
706	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure
707	out what is required here. */
708	if (uMaxIntelFamilyModelStep != UINT32_MAX)
709	InsertConfigInteger(pCPUM, "MaxIntelFamilyModelStep", uMaxIntelFamilyModelStep);
710	}
711
712	/* CPU Portability level, */
713	ULONG uCpuIdPortabilityLevel = 0;
714	hrc = pMachine->COMGETTER(CPUIDPortabilityLevel)(&uCpuIdPortabilityLevel); H();
715	InsertConfigInteger(pCPUM, "PortableCpuIdLevel", uCpuIdPortabilityLevel);
716
717	/* Physical Address Extension (PAE) */
718	BOOL fEnablePAE = false;
719	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_PAE, &fEnablePAE); H();
720	fEnablePAE \|= fIsGuest64Bit;
721	InsertConfigInteger(pRoot, "EnablePAE", fEnablePAE);
722
723	/* 64-bit guests (long mode) */
724	InsertConfigInteger(pCPUM, "Enable64bit", fIsGuest64Bit);
725
726	/* APIC/X2APIC configuration */
727	BOOL fEnableAPIC = true;
728	BOOL fEnableX2APIC = true;
729	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_APIC, &fEnableAPIC); H();
730	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_X2APIC, &fEnableX2APIC); H();
731	if (fEnableX2APIC)
732	Assert(fEnableAPIC);
733
734	/* CPUM profile name. */
735	InsertConfigString(pCPUM, "GuestCpuName", bstrCpuProfile);
736
737	/*
738	* Temporary(?) hack to make sure we emulate the ancient 16-bit CPUs
739	* correctly. There are way too many #UDs we'll miss using VT-x,
740	* raw-mode or qemu for the 186 and 286, while we'll get undefined opcodes
741	* dead wrong on 8086 (see http://www.os2museum.com/wp/undocumented-8086-opcodes/).
742	*/
743	if ( bstrCpuProfile.equals("Intel 80386") /* just for now */
744	\|\| bstrCpuProfile.equals("Intel 80286")
745	\|\| bstrCpuProfile.equals("Intel 80186")
746	\|\| bstrCpuProfile.equals("Nec V20")
747	\|\| bstrCpuProfile.equals("Intel 8086") )
748	{
749	InsertConfigInteger(pEM, "IemExecutesAll", true);
750	if (!bstrCpuProfile.equals("Intel 80386"))
751	{
752	fEnableAPIC = false;
753	fIOAPIC = false;
754	}
755	fEnableX2APIC = false;
756	}
757
758	/* Adjust firmware APIC handling to stay within the VCPU limits. */
759	if (uFwAPIC == 2 && !fEnableX2APIC)
760	{
761	if (fEnableAPIC)
762	uFwAPIC = 1;
763	else
764	uFwAPIC = 0;
765	LogRel(("Limiting the firmware APIC level from x2APIC to %s\n", fEnableAPIC ? "APIC" : "Disabled"));
766	}
767	else if (uFwAPIC == 1 && !fEnableAPIC)
768	{
769	uFwAPIC = 0;
770	LogRel(("Limiting the firmware APIC level from APIC to Disabled\n"));
771	}
772
773	/* Speculation Control. */
774	BOOL fSpecCtrl = FALSE;
775	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrl, &fSpecCtrl); H();
776	InsertConfigInteger(pCPUM, "SpecCtrl", fSpecCtrl);
777
778	/* Nested VT-x / AMD-V. */
779	BOOL fNestedHWVirt = FALSE;
780	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_HWVirt, &fNestedHWVirt); H();
781	InsertConfigInteger(pCPUM, "NestedHWVirt", fNestedHWVirt ? true : false);
782
783	/*
784	* Hardware virtualization extensions.
785	*/
786	/* Sanitize valid/useful APIC combinations, see @bugref{8868}. */
787	if (!fEnableAPIC)
788	{
789	if (fIsGuest64Bit)
790	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
791	N_("Cannot disable the APIC for a 64-bit guest."));
792	if (cCpus > 1)
793	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
794	N_("Cannot disable the APIC for an SMP guest."));
795	if (fIOAPIC)
796	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
797	N_("Cannot disable the APIC when the I/O APIC is present."));
798	}
799
800	BOOL fHMEnabled;
801	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Enabled, &fHMEnabled); H();
802	if (cCpus > 1 && !fHMEnabled)
803	{
804	LogRel(("Forced fHMEnabled to TRUE by SMP guest.\n"));
805	fHMEnabled = TRUE;
806	}
807
808	BOOL fHMForced;
809	fHMEnabled = fHMForced = TRUE;
810	LogRel(("fHMForced=true - No raw-mode support in this build!\n"));
811	if (!fHMForced) /* No need to query if already forced above. */
812	{
813	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Force, &fHMForced); H();
814	if (fHMForced)
815	LogRel(("fHMForced=true - HWVirtExPropertyType_Force\n"));
816	}
817	InsertConfigInteger(pRoot, "HMEnabled", fHMEnabled);
818
819	/* /HM/xyz */
820	PCFGMNODE pHM;
821	InsertConfigNode(pRoot, "HM", &pHM);
822	InsertConfigInteger(pHM, "HMForced", fHMForced);
823	if (fHMEnabled)
824	{
825	/* Indicate whether 64-bit guests are supported or not. */
826	InsertConfigInteger(pHM, "64bitEnabled", fIsGuest64Bit);
827
828	/** @todo Not exactly pretty to check strings; VBOXOSTYPE would be better,
829	but that requires quite a bit of API change in Main. */
830	if ( fIOAPIC
831	&& ( osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4")
832	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2000")
833	\|\| osTypeId == GUEST_OS_ID_STR_X86("WindowsXP")
834	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2003")))
835	{
836	/* Only allow TPR patching for NT, Win2k, XP and Windows Server 2003. (32 bits mode)
837	* We may want to consider adding more guest OSes (Solaris) later on.
838	*/
839	InsertConfigInteger(pHM, "TPRPatchingEnabled", 1);
840	}
841	}
842
843	/*
844	* Set VM execution engine.
845	*/
846	/** @todo r=aeichner Maybe provide a better VMM API for this instead of the different CFGM knobs. */
847	LogRel(("Using execution engine %u\n", enmExecEngine));
848	switch (enmExecEngine)
849	{
850	case VMExecutionEngine_HwVirt:
851	InsertConfigInteger(pEM, "IemExecutesAll", 0);
852	InsertConfigInteger(pEM, "IemRecompiled", 0);
853	InsertConfigInteger(pHM, "UseNEMInstead", 0);
854	InsertConfigInteger(pHM, "FallbackToNEM", 0);
855	InsertConfigInteger(pHM, "FallbackToIEM", 0);
856	break;
857	case VMExecutionEngine_NativeApi:
858	InsertConfigInteger(pEM, "IemExecutesAll", 0);
859	InsertConfigInteger(pEM, "IemRecompiled", 0);
860	InsertConfigInteger(pHM, "UseNEMInstead", 1);
861	InsertConfigInteger(pHM, "FallbackToNEM", 1);
862	InsertConfigInteger(pHM, "FallbackToIEM", 0);
863	break;
864	case VMExecutionEngine_Interpreter:
865	case VMExecutionEngine_Recompiler:
866	InsertConfigInteger(pEM, "IemExecutesAll", 1);
867	InsertConfigInteger(pEM, "IemRecompiled", enmExecEngine == VMExecutionEngine_Recompiler);
868	InsertConfigInteger(pHM, "UseNEMInstead", 0);
869	InsertConfigInteger(pHM, "FallbackToNEM", 0);
870	InsertConfigInteger(pHM, "FallbackToIEM", 1);
871	break;
872	case VMExecutionEngine_Default:
873	break; /* Nothing to do, let VMM decide. */
874	default:
875	AssertLogRelFailed();
876	}
877
878	/* HWVirtEx exclusive mode */
879	BOOL fHMExclusive = true;
880	hrc = platformProperties->COMGETTER(ExclusiveHwVirt)(&fHMExclusive); H();
881	InsertConfigInteger(pHM, "Exclusive", fHMExclusive);
882
883	/* Nested paging (VT-x/AMD-V) */
884	BOOL fEnableNestedPaging = false;
885	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_NestedPaging, &fEnableNestedPaging); H();
886	InsertConfigInteger(pHM, "EnableNestedPaging", fEnableNestedPaging);
887
888	/* Large pages; requires nested paging */
889	BOOL fEnableLargePages = false;
890	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_LargePages, &fEnableLargePages); H();
891	InsertConfigInteger(pHM, "EnableLargePages", fEnableLargePages);
892
893	/* VPID (VT-x) */
894	BOOL fEnableVPID = false;
895	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_VPID, &fEnableVPID); H();
896	InsertConfigInteger(pHM, "EnableVPID", fEnableVPID);
897
898	/* Unrestricted execution aka UX (VT-x) */
899	BOOL fEnableUX = false;
900	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UnrestrictedExecution, &fEnableUX); H();
901	InsertConfigInteger(pHM, "EnableUX", fEnableUX);
902
903	/* Virtualized VMSAVE/VMLOAD (AMD-V) */
904	BOOL fVirtVmsaveVmload = true;
905	hrc = host->GetProcessorFeature(ProcessorFeature_VirtVmsaveVmload, &fVirtVmsaveVmload); H();
906	InsertConfigInteger(pHM, "SvmVirtVmsaveVmload", fVirtVmsaveVmload);
907
908	/* Indirect branch prediction boundraries. */
909	BOOL fIBPBOnVMExit = false;
910	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMExit, &fIBPBOnVMExit); H();
911	InsertConfigInteger(pHM, "IBPBOnVMExit", fIBPBOnVMExit);
912
913	BOOL fIBPBOnVMEntry = false;
914	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMEntry, &fIBPBOnVMEntry); H();
915	InsertConfigInteger(pHM, "IBPBOnVMEntry", fIBPBOnVMEntry);
916
917	BOOL fSpecCtrlByHost = false;
918	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrlByHost, &fSpecCtrlByHost); H();
919	InsertConfigInteger(pHM, "SpecCtrlByHost", fSpecCtrlByHost);
920
921	BOOL fL1DFlushOnSched = true;
922	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnEMTScheduling, &fL1DFlushOnSched); H();
923	InsertConfigInteger(pHM, "L1DFlushOnSched", fL1DFlushOnSched);
924
925	BOOL fL1DFlushOnVMEntry = false;
926	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnVMEntry, &fL1DFlushOnVMEntry); H();
927	InsertConfigInteger(pHM, "L1DFlushOnVMEntry", fL1DFlushOnVMEntry);
928
929	BOOL fMDSClearOnSched = true;
930	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnEMTScheduling, &fMDSClearOnSched); H();
931	InsertConfigInteger(pHM, "MDSClearOnSched", fMDSClearOnSched);
932
933	BOOL fMDSClearOnVMEntry = false;
934	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnVMEntry, &fMDSClearOnVMEntry); H();
935	InsertConfigInteger(pHM, "MDSClearOnVMEntry", fMDSClearOnVMEntry);
936
937	/* Reset overwrite. */
938	mfTurnResetIntoPowerOff = GetExtraDataBoth(virtualBox, pMachine,
939	"VBoxInternal2/TurnResetIntoPowerOff", &strTmp)->equals("1");
940	if (mfTurnResetIntoPowerOff)
941	InsertConfigInteger(pRoot, "PowerOffInsteadOfReset", 1);
942
943	/** @todo This is a bit redundant but in order to avoid forcing setting version bumps later on
944	* and don't magically change behavior of old VMs we have to keep this for now. As soon as the user sets
945	* the execution to anything else than Default the execution engine setting takes precedence.
946	*/
947	if (enmExecEngine == VMExecutionEngine_Default)
948	{
949	/* Use NEM rather than HM. */
950	BOOL fUseNativeApi = false;
951	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UseNativeApi, &fUseNativeApi); H();
952	InsertConfigInteger(pHM, "UseNEMInstead", fUseNativeApi);
953	}
954
955	/* Enable workaround for missing TLB flush for OS/2 guests, see ticketref:20625. */
956	if (fOs2Guest)
957	InsertConfigInteger(pHM, "MissingOS2TlbFlushWorkaround", 1);
958
959	/*
960	* NEM
961	*/
962	PCFGMNODE pNEM;
963	InsertConfigNode(pRoot, "NEM", &pNEM);
964	InsertConfigInteger(pNEM, "Allow64BitGuests", fIsGuest64Bit);
965
966	/*
967	* Paravirt. provider.
968	*/
969	PCFGMNODE pParavirtNode;
970	InsertConfigNode(pRoot, "GIM", &pParavirtNode);
971	const char *pcszParavirtProvider;
972	bool fGimDeviceNeeded = true;
973	switch (enmParavirtProvider)
974	{
975	case ParavirtProvider_None:
976	pcszParavirtProvider = "None";
977	fGimDeviceNeeded = false;
978	break;
979
980	case ParavirtProvider_Minimal:
981	pcszParavirtProvider = "Minimal";
982	break;
983
984	case ParavirtProvider_HyperV:
985	pcszParavirtProvider = "HyperV";
986	break;
987
988	case ParavirtProvider_KVM:
989	pcszParavirtProvider = "KVM";
990	break;
991
992	default:
993	AssertMsgFailed(("Invalid enmParavirtProvider=%d\n", enmParavirtProvider));
994	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, N_("Invalid paravirt. provider '%d'"),
995	enmParavirtProvider);
996	}
997	InsertConfigString(pParavirtNode, "Provider", pcszParavirtProvider);
998
999	/*
1000	* Parse paravirt. debug options.
1001	*/
1002	bool fGimDebug = false;
1003	com::Utf8Str strGimDebugAddress = "127.0.0.1";
1004	uint32_t uGimDebugPort = 50000;
1005	if (strParavirtDebug.isNotEmpty())
1006	{
1007	/* Hyper-V debug options. */
1008	if (enmParavirtProvider == ParavirtProvider_HyperV)
1009	{
1010	bool fGimHvDebug = false;
1011	com::Utf8Str strGimHvVendor;
1012	bool fGimHvVsIf = false;
1013	bool fGimHvHypercallIf = false;
1014
1015	size_t uPos = 0;
1016	com::Utf8Str strDebugOptions = strParavirtDebug;
1017	com::Utf8Str strKey;
1018	com::Utf8Str strVal;
1019	while ((uPos = strDebugOptions.parseKeyValue(strKey, strVal, uPos)) != com::Utf8Str::npos)
1020	{
1021	if (strKey == "enabled")
1022	{
1023	if (strVal.toUInt32() == 1)
1024	{
1025	/* Apply defaults.
1026	The defaults are documented in the user manual,
1027	changes need to be reflected accordingly. */
1028	fGimHvDebug = true;
1029	strGimHvVendor = "Microsoft Hv";
1030	fGimHvVsIf = true;
1031	fGimHvHypercallIf = false;
1032	}
1033	/* else: ignore, i.e. don't assert below with 'enabled=0'. */
1034	}
1035	else if (strKey == "address")
1036	strGimDebugAddress = strVal;
1037	else if (strKey == "port")
1038	uGimDebugPort = strVal.toUInt32();
1039	else if (strKey == "vendor")
1040	strGimHvVendor = strVal;
1041	else if (strKey == "vsinterface")
1042	fGimHvVsIf = RT_BOOL(strVal.toUInt32());
1043	else if (strKey == "hypercallinterface")
1044	fGimHvHypercallIf = RT_BOOL(strVal.toUInt32());
1045	else
1046	{
1047	AssertMsgFailed(("Unrecognized Hyper-V debug option '%s'\n", strKey.c_str()));
1048	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1049	N_("Unrecognized Hyper-V debug option '%s' in '%s'"), strKey.c_str(),
1050	strDebugOptions.c_str());
1051	}
1052	}
1053
1054	/* Update HyperV CFGM node with active debug options. */
1055	if (fGimHvDebug)
1056	{
1057	PCFGMNODE pHvNode;
1058	InsertConfigNode(pParavirtNode, "HyperV", &pHvNode);
1059	InsertConfigString(pHvNode, "VendorID", strGimHvVendor);
1060	InsertConfigInteger(pHvNode, "VSInterface", fGimHvVsIf ? 1 : 0);
1061	InsertConfigInteger(pHvNode, "HypercallDebugInterface", fGimHvHypercallIf ? 1 : 0);
1062	fGimDebug = true;
1063	}
1064	}
1065	}
1066
1067	/*
1068	* Guest Compatibility Manager.
1069	*/
1070	PCFGMNODE pGcmNode;
1071	InsertConfigNode(pRoot, "GCM", &pGcmNode);
1072	/* OS/2 and Win9x guests can run DOS apps so they get the DOS specific
1073	fixes as well. */
1074	if (fDosGuest \|\| fOs2Guest \|\| fW9xGuest)
1075	InsertConfigInteger(pGcmNode, "DivByZeroDOS", 1);
1076	if (fOs2Guest)
1077	InsertConfigInteger(pGcmNode, "DivByZeroOS2", 1);
1078	if (fW9xGuest)
1079	InsertConfigInteger(pGcmNode, "DivByZeroWin9x", 1);
1080	/* MesaVmsvgaDrv (formerly LovelyMesaDrvWorkaround) is set futher down. */
1081
1082	/*
1083	* MM values.
1084	*/
1085	PCFGMNODE pMM;
1086	InsertConfigNode(pRoot, "MM", &pMM);
1087	InsertConfigInteger(pMM, "CanUseLargerHeap", chipsetType == ChipsetType_ICH9);
1088
1089	/*
1090	* PDM config.
1091	* Load drivers in VBoxC.[so\|dll]
1092	*/
1093	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
1094
1095	/*
1096	* Devices
1097	*/
1098	PCFGMNODE pDevices = NULL; /* /Devices */
1099	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
1100	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
1101	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
1102	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
1103	PCFGMNODE pLunL1 = NULL; /* /Devices/Dev/0/LUN#0/AttachedDriver/ */
1104	PCFGMNODE pBiosCfg = NULL; /* /Devices/pcbios/0/Config/ */
1105	PCFGMNODE pNetBootCfg = NULL; /* /Devices/pcbios/0/Config/NetBoot/ */
1106
1107	InsertConfigNode(pRoot, "Devices", &pDevices);
1108
1109	/*
1110	* GIM Device
1111	*/
1112	if (fGimDeviceNeeded)
1113	{
1114	InsertConfigNode(pDevices, "GIMDev", &pDev);
1115	InsertConfigNode(pDev, "0", &pInst);
1116	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1117	//InsertConfigNode(pInst, "Config", &pCfg);
1118
1119	if (fGimDebug)
1120	{
1121	InsertConfigNode(pInst, "LUN#998", &pLunL0);
1122	InsertConfigString(pLunL0, "Driver", "UDP");
1123	InsertConfigNode(pLunL0, "Config", &pLunL1);
1124	InsertConfigString(pLunL1, "ServerAddress", strGimDebugAddress);
1125	InsertConfigInteger(pLunL1, "ServerPort", uGimDebugPort);
1126	}
1127	}
1128
1129	/*
1130	* PC Arch.
1131	*/
1132	InsertConfigNode(pDevices, "pcarch", &pDev);
1133	InsertConfigNode(pDev, "0", &pInst);
1134	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1135	InsertConfigNode(pInst, "Config", &pCfg);
1136
1137	/*
1138	* The time offset
1139	*/
1140	LONG64 timeOffset;
1141	hrc = firmwareSettings->COMGETTER(TimeOffset)(&timeOffset); H();
1142	PCFGMNODE pTMNode;
1143	InsertConfigNode(pRoot, "TM", &pTMNode);
1144	InsertConfigInteger(pTMNode, "UTCOffset", timeOffset * 1000000);
1145
1146	/*
1147	* DMA
1148	*/
1149	InsertConfigNode(pDevices, "8237A", &pDev);
1150	InsertConfigNode(pDev, "0", &pInst);
1151	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1152
1153	/*
1154	* PCI buses.
1155	*/
1156	uint32_t uIocPCIAddress, uHbcPCIAddress;
1157	switch (chipsetType)
1158	{
1159	default:
1160	AssertFailed();
1161	RT_FALL_THRU();
1162	case ChipsetType_PIIX3:
1163	/* Create the base for adding bridges on demand */
1164	InsertConfigNode(pDevices, "pcibridge", NULL);
1165
1166	InsertConfigNode(pDevices, "pci", &pDev);
1167	uHbcPCIAddress = (0x0 << 16) \| 0;
1168	uIocPCIAddress = (0x1 << 16) \| 0; // ISA controller
1169	break;
1170	case ChipsetType_ICH9:
1171	/* Create the base for adding bridges on demand */
1172	InsertConfigNode(pDevices, "ich9pcibridge", NULL);
1173
1174	InsertConfigNode(pDevices, "ich9pci", &pDev);
1175	uHbcPCIAddress = (0x1e << 16) \| 0;
1176	uIocPCIAddress = (0x1f << 16) \| 0; // LPC controller
1177	break;
1178	}
1179	InsertConfigNode(pDev, "0", &pInst);
1180	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1181	InsertConfigNode(pInst, "Config", &pCfg);
1182	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1183	if (chipsetType == ChipsetType_ICH9)
1184	{
1185	/* Provide MCFG info */
1186	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1187	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1188
1189	#ifdef VBOX_WITH_PCI_PASSTHROUGH
1190	/* Add PCI passthrough devices */
1191	hrc = i_attachRawPCIDevices(pUVM, pBusMgr, pDevices); H();
1192	#endif
1193
1194	if (enmIommuType == IommuType_AMD)
1195	{
1196	/* AMD IOMMU. */
1197	InsertConfigNode(pDevices, "iommu-amd", &pDev);
1198	InsertConfigNode(pDev, "0", &pInst);
1199	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1200	InsertConfigNode(pInst, "Config", &pCfg);
1201	hrc = pBusMgr->assignPCIDevice("iommu-amd", pInst); H();
1202
1203	/* The AMD IOMMU device needs to know which PCI slot it's in, see @bugref{9654#c104}. */
1204	{
1205	PCIBusAddress Address;
1206	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1207	{
1208	uint32_t const u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1209	InsertConfigInteger(pCfg, "PCIAddress", u32IommuAddress);
1210	}
1211	else
1212	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1213	N_("Failed to find PCI address of the assigned IOMMU device!"));
1214	}
1215
1216	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1217	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1218	}
1219	else if (enmIommuType == IommuType_Intel)
1220	{
1221	/* Intel IOMMU. */
1222	InsertConfigNode(pDevices, "iommu-intel", &pDev);
1223	InsertConfigNode(pDev, "0", &pInst);
1224	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1225	InsertConfigNode(pInst, "Config", &pCfg);
1226	hrc = pBusMgr->assignPCIDevice("iommu-intel", pInst); H();
1227
1228	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1229	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1230	}
1231	}
1232
1233	/*
1234	* Enable the following devices: HPET, SMC and LPC on MacOS X guests or on ICH9 chipset
1235	*/
1236
1237	/*
1238	* High Precision Event Timer (HPET)
1239	*/
1240	BOOL fHPETEnabled;
1241	/* Other guests may wish to use HPET too, but MacOS X not functional without it */
1242	hrc = platformX86->COMGETTER(HPETEnabled)(&fHPETEnabled); H();
1243	/* so always enable HPET in extended profile */
1244	fHPETEnabled \|= fOsXGuest;
1245	/* HPET is always present on ICH9 */
1246	fHPETEnabled \|= (chipsetType == ChipsetType_ICH9);
1247	if (fHPETEnabled)
1248	{
1249	InsertConfigNode(pDevices, "hpet", &pDev);
1250	InsertConfigNode(pDev, "0", &pInst);
1251	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1252	InsertConfigNode(pInst, "Config", &pCfg);
1253	InsertConfigInteger(pCfg, "ICH9", (chipsetType == ChipsetType_ICH9) ? 1 : 0); /* boolean */
1254	}
1255
1256	/*
1257	* System Management Controller (SMC)
1258	*/
1259	BOOL fSmcEnabled;
1260	fSmcEnabled = fOsXGuest;
1261	if (fSmcEnabled)
1262	{
1263	InsertConfigNode(pDevices, "smc", &pDev);
1264	InsertConfigNode(pDev, "0", &pInst);
1265	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1266	InsertConfigNode(pInst, "Config", &pCfg);
1267
1268	bool fGetKeyFromRealSMC;
1269	Utf8Str strKey;
1270	vrc = getSmcDeviceKey(virtualBox, pMachine, &strKey, &fGetKeyFromRealSMC);
1271	AssertRCReturn(vrc, vrc);
1272
1273	if (!fGetKeyFromRealSMC)
1274	InsertConfigString(pCfg, "DeviceKey", strKey);
1275	InsertConfigInteger(pCfg, "GetKeyFromRealSMC", fGetKeyFromRealSMC);
1276	}
1277
1278	/*
1279	* Low Pin Count (LPC) bus
1280	*/
1281	BOOL fLpcEnabled;
1282	/** @todo implement appropriate getter */
1283	fLpcEnabled = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1284	if (fLpcEnabled)
1285	{
1286	InsertConfigNode(pDevices, "lpc", &pDev);
1287	InsertConfigNode(pDev, "0", &pInst);
1288	hrc = pBusMgr->assignPCIDevice("lpc", pInst); H();
1289	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1290	}
1291
1292	BOOL fShowRtc;
1293	fShowRtc = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1294
1295	/*
1296	* PS/2 keyboard & mouse.
1297	*/
1298	InsertConfigNode(pDevices, "pckbd", &pDev);
1299	InsertConfigNode(pDev, "0", &pInst);
1300	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1301	InsertConfigNode(pInst, "Config", &pCfg);
1302
1303	KeyboardHIDType_T aKbdHID;
1304	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
1305	if (aKbdHID != KeyboardHIDType_None)
1306	{
1307	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1308	InsertConfigString(pLunL0, "Driver", "KeyboardQueue");
1309	InsertConfigNode(pLunL0, "Config", &pCfg);
1310	InsertConfigInteger(pCfg, "QueueSize", 64);
1311
1312	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1313	InsertConfigString(pLunL1, "Driver", "MainKeyboard");
1314	}
1315
1316	PointingHIDType_T aPointingHID;
1317	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
1318	if (aPointingHID != PointingHIDType_None)
1319	{
1320	InsertConfigNode(pInst, "LUN#1", &pLunL0);
1321	InsertConfigString(pLunL0, "Driver", "MouseQueue");
1322	InsertConfigNode(pLunL0, "Config", &pCfg);
1323	InsertConfigInteger(pCfg, "QueueSize", 128);
1324
1325	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1326	InsertConfigString(pLunL1, "Driver", "MainMouse");
1327	}
1328
1329	/*
1330	* i8254 Programmable Interval Timer And Dummy Speaker
1331	*/
1332	InsertConfigNode(pDevices, "i8254", &pDev);
1333	InsertConfigNode(pDev, "0", &pInst);
1334	InsertConfigNode(pInst, "Config", &pCfg);
1335	#ifdef DEBUG
1336	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1337	#endif
1338
1339	/*
1340	* i8259 Programmable Interrupt Controller.
1341	*/
1342	InsertConfigNode(pDevices, "i8259", &pDev);
1343	InsertConfigNode(pDev, "0", &pInst);
1344	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1345	InsertConfigNode(pInst, "Config", &pCfg);
1346
1347	/*
1348	* Advanced Programmable Interrupt Controller.
1349	* SMP: Each CPU has a LAPIC, but we have a single device representing all LAPICs states,
1350	* thus only single insert
1351	*/
1352	if (fEnableAPIC)
1353	{
1354	InsertConfigNode(pDevices, "apic", &pDev);
1355	InsertConfigNode(pDev, "0", &pInst);
1356	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1357	InsertConfigNode(pInst, "Config", &pCfg);
1358	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1359	PDMAPICMODE enmAPICMode = PDMAPICMODE_APIC;
1360	if (fEnableX2APIC)
1361	enmAPICMode = PDMAPICMODE_X2APIC;
1362	else if (!fEnableAPIC)
1363	enmAPICMode = PDMAPICMODE_NONE;
1364	InsertConfigInteger(pCfg, "Mode", enmAPICMode);
1365	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1366
1367	if (fIOAPIC)
1368	{
1369	/*
1370	* I/O Advanced Programmable Interrupt Controller.
1371	*/
1372	InsertConfigNode(pDevices, "ioapic", &pDev);
1373	InsertConfigNode(pDev, "0", &pInst);
1374	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1375	InsertConfigNode(pInst, "Config", &pCfg);
1376	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1377	if (enmIommuType == IommuType_AMD)
1378	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1379	else if (enmIommuType == IommuType_Intel)
1380	{
1381	InsertConfigString(pCfg, "ChipType", "DMAR");
1382	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1383	}
1384	}
1385	}
1386
1387	/*
1388	* RTC MC146818.
1389	*/
1390	InsertConfigNode(pDevices, "mc146818", &pDev);
1391	InsertConfigNode(pDev, "0", &pInst);
1392	InsertConfigNode(pInst, "Config", &pCfg);
1393	BOOL fRTCUseUTC;
1394	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
1395	InsertConfigInteger(pCfg, "UseUTC", fRTCUseUTC ? 1 : 0);
1396
1397	/*
1398	* VGA.
1399	*/
1400	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
1401	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
1402	GraphicsControllerType_T enmGraphicsController;
1403	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
1404	switch (enmGraphicsController)
1405	{
1406	case GraphicsControllerType_Null:
1407	break;
1408	#ifdef VBOX_WITH_VMSVGA
1409	case GraphicsControllerType_VMSVGA:
1410	InsertConfigInteger(pHM, "LovelyMesaDrvWorkaround", 1); /* hits someone else's logging backdoor. */
1411	InsertConfigInteger(pNEM, "LovelyMesaDrvWorkaround", 1); /* hits someone else's logging backdoor. */
1412	InsertConfigInteger(pGcmNode, "MesaVmsvgaDrv", 1); /* hits someone else's logging backdoor. */
1413	RT_FALL_THROUGH();
1414	case GraphicsControllerType_VBoxSVGA:
1415	#endif
1416	case GraphicsControllerType_VBoxVGA:
1417	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine, pGraphicsAdapter, firmwareSettings);
1418	if (FAILED(vrc))
1419	return vrc;
1420	break;
1421	default:
1422	AssertMsgFailed(("Invalid graphicsController=%d\n", enmGraphicsController));
1423	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1424	N_("Invalid graphics controller type '%d'"), enmGraphicsController);
1425	}
1426
1427	/*
1428	* Firmware.
1429	*/
1430	FirmwareType_T eFwType = FirmwareType_BIOS;
1431	hrc = firmwareSettings->COMGETTER(FirmwareType)(&eFwType); H();
1432
1433	#ifdef VBOX_WITH_EFI
1434	BOOL fEfiEnabled = (eFwType >= FirmwareType_EFI) && (eFwType <= FirmwareType_EFIDUAL);
1435	#else
1436	BOOL fEfiEnabled = false;
1437	#endif
1438	if (!fEfiEnabled)
1439	{
1440	/*
1441	* PC Bios.
1442	*/
1443	InsertConfigNode(pDevices, "pcbios", &pDev);
1444	InsertConfigNode(pDev, "0", &pInst);
1445	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1446	InsertConfigNode(pInst, "Config", &pBiosCfg);
1447	InsertConfigInteger(pBiosCfg, "NumCPUs", cCpus);
1448	InsertConfigString(pBiosCfg, "HardDiskDevice", "piix3ide");
1449	InsertConfigString(pBiosCfg, "FloppyDevice", "i82078");
1450	InsertConfigInteger(pBiosCfg, "IOAPIC", fIOAPIC);
1451	InsertConfigInteger(pBiosCfg, "APIC", uFwAPIC);
1452	BOOL fPXEDebug;
1453	hrc = firmwareSettings->COMGETTER(PXEDebugEnabled)(&fPXEDebug); H();
1454	InsertConfigInteger(pBiosCfg, "PXEDebug", fPXEDebug);
1455	InsertConfigBytes(pBiosCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1456	BOOL fUuidLe;
1457	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1458	InsertConfigInteger(pBiosCfg, "UuidLe", fUuidLe);
1459	BOOL fAutoSerialNumGen;
1460	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1461	if (fAutoSerialNumGen)
1462	InsertConfigString(pBiosCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1463	InsertConfigNode(pBiosCfg, "NetBoot", &pNetBootCfg);
1464	InsertConfigInteger(pBiosCfg, "McfgBase", uMcfgBase);
1465	InsertConfigInteger(pBiosCfg, "McfgLength", cbMcfgLength);
1466
1467	AssertMsgReturn(SchemaDefs::MaxBootPosition <= 9, ("Too many boot devices %d\n", SchemaDefs::MaxBootPosition),
1468	VERR_INVALID_PARAMETER);
1469
1470	for (ULONG pos = 1; pos <= SchemaDefs::MaxBootPosition; ++pos)
1471	{
1472	DeviceType_T enmBootDevice;
1473	hrc = pMachine->GetBootOrder(pos, &enmBootDevice); H();
1474
1475	char szParamName[] = "BootDeviceX";
1476	szParamName[sizeof(szParamName) - 2] = (char)(pos - 1 + '0');
1477
1478	const char *pszBootDevice;
1479	switch (enmBootDevice)
1480	{
1481	case DeviceType_Null:
1482	pszBootDevice = "NONE";
1483	break;
1484	case DeviceType_HardDisk:
1485	pszBootDevice = "IDE";
1486	break;
1487	case DeviceType_DVD:
1488	pszBootDevice = "DVD";
1489	break;
1490	case DeviceType_Floppy:
1491	pszBootDevice = "FLOPPY";
1492	break;
1493	case DeviceType_Network:
1494	pszBootDevice = "LAN";
1495	break;
1496	default:
1497	AssertMsgFailed(("Invalid enmBootDevice=%d\n", enmBootDevice));
1498	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1499	N_("Invalid boot device '%d'"), enmBootDevice);
1500	}
1501	InsertConfigString(pBiosCfg, szParamName, pszBootDevice);
1502	}
1503
1504	/** @todo @bugref{7145}: We might want to enable this by default for new VMs. For now,
1505	* this is required for Windows 2012 guests. */
1506	if (osTypeId == GUEST_OS_ID_STR_X64("Windows2012"))
1507	InsertConfigInteger(pBiosCfg, "DmiExposeMemoryTable", 1); /* boolean */
1508	}
1509	else
1510	{
1511	/* Autodetect firmware type, basing on guest type */
1512	if (eFwType == FirmwareType_EFI)
1513	eFwType = fIsGuest64Bit ? FirmwareType_EFI64 : FirmwareType_EFI32;
1514	bool const f64BitEntry = eFwType == FirmwareType_EFI64;
1515
1516	Assert(eFwType == FirmwareType_EFI64 \|\| eFwType == FirmwareType_EFI32 \|\| eFwType == FirmwareType_EFIDUAL);
1517	#ifdef VBOX_WITH_EFI_IN_DD2
1518	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "VBoxEFIDual.fd"
1519	: eFwType == FirmwareType_EFI32 ? "VBoxEFI32.fd"
1520	: "VBoxEFI64.fd";
1521	#else
1522	Utf8Str efiRomFile;
1523	vrc = findEfiRom(virtualBox, PlatformArchitecture_x86, eFwType, &efiRomFile);
1524	AssertRCReturn(vrc, vrc);
1525	const char *pszEfiRomFile = efiRomFile.c_str();
1526	#endif
1527
1528	/* Get boot args */
1529	Utf8Str bootArgs;
1530	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiBootArgs", &bootArgs);
1531
1532	/* Get device props */
1533	Utf8Str deviceProps;
1534	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiDeviceProps", &deviceProps);
1535
1536	/* Get NVRAM file name */
1537	Utf8Str strNvram = mptrNvramStore->i_getNonVolatileStorageFile();
1538
1539	BOOL fUuidLe;
1540	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1541
1542	BOOL fAutoSerialNumGen;
1543	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1544
1545	/* Get graphics mode settings */
1546	uint32_t u32GraphicsMode = UINT32_MAX;
1547	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsMode", &strTmp);
1548	if (strTmp.isEmpty())
1549	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGopMode", &strTmp);
1550	if (!strTmp.isEmpty())
1551	u32GraphicsMode = strTmp.toUInt32();
1552
1553	/* Get graphics resolution settings, with some sanity checking */
1554	Utf8Str strResolution;
1555	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsResolution", &strResolution);
1556	if (!strResolution.isEmpty())
1557	{
1558	size_t pos = strResolution.find("x");
1559	if (pos != strResolution.npos)
1560	{
1561	Utf8Str strH, strV;
1562	strH.assignEx(strResolution, 0, pos);
1563	strV.assignEx(strResolution, pos+1, strResolution.length()-pos-1);
1564	uint32_t u32H = strH.toUInt32();
1565	uint32_t u32V = strV.toUInt32();
1566	if (u32H == 0 \|\| u32V == 0)
1567	strResolution.setNull();
1568	}
1569	else
1570	strResolution.setNull();
1571	}
1572	else
1573	{
1574	uint32_t u32H = 0;
1575	uint32_t u32V = 0;
1576	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiHorizontalResolution", &strTmp);
1577	if (strTmp.isEmpty())
1578	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaHorizontalResolution", &strTmp);
1579	if (!strTmp.isEmpty())
1580	u32H = strTmp.toUInt32();
1581
1582	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiVerticalResolution", &strTmp);
1583	if (strTmp.isEmpty())
1584	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaVerticalResolution", &strTmp);
1585	if (!strTmp.isEmpty())
1586	u32V = strTmp.toUInt32();
1587	if (u32H != 0 && u32V != 0)
1588	strResolution = Utf8StrFmt("%ux%u", u32H, u32V);
1589	}
1590
1591	/*
1592	* EFI subtree.
1593	*/
1594	InsertConfigNode(pDevices, "efi", &pDev);
1595	InsertConfigNode(pDev, "0", &pInst);
1596	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1597	InsertConfigNode(pInst, "Config", &pCfg);
1598	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1599	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1600	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1601	InsertConfigString(pCfg, "EfiRom", pszEfiRomFile);
1602	InsertConfigString(pCfg, "BootArgs", bootArgs);
1603	InsertConfigString(pCfg, "DeviceProps", deviceProps);
1604	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1605	InsertConfigInteger(pCfg, "APIC", uFwAPIC);
1606	InsertConfigBytes(pCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1607	InsertConfigInteger(pCfg, "UuidLe", fUuidLe);
1608	if (fAutoSerialNumGen)
1609	InsertConfigString(pCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1610	InsertConfigInteger(pCfg, "64BitEntry", f64BitEntry); /* boolean */
1611	InsertConfigString(pCfg, "NvramFile", strNvram);
1612	if (u32GraphicsMode != UINT32_MAX)
1613	InsertConfigInteger(pCfg, "GraphicsMode", u32GraphicsMode);
1614	if (!strResolution.isEmpty())
1615	InsertConfigString(pCfg, "GraphicsResolution", strResolution);
1616
1617	/* For OS X guests we'll force passing host's DMI info to the guest */
1618	if (fOsXGuest)
1619	{
1620	InsertConfigInteger(pCfg, "DmiUseHostInfo", 1);
1621	InsertConfigInteger(pCfg, "DmiExposeMemoryTable", 1);
1622	}
1623
1624	/* Attach the NVRAM storage driver. */
1625	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1626	InsertConfigString(pLunL0, "Driver", "NvramStore");
1627	}
1628
1629	/*
1630	* The USB Controllers.
1631	*/
1632	PCFGMNODE pUsbDevices = NULL;
1633	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, aKbdHID, aPointingHID, &pUsbDevices);
1634
1635	/*
1636	* Storage controllers.
1637	*/
1638	bool fFdcEnabled = false;
1639	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
1640	pDevices, pUsbDevices, pBiosCfg, &fFdcEnabled); VRC();
1641
1642	/*
1643	* Network adapters
1644	*/
1645	std::list<BootNic> llBootNics;
1646	vrc = i_configNetworkCtrls(pMachine, platformProperties, chipsetType, pBusMgr,
1647	pVMM, pUVM, pDevices, llBootNics); VRC();
1648
1649	/*
1650	* Build network boot information and transfer it to the BIOS.
1651	*/
1652	if (pNetBootCfg && !llBootNics.empty()) /* NetBoot node doesn't exist for EFI! */
1653	{
1654	llBootNics.sort(); /* Sort the list by boot priority. */
1655
1656	char achBootIdx[] = "0";
1657	unsigned uBootIdx = 0;
1658
1659	for (std::list<BootNic>::iterator it = llBootNics.begin(); it != llBootNics.end(); ++it)
1660	{
1661	/* A NIC with priority 0 is only used if it's first in the list. */
1662	if (it->mBootPrio == 0 && uBootIdx != 0)
1663	break;
1664
1665	PCFGMNODE pNetBtDevCfg;
1666	achBootIdx[0] = (char)('0' + uBootIdx++); /* Boot device order. */
1667	InsertConfigNode(pNetBootCfg, achBootIdx, &pNetBtDevCfg);
1668	InsertConfigInteger(pNetBtDevCfg, "NIC", it->mInstance);
1669	InsertConfigInteger(pNetBtDevCfg, "PCIBusNo", it->mPCIAddress.miBus);
1670	InsertConfigInteger(pNetBtDevCfg, "PCIDeviceNo", it->mPCIAddress.miDevice);
1671	InsertConfigInteger(pNetBtDevCfg, "PCIFunctionNo", it->mPCIAddress.miFn);
1672	}
1673	}
1674
1675	/*
1676	* Serial (UART) Ports
1677	*/
1678	/* serial enabled mask to be passed to dev ACPI */
1679	uint16_t auSerialIoPortBase[SchemaDefs::SerialPortCount] = {0};
1680	uint8_t auSerialIrq[SchemaDefs::SerialPortCount] = {0};
1681	InsertConfigNode(pDevices, "serial", &pDev);
1682	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::SerialPortCount; ++ulInstance)
1683	{
1684	ComPtr<ISerialPort> serialPort;
1685	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
1686	BOOL fEnabledSerPort = FALSE;
1687	if (serialPort)
1688	{
1689	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
1690	}
1691	if (!fEnabledSerPort)
1692	{
1693	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
1694	continue;
1695	}
1696
1697	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1698	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1699	InsertConfigNode(pInst, "Config", &pCfg);
1700
1701	ULONG ulIRQ;
1702	hrc = serialPort->COMGETTER(IRQ)(&ulIRQ); H();
1703	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1704	auSerialIrq[ulInstance] = (uint8_t)ulIRQ;
1705
1706	ULONG ulIOBase;
1707	hrc = serialPort->COMGETTER(IOAddress)(&ulIOBase); H();
1708	InsertConfigInteger(pCfg, "IOAddress", ulIOBase);
1709	auSerialIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1710
1711	BOOL fServer;
1712	hrc = serialPort->COMGETTER(Server)(&fServer); H();
1713	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
1714	UartType_T eUartType;
1715	const char *pszUartType;
1716	hrc = serialPort->COMGETTER(UartType)(&eUartType); H();
1717	switch (eUartType)
1718	{
1719	case UartType_U16450: pszUartType = "16450"; break;
1720	case UartType_U16750: pszUartType = "16750"; break;
1721	default: AssertFailed(); RT_FALL_THRU();
1722	case UartType_U16550A: pszUartType = "16550A"; break;
1723	}
1724	InsertConfigString(pCfg, "UartType", pszUartType);
1725
1726	PortMode_T eHostMode;
1727	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
1728
1729	m_aeSerialPortMode[ulInstance] = eHostMode;
1730	if (eHostMode != PortMode_Disconnected)
1731	{
1732	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
1733	if (RT_FAILURE(vrc))
1734	return vrc;
1735	}
1736	}
1737
1738	/*
1739	* Parallel (LPT) Ports
1740	*/
1741	/* parallel enabled mask to be passed to dev ACPI */
1742	uint16_t auParallelIoPortBase[SchemaDefs::ParallelPortCount] = {0};
1743	uint8_t auParallelIrq[SchemaDefs::ParallelPortCount] = {0};
1744	InsertConfigNode(pDevices, "parallel", &pDev);
1745	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::ParallelPortCount; ++ulInstance)
1746	{
1747	ComPtr<IParallelPort> parallelPort;
1748	hrc = pMachine->GetParallelPort(ulInstance, parallelPort.asOutParam()); H();
1749	BOOL fEnabledParPort = FALSE;
1750	if (parallelPort)
1751	{
1752	hrc = parallelPort->COMGETTER(Enabled)(&fEnabledParPort); H();
1753	}
1754	if (!fEnabledParPort)
1755	continue;
1756
1757	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1758	InsertConfigNode(pInst, "Config", &pCfg);
1759
1760	ULONG ulIRQ;
1761	hrc = parallelPort->COMGETTER(IRQ)(&ulIRQ); H();
1762	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1763	auParallelIrq[ulInstance] = (uint8_t)ulIRQ;
1764	ULONG ulIOBase;
1765	hrc = parallelPort->COMGETTER(IOBase)(&ulIOBase); H();
1766	InsertConfigInteger(pCfg, "IOBase", ulIOBase);
1767	auParallelIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1768
1769	hrc = parallelPort->COMGETTER(Path)(bstr.asOutParam()); H();
1770	if (!bstr.isEmpty())
1771	{
1772	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1773	InsertConfigString(pLunL0, "Driver", "HostParallel");
1774	InsertConfigNode(pLunL0, "Config", &pLunL1);
1775	InsertConfigString(pLunL1, "DevicePath", bstr);
1776	}
1777	}
1778
1779	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices); VRC();
1780
1781	/*
1782	* Audio configuration.
1783	*/
1784	bool fAudioEnabled = false;
1785	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
1786	fOsXGuest, &fAudioEnabled); VRC();
1787
1788	#if defined(VBOX_WITH_TPM)
1789	/*
1790	* Configure the Trusted Platform Module.
1791	*/
1792	ComObjPtr<ITrustedPlatformModule> ptrTpm;
1793	TpmType_T enmTpmType = TpmType_None;
1794
1795	hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
1796	hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
1797	if (enmTpmType != TpmType_None)
1798	{
1799	InsertConfigNode(pDevices, "tpm", &pDev);
1800	InsertConfigNode(pDev, "0", &pInst);
1801	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1802	InsertConfigNode(pInst, "Config", &pCfg);
1803	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1804
1805	switch (enmTpmType)
1806	{
1807	case TpmType_v1_2:
1808	case TpmType_v2_0:
1809	InsertConfigString(pLunL0, "Driver", "TpmEmuTpms");
1810	InsertConfigNode(pLunL0, "Config", &pCfg);
1811	InsertConfigInteger(pCfg, "TpmVersion", enmTpmType == TpmType_v1_2 ? 1 : 2);
1812	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1813	InsertConfigString(pLunL1, "Driver", "NvramStore");
1814	break;
1815	case TpmType_Host:
1816	#if defined(RT_OS_LINUX) \|\| defined(RT_OS_WINDOWS)
1817	InsertConfigString(pLunL0, "Driver", "TpmHost");
1818	InsertConfigNode(pLunL0, "Config", &pCfg);
1819	#endif
1820	break;
1821	case TpmType_Swtpm:
1822	hrc = ptrTpm->COMGETTER(Location)(bstr.asOutParam()); H();
1823	InsertConfigString(pLunL0, "Driver", "TpmEmu");
1824	InsertConfigNode(pLunL0, "Config", &pCfg);
1825	InsertConfigString(pCfg, "Location", bstr);
1826	break;
1827	default:
1828	AssertFailedBreak();
1829	}
1830	}
1831	#endif
1832
1833	/*
1834	* ACPI
1835	*/
1836	BOOL fACPI;
1837	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
1838	if (fACPI)
1839	{
1840	/* Always show the CPU leafs when we have multiple VCPUs or when the IO-APIC is enabled.
1841	* The Windows SMP kernel needs a CPU leaf or else its idle loop will burn cpu cycles; the
1842	* intelppm driver refuses to register an idle state handler.
1843	* Always show CPU leafs for OS X guests. */
1844	BOOL fShowCpu = fOsXGuest;
1845	if (cCpus > 1 \|\| fIOAPIC)
1846	fShowCpu = true;
1847
1848	BOOL fCpuHotPlug;
1849	hrc = pMachine->COMGETTER(CPUHotPlugEnabled)(&fCpuHotPlug); H();
1850
1851	InsertConfigNode(pDevices, "acpi", &pDev);
1852	InsertConfigNode(pDev, "0", &pInst);
1853	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1854	InsertConfigNode(pInst, "Config", &pCfg);
1855	hrc = pBusMgr->assignPCIDevice("acpi", pInst); H();
1856
1857	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1858
1859	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1860	InsertConfigInteger(pCfg, "FdcEnabled", fFdcEnabled);
1861	InsertConfigInteger(pCfg, "HpetEnabled", fHPETEnabled);
1862	InsertConfigInteger(pCfg, "SmcEnabled", fSmcEnabled);
1863	InsertConfigInteger(pCfg, "ShowRtc", fShowRtc);
1864	if (fOsXGuest && !llBootNics.empty())
1865	{
1866	BootNic aNic = llBootNics.front();
1867	uint32_t u32NicPCIAddr = (aNic.mPCIAddress.miDevice << 16) \| aNic.mPCIAddress.miFn;
1868	InsertConfigInteger(pCfg, "NicPciAddress", u32NicPCIAddr);
1869	}
1870	if (fOsXGuest && fAudioEnabled)
1871	{
1872	PCIBusAddress Address;
1873	if (pBusMgr->findPCIAddress("hda", 0, Address))
1874	{
1875	uint32_t u32AudioPCIAddr = (Address.miDevice << 16) \| Address.miFn;
1876	InsertConfigInteger(pCfg, "AudioPciAddress", u32AudioPCIAddr);
1877	}
1878	}
1879	if (fOsXGuest)
1880	{
1881	PCIBusAddress Address;
1882	if (pBusMgr->findPCIAddress("nvme", 0, Address))
1883	{
1884	uint32_t u32NvmePCIAddr = (Address.miDevice << 16) \| Address.miFn;
1885	InsertConfigInteger(pCfg, "NvmePciAddress", u32NvmePCIAddr);
1886	}
1887	}
1888	if (enmIommuType == IommuType_AMD)
1889	{
1890	PCIBusAddress Address;
1891	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1892	{
1893	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1894	InsertConfigInteger(pCfg, "IommuAmdEnabled", true);
1895	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1896	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1897	{
1898	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1899	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1900	}
1901	else
1902	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1903	N_("AMD IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1904	}
1905	}
1906	else if (enmIommuType == IommuType_Intel)
1907	{
1908	PCIBusAddress Address;
1909	if (pBusMgr->findPCIAddress("iommu-intel", 0, Address))
1910	{
1911	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1912	InsertConfigInteger(pCfg, "IommuIntelEnabled", true);
1913	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1914	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1915	{
1916	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1917	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1918	}
1919	else
1920	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1921	N_("Intel IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1922	}
1923	}
1924
1925	InsertConfigInteger(pCfg, "IocPciAddress", uIocPCIAddress);
1926	if (chipsetType == ChipsetType_ICH9)
1927	{
1928	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1929	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1930	/* 64-bit prefetch window root resource: Only for ICH9 and if PAE or Long Mode is enabled (@bugref{5454}). */
1931	if (fIsGuest64Bit \|\| fEnablePAE)
1932	InsertConfigInteger(pCfg, "PciPref64Enabled", 1);
1933	}
1934	InsertConfigInteger(pCfg, "HostBusPciAddress", uHbcPCIAddress);
1935	InsertConfigInteger(pCfg, "ShowCpu", fShowCpu);
1936	InsertConfigInteger(pCfg, "CpuHotPlug", fCpuHotPlug);
1937
1938	InsertConfigInteger(pCfg, "Serial0IoPortBase", auSerialIoPortBase[0]);
1939	InsertConfigInteger(pCfg, "Serial0Irq", auSerialIrq[0]);
1940
1941	InsertConfigInteger(pCfg, "Serial1IoPortBase", auSerialIoPortBase[1]);
1942	InsertConfigInteger(pCfg, "Serial1Irq", auSerialIrq[1]);
1943
1944	if (auSerialIoPortBase[2])
1945	{
1946	InsertConfigInteger(pCfg, "Serial2IoPortBase", auSerialIoPortBase[2]);
1947	InsertConfigInteger(pCfg, "Serial2Irq", auSerialIrq[2]);
1948	}
1949
1950	if (auSerialIoPortBase[3])
1951	{
1952	InsertConfigInteger(pCfg, "Serial3IoPortBase", auSerialIoPortBase[3]);
1953	InsertConfigInteger(pCfg, "Serial3Irq", auSerialIrq[3]);
1954	}
1955
1956	InsertConfigInteger(pCfg, "Parallel0IoPortBase", auParallelIoPortBase[0]);
1957	InsertConfigInteger(pCfg, "Parallel0Irq", auParallelIrq[0]);
1958
1959	InsertConfigInteger(pCfg, "Parallel1IoPortBase", auParallelIoPortBase[1]);
1960	InsertConfigInteger(pCfg, "Parallel1Irq", auParallelIrq[1]);
1961
1962	#if defined(VBOX_WITH_TPM)
1963	switch (enmTpmType)
1964	{
1965	case TpmType_v1_2:
1966	InsertConfigString(pCfg, "TpmMode", "tis1.2");
1967	break;
1968	case TpmType_v2_0:
1969	InsertConfigString(pCfg, "TpmMode", "fifo2.0");
1970	break;
1971	/** @todo Host and swtpm. */
1972	default:
1973	break;
1974	}
1975	#endif
1976
1977	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1978	InsertConfigString(pLunL0, "Driver", "ACPIHost");
1979	InsertConfigNode(pLunL0, "Config", &pCfg);
1980
1981	/* Attach the dummy CPU drivers */
1982	for (ULONG iCpuCurr = 1; iCpuCurr < cCpus; iCpuCurr++)
1983	{
1984	BOOL fCpuAttached = true;
1985
1986	if (fCpuHotPlug)
1987	{
1988	hrc = pMachine->GetCPUStatus(iCpuCurr, &fCpuAttached); H();
1989	}
1990
1991	if (fCpuAttached)
1992	{
1993	InsertConfigNode(pInst, Utf8StrFmt("LUN#%u", iCpuCurr).c_str(), &pLunL0);
1994	InsertConfigString(pLunL0, "Driver", "ACPICpu");
1995	InsertConfigNode(pLunL0, "Config", &pCfg);
1996	}
1997	}
1998	}
1999
2000	/*
2001	* Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
2002	*/
2003	vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
2004	}
2005	catch (ConfigError &x)
2006	{
2007	// InsertConfig threw something:
2008	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
2009	return x.m_vrc;
2010	}
2011	catch (HRESULT hrcXcpt)
2012	{
2013	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
2014	}
2015
2016	#ifdef VBOX_WITH_EXTPACK
2017	/*
2018	* Call the extension pack hooks if everything went well thus far.
2019	*/
2020	if (RT_SUCCESS(vrc))
2021	{
2022	pAlock->release();
2023	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
2024	pAlock->acquire();
2025	}
2026	#endif
2027
2028	/*
2029	* Apply the CFGM overlay.
2030	*/
2031	if (RT_SUCCESS(vrc))
2032	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
2033
2034	/*
2035	* Dump all extradata API settings tweaks, both global and per VM.
2036	*/
2037	if (RT_SUCCESS(vrc))
2038	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
2039
2040	#undef H
2041
2042	pAlock->release(); /* Avoid triggering the lock order inversion check. */
2043
2044	/*
2045	* Register VM state change handler.
2046	*/
2047	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
2048	AssertRC(vrc2);
2049	if (RT_SUCCESS(vrc))
2050	vrc = vrc2;
2051
2052	/*
2053	* Register VM runtime error handler.
2054	*/
2055	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
2056	AssertRC(vrc2);
2057	if (RT_SUCCESS(vrc))
2058	vrc = vrc2;
2059
2060	pAlock->acquire();
2061
2062	LogFlowFunc(("vrc = %Rrc\n", vrc));
2063	LogFlowFuncLeave();
2064
2065	return vrc;
2066	}

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigX86.cpp@ 104516

以其他格式下載: