VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp@ 57808

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1/* $Id: BusAssignmentManager.cpp 57808 2015-09-17 16:09:23Z vboxsync $ */
2
3/** @file
4 *
5 * VirtualBox bus slots assignment manager
6 */
7
8/*
9 * Copyright (C) 2010-2014 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.alldomusa.eu.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19#include "BusAssignmentManager.h"
20
21#include <iprt/asm.h>
22#include <iprt/string.h>
23
24#include <VBox/vmm/cfgm.h>
25#include <VBox/com/array.h>
26
27
28#include "PCIDeviceAttachmentImpl.h"
29
30#include <map>
31#include <vector>
32#include <algorithm>
33
34struct DeviceAssignmentRule
35{
36 const char* pszName;
37 int iBus;
38 int iDevice;
39 int iFn;
40 int iPriority;
41};
42
43struct DeviceAliasRule
44{
45 const char* pszDevName;
46 const char* pszDevAlias;
47};
48
49/* Those rules define PCI slots assignment */
50
51/* Device Bus Device Function Priority */
52
53/* Generic rules */
54static const DeviceAssignmentRule aGenericRules[] =
55{
56 /* VGA controller */
57 {"vga", 0, 2, 0, 0},
58 {"virtio-gpu", 0, 15, 0, 0},
59
60 /* VMM device */
61 {"VMMDev", 0, 4, 0, 0},
62
63 /* Audio controllers */
64 {"ichac97", 0, 5, 0, 0},
65 {"hda", 0, 5, 0, 0},
66
67 /* Storage controllers */
68 {"lsilogic", 0, 20, 0, 1},
69 {"buslogic", 0, 21, 0, 1},
70 {"lsilogicsas", 0, 22, 0, 1},
71 {"nvme", 0, 14, 0, 1},
72
73 /* USB controllers */
74 {"usb-ohci", 0, 6, 0, 0},
75 {"usb-ehci", 0, 11, 0, 0},
76 {"usb-xhci", 0, 12, 0, 0},
77
78 /* ACPI controller */
79 {"acpi", 0, 7, 0, 0},
80
81 /* Network controllers */
82 /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
83 * next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
84 * swap places, i.e. the first card goes to ID 17=0x11. */
85 {"nic", 0, 3, 0, 1},
86 {"nic", 0, 8, 0, 1},
87 {"nic", 0, 9, 0, 1},
88 {"nic", 0, 10, 0, 1},
89 {"nic", 0, 16, 0, 1},
90 {"nic", 0, 17, 0, 1},
91 {"nic", 0, 18, 0, 1},
92 {"nic", 0, 19, 0, 1},
93
94 /* ISA/LPC controller */
95 {"lpc", 0, 31, 0, 0},
96
97 { NULL, -1, -1, -1, 0}
98};
99
100/* PIIX3 chipset rules */
101static const DeviceAssignmentRule aPiix3Rules[] =
102{
103 {"piix3ide", 0, 1, 1, 0},
104 {"ahci", 0, 13, 0, 1},
105 {"pcibridge", 0, 24, 0, 0},
106 {"pcibridge", 0, 25, 0, 0},
107 { NULL, -1, -1, -1, 0}
108};
109
110
111/* ICH9 chipset rules */
112static const DeviceAssignmentRule aIch9Rules[] =
113{
114 /* Host Controller */
115 {"i82801", 0, 30, 0, 0},
116
117 /* Those are functions of LPC at 00:1e:00 */
118 /**
119 * Please note, that for devices being functions, like we do here, device 0
120 * must be multifunction, i.e. have header type 0x80. Our LPC device is.
121 * Alternative approach is to assign separate slot to each device.
122 */
123 {"piix3ide", 0, 31, 1, 2},
124 {"ahci", 0, 31, 2, 2},
125 {"smbus", 0, 31, 3, 2},
126 {"usb-ohci", 0, 31, 4, 2},
127 {"usb-ehci", 0, 31, 5, 2},
128 {"thermal", 0, 31, 6, 2},
129
130 /* to make sure rule never used before rules assigning devices on it */
131 {"ich9pcibridge", 0, 24, 0, 10},
132 {"ich9pcibridge", 0, 25, 0, 10},
133 {"ich9pcibridge", 1, 24, 0, 9},
134 {"ich9pcibridge", 1, 25, 0, 9},
135 {"ich9pcibridge", 2, 24, 0, 8},
136 {"ich9pcibridge", 2, 25, 0, 8},
137 {"ich9pcibridge", 3, 24, 0, 7},
138 {"ich9pcibridge", 3, 25, 0, 7},
139 {"ich9pcibridge", 4, 24, 0, 6},
140 {"ich9pcibridge", 4, 25, 0, 6},
141 {"ich9pcibridge", 5, 24, 0, 5},
142 {"ich9pcibridge", 5, 25, 0, 5},
143
144 /* Storage controllers */
145 {"ahci", 1, 0, 0, 0},
146 {"ahci", 1, 1, 0, 0},
147 {"ahci", 1, 2, 0, 0},
148 {"ahci", 1, 3, 0, 0},
149 {"ahci", 1, 4, 0, 0},
150 {"ahci", 1, 5, 0, 0},
151 {"ahci", 1, 6, 0, 0},
152 {"lsilogic", 1, 7, 0, 0},
153 {"lsilogic", 1, 8, 0, 0},
154 {"lsilogic", 1, 9, 0, 0},
155 {"lsilogic", 1, 10, 0, 0},
156 {"lsilogic", 1, 11, 0, 0},
157 {"lsilogic", 1, 12, 0, 0},
158 {"lsilogic", 1, 13, 0, 0},
159 {"buslogic", 1, 14, 0, 0},
160 {"buslogic", 1, 15, 0, 0},
161 {"buslogic", 1, 16, 0, 0},
162 {"buslogic", 1, 17, 0, 0},
163 {"buslogic", 1, 18, 0, 0},
164 {"buslogic", 1, 19, 0, 0},
165 {"buslogic", 1, 20, 0, 0},
166 {"lsilogicsas", 1, 21, 0, 0},
167 {"lsilogicsas", 1, 26, 0, 0},
168 {"lsilogicsas", 1, 27, 0, 0},
169 {"lsilogicsas", 1, 28, 0, 0},
170 {"lsilogicsas", 1, 29, 0, 0},
171 {"lsilogicsas", 1, 30, 0, 0},
172 {"lsilogicsas", 1, 31, 0, 0},
173 {"nvme", 1, 32, 0, 0},
174 {"nvme", 1, 33, 0, 0},
175 {"nvme", 1, 34, 0, 0},
176 {"nvme", 1, 35, 0, 0},
177 {"nvme", 1, 36, 0, 0},
178 {"nvme", 1, 37, 0, 0},
179 {"nvme", 1, 38, 0, 0},
180
181 /* NICs */
182 {"nic", 2, 0, 0, 0},
183 {"nic", 2, 1, 0, 0},
184 {"nic", 2, 2, 0, 0},
185 {"nic", 2, 3, 0, 0},
186 {"nic", 2, 4, 0, 0},
187 {"nic", 2, 5, 0, 0},
188 {"nic", 2, 6, 0, 0},
189 {"nic", 2, 7, 0, 0},
190 {"nic", 2, 8, 0, 0},
191 {"nic", 2, 9, 0, 0},
192 {"nic", 2, 10, 0, 0},
193 {"nic", 2, 11, 0, 0},
194 {"nic", 2, 12, 0, 0},
195 {"nic", 2, 13, 0, 0},
196 {"nic", 2, 14, 0, 0},
197 {"nic", 2, 15, 0, 0},
198 {"nic", 2, 16, 0, 0},
199 {"nic", 2, 17, 0, 0},
200 {"nic", 2, 18, 0, 0},
201 {"nic", 2, 19, 0, 0},
202 {"nic", 2, 20, 0, 0},
203 {"nic", 2, 21, 0, 0},
204 {"nic", 2, 26, 0, 0},
205 {"nic", 2, 27, 0, 0},
206 {"nic", 2, 28, 0, 0},
207 {"nic", 2, 29, 0, 0},
208 {"nic", 2, 30, 0, 0},
209 {"nic", 2, 31, 0, 0},
210
211 { NULL, -1, -1, -1, 0}
212};
213
214/* Aliasing rules */
215static const DeviceAliasRule aDeviceAliases[] =
216{
217 {"e1000", "nic"},
218 {"pcnet", "nic"},
219 {"virtio-net", "nic"},
220 {"ahci", "storage"},
221 {"lsilogic", "storage"},
222 {"buslogic", "storage"},
223 {"lsilogicsas", "storage"},
224 {"nvme", "storage"}
225};
226
227struct BusAssignmentManager::State
228{
229 struct PCIDeviceRecord
230 {
231 char szDevName[32];
232 PCIBusAddress HostAddress;
233
234 PCIDeviceRecord(const char* pszName, PCIBusAddress aHostAddress)
235 {
236 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
237 this->HostAddress = aHostAddress;
238 }
239
240 PCIDeviceRecord(const char* pszName)
241 {
242 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
243 }
244
245 bool operator<(const PCIDeviceRecord &a) const
246 {
247 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
248 }
249
250 bool operator==(const PCIDeviceRecord &a) const
251 {
252 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
253 }
254 };
255
256 typedef std::map <PCIBusAddress,PCIDeviceRecord > PCIMap;
257 typedef std::vector<PCIBusAddress> PCIAddrList;
258 typedef std::vector<const DeviceAssignmentRule*> PCIRulesList;
259 typedef std::map <PCIDeviceRecord,PCIAddrList > ReversePCIMap;
260
261 volatile int32_t cRefCnt;
262 ChipsetType_T mChipsetType;
263 PCIMap mPCIMap;
264 ReversePCIMap mReversePCIMap;
265
266 State()
267 : cRefCnt(1), mChipsetType(ChipsetType_Null)
268 {}
269 ~State()
270 {}
271
272 HRESULT init(ChipsetType_T chipsetType);
273
274 HRESULT record(const char* pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
275 HRESULT autoAssign(const char* pszName, PCIBusAddress& Address);
276 bool checkAvailable(PCIBusAddress& Address);
277 bool findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address);
278
279 const char* findAlias(const char* pszName);
280 void addMatchingRules(const char* pszName, PCIRulesList& aList);
281 void listAttachedPCIDevices(std::vector<ComPtr<IPCIDeviceAttachment> > &aAttached);
282};
283
284HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType)
285{
286 mChipsetType = chipsetType;
287 return S_OK;
288}
289
290HRESULT BusAssignmentManager::State::record(const char* pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
291{
292 PCIDeviceRecord devRec(pszName, HostAddress);
293
294 /* Remember address -> device mapping */
295 mPCIMap.insert(PCIMap::value_type(Address, devRec));
296
297 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
298 if (it == mReversePCIMap.end())
299 {
300 mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
301 it = mReversePCIMap.find(devRec);
302 }
303
304 /* Remember device name -> addresses mapping */
305 it->second.push_back(Address);
306
307 return S_OK;
308}
309
310bool BusAssignmentManager::State::findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address)
311{
312 PCIDeviceRecord devRec(pszDevName);
313
314 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
315 if (it == mReversePCIMap.end())
316 return false;
317
318 if (iInstance >= (int)it->second.size())
319 return false;
320
321 Address = it->second[iInstance];
322 return true;
323}
324
325void BusAssignmentManager::State::addMatchingRules(const char* pszName, PCIRulesList& aList)
326{
327 size_t iRuleset, iRule;
328 const DeviceAssignmentRule* aArrays[2] = {aGenericRules, NULL};
329
330 switch (mChipsetType)
331 {
332 case ChipsetType_PIIX3:
333 aArrays[1] = aPiix3Rules;
334 break;
335 case ChipsetType_ICH9:
336 aArrays[1] = aIch9Rules;
337 break;
338 default:
339 Assert(false);
340 break;
341 }
342
343 for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
344 {
345 if (aArrays[iRuleset] == NULL)
346 continue;
347
348 for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
349 {
350 if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
351 aList.push_back(&aArrays[iRuleset][iRule]);
352 }
353 }
354}
355
356const char* BusAssignmentManager::State::findAlias(const char* pszDev)
357{
358 for (size_t iAlias = 0; iAlias < RT_ELEMENTS(aDeviceAliases); iAlias++)
359 {
360 if (strcmp(pszDev, aDeviceAliases[iAlias].pszDevName) == 0)
361 return aDeviceAliases[iAlias].pszDevAlias;
362 }
363 return NULL;
364}
365
366static bool RuleComparator(const DeviceAssignmentRule* r1, const DeviceAssignmentRule* r2)
367{
368 return (r1->iPriority > r2->iPriority);
369}
370
371HRESULT BusAssignmentManager::State::autoAssign(const char* pszName, PCIBusAddress& Address)
372{
373 PCIRulesList matchingRules;
374
375 addMatchingRules(pszName, matchingRules);
376 const char* pszAlias = findAlias(pszName);
377 if (pszAlias)
378 addMatchingRules(pszAlias, matchingRules);
379
380 AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
381
382 stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
383
384 for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
385 {
386 const DeviceAssignmentRule* rule = matchingRules[iRule];
387
388 Address.miBus = rule->iBus;
389 Address.miDevice = rule->iDevice;
390 Address.miFn = rule->iFn;
391
392 if (checkAvailable(Address))
393 return S_OK;
394 }
395 AssertMsgFailed(("All possible candidate positions for %s exhausted\n", pszName));
396
397 return E_INVALIDARG;
398}
399
400bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
401{
402 PCIMap::const_iterator it = mPCIMap.find(Address);
403
404 return (it == mPCIMap.end());
405}
406
407void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<ComPtr<IPCIDeviceAttachment> > &aAttached)
408{
409 aAttached.resize(mPCIMap.size());
410
411 size_t i = 0;
412 ComObjPtr<PCIDeviceAttachment> dev;
413 for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
414 {
415 dev.createObject();
416 com::Bstr devname(it->second.szDevName);
417 dev->init(NULL, devname,
418 it->second.HostAddress.valid() ? it->second.HostAddress.asLong() : -1,
419 it->first.asLong(), it->second.HostAddress.valid());
420 dev.queryInterfaceTo(aAttached[i].asOutParam());
421 }
422}
423
424BusAssignmentManager::BusAssignmentManager()
425 : pState(NULL)
426{
427 pState = new State();
428 Assert(pState);
429}
430
431BusAssignmentManager::~BusAssignmentManager()
432{
433 if (pState)
434 {
435 delete pState;
436 pState = NULL;
437 }
438}
439
440BusAssignmentManager* BusAssignmentManager::createInstance(ChipsetType_T chipsetType)
441{
442 BusAssignmentManager* pInstance = new BusAssignmentManager();
443 pInstance->pState->init(chipsetType);
444 Assert(pInstance);
445 return pInstance;
446}
447
448void BusAssignmentManager::AddRef()
449{
450 ASMAtomicIncS32(&pState->cRefCnt);
451}
452void BusAssignmentManager::Release()
453{
454 if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
455 delete this;
456}
457
458DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char* pszName, uint64_t u64)
459{
460 int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
461 if (RT_FAILURE(vrc))
462 return E_INVALIDARG;
463
464 return S_OK;
465}
466
467HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char* pszDevName,
468 PCFGMNODE pCfg,
469 PCIBusAddress& GuestAddress,
470 PCIBusAddress HostAddress,
471 bool fGuestAddressRequired)
472{
473 HRESULT rc = S_OK;
474
475 if (!GuestAddress.valid())
476 rc = pState->autoAssign(pszDevName, GuestAddress);
477 else
478 {
479 bool fAvailable = pState->checkAvailable(GuestAddress);
480
481 if (!fAvailable)
482 {
483 if (fGuestAddressRequired)
484 rc = E_ACCESSDENIED;
485 else
486 rc = pState->autoAssign(pszDevName, GuestAddress);
487 }
488 }
489
490 if (FAILED(rc))
491 return rc;
492
493 Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
494
495 rc = pState->record(pszDevName, GuestAddress, HostAddress);
496 if (FAILED(rc))
497 return rc;
498
499 rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
500 if (FAILED(rc))
501 return rc;
502 rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
503 if (FAILED(rc))
504 return rc;
505 rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
506 if (FAILED(rc))
507 return rc;
508
509 return S_OK;
510}
511
512
513bool BusAssignmentManager::findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address)
514{
515 return pState->findPCIAddress(pszDevName, iInstance, Address);
516}
517void BusAssignmentManager::listAttachedPCIDevices(std::vector<ComPtr<IPCIDeviceAttachment> > &aAttached)
518{
519 pState->listAttachedPCIDevices(aAttached);
520}
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