VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 105898

最後變更 在這個檔案從105898是 105858,由 vboxsync 提交於 7 月 前

Disassembler/ARMv8: Implement decoding of the ldr/str (pre-/post-indexed) variant instructions and add testcases, bugref:10394
  • 屬性 svn:eol-style 設為 native
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1/* $Id: DisasmInternal-armv8.h 105858 2024-08-25 13:39:38Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.alldomusa.eu.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseReg,
58 kDisParmParseRegOff,
59 kDisParmParseImmsImmrN,
60 kDisParmParseHw,
61 kDisParmParseCond,
62 kDisParmParsePState,
63 kDisParmParseCRnCRm,
64 kDisParmParseSysReg,
65 kDisParmParseSh12,
66 kDisParmParseImmTbz,
67 kDisParmParseShift,
68 kDisParmParseShiftAmount,
69 kDisParmParseImmMemOff,
70 kDisParmParseSImmMemOff,
71 kDisParmParseSImmMemOffUnscaled,
72 kDisParmParseOption,
73 kDisParmParseS,
74 kDisParmParseSetPreIndexed,
75 kDisParmParseSetPostIndexed,
76 kDisParmParseMax
77} DISPARMPARSEIDX;
78/** @} */
79
80
81/**
82 * Opcode structure.
83 */
84typedef struct DISARMV8OPCODE
85{
86 /** The value of the fixed bits of the instruction. */
87 uint32_t fValue;
88 /** Special flags for the opcode. */
89 uint32_t fFlags;
90 /** The generic opcode structure. */
91 DISOPCODE Opc;
92} DISARMV8OPCODE;
93/** Pointer to a const opcode. */
94typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
95
96
97typedef struct DISARMV8INSNPARAM
98{
99 /** The parser to use for the decode step. */
100 DISPARMPARSEIDX idxParse;
101 /** Bit index at which the field starts. */
102 uint8_t idxBitStart;
103 /** Size of the bit field. */
104 uint8_t cBits;
105 /** The parameter this decoder param contributes to. */
106 uint8_t idxParam;
107} DISARMV8INSNPARAM;
108typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
109typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
110
111#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
112#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
113 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
114
115#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
116
117/**
118 * Opcode decode index.
119 */
120typedef enum DISARMV8OPCDECODE
121{
122 kDisArmV8OpcDecodeNop = 0,
123 kDisArmV8OpcDecodeLookup,
124 kDisArmV8OpcDecodeCollate,
125 kDisArmV8OpcDecodeMax
126} DISARMV8OPCDECODE;
127
128
129/**
130 * Decoder stage type.
131 */
132typedef enum kDisArmV8DecodeType
133{
134 kDisArmV8DecodeType_Invalid = 0,
135 kDisArmV8DecodeType_Map,
136 kDisArmV8DecodeType_Table,
137 kDisArmV8DecodeType_InsnClass,
138 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
139} kDisArmV8DecodeType;
140
141
142/**
143 * Decode header.
144 */
145typedef struct DISARMV8DECODEHDR
146{
147 /** Next stage decoding type. */
148 kDisArmV8DecodeType enmDecodeType;
149 /** Number of entries in the next decoder stage or
150 * opcodes in the instruction class. */
151 uint32_t cDecode;
152} DISARMV8DECODEHDR;
153/** Pointer to a decode header. */
154typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
155/** Pointer to a const decode header. */
156typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
157typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
158
159
160/**
161 * Instruction class descriptor.
162 */
163typedef struct DISARMV8INSNCLASS
164{
165 /** Decoder header. */
166 DISARMV8DECODEHDR Hdr;
167 /** Pointer to the arry of opcodes. */
168 PCDISARMV8OPCODE paOpcodes;
169 /** The mask of fixed instruction bits. */
170 uint32_t fFixedInsn;
171 /** Some flags for this instruction class. */
172 uint32_t fClass;
173 /** Opcode decoder function. */
174 DISARMV8OPCDECODE enmOpcDecode;
175 /** The mask of the bits relevant for decoding. */
176 uint32_t fMask;
177 /** Number of bits to shift to get an index. */
178 uint32_t cShift;
179 /** Parameter types. */
180 DISARMV8OPPARM aenmParamTypes[4];
181 /** The array of decoding steps. */
182 PCDISARMV8INSNPARAM paParms;
183} DISARMV8INSNCLASS;
184/** Pointer to a constant instruction class descriptor. */
185typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
186
187/** The instruction class distinguishes between a 32-bit and 64-bit variant using the sf bit (bit 31). */
188#define DISARMV8INSNCLASS_F_SF RT_BIT_32(0)
189/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
190#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
191/** The instruction class is using the 64-bit register encoding only. */
192#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
193/** The instruction class is using the 32-bit register encoding only. */
194#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
195
196
197#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
198 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
199#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
200 }; \
201 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
202#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
203 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \
204 DIS_ARMV8_INSN_DECODE_TERM \
205 }; \
206 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
207 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
208 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
209 a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
210 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \
211 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
212#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
213 a_enmParamType1, a_enmParamType2, a_enmParamType3) \
214 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
215 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone)
216#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
217 a_enmParamType1, a_enmParamType2) \
218 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
219 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone)
220#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
221 a_enmParamType1) \
222 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
223 a_enmParamType1, kDisArmv8OpParmNone)
224#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \
225 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
226 kDisArmv8OpParmNone)
227
228#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \
229 DIS_ARMV8_INSN_PARAM_NONE }
230
231/**
232 * Decoder lookup table entry.
233 */
234typedef struct DISARMV8DECODETBLENTRY
235{
236 /** The mask to apply to the instruction. */
237 uint32_t fMask;
238 /** The value the masked instruction must match for the entry to match. */
239 uint32_t fValue;
240 /** The next stage followed when there is a match. */
241 PCDISARMV8DECODEHDR pHdrNext;
242} DISARMV8DECODETBLENTRY;
243typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
244typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
245
246
247#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
248 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
249
250
251/**
252 * Decoder lookup table using masks and values.
253 */
254typedef struct DISARMV8DECODETBL
255{
256 /** The header for the decoder lookup table. */
257 DISARMV8DECODEHDR Hdr;
258 /** Pointer to the individual entries. */
259 PCDISARMV8DECODETBLENTRY paEntries;
260} DISARMV8DECODETBL;
261/** Pointer to a const decode table. */
262typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
263
264
265#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
266 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
267
268#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
269 }; \
270 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
271 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
272
273
274/**
275 * Decoder map when direct indexing is possible.
276 */
277typedef struct DISARMV8DECODEMAP
278{
279 /** The header for the decoder map. */
280 DISARMV8DECODEHDR Hdr;
281 /** The bitmask used to decide where to go next. */
282 uint32_t fMask;
283 /** Amount to shift to get at the index. */
284 uint32_t cShift;
285 /** Pointer to the array of pointers to the next stage to index into. */
286 PPCDISARMV8DECODEHDR papNext;
287} DISARMV8DECODEMAP;
288/** Pointer to a const decode map. */
289typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
290
291#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
292 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
293
294#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
295 }; \
296 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
297 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
298
299#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
300 }; \
301 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
302 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
303
304#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
305#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
306
307
308/** @name Decoder maps.
309 * @{ */
310extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
311
312extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
313/** @} */
314
315
316/** @} */
317#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
318
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