Virtio.cpp@ 81031

最後變更在這個檔案從81031是 81031,由 vboxsync 提交於 6 年前
PDM,Devices: Moving the PDMPCIDEV structures into the PDMDEVINS allocation. Preps for extending the config space to 4KB. bugref:9218
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1	/* $Id: Virtio.cpp 81031 2019-09-26 19:26:33Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
23
24	#include <iprt/param.h>
25	#include <iprt/uuid.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include "Virtio.h"
28
29	#define INSTANCE(pState) pState->szInstance
30	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)(pIface) - RT_UOFFSETOF(VPCISTATE, ifaceName)))
31
32	#ifdef LOG_ENABLED
33	# define QUEUENAME(s, q) (q->pcszName)
34	#endif
35
36
37
38	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
39
40	//RT_C_DECLS_BEGIN
41	//RT_C_DECLS_END
42
43
44	static void vqueueReset(PVQUEUE pQueue)
45	{
46	pQueue->VRing.addrDescriptors = 0;
47	pQueue->VRing.addrAvail = 0;
48	pQueue->VRing.addrUsed = 0;
49	pQueue->uNextAvailIndex = 0;
50	pQueue->uNextUsedIndex = 0;
51	pQueue->uPageNumber = 0;
52	}
53
54	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
55	{
56	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
57	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
58	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
59	pQueue->VRing.addrUsed = RT_ALIGN(
60	pQueue->VRing.addrAvail + RT_UOFFSETOF_DYN(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
61	PAGE_SIZE); /* The used ring must start from the next page. */
62	pQueue->uNextAvailIndex = 0;
63	pQueue->uNextUsedIndex = 0;
64	}
65
66	// void vqueueElemFree(PVQUEUEELEM pElem)
67	// {
68	// }
69
70	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
71	{
72	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
74	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
75	pDesc, sizeof(VRINGDESC));
76	}
77
78	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
79	{
80	uint16_t tmp;
81
82	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
83	pVRing->addrAvail + RT_UOFFSETOF_DYN(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
84	&tmp, sizeof(tmp));
85	return tmp;
86	}
87
88	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
89	{
90	uint16_t tmp;
91
92	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
93	pVRing->addrAvail + RT_UOFFSETOF(VRINGAVAIL, uFlags),
94	&tmp, sizeof(tmp));
95	return tmp;
96	}
97
98	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
99	{
100	uint16_t tmp;
101
102	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
103	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uFlags),
104	&tmp, sizeof(tmp));
105
106	if (fEnabled)
107	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
108	else
109	tmp \|= VRINGUSED_F_NO_NOTIFY;
110
111	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
112	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uFlags),
113	&tmp, sizeof(tmp));
114	}
115
116	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
117	{
118	if (vqueueIsEmpty(pState, pQueue))
119	return false;
120
121	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
123	pQueue->uNextAvailIndex++;
124	return true;
125	}
126
127	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
128	{
129	if (vqueueIsEmpty(pState, pQueue))
130	return false;
131
132	pElem->nIn = pElem->nOut = 0;
133
134	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
136
137	VRINGDESC desc;
138	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
139	if (fRemove)
140	pQueue->uNextAvailIndex++;
141	pElem->uIndex = idx;
142	do
143	{
144	VQUEUESEG *pSeg;
145
146	/*
147	* Malicious guests may try to trick us into writing beyond aSegsIn or
148	* aSegsOut boundaries by linking several descriptors into a loop. We
149	* cannot possibly get a sequence of linked descriptors exceeding the
150	* total number of descriptors in the ring (see @bugref{8620}).
151	*/
152	if (pElem->nIn + pElem->nOut >= VRING_MAX_SIZE)
153	{
154	static volatile uint32_t s_cMessages = 0;
155	static volatile uint32_t s_cThreshold = 1;
156	if (ASMAtomicIncU32(&s_cMessages) == ASMAtomicReadU32(&s_cThreshold))
157	{
158	LogRel(("%s: too many linked descriptors; check if the guest arranges descriptors in a loop.\n",
159	INSTANCE(pState)));
160	if (ASMAtomicReadU32(&s_cMessages) != 1)
161	LogRel(("%s: (the above error has occured %u times so far)\n",
162	INSTANCE(pState), ASMAtomicReadU32(&s_cMessages)));
163	ASMAtomicWriteU32(&s_cThreshold, ASMAtomicReadU32(&s_cThreshold) * 10);
164	}
165	break;
166	}
167	RT_UNTRUSTED_VALIDATED_FENCE();
168
169	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
170	if (desc.u16Flags & VRINGDESC_F_WRITE)
171	{
172	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
173	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
174	pSeg = &pElem->aSegsIn[pElem->nIn++];
175	}
176	else
177	{
178	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
179	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
180	pSeg = &pElem->aSegsOut[pElem->nOut++];
181	}
182
183	pSeg->addr = desc.u64Addr;
184	pSeg->cb = desc.uLen;
185	pSeg->pv = NULL;
186
187	idx = desc.u16Next;
188	} while (desc.u16Flags & VRINGDESC_F_NEXT);
189
190	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
191	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
192	return true;
193	}
194
195	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
196	{
197	uint16_t tmp;
198	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
199	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uIndex),
200	&tmp, sizeof(tmp));
201	return tmp;
202	}
203
204	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
205	{
206	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
207	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uIndex),
208	&u16Value, sizeof(u16Value));
209	}
210
211	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
212	{
213	VRINGUSEDELEM elem;
214
215	elem.uId = uId;
216	elem.uLen = uLen;
217	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
218	pVRing->addrUsed + RT_UOFFSETOF_DYN(VRINGUSED, aRing[uIndex % pVRing->uSize]),
219	&elem, sizeof(elem));
220	}
221
222
223	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue,
224	PVQUEUEELEM pElem, uint32_t uTotalLen, uint32_t uReserved)
225	{
226	Log2(("%s vqueuePut: %s"
227	" desc_idx=%u acb=%u (%u)\n",
228	INSTANCE(pState), QUEUENAME(pState, pQueue),
229	pElem->uIndex, uTotalLen, uReserved));
230
231	Assert(uReserved < uTotalLen);
232
233	uint32_t cbLen = uTotalLen - uReserved;
234	uint32_t cbSkip = uReserved;
235
236	for (unsigned i = 0; i < pElem->nIn && cbLen > 0; ++i)
237	{
238	if (cbSkip >= pElem->aSegsIn[i].cb) /* segment completely skipped? */
239	{
240	cbSkip -= pElem->aSegsIn[i].cb;
241	continue;
242	}
243
244	uint32_t cbSegLen = pElem->aSegsIn[i].cb - cbSkip;
245	if (cbSegLen > cbLen) /* last segment only partially used? */
246	cbSegLen = cbLen;
247
248	/*
249	* XXX: We should assert pv != NULL, but we need to check and
250	* fix all callers first.
251	*/
252	if (pElem->aSegsIn[i].pv != NULL)
253	{
254	Log2(("%s vqueuePut: %s"
255	" used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n",
256	INSTANCE(pState), QUEUENAME(pState, pQueue),
257	pQueue->uNextUsedIndex, i,
258	(void *)pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv,
259	pElem->aSegsIn[i].cb, cbSegLen));
260
261	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
262	pElem->aSegsIn[i].addr + cbSkip,
263	pElem->aSegsIn[i].pv,
264	cbSegLen);
265	}
266
267	cbSkip = 0;
268	cbLen -= cbSegLen;
269	}
270
271	Log2(("%s vqueuePut: %s"
272	" used_idx=%u guest_used_idx=%u id=%u len=%u\n",
273	INSTANCE(pState), QUEUENAME(pState, pQueue),
274	pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing),
275	pElem->uIndex, uTotalLen));
276
277	vringWriteUsedElem(pState, &pQueue->VRing,
278	pQueue->uNextUsedIndex++,
279	pElem->uIndex, uTotalLen);
280	}
281
282
283	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
284	{
285	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
286	INSTANCE(pState), QUEUENAME(pState, pQueue),
287	vringReadAvailFlags(pState, &pQueue->VRing),
288	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
289	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
290	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
291	{
292	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
293	if (RT_FAILURE(rc))
294	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
295	}
296	else
297	{
298	STAM_COUNTER_INC(&pState->StatIntsSkipped);
299	}
300
301	}
302
303	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
304	{
305	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
306	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
307	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
308	vqueueNotify(pState, pQueue);
309	}
310
311
312	/**
313	* Raise interrupt.
314	*
315	* @param pState The device state structure.
316	* @param rcBusy Status code to return when the critical section is busy.
317	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
318	*/
319	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
320	{
321	RT_NOREF_PV(rcBusy);
322	// int rc = vpciCsEnter(pState, rcBusy);
323	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
324	// return rc;
325
326	STAM_COUNTER_INC(&pState->StatIntsRaised);
327	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
328	INSTANCE(pState), u8IntCause));
329
330	pState->uISR \|= u8IntCause;
331	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
332	// vpciCsLeave(pState);
333	return VINF_SUCCESS;
334	}
335
336	/**
337	* Lower interrupt.
338	*
339	* @param pState The device state structure.
340	*/
341	static void vpciLowerInterrupt(VPCISTATE *pState)
342	{
343	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
344	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
345	}
346
347
348	void vpciReset(PVPCISTATE pState)
349	{
350	/* No interrupts should survive device reset, see @bugref(9556). */
351	if (pState->uISR)
352	vpciLowerInterrupt(pState);
353
354	pState->uGuestFeatures = 0;
355	pState->uQueueSelector = 0;
356	pState->uStatus = 0;
357	pState->uISR = 0;
358
359	for (unsigned i = 0; i < pState->nQueues; i++)
360	vqueueReset(&pState->Queues[i]);
361	}
362
363
364	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
365	PFNGETHOSTFEATURES pfnGetHostFeatures)
366	{
367	return pfnGetHostFeatures(pState)
368	\| VPCI_F_NOTIFY_ON_EMPTY;
369	}
370
371	/**
372	* Port I/O Handler for IN operations.
373	*
374	* @returns VBox status code.
375	*
376	* @param pDevIns The device instance.
377	* @param pvUser Pointer to the device state structure.
378	* @param Port Port number used for the IN operation.
379	* @param pu32 Where to store the result.
380	* @param cb Number of bytes read.
381	* @param pCallbacks Pointer to the callbacks.
382	* @thread EMT
383	*/
384	int vpciIOPortIn(PPDMDEVINS pDevIns,
385	void *pvUser,
386	RTIOPORT Port,
387	uint32_t *pu32,
388	unsigned cb,
389	PCVPCIIOCALLBACKS pCallbacks)
390	{
391	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
392	int rc = VINF_SUCCESS;
393	STAM_PROFILE_ADV_START(&pState->CTX_SUFF(StatIORead), a);
394	RT_NOREF_PV(pvUser);
395
396	/*
397	* We probably do not need to enter critical section when reading registers
398	* as the most of them are either constant or being changed during
399	* initialization only, the exception being ISR which can be raced by all
400	* threads but I see no big harm in it. It also happens to be the most read
401	* register as it gets read in interrupt handler. By dropping cs protection
402	* here we gain the ability to deliver RX packets to the guest while TX is
403	* holding cs transmitting queued packets.
404	*
405	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
406	if (RT_UNLIKELY(rc != VINF_SUCCESS))
407	{
408	STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF(StatIORead), a);
409	return rc;
410	}*/
411
412	Port -= pState->IOPortBase;
413	switch (Port)
414	{
415	case VPCI_HOST_FEATURES:
416	/* Tell the guest what features we support. */
417	*pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
418	\| VPCI_F_BAD_FEATURE;
419	break;
420
421	case VPCI_GUEST_FEATURES:
422	*pu32 = pState->uGuestFeatures;
423	break;
424
425	case VPCI_QUEUE_PFN:
426	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
427	break;
428
429	case VPCI_QUEUE_NUM:
430	Assert(cb == 2);
431	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
432	break;
433
434	case VPCI_QUEUE_SEL:
435	Assert(cb == 2);
436	(uint16_t)pu32 = pState->uQueueSelector;
437	break;
438
439	case VPCI_STATUS:
440	Assert(cb == 1);
441	(uint8_t)pu32 = pState->uStatus;
442	break;
443
444	case VPCI_ISR:
445	Assert(cb == 1);
446	(uint8_t)pu32 = pState->uISR;
447	pState->uISR = 0; /* read clears all interrupts */
448	vpciLowerInterrupt(pState);
449	break;
450
451	default:
452	if (Port >= VPCI_CONFIG)
453	rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
454	else
455	{
456	*pu32 = 0xFFFFFFFF;
457	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
458	INSTANCE(pState), Port, cb);
459	}
460	break;
461	}
462	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
463	STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF(StatIORead), a);
464	//vpciCsLeave(pState);
465	return rc;
466	}
467
468
469	/**
470	* Port I/O Handler for OUT operations.
471	*
472	* @returns VBox status code.
473	*
474	* @param pDevIns The device instance.
475	* @param pvUser User argument.
476	* @param Port Port number used for the IN operation.
477	* @param u32 The value to output.
478	* @param cb The value size in bytes.
479	* @param pCallbacks Pointer to the callbacks.
480	* @thread EMT
481	*/
482	int vpciIOPortOut(PPDMDEVINS pDevIns,
483	void *pvUser,
484	RTIOPORT Port,
485	uint32_t u32,
486	unsigned cb,
487	PCVPCIIOCALLBACKS pCallbacks)
488	{
489	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
490	int rc = VINF_SUCCESS;
491	bool fHasBecomeReady;
492	STAM_PROFILE_ADV_START(&pState->CTX_SUFF(StatIOWrite), a);
493	RT_NOREF_PV(pvUser);
494
495	Port -= pState->IOPortBase;
496	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
497
498	switch (Port)
499	{
500	case VPCI_GUEST_FEATURES:
501	{
502	const uint32_t uHostFeatures = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
503
504	if (RT_LIKELY((u32 & ~uHostFeatures) == 0))
505	{
506	pState->uGuestFeatures = u32;
507	}
508	else
509	{
510	/*
511	* Guest requests features we don't advertise. Stick
512	* to the minimum if negotiation looks completely
513	* botched, otherwise restrict to advertised features.
514	*/
515	if (u32 & VPCI_F_BAD_FEATURE)
516	{
517	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
518	INSTANCE(pState), u32));
519	pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
520	}
521	else
522	{
523	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
524	INSTANCE(pState), uHostFeatures, u32));
525	pState->uGuestFeatures = u32 & uHostFeatures;
526	}
527	}
528	pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
529	break;
530	}
531
532	case VPCI_QUEUE_PFN:
533	/*
534	* The guest is responsible for allocating the pages for queues,
535	* here it provides us with the page number of descriptor table.
536	* Note that we provide the size of the queue to the guest via
537	* VIRTIO_PCI_QUEUE_NUM.
538	*/
539	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
540	if (u32)
541	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
542	else
543	rc = pCallbacks->pfnReset(pState);
544	break;
545
546	case VPCI_QUEUE_SEL:
547	Assert(cb == 2);
548	u32 &= 0xFFFF;
549	if (u32 < pState->nQueues)
550	pState->uQueueSelector = u32;
551	else
552	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
553	break;
554
555	case VPCI_QUEUE_NOTIFY:
556	#ifdef IN_RING3
557	Assert(cb == 2);
558	u32 &= 0xFFFF;
559	if (u32 < pState->nQueues)
560	{
561	RT_UNTRUSTED_VALIDATED_FENCE();
562	if (pState->Queues[u32].VRing.addrDescriptors)
563	{
564	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
565	// if (RT_LIKELY(rc == VINF_SUCCESS))
566	// {
567	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
568	// vpciCsLeave(pState);
569	// }
570	}
571	else
572	Log(("%s The queue (#%d) being notified has not been initialized.\n",
573	INSTANCE(pState), u32));
574	}
575	else
576	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
577	#else
578	rc = VINF_IOM_R3_IOPORT_WRITE;
579	#endif
580	break;
581
582	case VPCI_STATUS:
583	Assert(cb == 1);
584	u32 &= 0xFF;
585	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
586	pState->uStatus = u32;
587	/* Writing 0 to the status port triggers device reset. */
588	if (u32 == 0)
589	rc = pCallbacks->pfnReset(pState);
590	else if (fHasBecomeReady)
591	{
592	/* Older hypervisors were lax and did not enforce bus mastering. Older guests
593	* (Linux prior to 2.6.34, NetBSD 6.x) were lazy and did not enable bus mastering.
594	* We automagically enable bus mastering on driver initialization to make existing
595	* drivers work.
596	*/
597	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
598	PDMPciDevSetCommand(pPciDev, PDMPciDevGetCommand(pPciDev) \| PCI_COMMAND_BUSMASTER);
599
600	pCallbacks->pfnReady(pState);
601	}
602	break;
603
604	default:
605	if (Port >= VPCI_CONFIG)
606	rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
607	else
608	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
609	INSTANCE(pState), Port, cb);
610	break;
611	}
612
613	STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF(StatIOWrite), a);
614	return rc;
615	}
616
617	#ifdef IN_RING3
618
619	/**
620	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
621	*/
622	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
623	{
624	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
625	Assert(&pThis->IBase == pInterface);
626
627	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
628	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
629	return NULL;
630	}
631
632	/**
633	* Gets the pointer to the status LED of a unit.
634	*
635	* @returns VBox status code.
636	* @param pInterface Pointer to the interface structure.
637	* @param iLUN The unit which status LED we desire.
638	* @param ppLed Where to store the LED pointer.
639	* @thread EMT
640	*/
641	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
642	{
643	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
644	int rc = VERR_PDM_LUN_NOT_FOUND;
645
646	if (iLUN == 0)
647	{
648	*ppLed = &pState->led;
649	rc = VINF_SUCCESS;
650	}
651	return rc;
652	}
653
654	/**
655	* Turns on/off the write status LED.
656	*
657	* @returns VBox status code.
658	* @param pState Pointer to the device state structure.
659	* @param fOn New LED state.
660	*/
661	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
662	{
663	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
664	if (fOn)
665	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
666	else
667	pState->led.Actual.s.fWriting = fOn;
668	}
669
670	/**
671	* Turns on/off the read status LED.
672	*
673	* @returns VBox status code.
674	* @param pState Pointer to the device state structure.
675	* @param fOn New LED state.
676	*/
677	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
678	{
679	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
680	if (fOn)
681	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
682	else
683	pState->led.Actual.s.fReading = fOn;
684	}
685
686
687	#if 0 /* unused */
688	/**
689	* Sets 32-bit register in PCI configuration space.
690	* @param refPciDev The PCI device.
691	* @param uOffset The register offset.
692	* @param u32Value The value to store in the register.
693	* @thread EMT
694	*/
695	DECLINLINE(void) vpciCfgSetU32(PDMPCIDEV& refPciDev, uint32_t uOffset, uint32_t u32Value)
696	{
697	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
698	(uint32_t)&refPciDev.config[uOffset] = u32Value;
699	}
700	#endif /* unused */
701
702
703	#ifdef DEBUG
704	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
705	{
706	Log2(("vpciDumpState: (called from %s)\n"
707	" uGuestFeatures = 0x%08x\n"
708	" uQueueSelector = 0x%04x\n"
709	" uStatus = 0x%02x\n"
710	" uISR = 0x%02x\n",
711	pcszCaller,
712	pState->uGuestFeatures,
713	pState->uQueueSelector,
714	pState->uStatus,
715	pState->uISR));
716
717	for (unsigned i = 0; i < pState->nQueues; i++)
718	Log2((" %s queue:\n"
719	" VRing.uSize = %u\n"
720	" VRing.addrDescriptors = %p\n"
721	" VRing.addrAvail = %p\n"
722	" VRing.addrUsed = %p\n"
723	" uNextAvailIndex = %u\n"
724	" uNextUsedIndex = %u\n"
725	" uPageNumber = %x\n",
726	pState->Queues[i].pcszName,
727	pState->Queues[i].VRing.uSize,
728	pState->Queues[i].VRing.addrDescriptors,
729	pState->Queues[i].VRing.addrAvail,
730	pState->Queues[i].VRing.addrUsed,
731	pState->Queues[i].uNextAvailIndex,
732	pState->Queues[i].uNextUsedIndex,
733	pState->Queues[i].uPageNumber));
734	}
735	#else
736	# define vpciDumpState(x, s) do {} while (0)
737	#endif
738
739	/**
740	* Saves the state of device.
741	*
742	* @returns VBox status code.
743	* @param pDevIns The device instance.
744	* @param pSSM The handle to the saved state.
745	*/
746	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
747	{
748	int rc;
749
750	vpciDumpState(pState, "vpciSaveExec");
751
752	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
753	AssertRCReturn(rc, rc);
754	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
755	AssertRCReturn(rc, rc);
756	rc = SSMR3PutU8( pSSM, pState->uStatus);
757	AssertRCReturn(rc, rc);
758	rc = SSMR3PutU8( pSSM, pState->uISR);
759	AssertRCReturn(rc, rc);
760
761	/* Save queue states */
762	rc = SSMR3PutU32(pSSM, pState->nQueues);
763	AssertRCReturn(rc, rc);
764	for (unsigned i = 0; i < pState->nQueues; i++)
765	{
766	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
767	AssertRCReturn(rc, rc);
768	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
769	AssertRCReturn(rc, rc);
770	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
771	AssertRCReturn(rc, rc);
772	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
773	AssertRCReturn(rc, rc);
774	}
775
776	return VINF_SUCCESS;
777	}
778
779	/**
780	* Loads a saved device state.
781	*
782	* @returns VBox status code.
783	* @param pDevIns The device instance.
784	* @param pSSM The handle to the saved state.
785	* @param uVersion The data unit version number.
786	* @param uPass The data pass.
787	*/
788	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
789	{
790	int rc;
791
792	if (uPass == SSM_PASS_FINAL)
793	{
794	/* Restore state data */
795	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
796	AssertRCReturn(rc, rc);
797	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
798	AssertRCReturn(rc, rc);
799	rc = SSMR3GetU8( pSSM, &pState->uStatus);
800	AssertRCReturn(rc, rc);
801	rc = SSMR3GetU8( pSSM, &pState->uISR);
802	AssertRCReturn(rc, rc);
803
804	/* Restore queues */
805	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
806	{
807	rc = SSMR3GetU32(pSSM, &pState->nQueues);
808	AssertRCReturn(rc, rc);
809	}
810	else
811	pState->nQueues = nQueues;
812	AssertLogRelMsgReturn(pState->nQueues <= VIRTIO_MAX_NQUEUES, ("%#x\n", pState->nQueues), VERR_SSM_LOAD_CONFIG_MISMATCH);
813	AssertLogRelMsgReturn(pState->uQueueSelector < pState->nQueues \|\| (pState->nQueues == 0 && pState->uQueueSelector),
814	("uQueueSelector=%u nQueues=%u\n", pState->uQueueSelector, pState->nQueues),
815	VERR_SSM_LOAD_CONFIG_MISMATCH);
816
817	for (unsigned i = 0; i < pState->nQueues; i++)
818	{
819	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
820	AssertRCReturn(rc, rc);
821	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
822	AssertRCReturn(rc, rc);
823
824	if (pState->Queues[i].uPageNumber)
825	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
826
827	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
828	AssertRCReturn(rc, rc);
829	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
830	AssertRCReturn(rc, rc);
831	}
832	}
833
834	vpciDumpState(pState, "vpciLoadExec");
835
836	return VINF_SUCCESS;
837	}
838
839	/**
840	* Set PCI configuration space registers.
841	*
842	* @param pPciDev Pointer to the PCI device structure.
843	* @param uDeviceId VirtiO Device Id
844	* @param uClass Class of PCI device (network, etc)
845	* @thread EMT
846	*/
847	static DECLCALLBACK(void) vpciConfigure(PPDMPCIDEV pPciDev,
848	uint16_t uDeviceId,
849	uint16_t uClass)
850	{
851	/* Configure PCI Device, assume 32-bit mode ******************************/
852	PDMPciDevSetVendorId(pPciDev, DEVICE_PCI_VENDOR_ID);
853	PDMPciDevSetDeviceId(pPciDev, DEVICE_PCI_BASE_ID + uDeviceId);
854	PDMPciDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
855	PDMPciDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);
856
857	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
858	PDMPciDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, 0x00);
859	/* Ethernet adapter */
860	PDMPciDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
861	PDMPciDevSetWord(pPciDev, VBOX_PCI_CLASS_DEVICE, uClass);
862	/* Interrupt Pin: INTA# */
863	PDMPciDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
864
865	#ifdef VBOX_WITH_MSI_DEVICES
866	PDMPciDevSetCapabilityList(pPciDev, 0x80);
867	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST);
868	#endif
869	}
870
871	#ifdef VBOX_WITH_STATISTICS
872	/* WARNING! This function must never be used in multithreaded context! */
873	static const char vpciCounter(const char pszDevFmt,
874	const char *pszCounter)
875	{
876	static char s_szCounterName[80];
877
878	RTStrPrintf(s_szCounterName, sizeof(s_szCounterName),
879	"/Devices/%s/%s", pszDevFmt, pszCounter);
880
881	return s_szCounterName;
882	}
883	#endif
884
885	/// @todo header
886	int vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
887	int iInstance, const char *pcszNameFmt,
888	uint16_t uDeviceId, uint16_t uClass,
889	uint32_t nQueues)
890	{
891	/* Init handles and log related stuff. */
892	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
893	pcszNameFmt, iInstance);
894
895	pState->pDevInsR3 = pDevIns;
896	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
897	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
898	pState->led.u32Magic = PDMLED_MAGIC;
899
900	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
901
902	/* Initialize critical section. */
903	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
904	if (RT_FAILURE(rc))
905	return rc;
906
907	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
908	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
909	/* Set PCI config registers */
910	vpciConfigure(pPciDev, uDeviceId, uClass);
911	/* Register PCI device */
912	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
913	if (RT_FAILURE(rc))
914	return rc;
915
916	#ifdef VBOX_WITH_MSI_DEVICES
917	#if 0
918	{
919	PDMMSIREG aMsiReg;
920
921	RT_ZERO(aMsiReg);
922	aMsiReg.cMsixVectors = 1;
923	aMsiReg.iMsixCapOffset = 0x80;
924	aMsiReg.iMsixNextOffset = 0x0;
925	aMsiReg.iMsixBar = 0;
926	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
927	if (RT_FAILURE (rc))
928	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
929	}
930	#endif
931	#endif
932
933	/* Status driver */
934	PPDMIBASE pBase;
935	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
936	if (RT_FAILURE(rc))
937	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
938	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
939
940	pState->nQueues = nQueues;
941
942	#if defined(VBOX_WITH_STATISTICS)
943	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", vpciCounter(pcszNameFmt, "IO/ReadR3"), iInstance);
944	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadR0, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R0", vpciCounter(pcszNameFmt, "IO/ReadR0"), iInstance);
945	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RC", vpciCounter(pcszNameFmt, "IO/ReadRC"), iInstance);
946	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", vpciCounter(pcszNameFmt, "IO/WriteR3"), iInstance);
947	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteR0, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R0", vpciCounter(pcszNameFmt, "IO/WriteR0"), iInstance);
948	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RC", vpciCounter(pcszNameFmt, "IO/WriteRC"), iInstance);
949	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
950	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
951	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in R3", vpciCounter(pcszNameFmt, "Cs/CsR3"), iInstance);
952	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsR0, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in R0", vpciCounter(pcszNameFmt, "Cs/CsR0"), iInstance);
953	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in RC", vpciCounter(pcszNameFmt, "Cs/CsRC"), iInstance);
954	#endif /* VBOX_WITH_STATISTICS */
955
956	return rc;
957	}
958
959	/**
960	* Destruct PCI-related part of device.
961	*
962	* We need to free non-VM resources only.
963	*
964	* @returns VBox status code.
965	* @param pState The device state structure.
966	*/
967	int vpciDestruct(VPCISTATE* pState)
968	{
969	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
970
971	if (PDMCritSectIsInitialized(&pState->cs))
972	PDMR3CritSectDelete(&pState->cs);
973
974	return VINF_SUCCESS;
975	}
976
977	/**
978	* Device relocation callback.
979	*
980	* When this callback is called the device instance data, and if the
981	* device have a GC component, is being relocated, or/and the selectors
982	* have been changed. The device must use the chance to perform the
983	* necessary pointer relocations and data updates.
984	*
985	* Before the GC code is executed the first time, this function will be
986	* called with a 0 delta so GC pointer calculations can be one in one place.
987	*
988	* @param pDevIns Pointer to the device instance.
989	* @param offDelta The relocation delta relative to the old location.
990	*
991	* @remark A relocation CANNOT fail.
992	*/
993	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
994	{
995	RT_NOREF(offDelta);
996	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE);
997	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
998	// TBD
999	}
1000
1001	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
1002	{
1003	PVQUEUE pQueue = NULL;
1004	/* Find an empty queue slot */
1005	for (unsigned i = 0; i < pState->nQueues; i++)
1006	{
1007	if (pState->Queues[i].VRing.uSize == 0)
1008	{
1009	pQueue = &pState->Queues[i];
1010	break;
1011	}
1012	}
1013
1014	if (!pQueue)
1015	{
1016	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
1017	}
1018	else
1019	{
1020	pQueue->VRing.uSize = uSize;
1021	pQueue->VRing.addrDescriptors = 0;
1022	pQueue->uPageNumber = 0;
1023	pQueue->pfnCallback = pfnCallback;
1024	pQueue->pcszName = pcszName;
1025	}
1026
1027	return pQueue;
1028	}
1029
1030	#endif /* IN_RING3 */
1031
1032	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
1033

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 81031

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