Virtio.cpp@ 44849

最後變更在這個檔案從44849是 44849,由 vboxsync 提交於 12 年前
DevirtioNet.cpp: cleanups.
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1	/* $Id: Virtio.cpp 44849 2013-02-27 20:22:06Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
20
21	#include <iprt/param.h>
22	#include <iprt/uuid.h>
23	#include <VBox/vmm/pdmdev.h>
24	#include "Virtio.h"
25
26	#define INSTANCE(pState) pState->szInstance
27	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
28
29	#ifdef LOG_ENABLED
30	#define QUEUENAME(s, q) (q->pcszName)
31	#endif /* DEBUG */
32
33
34
35	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
36
37	//RT_C_DECLS_BEGIN
38	//RT_C_DECLS_END
39
40
41	static void vqueueReset(PVQUEUE pQueue)
42	{
43	pQueue->VRing.addrDescriptors = 0;
44	pQueue->VRing.addrAvail = 0;
45	pQueue->VRing.addrUsed = 0;
46	pQueue->uNextAvailIndex = 0;
47	pQueue->uNextUsedIndex = 0;
48	pQueue->uPageNumber = 0;
49	}
50
51	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
52	{
53	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
54	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
55	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
56	pQueue->VRing.addrUsed = RT_ALIGN(
57	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
58	PAGE_SIZE); /* The used ring must start from the next page. */
59	pQueue->uNextAvailIndex = 0;
60	pQueue->uNextUsedIndex = 0;
61	}
62
63	// void vqueueElemFree(PVQUEUEELEM pElem)
64	// {
65	// }
66
67	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
68	{
69	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
70	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
71	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
72	pDesc, sizeof(VRINGDESC));
73	}
74
75	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
76	{
77	uint16_t tmp;
78
79	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
80	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
81	&tmp, sizeof(tmp));
82	return tmp;
83	}
84
85	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
86	{
87	uint16_t tmp;
88
89	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
90	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
91	&tmp, sizeof(tmp));
92	return tmp;
93	}
94
95	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
96	{
97	uint16_t tmp;
98
99	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
100	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
101	&tmp, sizeof(tmp));
102
103	if (fEnabled)
104	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
105	else
106	tmp \|= VRINGUSED_F_NO_NOTIFY;
107
108	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
109	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
110	&tmp, sizeof(tmp));
111	}
112
113	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
114	{
115	if (vqueueIsEmpty(pState, pQueue))
116	return false;
117
118	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
119	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
120	pQueue->uNextAvailIndex++;
121	return true;
122	}
123
124	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
125	{
126	if (vqueueIsEmpty(pState, pQueue))
127	return false;
128
129	pElem->nIn = pElem->nOut = 0;
130
131	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
132	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
133
134	VRINGDESC desc;
135	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
136	if (fRemove)
137	pQueue->uNextAvailIndex++;
138	pElem->uIndex = idx;
139	do
140	{
141	VQUEUESEG *pSeg;
142
143	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
144	if (desc.u16Flags & VRINGDESC_F_WRITE)
145	{
146	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
147	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
148	pSeg = &pElem->aSegsIn[pElem->nIn++];
149	}
150	else
151	{
152	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
153	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
154	pSeg = &pElem->aSegsOut[pElem->nOut++];
155	}
156
157	pSeg->addr = desc.u64Addr;
158	pSeg->cb = desc.uLen;
159	pSeg->pv = NULL;
160
161	idx = desc.u16Next;
162	} while (desc.u16Flags & VRINGDESC_F_NEXT);
163
164	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
165	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
166	return true;
167	}
168
169	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
170	{
171	uint16_t tmp;
172	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
173	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
174	&tmp, sizeof(tmp));
175	return tmp;
176	}
177
178	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
179	{
180	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
181	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
182	&u16Value, sizeof(u16Value));
183	}
184
185	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
186	{
187	VRINGUSEDELEM elem;
188
189	elem.uId = uId;
190	elem.uLen = uLen;
191	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
192	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
193	&elem, sizeof(elem));
194	}
195
196	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen, uint32_t uReserved)
197	{
198	unsigned int i, uOffset, cbReserved = uReserved;
199
200	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
201	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
202	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen - uReserved; i++)
203	{
204	uint32_t cbSegLen = RT_MIN(uLen - cbReserved - uOffset, pElem->aSegsIn[i].cb - cbReserved);
205	if (pElem->aSegsIn[i].pv)
206	{
207	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
208	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
209	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr + cbReserved,
210	pElem->aSegsIn[i].pv, cbSegLen);
211	cbReserved = 0;
212	}
213	uOffset += cbSegLen;
214	}
215
216	Assert((uReserved + uOffset) == uLen \|\| pElem->nIn == 0);
217	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
218	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
219	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
220	}
221
222	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
223	{
224	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
225	INSTANCE(pState), QUEUENAME(pState, pQueue),
226	vringReadAvailFlags(pState, &pQueue->VRing),
227	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
228	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
229	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
230	{
231	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
232	if (RT_FAILURE(rc))
233	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
234	}
235	else
236	{
237	STAM_COUNTER_INC(&pState->StatIntsSkipped);
238	}
239
240	}
241
242	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
243	{
244	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
245	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
246	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
247	vqueueNotify(pState, pQueue);
248	}
249
250	void vpciReset(PVPCISTATE pState)
251	{
252	pState->uGuestFeatures = 0;
253	pState->uQueueSelector = 0;
254	pState->uStatus = 0;
255	pState->uISR = 0;
256
257	for (unsigned i = 0; i < pState->nQueues; i++)
258	vqueueReset(&pState->Queues[i]);
259	}
260
261
262	/**
263	* Raise interrupt.
264	*
265	* @param pState The device state structure.
266	* @param rcBusy Status code to return when the critical section is busy.
267	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
268	*/
269	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
270	{
271	// int rc = vpciCsEnter(pState, rcBusy);
272	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
273	// return rc;
274
275	STAM_COUNTER_INC(&pState->StatIntsRaised);
276	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
277	INSTANCE(pState), u8IntCause));
278
279	pState->uISR \|= u8IntCause;
280	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
281	// vpciCsLeave(pState);
282	return VINF_SUCCESS;
283	}
284
285	/**
286	* Lower interrupt.
287	*
288	* @param pState The device state structure.
289	*/
290	PDMBOTHCBDECL(void) vpciLowerInterrupt(VPCISTATE *pState)
291	{
292	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
293	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
294	}
295
296	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
297	PFNGETHOSTFEATURES pfnGetHostFeatures)
298	{
299	return pfnGetHostFeatures(pState)
300	\| VPCI_F_NOTIFY_ON_EMPTY;
301	}
302
303	/**
304	* Port I/O Handler for IN operations.
305	*
306	* @returns VBox status code.
307	*
308	* @param pDevIns The device instance.
309	* @param pvUser Pointer to the device state structure.
310	* @param Port Port number used for the IN operation.
311	* @param pu32 Where to store the result.
312	* @param cb Number of bytes read.
313	* @thread EMT
314	*/
315	int vpciIOPortIn(PPDMDEVINS pDevIns,
316	void *pvUser,
317	RTIOPORT Port,
318	uint32_t *pu32,
319	unsigned cb,
320	PFNGETHOSTFEATURES pfnGetHostFeatures,
321	PFNGETCONFIG pfnGetConfig)
322	{
323	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
324	int rc = VINF_SUCCESS;
325	const char *szInst = INSTANCE(pState);
326	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
327
328	/*
329	* We probably do not need to enter critical section when reading registers
330	* as the most of them are either constant or being changed during
331	* initialization only, the exception being ISR which can be raced by all
332	* threads but I see no big harm in it. It also happens to be the most read
333	* register as it gets read in interrupt handler. By dropping cs protection
334	* here we gain the ability to deliver RX packets to the guest while TX is
335	* holding cs transmitting queued packets.
336	*
337	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
338	if (RT_UNLIKELY(rc != VINF_SUCCESS))
339	{
340	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
341	return rc;
342	}*/
343
344	Port -= pState->addrIOPort;
345	switch (Port)
346	{
347	case VPCI_HOST_FEATURES:
348	/* Tell the guest what features we support. */
349	*pu32 = vpciGetHostFeatures(pState, pfnGetHostFeatures)
350	\| VPCI_F_BAD_FEATURE;
351	break;
352
353	case VPCI_GUEST_FEATURES:
354	*pu32 = pState->uGuestFeatures;
355	break;
356
357	case VPCI_QUEUE_PFN:
358	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
359	break;
360
361	case VPCI_QUEUE_NUM:
362	Assert(cb == 2);
363	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
364	break;
365
366	case VPCI_QUEUE_SEL:
367	Assert(cb == 2);
368	(uint16_t)pu32 = pState->uQueueSelector;
369	break;
370
371	case VPCI_STATUS:
372	Assert(cb == 1);
373	(uint8_t)pu32 = pState->uStatus;
374	break;
375
376	case VPCI_ISR:
377	Assert(cb == 1);
378	(uint8_t)pu32 = pState->uISR;
379	pState->uISR = 0; /* read clears all interrupts */
380	vpciLowerInterrupt(pState);
381	break;
382
383	default:
384	if (Port >= VPCI_CONFIG)
385	rc = pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
386	else
387	{
388	*pu32 = 0xFFFFFFFF;
389	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
390	szInst, Port, cb);
391	}
392	break;
393	}
394	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", szInst, Port, cb2, *pu32));
395	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
396	//vpciCsLeave(pState);
397	return rc;
398	}
399
400
401	/**
402	* Port I/O Handler for OUT operations.
403	*
404	* @returns VBox status code.
405	*
406	* @param pDevIns The device instance.
407	* @param pvUser User argument.
408	* @param Port Port number used for the IN operation.
409	* @param u32 The value to output.
410	* @param cb The value size in bytes.
411	* @todo r=bird: Use a callback table instead of passing 6 function pointers
412	* for potential operations with each I/O port write.
413	* @thread EMT
414	*/
415	int vpciIOPortOut(PPDMDEVINS pDevIns,
416	void *pvUser,
417	RTIOPORT Port,
418	uint32_t u32,
419	unsigned cb,
420	PFNGETHOSTMINIMALFEATURES pfnGetHostMinimalFeatures,
421	PFNGETHOSTFEATURES pfnGetHostFeatures,
422	PFNSETHOSTFEATURES pfnSetHostFeatures,
423	PFNRESET pfnReset,
424	PFNREADY pfnReady,
425	PFNSETCONFIG pfnSetConfig)
426
427	{
428	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
429	int rc = VINF_SUCCESS;
430	const char *szInst = INSTANCE(pState);
431	bool fHasBecomeReady;
432	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
433
434	Port -= pState->addrIOPort;
435	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", szInst, Port, cb2, u32));
436
437	switch (Port)
438	{
439	case VPCI_GUEST_FEATURES:
440	/* Check if the guest negotiates properly, fall back to basics if it does not. */
441	if (VPCI_F_BAD_FEATURE & u32)
442	{
443	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
444	INSTANCE(pState), u32));
445	pState->uGuestFeatures = pfnGetHostMinimalFeatures(pState);
446	}
447	/* The guest may potentially desire features we don't support! */
448	else if (~vpciGetHostFeatures(pState, pfnGetHostFeatures) & u32)
449	{
450	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
451	INSTANCE(pState),
452	vpciGetHostFeatures(pState, pfnGetHostFeatures), u32));
453	pState->uGuestFeatures =
454	vpciGetHostFeatures(pState, pfnGetHostFeatures);
455	}
456	else
457	pState->uGuestFeatures = u32;
458	pfnSetHostFeatures(pState, pState->uGuestFeatures);
459	break;
460
461	case VPCI_QUEUE_PFN:
462	/*
463	* The guest is responsible for allocating the pages for queues,
464	* here it provides us with the page number of descriptor table.
465	* Note that we provide the size of the queue to the guest via
466	* VIRTIO_PCI_QUEUE_NUM.
467	*/
468	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
469	if (u32)
470	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
471	else
472	rc = pfnReset(pState);
473	break;
474
475	case VPCI_QUEUE_SEL:
476	Assert(cb == 2);
477	u32 &= 0xFFFF;
478	if (u32 < pState->nQueues)
479	pState->uQueueSelector = u32;
480	else
481	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", szInst, u32));
482	break;
483
484	case VPCI_QUEUE_NOTIFY:
485	#ifdef IN_RING3
486	Assert(cb == 2);
487	u32 &= 0xFFFF;
488	if (u32 < pState->nQueues)
489	if (pState->Queues[u32].VRing.addrDescriptors)
490	{
491	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
492	// if (RT_LIKELY(rc == VINF_SUCCESS))
493	// {
494	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
495	// vpciCsLeave(pState);
496	// }
497	}
498	else
499	Log(("%s The queue (#%d) being notified has not been initialized.\n",
500	INSTANCE(pState), u32));
501	else
502	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
503	#else
504	rc = VINF_IOM_R3_IOPORT_WRITE;
505	#endif
506	break;
507
508	case VPCI_STATUS:
509	Assert(cb == 1);
510	u32 &= 0xFF;
511	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
512	pState->uStatus = u32;
513	/* Writing 0 to the status port triggers device reset. */
514	if (u32 == 0)
515	rc = pfnReset(pState);
516	else if (fHasBecomeReady)
517	pfnReady(pState);
518	break;
519
520	default:
521	if (Port >= VPCI_CONFIG)
522	rc = pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
523	else
524	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
525	szInst, Port, cb);
526	break;
527	}
528
529	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
530	return rc;
531	}
532
533	#ifdef IN_RING3
534
535	/**
536	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
537	*/
538	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
539	{
540	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
541	Assert(&pThis->IBase == pInterface);
542
543	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
544	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
545	return NULL;
546	}
547
548	/**
549	* Gets the pointer to the status LED of a unit.
550	*
551	* @returns VBox status code.
552	* @param pInterface Pointer to the interface structure.
553	* @param iLUN The unit which status LED we desire.
554	* @param ppLed Where to store the LED pointer.
555	* @thread EMT
556	*/
557	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
558	{
559	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
560	int rc = VERR_PDM_LUN_NOT_FOUND;
561
562	if (iLUN == 0)
563	{
564	*ppLed = &pState->led;
565	rc = VINF_SUCCESS;
566	}
567	return rc;
568	}
569
570	/**
571	* Turns on/off the write status LED.
572	*
573	* @returns VBox status code.
574	* @param pState Pointer to the device state structure.
575	* @param fOn New LED state.
576	*/
577	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
578	{
579	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
580	if (fOn)
581	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
582	else
583	pState->led.Actual.s.fWriting = fOn;
584	}
585
586	/**
587	* Turns on/off the read status LED.
588	*
589	* @returns VBox status code.
590	* @param pState Pointer to the device state structure.
591	* @param fOn New LED state.
592	*/
593	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
594	{
595	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
596	if (fOn)
597	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
598	else
599	pState->led.Actual.s.fReading = fOn;
600	}
601
602	/**
603	* Sets 8-bit register in PCI configuration space.
604	* @param refPciDev The PCI device.
605	* @param uOffset The register offset.
606	* @param u16Value The value to store in the register.
607	* @thread EMT
608	*/
609	DECLINLINE(void) vpciCfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
610	{
611	Assert(uOffset < sizeof(refPciDev.config));
612	refPciDev.config[uOffset] = u8Value;
613	}
614
615	/**
616	* Sets 16-bit register in PCI configuration space.
617	* @param refPciDev The PCI device.
618	* @param uOffset The register offset.
619	* @param u16Value The value to store in the register.
620	* @thread EMT
621	*/
622	DECLINLINE(void) vpciCfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
623	{
624	Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
625	(uint16_t)&refPciDev.config[uOffset] = u16Value;
626	}
627
628	/**
629	* Sets 32-bit register in PCI configuration space.
630	* @param refPciDev The PCI device.
631	* @param uOffset The register offset.
632	* @param u32Value The value to store in the register.
633	* @thread EMT
634	*/
635	DECLINLINE(void) vpciCfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
636	{
637	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
638	(uint32_t)&refPciDev.config[uOffset] = u32Value;
639	}
640
641
642	#ifdef DEBUG
643	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
644	{
645	Log2(("vpciDumpState: (called from %s)\n"
646	" uGuestFeatures = 0x%08x\n"
647	" uQueueSelector = 0x%04x\n"
648	" uStatus = 0x%02x\n"
649	" uISR = 0x%02x\n",
650	pcszCaller,
651	pState->uGuestFeatures,
652	pState->uQueueSelector,
653	pState->uStatus,
654	pState->uISR));
655
656	for (unsigned i = 0; i < pState->nQueues; i++)
657	Log2((" %s queue:\n"
658	" VRing.uSize = %u\n"
659	" VRing.addrDescriptors = %p\n"
660	" VRing.addrAvail = %p\n"
661	" VRing.addrUsed = %p\n"
662	" uNextAvailIndex = %u\n"
663	" uNextUsedIndex = %u\n"
664	" uPageNumber = %x\n",
665	pState->Queues[i].pcszName,
666	pState->Queues[i].VRing.uSize,
667	pState->Queues[i].VRing.addrDescriptors,
668	pState->Queues[i].VRing.addrAvail,
669	pState->Queues[i].VRing.addrUsed,
670	pState->Queues[i].uNextAvailIndex,
671	pState->Queues[i].uNextUsedIndex,
672	pState->Queues[i].uPageNumber));
673	}
674	#else
675	# define vpciDumpState(x, s) do {} while (0)
676	#endif
677
678	/**
679	* Saves the state of device.
680	*
681	* @returns VBox status code.
682	* @param pDevIns The device instance.
683	* @param pSSM The handle to the saved state.
684	*/
685	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
686	{
687	int rc;
688
689	vpciDumpState(pState, "vpciSaveExec");
690
691	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
692	AssertRCReturn(rc, rc);
693	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
694	AssertRCReturn(rc, rc);
695	rc = SSMR3PutU8( pSSM, pState->uStatus);
696	AssertRCReturn(rc, rc);
697	rc = SSMR3PutU8( pSSM, pState->uISR);
698	AssertRCReturn(rc, rc);
699
700	/* Save queue states */
701	rc = SSMR3PutU32(pSSM, pState->nQueues);
702	AssertRCReturn(rc, rc);
703	for (unsigned i = 0; i < pState->nQueues; i++)
704	{
705	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
706	AssertRCReturn(rc, rc);
707	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
708	AssertRCReturn(rc, rc);
709	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
710	AssertRCReturn(rc, rc);
711	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
712	AssertRCReturn(rc, rc);
713	}
714
715	return VINF_SUCCESS;
716	}
717
718	/**
719	* Loads a saved device state.
720	*
721	* @returns VBox status code.
722	* @param pDevIns The device instance.
723	* @param pSSM The handle to the saved state.
724	* @param uVersion The data unit version number.
725	* @param uPass The data pass.
726	*/
727	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
728	{
729	int rc;
730
731	if (uPass == SSM_PASS_FINAL)
732	{
733	/* Restore state data */
734	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
735	AssertRCReturn(rc, rc);
736	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
737	AssertRCReturn(rc, rc);
738	rc = SSMR3GetU8( pSSM, &pState->uStatus);
739	AssertRCReturn(rc, rc);
740	rc = SSMR3GetU8( pSSM, &pState->uISR);
741	AssertRCReturn(rc, rc);
742
743	/* Restore queues */
744	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
745	{
746	rc = SSMR3GetU32(pSSM, &pState->nQueues);
747	AssertRCReturn(rc, rc);
748	}
749	else
750	pState->nQueues = nQueues;
751	for (unsigned i = 0; i < pState->nQueues; i++)
752	{
753	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
754	AssertRCReturn(rc, rc);
755	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
756	AssertRCReturn(rc, rc);
757
758	if (pState->Queues[i].uPageNumber)
759	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
760
761	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
762	AssertRCReturn(rc, rc);
763	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
764	AssertRCReturn(rc, rc);
765	}
766	}
767
768	vpciDumpState(pState, "vpciLoadExec");
769
770	return VINF_SUCCESS;
771	}
772
773	/**
774	* Set PCI configuration space registers.
775	*
776	* @param pci Reference to PCI device structure.
777	* @param uSubsystemId PCI Subsystem Id
778	* @param uClass Class of PCI device (network, etc)
779	* @thread EMT
780	*/
781	static DECLCALLBACK(void) vpciConfigure(PCIDEVICE& pci,
782	uint16_t uSubsystemId,
783	uint16_t uClass)
784	{
785	/* Configure PCI Device, assume 32-bit mode ******************************/
786	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
787	PCIDevSetDeviceId(&pci, DEVICE_PCI_DEVICE_ID);
788	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
789	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, uSubsystemId);
790
791	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
792	vpciCfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x00);
793	/* Ethernet adapter */
794	vpciCfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
795	vpciCfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, uClass);
796	/* Interrupt Pin: INTA# */
797	vpciCfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
798
799	#ifdef VBOX_WITH_MSI_DEVICES
800	PCIDevSetCapabilityList (&pci, 0x80);
801	PCIDevSetStatus (&pci, VBOX_PCI_STATUS_CAP_LIST);
802	#endif
803	}
804
805	/* WARNING! This function must never be used in multithreaded context! */
806	static const char vpciCounter(const char pszDevFmt,
807	const char *pszCounter)
808	{
809	static char g_szCounterName[80];
810
811	RTStrPrintf(g_szCounterName, sizeof(g_szCounterName),
812	"/Devices/%s/%s", pszDevFmt, pszCounter);
813
814	return g_szCounterName;
815	}
816
817	// TODO: header
818	DECLCALLBACK(int) vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
819	int iInstance, const char *pcszNameFmt,
820	uint16_t uSubsystemId, uint16_t uClass,
821	uint32_t nQueues)
822	{
823	/* Init handles and log related stuff. */
824	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
825	pcszNameFmt, iInstance);
826
827	pState->pDevInsR3 = pDevIns;
828	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
829	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
830	pState->led.u32Magic = PDMLED_MAGIC;
831
832	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
833
834	/* Initialize critical section. */
835	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
836	if (RT_FAILURE(rc))
837	return rc;
838
839	/* Set PCI config registers */
840	vpciConfigure(pState->pciDevice, uSubsystemId, uClass);
841	/* Register PCI device */
842	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
843	if (RT_FAILURE(rc))
844	return rc;
845
846	#ifdef VBOX_WITH_MSI_DEVICES
847	#if 0
848	{
849	PDMMSIREG aMsiReg;
850
851	RT_ZERO(aMsiReg);
852	aMsiReg.cMsixVectors = 1;
853	aMsiReg.iMsixCapOffset = 0x80;
854	aMsiReg.iMsixNextOffset = 0x0;
855	aMsiReg.iMsixBar = 0;
856	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
857	if (RT_FAILURE (rc))
858	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
859	}
860	#endif
861	#endif
862
863	/* Status driver */
864	PPDMIBASE pBase;
865	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
866	if (RT_FAILURE(rc))
867	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
868	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
869
870	pState->nQueues = nQueues;
871
872	#if defined(VBOX_WITH_STATISTICS)
873	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
874	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
875	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
876	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
877	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
878	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
879	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
880	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
881	#endif /* VBOX_WITH_STATISTICS */
882
883	return rc;
884	}
885
886	/**
887	* Destruct PCI-related part of device.
888	*
889	* We need to free non-VM resources only.
890	*
891	* @returns VBox status.
892	* @param pState The device state structure.
893	*/
894	int vpciDestruct(VPCISTATE* pState)
895	{
896	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
897
898	if (PDMCritSectIsInitialized(&pState->cs))
899	PDMR3CritSectDelete(&pState->cs);
900
901	return VINF_SUCCESS;
902	}
903
904	/**
905	* Device relocation callback.
906	*
907	* When this callback is called the device instance data, and if the
908	* device have a GC component, is being relocated, or/and the selectors
909	* have been changed. The device must use the chance to perform the
910	* necessary pointer relocations and data updates.
911	*
912	* Before the GC code is executed the first time, this function will be
913	* called with a 0 delta so GC pointer calculations can be one in one place.
914	*
915	* @param pDevIns Pointer to the device instance.
916	* @param offDelta The relocation delta relative to the old location.
917	*
918	* @remark A relocation CANNOT fail.
919	*/
920	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
921	{
922	VPCISTATE* pState = PDMINS_2_DATA(pDevIns, VPCISTATE*);
923	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
924	// TBD
925	}
926
927	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize,
928	void (pfnCallback)(void pvState, PVQUEUE pQueue),
929	const char *pcszName)
930	{
931	PVQUEUE pQueue = NULL;
932	/* Find an empty queue slot */
933	for (unsigned i = 0; i < pState->nQueues; i++)
934	{
935	if (pState->Queues[i].VRing.uSize == 0)
936	{
937	pQueue = &pState->Queues[i];
938	break;
939	}
940	}
941
942	if (!pQueue)
943	{
944	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
945	}
946	else
947	{
948	pQueue->VRing.uSize = uSize;
949	pQueue->VRing.addrDescriptors = 0;
950	pQueue->uPageNumber = 0;
951	pQueue->pfnCallback = pfnCallback;
952	pQueue->pcszName = pcszName;
953	}
954
955	return pQueue;
956	}
957
958	#endif /* IN_RING3 */
959
960	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 44849

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