VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.h@ 25675

最後變更 在這個檔案從25675是 25675,由 vboxsync 提交於 15 年 前

LsiLogic: Introduce NumPorts configuration parameter to configure the number of ports for the SAS controller. Allows up to 255 disks attached to one controller
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
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1/* $Id: DevLsiLogicSCSI.h 25675 2010-01-07 01:11:59Z vboxsync $ */
2/** @file
3 * VBox storage devices: LsiLogic LSI53c1030 SCSI controller - Defines and structures.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21#ifndef __DEVLSILOGICSCSI_H__
22#define __DEVLSILOGICSCSI_H__
23
24#include <iprt/stdint.h>
25
26/*
27 * I/O port registered in the ISA compatible range to let the BIOS access
28 * the controller.
29 */
30#define LSILOGIC_ISA_IO_PORT 0x340
31
32#define LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT 1024
33#define LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT 128
34
35#define LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH 3
36
37#define LSILOGIC_NR_OF_ALLOWED_BIGGER_LISTS 100
38
39/** Equal for all devices */
40#define LSILOGICSCSI_PCI_VENDOR_ID (0x1000)
41
42/** SPI SCSI controller (LSI53C1030) */
43#define LSILOGICSCSI_PCI_SPI_CTRLNAME "LSI53C1030"
44#define LSILOGICSCSI_PCI_SPI_DEVICE_ID (0x0030)
45#define LSILOGICSCSI_PCI_SPI_REVISION_ID (0x00)
46#define LSILOGICSCSI_PCI_SPI_CLASS_CODE (0x01)
47#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID (0x1000)
48#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID (0x8000)
49#define LSILOGICSCSI_PCI_SPI_PORTS_MAX 1
50#define LSILOGICSCSI_PCI_SPI_BUSES_MAX 1
51#define LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX 16
52#define LSILOGICSCSI_PCI_SPI_DEVICES_MAX (LSILOGICSCSI_PCI_SPI_BUSES_MAX*LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX)
53
54/** SAS SCSI controller (SAS1068 PCI-X Fusion-MPT SAS) */
55#define LSILOGICSCSI_PCI_SAS_CTRLNAME "SAS1068"
56#define LSILOGICSCSI_PCI_SAS_DEVICE_ID (0x0054)
57#define LSILOGICSCSI_PCI_SAS_REVISION_ID (0x00)
58#define LSILOGICSCSI_PCI_SAS_CLASS_CODE (0x00)
59#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID (0x1000)
60#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID (0x8000)
61#define LSILOGICSCSI_PCI_SAS_PORTS_MAX 256
62#define LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT 8
63#define LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX 1
64#define LSILOGICSCSI_PCI_SAS_DEVICES_MAX (LSILOGICSCSI_PCI_SAS_PORTS_MAX * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX)
65
66/**
67 * A SAS address.
68 */
69#pragma pack(1)
70typedef union SASADDRESS
71{
72 /** 64bit view. */
73 uint64_t u64Address;
74 /** 32bit view. */
75 uint32_t u32Address[2];
76 /** 16bit view. */
77 uint16_t u16Address[4];
78 /** Byte view. */
79 uint8_t u8Address[8];
80} SASADDRESS, *PSASADDRESS;
81#pragma pack()
82AssertCompileSize(SASADDRESS, 8);
83
84/**
85 * Possible device types we support.
86 */
87typedef enum LSILOGICCTRLTYPE
88{
89 /** SPI SCSI controller (PCI dev id 0x0030) */
90 LSILOGICCTRLTYPE_SCSI_SPI = 0,
91 /** SAS SCSI controller (PCI dev id 0x0054) */
92 LSILOGICCTRLTYPE_SCSI_SAS = 1,
93 /** 32bit hack */
94 LSILOGICCTRLTYPE_32BIT_HACK = 0x7fffffff
95} LSILOGICCTRLTYPE, *PLSILOGICCTRLTYPE;
96
97/**
98 * A simple SG element for a 64bit adress.
99 */
100#pragma pack(1)
101typedef struct MptSGEntrySimple64
102{
103 /** Length of the buffer this entry describes. */
104 unsigned u24Length: 24;
105 /** Flag whether this element is the end of the list. */
106 unsigned fEndOfList: 1;
107 /** Flag whether the address is 32bit or 64bits wide. */
108 unsigned f64BitAddress: 1;
109 /** Flag whether this buffer contains data to be transfered or is the destination. */
110 unsigned fBufferContainsData: 1;
111 /** Flag whether this is a local address or a system address. */
112 unsigned fLocalAddress: 1;
113 /** Element type. */
114 unsigned u2ElementType: 2;
115 /** Flag whether this is the last element of the buffer. */
116 unsigned fEndOfBuffer: 1;
117 /** Flag whether this is the last element of the current segment. */
118 unsigned fLastElement: 1;
119 /** Lower 32bits of the address of the data buffer. */
120 unsigned u32DataBufferAddressLow: 32;
121 /** Upper 32bits of the address of the data buffer. */
122 unsigned u32DataBufferAddressHigh: 32;
123} MptSGEntrySimple64, *PMptSGEntrySimple64;
124#pragma pack()
125AssertCompileSize(MptSGEntrySimple64, 12);
126
127/**
128 * A simple SG element for a 32bit adress.
129 */
130#pragma pack(1)
131typedef struct MptSGEntrySimple32
132{
133 /** Length of the buffer this entry describes. */
134 unsigned u24Length: 24;
135 /** Flag whether this element is the end of the list. */
136 unsigned fEndOfList: 1;
137 /** Flag whether the address is 32bit or 64bits wide. */
138 unsigned f64BitAddress: 1;
139 /** Flag whether this buffer contains data to be transfered or is the destination. */
140 unsigned fBufferContainsData: 1;
141 /** Flag whether this is a local address or a system address. */
142 unsigned fLocalAddress: 1;
143 /** Element type. */
144 unsigned u2ElementType: 2;
145 /** Flag whether this is the last element of the buffer. */
146 unsigned fEndOfBuffer: 1;
147 /** Flag whether this is the last element of the current segment. */
148 unsigned fLastElement: 1;
149 /** Lower 32bits of the address of the data buffer. */
150 unsigned u32DataBufferAddressLow: 32;
151} MptSGEntrySimple32, *PMptSGEntrySimple32;
152#pragma pack()
153AssertCompileSize(MptSGEntrySimple32, 8);
154
155/**
156 * A chain SG element.
157 */
158#pragma pack(1)
159typedef struct MptSGEntryChain
160{
161 /** Size of the segment. */
162 unsigned u16Length: 16;
163 /** Offset in 32bit words of the next chain element in the segment
164 * identified by this element. */
165 unsigned u8NextChainOffset: 8;
166 /** Reserved. */
167 unsigned fReserved0: 1;
168 /** Flag whether the address is 32bit or 64bits wide. */
169 unsigned f64BitAddress: 1;
170 /** Reserved. */
171 unsigned fReserved1: 1;
172 /** Flag whether this is a local address or a system address. */
173 unsigned fLocalAddress: 1;
174 /** Element type. */
175 unsigned u2ElementType: 2;
176 /** Flag whether this is the last element of the buffer. */
177 unsigned u2Reserved2: 2;
178 /** Lower 32bits of the address of the data buffer. */
179 unsigned u32SegmentAddressLow: 32;
180 /** Upper 32bits of the address of the data buffer. */
181 unsigned u32SegmentAddressHigh: 32;
182} MptSGEntryChain, *PMptSGEntryChain;
183#pragma pack()
184AssertCompileSize(MptSGEntryChain, 12);
185
186typedef union MptSGEntryUnion
187{
188 MptSGEntrySimple64 Simple64;
189 MptSGEntrySimple32 Simple32;
190 MptSGEntryChain Chain;
191} MptSGEntryUnion, *PMptSGEntryUnion;
192
193/**
194 * MPT Fusion message header - Common for all message frames.
195 * This is filled in by the guest.
196 */
197#pragma pack(1)
198typedef struct MptMessageHdr
199{
200 /** Function dependent data. */
201 uint16_t u16FunctionDependent;
202 /** Chain offset. */
203 uint8_t u8ChainOffset;
204 /** The function code. */
205 uint8_t u8Function;
206 /** Function dependent data. */
207 uint8_t au8FunctionDependent[3];
208 /** Message flags. */
209 uint8_t u8MessageFlags;
210 /** Message context - Unique ID from the guest unmodified by the device. */
211 uint32_t u32MessageContext;
212} MptMessageHdr, *PMptMessageHdr;
213#pragma pack()
214AssertCompileSize(MptMessageHdr, 12);
215
216/** Defined function codes found in the message header. */
217#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST (0x00)
218#define MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT (0x01)
219#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT (0x02)
220#define MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS (0x03)
221#define MPT_MESSAGE_HDR_FUNCTION_CONFIG (0x04)
222#define MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS (0x05)
223#define MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE (0x06)
224#define MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION (0x07)
225#define MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK (0x08)
226#define MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD (0x09)
227#define MPT_MESSAGE_HDR_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A)
228#define MPT_MESSAGE_HDR_FUNCTION_TARGET_ASSIST (0x0B)
229#define MPT_MESSAGE_HDR_FUNCTION_TARGET_STATUS_SEND (0x0C)
230#define MPT_MESSAGE_HDR_FUNCTION_TARGET_MODE_ABORT (0x0D)
231
232#ifdef DEBUG
233/**
234 * Function names
235 */
236static const char * const g_apszMPTFunctionNames[] =
237{
238 "SCSI I/O Request",
239 "SCSI Task Management",
240 "IOC Init",
241 "IOC Facts",
242 "Config",
243 "Port Facts",
244 "Port Enable",
245 "Event Notification",
246 "Event Ack",
247 "Firmware Download"
248};
249#endif
250
251/**
252 * Default reply message.
253 * Send from the device to the guest upon completion of a request.
254 */
255 #pragma pack(1)
256typedef struct MptDefaultReplyMessage
257{
258 /** Function dependent data. */
259 uint16_t u16FunctionDependent;
260 /** Length of the message in 32bit DWords. */
261 uint8_t u8MessageLength;
262 /** Function which completed. */
263 uint8_t u8Function;
264 /** Function dependent. */
265 uint8_t au8FunctionDependent[3];
266 /** Message flags. */
267 uint8_t u8MessageFlags;
268 /** Message context given in the request. */
269 uint32_t u32MessageContext;
270 /** Function dependent status code. */
271 uint16_t u16FunctionDependentStatus;
272 /** Status of the IOC. */
273 uint16_t u16IOCStatus;
274 /** Additional log info. */
275 uint32_t u32IOCLogInfo;
276} MptDefaultReplyMessage, *PMptDefaultReplyMessage;
277#pragma pack()
278AssertCompileSize(MptDefaultReplyMessage, 20);
279
280/**
281 * IO controller init request.
282 */
283#pragma pack(1)
284typedef struct MptIOCInitRequest
285{
286 /** Which system send this init request. */
287 uint8_t u8WhoInit;
288 /** Reserved */
289 uint8_t u8Reserved;
290 /** Chain offset in the SG list. */
291 uint8_t u8ChainOffset;
292 /** Function to execute. */
293 uint8_t u8Function;
294 /** Flags */
295 uint8_t u8Flags;
296 /** Maximum number of devices the driver can handle. */
297 uint8_t u8MaxDevices;
298 /** Maximum number of buses the driver can handle. */
299 uint8_t u8MaxBuses;
300 /** Message flags. */
301 uint8_t u8MessageFlags;
302 /** Message context ID. */
303 uint32_t u32MessageContext;
304 /** Reply frame size. */
305 uint16_t u16ReplyFrameSize;
306 /** Reserved */
307 uint16_t u16Reserved;
308 /** Upper 32bit part of the 64bit address the message frames are in.
309 * That means all frames must be in the same 4GB segment. */
310 uint32_t u32HostMfaHighAddr;
311 /** Upper 32bit of the sense buffer. */
312 uint32_t u32SenseBufferHighAddr;
313} MptIOCInitRequest, *PMptIOCInitRequest;
314#pragma pack()
315AssertCompileSize(MptIOCInitRequest, 24);
316
317/**
318 * IO controller init reply.
319 */
320#pragma pack(1)
321typedef struct MptIOCInitReply
322{
323 /** Which subsystem send this init request. */
324 uint8_t u8WhoInit;
325 /** Reserved */
326 uint8_t u8Reserved;
327 /** Message length */
328 uint8_t u8MessageLength;
329 /** Function. */
330 uint8_t u8Function;
331 /** Flags */
332 uint8_t u8Flags;
333 /** Maximum number of devices the driver can handle. */
334 uint8_t u8MaxDevices;
335 /** Maximum number of busses the driver can handle. */
336 uint8_t u8MaxBuses;
337 /** Message flags. */
338 uint8_t u8MessageFlags;
339 /** Message context ID */
340 uint32_t u32MessageContext;
341 /** Reserved */
342 uint16_t u16Reserved;
343 /** IO controller status. */
344 uint16_t u16IOCStatus;
345 /** IO controller log information. */
346 uint32_t u32IOCLogInfo;
347} MptIOCInitReply, *PMptIOCInitReply;
348#pragma pack()
349AssertCompileSize(MptIOCInitReply, 20);
350
351/**
352 * IO controller facts request.
353 */
354#pragma pack(1)
355typedef struct MptIOCFactsRequest
356{
357 /** Reserved. */
358 uint16_t u16Reserved;
359 /** Chain offset in SG list. */
360 uint8_t u8ChainOffset;
361 /** Function number. */
362 uint8_t u8Function;
363 /** Reserved */
364 uint8_t u8Reserved[3];
365 /** Message flags. */
366 uint8_t u8MessageFlags;
367 /** Message context ID. */
368 uint32_t u32MessageContext;
369} MptIOCFactsRequest, *PMptIOCFactsRequest;
370#pragma pack()
371AssertCompileSize(MptIOCFactsRequest, 12);
372
373/**
374 * IO controller facts reply.
375 */
376#pragma pack(1)
377typedef struct MptIOCFactsReply
378{
379 /** Message version. */
380 uint16_t u16MessageVersion;
381 /** Message length. */
382 uint8_t u8MessageLength;
383 /** Function number. */
384 uint8_t u8Function;
385 /** Reserved */
386 uint16_t u16Reserved1;
387 /** IO controller number */
388 uint8_t u8IOCNumber;
389 /** Message flags. */
390 uint8_t u8MessageFlags;
391 /** Message context ID. */
392 uint32_t u32MessageContext;
393 /** IO controller exceptions */
394 uint16_t u16IOCExceptions;
395 /** IO controller status. */
396 uint16_t u16IOCStatus;
397 /** IO controller log information. */
398 uint32_t u32IOCLogInfo;
399 /** Maximum chain depth. */
400 uint8_t u8MaxChainDepth;
401 /** The current value of the WhoInit field. */
402 uint8_t u8WhoInit;
403 /** Block size. */
404 uint8_t u8BlockSize;
405 /** Flags. */
406 uint8_t u8Flags;
407 /** Depth of the reply queue. */
408 uint16_t u16ReplyQueueDepth;
409 /** Size of a request frame. */
410 uint16_t u16RequestFrameSize;
411 /** Reserved */
412 uint16_t u16Reserved2;
413 /** Product ID. */
414 uint16_t u16ProductID;
415 /** Current value of the high 32bit MFA address. */
416 uint32_t u32CurrentHostMFAHighAddr;
417 /** Global credits - Number of entries allocated to queues */
418 uint16_t u16GlobalCredits;
419 /** Number of ports on the IO controller */
420 uint8_t u8NumberOfPorts;
421 /** Event state. */
422 uint8_t u8EventState;
423 /** Current value of the high 32bit sense buffer address. */
424 uint32_t u32CurrentSenseBufferHighAddr;
425 /** Current reply frame size. */
426 uint16_t u16CurReplyFrameSize;
427 /** Maximum number of devices. */
428 uint8_t u8MaxDevices;
429 /** Maximum number of buses. */
430 uint8_t u8MaxBuses;
431 /** Size of the firmware image. */
432 uint32_t u32FwImageSize;
433 /** Reserved. */
434 uint32_t u32Reserved;
435 /** Firmware version */
436 uint32_t u32FWVersion;
437} MptIOCFactsReply, *PMptIOCFactsReply;
438#pragma pack()
439AssertCompileSize(MptIOCFactsReply, 60);
440
441/**
442 * Port facts request
443 */
444#pragma pack(1)
445typedef struct MptPortFactsRequest
446{
447 /** Reserved */
448 uint16_t u16Reserved1;
449 /** Message length. */
450 uint8_t u8MessageLength;
451 /** Function number. */
452 uint8_t u8Function;
453 /** Reserved */
454 uint16_t u16Reserved2;
455 /** Port number to get facts for. */
456 uint8_t u8PortNumber;
457 /** Message flags. */
458 uint8_t u8MessageFlags;
459 /** Message context ID. */
460 uint32_t u32MessageContext;
461} MptPortFactsRequest, *PMptPortFactsRequest;
462#pragma pack()
463AssertCompileSize(MptPortFactsRequest, 12);
464
465/**
466 * Port facts reply.
467 */
468#pragma pack(1)
469typedef struct MptPortFactsReply
470{
471 /** Reserved. */
472 uint16_t u16Reserved1;
473 /** Message length. */
474 uint8_t u8MessageLength;
475 /** Function number. */
476 uint8_t u8Function;
477 /** Reserved */
478 uint16_t u16Reserved2;
479 /** Port number the facts are for. */
480 uint8_t u8PortNumber;
481 /** Message flags. */
482 uint8_t u8MessageFlags;
483 /** Message context ID. */
484 uint32_t u32MessageContext;
485 /** Reserved. */
486 uint16_t u16Reserved3;
487 /** IO controller status. */
488 uint16_t u16IOCStatus;
489 /** IO controller log information. */
490 uint32_t u32IOCLogInfo;
491 /** Reserved */
492 uint8_t u8Reserved;
493 /** Port type */
494 uint8_t u8PortType;
495 /** Maximum number of devices on this port. */
496 uint16_t u16MaxDevices;
497 /** SCSI ID of this port on the attached bus. */
498 uint16_t u16PortSCSIID;
499 /** Protocol flags. */
500 uint16_t u16ProtocolFlags;
501 /** Maxmimum number of target command buffers which can be posted to this port at a time. */
502 uint16_t u16MaxPostedCmdBuffers;
503 /** Maximum number of target IDs that remain persistent between power/reset cycles. */
504 uint16_t u16MaxPersistentIDs;
505 /** Maximum number of LAN buckets. */
506 uint16_t u16MaxLANBuckets;
507 /** Reserved. */
508 uint16_t u16Reserved4;
509 /** Reserved. */
510 uint32_t u32Reserved;
511} MptPortFactsReply, *PMptPortFactsReply;
512#pragma pack()
513AssertCompileSize(MptPortFactsReply, 40);
514
515/**
516 * Port Enable request.
517 */
518#pragma pack(1)
519typedef struct MptPortEnableRequest
520{
521 /** Reserved. */
522 uint16_t u16Reserved1;
523 /** Message length. */
524 uint8_t u8MessageLength;
525 /** Function number. */
526 uint8_t u8Function;
527 /** Reserved. */
528 uint16_t u16Reserved2;
529 /** Port number to enable. */
530 uint8_t u8PortNumber;
531 /** Message flags. */
532 uint8_t u8MessageFlags;
533 /** Message context ID. */
534 uint32_t u32MessageContext;
535} MptPortEnableRequest, *PMptPortEnableRequest;
536#pragma pack()
537AssertCompileSize(MptPortEnableRequest, 12);
538
539/**
540 * Port enable reply.
541 */
542#pragma pack(1)
543typedef struct MptPortEnableReply
544{
545 /** Reserved. */
546 uint16_t u16Reserved1;
547 /** Message length. */
548 uint8_t u8MessageLength;
549 /** Function number. */
550 uint8_t u8Function;
551 /** Reserved */
552 uint16_t u16Reserved2;
553 /** Port number which was enabled. */
554 uint8_t u8PortNumber;
555 /** Message flags. */
556 uint8_t u8MessageFlags;
557 /** Message context ID. */
558 uint32_t u32MessageContext;
559 /** Reserved. */
560 uint16_t u16Reserved3;
561 /** IO controller status */
562 uint16_t u16IOCStatus;
563 /** IO controller log information. */
564 uint32_t u32IOCLogInfo;
565} MptPortEnableReply, *PMptPortEnableReply;
566#pragma pack()
567AssertCompileSize(MptPortEnableReply, 20);
568
569/**
570 * Event notification request.
571 */
572#pragma pack(1)
573typedef struct MptEventNotificationRequest
574{
575 /** Switch - Turns event notification on and off. */
576 uint8_t u8Switch;
577 /** Reserved. */
578 uint8_t u8Reserved1;
579 /** Chain offset. */
580 uint8_t u8ChainOffset;
581 /** Function number. */
582 uint8_t u8Function;
583 /** Reserved. */
584 uint8_t u8reserved2[3];
585 /** Message flags. */
586 uint8_t u8MessageFlags;
587 /** Message context ID. */
588 uint32_t u32MessageContext;
589} MptEventNotificationRequest, *PMptEventNotificationRequest;
590#pragma pack()
591AssertCompileSize(MptEventNotificationRequest, 12);
592
593/**
594 * Event notification reply.
595 */
596#pragma pack(1)
597typedef struct MptEventNotificationReply
598{
599 /** Event data length. */
600 uint16_t u16EventDataLength;
601 /** Message length. */
602 uint8_t u8MessageLength;
603 /** Function number. */
604 uint8_t u8Function;
605 /** Reserved. */
606 uint16_t u16Reserved1;
607 /** Ack required. */
608 uint8_t u8AckRequired;
609 /** Message flags. */
610 uint8_t u8MessageFlags;
611 /** Message context ID. */
612 uint32_t u32MessageContext;
613 /** Reserved. */
614 uint16_t u16Reserved2;
615 /** IO controller status. */
616 uint16_t u16IOCStatus;
617 /** IO controller log information. */
618 uint32_t u32IOCLogInfo;
619 /** Notification event. */
620 uint32_t u32Event;
621 /** Event context. */
622 uint32_t u32EventContext;
623 /** Event data. */
624 uint32_t u32EventData;
625} MptEventNotificationReply, *PMptEventNotificationReply;
626#pragma pack()
627AssertCompileSize(MptEventNotificationReply, 32);
628
629#define MPT_EVENT_EVENT_CHANGE (0x0000000a)
630
631/**
632 * SCSI IO Request
633 */
634#pragma pack(1)
635typedef struct MptSCSIIORequest
636{
637 /** Target ID */
638 uint8_t u8TargetID;
639 /** Bus number */
640 uint8_t u8Bus;
641 /** Chain offset */
642 uint8_t u8ChainOffset;
643 /** Function number. */
644 uint8_t u8Function;
645 /** CDB length. */
646 uint8_t u8CDBLength;
647 /** Sense buffer length. */
648 uint8_t u8SenseBufferLength;
649 /** Rserved */
650 uint8_t u8Reserved;
651 /** Message flags. */
652 uint8_t u8MessageFlags;
653 /** Message context ID. */
654 uint32_t u32MessageContext;
655 /** LUN */
656 uint8_t au8LUN[8];
657 /** Control values. */
658 uint32_t u32Control;
659 /** The CDB. */
660 uint8_t au8CDB[16];
661 /** Data length. */
662 uint32_t u32DataLength;
663 /** Sense buffer low 32bit address. */
664 uint32_t u32SenseBufferLowAddress;
665} MptSCSIIORequest, *PMptSCSIIORequest;
666#pragma pack()
667AssertCompileSize(MptSCSIIORequest, 48);
668
669#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(x) (((x) & 0x3000000) >> 24)
670#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE (0x0)
671#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE (0x1)
672#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ (0x2)
673
674/**
675 * SCSI IO error reply.
676 */
677#pragma pack(1)
678typedef struct MptSCSIIOErrorReply
679{
680 /** Target ID */
681 uint8_t u8TargetID;
682 /** Bus number */
683 uint8_t u8Bus;
684 /** Message length. */
685 uint8_t u8MessageLength;
686 /** Function number. */
687 uint8_t u8Function;
688 /** CDB length */
689 uint8_t u8CDBLength;
690 /** Sense buffer length */
691 uint8_t u8SenseBufferLength;
692 /** Reserved */
693 uint8_t u8Reserved;
694 /** Message flags */
695 uint8_t u8MessageFlags;
696 /** Message context ID */
697 uint32_t u32MessageContext;
698 /** SCSI status. */
699 uint8_t u8SCSIStatus;
700 /** SCSI state */
701 uint8_t u8SCSIState;
702 /** IO controller status */
703 uint16_t u16IOCStatus;
704 /** IO controller log information */
705 uint32_t u32IOCLogInfo;
706 /** Transfer count */
707 uint32_t u32TransferCount;
708 /** Sense count */
709 uint32_t u32SenseCount;
710 /** Response information */
711 uint32_t u32ResponseInfo;
712} MptSCSIIOErrorReply, *PMptSCSIIOErrorReply;
713#pragma pack()
714AssertCompileSize(MptSCSIIOErrorReply, 32);
715
716#define MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID (0x01)
717#define MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED (0x08)
718
719/**
720 * IOC status codes sepcific to the SCSI I/O error reply.
721 */
722#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS (0x0041)
723#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID (0x0042)
724#define MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE (0x0043)
725
726/**
727 * SCSI task management request.
728 */
729#pragma pack(1)
730typedef struct MptSCSITaskManagementRequest
731{
732 /** Target ID */
733 uint8_t u8TargetID;
734 /** Bus number */
735 uint8_t u8Bus;
736 /** Chain offset */
737 uint8_t u8ChainOffset;
738 /** Function number */
739 uint8_t u8Function;
740 /** Reserved */
741 uint8_t u8Reserved1;
742 /** Task type */
743 uint8_t u8TaskType;
744 /** Reserved */
745 uint8_t u8Reserved2;
746 /** Message flags */
747 uint8_t u8MessageFlags;
748 /** Message context ID */
749 uint32_t u32MessageContext;
750 /** LUN */
751 uint8_t au8LUN[8];
752 /** Reserved */
753 uint8_t auReserved[28];
754 /** Task message context ID. */
755 uint32_t u32TaskMessageContext;
756} MptSCSITaskManagementRequest, *PMptSCSITaskManagementRequest;
757#pragma pack()
758AssertCompileSize(MptSCSITaskManagementRequest, 52);
759
760/**
761 * SCSI task management reply.
762 */
763#pragma pack(1)
764typedef struct MptSCSITaskManagementReply
765{
766 /** Target ID */
767 uint8_t u8TargetID;
768 /** Bus number */
769 uint8_t u8Bus;
770 /** Message length */
771 uint8_t u8MessageLength;
772 /** Function number */
773 uint8_t u8Function;
774 /** Reserved */
775 uint8_t u8Reserved1;
776 /** Task type */
777 uint8_t u8TaskType;
778 /** Reserved */
779 uint8_t u8Reserved2;
780 /** Message flags */
781 uint8_t u8MessageFlags;
782 /** Message context ID */
783 uint32_t u32MessageContext;
784 /** Reserved */
785 uint16_t u16Reserved;
786 /** IO controller status */
787 uint16_t u16IOCStatus;
788 /** IO controller log information */
789 uint32_t u32IOCLogInfo;
790 /** Termination count */
791 uint32_t u32TerminationCount;
792} MptSCSITaskManagementReply, *PMptSCSITaskManagementReply;
793#pragma pack()
794AssertCompileSize(MptSCSITaskManagementReply, 24);
795
796/**
797 * Page address for SAS expander page types.
798 */
799#pragma pack(1)
800typedef union MptConfigurationPageAddressSASExpander
801{
802 struct
803 {
804 uint16_t u16Handle;
805 uint16_t u16Reserved;
806 } Form0And2;
807 struct
808 {
809 uint16_t u16Handle;
810 uint8_t u8PhyNum;
811 uint8_t u8Reserved;
812 } Form1;
813} MptConfigurationPageAddressSASExpander, *PMptConfigurationPageAddressSASExpander;
814#pragma pack()
815
816/**
817 * Page address for SAS device page types.
818 */
819#pragma pack(1)
820typedef union MptConfigurationPageAddressSASDevice
821{
822 struct
823 {
824 uint16_t u16Handle;
825 uint16_t u16Reserved;
826 } Form0And2;
827 struct
828 {
829 uint8_t u8TargetID;
830 uint8_t u8Bus;
831 uint8_t u8Reserved;
832 } Form1;
833} MptConfigurationPageAddressSASDevice, *PMptConfigurationPageAddressSASDevice;
834#pragma pack()
835
836/**
837 * Page address for SAS PHY page types.
838 */
839#pragma pack(1)
840typedef union MptConfigurationPageAddressSASPHY
841{
842 struct
843 {
844 uint8_t u8PhyNumber;
845 uint8_t u8Reserved[3];
846 } Form0;
847 struct
848 {
849 uint16_t u16Index;
850 uint16_t u16Reserved;
851 } Form1;
852} MptConfigurationPageAddressSASPHY, *PMptConfigurationPageAddressSASPHY;
853#pragma pack()
854
855/**
856 * Page address for SAS Enclosure page types.
857 */
858#pragma pack(1)
859typedef struct MptConfigurationPageAddressSASEnclosure
860{
861 uint16_t u16Handle;
862 uint16_t u16Reserved;
863} MptConfigurationPageAddressSASEnclosure, *PMptConfigurationPageAddressSASEnclosure;
864#pragma pack()
865
866/**
867 * Union of all possible address types.
868 */
869#pragma pack(1)
870typedef union MptConfigurationPageAddress
871{
872 /** 32bit view. */
873 uint32_t u32PageAddress;
874 struct
875 {
876 /** Port number to get the configuration page for. */
877 uint8_t u8PortNumber;
878 /** Reserved. */
879 uint8_t u8Reserved[3];
880 } MPIPortNumber;
881 struct
882 {
883 /** Target ID to get the configuration page for. */
884 uint8_t u8TargetID;
885 /** Bus number to get the configuration page for. */
886 uint8_t u8Bus;
887 /** Reserved. */
888 uint8_t u8Reserved[2];
889 } BusAndTargetId;
890 MptConfigurationPageAddressSASExpander SASExpander;
891 MptConfigurationPageAddressSASDevice SASDevice;
892 MptConfigurationPageAddressSASPHY SASPHY;
893 MptConfigurationPageAddressSASEnclosure SASEnclosure;
894} MptConfigurationPageAddress, *PMptConfigurationPageAddress;
895#pragma pack()
896AssertCompileSize(MptConfigurationPageAddress, 4);
897
898#define MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(x) (((x).u32PageAddress >> 28) & 0x0f)
899
900/**
901 * Configuration request
902 */
903#pragma pack(1)
904typedef struct MptConfigurationRequest
905{
906 /** Action code. */
907 uint8_t u8Action;
908 /** Reserved. */
909 uint8_t u8Reserved1;
910 /** Chain offset. */
911 uint8_t u8ChainOffset;
912 /** Function number. */
913 uint8_t u8Function;
914 /** Extended page length. */
915 uint16_t u16ExtPageLength;
916 /** Extended page type */
917 uint8_t u8ExtPageType;
918 /** Message flags. */
919 uint8_t u8MessageFlags;
920 /** Message context ID. */
921 uint32_t u32MessageContext;
922 /** Reserved. */
923 uint8_t u8Reserved2[8];
924 /** Version number of the page. */
925 uint8_t u8PageVersion;
926 /** Length of the page in 32bit Dwords. */
927 uint8_t u8PageLength;
928 /** Page number to access. */
929 uint8_t u8PageNumber;
930 /** Type of the page beeing accessed. */
931 uint8_t u8PageType;
932 /** Page type dependent address. */
933 MptConfigurationPageAddress PageAddress;
934 /** Simple SG element describing the buffer. */
935 MptSGEntrySimple64 SimpleSGElement;
936} MptConfigurationRequest, *PMptConfigurationRequest;
937#pragma pack()
938AssertCompileSize(MptConfigurationRequest, 40);
939
940/** Possible action codes. */
941#define MPT_CONFIGURATION_REQUEST_ACTION_HEADER (0x00)
942#define MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT (0x01)
943#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT (0x02)
944#define MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT (0x03)
945#define MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT (0x04)
946#define MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM (0x05)
947#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM (0x06)
948
949/** Page type codes. */
950#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IO_UNIT (0x00)
951#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IOC (0x01)
952#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_BIOS (0x02)
953#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_SCSI_PORT (0x03)
954#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_EXTENDED (0x0F)
955
956/**
957 * Configuration reply.
958 */
959#pragma pack(1)
960typedef struct MptConfigurationReply
961{
962 /** Action code. */
963 uint8_t u8Action;
964 /** Reserved. */
965 uint8_t u8Reserved;
966 /** Message length. */
967 uint8_t u8MessageLength;
968 /** Function number. */
969 uint8_t u8Function;
970 /** Extended page length. */
971 uint16_t u16ExtPageLength;
972 /** Extended page type */
973 uint8_t u8ExtPageType;
974 /** Message flags. */
975 uint8_t u8MessageFlags;
976 /** Message context ID. */
977 uint32_t u32MessageContext;
978 /** Reserved. */
979 uint16_t u16Reserved;
980 /** I/O controller status. */
981 uint16_t u16IOCStatus;
982 /** I/O controller log information. */
983 uint32_t u32IOCLogInfo;
984 /** Version number of the page. */
985 uint8_t u8PageVersion;
986 /** Length of the page in 32bit Dwords. */
987 uint8_t u8PageLength;
988 /** Page number to access. */
989 uint8_t u8PageNumber;
990 /** Type of the page beeing accessed. */
991 uint8_t u8PageType;
992} MptConfigurationReply, *PMptConfigurationReply;
993#pragma pack()
994AssertCompileSize(MptConfigurationReply, 24);
995
996/** Additional I/O controller status codes for the configuration reply. */
997#define MPT_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
998#define MPT_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
999#define MPT_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
1000#define MPT_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
1001#define MPT_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
1002#define MPT_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
1003
1004/**
1005 * Union of all possible request messages.
1006 */
1007typedef union MptRequestUnion
1008{
1009 MptMessageHdr Header;
1010 MptIOCInitRequest IOCInit;
1011 MptIOCFactsRequest IOCFacts;
1012 MptPortFactsRequest PortFacts;
1013 MptPortEnableRequest PortEnable;
1014 MptEventNotificationRequest EventNotification;
1015 MptSCSIIORequest SCSIIO;
1016 MptSCSITaskManagementRequest SCSITaskManagement;
1017 MptConfigurationRequest Configuration;
1018} MptRequestUnion, *PMptRequestUnion;
1019
1020/**
1021 * Union of all possible reply messages.
1022 */
1023typedef union MptReplyUnion
1024{
1025 /** 16bit view. */
1026 uint16_t au16Reply[30];
1027 MptDefaultReplyMessage Header;
1028 MptIOCInitReply IOCInit;
1029 MptIOCFactsReply IOCFacts;
1030 MptPortFactsReply PortFacts;
1031 MptPortEnableReply PortEnable;
1032 MptEventNotificationReply EventNotification;
1033 MptSCSIIOErrorReply SCSIIOError;
1034 MptSCSITaskManagementReply SCSITaskManagement;
1035 MptConfigurationReply Configuration;
1036} MptReplyUnion, *PMptReplyUnion;
1037
1038
1039/**
1040 * Configuration Page attributes.
1041 */
1042#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY (0x00)
1043#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE (0x10)
1044#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT (0x20)
1045#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY (0x30)
1046
1047#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(u8PageType) ((u8PageType) & 0xf0)
1048
1049/**
1050 * Configuration Page types.
1051 */
1052#define MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT (0x00)
1053#define MPT_CONFIGURATION_PAGE_TYPE_IOC (0x01)
1054#define MPT_CONFIGURATION_PAGE_TYPE_BIOS (0x02)
1055#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT (0x03)
1056#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE (0x04)
1057#define MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING (0x09)
1058#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED (0x0F)
1059
1060#define MPT_CONFIGURATION_PAGE_TYPE_GET(u8PageType) ((u8PageType) & 0x0f)
1061
1062/**
1063 * Extented page types.
1064 */
1065#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT (0x10)
1066#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER (0x11)
1067#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE (0x12)
1068#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS (0x13)
1069#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_LOG (0x14)
1070#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE (0x15)
1071
1072/**
1073 * Configuration Page header - Common to all pages.
1074 */
1075#pragma pack(1)
1076typedef struct MptConfigurationPageHeader
1077{
1078 /** Version of the page. */
1079 uint8_t u8PageVersion;
1080 /** The length of the page in 32bit D-Words. */
1081 uint8_t u8PageLength;
1082 /** Number of the page. */
1083 uint8_t u8PageNumber;
1084 /** Type of the page. */
1085 uint8_t u8PageType;
1086} MptConfigurationPageHeader, *PMptConfigurationPageHeader;
1087#pragma pack()
1088AssertCompileSize(MptConfigurationPageHeader, 4);
1089
1090/**
1091 * Extended configuration page header - Common to all extended pages.
1092 */
1093#pragma pack(1)
1094typedef struct MptExtendedConfigurationPageHeader
1095{
1096 /** Version of the page. */
1097 uint8_t u8PageVersion;
1098 /** Reserved. */
1099 uint8_t u8Reserved1;
1100 /** Number of the page. */
1101 uint8_t u8PageNumber;
1102 /** Type of the page. */
1103 uint8_t u8PageType;
1104 /** Extended page length. */
1105 uint16_t u16ExtPageLength;
1106 /** Extended page type. */
1107 uint8_t u8ExtPageType;
1108 /** Reserved */
1109 uint8_t u8Reserved2;
1110} MptExtendedConfigurationPageHeader, *PMptExtendedConfigurationPageHeader;
1111#pragma pack()
1112AssertCompileSize(MptExtendedConfigurationPageHeader, 8);
1113
1114/**
1115 * Manufacturing page 0. - Readonly.
1116 */
1117#pragma pack(1)
1118typedef struct MptConfigurationPageManufacturing0
1119{
1120 /** Union. */
1121 union
1122 {
1123 /** Byte view. */
1124 uint8_t abPageData[76];
1125 /** Field view. */
1126 struct
1127 {
1128 /** The omnipresent header. */
1129 MptConfigurationPageHeader Header;
1130 /** Name of the chip. */
1131 uint8_t abChipName[16];
1132 /** Chip revision. */
1133 uint8_t abChipRevision[8];
1134 /** Board name. */
1135 uint8_t abBoardName[16];
1136 /** Board assembly. */
1137 uint8_t abBoardAssembly[16];
1138 /** Board tracer number. */
1139 uint8_t abBoardTracerNumber[16];
1140 } fields;
1141 } u;
1142} MptConfigurationPageManufacturing0, *PMptConfigurationPageManufacturing0;
1143#pragma pack()
1144AssertCompileSize(MptConfigurationPageManufacturing0, 76);
1145
1146/**
1147 * Manufacturing page 1. - Readonly Persistent.
1148 */
1149#pragma pack(1)
1150typedef struct MptConfigurationPageManufacturing1
1151{
1152 /** Union */
1153 union
1154 {
1155 /** Byte view */
1156 uint8_t abPageData[260];
1157 /** Field view */
1158 struct
1159 {
1160 /** The omnipresent header. */
1161 MptConfigurationPageHeader Header;
1162 /** VPD info - don't know what belongs here so all zero. */
1163 uint8_t abVPDInfo[256];
1164 } fields;
1165 } u;
1166} MptConfigurationPageManufacturing1, *PMptConfigurationPageManufacturing1;
1167#pragma pack()
1168AssertCompileSize(MptConfigurationPageManufacturing1, 260);
1169
1170/**
1171 * Manufacturing page 2. - Readonly.
1172 */
1173#pragma pack(1)
1174typedef struct MptConfigurationPageManufacturing2
1175{
1176 /** Union. */
1177 union
1178 {
1179 /** Byte view. */
1180 uint8_t abPageData[8];
1181 /** Field view. */
1182 struct
1183 {
1184 /** The omnipresent header. */
1185 MptConfigurationPageHeader Header;
1186 /** PCI Device ID. */
1187 uint16_t u16PCIDeviceID;
1188 /** PCI Revision ID. */
1189 uint8_t u8PCIRevisionID;
1190 /** Reserved. */
1191 uint8_t u8Reserved;
1192 /** Hardware specific settings... */
1193 } fields;
1194 } u;
1195} MptConfigurationPageManufacturing2, *PMptConfigurationPageManufacturing2;
1196#pragma pack()
1197AssertCompileSize(MptConfigurationPageManufacturing2, 8);
1198
1199/**
1200 * Manufacturing page 3. - Readonly.
1201 */
1202#pragma pack(1)
1203typedef struct MptConfigurationPageManufacturing3
1204{
1205 /** Union. */
1206 union
1207 {
1208 /** Byte view. */
1209 uint8_t abPageData[8];
1210 /** Field view. */
1211 struct
1212 {
1213 /** The omnipresent header. */
1214 MptConfigurationPageHeader Header;
1215 /** PCI Device ID. */
1216 uint16_t u16PCIDeviceID;
1217 /** PCI Revision ID. */
1218 uint8_t u8PCIRevisionID;
1219 /** Reserved. */
1220 uint8_t u8Reserved;
1221 /** Chip specific settings... */
1222 } fields;
1223 } u;
1224} MptConfigurationPageManufacturing3, *PMptConfigurationPageManufacturing3;
1225#pragma pack()
1226AssertCompileSize(MptConfigurationPageManufacturing3, 8);
1227
1228/**
1229 * Manufacturing page 4. - Readonly.
1230 */
1231#pragma pack(1)
1232typedef struct MptConfigurationPageManufacturing4
1233{
1234 /** Union. */
1235 union
1236 {
1237 /** Byte view. */
1238 uint8_t abPageData[84];
1239 /** Field view. */
1240 struct
1241 {
1242 /** The omnipresent header. */
1243 MptConfigurationPageHeader Header;
1244 /** Reserved. */
1245 uint32_t u32Reserved;
1246 /** InfoOffset0. */
1247 uint8_t u8InfoOffset0;
1248 /** Info size. */
1249 uint8_t u8InfoSize0;
1250 /** InfoOffset1. */
1251 uint8_t u8InfoOffset1;
1252 /** Info size. */
1253 uint8_t u8InfoSize1;
1254 /** Size of the inquiry data. */
1255 uint8_t u8InquirySize;
1256 /** Reserved. */
1257 uint8_t abReserved[3];
1258 /** Inquiry data. */
1259 uint8_t abInquiryData[56];
1260 /** IS volume settings. */
1261 uint32_t u32ISVolumeSettings;
1262 /** IME volume settings. */
1263 uint32_t u32IMEVolumeSettings;
1264 /** IM volume settings. */
1265 uint32_t u32IMVolumeSettings;
1266 } fields;
1267 } u;
1268} MptConfigurationPageManufacturing4, *PMptConfigurationPageManufacturing4;
1269#pragma pack()
1270AssertCompileSize(MptConfigurationPageManufacturing4, 84);
1271
1272/**
1273 * Manufacturing page 5 - Readonly.
1274 */
1275#pragma pack(1)
1276typedef struct MptConfigurationPageManufacturing5
1277{
1278 /** Union. */
1279 union
1280 {
1281 /** Byte view. */
1282 uint8_t abPageData[88];
1283 /** Field view. */
1284 struct
1285 {
1286 /** The omnipresent header. */
1287 MptConfigurationPageHeader Header;
1288 /** Base WWID. */
1289 uint64_t u64BaseWWID;
1290 /** Flags */
1291 uint8_t u8Flags;
1292 /** Number of ForceWWID fields in this page. */
1293 uint8_t u8NumForceWWID;
1294 /** Reserved */
1295 uint16_t u16Reserved;
1296 /** Reserved */
1297 uint32_t au32Reserved[2];
1298 /** ForceWWID entries Maximum of 8 because the SAS controller doesn't has more */
1299 uint64_t au64ForceWWID[8];
1300 } fields;
1301 } u;
1302} MptConfigurationPageManufacturing5, *PMptConfigurationPageManufacturing5;
1303#pragma pack()
1304AssertCompileSize(MptConfigurationPageManufacturing5, 24+64);
1305
1306/**
1307 * Manufacturing page 6 - Readonly.
1308 */
1309#pragma pack(1)
1310typedef struct MptConfigurationPageManufacturing6
1311{
1312 /** Union. */
1313 union
1314 {
1315 /** Byte view. */
1316 uint8_t abPageData[4];
1317 /** Field view. */
1318 struct
1319 {
1320 /** The omnipresent header. */
1321 MptConfigurationPageHeader Header;
1322 /** Product specific data - 0 for now */
1323 } fields;
1324 } u;
1325} MptConfigurationPageManufacturing6, *PMptConfigurationPageManufacturing6;
1326#pragma pack()
1327AssertCompileSize(MptConfigurationPageManufacturing6, 4);
1328
1329/**
1330 * Manufacturing page 7 - Readonly.
1331 */
1332#pragma pack(1)
1333typedef struct MptConfigurationPageManufacturing7
1334{
1335 /** Union. */
1336 union
1337 {
1338 /** Byte view. */
1339 uint8_t abPageData[228];
1340 /** Field view. */
1341 struct
1342 {
1343 /** The omnipresent header. */
1344 MptConfigurationPageHeader Header;
1345 /** Reserved */
1346 uint32_t au32Reserved[2];
1347 /** Flags */
1348 uint32_t u32Flags;
1349 /** Enclosure name */
1350 uint8_t szEnclosureName[16];
1351 /** Nummber of PHYs */
1352 uint8_t u8NumPhys;
1353 /** Reserved */
1354 uint8_t au8Reserved[3];
1355 /** PHY list for the SAS controller */
1356 struct
1357 {
1358 /** Pinout */
1359 uint32_t u32Pinout;
1360 /** Connector name */
1361 uint8_t szConnector[16];
1362 /** Location */
1363 uint8_t u8Location;
1364 /** reserved */
1365 uint8_t u8Reserved;
1366 /** Slot */
1367 uint16_t u16Slot;
1368 } aPHYs[LSILOGICSCSI_PCI_SAS_PORTS_MAX];
1369 } fields;
1370 } u;
1371} MptConfigurationPageManufacturing7, *PMptConfigurationPageManufacturing7;
1372#pragma pack()
1373AssertCompileSize(MptConfigurationPageManufacturing7, 36+(LSILOGICSCSI_PCI_SAS_PORTS_MAX * 24));
1374
1375/** Flags for the flags field */
1376#define LSILOGICSCSI_MANUFACTURING7_FLAGS_USE_PROVIDED_INFORMATION RT_BIT(0)
1377
1378/** Flags for the pinout field */
1379#define LSILOGICSCSI_MANUFACTURING7_PINOUT_UNKNOWN RT_BIT(0)
1380#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8482 RT_BIT(1)
1381#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE1 RT_BIT(8)
1382#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE2 RT_BIT(9)
1383#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE3 RT_BIT(10)
1384#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE4 RT_BIT(11)
1385#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE1 RT_BIT(16)
1386#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE2 RT_BIT(17)
1387#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE3 RT_BIT(18)
1388#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE4 RT_BIT(19)
1389
1390/** Flags for the location field */
1391#define LSILOGICSCSI_MANUFACTURING7_LOCATION_UNKNOWN 0x01
1392#define LSILOGICSCSI_MANUFACTURING7_LOCATION_INTERNAL 0x02
1393#define LSILOGICSCSI_MANUFACTURING7_LOCATION_EXTERNAL 0x04
1394#define LSILOGICSCSI_MANUFACTURING7_LOCATION_SWITCHABLE 0x08
1395#define LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO 0x10
1396#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_PRESENT 0x20
1397#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_CONNECTED 0x80
1398
1399/**
1400 * Manufacturing page 8 - Readonly.
1401 */
1402#pragma pack(1)
1403typedef struct MptConfigurationPageManufacturing8
1404{
1405 /** Union. */
1406 union
1407 {
1408 /** Byte view. */
1409 uint8_t abPageData[4];
1410 /** Field view. */
1411 struct
1412 {
1413 /** The omnipresent header. */
1414 MptConfigurationPageHeader Header;
1415 /** Product specific information */
1416 } fields;
1417 } u;
1418} MptConfigurationPageManufacturing8, *PMptConfigurationPageManufacturing8;
1419#pragma pack()
1420AssertCompileSize(MptConfigurationPageManufacturing8, 4);
1421
1422/**
1423 * Manufacturing page 9 - Readonly.
1424 */
1425#pragma pack(1)
1426typedef struct MptConfigurationPageManufacturing9
1427{
1428 /** Union. */
1429 union
1430 {
1431 /** Byte view. */
1432 uint8_t abPageData[4];
1433 /** Field view. */
1434 struct
1435 {
1436 /** The omnipresent header. */
1437 MptConfigurationPageHeader Header;
1438 /** Product specific information */
1439 } fields;
1440 } u;
1441} MptConfigurationPageManufacturing9, *PMptConfigurationPageManufacturing9;
1442#pragma pack()
1443AssertCompileSize(MptConfigurationPageManufacturing9, 4);
1444
1445/**
1446 * Manufacturing page 10 - Readonly.
1447 */
1448#pragma pack(1)
1449typedef struct MptConfigurationPageManufacturing10
1450{
1451 /** Union. */
1452 union
1453 {
1454 /** Byte view. */
1455 uint8_t abPageData[4];
1456 /** Field view. */
1457 struct
1458 {
1459 /** The omnipresent header. */
1460 MptConfigurationPageHeader Header;
1461 /** Product specific information */
1462 } fields;
1463 } u;
1464} MptConfigurationPageManufacturing10, *PMptConfigurationPageManufacturing10;
1465#pragma pack()
1466AssertCompileSize(MptConfigurationPageManufacturing10, 4);
1467
1468/**
1469 * IO Unit page 0. - Readonly.
1470 */
1471#pragma pack(1)
1472typedef struct MptConfigurationPageIOUnit0
1473{
1474 /** Union. */
1475 union
1476 {
1477 /** Byte view. */
1478 uint8_t abPageData[12];
1479 /** Field view. */
1480 struct
1481 {
1482 /** The omnipresent header. */
1483 MptConfigurationPageHeader Header;
1484 /** A unique identifier. */
1485 uint64_t u64UniqueIdentifier;
1486 } fields;
1487 } u;
1488} MptConfigurationPageIOUnit0, *PMptConfigurationPageIOUnit0;
1489#pragma pack()
1490AssertCompileSize(MptConfigurationPageIOUnit0, 12);
1491
1492/**
1493 * IO Unit page 1. - Read/Write.
1494 */
1495#pragma pack(1)
1496typedef struct MptConfigurationPageIOUnit1
1497{
1498 /** Union. */
1499 union
1500 {
1501 /** Byte view. */
1502 uint8_t abPageData[8];
1503 /** Field view. */
1504 struct
1505 {
1506 /** The omnipresent header. */
1507 MptConfigurationPageHeader Header;
1508 /** Flag whether this is a single function PCI device. */
1509 unsigned fSingleFunction: 1;
1510 /** Flag whether all possible paths to a device are mapped. */
1511 unsigned fAllPathsMapped: 1;
1512 /** Reserved. */
1513 unsigned u4Reserved: 4;
1514 /** Flag whether all RAID functionality is disabled. */
1515 unsigned fIntegratedRAIDDisabled: 1;
1516 /** Flag whether 32bit PCI accesses are forced. */
1517 unsigned f32BitAccessForced: 1;
1518 /** Reserved. */
1519 unsigned abReserved: 24;
1520 } fields;
1521 } u;
1522} MptConfigurationPageIOUnit1, *PMptConfigurationPageIOUnit1;
1523#pragma pack()
1524AssertCompileSize(MptConfigurationPageIOUnit1, 8);
1525
1526/**
1527 * Adapter Ordering.
1528 */
1529#pragma pack(1)
1530typedef struct MptConfigurationPageIOUnit2AdapterOrdering
1531{
1532 /** PCI bus number. */
1533 unsigned u8PCIBusNumber: 8;
1534 /** PCI device and function number. */
1535 unsigned u8PCIDevFn: 8;
1536 /** Flag whether the adapter is embedded. */
1537 unsigned fAdapterEmbedded: 1;
1538 /** Flag whether the adapter is enabled. */
1539 unsigned fAdapterEnabled: 1;
1540 /** Reserved. */
1541 unsigned u6Reserved: 6;
1542 /** Reserved. */
1543 unsigned u8Reserved: 8;
1544} MptConfigurationPageIOUnit2AdapterOrdering, *PMptConfigurationPageIOUnit2AdapterOrdering;
1545#pragma pack()
1546AssertCompileSize(MptConfigurationPageIOUnit2AdapterOrdering, 4);
1547
1548/**
1549 * IO Unit page 2. - Read/Write.
1550 */
1551#pragma pack(1)
1552typedef struct MptConfigurationPageIOUnit2
1553{
1554 /** Union. */
1555 union
1556 {
1557 /** Byte view. */
1558 uint8_t abPageData[28];
1559 /** Field view. */
1560 struct
1561 {
1562 /** The omnipresent header. */
1563 MptConfigurationPageHeader Header;
1564 /** Reserved. */
1565 unsigned fReserved: 1;
1566 /** Flag whether Pause on error is enabled. */
1567 unsigned fPauseOnError: 1;
1568 /** Flag whether verbose mode is enabled. */
1569 unsigned fVerboseModeEnabled: 1;
1570 /** Set to disable color video. */
1571 unsigned fDisableColorVideo: 1;
1572 /** Flag whether int 40h is hooked. */
1573 unsigned fNotHookInt40h: 1;
1574 /** Reserved. */
1575 unsigned u3Reserved: 3;
1576 /** Reserved. */
1577 unsigned abReserved: 24;
1578 /** BIOS version. */
1579 uint32_t u32BIOSVersion;
1580 /** Adapter ordering. */
1581 MptConfigurationPageIOUnit2AdapterOrdering aAdapterOrder[4];
1582 } fields;
1583 } u;
1584} MptConfigurationPageIOUnit2, *PMptConfigurationPageIOUnit2;
1585#pragma pack()
1586AssertCompileSize(MptConfigurationPageIOUnit2, 28);
1587
1588/*
1589 * IO Unit page 3. - Read/Write.
1590 */
1591#pragma pack(1)
1592typedef struct MptConfigurationPageIOUnit3
1593{
1594 /** Union. */
1595 union
1596 {
1597 /** Byte view. */
1598 uint8_t abPageData[8];
1599 /** Field view. */
1600 struct
1601 {
1602 /** The omnipresent header. */
1603 MptConfigurationPageHeader Header;
1604 /** Number of GPIO values. */
1605 uint8_t u8GPIOCount;
1606 /** Reserved. */
1607 uint8_t abReserved[3];
1608 } fields;
1609 } u;
1610} MptConfigurationPageIOUnit3, *PMptConfigurationPageIOUnit3;
1611#pragma pack()
1612AssertCompileSize(MptConfigurationPageIOUnit3, 8);
1613
1614/*
1615 * IO Unit page 4. - Readonly for everyone except the BIOS.
1616 */
1617#pragma pack(1)
1618typedef struct MptConfigurationPageIOUnit4
1619{
1620 /** Union. */
1621 union
1622 {
1623 /** Byte view. */
1624 uint8_t abPageData[20];
1625 /** Field view. */
1626 struct
1627 {
1628 /** The omnipresent header. */
1629 MptConfigurationPageHeader Header;
1630 /** Reserved */
1631 uint32_t u32Reserved;
1632 /** SG entry describing the Firmware location. */
1633 MptSGEntrySimple64 FWImageSGE;
1634 } fields;
1635 } u;
1636} MptConfigurationPageIOUnit4, *PMptConfigurationPageIOUnit4;
1637#pragma pack()
1638AssertCompileSize(MptConfigurationPageIOUnit4, 20);
1639
1640/**
1641 * IOC page 0. - Readonly
1642 */
1643#pragma pack(1)
1644typedef struct MptConfigurationPageIOC0
1645{
1646 /** Union. */
1647 union
1648 {
1649 /** Byte view. */
1650 uint8_t abPageData[28];
1651 /** Field view. */
1652 struct
1653 {
1654 /** The omnipresent header. */
1655 MptConfigurationPageHeader Header;
1656 /** Total ammount of NV memory in bytes. */
1657 uint32_t u32TotalNVStore;
1658 /** Number of free bytes in the NV store. */
1659 uint32_t u32FreeNVStore;
1660 /** PCI vendor ID. */
1661 uint16_t u16VendorId;
1662 /** PCI device ID. */
1663 uint16_t u16DeviceId;
1664 /** PCI revision ID. */
1665 uint8_t u8RevisionId;
1666 /** Reserved. */
1667 uint8_t abReserved[3];
1668 /** PCI class code. */
1669 uint32_t u32ClassCode;
1670 /** Subsystem vendor Id. */
1671 uint16_t u16SubsystemVendorId;
1672 /** Subsystem Id. */
1673 uint16_t u16SubsystemId;
1674 } fields;
1675 } u;
1676} MptConfigurationPageIOC0, *PMptConfigurationPageIOC0;
1677#pragma pack()
1678AssertCompileSize(MptConfigurationPageIOC0, 28);
1679
1680/**
1681 * IOC page 1. - Read/Write
1682 */
1683#pragma pack(1)
1684typedef struct MptConfigurationPageIOC1
1685{
1686 /** Union. */
1687 union
1688 {
1689 /** Byte view. */
1690 uint8_t abPageData[16];
1691 /** Field view. */
1692 struct
1693 {
1694 /** The omnipresent header. */
1695 MptConfigurationPageHeader Header;
1696 /** Flag whether reply coalescing is enabled. */
1697 unsigned fReplyCoalescingEnabled: 1;
1698 /** Reserved. */
1699 unsigned u31Reserved: 31;
1700 /** Coalescing Timeout in microseconds. */
1701 unsigned u32CoalescingTimeout: 32;
1702 /** Coalescing depth. */
1703 unsigned u8CoalescingDepth: 8;
1704 /** Reserved. */
1705 unsigned u8Reserved0: 8;
1706 unsigned u8Reserved1: 8;
1707 unsigned u8Reserved2: 8;
1708 } fields;
1709 } u;
1710} MptConfigurationPageIOC1, *PMptConfigurationPageIOC1;
1711#pragma pack()
1712AssertCompileSize(MptConfigurationPageIOC1, 16);
1713
1714/**
1715 * IOC page 2. - Readonly
1716 */
1717#pragma pack(1)
1718typedef struct MptConfigurationPageIOC2
1719{
1720 /** Union. */
1721 union
1722 {
1723 /** Byte view. */
1724 uint8_t abPageData[12];
1725 /** Field view. */
1726 struct
1727 {
1728 /** The omnipresent header. */
1729 MptConfigurationPageHeader Header;
1730 /** Flag whether striping is supported. */
1731 unsigned fStripingSupported: 1;
1732 /** Flag whether enhanced mirroring is supported. */
1733 unsigned fEnhancedMirroringSupported: 1;
1734 /** Flag whether mirroring is supported. */
1735 unsigned fMirroringSupported: 1;
1736 /** Reserved. */
1737 unsigned u26Reserved: 26;
1738 /** Flag whether SES is supported. */
1739 unsigned fSESSupported: 1;
1740 /** Flag whether SAF-TE is supported. */
1741 unsigned fSAFTESupported: 1;
1742 /** Flag whether cross channel volumes are supported. */
1743 unsigned fCrossChannelVolumesSupported: 1;
1744 /** Number of active integrated RAID volumes. */
1745 unsigned u8NumActiveVolumes: 8;
1746 /** Maximum number of integrated RAID volumes supported. */
1747 unsigned u8MaxVolumes: 8;
1748 /** Number of active integrated RAID physical disks. */
1749 unsigned u8NumActivePhysDisks: 8;
1750 /** Maximum number of integrated RAID physical disks supported. */
1751 unsigned u8MaxPhysDisks: 8;
1752 /** RAID volumes... - not supported. */
1753 } fields;
1754 } u;
1755} MptConfigurationPageIOC2, *PMptConfigurationPageIOC2;
1756#pragma pack()
1757AssertCompileSize(MptConfigurationPageIOC2, 12);
1758
1759/**
1760 * IOC page 3. - Readonly
1761 */
1762#pragma pack(1)
1763typedef struct MptConfigurationPageIOC3
1764{
1765 /** Union. */
1766 union
1767 {
1768 /** Byte view. */
1769 uint8_t abPageData[8];
1770 /** Field view. */
1771 struct
1772 {
1773 /** The omnipresent header. */
1774 MptConfigurationPageHeader Header;
1775 /** Number of active integrated RAID physical disks. */
1776 uint8_t u8NumPhysDisks;
1777 /** Reserved. */
1778 uint8_t abReserved[3];
1779 } fields;
1780 } u;
1781} MptConfigurationPageIOC3, *PMptConfigurationPageIOC3;
1782#pragma pack()
1783AssertCompileSize(MptConfigurationPageIOC3, 8);
1784
1785/**
1786 * IOC page 4. - Read/Write
1787 */
1788#pragma pack(1)
1789typedef struct MptConfigurationPageIOC4
1790{
1791 /** Union. */
1792 union
1793 {
1794 /** Byte view. */
1795 uint8_t abPageData[8];
1796 /** Field view. */
1797 struct
1798 {
1799 /** The omnipresent header. */
1800 MptConfigurationPageHeader Header;
1801 /** Number of SEP entries in this page. */
1802 uint8_t u8ActiveSEP;
1803 /** Maximum number of SEp entries supported. */
1804 uint8_t u8MaxSEP;
1805 /** Reserved. */
1806 uint16_t u16Reserved;
1807 /** SEP entries... - not supported. */
1808 } fields;
1809 } u;
1810} MptConfigurationPageIOC4, *PMptConfigurationPageIOC4;
1811#pragma pack()
1812AssertCompileSize(MptConfigurationPageIOC4, 8);
1813
1814/**
1815 * IOC page 6. - Read/Write
1816 */
1817#pragma pack(1)
1818typedef struct MptConfigurationPageIOC6
1819{
1820 /** Union. */
1821 union
1822 {
1823 /** Byte view. */
1824 uint8_t abPageData[60];
1825 /** Field view. */
1826 struct
1827 {
1828 /** The omnipresent header. */
1829 MptConfigurationPageHeader Header;
1830 uint32_t u32CapabilitiesFlags;
1831 uint8_t u8MaxDrivesIS;
1832 uint8_t u8MaxDrivesIM;
1833 uint8_t u8MaxDrivesIME;
1834 uint8_t u8Reserved1;
1835 uint8_t u8MinDrivesIS;
1836 uint8_t u8MinDrivesIM;
1837 uint8_t u8MinDrivesIME;
1838 uint8_t u8Reserved2;
1839 uint8_t u8MaxGlobalHotSpares;
1840 uint8_t u8Reserved3;
1841 uint16_t u16Reserved4;
1842 uint32_t u32Reserved5;
1843 uint32_t u32SupportedStripeSizeMapIS;
1844 uint32_t u32SupportedStripeSizeMapIME;
1845 uint32_t u32Reserved6;
1846 uint8_t u8MetadataSize;
1847 uint8_t u8Reserved7;
1848 uint16_t u16Reserved8;
1849 uint16_t u16MaxBadBlockTableEntries;
1850 uint16_t u16Reserved9;
1851 uint16_t u16IRNvsramUsage;
1852 uint16_t u16Reserved10;
1853 uint32_t u32IRNvsramVersion;
1854 uint32_t u32Reserved11;
1855 } fields;
1856 } u;
1857} MptConfigurationPageIOC6, *PMptConfigurationPageIOC6;
1858#pragma pack()
1859AssertCompileSize(MptConfigurationPageIOC6, 60);
1860
1861/**
1862 * BIOS page 1 - Read/write.
1863 */
1864#pragma pack(1)
1865typedef struct MptConfigurationPageBIOS1
1866{
1867 /** Union. */
1868 union
1869 {
1870 /** Byte view. */
1871 uint8_t abPageData[48];
1872 /** Field view. */
1873 struct
1874 {
1875 /** The omnipresent header. */
1876 MptConfigurationPageHeader Header;
1877 /** BIOS options */
1878 uint32_t u32BiosOptions;
1879 /** IOC settings */
1880 uint32_t u32IOCSettings;
1881 /** Reserved */
1882 uint32_t u32Reserved;
1883 /** Device settings */
1884 uint32_t u32DeviceSettings;
1885 /** Number of devices */
1886 uint16_t u16NumberOfDevices;
1887 /** Expander spinup */
1888 uint8_t u8ExpanderSpinup;
1889 /** Reserved */
1890 uint8_t u8Reserved;
1891 /** I/O timeout of block devices without removable media */
1892 uint16_t u16IOTimeoutBlockDevicesNonRM;
1893 /** I/O timeout sequential */
1894 uint16_t u16IOTimeoutSequential;
1895 /** I/O timeout other */
1896 uint16_t u16IOTimeoutOther;
1897 /** I/O timeout of block devices with removable media */
1898 uint16_t u16IOTimeoutBlockDevicesRM;
1899 } fields;
1900 } u;
1901} MptConfigurationPageBIOS1, *PMptConfigurationPageBIOS1;
1902#pragma pack()
1903AssertCompileSize(MptConfigurationPageBIOS1, 48);
1904
1905#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_DISABLE RT_BIT(0)
1906#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_SCAN_FROM_HIGH_TO_LOW RT_BIT(1)
1907#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SAS_SUPPORT RT_BIT(8)
1908#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_FC_SUPPORT RT_BIT(9)
1909#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SPI_SUPPORT RT_BIT(10)
1910
1911#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ALTERNATE_CHS RT_BIT(3)
1912
1913#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_SET(x) ((x) << 4)
1914#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_DISABLED 0x00
1915#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BIOS_ONLY 0x01
1916#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_OS_ONLY 0x02
1917#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BOT 0x03
1918
1919#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_SET(x) ((x) << 6)
1920#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_NO_INT13H 0x00
1921#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_BOOT_MEDIA_INT13H 0x01
1922#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_INT13H 0x02
1923
1924#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_SET(x) ((x & 0xF) << 8)
1925#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_GET(x) ((x >> 8) & 0x0F)
1926#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_SET(x) ((x & 0xF) << 12)
1927#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_GET(x) ((x >> 12) & 0x0F)
1928
1929#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SET(x) (((x) & 0x3) << 16)
1930#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_ENCLOSURE 0x0
1931#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SAS_ADDRESS 0x1
1932
1933#define LSILOGICSCSI_BIOS1_IOCSETTINGS_DIRECT_ATTACH_SPINUP_MODE_ALL RT_BIT(18)
1934#define LSILOGICSCSI_BIOS1_IOCSETTINGS_AUTO_PORT_ENABLE RT_BIT(19)
1935
1936#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_SET(x) (((x) & 0xF) << 20)
1937#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_GET(x) ((x >> 20) & 0x0F)
1938
1939#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_SET(x) (((x) & 0xF) << 24)
1940#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_GET(x) ((x >> 24) & 0x0F)
1941
1942#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS RT_BIT(0)
1943#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_NON_REMOVABLE_DEVICES RT_BIT(1)
1944#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_REMOVABLE_DEVICES RT_BIT(2)
1945#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS2 RT_BIT(3)
1946#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_SMART_POLLING RT_BIT(4)
1947
1948#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_SET(x) ((x) & 0x0F)
1949#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_GET(x) ((x) & 0x0F)
1950#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_SET(x) (((x) & 0x0F) << 4)
1951#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_GET(x) ((x >> 4) & 0x0F)
1952
1953/**
1954 * BIOS page 2 - Read/write.
1955 */
1956#pragma pack(1)
1957typedef struct MptConfigurationPageBIOS2
1958{
1959 /** Union. */
1960 union
1961 {
1962 /** Byte view. */
1963 uint8_t abPageData[384];
1964 /** Field view. */
1965 struct
1966 {
1967 /** The omnipresent header. */
1968 MptConfigurationPageHeader Header;
1969 /** Reserved */
1970 uint32_t au32Reserved[6];
1971 /** Format of the boot device field. */
1972 uint8_t u8BootDeviceForm;
1973 /** Previous format of the boot device field. */
1974 uint8_t u8PrevBootDeviceForm;
1975 /** Reserved */
1976 uint16_t u16Reserved;
1977 /** Boot device fields - dependent on the format */
1978 union
1979 {
1980 /** Device for AdapterNumber:Bus:Target:LUN */
1981 struct
1982 {
1983 /** Target ID */
1984 uint8_t u8TargetID;
1985 /** Bus */
1986 uint8_t u8Bus;
1987 /** Adapter Number */
1988 uint8_t u8AdapterNumber;
1989 /** Reserved */
1990 uint8_t u8Reserved;
1991 /** Reserved */
1992 uint32_t au32Reserved[3];
1993 /** LUN */
1994 uint32_t aLUN[5];
1995 /** Reserved */
1996 uint32_t au32Reserved2[56];
1997 } AdapterNumberBusTargetLUN;
1998 /** Device for PCIAddress:Bus:Target:LUN */
1999 struct
2000 {
2001 /** Target ID */
2002 uint8_t u8TargetID;
2003 /** Bus */
2004 uint8_t u8Bus;
2005 /** Adapter Number */
2006 uint16_t u16PCIAddress;
2007 /** Reserved */
2008 uint32_t au32Reserved[3];
2009 /** LUN */
2010 uint32_t aLUN[5];
2011 /** Reserved */
2012 uint32_t au32Reserved2[56];
2013 } PCIAddressBusTargetLUN;
2014 /** Device for PCISlotNo:Bus:Target:LUN */
2015 struct
2016 {
2017 /** Target ID */
2018 uint8_t u8TargetID;
2019 /** Bus */
2020 uint8_t u8Bus;
2021 /** PCI Slot Number */
2022 uint8_t u16PCISlotNo;
2023 /** Reserved */
2024 uint32_t au32Reserved[3];
2025 /** LUN */
2026 uint32_t aLUN[5];
2027 /** Reserved */
2028 uint32_t au32Reserved2[56];
2029 } PCIAddressBusSlotLUN;
2030 /** Device for FC channel world wide name */
2031 struct
2032 {
2033 /** World wide port name low */
2034 uint32_t u32WorldWidePortNameLow;
2035 /** World wide port name high */
2036 uint32_t u32WorldWidePortNameHigh;
2037 /** Reserved */
2038 uint32_t au32Reserved[3];
2039 /** LUN */
2040 uint32_t aLUN[5];
2041 /** Reserved */
2042 uint32_t au32Reserved2[56];
2043 } FCWorldWideName;
2044 /** Device for FC channel world wide name */
2045 struct
2046 {
2047 /** SAS address */
2048 SASADDRESS SASAddress;
2049 /** Reserved */
2050 uint32_t au32Reserved[3];
2051 /** LUN */
2052 uint32_t aLUN[5];
2053 /** Reserved */
2054 uint32_t au32Reserved2[56];
2055 } SASWorldWideName;
2056 /** Device for Enclosure/Slot */
2057 struct
2058 {
2059 /** Enclosure logical ID */
2060 uint64_t u64EnclosureLogicalID;
2061 /** Reserved */
2062 uint32_t au32Reserved[3];
2063 /** LUN */
2064 uint32_t aLUN[5];
2065 /** Reserved */
2066 uint32_t au32Reserved2[56];
2067 } EnclosureSlot;
2068 } BootDevice;
2069 } fields;
2070 } u;
2071} MptConfigurationPageBIOS2, *PMptConfigurationPageBIOS2;
2072#pragma pack()
2073AssertCompileSize(MptConfigurationPageBIOS2, 384);
2074
2075#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SET(x) ((x) & 0x0F)
2076#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FIRST 0x0
2077#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ADAPTER_BUS_TARGET_LUN 0x1
2078#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCIADDR_BUS_TARGET_LUN 0x2
2079#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCISLOT_BUS_TARGET_LUN 0x3
2080#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FC_WWN 0x4
2081#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SAS_WWN 0x5
2082#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ENCLOSURE_SLOT 0x6
2083
2084/**
2085 * BIOS page 4 - Read/Write (Where is 3? - not defined in the spec)
2086 */
2087#pragma pack(1)
2088typedef struct MptConfigurationPageBIOS4
2089{
2090 /** Union. */
2091 union
2092 {
2093 /** Byte view. */
2094 uint8_t abPageData[12];
2095 /** Field view. */
2096 struct
2097 {
2098 /** The omnipresent header. */
2099 MptConfigurationPageHeader Header;
2100 /** Reassignment Base WWID */
2101 uint64_t u64ReassignmentBaseWWID;
2102 } fields;
2103 } u;
2104} MptConfigurationPageBIOS4, *PMptConfigurationPageBIOS4;
2105#pragma pack()
2106AssertCompileSize(MptConfigurationPageBIOS4, 12);
2107
2108/**
2109 * SCSI-SPI port page 0. - Readonly
2110 */
2111#pragma pack(1)
2112typedef struct MptConfigurationPageSCSISPIPort0
2113{
2114 /** Union. */
2115 union
2116 {
2117 /** Byte view. */
2118 uint8_t abPageData[12];
2119 /** Field view. */
2120 struct
2121 {
2122 /** The omnipresent header. */
2123 MptConfigurationPageHeader Header;
2124 /** Flag whether this port is information unit trnafsers capable. */
2125 unsigned fInformationUnitTransfersCapable: 1;
2126 /** Flag whether the port is DT (Dual Transfer) capable. */
2127 unsigned fDTCapable: 1;
2128 /** Flag whether the port is QAS (Quick Arbitrate and Select) capable. */
2129 unsigned fQASCapable: 1;
2130 /** Reserved. */
2131 unsigned u5Reserved1: 5;
2132 /** Minimum Synchronous transfer period. */
2133 unsigned u8MinimumSynchronousTransferPeriod: 8;
2134 /** Maximum synchronous offset. */
2135 unsigned u8MaximumSynchronousOffset: 8;
2136 /** Reserved. */
2137 unsigned u5Reserved2: 5;
2138 /** Flag whether indicating the width of the bus - 0 narrow and 1 for wide. */
2139 unsigned fWide: 1;
2140 /** Reserved */
2141 unsigned fReserved: 1;
2142 /** Flag whether the port is AIP (Asynchronous Information Protection) capable. */
2143 unsigned fAIPCapable: 1;
2144 /** Signaling Type. */
2145 unsigned u2SignalingType: 2;
2146 /** Reserved. */
2147 unsigned u30Reserved: 30;
2148 } fields;
2149 } u;
2150} MptConfigurationPageSCSISPIPort0, *PMptConfigurationPageSCSISPIPort0;
2151#pragma pack()
2152AssertCompileSize(MptConfigurationPageSCSISPIPort0, 12);
2153
2154/**
2155 * SCSI-SPI port page 1. - Read/Write
2156 */
2157#pragma pack(1)
2158typedef struct MptConfigurationPageSCSISPIPort1
2159{
2160 /** Union. */
2161 union
2162 {
2163 /** Byte view. */
2164 uint8_t abPageData[12];
2165 /** Field view. */
2166 struct
2167 {
2168 /** The omnipresent header. */
2169 MptConfigurationPageHeader Header;
2170 /** The SCSI ID of the port. */
2171 uint8_t u8SCSIID;
2172 /** Reserved. */
2173 uint8_t u8Reserved;
2174 /** Port response IDs Bit mask field. */
2175 uint16_t u16PortResponseIDsBitmask;
2176 /** Value for the on BUS timer. */
2177 uint32_t u32OnBusTimerValue;
2178 } fields;
2179 } u;
2180} MptConfigurationPageSCSISPIPort1, *PMptConfigurationPageSCSISPIPort1;
2181#pragma pack()
2182AssertCompileSize(MptConfigurationPageSCSISPIPort1, 12);
2183
2184/**
2185 * Device settings for one device.
2186 */
2187#pragma pack(1)
2188typedef struct MptDeviceSettings
2189{
2190 /** Timeout for I/O in seconds. */
2191 unsigned u8Timeout: 8;
2192 /** Minimum synchronous factor. */
2193 unsigned u8SyncFactor: 8;
2194 /** Flag whether disconnect is enabled. */
2195 unsigned fDisconnectEnable: 1;
2196 /** Flag whether Scan ID is enabled. */
2197 unsigned fScanIDEnable: 1;
2198 /** Flag whether Scan LUNs is enabled. */
2199 unsigned fScanLUNEnable: 1;
2200 /** Flag whether tagged queuing is enabled. */
2201 unsigned fTaggedQueuingEnabled: 1;
2202 /** Flag whether wide is enabled. */
2203 unsigned fWideDisable: 1;
2204 /** Flag whether this device is bootable. */
2205 unsigned fBootChoice: 1;
2206 /** Reserved. */
2207 unsigned u10Reserved: 10;
2208} MptDeviceSettings, *PMptDeviceSettings;
2209#pragma pack()
2210AssertCompileSize(MptDeviceSettings, 4);
2211
2212/**
2213 * SCSI-SPI port page 2. - Read/Write for the BIOS
2214 */
2215#pragma pack(1)
2216typedef struct MptConfigurationPageSCSISPIPort2
2217{
2218 /** Union. */
2219 union
2220 {
2221 /** Byte view. */
2222 uint8_t abPageData[76];
2223 /** Field view. */
2224 struct
2225 {
2226 /** The omnipresent header. */
2227 MptConfigurationPageHeader Header;
2228 /** Flag indicating the bus scan order. */
2229 unsigned fBusScanOrderHighToLow: 1;
2230 /** Reserved. */
2231 unsigned fReserved: 1;
2232 /** Flag whether SCSI Bus resets are avoided. */
2233 unsigned fAvoidSCSIBusResets: 1;
2234 /** Flag whether alternate CHS is used. */
2235 unsigned fAlternateCHS: 1;
2236 /** Flag whether termination is disabled. */
2237 unsigned fTerminationDisabled: 1;
2238 /** Reserved. */
2239 unsigned u27Reserved: 27;
2240 /** Host SCSI ID. */
2241 unsigned u4HostSCSIID: 4;
2242 /** Initialize HBA. */
2243 unsigned u2InitializeHBA: 2;
2244 /** Removeable media setting. */
2245 unsigned u2RemovableMediaSetting: 2;
2246 /** Spinup delay. */
2247 unsigned u4SpinupDelay: 4;
2248 /** Negotiating settings. */
2249 unsigned u2NegotitatingSettings: 2;
2250 /** Reserved. */
2251 unsigned u18Reserved: 18;
2252 /** Device Settings. */
2253 MptDeviceSettings aDeviceSettings[16];
2254 } fields;
2255 } u;
2256} MptConfigurationPageSCSISPIPort2, *PMptConfigurationPageSCSISPIPort2;
2257#pragma pack()
2258AssertCompileSize(MptConfigurationPageSCSISPIPort2, 76);
2259
2260/**
2261 * SCSI-SPI device page 0. - Readonly
2262 */
2263#pragma pack(1)
2264typedef struct MptConfigurationPageSCSISPIDevice0
2265{
2266 /** Union. */
2267 union
2268 {
2269 /** Byte view. */
2270 uint8_t abPageData[12];
2271 /** Field view. */
2272 struct
2273 {
2274 /** The omnipresent header. */
2275 MptConfigurationPageHeader Header;
2276 /** Negotiated Parameters. */
2277 /** Information Units enabled. */
2278 unsigned fInformationUnitsEnabled: 1;
2279 /** Dual Transfers Enabled. */
2280 unsigned fDTEnabled: 1;
2281 /** QAS enabled. */
2282 unsigned fQASEnabled: 1;
2283 /** Reserved. */
2284 unsigned u5Reserved1: 5;
2285 /** Synchronous Transfer period. */
2286 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2287 /** Synchronous offset. */
2288 unsigned u8NegotiatedSynchronousOffset: 8;
2289 /** Reserved. */
2290 unsigned u5Reserved2: 5;
2291 /** Width - 0 for narrow and 1 for wide. */
2292 unsigned fWide: 1;
2293 /** Reserved. */
2294 unsigned fReserved: 1;
2295 /** AIP enabled. */
2296 unsigned fAIPEnabled: 1;
2297 /** Flag whether negotiation occurred. */
2298 unsigned fNegotationOccured: 1;
2299 /** Flag whether a SDTR message was rejected. */
2300 unsigned fSDTRRejected: 1;
2301 /** Flag whether a WDTR message was rejected. */
2302 unsigned fWDTRRejected: 1;
2303 /** Flag whether a PPR message was rejected. */
2304 unsigned fPPRRejected: 1;
2305 /** Reserved. */
2306 unsigned u28Reserved: 28;
2307 } fields;
2308 } u;
2309} MptConfigurationPageSCSISPIDevice0, *PMptConfigurationPageSCSISPIDevice0;
2310#pragma pack()
2311AssertCompileSize(MptConfigurationPageSCSISPIDevice0, 12);
2312
2313/**
2314 * SCSI-SPI device page 1. - Read/Write
2315 */
2316#pragma pack(1)
2317typedef struct MptConfigurationPageSCSISPIDevice1
2318{
2319 /** Union. */
2320 union
2321 {
2322 /** Byte view. */
2323 uint8_t abPageData[16];
2324 /** Field view. */
2325 struct
2326 {
2327 /** The omnipresent header. */
2328 MptConfigurationPageHeader Header;
2329 /** Requested Parameters. */
2330 /** Information Units enable. */
2331 bool fInformationUnitsEnable: 1;
2332 /** Dual Transfers Enable. */
2333 bool fDTEnable: 1;
2334 /** QAS enable. */
2335 bool fQASEnable: 1;
2336 /** Reserved. */
2337 unsigned u5Reserved1: 5;
2338 /** Synchronous Transfer period. */
2339 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2340 /** Synchronous offset. */
2341 unsigned u8NegotiatedSynchronousOffset: 8;
2342 /** Reserved. */
2343 unsigned u5Reserved2: 5;
2344 /** Width - 0 for narrow and 1 for wide. */
2345 bool fWide: 1;
2346 /** Reserved. */
2347 bool fReserved1: 1;
2348 /** AIP enable. */
2349 bool fAIPEnable: 1;
2350 /** Reserved. */
2351 bool fReserved2: 1;
2352 /** WDTR disallowed. */
2353 bool fWDTRDisallowed: 1;
2354 /** SDTR disallowed. */
2355 bool fSDTRDisallowed: 1;
2356 /** Reserved. */
2357 unsigned u29Reserved: 29;
2358 } fields;
2359 } u;
2360} MptConfigurationPageSCSISPIDevice1, *PMptConfigurationPageSCSISPIDevice1;
2361#pragma pack()
2362AssertCompileSize(MptConfigurationPageSCSISPIDevice1, 16);
2363
2364/**
2365 * SCSI-SPI device page 2. - Read/Write
2366 */
2367#pragma pack(1)
2368typedef struct MptConfigurationPageSCSISPIDevice2
2369{
2370 /** Union. */
2371 union
2372 {
2373 /** Byte view. */
2374 uint8_t abPageData[16];
2375 /** Field view. */
2376 struct
2377 {
2378 /** The omnipresent header. */
2379 MptConfigurationPageHeader Header;
2380 /** Reserved. */
2381 unsigned u4Reserved: 4;
2382 /** ISI enable. */
2383 unsigned fISIEnable: 1;
2384 /** Secondary driver enable. */
2385 unsigned fSecondaryDriverEnable: 1;
2386 /** Reserved. */
2387 unsigned fReserved: 1;
2388 /** Slew reate controler. */
2389 unsigned u3SlewRateControler: 3;
2390 /** Primary drive strength controler. */
2391 unsigned u3PrimaryDriveStrengthControl: 3;
2392 /** Secondary drive strength controler. */
2393 unsigned u3SecondaryDriveStrengthControl: 3;
2394 /** Reserved. */
2395 unsigned u12Reserved: 12;
2396 /** XCLKH_ST. */
2397 unsigned fXCLKH_ST: 1;
2398 /** XCLKS_ST. */
2399 unsigned fXCLKS_ST: 1;
2400 /** XCLKH_DT. */
2401 unsigned fXCLKH_DT: 1;
2402 /** XCLKS_DT. */
2403 unsigned fXCLKS_DT: 1;
2404 /** Parity pipe select. */
2405 unsigned u2ParityPipeSelect: 2;
2406 /** Reserved. */
2407 unsigned u30Reserved: 30;
2408 /** Data bit pipeline select. */
2409 unsigned u32DataPipelineSelect: 32;
2410 } fields;
2411 } u;
2412} MptConfigurationPageSCSISPIDevice2, *PMptConfigurationPageSCSISPIDevice2;
2413#pragma pack()
2414AssertCompileSize(MptConfigurationPageSCSISPIDevice2, 16);
2415
2416/**
2417 * SCSI-SPI device page 3 (Revision G). - Readonly
2418 */
2419#pragma pack(1)
2420typedef struct MptConfigurationPageSCSISPIDevice3
2421{
2422 /** Union. */
2423 union
2424 {
2425 /** Byte view. */
2426 uint8_t abPageData[1];
2427 /** Field view. */
2428 struct
2429 {
2430 /** The omnipresent header. */
2431 MptConfigurationPageHeader Header;
2432 /** Number of times the IOC rejected a message because it doesn't support the operation. */
2433 uint16_t u16MsgRejectCount;
2434 /** Number of times the SCSI bus entered an invalid operation state. */
2435 uint16_t u16PhaseErrorCount;
2436 /** Number of parity errors. */
2437 uint16_t u16ParityCount;
2438 /** Reserved. */
2439 uint16_t u16Reserved;
2440 } fields;
2441 } u;
2442} MptConfigurationPageSCSISPIDevice3, *PMptConfigurationPageSCSISPIDevice3;
2443#pragma pack()
2444AssertCompileSize(MptConfigurationPageSCSISPIDevice3, 12);
2445
2446/**
2447 * PHY entry for the SAS I/O unit page 0
2448 */
2449#pragma pack(1)
2450typedef struct MptConfigurationPageSASIOUnit0PHY
2451{
2452 /** Port number */
2453 uint8_t u8Port;
2454 /** Port flags */
2455 uint8_t u8PortFlags;
2456 /** Phy flags */
2457 uint8_t u8PhyFlags;
2458 /** negotiated link rate */
2459 uint8_t u8NegotiatedLinkRate;
2460 /** Controller phy device info */
2461 uint32_t u32ControllerPhyDeviceInfo;
2462 /** Attached device handle */
2463 uint16_t u16AttachedDevHandle;
2464 /** Controller device handle */
2465 uint16_t u16ControllerDevHandle;
2466 /** Discovery status */
2467 uint32_t u32DiscoveryStatus;
2468} MptConfigurationPageSASIOUnit0PHY, *PMptConfigurationPageSASIOUnit0PHY;
2469#pragma pack()
2470AssertCompileSize(MptConfigurationPageSASIOUnit0PHY, 16);
2471
2472/**
2473 * SAS I/O Unit page 0 - Readonly
2474 */
2475#pragma pack(1)
2476typedef struct MptConfigurationPageSASIOUnit0
2477{
2478 /** Union. */
2479 union
2480 {
2481 /** Byte view - variable. */
2482 uint8_t abPageData[1];
2483 /** Field view. */
2484 struct
2485 {
2486 /** The omnipresent header. */
2487 MptExtendedConfigurationPageHeader ExtHeader;
2488 /** Nvdata version default */
2489 uint16_t u16NvdataVersionDefault;
2490 /** Nvdata version persisent */
2491 uint16_t u16NvdataVersionPersistent;
2492 /** Number of physical ports */
2493 uint8_t u8NumPhys;
2494 /** Reserved */
2495 uint8_t au8Reserved[3];
2496 /** Content for each physical port - variable depending on the amount of ports. */
2497 MptConfigurationPageSASIOUnit0PHY aPHY[1];
2498 } fields;
2499 } u;
2500} MptConfigurationPageSASIOUnit0, *PMptConfigurationPageSASIOUnit0;
2501#pragma pack()
2502AssertCompileSize(MptConfigurationPageSASIOUnit0, 8+2+2+1+3+sizeof(MptConfigurationPageSASIOUnit0PHY));
2503
2504#define LSILOGICSCSI_SASIOUNIT0_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit0) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit0PHY))
2505
2506#define LSILOGICSCSI_SASIOUNIT0_PORT_CONFIGURATION_AUTO RT_BIT(0)
2507#define LSILOGICSCSI_SASIOUNIT0_PORT_TARGET_IOC RT_BIT(2)
2508#define LSILOGICSCSI_SASIOUNIT0_PORT_DISCOVERY_IN_STATUS RT_BIT(3)
2509
2510#define LSILOGICSCSI_SASIOUNIT0_PHY_RX_INVERTED RT_BIT(0)
2511#define LSILOGICSCSI_SASIOUNIT0_PHY_TX_INVERTED RT_BIT(1)
2512#define LSILOGICSCSI_SASIOUNIT0_PHY_DISABLED RT_BIT(2)
2513
2514#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(x) ((x) & 0x0F)
2515#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_GET(x) ((x) & 0x0F)
2516#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_UNKNOWN 0x00
2517#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_DISABLED 0x01
2518#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED 0x02
2519#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SATA_OOB 0x03
2520#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_15GB 0x08
2521#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB 0x09
2522
2523#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(x) ((x) & 0x3)
2524#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO 0x0
2525#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END 0x1
2526#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_EDGE_EXPANDER 0x2
2527#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2528
2529#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA_HOST RT_BIT(3)
2530#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_INITIATOR RT_BIT(4)
2531#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_INITIATOR RT_BIT(5)
2532#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_INITIATOR RT_BIT(6)
2533#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA RT_BIT(7)
2534#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_TARGET RT_BIT(8)
2535#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_TARGET RT_BIT(9)
2536#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET RT_BIT(10)
2537#define LSILOGICSCSI_SASIOUNIT0_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2538#define LSILOGICSCSI_SASIOUNIT0_DEVICE_LSI RT_BIT(12)
2539#define LSILOGICSCSI_SASIOUNIT0_DEVICE_ATAPI_DEVICE RT_BIT(13)
2540#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SEP_DEVICE RT_BIT(14)
2541
2542#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_LOOP RT_BIT(0)
2543#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNADDRESSABLE RT_BIT(1)
2544#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SAME_SAS_ADDR RT_BIT(2)
2545#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXPANDER_ERROR RT_BIT(3)
2546#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_TIMEOUT RT_BIT(4)
2547#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_OOE RT_BIT(5)
2548#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_IDX RT_BIT(6)
2549#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_FUNC_FAILED RT_BIT(7)
2550#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_CRC_ERROR RT_BIT(8)
2551#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SUBTRSCTIVE_LNK RT_BIT(9)
2552#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_TBL_LNK RT_BIT(10)
2553#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNSUPPORTED_DEV RT_BIT(11)
2554#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MAX_SATA_TGTS RT_BIT(12)
2555#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MULT_CTRLS RT_BIT(13)
2556
2557/**
2558 * PHY entry for the SAS I/O unit page 1
2559 */
2560#pragma pack(1)
2561typedef struct MptConfigurationPageSASIOUnit1PHY
2562{
2563 /** Port number */
2564 uint8_t u8Port;
2565 /** Port flags */
2566 uint8_t u8PortFlags;
2567 /** Phy flags */
2568 uint8_t u8PhyFlags;
2569 /** Max link rate */
2570 uint8_t u8MaxMinLinkRate;
2571 /** Controller phy device info */
2572 uint32_t u32ControllerPhyDeviceInfo;
2573 /** Maximum target port connect time */
2574 uint16_t u16MaxTargetPortConnectTime;
2575 /** Reserved */
2576 uint16_t u16Reserved;
2577} MptConfigurationPageSASIOUnit1PHY, *PMptConfigurationPageSASIOUnit1PHY;
2578#pragma pack()
2579AssertCompileSize(MptConfigurationPageSASIOUnit1PHY, 12);
2580
2581/**
2582 * SAS I/O Unit page 1 - Read/Write
2583 */
2584#pragma pack(1)
2585typedef struct MptConfigurationPageSASIOUnit1
2586{
2587 /** Union. */
2588 union
2589 {
2590 /** Byte view - variable. */
2591 uint8_t abPageData[1];
2592 /** Field view. */
2593 struct
2594 {
2595 /** The omnipresent header. */
2596 MptExtendedConfigurationPageHeader ExtHeader;
2597 /** Control flags */
2598 uint16_t u16ControlFlags;
2599 /** maximum number of SATA targets */
2600 uint16_t u16MaxNumSATATargets;
2601 /** additional control flags */
2602 uint16_t u16AdditionalControlFlags;
2603 /** Reserved */
2604 uint16_t u16Reserved;
2605 /** Number of PHYs */
2606 uint8_t u8NumPhys;
2607 /** maximum SATA queue depth */
2608 uint8_t u8SATAMaxQDepth;
2609 /** Delay for reporting missing devices. */
2610 uint8_t u8ReportDeviceMissingDelay;
2611 /** I/O device missing delay */
2612 uint8_t u8IODeviceMissingDelay;
2613 /** Content for each physical port - variable depending on the number of ports */
2614 MptConfigurationPageSASIOUnit1PHY aPHY[1];
2615 } fields;
2616 } u;
2617} MptConfigurationPageSASIOUnit1, *PMptConfigurationPageSASIOUnit1;
2618#pragma pack()
2619AssertCompileSize(MptConfigurationPageSASIOUnit1, 8+12+sizeof(MptConfigurationPageSASIOUnit1PHY));
2620
2621#define LSILOGICSCSI_SASIOUNIT1_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit1) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit1PHY))
2622
2623#define LSILOGICSCSI_SASIOUNIT1_CONTROL_CLEAR_SATA_AFFILIATION RT_BIT(0)
2624#define LSILOGICSCSI_SASIOUNIT1_CONTROL_FIRST_LEVEL_DISCOVERY_ONLY RT_BIT(1)
2625#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SUBTRACTIVE_LNK_ILLEGAL RT_BIT(2)
2626#define LSILOGICSCSI_SASIOUNIT1_CONTROL_IOC_ENABLE_HIGH_PHY RT_BIT(3)
2627#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED RT_BIT(4)
2628#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED RT_BIT(5)
2629#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED RT_BIT(6)
2630#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LBA48_REQUIRED RT_BIT(7)
2631#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_INIT_POSTPONED RT_BIT(8)
2632
2633#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SET(x) (((x) & 0x3) << 9)
2634#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_GET(x) (((x) >> 9) & 0x3)
2635#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS_AND_SATA 0x00
2636#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS 0x01
2637#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SATA 0x02
2638
2639#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_EXP_ADDR RT_BIT(11)
2640#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SETTINGS_PRESERV_REQUIRED RT_BIT(12)
2641#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_15GB RT_BIT(13)
2642#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_30GB RT_BIT(14)
2643#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SAS_SELF_TEST_ENABLED RT_BIT(15)
2644
2645#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_TBL_LNKS_ALLOW RT_BIT(0)
2646#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_NO_AFFIL RT_BIT(1)
2647#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_SELF_AFFIL RT_BIT(2)
2648#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_OTHER_AFFIL RT_BIT(3)
2649#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_PORT_EN_ONLY RT_BIT(4)
2650#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_HIDE_NON_ZERO_PHYS RT_BIT(5)
2651#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_ASYNC_NOTIF RT_BIT(6)
2652#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_MULT_PORTS_ILL_SAME_DOMAIN RT_BIT(7)
2653
2654#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_UNITS_16_SEC RT_BIT(7)
2655#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_SET(x) ((x) & 0x7F)
2656#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_GET(x) ((x) & 0x7F)
2657
2658#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_AUTO RT_BIT(0)
2659#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_IOC1 RT_BIT(2)
2660
2661#define LSILOGICSCSI_SASIOUNIT1_PHY_RX_INVERT RT_BIT(0)
2662#define LSILOGICSCSI_SASIOUNIT1_PHY_TX_INVERT RT_BIT(1)
2663#define LSILOGICSCSI_SASIOUNIT1_PHY_DISABLE RT_BIT(2)
2664
2665#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(x) ((x) & 0x0F)
2666#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_GET(x) ((x) & 0x0F)
2667#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(x) (((x) & 0x0F) << 4)
2668#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_GET(x) ((x >> 4) & 0x0F)
2669#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB 0x8
2670#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB 0x9
2671
2672#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_SET(x) ((x) & 0x3)
2673#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_GET(x) ((x) & 0x3)
2674#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_NO 0x0
2675#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_END 0x1
2676#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_EDGE_EXPANDER 0x2
2677#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2678#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_INITIATOR RT_BIT(4)
2679#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_INITIATOR RT_BIT(5)
2680#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_INITIATOR RT_BIT(6)
2681#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_TARGET RT_BIT(8)
2682#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_TARGET RT_BIT(9)
2683#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_TARGET RT_BIT(10)
2684#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2685#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_LSI RT_BIT(12)
2686#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_ATAPI RT_BIT(13)
2687#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SEP RT_BIT(14)
2688
2689/**
2690 * SAS I/O unit page 2 - Read/Write
2691 */
2692#pragma pack(1)
2693typedef struct MptConfigurationPageSASIOUnit2
2694{
2695 /** Union. */
2696 union
2697 {
2698 /** Byte view - variable. */
2699 uint8_t abPageData[1];
2700 /** Field view. */
2701 struct
2702 {
2703 /** The omnipresent header. */
2704 MptExtendedConfigurationPageHeader ExtHeader;
2705 /** Device numbers per enclosure */
2706 uint8_t u8NumDevsPerEnclosure;
2707 /** Boot device wait time */
2708 uint8_t u8BootDeviceWaitTime;
2709 /** Reserved */
2710 uint16_t u16Reserved;
2711 /** Maximum number of persistent Bus and target ID mappings */
2712 uint16_t u16MaxPersistentIDs;
2713 /** Number of persistent IDs used */
2714 uint16_t u16NumPersistentIDsUsed;
2715 /** Status */
2716 uint8_t u8Status;
2717 /** Flags */
2718 uint8_t u8Flags;
2719 /** Maximum number of physical mapped IDs */
2720 uint16_t u16MaxNumPhysicalMappedIDs;
2721 } fields;
2722 } u;
2723} MptConfigurationPageSASIOUnit2, *PMptConfigurationPageSASIOUnit2;
2724#pragma pack()
2725AssertCompileSize(MptConfigurationPageSASIOUnit2, 20);
2726
2727#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_TBL_FULL RT_BIT(0)
2728#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_DISABLED RT_BIT(1)
2729#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_ENC_DEV_UNMAPPED RT_BIT(2)
2730#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_DEV_LIMIT_EXCEEDED RT_BIT(3)
2731
2732#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_MAP_DISABLE RT_BIT(0)
2733#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_SET(x) ((x & 0x7) << 1)
2734#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_GET(x) ((x >> 1) & 0x7)
2735#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_NO 0x0
2736#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_DIRECT_ATTACHED 0x1
2737#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_ENC 0x2
2738#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_HOST 0x7
2739#define LSILOGICSCSI_SASIOUNIT2_FLAGS_RESERVE_TARGET_ID_ZERO RT_BIT(4)
2740#define LSILOGICSCSI_SASIOUNIT2_FLAGS_START_SLOT_NUMBER_ONE RT_BIT(5)
2741
2742/**
2743 * SAS I/O unit page 3 - Read/Write
2744 */
2745#pragma pack(1)
2746typedef struct MptConfigurationPageSASIOUnit3
2747{
2748 /** Union. */
2749 union
2750 {
2751 /** Byte view - variable. */
2752 uint8_t abPageData[1];
2753 /** Field view. */
2754 struct
2755 {
2756 /** The omnipresent header. */
2757 MptExtendedConfigurationPageHeader ExtHeader;
2758 /** Reserved */
2759 uint32_t u32Reserved;
2760 uint32_t u32MaxInvalidDwordCount;
2761 uint32_t u32InvalidDwordCountTime;
2762 uint32_t u32MaxRunningDisparityErrorCount;
2763 uint32_t u32RunningDisparityErrorTime;
2764 uint32_t u32MaxLossDwordSynchCount;
2765 uint32_t u32LossDwordSynchCountTime;
2766 uint32_t u32MaxPhysResetProblemCount;
2767 uint32_t u32PhyResetProblemTime;
2768 } fields;
2769 } u;
2770} MptConfigurationPageSASIOUnit3, *PMptConfigurationPageSASIOUnit3;
2771#pragma pack()
2772AssertCompileSize(MptConfigurationPageSASIOUnit3, 44);
2773
2774/**
2775 * SAS PHY page 0 - Readonly
2776 */
2777#pragma pack(1)
2778typedef struct MptConfigurationPageSASPHY0
2779{
2780 /** Union. */
2781 union
2782 {
2783 /** Byte view - variable. */
2784 uint8_t abPageData[1];
2785 /** Field view. */
2786 struct
2787 {
2788 /** The omnipresent header. */
2789 MptExtendedConfigurationPageHeader ExtHeader;
2790 /** Owner dev handle. */
2791 uint16_t u16OwnerDevHandle;
2792 /** Reserved */
2793 uint16_t u16Reserved0;
2794 /** SAS address */
2795 SASADDRESS SASAddress;
2796 /** Attached device handle */
2797 uint16_t u16AttachedDevHandle;
2798 /** Attached phy identifier */
2799 uint8_t u8AttachedPhyIdentifier;
2800 /** Reserved */
2801 uint8_t u8Reserved1;
2802 /** Attached device information */
2803 uint32_t u32AttachedDeviceInfo;
2804 /** Programmed link rate */
2805 uint8_t u8ProgrammedLinkRate;
2806 /** Hardware link rate */
2807 uint8_t u8HwLinkRate;
2808 /** Change count */
2809 uint8_t u8ChangeCount;
2810 /** Flags */
2811 uint8_t u8Flags;
2812 /** Phy information */
2813 uint32_t u32PhyInfo;
2814 } fields;
2815 } u;
2816} MptConfigurationPageSASPHY0, *PMptConfigurationPageSASPHY0;
2817#pragma pack()
2818AssertCompileSize(MptConfigurationPageSASPHY0, 36);
2819
2820#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2821#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2822#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO 0x0
2823#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END 0x1
2824#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2825#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2826#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2827#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2828#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2829#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2830#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2831#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2832#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2833#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_LSI RT_BIT(12)
2834#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
2835#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SEP RT_BIT(14)
2836
2837/**
2838 * SAS PHY page 1 - Readonly
2839 */
2840#pragma pack(1)
2841typedef struct MptConfigurationPageSASPHY1
2842{
2843 /** Union. */
2844 union
2845 {
2846 /** Byte view - variable. */
2847 uint8_t abPageData[1];
2848 /** Field view. */
2849 struct
2850 {
2851 /** The omnipresent header. */
2852 MptExtendedConfigurationPageHeader ExtHeader;
2853 /** Reserved */
2854 uint32_t u32Reserved0;
2855 uint32_t u32InvalidDwordCound;
2856 uint32_t u32RunningDisparityErrorCount;
2857 uint32_t u32LossDwordSynchCount;
2858 uint32_t u32PhyResetProblemCount;
2859 } fields;
2860 } u;
2861} MptConfigurationPageSASPHY1, *PMptConfigurationPageSASPHY1;
2862#pragma pack()
2863AssertCompileSize(MptConfigurationPageSASPHY1, 28);
2864
2865/**
2866 * SAS Device page 0 - Readonly
2867 */
2868#pragma pack(1)
2869typedef struct MptConfigurationPageSASDevice0
2870{
2871 /** Union. */
2872 union
2873 {
2874 /** Byte view - variable. */
2875 uint8_t abPageData[1];
2876 /** Field view. */
2877 struct
2878 {
2879 /** The omnipresent header. */
2880 MptExtendedConfigurationPageHeader ExtHeader;
2881 /** Slot number */
2882 uint16_t u16Slot;
2883 /** Enclosure handle. */
2884 uint16_t u16EnclosureHandle;
2885 /** SAS address */
2886 SASADDRESS SASAddress;
2887 /** Parent device handle */
2888 uint16_t u16ParentDevHandle;
2889 /** Phy number */
2890 uint8_t u8PhyNum;
2891 /** Access status */
2892 uint8_t u8AccessStatus;
2893 /** Device handle */
2894 uint16_t u16DevHandle;
2895 /** Target ID */
2896 uint8_t u8TargetID;
2897 /** Bus */
2898 uint8_t u8Bus;
2899 /** Device info */
2900 uint32_t u32DeviceInfo;
2901 /** Flags */
2902 uint16_t u16Flags;
2903 /** Physical port */
2904 uint8_t u8PhysicalPort;
2905 /** Reserved */
2906 uint8_t u8Reserved0;
2907 } fields;
2908 } u;
2909} MptConfigurationPageSASDevice0, *PMptConfigurationPageSASDevice0;
2910#pragma pack()
2911AssertCompileSize(MptConfigurationPageSASDevice0, 36);
2912
2913#define LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS (0x00)
2914
2915#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2916#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2917#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_NO 0x0
2918#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_END 0x1
2919#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2920#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2921#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2922#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2923#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2924#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2925#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2926#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2927#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2928#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_LSI RT_BIT(12)
2929#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
2930#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SEP RT_BIT(14)
2931
2932#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT (RT_BIT(0))
2933#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID (RT_BIT(1))
2934#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT (RT_BIT(2))
2935
2936/**
2937 * SAS Device page 1 - Readonly
2938 */
2939#pragma pack(1)
2940typedef struct MptConfigurationPageSASDevice1
2941{
2942 /** Union. */
2943 union
2944 {
2945 /** Byte view - variable. */
2946 uint8_t abPageData[1];
2947 /** Field view. */
2948 struct
2949 {
2950 /** The omnipresent header. */
2951 MptExtendedConfigurationPageHeader ExtHeader;
2952 /** Reserved */
2953 uint32_t u32Reserved0;
2954 /** SAS address */
2955 SASADDRESS SASAddress;
2956 /** Reserved */
2957 uint32_t u32Reserved;
2958 /** Device handle */
2959 uint16_t u16DevHandle;
2960 /** Target ID */
2961 uint8_t u8TargetID;
2962 /** Bus */
2963 uint8_t u8Bus;
2964 /** Initial REgister device FIS */
2965 uint32_t au32InitialRegDeviceFIS[5];
2966 } fields;
2967 } u;
2968} MptConfigurationPageSASDevice1, *PMptConfigurationPageSASDevice1;
2969#pragma pack()
2970AssertCompileSize(MptConfigurationPageSASDevice1, 48);
2971
2972/**
2973 * SAS Device page 2 - Read/Write persistent
2974 */
2975#pragma pack(1)
2976typedef struct MptConfigurationPageSASDevice2
2977{
2978 /** Union. */
2979 union
2980 {
2981 /** Byte view - variable. */
2982 uint8_t abPageData[1];
2983 /** Field view. */
2984 struct
2985 {
2986 /** The omnipresent header. */
2987 MptExtendedConfigurationPageHeader ExtHeader;
2988 /** Physical identifier */
2989 SASADDRESS SASAddress;
2990 /** Enclosure mapping */
2991 uint32_t u32EnclosureMapping;
2992 } fields;
2993 } u;
2994} MptConfigurationPageSASDevice2, *PMptConfigurationPageSASDevice2;
2995#pragma pack()
2996AssertCompileSize(MptConfigurationPageSASDevice2, 20);
2997
2998/**
2999 * A device entitiy containing all pages.
3000 */
3001typedef struct MptSASDevice
3002{
3003 /** Pointer to the next device if any. */
3004 struct MptSASDevice *pNext;
3005 /** Pointer to the previous device if any. */
3006 struct MptSASDevice *pPrev;
3007
3008 MptConfigurationPageSASDevice0 SASDevicePage0;
3009 MptConfigurationPageSASDevice1 SASDevicePage1;
3010 MptConfigurationPageSASDevice2 SASDevicePage2;
3011} MptSASDevice, *PMptSASDevice;
3012
3013/**
3014 * SAS Expander page 0 - Readonly
3015 */
3016#pragma pack(1)
3017typedef struct MptConfigurationPageSASExpander0
3018{
3019 /** Union. */
3020 union
3021 {
3022 /** Byte view - variable. */
3023 uint8_t abPageData[1];
3024 /** Field view. */
3025 struct
3026 {
3027 /** The omnipresent header. */
3028 MptExtendedConfigurationPageHeader ExtHeader;
3029 /** Physical port */
3030 uint8_t u8PhysicalPort;
3031 /** Reserved */
3032 uint8_t u8Reserved0;
3033 /** Enclosure handle */
3034 uint16_t u16EnclosureHandle;
3035 /** SAS address */
3036 SASADDRESS SASAddress;
3037 /** Discovery status */
3038 uint32_t u32DiscoveryStatus;
3039 /** Device handle. */
3040 uint16_t u16DevHandle;
3041 /** Parent device handle */
3042 uint16_t u16ParentDevHandle;
3043 /** Expander change count */
3044 uint16_t u16ExpanderChangeCount;
3045 /** Expander route indexes */
3046 uint16_t u16ExpanderRouteIndexes;
3047 /** Number of PHys in this expander */
3048 uint8_t u8NumPhys;
3049 /** SAS level */
3050 uint8_t u8SASLevel;
3051 /** Flags */
3052 uint8_t u8Flags;
3053 /** Reserved */
3054 uint8_t u8Reserved1;
3055 } fields;
3056 } u;
3057} MptConfigurationPageSASExpander0, *PMptConfigurationPageSASExpander0;
3058#pragma pack()
3059AssertCompileSize(MptConfigurationPageSASExpander0, 36);
3060
3061/**
3062 * SAS Expander page 1 - Readonly
3063 */
3064#pragma pack(1)
3065typedef struct MptConfigurationPageSASExpander1
3066{
3067 /** Union. */
3068 union
3069 {
3070 /** Byte view - variable. */
3071 uint8_t abPageData[1];
3072 /** Field view. */
3073 struct
3074 {
3075 /** The omnipresent header. */
3076 MptExtendedConfigurationPageHeader ExtHeader;
3077 /** Physical port */
3078 uint8_t u8PhysicalPort;
3079 /** Reserved */
3080 uint8_t u8Reserved0[3];
3081 /** Number of PHYs */
3082 uint8_t u8NumPhys;
3083 /** Number of the Phy the information in this page is for. */
3084 uint8_t u8Phy;
3085 /** Number of routing table entries */
3086 uint16_t u16NumTableEntriesProgrammed;
3087 /** Programmed link rate */
3088 uint8_t u8ProgrammedLinkRate;
3089 /** Hardware link rate */
3090 uint8_t u8HwLinkRate;
3091 /** Attached device handle */
3092 uint16_t u16AttachedDevHandle;
3093 /** Phy information */
3094 uint32_t u32PhyInfo;
3095 /** Attached device information */
3096 uint32_t u32AttachedDeviceInfo;
3097 /** Owner device handle. */
3098 uint16_t u16OwnerDevHandle;
3099 /** Change count */
3100 uint8_t u8ChangeCount;
3101 /** Negotiated link rate */
3102 uint8_t u8NegotiatedLinkRate;
3103 /** Phy identifier */
3104 uint8_t u8PhyIdentifier;
3105 /** Attached phy identifier */
3106 uint8_t u8AttachedPhyIdentifier;
3107 /** Reserved */
3108 uint8_t u8Reserved1;
3109 /** Discovery information */
3110 uint8_t u8DiscoveryInfo;
3111 /** Reserved */
3112 uint32_t u32Reserved;
3113 } fields;
3114 } u;
3115} MptConfigurationPageSASExpander1, *PMptConfigurationPageSASExpander1;
3116#pragma pack()
3117AssertCompileSize(MptConfigurationPageSASExpander1, 40);
3118
3119/**
3120 * Structure of all supported pages for the SCSI SPI controller.
3121 * Used to load the device state from older versions.
3122 */
3123typedef struct MptConfigurationPagesSupported_SSM_V2
3124{
3125 MptConfigurationPageManufacturing0 ManufacturingPage0;
3126 MptConfigurationPageManufacturing1 ManufacturingPage1;
3127 MptConfigurationPageManufacturing2 ManufacturingPage2;
3128 MptConfigurationPageManufacturing3 ManufacturingPage3;
3129 MptConfigurationPageManufacturing4 ManufacturingPage4;
3130 MptConfigurationPageIOUnit0 IOUnitPage0;
3131 MptConfigurationPageIOUnit1 IOUnitPage1;
3132 MptConfigurationPageIOUnit2 IOUnitPage2;
3133 MptConfigurationPageIOUnit3 IOUnitPage3;
3134 MptConfigurationPageIOC0 IOCPage0;
3135 MptConfigurationPageIOC1 IOCPage1;
3136 MptConfigurationPageIOC2 IOCPage2;
3137 MptConfigurationPageIOC3 IOCPage3;
3138 MptConfigurationPageIOC4 IOCPage4;
3139 MptConfigurationPageIOC6 IOCPage6;
3140 struct
3141 {
3142 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3143 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3144 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3145 } aPortPages[1]; /* Currently only one port supported. */
3146 struct
3147 {
3148 struct
3149 {
3150 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3151 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3152 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3153 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3154 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3155 } aBuses[1]; /* Only one bus at the moment. */
3156} MptConfigurationPagesSupported_SSM_V2, *PMptConfigurationPagesSupported_SSM_V2;
3157
3158typedef struct MptConfigurationPagesSpi
3159{
3160 struct
3161 {
3162 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3163 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3164 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3165 } aPortPages[1]; /* Currently only one port supported. */
3166 struct
3167 {
3168 struct
3169 {
3170 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3171 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3172 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3173 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3174 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3175 } aBuses[1]; /* Only one bus at the moment. */
3176} MptConfigurationPagesSpi, *PMptConfigurationPagesSpi;
3177
3178typedef struct MptPHY
3179{
3180 MptConfigurationPageSASPHY0 SASPHYPage0;
3181 MptConfigurationPageSASPHY1 SASPHYPage1;
3182} MptPHY, *PMptPHY;
3183
3184#pragma pack(1)
3185typedef struct MptConfigurationPagesSas
3186{
3187 /** Size of the I/O unit page 0 */
3188 uint32_t cbSASIOUnitPage0;
3189 /** Pointer to the I/O unit page 0 */
3190 PMptConfigurationPageSASIOUnit0 pSASIOUnitPage0;
3191 /** Size of the I/O unit page 1 */
3192 uint32_t cbSASIOUnitPage1;
3193 /** Pointer to the I/O unit page 1 */
3194 PMptConfigurationPageSASIOUnit1 pSASIOUnitPage1;
3195 /** I/O unit page 2 */
3196 MptConfigurationPageSASIOUnit2 SASIOUnitPage2;
3197 /** I/O unit page 3 */
3198 MptConfigurationPageSASIOUnit3 SASIOUnitPage3;
3199
3200 /** Number of PHYs in the array. */
3201 uint32_t cPHYs;
3202 /** Pointer to an array of per PHYS pages. */
3203 R3PTRTYPE(PMptPHY) paPHYs;
3204
3205 /** Number of devices detected. */
3206 uint32_t cDevices;
3207 /** Pointer to the first SAS device. */
3208 R3PTRTYPE(PMptSASDevice) pSASDeviceHead;
3209 /** Pointer to the last SAS device. */
3210 R3PTRTYPE(PMptSASDevice) pSASDeviceTail;
3211} MptConfigurationPagesSas, *PMptConfigurationPagesSas;
3212#pragma pack()
3213
3214/**
3215 * Structure of all supported pages for both controllers.
3216 */
3217typedef struct MptConfigurationPagesSupported
3218{
3219 MptConfigurationPageManufacturing0 ManufacturingPage0;
3220 MptConfigurationPageManufacturing1 ManufacturingPage1;
3221 MptConfigurationPageManufacturing2 ManufacturingPage2;
3222 MptConfigurationPageManufacturing3 ManufacturingPage3;
3223 MptConfigurationPageManufacturing4 ManufacturingPage4;
3224 MptConfigurationPageManufacturing5 ManufacturingPage5;
3225 MptConfigurationPageManufacturing6 ManufacturingPage6;
3226 MptConfigurationPageManufacturing7 ManufacturingPage7;
3227 MptConfigurationPageManufacturing8 ManufacturingPage8;
3228 MptConfigurationPageManufacturing9 ManufacturingPage9;
3229 MptConfigurationPageManufacturing10 ManufacturingPage10;
3230 MptConfigurationPageIOUnit0 IOUnitPage0;
3231 MptConfigurationPageIOUnit1 IOUnitPage1;
3232 MptConfigurationPageIOUnit2 IOUnitPage2;
3233 MptConfigurationPageIOUnit3 IOUnitPage3;
3234 MptConfigurationPageIOUnit4 IOUnitPage4;
3235 MptConfigurationPageIOC0 IOCPage0;
3236 MptConfigurationPageIOC1 IOCPage1;
3237 MptConfigurationPageIOC2 IOCPage2;
3238 MptConfigurationPageIOC3 IOCPage3;
3239 MptConfigurationPageIOC4 IOCPage4;
3240 MptConfigurationPageIOC6 IOCPage6;
3241 /* BIOS page 0 is not described */
3242 MptConfigurationPageBIOS1 BIOSPage1;
3243 MptConfigurationPageBIOS2 BIOSPage2;
3244 /* BIOS page 3 is not described */
3245 MptConfigurationPageBIOS4 BIOSPage4;
3246
3247 /** Controller dependent data. */
3248 union
3249 {
3250 MptConfigurationPagesSpi SpiPages;
3251 MptConfigurationPagesSas SasPages;
3252 } u;
3253} MptConfigurationPagesSupported, *PMptConfigurationPagesSupported;
3254
3255/**
3256 * Initializes a page header.
3257 */
3258#define MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags) \
3259 (pg)->u.fields.Header.u8PageType = flags; \
3260 (pg)->u.fields.Header.u8PageNumber = nr; \
3261 (pg)->u.fields.Header.u8PageLength = sizeof(type) / 4
3262
3263#define MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pg, type, nr, flags) \
3264 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING)
3265
3266#define MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(pg, type, nr, flags) \
3267 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT)
3268
3269#define MPT_CONFIG_PAGE_HEADER_INIT_IOC(pg, type, nr, flags) \
3270 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IOC)
3271
3272#define MPT_CONFIG_PAGE_HEADER_INIT_BIOS(pg, type, nr, flags) \
3273 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_BIOS)
3274
3275/**
3276 * Initializes a extended page header.
3277 */
3278#define MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pg, cb, nr, flags, exttype) \
3279 (pg)->u.fields.ExtHeader.u8PageType = flags | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED; \
3280 (pg)->u.fields.ExtHeader.u8PageNumber = nr; \
3281 (pg)->u.fields.ExtHeader.u8ExtPageType = exttype; \
3282 (pg)->u.fields.ExtHeader.u16ExtPageLength = cb / 4
3283
3284/**
3285 * Possible SG element types.
3286 */
3287enum MPTSGENTRYTYPE
3288{
3289 MPTSGENTRYTYPE_TRANSACTION_CONTEXT = 0x00,
3290 MPTSGENTRYTYPE_SIMPLE = 0x01,
3291 MPTSGENTRYTYPE_CHAIN = 0x03
3292};
3293
3294/**
3295 * Register interface.
3296 */
3297
3298/**
3299 * Defined states that the SCSI controller can have.
3300 */
3301typedef enum LSILOGICSTATE
3302{
3303 /** Reset state. */
3304 LSILOGICSTATE_RESET = 0x00,
3305 /** Ready state. */
3306 LSILOGICSTATE_READY = 0x01,
3307 /** Operational state. */
3308 LSILOGICSTATE_OPERATIONAL = 0x02,
3309 /** Fault state. */
3310 LSILOGICSTATE_FAULT = 0x04,
3311 /** 32bit size hack */
3312 LSILOGICSTATE_32BIT_HACK = 0x7fffffff
3313} LSILOGICSTATE;
3314
3315/**
3316 * Which entity needs to initialize the controller
3317 * to get into the operational state.
3318 */
3319typedef enum LSILOGICWHOINIT
3320{
3321 /** Not initialized. */
3322 LSILOGICWHOINIT_NOT_INITIALIZED = 0x00,
3323 /** System BIOS. */
3324 LSILOGICWHOINIT_SYSTEM_BIOS = 0x01,
3325 /** ROM Bios. */
3326 LSILOGICWHOINIT_ROM_BIOS = 0x02,
3327 /** PCI Peer. */
3328 LSILOGICWHOINIT_PCI_PEER = 0x03,
3329 /** Host driver. */
3330 LSILOGICWHOINIT_HOST_DRIVER = 0x04,
3331 /** Manufacturing. */
3332 LSILOGICWHOINIT_MANUFACTURING = 0x05,
3333 /** 32bit size hack. */
3334 LSILOGICWHOINIT_32BIT_HACK = 0x7fffffff
3335} LSILOGICWHOINIT;
3336
3337
3338/**
3339 * IOC status codes.
3340 */
3341#define LSILOGIC_IOCSTATUS_SUCCESS 0x0000
3342#define LSILOGIC_IOCSTATUS_INVALID_FUNCTION 0x0001
3343#define LSILOGIC_IOCSTATUS_BUSY 0x0002
3344#define LSILOGIC_IOCSTATUS_INVALID_SGL 0x0003
3345#define LSILOGIC_IOCSTATUS_INTERNAL_ERROR 0x0004
3346#define LSILOGIC_IOCSTATUS_RESERVED 0x0005
3347#define LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES 0x0006
3348#define LSILOGIC_IOCSTATUS_INVALID_FIELD 0x0007
3349#define LSILOGIC_IOCSTATUS_INVALID_STATE 0x0008
3350#define LSILOGIC_IOCSTATUS_OP_STATE_NOT_SUPPOTED 0x0009
3351
3352/**
3353 * Size of the I/O and MMIO space.
3354 */
3355#define LSILOGIC_PCI_SPACE_IO_SIZE 256
3356#define LSILOGIC_PCI_SPACE_MEM_SIZE 128 * _1K
3357
3358/**
3359 * Doorbell register - Used to get the status of the controller and
3360 * initialise it.
3361 */
3362#define LSILOGIC_REG_DOORBELL 0x00
3363# define LSILOGIC_REG_DOORBELL_SET_STATE(enmState) (((enmState) & 0x0f) << 28)
3364# define LSILOGIC_REG_DOORBELL_SET_USED(fUsed) (((fUsed) ? 1 : 0) << 27)
3365# define LSILOGIC_REG_DOORBELL_SET_WHOINIT(enmWhoInit) (((enmWhoInit) & 0x07) << 24)
3366# define LSILOGIC_REG_DOORBELL_SET_FAULT_CODE(u16Code) (u16Code)
3367# define LSILOGIC_REG_DOORBELL_GET_FUNCTION(x) (((x) & 0xff000000) >> 24)
3368# define LSILOGIC_REG_DOORBELL_GET_SIZE(x) (((x) & 0x00ff0000) >> 16)
3369
3370/**
3371 * Functions which can be passed through the system doorbell.
3372 */
3373#define LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET 0x40
3374#define LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET 0x41
3375#define LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE 0x42
3376#define LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL 0x43
3377
3378/**
3379 * Write sequence register for the diagnostic register.
3380 */
3381#define LSILOGIC_REG_WRITE_SEQUENCE 0x04
3382
3383/**
3384 * Diagnostic register - used to reset the controller.
3385 */
3386#define LSILOGIC_REG_HOST_DIAGNOSTIC 0x08
3387# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_MEM_ENABLE (RT_BIT(0))
3388# define LSILOGIC_REG_HOST_DIAGNOSTIC_DISABLE_ARM (RT_BIT(1))
3389# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER (RT_BIT(2))
3390# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE (RT_BIT(4))
3391# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_HISTORY (RT_BIT(5))
3392# define LSILOGIC_REG_HOST_DIAGNOSTIC_FLASH_BAD_SIG (RT_BIT(6))
3393# define LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE (RT_BIT(7))
3394# define LSILOGIC_REG_HOST_DIAGNOSTIC_PREVENT_IOC_BOOT (RT_BIT(9))
3395# define LSILOGIC_REG_HOST_DIAGNOSTIC_CLEAR_FLASH_BAD_SIG (RT_BIT(10))
3396
3397#define LSILOGIC_REG_TEST_BASE_ADDRESS 0x0c
3398#define LSILOGIC_REG_DIAG_RW_DATA 0x10
3399#define LSILOGIC_REG_DIAG_RW_ADDRESS 0x14
3400
3401/**
3402 * Interrupt status register.
3403 */
3404#define LSILOGIC_REG_HOST_INTR_STATUS 0x30
3405# define LSILOGIC_REG_HOST_INTR_STATUS_W_MASK (RT_BIT(3))
3406# define LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS (RT_BIT(31))
3407# define LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR (RT_BIT(3))
3408# define LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL (RT_BIT(0))
3409
3410/**
3411 * Interrupt mask register.
3412 */
3413#define LSILOGIC_REG_HOST_INTR_MASK 0x34
3414# define LSILOGIC_REG_HOST_INTR_MASK_W_MASK (RT_BIT(0) | RT_BIT(3) | RT_BIT(8) | RT_BIT(9))
3415# define LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING (RT_BIT(8) | RT_BIT(9))
3416# define LSILOGIC_REG_HOST_INTR_MASK_DOORBELL RT_BIT(0)
3417# define LSILOGIC_REG_HOST_INTR_MASK_REPLY RT_BIT(3)
3418
3419/**
3420 * Queue registers.
3421 */
3422#define LSILOGIC_REG_REQUEST_QUEUE 0x40
3423#define LSILOGIC_REG_REPLY_QUEUE 0x44
3424
3425#endif /* __DEVLSILOGICSCSI_H__ */
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