DevBusLogic.cpp@ 63289

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1	/* $Id: DevBusLogic.cpp 63218 2016-08-09 15:52:35Z vboxsync $ */
2	/** @file
3	* VBox storage devices - BusLogic SCSI host adapter BT-958.
4	*
5	* Based on the Multi-Master Ultra SCSI Systems Technical Reference Manual.
6	*/
7
8	/*
9	* Copyright (C) 2006-2016 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.alldomusa.eu.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_BUSLOGIC
25	#include <VBox/vmm/pdmdev.h>
26	#include <VBox/vmm/pdmstorageifs.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/scsi.h>
29	#include <iprt/asm.h>
30	#include <iprt/assert.h>
31	#include <iprt/string.h>
32	#include <iprt/log.h>
33	#ifdef IN_RING3
34	# include <iprt/alloc.h>
35	# include <iprt/memcache.h>
36	# include <iprt/param.h>
37	# include <iprt/uuid.h>
38	#endif
39
40	#include "VBoxSCSI.h"
41	#include "VBoxDD.h"
42
43
44	/*********************************************************************************************************************************
45	* Defined Constants And Macros *
46	*********************************************************************************************************************************/
47	/** Maximum number of attached devices the adapter can handle. */
48	#define BUSLOGIC_MAX_DEVICES 16
49
50	/** Maximum number of scatter gather elements this device can handle. */
51	#define BUSLOGIC_MAX_SCATTER_GATHER_LIST_SIZE 128
52
53	/** Size of the command buffer. */
54	#define BUSLOGIC_COMMAND_SIZE_MAX 53
55
56	/** Size of the reply buffer. */
57	#define BUSLOGIC_REPLY_SIZE_MAX 64
58
59	/** Custom fixed I/O ports for BIOS controller access.
60	* Note that these should not be in the ISA range (below 400h) to avoid
61	* conflicts with ISA device probing. Addresses in the 300h-340h range should be
62	* especially avoided.
63	*/
64	#define BUSLOGIC_BIOS_IO_PORT 0x430
65
66	/** State saved version. */
67	#define BUSLOGIC_SAVED_STATE_MINOR_VERSION 4
68
69	/** Saved state version before the suspend on error feature was implemented. */
70	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1
71	/** Saved state version before 24-bit mailbox support was implemented. */
72	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX 2
73	/** Saved state version before command buffer size was raised. */
74	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_CMDBUF_RESIZE 3
75
76	/** Command buffer size in old saved states. */
77	#define BUSLOGIC_COMMAND_SIZE_OLD 5
78
79	/** The duration of software-initiated reset (in nano seconds).
80	* Not documented, set to 50 ms. */
81	#define BUSLOGIC_RESET_DURATION_NS UINT64_C(50000000)
82
83
84	/*********************************************************************************************************************************
85	* Structures and Typedefs *
86	*********************************************************************************************************************************/
87	/**
88	* State of a device attached to the buslogic host adapter.
89	*
90	* @implements PDMIBASE
91	* @implements PDMISCSIPORT
92	* @implements PDMILEDPORTS
93	*/
94	typedef struct BUSLOGICDEVICE
95	{
96	/** Pointer to the owning buslogic device instance. - R3 pointer */
97	R3PTRTYPE(struct BUSLOGIC *) pBusLogicR3;
98	/** Pointer to the owning buslogic device instance. - R0 pointer */
99	R0PTRTYPE(struct BUSLOGIC *) pBusLogicR0;
100	/** Pointer to the owning buslogic device instance. - RC pointer */
101	RCPTRTYPE(struct BUSLOGIC *) pBusLogicRC;
102
103	/** Flag whether device is present. */
104	bool fPresent;
105	/** LUN of the device. */
106	RTUINT iLUN;
107
108	#if HC_ARCH_BITS == 64
109	uint32_t Alignment0;
110	#endif
111
112	/** Our base interface. */
113	PDMIBASE IBase;
114	/** SCSI port interface. */
115	PDMISCSIPORT ISCSIPort;
116	/** Led interface. */
117	PDMILEDPORTS ILed;
118	/** Pointer to the attached driver's base interface. */
119	R3PTRTYPE(PPDMIBASE) pDrvBase;
120	/** Pointer to the underlying SCSI connector interface. */
121	R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;
122	/** The status LED state for this device. */
123	PDMLED Led;
124
125	#if HC_ARCH_BITS == 64
126	uint32_t Alignment1;
127	#endif
128
129	/** Number of outstanding tasks on the port. */
130	volatile uint32_t cOutstandingRequests;
131
132	} BUSLOGICDEVICE, *PBUSLOGICDEVICE;
133
134	/**
135	* Commands the BusLogic adapter supports.
136	*/
137	enum BUSLOGICCOMMAND
138	{
139	BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00,
140	BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01,
141	BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02,
142	BUSLOGICCOMMAND_EXECUTE_BIOS_COMMAND = 0x03,
143	BUSLOGICCOMMAND_INQUIRE_BOARD_ID = 0x04,
144	BUSLOGICCOMMAND_ENABLE_OUTGOING_MAILBOX_AVAILABLE_INTERRUPT = 0x05,
145	BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT = 0x06,
146	BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS = 0x07,
147	BUSLOGICCOMMAND_SET_TIME_OFF_BUS = 0x08,
148	BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE = 0x09,
149	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7 = 0x0a,
150	BUSLOGICCOMMAND_INQUIRE_CONFIGURATION = 0x0b,
151	BUSLOGICCOMMAND_ENABLE_TARGET_MODE = 0x0c,
152	BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION = 0x0d,
153	BUSLOGICCOMMAND_WRITE_ADAPTER_LOCAL_RAM = 0x1a,
154	BUSLOGICCOMMAND_READ_ADAPTER_LOCAL_RAM = 0x1b,
155	BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO = 0x1c,
156	BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO = 0x1d,
157	BUSLOGICCOMMAND_ECHO_COMMAND_DATA = 0x1f,
158	BUSLOGICCOMMAND_HOST_ADAPTER_DIAGNOSTIC = 0x20,
159	BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS = 0x21,
160	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15 = 0x23,
161	BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES = 0x24,
162	BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT = 0x25,
163	BUSLOGICCOMMAND_EXT_BIOS_INFO = 0x28,
164	BUSLOGICCOMMAND_UNLOCK_MAILBOX = 0x29,
165	BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX = 0x81,
166	BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND = 0x83,
167	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER = 0x84,
168	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER = 0x85,
169	BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION = 0x86,
170	BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER = 0x8b,
171	BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD = 0x8c,
172	BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION = 0x8d,
173	BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE = 0x8f,
174	BUSLOGICCOMMAND_STORE_HOST_ADAPTER_LOCAL_RAM = 0x90,
175	BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM = 0x91,
176	BUSLOGICCOMMAND_STORE_LOCAL_DATA_IN_EEPROM = 0x92,
177	BUSLOGICCOMMAND_UPLOAD_AUTO_SCSI_CODE = 0x94,
178	BUSLOGICCOMMAND_MODIFY_IO_ADDRESS = 0x95,
179	BUSLOGICCOMMAND_SET_CCB_FORMAT = 0x96,
180	BUSLOGICCOMMAND_WRITE_INQUIRY_BUFFER = 0x9a,
181	BUSLOGICCOMMAND_READ_INQUIRY_BUFFER = 0x9b,
182	BUSLOGICCOMMAND_FLASH_ROM_UPLOAD_DOWNLOAD = 0xa7,
183	BUSLOGICCOMMAND_READ_SCAM_DATA = 0xa8,
184	BUSLOGICCOMMAND_WRITE_SCAM_DATA = 0xa9
185	} BUSLOGICCOMMAND;
186
187	#pragma pack(1)
188	/**
189	* Auto SCSI structure which is located
190	* in host adapter RAM and contains several
191	* configuration parameters.
192	*/
193	typedef struct AutoSCSIRam
194	{
195	uint8_t aInternalSignature[2];
196	uint8_t cbInformation;
197	uint8_t aHostAdaptertype[6];
198	uint8_t uReserved1;
199	bool fFloppyEnabled : 1;
200	bool fFloppySecondary : 1;
201	bool fLevelSensitiveInterrupt : 1;
202	unsigned char uReserved2 : 2;
203	unsigned char uSystemRAMAreForBIOS : 3;
204	unsigned char uDMAChannel : 7;
205	bool fDMAAutoConfiguration : 1;
206	unsigned char uIrqChannel : 7;
207	bool fIrqAutoConfiguration : 1;
208	uint8_t uDMATransferRate;
209	uint8_t uSCSIId;
210	bool fLowByteTerminated : 1;
211	bool fParityCheckingEnabled : 1;
212	bool fHighByteTerminated : 1;
213	bool fNoisyCablingEnvironment : 1;
214	bool fFastSynchronousNeogtiation : 1;
215	bool fBusResetEnabled : 1;
216	bool fReserved3 : 1;
217	bool fActiveNegotiationEnabled : 1;
218	uint8_t uBusOnDelay;
219	uint8_t uBusOffDelay;
220	bool fHostAdapterBIOSEnabled : 1;
221	bool fBIOSRedirectionOfInt19 : 1;
222	bool fExtendedTranslation : 1;
223	bool fMapRemovableAsFixed : 1;
224	bool fReserved4 : 1;
225	bool fBIOSSupportsMoreThan2Drives : 1;
226	bool fBIOSInterruptMode : 1;
227	bool fFlopticalSupport : 1;
228	uint16_t u16DeviceEnabledMask;
229	uint16_t u16WidePermittedMask;
230	uint16_t u16FastPermittedMask;
231	uint16_t u16SynchronousPermittedMask;
232	uint16_t u16DisconnectPermittedMask;
233	uint16_t u16SendStartUnitCommandMask;
234	uint16_t u16IgnoreInBIOSScanMask;
235	unsigned char uPCIInterruptPin : 2;
236	unsigned char uHostAdapterIoPortAddress : 2;
237	bool fStrictRoundRobinMode : 1;
238	bool fVesaBusSpeedGreaterThan33MHz : 1;
239	bool fVesaBurstWrite : 1;
240	bool fVesaBurstRead : 1;
241	uint16_t u16UltraPermittedMask;
242	uint32_t uReserved5;
243	uint8_t uReserved6;
244	uint8_t uAutoSCSIMaximumLUN;
245	bool fReserved7 : 1;
246	bool fSCAMDominant : 1;
247	bool fSCAMenabled : 1;
248	bool fSCAMLevel2 : 1;
249	unsigned char uReserved8 : 4;
250	bool fInt13Extension : 1;
251	bool fReserved9 : 1;
252	bool fCDROMBoot : 1;
253	unsigned char uReserved10 : 5;
254	unsigned char uBootTargetId : 4;
255	unsigned char uBootChannel : 4;
256	bool fForceBusDeviceScanningOrder : 1;
257	unsigned char uReserved11 : 7;
258	uint16_t u16NonTaggedToAlternateLunPermittedMask;
259	uint16_t u16RenegotiateSyncAfterCheckConditionMask;
260	uint8_t aReserved12[10];
261	uint8_t aManufacturingDiagnostic[2];
262	uint16_t u16Checksum;
263	} AutoSCSIRam, *PAutoSCSIRam;
264	AssertCompileSize(AutoSCSIRam, 64);
265	#pragma pack()
266
267	/**
268	* The local Ram.
269	*/
270	typedef union HostAdapterLocalRam
271	{
272	/** Byte view. */
273	uint8_t u8View[256];
274	/** Structured view. */
275	struct
276	{
277	/** Offset 0 - 63 is for BIOS. */
278	uint8_t u8Bios[64];
279	/** Auto SCSI structure. */
280	AutoSCSIRam autoSCSIData;
281	} structured;
282	} HostAdapterLocalRam, *PHostAdapterLocalRam;
283	AssertCompileSize(HostAdapterLocalRam, 256);
284
285
286	/** Ugly 24-bit big-endian addressing. */
287	typedef struct
288	{
289	uint8_t hi;
290	uint8_t mid;
291	uint8_t lo;
292	} Addr24, Len24;
293	AssertCompileSize(Addr24, 3);
294
295	#define ADDR_TO_U32(x) (((x).hi << 16) \| ((x).mid << 8) \| (x).lo)
296	#define LEN_TO_U32 ADDR_TO_U32
297	#define U32_TO_ADDR(a, x) do {(a).hi = (x) >> 16; (a).mid = (x) >> 8; (a).lo = (x);} while(0)
298	#define U32_TO_LEN U32_TO_ADDR
299
300	/** @name Compatible ISA base I/O port addresses. Disabled if zero.
301	* @{ */
302	#define NUM_ISA_BASES 8
303	#define MAX_ISA_BASE (NUM_ISA_BASES - 1)
304	#define ISA_BASE_DISABLED 6
305
306	static uint16_t const g_aISABases[NUM_ISA_BASES] =
307	{
308	0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0, 0
309	};
310	/** @} */
311
312	/** Pointer to a task state structure. */
313	typedef struct BUSLOGICTASKSTATE *PBUSLOGICTASKSTATE;
314
315	/**
316	* Main BusLogic device state.
317	*
318	* @extends PCIDEVICE
319	* @implements PDMILEDPORTS
320	*/
321	typedef struct BUSLOGIC
322	{
323	/** The PCI device structure. */
324	PCIDEVICE dev;
325	/** Pointer to the device instance - HC ptr */
326	PPDMDEVINSR3 pDevInsR3;
327	/** Pointer to the device instance - R0 ptr */
328	PPDMDEVINSR0 pDevInsR0;
329	/** Pointer to the device instance - RC ptr. */
330	PPDMDEVINSRC pDevInsRC;
331
332	/** Whether R0 is enabled. */
333	bool fR0Enabled;
334	/** Whether RC is enabled. */
335	bool fGCEnabled;
336
337	/** Base address of the I/O ports. */
338	RTIOPORT IOPortBase;
339	/** Base address of the memory mapping. */
340	RTGCPHYS MMIOBase;
341	/** Status register - Readonly. */
342	volatile uint8_t regStatus;
343	/** Interrupt register - Readonly. */
344	volatile uint8_t regInterrupt;
345	/** Geometry register - Readonly. */
346	volatile uint8_t regGeometry;
347	/** Pending (delayed) interrupt. */
348	uint8_t uPendingIntr;
349
350	/** Local RAM for the fetch hostadapter local RAM request.
351	* I don't know how big the buffer really is but the maximum
352	* seems to be 256 bytes because the offset and count field in the command request
353	* are only one byte big.
354	*/
355	HostAdapterLocalRam LocalRam;
356
357	/** Command code the guest issued. */
358	uint8_t uOperationCode;
359	/** Buffer for the command parameters the adapter is currently receiving from the guest.
360	* Size of the largest command which is possible.
361	*/
362	uint8_t aCommandBuffer[BUSLOGIC_COMMAND_SIZE_MAX]; /* Size of the biggest request. */
363	/** Current position in the command buffer. */
364	uint8_t iParameter;
365	/** Parameters left until the command is complete. */
366	uint8_t cbCommandParametersLeft;
367
368	/** Whether we are using the RAM or reply buffer. */
369	bool fUseLocalRam;
370	/** Buffer to store reply data from the controller to the guest. */
371	uint8_t aReplyBuffer[BUSLOGIC_REPLY_SIZE_MAX]; /* Size of the biggest reply. */
372	/** Position in the buffer we are reading next. */
373	uint8_t iReply;
374	/** Bytes left until the reply buffer is empty. */
375	uint8_t cbReplyParametersLeft;
376
377	/** Flag whether IRQs are enabled. */
378	bool fIRQEnabled;
379	/** Flag whether the ISA I/O port range is disabled
380	* to prevent the BIOS to access the device. */
381	bool fISAEnabled; /*< @todo unused, to be removed /
382	/** Flag whether 24-bit mailboxes are in use (default is 32-bit). */
383	bool fMbxIs24Bit;
384	/** ISA I/O port base (encoded in FW-compatible format). */
385	uint8_t uISABaseCode;
386
387	/** ISA I/O port base (disabled if zero). */
388	RTIOPORT IOISABase;
389	/** Default ISA I/O port base in FW-compatible format. */
390	uint8_t uDefaultISABaseCode;
391
392	/** Number of mailboxes the guest set up. */
393	uint32_t cMailbox;
394
395	#if HC_ARCH_BITS == 64
396	uint32_t Alignment0;
397	#endif
398
399	/** Time when HBA reset was last initiated. / /< @todo does this need to be saved? /
400	uint64_t u64ResetTime;
401	/** Physical base address of the outgoing mailboxes. */
402	RTGCPHYS GCPhysAddrMailboxOutgoingBase;
403	/** Current outgoing mailbox position. */
404	uint32_t uMailboxOutgoingPositionCurrent;
405	/** Number of mailboxes ready. */
406	volatile uint32_t cMailboxesReady;
407	/** Whether a notification to R3 was sent. */
408	volatile bool fNotificationSent;
409
410	#if HC_ARCH_BITS == 64
411	uint32_t Alignment1;
412	#endif
413
414	/** Physical base address of the incoming mailboxes. */
415	RTGCPHYS GCPhysAddrMailboxIncomingBase;
416	/** Current incoming mailbox position. */
417	uint32_t uMailboxIncomingPositionCurrent;
418
419	/** Whether strict round robin is enabled. */
420	bool fStrictRoundRobinMode;
421	/** Whether the extended LUN CCB format is enabled for 32 possible logical units. */
422	bool fExtendedLunCCBFormat;
423
424	/** Queue to send tasks to R3. - HC ptr */
425	R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
426	/** Queue to send tasks to R3. - HC ptr */
427	R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
428	/** Queue to send tasks to R3. - RC ptr */
429	RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
430
431	uint32_t Alignment2;
432
433	/** Critical section protecting access to the interrupt status register. */
434	PDMCRITSECT CritSectIntr;
435
436	/** Cache for task states. */
437	R3PTRTYPE(RTMEMCACHE) hTaskCache;
438
439	/** Device state for BIOS access. */
440	VBOXSCSI VBoxSCSI;
441
442	/** BusLogic device states. */
443	BUSLOGICDEVICE aDeviceStates[BUSLOGIC_MAX_DEVICES];
444
445	/** The base interface.
446	* @todo use PDMDEVINS::IBase */
447	PDMIBASE IBase;
448	/** Status Port - Leds interface. */
449	PDMILEDPORTS ILeds;
450	/** Partner of ILeds. */
451	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
452
453	#if HC_ARCH_BITS == 64
454	uint32_t Alignment3;
455	#endif
456
457	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
458	* a port is entering the idle state. */
459	bool volatile fSignalIdle;
460	/** Flag whether we have tasks which need to be processed again. */
461	bool volatile fRedo;
462	/** Flag whether the worker thread is sleeping. */
463	volatile bool fWrkThreadSleeping;
464	/** Flag whether a request from the BIOS is pending which the
465	* worker thread needs to process. */
466	volatile bool fBiosReqPending;
467	/** List of tasks which can be redone. */
468	R3PTRTYPE(volatile PBUSLOGICTASKSTATE) pTasksRedoHead;
469
470	/** The support driver session handle. */
471	R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
472	/** Worker thread. */
473	R3PTRTYPE(PPDMTHREAD) pThreadWrk;
474	/** The event semaphore the processing thread waits on. */
475	SUPSEMEVENT hEvtProcess;
476
477	#ifdef LOG_ENABLED
478	# if HC_ARCH_BITS == 64
479	uint32_t Alignment4;
480	# endif
481
482	volatile uint32_t cInMailboxesReady;
483	#endif
484
485	} BUSLOGIC, *PBUSLOGIC;
486
487	/** Register offsets in the I/O port space. */
488	#define BUSLOGIC_REGISTER_CONTROL 0 /*< Writeonly /
489	/** Fields for the control register. */
490	# define BL_CTRL_RSBUS RT_BIT(4) /* Reset SCSI Bus. */
491	# define BL_CTRL_RINT RT_BIT(5) /* Reset Interrupt. */
492	# define BL_CTRL_RSOFT RT_BIT(6) /* Soft Reset. */
493	# define BL_CTRL_RHARD RT_BIT(7) /* Hard Reset. */
494
495	#define BUSLOGIC_REGISTER_STATUS 0 /*< Readonly /
496	/** Fields for the status register. */
497	# define BL_STAT_CMDINV RT_BIT(0) /* Command Invalid. */
498	# define BL_STAT_DIRRDY RT_BIT(2) /* Data In Register Ready. */
499	# define BL_STAT_CPRBSY RT_BIT(3) /* Command/Parameter Out Register Busy. */
500	# define BL_STAT_HARDY RT_BIT(4) /* Host Adapter Ready. */
501	# define BL_STAT_INREQ RT_BIT(5) /* Initialization Required. */
502	# define BL_STAT_DFAIL RT_BIT(6) /* Diagnostic Failure. */
503	# define BL_STAT_DACT RT_BIT(7) /* Diagnistic Active. */
504
505	#define BUSLOGIC_REGISTER_COMMAND 1 /*< Writeonly /
506	#define BUSLOGIC_REGISTER_DATAIN 1 /*< Readonly /
507	#define BUSLOGIC_REGISTER_INTERRUPT 2 /*< Readonly /
508	/** Fields for the interrupt register. */
509	# define BL_INTR_IMBL RT_BIT(0) /* Incoming Mailbox Loaded. */
510	# define BL_INTR_OMBR RT_BIT(1) /* Outgoing Mailbox Available. */
511	# define BL_INTR_CMDC RT_BIT(2) /* Command Complete. */
512	# define BL_INTR_RSTS RT_BIT(3) /* SCSI Bus Reset State. */
513	# define BL_INTR_INTV RT_BIT(7) /* Interrupt Valid. */
514
515	#define BUSLOGIC_REGISTER_GEOMETRY 3 /* Readonly */
516	# define BL_GEOM_XLATEN RT_BIT(7) /* Extended geometry translation enabled. */
517
518	/** Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */
519	typedef struct ReplyInquirePCIHostAdapterInformation
520	{
521	uint8_t IsaIOPort;
522	uint8_t IRQ;
523	unsigned char LowByteTerminated : 1;
524	unsigned char HighByteTerminated : 1;
525	unsigned char uReserved : 2; /* Reserved. */
526	unsigned char JP1 : 1; /* Whatever that means. */
527	unsigned char JP2 : 1; /* Whatever that means. */
528	unsigned char JP3 : 1; /* Whatever that means. */
529	/** Whether the provided info is valid. */
530	unsigned char InformationIsValid: 1;
531	uint8_t uReserved2; /* Reserved. */
532	} ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation;
533	AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4);
534
535	/** Structure for the INQUIRE_CONFIGURATION reply. */
536	typedef struct ReplyInquireConfiguration
537	{
538	unsigned char uReserved1 : 5;
539	bool fDmaChannel5 : 1;
540	bool fDmaChannel6 : 1;
541	bool fDmaChannel7 : 1;
542	bool fIrqChannel9 : 1;
543	bool fIrqChannel10 : 1;
544	bool fIrqChannel11 : 1;
545	bool fIrqChannel12 : 1;
546	unsigned char uReserved2 : 1;
547	bool fIrqChannel14 : 1;
548	bool fIrqChannel15 : 1;
549	unsigned char uReserved3 : 1;
550	unsigned char uHostAdapterId : 4;
551	unsigned char uReserved4 : 4;
552	} ReplyInquireConfiguration, *PReplyInquireConfiguration;
553	AssertCompileSize(ReplyInquireConfiguration, 3);
554
555	/** Structure for the INQUIRE_SETUP_INFORMATION reply. */
556	typedef struct ReplyInquireSetupInformationSynchronousValue
557	{
558	unsigned char uOffset : 4;
559	unsigned char uTransferPeriod : 3;
560	bool fSynchronous : 1;
561	}ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue;
562	AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1);
563
564	typedef struct ReplyInquireSetupInformation
565	{
566	bool fSynchronousInitiationEnabled : 1;
567	bool fParityCheckingEnabled : 1;
568	unsigned char uReserved1 : 6;
569	uint8_t uBusTransferRate;
570	uint8_t uPreemptTimeOnBus;
571	uint8_t uTimeOffBus;
572	uint8_t cMailbox;
573	Addr24 MailboxAddress;
574	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId0To7[8];
575	uint8_t uDisconnectPermittedId0To7;
576	uint8_t uSignature;
577	uint8_t uCharacterD;
578	uint8_t uHostBusType;
579	uint8_t uWideTransferPermittedId0To7;
580	uint8_t uWideTransfersActiveId0To7;
581	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId8To15[8];
582	uint8_t uDisconnectPermittedId8To15;
583	uint8_t uReserved2;
584	uint8_t uWideTransferPermittedId8To15;
585	uint8_t uWideTransfersActiveId8To15;
586	} ReplyInquireSetupInformation, *PReplyInquireSetupInformation;
587	AssertCompileSize(ReplyInquireSetupInformation, 34);
588
589	/** Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */
590	#pragma pack(1)
591	typedef struct ReplyInquireExtendedSetupInformation
592	{
593	uint8_t uBusType;
594	uint8_t uBiosAddress;
595	uint16_t u16ScatterGatherLimit;
596	uint8_t cMailbox;
597	uint32_t uMailboxAddressBase;
598	unsigned char uReserved1 : 2;
599	bool fFastEISA : 1;
600	unsigned char uReserved2 : 3;
601	bool fLevelSensitiveInterrupt : 1;
602	unsigned char uReserved3 : 1;
603	unsigned char aFirmwareRevision[3];
604	bool fHostWideSCSI : 1;
605	bool fHostDifferentialSCSI : 1;
606	bool fHostSupportsSCAM : 1;
607	bool fHostUltraSCSI : 1;
608	bool fHostSmartTermination : 1;
609	unsigned char uReserved4 : 3;
610	} ReplyInquireExtendedSetupInformation, *PReplyInquireExtendedSetupInformation;
611	AssertCompileSize(ReplyInquireExtendedSetupInformation, 14);
612	#pragma pack()
613
614	/** Structure for the INITIALIZE EXTENDED MAILBOX request. */
615	#pragma pack(1)
616	typedef struct RequestInitializeExtendedMailbox
617	{
618	/** Number of mailboxes in guest memory. */
619	uint8_t cMailbox;
620	/** Physical address of the first mailbox. */
621	uint32_t uMailboxBaseAddress;
622	} RequestInitializeExtendedMailbox, *PRequestInitializeExtendedMailbox;
623	AssertCompileSize(RequestInitializeExtendedMailbox, 5);
624	#pragma pack()
625
626	/** Structure for the INITIALIZE MAILBOX request. */
627	typedef struct
628	{
629	/** Number of mailboxes to set up. */
630	uint8_t cMailbox;
631	/** Physical address of the first mailbox. */
632	Addr24 aMailboxBaseAddr;
633	} RequestInitMbx, *PRequestInitMbx;
634	AssertCompileSize(RequestInitMbx, 4);
635
636	/**
637	* Structure of a mailbox in guest memory.
638	* The incoming and outgoing mailbox have the same size
639	* but the incoming one has some more fields defined which
640	* are marked as reserved in the outgoing one.
641	* The last field is also different from the type.
642	* For outgoing mailboxes it is the action and
643	* for incoming ones the completion status code for the task.
644	* We use one structure for both types.
645	*/
646	typedef struct Mailbox32
647	{
648	/** Physical address of the CCB structure in the guest memory. */
649	uint32_t u32PhysAddrCCB;
650	/** Type specific data. */
651	union
652	{
653	/** For outgoing mailboxes. */
654	struct
655	{
656	/** Reserved */
657	uint8_t uReserved[3];
658	/** Action code. */
659	uint8_t uActionCode;
660	} out;
661	/** For incoming mailboxes. */
662	struct
663	{
664	/** The host adapter status after finishing the request. */
665	uint8_t uHostAdapterStatus;
666	/** The status of the device which executed the request after executing it. */
667	uint8_t uTargetDeviceStatus;
668	/** Reserved. */
669	uint8_t uReserved;
670	/** The completion status code of the request. */
671	uint8_t uCompletionCode;
672	} in;
673	} u;
674	} Mailbox32, *PMailbox32;
675	AssertCompileSize(Mailbox32, 8);
676
677	/** Old style 24-bit mailbox entry. */
678	typedef struct Mailbox24
679	{
680	/** Mailbox command (incoming) or state (outgoing). */
681	uint8_t uCmdState;
682	/** Physical address of the CCB structure in the guest memory. */
683	Addr24 aPhysAddrCCB;
684	} Mailbox24, *PMailbox24;
685	AssertCompileSize(Mailbox24, 4);
686
687	/**
688	* Action codes for outgoing mailboxes.
689	*/
690	enum BUSLOGIC_MAILBOX_OUTGOING_ACTION
691	{
692	BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE = 0x00,
693	BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND = 0x01,
694	BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND = 0x02
695	};
696
697	/**
698	* Completion codes for incoming mailboxes.
699	*/
700	enum BUSLOGIC_MAILBOX_INCOMING_COMPLETION
701	{
702	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE = 0x00,
703	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR = 0x01,
704	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED = 0x02,
705	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND = 0x03,
706	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR = 0x04,
707	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_INVALID_CCB = 0x05
708	};
709
710	/**
711	* Host adapter status for incoming mailboxes.
712	*/
713	enum BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS
714	{
715	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED = 0x00,
716	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED = 0x0a,
717	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG = 0x0b,
718	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_UNDERUN = 0x0c,
719	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT = 0x11,
720	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_OVERRUN = 0x12,
721	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNEXPECTED_BUS_FREE = 0x13,
722	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_BUS_PHASE_REQUESTED = 0x14,
723	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_OUTGOING_MAILBOX_ACTION_CODE = 0x15,
724	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_OPERATION_CODE = 0x16,
725	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CCB_HAS_INVALID_LUN = 0x17,
726	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER = 0x1a,
727	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_AUTO_REQUEST_SENSE_FAILED = 0x1b,
728	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TAGGED_QUEUING_MESSAGE_REJECTED = 0x1c,
729	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNSUPPORTED_MESSAGE_RECEIVED = 0x1d,
730	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_FAILED = 0x20,
731	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_FAILED_RESPONSE_TO_ATN = 0x21,
732	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_RST = 0x22,
733	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_OTHER_DEVICE_ASSERTED_RST = 0x23,
734	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_DEVICE_RECONNECTED_IMPROPERLY = 0x24,
735	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_BUS_DEVICE_RESET = 0x25,
736	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED = 0x26,
737	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_SOFTWARE_ERROR = 0x27,
738	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_TIMEOUT_ERROR = 0x30,
739	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_PARITY_ERROR_DETECTED = 0x34
740	};
741
742	/**
743	* Device status codes for incoming mailboxes.
744	*/
745	enum BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS
746	{
747	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD = 0x00,
748	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION = 0x02,
749	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_DEVICE_BUSY = 0x08
750	};
751
752	/**
753	* Opcode types for CCB.
754	*/
755	enum BUSLOGIC_CCB_OPCODE
756	{
757	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB = 0x00,
758	BUSLOGIC_CCB_OPCODE_TARGET_CCB = 0x01,
759	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER = 0x02,
760	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH = 0x03,
761	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER = 0x04,
762	BUSLOGIC_CCB_OPCODE_BUS_DEVICE_RESET = 0x81
763	};
764
765	/**
766	* Data transfer direction.
767	*/
768	enum BUSLOGIC_CCB_DIRECTION
769	{
770	BUSLOGIC_CCB_DIRECTION_UNKNOWN = 0x00,
771	BUSLOGIC_CCB_DIRECTION_IN = 0x01,
772	BUSLOGIC_CCB_DIRECTION_OUT = 0x02,
773	BUSLOGIC_CCB_DIRECTION_NO_DATA = 0x03
774	};
775
776	/**
777	* The command control block for a SCSI request.
778	*/
779	typedef struct CCB32
780	{
781	/** Opcode. */
782	uint8_t uOpcode;
783	/** Reserved */
784	unsigned char uReserved1 : 3;
785	/** Data direction for the request. */
786	unsigned char uDataDirection : 2;
787	/** Whether the request is tag queued. */
788	bool fTagQueued : 1;
789	/** Queue tag mode. */
790	unsigned char uQueueTag : 2;
791	/** Length of the SCSI CDB. */
792	uint8_t cbCDB;
793	/** Sense data length. */
794	uint8_t cbSenseData;
795	/** Data length. */
796	uint32_t cbData;
797	/** Data pointer.
798	* This points to the data region or a scatter gather list based on the opcode.
799	*/
800	uint32_t u32PhysAddrData;
801	/** Reserved. */
802	uint8_t uReserved2[2];
803	/** Host adapter status. */
804	uint8_t uHostAdapterStatus;
805	/** Device adapter status. */
806	uint8_t uDeviceStatus;
807	/** The device the request is sent to. */
808	uint8_t uTargetId;
809	/*The LUN in the device. /
810	unsigned char uLogicalUnit : 5;
811	/** Legacy tag. */
812	bool fLegacyTagEnable : 1;
813	/** Legacy queue tag. */
814	unsigned char uLegacyQueueTag : 2;
815	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
816	uint8_t abCDB[12];
817	/** Reserved. */
818	uint8_t uReserved3[6];
819	/** Sense data pointer. */
820	uint32_t u32PhysAddrSenseData;
821	} CCB32, *PCCB32;
822	AssertCompileSize(CCB32, 40);
823
824
825	/**
826	* The 24-bit command control block.
827	*/
828	typedef struct CCB24
829	{
830	/** Opcode. */
831	uint8_t uOpcode;
832	/** The LUN in the device. */
833	unsigned char uLogicalUnit : 3;
834	/** Data direction for the request. */
835	unsigned char uDataDirection : 2;
836	/** The target device ID. */
837	unsigned char uTargetId : 3;
838	/** Length of the SCSI CDB. */
839	uint8_t cbCDB;
840	/** Sense data length. */
841	uint8_t cbSenseData;
842	/** Data length. */
843	Len24 acbData;
844	/** Data pointer.
845	* This points to the data region or a scatter gather list based on the opc
846	*/
847	Addr24 aPhysAddrData;
848	/** Pointer to next CCB for linked commands. */
849	Addr24 aPhysAddrLink;
850	/** Command linking identifier. */
851	uint8_t uLinkId;
852	/** Host adapter status. */
853	uint8_t uHostAdapterStatus;
854	/** Device adapter status. */
855	uint8_t uDeviceStatus;
856	/** Two unused bytes. */
857	uint8_t aReserved[2];
858	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
859	uint8_t abCDB[12];
860	} CCB24, *PCCB24;
861	AssertCompileSize(CCB24, 30);
862
863	/**
864	* The common 24-bit/32-bit command control block. The 32-bit CCB is laid out
865	* such that many fields are in the same location as in the older 24-bit CCB.
866	*/
867	typedef struct CCBC
868	{
869	/** Opcode. */
870	uint8_t uOpcode;
871	/** The LUN in the device. */
872	unsigned char uPad1 : 3;
873	/** Data direction for the request. */
874	unsigned char uDataDirection : 2;
875	/** The target device ID. */
876	unsigned char uPad2 : 3;
877	/** Length of the SCSI CDB. */
878	uint8_t cbCDB;
879	/** Sense data length. */
880	uint8_t cbSenseData;
881	uint8_t aPad1[10];
882	/** Host adapter status. */
883	uint8_t uHostAdapterStatus;
884	/** Device adapter status. */
885	uint8_t uDeviceStatus;
886	uint8_t aPad2[2];
887	/** The SCSI CDB (up to 12 bytes). */
888	uint8_t abCDB[12];
889	} CCBC, *PCCBC;
890	AssertCompileSize(CCBC, 30);
891
892	/* Make sure that the 24-bit/32-bit/common CCB offsets match. */
893	AssertCompileMemberOffset(CCBC, cbCDB, 2);
894	AssertCompileMemberOffset(CCB24, cbCDB, 2);
895	AssertCompileMemberOffset(CCB32, cbCDB, 2);
896	AssertCompileMemberOffset(CCBC, uHostAdapterStatus, 14);
897	AssertCompileMemberOffset(CCB24, uHostAdapterStatus, 14);
898	AssertCompileMemberOffset(CCB32, uHostAdapterStatus, 14);
899	AssertCompileMemberOffset(CCBC, abCDB, 18);
900	AssertCompileMemberOffset(CCB24, abCDB, 18);
901	AssertCompileMemberOffset(CCB32, abCDB, 18);
902
903	/** A union of all CCB types (24-bit/32-bit/common). */
904	typedef union CCBU
905	{
906	CCB32 n; /*< New 32-bit CCB. /
907	CCB24 o; /*< Old 24-bit CCB. /
908	CCBC c; /*< Common CCB subset. /
909	} CCBU, *PCCBU;
910
911	/** 32-bit scatter-gather list entry. */
912	typedef struct SGE32
913	{
914	uint32_t cbSegment;
915	uint32_t u32PhysAddrSegmentBase;
916	} SGE32, *PSGE32;
917	AssertCompileSize(SGE32, 8);
918
919	/** 24-bit scatter-gather list entry. */
920	typedef struct SGE24
921	{
922	Len24 acbSegment;
923	Addr24 aPhysAddrSegmentBase;
924	} SGE24, *PSGE24;
925	AssertCompileSize(SGE24, 6);
926
927	/**
928	* The structure for the "Execute SCSI Command" command.
929	*/
930	typedef struct ESCMD
931	{
932	/** Data length. */
933	uint32_t cbData;
934	/** Data pointer. */
935	uint32_t u32PhysAddrData;
936	/** The device the request is sent to. */
937	uint8_t uTargetId;
938	/** The LUN in the device. */
939	uint8_t uLogicalUnit;
940	/** Reserved */
941	unsigned char uReserved1 : 3;
942	/** Data direction for the request. */
943	unsigned char uDataDirection : 2;
944	/** Reserved */
945	unsigned char uReserved2 : 3;
946	/** Length of the SCSI CDB. */
947	uint8_t cbCDB;
948	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
949	uint8_t abCDB[12];
950	} ESCMD, *PESCMD;
951	AssertCompileSize(ESCMD, 24);
952
953	/**
954	* Task state for a CCB request.
955	*/
956	typedef struct BUSLOGICTASKSTATE
957	{
958	/** Next in the redo list. */
959	PBUSLOGICTASKSTATE pRedoNext;
960	/** Device this task is assigned to. */
961	R3PTRTYPE(PBUSLOGICDEVICE) pTargetDeviceR3;
962	/** The command control block from the guest. */
963	CCBU CommandControlBlockGuest;
964	/** Mailbox read from guest memory. */
965	Mailbox32 MailboxGuest;
966	/** The SCSI request we pass to the underlying SCSI engine. */
967	PDMSCSIREQUEST PDMScsiRequest;
968	/** Data buffer segment */
969	RTSGSEG DataSeg;
970	/** Pointer to the R3 sense buffer. */
971	uint8_t *pbSenseBuffer;
972	/** Flag whether this is a request from the BIOS. */
973	bool fBIOS;
974	/** 24-bit request flag (default is 32-bit). */
975	bool fIs24Bit;
976	/** S/G entry size (depends on the above flag). */
977	uint8_t cbSGEntry;
978	} BUSLOGICTASKSTATE;
979
980	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
981
982	#define PDMIBASE_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, IBase)) )
983	#define PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ISCSIPort)) )
984	#define PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ILed)) )
985	#define PDMIBASE_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, IBase)) )
986	#define PDMILEDPORTS_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, ILeds)) )
987
988
989	/*********************************************************************************************************************************
990	* Internal Functions *
991	*********************************************************************************************************************************/
992	#ifdef IN_RING3
993	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode);
994	#endif
995
996
997	/**
998	* Assert IRQ line of the BusLogic adapter.
999	*
1000	* @returns nothing.
1001	* @param pBusLogic Pointer to the BusLogic device instance.
1002	* @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled
1003	* @param uFlag Type of interrupt being generated.
1004	*/
1005	static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType)
1006	{
1007	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1008
1009	/* The CMDC interrupt has priority over IMBL and OMBR. */
1010	if (uIrqType & (BL_INTR_IMBL \| BL_INTR_OMBR))
1011	{
1012	if (!(pBusLogic->regInterrupt & BL_INTR_CMDC))
1013	pBusLogic->regInterrupt \|= uIrqType; /* Report now. */
1014	else
1015	pBusLogic->uPendingIntr \|= uIrqType; /* Report later. */
1016	}
1017	else if (uIrqType & BL_INTR_CMDC)
1018	{
1019	AssertMsg(pBusLogic->regInterrupt == 0 \|\| pBusLogic->regInterrupt == (BL_INTR_INTV \| BL_INTR_CMDC),
1020	("regInterrupt=%02X\n", pBusLogic->regInterrupt));
1021	pBusLogic->regInterrupt \|= uIrqType;
1022	}
1023	else
1024	AssertMsgFailed(("Invalid interrupt state!\n"));
1025
1026	pBusLogic->regInterrupt \|= BL_INTR_INTV;
1027	if (pBusLogic->fIRQEnabled && !fSuppressIrq)
1028	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1);
1029	}
1030
1031	/**
1032	* Deasserts the interrupt line of the BusLogic adapter.
1033	*
1034	* @returns nothing
1035	* @param pBuslogic Pointer to the BusLogic device instance.
1036	*/
1037	static void buslogicClearInterrupt(PBUSLOGIC pBusLogic)
1038	{
1039	LogFlowFunc(("pBusLogic=%#p, clearing %#02x (pending %#02x)\n",
1040	pBusLogic, pBusLogic->regInterrupt, pBusLogic->uPendingIntr));
1041	pBusLogic->regInterrupt = 0;
1042	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0);
1043	/* If there's another pending interrupt, report it now. */
1044	if (pBusLogic->uPendingIntr)
1045	{
1046	buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr);
1047	pBusLogic->uPendingIntr = 0;
1048	}
1049	}
1050
1051	#if defined(IN_RING3)
1052
1053	/**
1054	* Advances the mailbox pointer to the next slot.
1055	*/
1056	DECLINLINE(void) buslogicR3OutgoingMailboxAdvance(PBUSLOGIC pBusLogic)
1057	{
1058	pBusLogic->uMailboxOutgoingPositionCurrent = (pBusLogic->uMailboxOutgoingPositionCurrent + 1) % pBusLogic->cMailbox;
1059	}
1060
1061	/**
1062	* Initialize local RAM of host adapter with default values.
1063	*
1064	* @returns nothing.
1065	* @param pBusLogic.
1066	*/
1067	static void buslogicR3InitializeLocalRam(PBUSLOGIC pBusLogic)
1068	{
1069	/*
1070	* These values are mostly from what I think is right
1071	* looking at the dmesg output from a Linux guest inside
1072	* a VMware server VM.
1073	*
1074	* So they don't have to be right :)
1075	*/
1076	memset(pBusLogic->LocalRam.u8View, 0, sizeof(HostAdapterLocalRam));
1077	pBusLogic->LocalRam.structured.autoSCSIData.fLevelSensitiveInterrupt = true;
1078	pBusLogic->LocalRam.structured.autoSCSIData.fParityCheckingEnabled = true;
1079	pBusLogic->LocalRam.structured.autoSCSIData.fExtendedTranslation = true; /* Same as in geometry register. */
1080	pBusLogic->LocalRam.structured.autoSCSIData.u16DeviceEnabledMask = UINT16_MAX; /* All enabled. Maybe mask out non present devices? */
1081	pBusLogic->LocalRam.structured.autoSCSIData.u16WidePermittedMask = UINT16_MAX;
1082	pBusLogic->LocalRam.structured.autoSCSIData.u16FastPermittedMask = UINT16_MAX;
1083	pBusLogic->LocalRam.structured.autoSCSIData.u16SynchronousPermittedMask = UINT16_MAX;
1084	pBusLogic->LocalRam.structured.autoSCSIData.u16DisconnectPermittedMask = UINT16_MAX;
1085	pBusLogic->LocalRam.structured.autoSCSIData.fStrictRoundRobinMode = pBusLogic->fStrictRoundRobinMode;
1086	pBusLogic->LocalRam.structured.autoSCSIData.u16UltraPermittedMask = UINT16_MAX;
1087	/** @todo calculate checksum? */
1088	}
1089
1090	/**
1091	* Do a hardware reset of the buslogic adapter.
1092	*
1093	* @returns VBox status code.
1094	* @param pBusLogic Pointer to the BusLogic device instance.
1095	* @param fResetIO Flag determining whether ISA I/O should be reset.
1096	*/
1097	static int buslogicR3HwReset(PBUSLOGIC pBusLogic, bool fResetIO)
1098	{
1099	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1100
1101	/* Reset registers to default values. */
1102	pBusLogic->regStatus = BL_STAT_HARDY \| BL_STAT_INREQ;
1103	pBusLogic->regGeometry = BL_GEOM_XLATEN;
1104	pBusLogic->uOperationCode = 0xff; /* No command executing. */
1105	pBusLogic->iParameter = 0;
1106	pBusLogic->cbCommandParametersLeft = 0;
1107	pBusLogic->fIRQEnabled = true;
1108	pBusLogic->fStrictRoundRobinMode = false;
1109	pBusLogic->fExtendedLunCCBFormat = false;
1110	pBusLogic->uMailboxOutgoingPositionCurrent = 0;
1111	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1112
1113	/* Clear any active/pending interrupts. */
1114	pBusLogic->uPendingIntr = 0;
1115	buslogicClearInterrupt(pBusLogic);
1116
1117	/* Guest-initiated HBA reset does not affect ISA port I/O. */
1118	if (fResetIO)
1119	{
1120	buslogicR3RegisterISARange(pBusLogic, pBusLogic->uDefaultISABaseCode);
1121	}
1122	buslogicR3InitializeLocalRam(pBusLogic);
1123	vboxscsiInitialize(&pBusLogic->VBoxSCSI);
1124
1125	return VINF_SUCCESS;
1126	}
1127
1128	#endif /* IN_RING3 */
1129
1130	/**
1131	* Resets the command state machine for the next command and notifies the guest.
1132	*
1133	* @returns nothing.
1134	* @param pBusLogic Pointer to the BusLogic device instance
1135	* @param fSuppressIrq Flag to suppress IRQ generation regardless of current state
1136	*/
1137	static void buslogicCommandComplete(PBUSLOGIC pBusLogic, bool fSuppressIrq)
1138	{
1139	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1140
1141	pBusLogic->fUseLocalRam = false;
1142	pBusLogic->regStatus \|= BL_STAT_HARDY;
1143	pBusLogic->iReply = 0;
1144
1145	/* Modify I/O address does not generate an interrupt. */
1146	if (pBusLogic->uOperationCode != BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND)
1147	{
1148	/* Notify that the command is complete. */
1149	pBusLogic->regStatus &= ~BL_STAT_DIRRDY;
1150	buslogicSetInterrupt(pBusLogic, fSuppressIrq, BL_INTR_CMDC);
1151	}
1152
1153	pBusLogic->uOperationCode = 0xff;
1154	pBusLogic->iParameter = 0;
1155	}
1156
1157	#if defined(IN_RING3)
1158
1159	/**
1160	* Initiates a hard reset which was issued from the guest.
1161	*
1162	* @returns nothing
1163	* @param pBusLogic Pointer to the BusLogic device instance.
1164	* @param fHardReset Flag initiating a hard (vs. soft) reset.
1165	*/
1166	static void buslogicR3InitiateReset(PBUSLOGIC pBusLogic, bool fHardReset)
1167	{
1168	LogFlowFunc(("pBusLogic=%#p fHardReset=%d\n", pBusLogic, fHardReset));
1169
1170	buslogicR3HwReset(pBusLogic, false);
1171
1172	if (fHardReset)
1173	{
1174	/* Set the diagnostic active bit in the status register and clear the ready state. */
1175	pBusLogic->regStatus \|= BL_STAT_DACT;
1176	pBusLogic->regStatus &= ~BL_STAT_HARDY;
1177
1178	/* Remember when the guest initiated a reset (after we're done resetting). */
1179	pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
1180	}
1181	}
1182
1183	/**
1184	* Send a mailbox with set status codes to the guest.
1185	*
1186	* @returns nothing.
1187	* @param pBusLogic Pointer to the BusLogic device instance.
1188	* @param pTaskState Pointer to the task state with the mailbox to send.
1189	* @param uHostAdapterStatus The host adapter status code to set.
1190	* @param uDeviceStatus The target device status to set.
1191	* @param uMailboxCompletionCode Completion status code to set in the mailbox.
1192	*/
1193	static void buslogicR3SendIncomingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState,
1194	uint8_t uHostAdapterStatus, uint8_t uDeviceStatus,
1195	uint8_t uMailboxCompletionCode)
1196	{
1197	pTaskState->MailboxGuest.u.in.uHostAdapterStatus = uHostAdapterStatus;
1198	pTaskState->MailboxGuest.u.in.uTargetDeviceStatus = uDeviceStatus;
1199	pTaskState->MailboxGuest.u.in.uCompletionCode = uMailboxCompletionCode;
1200
1201	int rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_SUCCESS);
1202	AssertRC(rc);
1203
1204	RTGCPHYS GCPhysAddrMailboxIncoming = pBusLogic->GCPhysAddrMailboxIncomingBase
1205	+ ( pBusLogic->uMailboxIncomingPositionCurrent
1206	* (pTaskState->fIs24Bit ? sizeof(Mailbox24) : sizeof(Mailbox32)) );
1207
1208	if (uMailboxCompletionCode != BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND)
1209	{
1210	RTGCPHYS GCPhysAddrCCB = pTaskState->MailboxGuest.u32PhysAddrCCB;
1211	LogFlowFunc(("Completing CCB %RGp hstat=%u, dstat=%u, outgoing mailbox at %RGp\n", GCPhysAddrCCB,
1212	uHostAdapterStatus, uDeviceStatus, GCPhysAddrMailboxIncoming));
1213
1214	/* Update CCB. */
1215	pTaskState->CommandControlBlockGuest.c.uHostAdapterStatus = uHostAdapterStatus;
1216	pTaskState->CommandControlBlockGuest.c.uDeviceStatus = uDeviceStatus;
1217	/* Rewrite CCB up to the CDB; perhaps more than necessary. */
1218	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
1219	&pTaskState->CommandControlBlockGuest, RT_OFFSETOF(CCBC, abCDB));
1220	}
1221
1222	# ifdef RT_STRICT
1223	uint8_t uCode;
1224	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
1225	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming + uCodeOffs, &uCode, sizeof(uCode));
1226	Assert(uCode == BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE);
1227	# endif
1228
1229	/* Update mailbox. */
1230	if (pTaskState->fIs24Bit)
1231	{
1232	Mailbox24 Mbx24;
1233
1234	Mbx24.uCmdState = pTaskState->MailboxGuest.u.in.uCompletionCode;
1235	U32_TO_ADDR(Mbx24.aPhysAddrCCB, pTaskState->MailboxGuest.u32PhysAddrCCB);
1236	Log(("24-bit mailbox: completion code=%u, CCB at %RGp\n", Mbx24.uCmdState, (RTGCPHYS)ADDR_TO_U32(Mbx24.aPhysAddrCCB)));
1237	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &Mbx24, sizeof(Mailbox24));
1238	}
1239	else
1240	{
1241	Log(("32-bit mailbox: completion code=%u, CCB at %RGp\n", pTaskState->MailboxGuest.u.in.uCompletionCode, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
1242	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming,
1243	&pTaskState->MailboxGuest, sizeof(Mailbox32));
1244	}
1245
1246	/* Advance to next mailbox position. */
1247	pBusLogic->uMailboxIncomingPositionCurrent++;
1248	if (pBusLogic->uMailboxIncomingPositionCurrent >= pBusLogic->cMailbox)
1249	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1250
1251	# ifdef LOG_ENABLED
1252	ASMAtomicIncU32(&pBusLogic->cInMailboxesReady);
1253	# endif
1254
1255	buslogicSetInterrupt(pBusLogic, false, BL_INTR_IMBL);
1256
1257	PDMCritSectLeave(&pBusLogic->CritSectIntr);
1258	}
1259
1260	# ifdef LOG_ENABLED
1261
1262	/**
1263	* Dumps the content of a mailbox for debugging purposes.
1264	*
1265	* @return nothing
1266	* @param pMailbox The mailbox to dump.
1267	* @param fOutgoing true if dumping the outgoing state.
1268	* false if dumping the incoming state.
1269	*/
1270	static void buslogicR3DumpMailboxInfo(PMailbox32 pMailbox, bool fOutgoing)
1271	{
1272	Log(("%s: Dump for %s mailbox:\n", __FUNCTION__, fOutgoing ? "outgoing" : "incoming"));
1273	Log(("%s: u32PhysAddrCCB=%#x\n", __FUNCTION__, pMailbox->u32PhysAddrCCB));
1274	if (fOutgoing)
1275	{
1276	Log(("%s: uActionCode=%u\n", __FUNCTION__, pMailbox->u.out.uActionCode));
1277	}
1278	else
1279	{
1280	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pMailbox->u.in.uHostAdapterStatus));
1281	Log(("%s: uTargetDeviceStatus=%u\n", __FUNCTION__, pMailbox->u.in.uTargetDeviceStatus));
1282	Log(("%s: uCompletionCode=%u\n", __FUNCTION__, pMailbox->u.in.uCompletionCode));
1283	}
1284	}
1285
1286	/**
1287	* Dumps the content of a command control block for debugging purposes.
1288	*
1289	* @returns nothing.
1290	* @param pCCB Pointer to the command control block to dump.
1291	* @param fIs24BitCCB Flag to determine CCB format.
1292	*/
1293	static void buslogicR3DumpCCBInfo(PCCBU pCCB, bool fIs24BitCCB)
1294	{
1295	Log(("%s: Dump for %s Command Control Block:\n", __FUNCTION__, fIs24BitCCB ? "24-bit" : "32-bit"));
1296	Log(("%s: uOpCode=%#x\n", __FUNCTION__, pCCB->c.uOpcode));
1297	Log(("%s: uDataDirection=%u\n", __FUNCTION__, pCCB->c.uDataDirection));
1298	Log(("%s: cbCDB=%u\n", __FUNCTION__, pCCB->c.cbCDB));
1299	Log(("%s: cbSenseData=%u\n", __FUNCTION__, pCCB->c.cbSenseData));
1300	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pCCB->c.uHostAdapterStatus));
1301	Log(("%s: uDeviceStatus=%u\n", __FUNCTION__, pCCB->c.uDeviceStatus));
1302	if (fIs24BitCCB)
1303	{
1304	Log(("%s: cbData=%u\n", __FUNCTION__, LEN_TO_U32(pCCB->o.acbData)));
1305	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, ADDR_TO_U32(pCCB->o.aPhysAddrData)));
1306	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->o.uTargetId));
1307	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->o.uLogicalUnit));
1308	}
1309	else
1310	{
1311	Log(("%s: cbData=%u\n", __FUNCTION__, pCCB->n.cbData));
1312	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrData));
1313	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->n.uTargetId));
1314	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->n.uLogicalUnit));
1315	Log(("%s: fTagQueued=%d\n", __FUNCTION__, pCCB->n.fTagQueued));
1316	Log(("%s: uQueueTag=%u\n", __FUNCTION__, pCCB->n.uQueueTag));
1317	Log(("%s: fLegacyTagEnable=%u\n", __FUNCTION__, pCCB->n.fLegacyTagEnable));
1318	Log(("%s: uLegacyQueueTag=%u\n", __FUNCTION__, pCCB->n.uLegacyQueueTag));
1319	Log(("%s: PhysAddrSenseData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrSenseData));
1320	}
1321	Log(("%s: uCDB[0]=%#x\n", __FUNCTION__, pCCB->c.abCDB[0]));
1322	for (int i = 1; i < pCCB->c.cbCDB; i++)
1323	Log(("%s: uCDB[%d]=%u\n", __FUNCTION__, i, pCCB->c.abCDB[i]));
1324	}
1325
1326	# endif /* LOG_ENABLED */
1327
1328	/**
1329	* Allocate data buffer.
1330	*
1331	* @param pTaskState Pointer to the task state.
1332	* @param GCSGList Guest physical address of S/G list.
1333	* @param cEntries Number of list entries to read.
1334	* @param pSGEList Pointer to 32-bit S/G list storage.
1335	*/
1336	static void buslogicR3ReadSGEntries(PBUSLOGICTASKSTATE pTaskState, RTGCPHYS GCSGList, uint32_t cEntries, SGE32 *pSGEList)
1337	{
1338	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1339	SGE24 aSGE24[32];
1340	Assert(cEntries <= RT_ELEMENTS(aSGE24));
1341
1342	/* Read the S/G entries. Convert 24-bit entries to 32-bit format. */
1343	if (pTaskState->fIs24Bit)
1344	{
1345	Log2(("Converting %u 24-bit S/G entries to 32-bit\n", cEntries));
1346	PDMDevHlpPhysRead(pDevIns, GCSGList, &aSGE24, cEntries * sizeof(SGE24));
1347	for (uint32_t i = 0; i < cEntries; ++i)
1348	{
1349	pSGEList[i].cbSegment = LEN_TO_U32(aSGE24[i].acbSegment);
1350	pSGEList[i].u32PhysAddrSegmentBase = ADDR_TO_U32(aSGE24[i].aPhysAddrSegmentBase);
1351	}
1352	}
1353	else
1354	PDMDevHlpPhysRead(pDevIns, GCSGList, pSGEList, cEntries * sizeof(SGE32));
1355	}
1356
1357	/**
1358	* Allocate data buffer.
1359	*
1360	* @returns VBox status code.
1361	* @param pTaskState Pointer to the task state.
1362	*/
1363	static int buslogicR3DataBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1364	{
1365	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1366	uint32_t cbDataCCB;
1367	uint32_t u32PhysAddrCCB;
1368
1369	/* Extract the data length and physical address from the CCB. */
1370	if (pTaskState->fIs24Bit)
1371	{
1372	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1373	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1374	}
1375	else
1376	{
1377	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1378	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1379	}
1380
1381	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection != BUSLOGIC_CCB_DIRECTION_NO_DATA)
1382	&& cbDataCCB)
1383	{
1384	/** @todo Check following assumption and what residual means. */
1385	/*
1386	* The BusLogic adapter can handle two different data buffer formats.
1387	* The first one is that the data pointer entry in the CCB points to
1388	* the buffer directly. In second mode the data pointer points to a
1389	* scatter gather list which describes the buffer.
1390	*/
1391	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1392	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1393	{
1394	uint32_t cScatterGatherGCRead;
1395	uint32_t iScatterGatherEntry;
1396	SGE32 aScatterGatherReadGC[32]; /* A buffer for scatter gather list entries read from guest memory. */
1397	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1398	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1399	size_t cbDataToTransfer = 0;
1400
1401	/* Count number of bytes to transfer. */
1402	do
1403	{
1404	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1405	? cScatterGatherGCLeft
1406	: RT_ELEMENTS(aScatterGatherReadGC);
1407	cScatterGatherGCLeft -= cScatterGatherGCRead;
1408
1409	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1410
1411	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1412	{
1413	RTGCPHYS GCPhysAddrDataBase;
1414
1415	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1416
1417	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1418	cbDataToTransfer += aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1419
1420	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n",
1421	__FUNCTION__, GCPhysAddrDataBase,
1422	aScatterGatherReadGC[iScatterGatherEntry].cbSegment));
1423	}
1424
1425	/* Set address to the next entries to read. */
1426	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1427	} while (cScatterGatherGCLeft > 0);
1428
1429	Log(("%s: cbDataToTransfer=%d\n", __FUNCTION__, cbDataToTransfer));
1430
1431	/* Allocate buffer */
1432	pTaskState->DataSeg.cbSeg = cbDataToTransfer;
1433	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1434	if (!pTaskState->DataSeg.pvSeg)
1435	return VERR_NO_MEMORY;
1436
1437	/* Copy the data if needed */
1438	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
1439	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN))
1440	{
1441	cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1442	GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1443	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1444
1445	do
1446	{
1447	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1448	? cScatterGatherGCLeft
1449	: RT_ELEMENTS(aScatterGatherReadGC);
1450	cScatterGatherGCLeft -= cScatterGatherGCRead;
1451
1452	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1453
1454	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1455	{
1456	RTGCPHYS GCPhysAddrDataBase;
1457
1458	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1459
1460	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1461	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1462
1463	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1464
1465	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1466	pbData += cbDataToTransfer;
1467	}
1468
1469	/* Set address to the next entries to read. */
1470	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1471	} while (cScatterGatherGCLeft > 0);
1472	}
1473
1474	}
1475	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1476	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1477	{
1478	/* The buffer is not scattered. */
1479	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1480
1481	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1482
1483	pTaskState->DataSeg.cbSeg = cbDataCCB;
1484	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1485	if (!pTaskState->DataSeg.pvSeg)
1486	return VERR_NO_MEMORY;
1487
1488	Log(("Non scattered buffer:\n"));
1489	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1490	Log(("cbData=%u\n", cbDataCCB));
1491	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1492
1493	/* Copy the data into the buffer. */
1494	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1495	}
1496	}
1497
1498	return VINF_SUCCESS;
1499	}
1500
1501	/**
1502	* Free allocated resources used for the scatter gather list.
1503	*
1504	* @returns nothing.
1505	* @param pTaskState Pointer to the task state.
1506	*/
1507	static void buslogicR3DataBufferFree(PBUSLOGICTASKSTATE pTaskState)
1508	{
1509	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1510	uint32_t cbDataCCB;
1511	uint32_t u32PhysAddrCCB;
1512
1513	/* Extract the data length and physical address from the CCB. */
1514	if (pTaskState->fIs24Bit)
1515	{
1516	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1517	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1518	}
1519	else
1520	{
1521	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1522	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1523	}
1524
1525	#if 1
1526	/* Hack for NT 10/91: A CCB describes a 2K buffer, but TEST UNIT READY is executed. This command
1527	* returns no data, hence the buffer must be left alone!
1528	*/
1529	if (pTaskState->CommandControlBlockGuest.c.abCDB[0] == 0)
1530	cbDataCCB = 0;
1531	#endif
1532
1533	LogFlowFunc(("pTaskState=%#p cbDataCCB=%u direction=%u cbSeg=%u\n", pTaskState, cbDataCCB,
1534	pTaskState->CommandControlBlockGuest.c.uDataDirection, pTaskState->DataSeg.cbSeg));
1535
1536	if ( (cbDataCCB > 0)
1537	&& ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
1538	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)))
1539	{
1540	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1541	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1542	{
1543	uint32_t cScatterGatherGCRead;
1544	uint32_t iScatterGatherEntry;
1545	SGE32 aScatterGatherReadGC[32]; /* Number of scatter gather list entries read from guest memory. */
1546	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1547	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1548	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1549
1550	do
1551	{
1552	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1553	? cScatterGatherGCLeft
1554	: RT_ELEMENTS(aScatterGatherReadGC);
1555	cScatterGatherGCLeft -= cScatterGatherGCRead;
1556
1557	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1558
1559	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1560	{
1561	RTGCPHYS GCPhysAddrDataBase;
1562	size_t cbDataToTransfer;
1563
1564	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1565
1566	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1567	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1568
1569	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1570
1571	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1572	pbData += cbDataToTransfer;
1573	}
1574
1575	/* Set address to the next entries to read. */
1576	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1577	} while (cScatterGatherGCLeft > 0);
1578
1579	}
1580	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1581	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1582	{
1583	/* The buffer is not scattered. */
1584	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1585
1586	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1587
1588	Log(("Non-scattered buffer:\n"));
1589	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1590	Log(("cbData=%u\n", cbDataCCB));
1591	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1592
1593	/* Copy the data into the guest memory. */
1594	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1595	}
1596
1597	}
1598	/* Update residual data length. */
1599	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1600	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1601	{
1602	uint32_t cbResidual;
1603
1604	/** @todo we need to get the actual transfer length from the VSCSI layer?! */
1605	cbResidual = 0; //LEN_TO_U32(pTaskState->CCBGuest.acbData) - ???;
1606	if (pTaskState->fIs24Bit)
1607	U32_TO_LEN(pTaskState->CommandControlBlockGuest.o.acbData, cbResidual);
1608	else
1609	pTaskState->CommandControlBlockGuest.n.cbData = cbResidual;
1610	}
1611
1612	RTMemFree(pTaskState->DataSeg.pvSeg);
1613	pTaskState->DataSeg.pvSeg = NULL;
1614	pTaskState->DataSeg.cbSeg = 0;
1615	}
1616
1617	/** Convert sense buffer length taking into account shortcut values. */
1618	static uint32_t buslogicR3ConvertSenseBufferLength(uint32_t cbSense)
1619	{
1620	/* Convert special sense buffer length values. */
1621	if (cbSense == 0)
1622	cbSense = 14; /* 0 means standard 14-byte buffer. */
1623	else if (cbSense == 1)
1624	cbSense = 0; /* 1 means no sense data. */
1625	else if (cbSense < 8)
1626	AssertMsgFailed(("Reserved cbSense value of %d used!\n", cbSense));
1627
1628	return cbSense;
1629	}
1630
1631	/**
1632	* Free the sense buffer.
1633	*
1634	* @returns nothing.
1635	* @param pTaskState Pointer to the task state.
1636	* @param fCopy If sense data should be copied to guest memory.
1637	*/
1638	static void buslogicR3SenseBufferFree(PBUSLOGICTASKSTATE pTaskState, bool fCopy)
1639	{
1640	uint32_t cbSenseBuffer;
1641
1642	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1643
1644	/* Copy the sense buffer into guest memory if requested. */
1645	if (fCopy && cbSenseBuffer)
1646	{
1647	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1648	RTGCPHYS GCPhysAddrSenseBuffer;
1649
1650	/* With 32-bit CCBs, the (optional) sense buffer physical address is provided separately.
1651	* On the other hand, with 24-bit CCBs, the sense buffer is simply located at the end of
1652	* the CCB, right after the variable-length CDB.
1653	*/
1654	if (pTaskState->fIs24Bit)
1655	{
1656	GCPhysAddrSenseBuffer = pTaskState->MailboxGuest.u32PhysAddrCCB;
1657	GCPhysAddrSenseBuffer += pTaskState->CommandControlBlockGuest.c.cbCDB + RT_OFFSETOF(CCB24, abCDB);
1658	}
1659	else
1660	GCPhysAddrSenseBuffer = pTaskState->CommandControlBlockGuest.n.u32PhysAddrSenseData;
1661
1662	Log3(("%s: sense buffer: %.*Rhxs\n", __FUNCTION__, cbSenseBuffer, pTaskState->pbSenseBuffer));
1663	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrSenseBuffer, pTaskState->pbSenseBuffer, cbSenseBuffer);
1664	}
1665
1666	RTMemFree(pTaskState->pbSenseBuffer);
1667	pTaskState->pbSenseBuffer = NULL;
1668	}
1669
1670	/**
1671	* Alloc the sense buffer.
1672	*
1673	* @returns VBox status code.
1674	* @param pTaskState Pointer to the task state.
1675	* @note Current assumption is that the sense buffer is not scattered and does not cross a page boundary.
1676	*/
1677	static int buslogicR3SenseBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1678	{
1679	pTaskState->pbSenseBuffer = NULL;
1680
1681	uint32_t cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1682	if (cbSenseBuffer)
1683	{
1684	pTaskState->pbSenseBuffer = (uint8_t *)RTMemAllocZ(cbSenseBuffer);
1685	if (!pTaskState->pbSenseBuffer)
1686	return VERR_NO_MEMORY;
1687	}
1688
1689	return VINF_SUCCESS;
1690	}
1691
1692	#endif /* IN_RING3 */
1693
1694	/**
1695	* Parses the command buffer and executes it.
1696	*
1697	* @returns VBox status code.
1698	* @param pBusLogic Pointer to the BusLogic device instance.
1699	*/
1700	static int buslogicProcessCommand(PBUSLOGIC pBusLogic)
1701	{
1702	int rc = VINF_SUCCESS;
1703	bool fSuppressIrq = false;
1704
1705	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1706	AssertMsg(pBusLogic->uOperationCode != 0xff, ("There is no command to execute\n"));
1707
1708	switch (pBusLogic->uOperationCode)
1709	{
1710	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
1711	/* Valid command, no reply. */
1712	pBusLogic->cbReplyParametersLeft = 0;
1713	break;
1714	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
1715	{
1716	PReplyInquirePCIHostAdapterInformation pReply = (PReplyInquirePCIHostAdapterInformation)pBusLogic->aReplyBuffer;
1717	memset(pReply, 0, sizeof(ReplyInquirePCIHostAdapterInformation));
1718
1719	/* It seems VMware does not provide valid information here too, lets do the same :) */
1720	pReply->InformationIsValid = 0;
1721	pReply->IsaIOPort = pBusLogic->uISABaseCode;
1722	pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev);
1723	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation);
1724	break;
1725	}
1726	case BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT:
1727	{
1728	/* no-op */
1729	pBusLogic->cbReplyParametersLeft = 0;
1730	break;
1731	}
1732	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
1733	{
1734	/* Modify the ISA-compatible I/O port base. Note that this technically
1735	* violates the PCI spec, as this address is not reported through PCI.
1736	* However, it is required for compatibility with old drivers.
1737	*/
1738	#ifdef IN_RING3
1739	Log(("ISA I/O for PCI (code %x)\n", pBusLogic->aCommandBuffer[0]));
1740	buslogicR3RegisterISARange(pBusLogic, pBusLogic->aCommandBuffer[0]);
1741	pBusLogic->cbReplyParametersLeft = 0;
1742	fSuppressIrq = true;
1743	break;
1744	#else
1745	AssertMsgFailed(("Must never get here!\n"));
1746	#endif
1747	}
1748	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
1749	{
1750	/* The special option byte is important: If it is '0' or 'B', Windows NT drivers
1751	* for Adaptec AHA-154x may claim the adapter. The BusLogic drivers will claim
1752	* the adapter only when the byte is not '0' or 'B'.
1753	*/
1754	pBusLogic->aReplyBuffer[0] = 'A'; /* Firmware option bytes */
1755	pBusLogic->aReplyBuffer[1] = 'A'; /* Special option byte */
1756
1757	/* We report version 5.07B. This reply will provide the first two digits. */
1758	pBusLogic->aReplyBuffer[2] = '5'; /* Major version 5 */
1759	pBusLogic->aReplyBuffer[3] = '0'; /* Minor version 0 */
1760	pBusLogic->cbReplyParametersLeft = 4; /* Reply is 4 bytes long */
1761	break;
1762	}
1763	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
1764	{
1765	pBusLogic->aReplyBuffer[0] = '7';
1766	pBusLogic->cbReplyParametersLeft = 1;
1767	break;
1768	}
1769	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
1770	{
1771	pBusLogic->aReplyBuffer[0] = 'B';
1772	pBusLogic->cbReplyParametersLeft = 1;
1773	break;
1774	}
1775	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
1776	/* The parameter list length is determined by the first byte of the command buffer. */
1777	if (pBusLogic->iParameter == 1)
1778	{
1779	/* First pass - set the number of following parameter bytes. */
1780	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0];
1781	Log(("Set HA options: %u bytes follow\n", pBusLogic->cbCommandParametersLeft));
1782	}
1783	else
1784	{
1785	/* Second pass - process received data. */
1786	Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1787	/* We ignore the data - it only concerns the SCSI hardware protocol. */
1788	}
1789	pBusLogic->cbReplyParametersLeft = 0;
1790	break;
1791
1792	case BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND:
1793	/* The parameter list length is at least 12 bytes; the 12th byte determines
1794	* the number of additional CDB bytes that will follow.
1795	*/
1796	if (pBusLogic->iParameter == 12)
1797	{
1798	/* First pass - set the number of following CDB bytes. */
1799	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[11];
1800	Log(("Execute SCSI cmd: %u more bytes follow\n", pBusLogic->cbCommandParametersLeft));
1801	}
1802	else
1803	{
1804	PESCMD pCmd;
1805
1806	/* Second pass - process received data. */
1807	Log(("Execute SCSI cmd: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1808
1809	pCmd = (PESCMD)pBusLogic->aCommandBuffer;
1810	Log(("Addr %08X, cbData %08X, cbCDB=%u\n", pCmd->u32PhysAddrData, pCmd->cbData, pCmd->cbCDB));
1811	}
1812	// This is currently a dummy - just fails every command.
1813	pBusLogic->cbReplyParametersLeft = 4;
1814	pBusLogic->aReplyBuffer[0] = pBusLogic->aReplyBuffer[1] = 0;
1815	pBusLogic->aReplyBuffer[2] = 0x11; /* HBA status (timeout). */
1816	pBusLogic->aReplyBuffer[3] = 0; /* Device status. */
1817	break;
1818
1819	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
1820	{
1821	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1822	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1823	memset(pBusLogic->aReplyBuffer, 0, pBusLogic->cbReplyParametersLeft);
1824	const char aModelName[] = "958D "; /* Trailing \0 is fine, that's the filler anyway. */
1825	int cCharsToTransfer = pBusLogic->cbReplyParametersLeft <= sizeof(aModelName)
1826	? pBusLogic->cbReplyParametersLeft
1827	: sizeof(aModelName);
1828
1829	for (int i = 0; i < cCharsToTransfer; i++)
1830	pBusLogic->aReplyBuffer[i] = aModelName[i];
1831
1832	break;
1833	}
1834	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
1835	{
1836	uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev);
1837
1838	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration);
1839	PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer;
1840	memset(pReply, 0, sizeof(ReplyInquireConfiguration));
1841
1842	pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */
1843	pReply->fDmaChannel6 = 1; /* DMA channel 6 is a good default. */
1844	/* The PCI IRQ is not necessarily representable in this structure.
1845	* If that is the case, the guest likely won't function correctly,
1846	* therefore we log a warning.
1847	*/
1848	switch (uPciIrq)
1849	{
1850	case 9: pReply->fIrqChannel9 = 1; break;
1851	case 10: pReply->fIrqChannel10 = 1; break;
1852	case 11: pReply->fIrqChannel11 = 1; break;
1853	case 12: pReply->fIrqChannel12 = 1; break;
1854	case 14: pReply->fIrqChannel14 = 1; break;
1855	case 15: pReply->fIrqChannel15 = 1; break;
1856	default:
1857	LogRel(("Warning: PCI IRQ %d cannot be represented as ISA!\n", uPciIrq));
1858	break;
1859	}
1860	break;
1861	}
1862	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
1863	{
1864	/* Some Adaptec AHA-154x drivers (e.g. OS/2) execute this command and expect
1865	* it to fail. If it succeeds, the drivers refuse to load. However, some newer
1866	* Adaptec 154x models supposedly support it too??
1867	*/
1868
1869	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1870	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1871	PReplyInquireExtendedSetupInformation pReply = (PReplyInquireExtendedSetupInformation)pBusLogic->aReplyBuffer;
1872	memset(pReply, 0, sizeof(ReplyInquireExtendedSetupInformation));
1873
1874	/** @todo should this reflect the RAM contents (AutoSCSIRam)? */
1875	pReply->uBusType = 'E'; /* EISA style */
1876	pReply->u16ScatterGatherLimit = 8192;
1877	pReply->cMailbox = pBusLogic->cMailbox;
1878	pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase;
1879	pReply->fLevelSensitiveInterrupt = true;
1880	pReply->fHostWideSCSI = true;
1881	pReply->fHostUltraSCSI = true;
1882	memcpy(pReply->aFirmwareRevision, "07B", sizeof(pReply->aFirmwareRevision));
1883
1884	break;
1885	}
1886	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
1887	{
1888	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1889	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1890	PReplyInquireSetupInformation pReply = (PReplyInquireSetupInformation)pBusLogic->aReplyBuffer;
1891	memset(pReply, 0, sizeof(ReplyInquireSetupInformation));
1892	pReply->fSynchronousInitiationEnabled = true;
1893	pReply->fParityCheckingEnabled = true;
1894	pReply->cMailbox = pBusLogic->cMailbox;
1895	U32_TO_ADDR(pReply->MailboxAddress, pBusLogic->GCPhysAddrMailboxOutgoingBase);
1896	pReply->uSignature = 'B';
1897	/* The 'D' signature prevents Adaptec's OS/2 drivers from getting too
1898	* friendly with BusLogic hardware and upsetting the HBA state.
1899	*/
1900	pReply->uCharacterD = 'D'; /* BusLogic model. */
1901	pReply->uHostBusType = 'F'; /* PCI bus. */
1902	break;
1903	}
1904	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
1905	{
1906	/*
1907	* First element in the command buffer contains start offset to read from
1908	* and second one the number of bytes to read.
1909	*/
1910	uint8_t uOffset = pBusLogic->aCommandBuffer[0];
1911	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[1];
1912
1913	pBusLogic->fUseLocalRam = true;
1914	pBusLogic->iReply = uOffset;
1915	break;
1916	}
1917	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
1918	{
1919	PRequestInitMbx pRequest = (PRequestInitMbx)pBusLogic->aCommandBuffer;
1920
1921	pBusLogic->fMbxIs24Bit = true;
1922	pBusLogic->cMailbox = pRequest->cMailbox;
1923	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)ADDR_TO_U32(pRequest->aMailboxBaseAddr);
1924	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1925	pBusLogic->GCPhysAddrMailboxIncomingBase = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->cMailbox * sizeof(Mailbox24));
1926
1927	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1928	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1929	Log(("cMailboxes=%u (24-bit mode)\n", pBusLogic->cMailbox));
1930	LogRel(("Initialized 24-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, ADDR_TO_U32(pRequest->aMailboxBaseAddr)));
1931
1932	pBusLogic->regStatus &= ~BL_STAT_INREQ;
1933	pBusLogic->cbReplyParametersLeft = 0;
1934	break;
1935	}
1936	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
1937	{
1938	PRequestInitializeExtendedMailbox pRequest = (PRequestInitializeExtendedMailbox)pBusLogic->aCommandBuffer;
1939
1940	pBusLogic->fMbxIs24Bit = false;
1941	pBusLogic->cMailbox = pRequest->cMailbox;
1942	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress;
1943	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1944	pBusLogic->GCPhysAddrMailboxIncomingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress + (pBusLogic->cMailbox * sizeof(Mailbox32));
1945
1946	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1947	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1948	Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox));
1949	LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress));
1950
1951	pBusLogic->regStatus &= ~BL_STAT_INREQ;
1952	pBusLogic->cbReplyParametersLeft = 0;
1953	break;
1954	}
1955	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
1956	{
1957	if (pBusLogic->aCommandBuffer[0] == 0)
1958	pBusLogic->fStrictRoundRobinMode = false;
1959	else if (pBusLogic->aCommandBuffer[0] == 1)
1960	pBusLogic->fStrictRoundRobinMode = true;
1961	else
1962	AssertMsgFailed(("Invalid round robin mode %d\n", pBusLogic->aCommandBuffer[0]));
1963
1964	pBusLogic->cbReplyParametersLeft = 0;
1965	break;
1966	}
1967	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
1968	{
1969	if (pBusLogic->aCommandBuffer[0] == 0)
1970	pBusLogic->fExtendedLunCCBFormat = false;
1971	else if (pBusLogic->aCommandBuffer[0] == 1)
1972	pBusLogic->fExtendedLunCCBFormat = true;
1973	else
1974	AssertMsgFailed(("Invalid CCB format %d\n", pBusLogic->aCommandBuffer[0]));
1975
1976	pBusLogic->cbReplyParametersLeft = 0;
1977	break;
1978	}
1979	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
1980	/* This is supposed to send TEST UNIT READY to each target/LUN.
1981	* We cheat and skip that, since we already know what's attached
1982	*/
1983	memset(pBusLogic->aReplyBuffer, 0, 8);
1984	for (int i = 0; i < 8; ++i)
1985	{
1986	if (pBusLogic->aDeviceStates[i].fPresent)
1987	pBusLogic->aReplyBuffer[i] = 1;
1988	}
1989	pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */
1990	pBusLogic->cbReplyParametersLeft = 8;
1991	break;
1992	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
1993	/* See note about cheating above. */
1994	memset(pBusLogic->aReplyBuffer, 0, 8);
1995	for (int i = 0; i < 8; ++i)
1996	{
1997	if (pBusLogic->aDeviceStates[i + 8].fPresent)
1998	pBusLogic->aReplyBuffer[i] = 1;
1999	}
2000	pBusLogic->cbReplyParametersLeft = 8;
2001	break;
2002	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
2003	{
2004	/* Each bit which is set in the 16bit wide variable means a present device. */
2005	uint16_t u16TargetsPresentMask = 0;
2006
2007	for (uint8_t i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
2008	{
2009	if (pBusLogic->aDeviceStates[i].fPresent)
2010	u16TargetsPresentMask \|= (1 << i);
2011	}
2012	pBusLogic->aReplyBuffer[0] = (uint8_t)u16TargetsPresentMask;
2013	pBusLogic->aReplyBuffer[1] = (uint8_t)(u16TargetsPresentMask >> 8);
2014	pBusLogic->cbReplyParametersLeft = 2;
2015	break;
2016	}
2017	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2018	{
2019	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
2020
2021	for (uint8_t i = 0; i < pBusLogic->cbReplyParametersLeft; i++)
2022	pBusLogic->aReplyBuffer[i] = 0; /** @todo Figure if we need something other here. It's not needed for the linux driver */
2023
2024	break;
2025	}
2026	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2027	{
2028	if (pBusLogic->aCommandBuffer[0] == 0)
2029	pBusLogic->fIRQEnabled = false;
2030	else
2031	pBusLogic->fIRQEnabled = true;
2032	/* No interrupt signaled regardless of enable/disable. */
2033	fSuppressIrq = true;
2034	break;
2035	}
2036	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2037	{
2038	pBusLogic->aReplyBuffer[0] = pBusLogic->aCommandBuffer[0];
2039	pBusLogic->cbReplyParametersLeft = 1;
2040	break;
2041	}
2042	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2043	{
2044	pBusLogic->cbReplyParametersLeft = 0;
2045	pBusLogic->LocalRam.structured.autoSCSIData.uBusOnDelay = pBusLogic->aCommandBuffer[0];
2046	Log(("Bus-on time: %d\n", pBusLogic->aCommandBuffer[0]));
2047	break;
2048	}
2049	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2050	{
2051	pBusLogic->cbReplyParametersLeft = 0;
2052	pBusLogic->LocalRam.structured.autoSCSIData.uBusOffDelay = pBusLogic->aCommandBuffer[0];
2053	Log(("Bus-off time: %d\n", pBusLogic->aCommandBuffer[0]));
2054	break;
2055	}
2056	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2057	{
2058	pBusLogic->cbReplyParametersLeft = 0;
2059	pBusLogic->LocalRam.structured.autoSCSIData.uDMATransferRate = pBusLogic->aCommandBuffer[0];
2060	Log(("Bus transfer rate: %02X\n", pBusLogic->aCommandBuffer[0]));
2061	break;
2062	}
2063	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2064	{
2065	RTGCPHYS GCPhysFifoBuf;
2066	Addr24 addr;
2067
2068	pBusLogic->cbReplyParametersLeft = 0;
2069	addr.hi = pBusLogic->aCommandBuffer[0];
2070	addr.mid = pBusLogic->aCommandBuffer[1];
2071	addr.lo = pBusLogic->aCommandBuffer[2];
2072	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2073	Log(("Write busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2074	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2075	&pBusLogic->LocalRam.u8View[64], 64);
2076	break;
2077	}
2078	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2079	{
2080	RTGCPHYS GCPhysFifoBuf;
2081	Addr24 addr;
2082
2083	pBusLogic->cbReplyParametersLeft = 0;
2084	addr.hi = pBusLogic->aCommandBuffer[0];
2085	addr.mid = pBusLogic->aCommandBuffer[1];
2086	addr.lo = pBusLogic->aCommandBuffer[2];
2087	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2088	Log(("Read busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2089	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2090	&pBusLogic->LocalRam.u8View[64], 64);
2091	break;
2092	}
2093	default:
2094	AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode));
2095	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2096	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2097	/* Commands valid for Adaptec 154xC which we don't handle since
2098	* we pretend being 154xB compatible. Just mark the command as invalid.
2099	*/
2100	Log(("Command %#x not valid for this adapter\n", pBusLogic->uOperationCode));
2101	pBusLogic->cbReplyParametersLeft = 0;
2102	pBusLogic->regStatus \|= BL_STAT_CMDINV;
2103	break;
2104	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */
2105	AssertMsgFailed(("Invalid mailbox execute state!\n"));
2106	}
2107
2108	Log(("uOperationCode=%#x, cbReplyParametersLeft=%d\n", pBusLogic->uOperationCode, pBusLogic->cbReplyParametersLeft));
2109
2110	/* Set the data in ready bit in the status register in case the command has a reply. */
2111	if (pBusLogic->cbReplyParametersLeft)
2112	pBusLogic->regStatus \|= BL_STAT_DIRRDY;
2113	else if (!pBusLogic->cbCommandParametersLeft)
2114	buslogicCommandComplete(pBusLogic, fSuppressIrq);
2115
2116	return rc;
2117	}
2118
2119	/**
2120	* Read a register from the BusLogic adapter.
2121	*
2122	* @returns VBox status code.
2123	* @param pBusLogic Pointer to the BusLogic instance data.
2124	* @param iRegister The index of the register to read.
2125	* @param pu32 Where to store the register content.
2126	*/
2127	static int buslogicRegisterRead(PBUSLOGIC pBusLogic, unsigned iRegister, uint32_t *pu32)
2128	{
2129	int rc = VINF_SUCCESS;
2130
2131	switch (iRegister)
2132	{
2133	case BUSLOGIC_REGISTER_STATUS:
2134	{
2135	*pu32 = pBusLogic->regStatus;
2136
2137	/* If the diagnostic active bit is set, we are in a guest-initiated
2138	* hard reset. If the guest reads the status register and waits for
2139	* the host adapter ready bit to be set, we terminate the reset right
2140	* away. However, guests may also expect the reset condition to clear
2141	* automatically after a period of time, in which case we can't show
2142	* the DIAG bit at all.
2143	*/
2144	if (pBusLogic->regStatus & BL_STAT_DACT)
2145	{
2146	uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
2147
2148	pBusLogic->regStatus &= ~BL_STAT_DACT;
2149	pBusLogic->regStatus \|= BL_STAT_HARDY;
2150
2151	if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS)
2152	{
2153	/* If reset already expired, let the guest see that right away. */
2154	*pu32 = pBusLogic->regStatus;
2155	pBusLogic->u64ResetTime = 0;
2156	}
2157	}
2158	break;
2159	}
2160	case BUSLOGIC_REGISTER_DATAIN:
2161	{
2162	if (pBusLogic->fUseLocalRam)
2163	*pu32 = pBusLogic->LocalRam.u8View[pBusLogic->iReply];
2164	else
2165	*pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply];
2166
2167	/* Careful about underflow - guest can read data register even if
2168	* no data is available.
2169	*/
2170	if (pBusLogic->cbReplyParametersLeft)
2171	{
2172	pBusLogic->iReply++;
2173	pBusLogic->cbReplyParametersLeft--;
2174	if (!pBusLogic->cbReplyParametersLeft)
2175	{
2176	/*
2177	* Reply finished, set command complete bit, unset data-in ready bit and
2178	* interrupt the guest if enabled.
2179	*/
2180	buslogicCommandComplete(pBusLogic, false);
2181	}
2182	}
2183	LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32,
2184	pBusLogic->iReply, pBusLogic->cbReplyParametersLeft));
2185	break;
2186	}
2187	case BUSLOGIC_REGISTER_INTERRUPT:
2188	{
2189	*pu32 = pBusLogic->regInterrupt;
2190	break;
2191	}
2192	case BUSLOGIC_REGISTER_GEOMETRY:
2193	{
2194	*pu32 = pBusLogic->regGeometry;
2195	break;
2196	}
2197	default:
2198	*pu32 = UINT32_C(0xffffffff);
2199	}
2200
2201	Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2202	__FUNCTION__, pu32, 1, pu32, iRegister, rc));
2203
2204	return rc;
2205	}
2206
2207	/**
2208	* Write a value to a register.
2209	*
2210	* @returns VBox status code.
2211	* @param pBusLogic Pointer to the BusLogic instance data.
2212	* @param iRegister The index of the register to read.
2213	* @param uVal The value to write.
2214	*/
2215	static int buslogicRegisterWrite(PBUSLOGIC pBusLogic, unsigned iRegister, uint8_t uVal)
2216	{
2217	int rc = VINF_SUCCESS;
2218
2219	switch (iRegister)
2220	{
2221	case BUSLOGIC_REGISTER_CONTROL:
2222	{
2223	if ((uVal & BL_CTRL_RHARD) \|\| (uVal & BL_CTRL_RSOFT))
2224	{
2225	#ifdef IN_RING3
2226	bool fHardReset = !!(uVal & BL_CTRL_RHARD);
2227
2228	LogRel(("BusLogic: %s reset\n", fHardReset ? "hard" : "soft"));
2229	buslogicR3InitiateReset(pBusLogic, fHardReset);
2230	#else
2231	rc = VINF_IOM_R3_IOPORT_WRITE;
2232	#endif
2233	break;
2234	}
2235
2236	rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_IOM_R3_IOPORT_WRITE);
2237	if (rc != VINF_SUCCESS)
2238	return rc;
2239
2240	#ifdef LOG_ENABLED
2241	uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0);
2242	Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady));
2243	#endif
2244
2245	if (uVal & BL_CTRL_RINT)
2246	buslogicClearInterrupt(pBusLogic);
2247
2248	PDMCritSectLeave(&pBusLogic->CritSectIntr);
2249
2250	break;
2251	}
2252	case BUSLOGIC_REGISTER_COMMAND:
2253	{
2254	/* Fast path for mailbox execution command. */
2255	if ((uVal == BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND) && (pBusLogic->uOperationCode == 0xff))
2256	{
2257	/* If there are no mailboxes configured, don't even try to do anything. */
2258	if (pBusLogic->cMailbox)
2259	{
2260	ASMAtomicIncU32(&pBusLogic->cMailboxesReady);
2261	if (!ASMAtomicXchgBool(&pBusLogic->fNotificationSent, true))
2262	{
2263	/* Send new notification to the queue. */
2264	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pBusLogic->CTX_SUFF(pNotifierQueue));
2265	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2266	PDMQueueInsert(pBusLogic->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2267	}
2268	}
2269
2270	return rc;
2271	}
2272
2273	/*
2274	* Check if we are already fetch command parameters from the guest.
2275	* If not we initialize executing a new command.
2276	*/
2277	if (pBusLogic->uOperationCode == 0xff)
2278	{
2279	pBusLogic->uOperationCode = uVal;
2280	pBusLogic->iParameter = 0;
2281
2282	/* Mark host adapter as busy and clear the invalid status bit. */
2283	pBusLogic->regStatus &= ~(BL_STAT_HARDY \| BL_STAT_CMDINV);
2284
2285	/* Get the number of bytes for parameters from the command code. */
2286	switch (pBusLogic->uOperationCode)
2287	{
2288	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
2289	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
2290	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
2291	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
2292	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
2293	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
2294	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
2295	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
2296	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
2297	pBusLogic->cbCommandParametersLeft = 0;
2298	break;
2299	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
2300	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
2301	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
2302	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
2303	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
2304	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
2305	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2306	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2307	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2308	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2309	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2310	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2311	pBusLogic->cbCommandParametersLeft = 1;
2312	break;
2313	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
2314	pBusLogic->cbCommandParametersLeft = 2;
2315	break;
2316	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2317	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2318	pBusLogic->cbCommandParametersLeft = 3;
2319	break;
2320	case BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT:
2321	pBusLogic->cbCommandParametersLeft = 4;
2322	break;
2323	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
2324	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitMbx);
2325	break;
2326	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
2327	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox);
2328	break;
2329	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
2330	/* There must be at least one byte following this command. */
2331	pBusLogic->cbCommandParametersLeft = 1;
2332	break;
2333	case BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND:
2334	/* 12 bytes + variable-length CDB. */
2335	pBusLogic->cbCommandParametersLeft = 12;
2336	break;
2337	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2338	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2339	/* Invalid commands. */
2340	pBusLogic->cbCommandParametersLeft = 0;
2341	break;
2342	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should not come here anymore. */
2343	default:
2344	AssertMsgFailed(("Invalid operation code %#x\n", uVal));
2345	}
2346	}
2347	else
2348	{
2349	#ifndef IN_RING3
2350	/* This command must be executed in R3 as it rehooks the ISA I/O port. */
2351	if (pBusLogic->uOperationCode == BUSLOGICCOMMAND_MODIFY_IO_ADDRESS)
2352	{
2353	rc = VINF_IOM_R3_IOPORT_WRITE;
2354	break;
2355	}
2356	#endif
2357	/*
2358	* The real adapter would set the Command register busy bit in the status register.
2359	* The guest has to wait until it is unset.
2360	* We don't need to do it because the guest does not continue execution while we are in this
2361	* function.
2362	*/
2363	pBusLogic->aCommandBuffer[pBusLogic->iParameter] = uVal;
2364	pBusLogic->iParameter++;
2365	pBusLogic->cbCommandParametersLeft--;
2366	}
2367
2368	/* Start execution of command if there are no parameters left. */
2369	if (!pBusLogic->cbCommandParametersLeft)
2370	{
2371	rc = buslogicProcessCommand(pBusLogic);
2372	AssertMsgRC(rc, ("Processing command failed rc=%Rrc\n", rc));
2373	}
2374	break;
2375	}
2376
2377	/* On BusLogic adapters, the interrupt and geometry registers are R/W.
2378	* That is different from Adaptec 154x where those are read only.
2379	*/
2380	case BUSLOGIC_REGISTER_INTERRUPT:
2381	pBusLogic->regInterrupt = uVal;
2382	break;
2383
2384	case BUSLOGIC_REGISTER_GEOMETRY:
2385	pBusLogic->regGeometry = uVal;
2386	break;
2387
2388	default:
2389	AssertMsgFailed(("Register not available\n"));
2390	rc = VERR_IOM_IOPORT_UNUSED;
2391	}
2392
2393	return rc;
2394	}
2395
2396	/**
2397	* Memory mapped I/O Handler for read operations.
2398	*
2399	* @returns VBox status code.
2400	*
2401	* @param pDevIns The device instance.
2402	* @param pvUser User argument.
2403	* @param GCPhysAddr Physical address (in GC) where the read starts.
2404	* @param pv Where to store the result.
2405	* @param cb Number of bytes read.
2406	*/
2407	PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2408	{
2409	RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
2410
2411	/* the linux driver does not make use of the MMIO area. */
2412	AssertMsgFailed(("MMIO Read\n"));
2413	return VINF_SUCCESS;
2414	}
2415
2416	/**
2417	* Memory mapped I/O Handler for write operations.
2418	*
2419	* @returns VBox status code.
2420	*
2421	* @param pDevIns The device instance.
2422	* @param pvUser User argument.
2423	* @param GCPhysAddr Physical address (in GC) where the read starts.
2424	* @param pv Where to fetch the result.
2425	* @param cb Number of bytes to write.
2426	*/
2427	PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
2428	{
2429	RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
2430
2431	/* the linux driver does not make use of the MMIO area. */
2432	AssertMsgFailed(("MMIO Write\n"));
2433	return VINF_SUCCESS;
2434	}
2435
2436	/**
2437	* Port I/O Handler for IN operations.
2438	*
2439	* @returns VBox status code.
2440	*
2441	* @param pDevIns The device instance.
2442	* @param pvUser User argument.
2443	* @param uPort Port number used for the IN operation.
2444	* @param pu32 Where to store the result.
2445	* @param cb Number of bytes read.
2446	*/
2447	PDMBOTHCBDECL(int) buslogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2448	{
2449	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2450	unsigned iRegister = Port % 4;
2451	RT_NOREF_PV(pvUser); RT_NOREF_PV(cb);
2452
2453	Assert(cb == 1);
2454
2455	return buslogicRegisterRead(pBusLogic, iRegister, pu32);
2456	}
2457
2458	/**
2459	* Port I/O Handler for OUT operations.
2460	*
2461	* @returns VBox status code.
2462	*
2463	* @param pDevIns The device instance.
2464	* @param pvUser User argument.
2465	* @param uPort Port number used for the IN operation.
2466	* @param u32 The value to output.
2467	* @param cb The value size in bytes.
2468	*/
2469	PDMBOTHCBDECL(int) buslogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2470	{
2471	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2472	unsigned iRegister = Port % 4;
2473	uint8_t uVal = (uint8_t)u32;
2474	RT_NOREF2(pvUser, cb);
2475
2476	Assert(cb == 1);
2477
2478	int rc = buslogicRegisterWrite(pBusLogic, iRegister, (uint8_t)uVal);
2479
2480	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x rc=%Rrc\n",
2481	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port, rc));
2482
2483	return rc;
2484	}
2485
2486	#ifdef IN_RING3
2487
2488	static int buslogicR3PrepareBIOSSCSIRequest(PBUSLOGIC pBusLogic)
2489	{
2490	int rc;
2491	PBUSLOGICTASKSTATE pTaskState;
2492	uint32_t uTargetDevice;
2493
2494	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
2495	AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
2496
2497	pTaskState->fBIOS = true;
2498
2499	rc = vboxscsiSetupRequest(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, &uTargetDevice);
2500	AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
2501
2502	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2503
2504	pTaskState->CTX_SUFF(pTargetDevice) = &pBusLogic->aDeviceStates[uTargetDevice];
2505
2506	if (!pTaskState->CTX_SUFF(pTargetDevice)->fPresent)
2507	{
2508	/* Device is not present. */
2509	AssertMsg(pTaskState->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,
2510	("Device is not present but command is not inquiry\n"));
2511
2512	SCSIINQUIRYDATA ScsiInquiryData;
2513
2514	memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
2515	ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
2516	ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
2517
2518	memcpy(pBusLogic->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
2519
2520	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, SCSI_STATUS_OK);
2521	AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
2522
2523	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2524	}
2525	else
2526	{
2527	LogFlowFunc(("before increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2528	ASMAtomicIncU32(&pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests);
2529	LogFlowFunc(("after increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2530
2531	rc = pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector->pfnSCSIRequestSend(pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector,
2532	&pTaskState->PDMScsiRequest);
2533	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2534	}
2535
2536	return rc;
2537	}
2538
2539
2540	/**
2541	* Port I/O Handler for IN operations - BIOS port.
2542	*
2543	* @returns VBox status code.
2544	*
2545	* @param pDevIns The device instance.
2546	* @param pvUser User argument.
2547	* @param uPort Port number used for the IN operation.
2548	* @param pu32 Where to store the result.
2549	* @param cb Number of bytes read.
2550	*/
2551	static DECLCALLBACK(int) buslogicR3BiosIoPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2552	{
2553	RT_NOREF(pvUser, cb);
2554	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2555
2556	Assert(cb == 1);
2557
2558	int rc = vboxscsiReadRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pu32);
2559
2560	//Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2561	// __FUNCTION__, pu32, 1, pu32, (Port - BUSLOGIC_BIOS_IO_PORT), rc));
2562
2563	return rc;
2564	}
2565
2566	/**
2567	* Port I/O Handler for OUT operations - BIOS port.
2568	*
2569	* @returns VBox status code.
2570	*
2571	* @param pDevIns The device instance.
2572	* @param pvUser User argument.
2573	* @param uPort Port number used for the IN operation.
2574	* @param u32 The value to output.
2575	* @param cb The value size in bytes.
2576	*/
2577	static DECLCALLBACK(int) buslogicR3BiosIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2578	{
2579	RT_NOREF(pvUser, cb);
2580	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2581	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
2582
2583	/*
2584	* If there is already a request form the BIOS pending ignore this write
2585	* because it should not happen.
2586	*/
2587	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
2588	return VINF_SUCCESS;
2589
2590	Assert(cb == 1);
2591
2592	int rc = vboxscsiWriteRegister(&pThis->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), (uint8_t)u32);
2593	if (rc == VERR_MORE_DATA)
2594	{
2595	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
2596	/* Send a notifier to the PDM queue that there are pending requests. */
2597	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotifierQueue));
2598	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2599	PDMQueueInsert(pThis->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2600	rc = VINF_SUCCESS;
2601	}
2602	else if (RT_FAILURE(rc))
2603	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2604
2605	return VINF_SUCCESS;
2606	}
2607
2608	/**
2609	* Port I/O Handler for primary port range OUT string operations.
2610	* @see FNIOMIOPORTOUTSTRING for details.
2611	*/
2612	static DECLCALLBACK(int) buslogicR3BiosIoPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
2613	uint8_t const pbSrc, uint32_t pcTransfers, unsigned cb)
2614	{
2615	RT_NOREF(pvUser);
2616	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2617	Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2618
2619	/*
2620	* If there is already a request form the BIOS pending ignore this write
2621	* because it should not happen.
2622	*/
2623	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
2624	return VINF_SUCCESS;
2625
2626	int rc = vboxscsiWriteString(pDevIns, &pThis->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pbSrc, pcTransfers, cb);
2627	if (rc == VERR_MORE_DATA)
2628	{
2629	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
2630	/* Send a notifier to the PDM queue that there are pending requests. */
2631	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotifierQueue));
2632	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2633	PDMQueueInsert(pThis->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2634	}
2635	else if (RT_FAILURE(rc))
2636	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2637
2638	return VINF_SUCCESS;
2639	}
2640
2641	/**
2642	* Port I/O Handler for primary port range IN string operations.
2643	* @see FNIOMIOPORTINSTRING for details.
2644	*/
2645	static DECLCALLBACK(int) buslogicR3BiosIoPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
2646	uint8_t pbDst, uint32_t pcTransfers, unsigned cb)
2647	{
2648	RT_NOREF(pvUser);
2649	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2650	LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2651
2652	return vboxscsiReadString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2653	pbDst, pcTransfers, cb);
2654	}
2655
2656	/**
2657	* Update the ISA I/O range.
2658	*
2659	* @returns nothing.
2660	* @param pBusLogic Pointer to the BusLogic device instance.
2661	* @param uBaseCode Encoded ISA I/O base; only low 3 bits are used.
2662	*/
2663	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode)
2664	{
2665	uint8_t uCode = uBaseCode & MAX_ISA_BASE;
2666	uint16_t uNewBase = g_aISABases[uCode];
2667	int rc = VINF_SUCCESS;
2668
2669	LogFlowFunc(("ISA I/O code %02X, new base %X\n", uBaseCode, uNewBase));
2670
2671	/* Check if the same port range is already registered. */
2672	if (uNewBase != pBusLogic->IOISABase)
2673	{
2674	/* Unregister the old range, if any. */
2675	if (pBusLogic->IOISABase)
2676	rc = PDMDevHlpIOPortDeregister(pBusLogic->CTX_SUFF(pDevIns), pBusLogic->IOISABase, 4);
2677
2678	if (RT_SUCCESS(rc))
2679	{
2680	pBusLogic->IOISABase = 0; /* First mark as unregistered. */
2681	pBusLogic->uISABaseCode = ISA_BASE_DISABLED;
2682
2683	if (uNewBase)
2684	{
2685	/* Register the new range if requested. */
2686	rc = PDMDevHlpIOPortRegister(pBusLogic->CTX_SUFF(pDevIns), uNewBase, 4, NULL,
2687	buslogicIOPortWrite, buslogicIOPortRead,
2688	NULL, NULL,
2689	"BusLogic ISA");
2690	if (RT_SUCCESS(rc))
2691	{
2692	pBusLogic->IOISABase = uNewBase;
2693	pBusLogic->uISABaseCode = uCode;
2694	}
2695	}
2696	}
2697	if (RT_SUCCESS(rc))
2698	{
2699	if (uNewBase)
2700	{
2701	Log(("ISA I/O base: %x\n", uNewBase));
2702	LogRel(("BusLogic: ISA I/O base: %x\n", uNewBase));
2703	}
2704	else
2705	{
2706	Log(("Disabling ISA I/O ports.\n"));
2707	LogRel(("BusLogic: ISA I/O disabled\n"));
2708	}
2709	}
2710
2711	}
2712	return rc;
2713	}
2714
2715	static void buslogicR3WarningDiskFull(PPDMDEVINS pDevIns)
2716	{
2717	int rc;
2718	LogRel(("BusLogic#%d: Host disk full\n", pDevIns->iInstance));
2719	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_DISKFULL",
2720	N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
2721	AssertRC(rc);
2722	}
2723
2724	static void buslogicR3WarningFileTooBig(PPDMDEVINS pDevIns)
2725	{
2726	int rc;
2727	LogRel(("BusLogic#%d: File too big\n", pDevIns->iInstance));
2728	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_FILETOOBIG",
2729	N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
2730	AssertRC(rc);
2731	}
2732
2733	static void buslogicR3WarningISCSI(PPDMDEVINS pDevIns)
2734	{
2735	int rc;
2736	LogRel(("BusLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));
2737	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_ISCSIDOWN",
2738	N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
2739	AssertRC(rc);
2740	}
2741
2742	static void buslogicR3WarningUnknown(PPDMDEVINS pDevIns, int rc)
2743	{
2744	int rc2;
2745	LogRel(("BusLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));
2746	rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_UNKNOWN",
2747	N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);
2748	AssertRC(rc2);
2749	}
2750
2751	static void buslogicR3RedoSetWarning(PBUSLOGIC pThis, int rc)
2752	{
2753	if (rc == VERR_DISK_FULL)
2754	buslogicR3WarningDiskFull(pThis->CTX_SUFF(pDevIns));
2755	else if (rc == VERR_FILE_TOO_BIG)
2756	buslogicR3WarningFileTooBig(pThis->CTX_SUFF(pDevIns));
2757	else if (rc == VERR_BROKEN_PIPE \|\| rc == VERR_NET_CONNECTION_REFUSED)
2758	{
2759	/* iSCSI connection abort (first error) or failure to reestablish
2760	* connection (second error). Pause VM. On resume we'll retry. */
2761	buslogicR3WarningISCSI(pThis->CTX_SUFF(pDevIns));
2762	}
2763	else if (rc != VERR_VD_DEK_MISSING)
2764	buslogicR3WarningUnknown(pThis->CTX_SUFF(pDevIns), rc);
2765	}
2766
2767
2768	static DECLCALLBACK(int) buslogicR3MmioMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
2769	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2770	{
2771	RT_NOREF(iRegion);
2772	PPDMDEVINS pDevIns = pPciDev->pDevIns;
2773	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2774	int rc = VINF_SUCCESS;
2775
2776	Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2777
2778	Assert(cb >= 32);
2779
2780	if (enmType == PCI_ADDRESS_SPACE_MEM)
2781	{
2782	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2783	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
2784	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2785	buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO");
2786	if (RT_FAILURE(rc))
2787	return rc;
2788
2789	if (pThis->fR0Enabled)
2790	{
2791	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
2792	"buslogicMMIOWrite", "buslogicMMIORead");
2793	if (RT_FAILURE(rc))
2794	return rc;
2795	}
2796
2797	if (pThis->fGCEnabled)
2798	{
2799	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
2800	"buslogicMMIOWrite", "buslogicMMIORead");
2801	if (RT_FAILURE(rc))
2802	return rc;
2803	}
2804
2805	pThis->MMIOBase = GCPhysAddress;
2806	}
2807	else if (enmType == PCI_ADDRESS_SPACE_IO)
2808	{
2809	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2810	NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI");
2811	if (RT_FAILURE(rc))
2812	return rc;
2813
2814	if (pThis->fR0Enabled)
2815	{
2816	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2817	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2818	if (RT_FAILURE(rc))
2819	return rc;
2820	}
2821
2822	if (pThis->fGCEnabled)
2823	{
2824	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2825	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2826	if (RT_FAILURE(rc))
2827	return rc;
2828	}
2829
2830	pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2831	}
2832	else
2833	AssertMsgFailed(("Invalid enmType=%d\n", enmType));
2834
2835	return rc;
2836	}
2837
2838	static DECLCALLBACK(int) buslogicR3DeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,
2839	int rcCompletion, bool fRedo, int rcReq)
2840	{
2841	RT_NOREF(pInterface);
2842	int rc;
2843	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)pSCSIRequest->pvUser;
2844	PBUSLOGICDEVICE pBusLogicDevice = pTaskState->CTX_SUFF(pTargetDevice);
2845	PBUSLOGIC pBusLogic = pBusLogicDevice->CTX_SUFF(pBusLogic);
2846
2847	LogFlowFunc(("before decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2848	ASMAtomicDecU32(&pBusLogicDevice->cOutstandingRequests);
2849	LogFlowFunc(("after decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2850
2851	if (fRedo)
2852	{
2853	if (!pTaskState->fBIOS)
2854	{
2855	buslogicR3DataBufferFree(pTaskState);
2856
2857	if (pTaskState->pbSenseBuffer)
2858	buslogicR3SenseBufferFree(pTaskState, false /* fCopy */);
2859	}
2860
2861	/* Add to the list. */
2862	do
2863	{
2864	pTaskState->pRedoNext = ASMAtomicReadPtrT(&pBusLogic->pTasksRedoHead, PBUSLOGICTASKSTATE);
2865	} while (!ASMAtomicCmpXchgPtr(&pBusLogic->pTasksRedoHead, pTaskState, pTaskState->pRedoNext));
2866
2867	/* Suspend the VM if not done already. */
2868	if (!ASMAtomicXchgBool(&pBusLogic->fRedo, true))
2869	buslogicR3RedoSetWarning(pBusLogic, rcReq);
2870	}
2871	else
2872	{
2873	if (pTaskState->fBIOS)
2874	{
2875	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, pSCSIRequest, rcCompletion);
2876	AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2877	}
2878	else
2879	{
2880	buslogicR3DataBufferFree(pTaskState);
2881
2882	if (pTaskState->pbSenseBuffer)
2883	buslogicR3SenseBufferFree(pTaskState, (rcCompletion != SCSI_STATUS_OK));
2884
2885	if (rcCompletion == SCSI_STATUS_OK)
2886	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2887	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2888	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2889	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR);
2890	else if (rcCompletion == SCSI_STATUS_CHECK_CONDITION)
2891	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2892	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2893	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION,
2894	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2895	else
2896	AssertMsgFailed(("invalid completion status %d\n", rcCompletion));
2897	}
2898	#ifdef LOG_ENABLED
2899	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2900	#endif
2901
2902	/* Remove task from the cache. */
2903	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2904	}
2905
2906	if (pBusLogicDevice->cOutstandingRequests == 0 && pBusLogic->fSignalIdle)
2907	PDMDevHlpAsyncNotificationCompleted(pBusLogic->pDevInsR3);
2908
2909	return VINF_SUCCESS;
2910	}
2911
2912	static DECLCALLBACK(int) buslogicR3QueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,
2913	uint32_t piInstance, uint32_t piLUN)
2914	{
2915	PBUSLOGICDEVICE pBusLogicDevice = PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface);
2916	PPDMDEVINS pDevIns = pBusLogicDevice->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
2917
2918	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2919	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2920	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2921
2922	*ppcszController = pDevIns->pReg->szName;
2923	*piInstance = pDevIns->iInstance;
2924	*piLUN = pBusLogicDevice->iLUN;
2925
2926	return VINF_SUCCESS;
2927	}
2928
2929	static int buslogicR3DeviceSCSIRequestSetup(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2930	{
2931	int rc = VINF_SUCCESS;
2932	uint8_t uTargetIdCCB;
2933	PBUSLOGICDEVICE pTargetDevice;
2934
2935	/* Fetch the CCB from guest memory. */
2936	/** @todo How much do we really have to read? */
2937	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
2938	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
2939	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
2940
2941	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
2942	if (RT_LIKELY(uTargetIdCCB < RT_ELEMENTS(pBusLogic->aDeviceStates)))
2943	{
2944	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
2945	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
2946
2947	#ifdef LOG_ENABLED
2948	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2949	#endif
2950
2951	/* Alloc required buffers. */
2952	rc = buslogicR3DataBufferAlloc(pTaskState);
2953	AssertMsgRC(rc, ("Alloc failed rc=%Rrc\n", rc));
2954
2955	rc = buslogicR3SenseBufferAlloc(pTaskState);
2956	AssertMsgRC(rc, ("Mapping sense buffer failed rc=%Rrc\n", rc));
2957
2958	/* Check if device is present on bus. If not return error immediately and don't process this further. */
2959	if (!pBusLogic->aDeviceStates[uTargetIdCCB].fPresent)
2960	{
2961	buslogicR3DataBufferFree(pTaskState);
2962
2963	if (pTaskState->pbSenseBuffer)
2964	buslogicR3SenseBufferFree(pTaskState, true);
2965
2966	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2967	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT,
2968	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2969	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2970
2971	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2972	}
2973	else
2974	{
2975	/* Setup SCSI request. */
2976	pTaskState->PDMScsiRequest.uLogicalUnit = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uLogicalUnit
2977	: pTaskState->CommandControlBlockGuest.n.uLogicalUnit;
2978
2979	if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)
2980	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_UNKNOWN;
2981	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
2982	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;
2983	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
2984	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;
2985	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_NO_DATA)
2986	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;
2987	else
2988	AssertMsgFailed(("Invalid data direction type %d\n", pTaskState->CommandControlBlockGuest.c.uDataDirection));
2989
2990	pTaskState->PDMScsiRequest.cbCDB = pTaskState->CommandControlBlockGuest.c.cbCDB;
2991	pTaskState->PDMScsiRequest.pbCDB = pTaskState->CommandControlBlockGuest.c.abCDB;
2992	if (pTaskState->DataSeg.cbSeg)
2993	{
2994	pTaskState->PDMScsiRequest.cbScatterGather = (uint32_t)pTaskState->DataSeg.cbSeg;
2995	pTaskState->PDMScsiRequest.cScatterGatherEntries = 1;
2996	pTaskState->PDMScsiRequest.paScatterGatherHead = &pTaskState->DataSeg;
2997	}
2998	else
2999	{
3000	pTaskState->PDMScsiRequest.cbScatterGather = 0;
3001	pTaskState->PDMScsiRequest.cScatterGatherEntries = 0;
3002	pTaskState->PDMScsiRequest.paScatterGatherHead = NULL;
3003	}
3004	pTaskState->PDMScsiRequest.cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
3005	pTaskState->PDMScsiRequest.pbSenseBuffer = pTaskState->pbSenseBuffer;
3006	pTaskState->PDMScsiRequest.pvUser = pTaskState;
3007
3008	ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);
3009	rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pTaskState->PDMScsiRequest);
3010	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
3011	}
3012	}
3013	else
3014	{
3015	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3016
3017	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
3018	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER,
3019	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
3020	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
3021	}
3022
3023	return rc;
3024	}
3025
3026	static int buslogicR3DeviceSCSIRequestAbort(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
3027	{
3028	int rc = VINF_SUCCESS;
3029	uint8_t uTargetIdCCB;
3030	PBUSLOGICDEVICE pTargetDevice;
3031	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
3032
3033	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
3034	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
3035
3036	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
3037	if (RT_LIKELY(uTargetIdCCB < RT_ELEMENTS(pBusLogic->aDeviceStates)))
3038	{
3039	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
3040	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
3041
3042	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
3043	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED,
3044	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
3045	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND);
3046
3047	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3048	}
3049	else
3050	{
3051	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3052
3053	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
3054	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER,
3055	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
3056	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
3057	}
3058
3059	return rc;
3060	}
3061
3062	/**
3063	* Read a mailbox from guest memory. Convert 24-bit mailboxes to
3064	* 32-bit format.
3065	*
3066	* @returns Mailbox guest physical address.
3067	* @param pBusLogic Pointer to the BusLogic instance data.
3068	* @param pTaskStat Pointer to the task state being set up.
3069	*/
3070	static RTGCPHYS buslogicR3ReadOutgoingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
3071	{
3072	RTGCPHYS GCMailbox;
3073
3074	if (pBusLogic->fMbxIs24Bit)
3075	{
3076	Mailbox24 Mbx24;
3077
3078	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox24));
3079	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3080	pTaskState->MailboxGuest.u32PhysAddrCCB = ADDR_TO_U32(Mbx24.aPhysAddrCCB);
3081	pTaskState->MailboxGuest.u.out.uActionCode = Mbx24.uCmdState;
3082	}
3083	else
3084	{
3085	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox32));
3086	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &pTaskState->MailboxGuest, sizeof(Mailbox32));
3087	}
3088
3089	return GCMailbox;
3090	}
3091
3092	/**
3093	* Read mailbox from the guest and execute command.
3094	*
3095	* @returns VBox status code.
3096	* @param pBusLogic Pointer to the BusLogic instance data.
3097	*/
3098	static int buslogicR3ProcessMailboxNext(PBUSLOGIC pBusLogic)
3099	{
3100	PBUSLOGICTASKSTATE pTaskState = NULL;
3101	RTGCPHYS GCPhysAddrMailboxCurrent;
3102	int rc;
3103
3104	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
3105	AssertMsgReturn(RT_SUCCESS(rc) && (pTaskState != NULL), ("Failed to get task state from cache\n"), rc);
3106
3107	pTaskState->fBIOS = false;
3108	pTaskState->fIs24Bit = pBusLogic->fMbxIs24Bit;
3109	pTaskState->cbSGEntry = pBusLogic->fMbxIs24Bit ? sizeof(SGE24) : sizeof(SGE32);
3110
3111	if (!pBusLogic->fStrictRoundRobinMode)
3112	{
3113	/* Search for a filled mailbox - stop if we have scanned all mailboxes. */
3114	uint8_t uMailboxPosCur = pBusLogic->uMailboxOutgoingPositionCurrent;
3115
3116	do
3117	{
3118	/* Fetch mailbox from guest memory. */
3119	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
3120
3121	/* Check the next mailbox. */
3122	buslogicR3OutgoingMailboxAdvance(pBusLogic);
3123	} while ( pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE
3124	&& uMailboxPosCur != pBusLogic->uMailboxOutgoingPositionCurrent);
3125	}
3126	else
3127	{
3128	/* Fetch mailbox from guest memory. */
3129	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
3130	}
3131
3132	/*
3133	* Check if the mailbox is actually loaded.
3134	* It might be possible that the guest notified us without
3135	* a loaded mailbox. Do nothing in that case but leave a
3136	* log entry.
3137	*/
3138	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE)
3139	{
3140	Log(("No loaded mailbox left\n"));
3141	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3142	return VERR_NO_DATA;
3143	}
3144
3145	LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
3146	#ifdef LOG_ENABLED
3147	buslogicR3DumpMailboxInfo(&pTaskState->MailboxGuest, true);
3148	#endif
3149
3150	/* We got the mailbox, mark it as free in the guest. */
3151	uint8_t uActionCode = BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE;
3152	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
3153	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent + uCodeOffs, &uActionCode, sizeof(uActionCode));
3154
3155	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND)
3156	rc = buslogicR3DeviceSCSIRequestSetup(pBusLogic, pTaskState);
3157	else if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND)
3158	{
3159	LogFlow(("Aborting mailbox\n"));
3160	rc = buslogicR3DeviceSCSIRequestAbort(pBusLogic, pTaskState);
3161	}
3162	else
3163	AssertMsgFailed(("Invalid outgoing mailbox action code %u\n", pTaskState->MailboxGuest.u.out.uActionCode));
3164
3165	AssertRC(rc);
3166
3167	/* Advance to the next mailbox. */
3168	if (pBusLogic->fStrictRoundRobinMode)
3169	buslogicR3OutgoingMailboxAdvance(pBusLogic);
3170
3171	return rc;
3172	}
3173
3174	/**
3175	* Transmit queue consumer
3176	* Queue a new async task.
3177	*
3178	* @returns Success indicator.
3179	* If false the item will not be removed and the flushing will stop.
3180	* @param pDevIns The device instance.
3181	* @param pItem The item to consume. Upon return this item will be freed.
3182	*/
3183	static DECLCALLBACK(bool) buslogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3184	{
3185	RT_NOREF(pItem);
3186	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3187
3188	int rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3189	AssertRC(rc);
3190
3191	return true;
3192	}
3193
3194	/**
3195	* Kicks the controller to process pending tasks after the VM was resumed
3196	* or loaded from a saved state.
3197	*
3198	* @returns nothing.
3199	* @param pThis The BusLogic device instance.
3200	*/
3201	static void buslogicR3Kick(PBUSLOGIC pThis)
3202	{
3203	if (pThis->fRedo)
3204	{
3205	pThis->fRedo = false;
3206	if (pThis->VBoxSCSI.fBusy)
3207	{
3208
3209	/* The BIOS had a request active when we got suspended. Resume it. */
3210	int rc = buslogicR3PrepareBIOSSCSIRequest(pThis);
3211	AssertRC(rc);
3212	}
3213	else
3214	{
3215	/* Queue all pending tasks again. */
3216	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3217
3218	pThis->pTasksRedoHead = NULL;
3219
3220	while (pTaskState)
3221	{
3222	PBUSLOGICTASKSTATE pCur = pTaskState;
3223
3224	int rc = buslogicR3DeviceSCSIRequestSetup(pThis, pCur);
3225	AssertRC(rc);
3226
3227	pTaskState = pTaskState->pRedoNext;
3228	}
3229	}
3230	}
3231	}
3232
3233	/** @callback_method_impl{FNSSMDEVLIVEEXEC} */
3234	static DECLCALLBACK(int) buslogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
3235	{
3236	RT_NOREF(uPass);
3237	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3238
3239	/* Save the device config. */
3240	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3241	SSMR3PutBool(pSSM, pThis->aDeviceStates[i].fPresent);
3242
3243	return VINF_SSM_DONT_CALL_AGAIN;
3244	}
3245
3246	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
3247	static DECLCALLBACK(int) buslogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3248	{
3249	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3250
3251	/* Every device first. */
3252	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3253	{
3254	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3255
3256	AssertMsg(!pDevice->cOutstandingRequests,
3257	("There are still outstanding requests on this device\n"));
3258	SSMR3PutBool(pSSM, pDevice->fPresent);
3259	SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
3260	}
3261	/* Now the main device state. */
3262	SSMR3PutU8 (pSSM, pBusLogic->regStatus);
3263	SSMR3PutU8 (pSSM, pBusLogic->regInterrupt);
3264	SSMR3PutU8 (pSSM, pBusLogic->regGeometry);
3265	SSMR3PutMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3266	SSMR3PutU8 (pSSM, pBusLogic->uOperationCode);
3267	SSMR3PutMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3268	SSMR3PutU8 (pSSM, pBusLogic->iParameter);
3269	SSMR3PutU8 (pSSM, pBusLogic->cbCommandParametersLeft);
3270	SSMR3PutBool (pSSM, pBusLogic->fUseLocalRam);
3271	SSMR3PutMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3272	SSMR3PutU8 (pSSM, pBusLogic->iReply);
3273	SSMR3PutU8 (pSSM, pBusLogic->cbReplyParametersLeft);
3274	SSMR3PutBool (pSSM, pBusLogic->fIRQEnabled);
3275	SSMR3PutU8 (pSSM, pBusLogic->uISABaseCode);
3276	SSMR3PutU32 (pSSM, pBusLogic->cMailbox);
3277	SSMR3PutBool (pSSM, pBusLogic->fMbxIs24Bit);
3278	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxOutgoingBase);
3279	SSMR3PutU32 (pSSM, pBusLogic->uMailboxOutgoingPositionCurrent);
3280	SSMR3PutU32 (pSSM, pBusLogic->cMailboxesReady);
3281	SSMR3PutBool (pSSM, pBusLogic->fNotificationSent);
3282	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxIncomingBase);
3283	SSMR3PutU32 (pSSM, pBusLogic->uMailboxIncomingPositionCurrent);
3284	SSMR3PutBool (pSSM, pBusLogic->fStrictRoundRobinMode);
3285	SSMR3PutBool (pSSM, pBusLogic->fExtendedLunCCBFormat);
3286
3287	vboxscsiR3SaveExec(&pBusLogic->VBoxSCSI, pSSM);
3288
3289	/*
3290	* Save the physical addresses of the command control blocks of still pending tasks.
3291	* They are processed again on resume.
3292	*
3293	* The number of pending tasks needs to be determined first.
3294	*/
3295	uint32_t cTasks = 0;
3296
3297	PBUSLOGICTASKSTATE pTaskState = pBusLogic->pTasksRedoHead;
3298	if (pBusLogic->fRedo)
3299	{
3300	while (pTaskState)
3301	{
3302	cTasks++;
3303	pTaskState = pTaskState->pRedoNext;
3304	}
3305	}
3306	SSMR3PutU32(pSSM, cTasks);
3307
3308	/* Write the address of every task now. */
3309	pTaskState = pBusLogic->pTasksRedoHead;
3310	while (pTaskState)
3311	{
3312	SSMR3PutU32(pSSM, pTaskState->MailboxGuest.u32PhysAddrCCB);
3313	pTaskState = pTaskState->pRedoNext;
3314	}
3315
3316	return SSMR3PutU32(pSSM, UINT32_MAX);
3317	}
3318
3319	/** @callback_method_impl{FNSSMDEVLOADDONE} */
3320	static DECLCALLBACK(int) buslogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3321	{
3322	RT_NOREF(pSSM);
3323	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3324
3325	buslogicR3RegisterISARange(pThis, pThis->uISABaseCode);
3326	buslogicR3Kick(pThis);
3327	return VINF_SUCCESS;
3328	}
3329
3330	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
3331	static DECLCALLBACK(int) buslogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3332	{
3333	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3334	int rc = VINF_SUCCESS;
3335
3336	/* We support saved states only from this and older versions. */
3337	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_VERSION)
3338	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3339
3340	/* Every device first. */
3341	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3342	{
3343	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3344
3345	AssertMsg(!pDevice->cOutstandingRequests,
3346	("There are still outstanding requests on this device\n"));
3347	bool fPresent;
3348	rc = SSMR3GetBool(pSSM, &fPresent);
3349	AssertRCReturn(rc, rc);
3350	if (pDevice->fPresent != fPresent)
3351	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"), i, pDevice->fPresent, fPresent);
3352
3353	if (uPass == SSM_PASS_FINAL)
3354	SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
3355	}
3356
3357	if (uPass != SSM_PASS_FINAL)
3358	return VINF_SUCCESS;
3359
3360	/* Now the main device state. */
3361	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regStatus);
3362	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regInterrupt);
3363	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regGeometry);
3364	SSMR3GetMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3365	SSMR3GetU8 (pSSM, &pBusLogic->uOperationCode);
3366	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_CMDBUF_RESIZE)
3367	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3368	else
3369	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, BUSLOGIC_COMMAND_SIZE_OLD);
3370	SSMR3GetU8 (pSSM, &pBusLogic->iParameter);
3371	SSMR3GetU8 (pSSM, &pBusLogic->cbCommandParametersLeft);
3372	SSMR3GetBool (pSSM, &pBusLogic->fUseLocalRam);
3373	SSMR3GetMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3374	SSMR3GetU8 (pSSM, &pBusLogic->iReply);
3375	SSMR3GetU8 (pSSM, &pBusLogic->cbReplyParametersLeft);
3376	SSMR3GetBool (pSSM, &pBusLogic->fIRQEnabled);
3377	SSMR3GetU8 (pSSM, &pBusLogic->uISABaseCode);
3378	SSMR3GetU32 (pSSM, &pBusLogic->cMailbox);
3379	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX)
3380	SSMR3GetBool (pSSM, &pBusLogic->fMbxIs24Bit);
3381	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxOutgoingBase);
3382	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxOutgoingPositionCurrent);
3383	SSMR3GetU32 (pSSM, (uint32_t *)&pBusLogic->cMailboxesReady);
3384	SSMR3GetBool (pSSM, (bool *)&pBusLogic->fNotificationSent);
3385	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxIncomingBase);
3386	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxIncomingPositionCurrent);
3387	SSMR3GetBool (pSSM, &pBusLogic->fStrictRoundRobinMode);
3388	SSMR3GetBool (pSSM, &pBusLogic->fExtendedLunCCBFormat);
3389
3390	rc = vboxscsiR3LoadExec(&pBusLogic->VBoxSCSI, pSSM);
3391	if (RT_FAILURE(rc))
3392	{
3393	LogRel(("BusLogic: Failed to restore BIOS state: %Rrc.\n", rc));
3394	return PDMDEV_SET_ERROR(pDevIns, rc,
3395	N_("BusLogic: Failed to restore BIOS state\n"));
3396	}
3397
3398	if (pBusLogic->VBoxSCSI.fBusy)
3399	pBusLogic->fRedo = true;
3400
3401	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING)
3402	{
3403	/* Check if there are pending tasks saved. */
3404	uint32_t cTasks = 0;
3405
3406	SSMR3GetU32(pSSM, &cTasks);
3407
3408	if (cTasks)
3409	pBusLogic->fRedo = true;
3410
3411	for (uint32_t i = 0; i < cTasks; i++)
3412	{
3413	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)RTMemCacheAlloc(pBusLogic->hTaskCache);
3414	if (!pTaskState)
3415	{
3416	rc = VERR_NO_MEMORY;
3417	break;
3418	}
3419
3420	rc = SSMR3GetU32(pSSM, &pTaskState->MailboxGuest.u32PhysAddrCCB);
3421	if (RT_FAILURE(rc))
3422	{
3423	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3424	break;
3425	}
3426
3427	/* Link into the list. */
3428	pTaskState->pRedoNext = pBusLogic->pTasksRedoHead;
3429	pBusLogic->pTasksRedoHead = pTaskState;
3430	}
3431	}
3432
3433	if (RT_SUCCESS(rc))
3434	{
3435	uint32_t u32;
3436	rc = SSMR3GetU32(pSSM, &u32);
3437	if (RT_SUCCESS(rc))
3438	AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3439	}
3440
3441	return rc;
3442	}
3443
3444	/**
3445	* Gets the pointer to the status LED of a device - called from the SCSI driver.
3446	*
3447	* @returns VBox status code.
3448	* @param pInterface Pointer to the interface structure containing the called function pointer.
3449	* @param iLUN The unit which status LED we desire. Always 0 here as the driver
3450	* doesn't know about other LUN's.
3451	* @param ppLed Where to store the LED pointer.
3452	*/
3453	static DECLCALLBACK(int) buslogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3454	{
3455	PBUSLOGICDEVICE pDevice = PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface);
3456	if (iLUN == 0)
3457	{
3458	*ppLed = &pDevice->Led;
3459	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3460	return VINF_SUCCESS;
3461	}
3462	return VERR_PDM_LUN_NOT_FOUND;
3463	}
3464
3465	/**
3466	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3467	*/
3468	static DECLCALLBACK(void ) buslogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
3469	{
3470	PBUSLOGICDEVICE pDevice = PDMIBASE_2_PBUSLOGICDEVICE(pInterface);
3471	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
3472	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISCSIPORT, &pDevice->ISCSIPort);
3473	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
3474	return NULL;
3475	}
3476
3477	/**
3478	* Gets the pointer to the status LED of a unit.
3479	*
3480	* @returns VBox status code.
3481	* @param pInterface Pointer to the interface structure containing the called function pointer.
3482	* @param iLUN The unit which status LED we desire.
3483	* @param ppLed Where to store the LED pointer.
3484	*/
3485	static DECLCALLBACK(int) buslogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3486	{
3487	PBUSLOGIC pBusLogic = PDMILEDPORTS_2_PBUSLOGIC(pInterface);
3488	if (iLUN < BUSLOGIC_MAX_DEVICES)
3489	{
3490	*ppLed = &pBusLogic->aDeviceStates[iLUN].Led;
3491	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3492	return VINF_SUCCESS;
3493	}
3494	return VERR_PDM_LUN_NOT_FOUND;
3495	}
3496
3497	/**
3498	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3499	*/
3500	static DECLCALLBACK(void ) buslogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
3501	{
3502	PBUSLOGIC pThis = PDMIBASE_2_PBUSLOGIC(pInterface);
3503	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3504	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
3505	return NULL;
3506	}
3507
3508	/**
3509	* The worker thread processing requests from the guest.
3510	*
3511	* @returns VBox status code.
3512	* @param pDevIns The device instance.
3513	* @param pThread The thread structure.
3514	*/
3515	static DECLCALLBACK(int) buslogicR3Worker(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3516	{
3517	RT_NOREF(pDevIns);
3518	PBUSLOGIC pThis = (PBUSLOGIC)pThread->pvUser;
3519	int rc = VINF_SUCCESS;
3520
3521	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3522	return VINF_SUCCESS;
3523
3524	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3525	{
3526	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, true);
3527	bool fNotificationSent = ASMAtomicXchgBool(&pThis->fNotificationSent, false);
3528	if (!fNotificationSent)
3529	{
3530	Assert(ASMAtomicReadBool(&pThis->fWrkThreadSleeping));
3531	rc = SUPSemEventWaitNoResume(pThis->pSupDrvSession, pThis->hEvtProcess, RT_INDEFINITE_WAIT);
3532	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3533	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3534	break;
3535	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
3536	ASMAtomicWriteBool(&pThis->fNotificationSent, false);
3537	}
3538
3539	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, false);
3540
3541	/* Check whether there is a BIOS request pending and process it first. */
3542	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
3543	{
3544	rc = buslogicR3PrepareBIOSSCSIRequest(pThis);
3545	AssertRC(rc);
3546	ASMAtomicXchgBool(&pThis->fBiosReqPending, false);
3547	}
3548	else
3549	{
3550	ASMAtomicXchgU32(&pThis->cMailboxesReady, 0); /** @todo Actually not required anymore but to stay compatible with older saved states. */
3551
3552	/* Process mailboxes. */
3553	do
3554	{
3555	rc = buslogicR3ProcessMailboxNext(pThis);
3556	AssertMsg(RT_SUCCESS(rc) \|\| rc == VERR_NO_DATA, ("Processing mailbox failed rc=%Rrc\n", rc));
3557	} while (RT_SUCCESS(rc));
3558	}
3559	} /* While running */
3560
3561	return VINF_SUCCESS;
3562	}
3563
3564
3565	/**
3566	* Unblock the worker thread so it can respond to a state change.
3567	*
3568	* @returns VBox status code.
3569	* @param pDevIns The device instance.
3570	* @param pThread The send thread.
3571	*/
3572	static DECLCALLBACK(int) buslogicR3WorkerWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3573	{
3574	RT_NOREF(pThread);
3575	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3576	return SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3577	}
3578
3579	/**
3580	* BusLogic debugger info callback.
3581	*
3582	* @param pDevIns The device instance.
3583	* @param pHlp The output helpers.
3584	* @param pszArgs The arguments.
3585	*/
3586	static DECLCALLBACK(void) buslogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3587	{
3588	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3589	unsigned i;
3590	bool fVerbose = false;
3591
3592	/* Parse arguments. */
3593	if (pszArgs)
3594	fVerbose = strstr(pszArgs, "verbose") != NULL;
3595
3596	/* Show basic information. */
3597	pHlp->pfnPrintf(pHlp,
3598	"%s#%d: PCI I/O=%RTiop ISA I/O=%RTiop MMIO=%RGp IRQ=%u GC=%RTbool R0=%RTbool\n",
3599	pDevIns->pReg->szName,
3600	pDevIns->iInstance,
3601	pThis->IOPortBase, pThis->IOISABase, pThis->MMIOBase,
3602	PCIDevGetInterruptLine(&pThis->dev),
3603	!!pThis->fGCEnabled, !!pThis->fR0Enabled);
3604
3605	/* Print mailbox state. */
3606	if (pThis->regStatus & BL_STAT_INREQ)
3607	pHlp->pfnPrintf(pHlp, "Mailbox not initialized\n");
3608	else
3609	pHlp->pfnPrintf(pHlp, "%u-bit mailbox with %u entries at %RGp (%d LUN CCBs)\n",
3610	pThis->fMbxIs24Bit ? 24 : 32, pThis->cMailbox,
3611	pThis->GCPhysAddrMailboxOutgoingBase,
3612	pThis->fMbxIs24Bit ? 8 : pThis->fExtendedLunCCBFormat ? 64 : 8);
3613
3614	/* Print register contents. */
3615	pHlp->pfnPrintf(pHlp, "Registers: STAT=%02x INTR=%02x GEOM=%02x\n",
3616	pThis->regStatus, pThis->regInterrupt, pThis->regGeometry);
3617
3618	/* Print miscellaneous state. */
3619	pHlp->pfnPrintf(pHlp, "HAC interrupts: %s\n",
3620	pThis->fIRQEnabled ? "on" : "off");
3621
3622	/* Print the current command, if any. */
3623	if (pThis->uOperationCode != 0xff )
3624	pHlp->pfnPrintf(pHlp, "Current command: %02X\n", pThis->uOperationCode);
3625
3626	if (fVerbose && (pThis->regStatus & BL_STAT_INREQ) == 0)
3627	{
3628	RTGCPHYS GCMailbox;
3629
3630	/* Dump the mailbox contents. */
3631	if (pThis->fMbxIs24Bit)
3632	{
3633	Mailbox24 Mbx24;
3634
3635	/* Outgoing mailbox, 24-bit format. */
3636	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3637	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (24-bit) at %06X:\n", GCMailbox);
3638	for (i = 0; i < pThis->cMailbox; ++i)
3639	{
3640	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3641	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X action code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3642	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3643	GCMailbox += sizeof(Mailbox24);
3644	}
3645
3646	/* Incoming mailbox, 24-bit format. */
3647	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox24));
3648	pHlp->pfnPrintf(pHlp, " Incoming mailbox entries (24-bit) at %06X:\n", GCMailbox);
3649	for (i = 0; i < pThis->cMailbox; ++i)
3650	{
3651	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3652	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X completion code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3653	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxIncomingPositionCurrent == i ? " *" : "");
3654	GCMailbox += sizeof(Mailbox24);
3655	}
3656
3657	}
3658	else
3659	{
3660	Mailbox32 Mbx32;
3661
3662	/* Outgoing mailbox, 32-bit format. */
3663	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3664	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3665	for (i = 0; i < pThis->cMailbox; ++i)
3666	{
3667	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3668	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X action code %02X", i, Mbx32.u32PhysAddrCCB, Mbx32.u.out.uActionCode);
3669	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3670	GCMailbox += sizeof(Mailbox32);
3671	}
3672
3673	/* Incoming mailbox, 32-bit format. */
3674	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox32));
3675	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3676	for (i = 0; i < pThis->cMailbox; ++i)
3677	{
3678	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3679	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X completion code %02X BTSTAT %02X SDSTAT %02X", i,
3680	Mbx32.u32PhysAddrCCB, Mbx32.u.in.uCompletionCode, Mbx32.u.in.uHostAdapterStatus, Mbx32.u.in.uTargetDeviceStatus);
3681	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3682	GCMailbox += sizeof(Mailbox32);
3683	}
3684
3685	}
3686	}
3687	}
3688
3689	/* -=-=-=-=- Helper -=-=-=-=- */
3690
3691	/**
3692	* Checks if all asynchronous I/O is finished.
3693	*
3694	* Used by buslogicR3Reset, buslogicR3Suspend and buslogicR3PowerOff.
3695	*
3696	* @returns true if quiesced, false if busy.
3697	* @param pDevIns The device instance.
3698	*/
3699	static bool buslogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
3700	{
3701	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3702
3703	for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3704	{
3705	PBUSLOGICDEVICE pThisDevice = &pThis->aDeviceStates[i];
3706	if (pThisDevice->pDrvBase)
3707	{
3708	if (pThisDevice->cOutstandingRequests != 0)
3709	return false;
3710	}
3711	}
3712
3713	return true;
3714	}
3715
3716	/**
3717	* Callback employed by buslogicR3Suspend and buslogicR3PowerOff..
3718	*
3719	* @returns true if we've quiesced, false if we're still working.
3720	* @param pDevIns The device instance.
3721	*/
3722	static DECLCALLBACK(bool) buslogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
3723	{
3724	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3725	return false;
3726
3727	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3728	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3729	return true;
3730	}
3731
3732	/**
3733	* Common worker for ahciR3Suspend and ahciR3PowerOff.
3734	*/
3735	static void buslogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns, bool fPowerOff)
3736	{
3737	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3738
3739	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3740	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3741	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncSuspendOrPowerOffDone);
3742	else
3743	{
3744	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3745
3746	AssertMsg(!pThis->fNotificationSent, ("The PDM Queue should be empty at this point\n"));
3747
3748	if (pThis->fRedo)
3749	{
3750	if (fPowerOff)
3751	{
3752	/* Free tasks which would have been queued again on resume. */
3753	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3754
3755	pThis->pTasksRedoHead = NULL;
3756
3757	while (pTaskState)
3758	{
3759	PBUSLOGICTASKSTATE pFree;
3760
3761	pFree = pTaskState;
3762	pTaskState = pTaskState->pRedoNext;
3763
3764	RTMemCacheFree(pThis->hTaskCache, pFree);
3765	}
3766	pThis->fRedo = false;
3767	}
3768	else if (pThis->VBoxSCSI.fBusy)
3769	{
3770	/* Destroy the task because the BIOS interface has all necessary information. */
3771	Assert(pThis->pTasksRedoHead->fBIOS);
3772	Assert(!pThis->pTasksRedoHead->pRedoNext);
3773
3774	RTMemCacheFree(pThis->hTaskCache, pThis->pTasksRedoHead);
3775	pThis->pTasksRedoHead = NULL;
3776	}
3777	}
3778	}
3779	}
3780
3781	/**
3782	* Suspend notification.
3783	*
3784	* @param pDevIns The device instance data.
3785	*/
3786	static DECLCALLBACK(void) buslogicR3Suspend(PPDMDEVINS pDevIns)
3787	{
3788	Log(("buslogicR3Suspend\n"));
3789	buslogicR3SuspendOrPowerOff(pDevIns, false /* fPoweroff */);
3790	}
3791
3792	/**
3793	* Resume notification.
3794	*
3795	* @param pDevIns The device instance data.
3796	*/
3797	static DECLCALLBACK(void) buslogicR3Resume(PPDMDEVINS pDevIns)
3798	{
3799	Log(("buslogicR3Resume\n"));
3800	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3801	buslogicR3Kick(pThis);
3802	}
3803
3804
3805	/**
3806	* Detach notification.
3807	*
3808	* One harddisk at one port has been unplugged.
3809	* The VM is suspended at this point.
3810	*
3811	* @param pDevIns The device instance.
3812	* @param iLUN The logical unit which is being detached.
3813	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3814	*/
3815	static DECLCALLBACK(void) buslogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3816	{
3817	RT_NOREF(fFlags);
3818	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3819	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3820
3821	Log(("%s:\n", __FUNCTION__));
3822
3823	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3824	("BusLogic: Device does not support hotplugging\n"));
3825
3826	/*
3827	* Zero some important members.
3828	*/
3829	pDevice->pDrvBase = NULL;
3830	pDevice->fPresent = false;
3831	pDevice->pDrvSCSIConnector = NULL;
3832	}
3833
3834	/**
3835	* Attach command.
3836	*
3837	* This is called when we change block driver.
3838	*
3839	* @returns VBox status code.
3840	* @param pDevIns The device instance.
3841	* @param iLUN The logical unit which is being detached.
3842	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3843	*/
3844	static DECLCALLBACK(int) buslogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3845	{
3846	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3847	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3848	int rc;
3849
3850	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3851	("BusLogic: Device does not support hotplugging\n"),
3852	VERR_INVALID_PARAMETER);
3853
3854	/* the usual paranoia */
3855	AssertRelease(!pDevice->pDrvBase);
3856	AssertRelease(!pDevice->pDrvSCSIConnector);
3857	Assert(pDevice->iLUN == iLUN);
3858
3859	/*
3860	* Try attach the block device and get the interfaces,
3861	* required as well as optional.
3862	*/
3863	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
3864	if (RT_SUCCESS(rc))
3865	{
3866	/* Get SCSI connector interface. */
3867	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
3868	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
3869	pDevice->fPresent = true;
3870	}
3871	else
3872	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
3873
3874	if (RT_FAILURE(rc))
3875	{
3876	pDevice->pDrvBase = NULL;
3877	pDevice->pDrvSCSIConnector = NULL;
3878	}
3879	return rc;
3880	}
3881
3882	/**
3883	* Callback employed by buslogicR3Reset.
3884	*
3885	* @returns true if we've quiesced, false if we're still working.
3886	* @param pDevIns The device instance.
3887	*/
3888	static DECLCALLBACK(bool) buslogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
3889	{
3890	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3891
3892	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3893	return false;
3894	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3895
3896	buslogicR3HwReset(pThis, true);
3897	return true;
3898	}
3899
3900	/**
3901	* @copydoc FNPDMDEVRESET
3902	*/
3903	static DECLCALLBACK(void) buslogicR3Reset(PPDMDEVINS pDevIns)
3904	{
3905	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3906
3907	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3908	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3909	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncResetDone);
3910	else
3911	{
3912	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3913	buslogicR3HwReset(pThis, true);
3914	}
3915	}
3916
3917	static DECLCALLBACK(void) buslogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3918	{
3919	RT_NOREF(offDelta);
3920	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3921
3922	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3923	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
3924
3925	for (uint32_t i = 0; i < BUSLOGIC_MAX_DEVICES; i++)
3926	{
3927	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
3928
3929	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
3930	}
3931
3932	}
3933
3934	/**
3935	* Poweroff notification.
3936	*
3937	* @param pDevIns Pointer to the device instance
3938	*/
3939	static DECLCALLBACK(void) buslogicR3PowerOff(PPDMDEVINS pDevIns)
3940	{
3941	Log(("buslogicR3PowerOff\n"));
3942	buslogicR3SuspendOrPowerOff(pDevIns, true /* fPoweroff */);
3943	}
3944
3945	/**
3946	* Destroy a driver instance.
3947	*
3948	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
3949	* resources can be freed correctly.
3950	*
3951	* @param pDevIns The device instance data.
3952	*/
3953	static DECLCALLBACK(int) buslogicR3Destruct(PPDMDEVINS pDevIns)
3954	{
3955	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3956	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3957
3958	PDMR3CritSectDelete(&pThis->CritSectIntr);
3959
3960	/*
3961	* Free all tasks which are still hanging around
3962	* (Power off after the VM was suspended).
3963	*/
3964	if (pThis->fRedo)
3965	{
3966	/* Free tasks which would have been queued again on resume. */
3967	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3968
3969	pThis->pTasksRedoHead = NULL;
3970
3971	while (pTaskState)
3972	{
3973	PBUSLOGICTASKSTATE pFree;
3974
3975	pFree = pTaskState;
3976	pTaskState = pTaskState->pRedoNext;
3977
3978	RTMemCacheFree(pThis->hTaskCache, pFree);
3979	}
3980	pThis->fRedo = false;
3981	}
3982
3983	if (pThis->hEvtProcess != NIL_SUPSEMEVENT)
3984	{
3985	SUPSemEventClose(pThis->pSupDrvSession, pThis->hEvtProcess);
3986	pThis->hEvtProcess = NIL_SUPSEMEVENT;
3987	}
3988
3989	int rc = RTMemCacheDestroy(pThis->hTaskCache);
3990	AssertMsgRC(rc, ("Destroying task cache failed rc=%Rrc\n", rc));
3991
3992	return rc;
3993	}
3994
3995	/**
3996	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3997	*/
3998	static DECLCALLBACK(int) buslogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3999	{
4000	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
4001	int rc = VINF_SUCCESS;
4002	bool fBootable = true;
4003	char achISACompat[16];
4004	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4005
4006	/*
4007	* Init instance data (do early because of constructor).
4008	*/
4009	pThis->hTaskCache = NIL_RTMEMCACHE;
4010	pThis->pDevInsR3 = pDevIns;
4011	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4012	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4013	pThis->IBase.pfnQueryInterface = buslogicR3StatusQueryInterface;
4014	pThis->ILeds.pfnQueryStatusLed = buslogicR3StatusQueryStatusLed;
4015
4016	PCIDevSetVendorId (&pThis->dev, 0x104b); /* BusLogic */
4017	PCIDevSetDeviceId (&pThis->dev, 0x1040); /* BT-958 */
4018	PCIDevSetCommand (&pThis->dev, 0x0003);
4019	PCIDevSetRevisionId (&pThis->dev, 0x01);
4020	PCIDevSetClassProg (&pThis->dev, 0x00); /* SCSI */
4021	PCIDevSetClassSub (&pThis->dev, 0x00); /* SCSI */
4022	PCIDevSetClassBase (&pThis->dev, 0x01); /* Mass storage */
4023	PCIDevSetBaseAddress (&pThis->dev, 0, true /IO/, false /Pref/, false /64-bit/, 0x00000000);
4024	PCIDevSetBaseAddress (&pThis->dev, 1, false /IO/, false /Pref/, false /64-bit/, 0x00000000);
4025	PCIDevSetSubSystemVendorId(&pThis->dev, 0x104b);
4026	PCIDevSetSubSystemId (&pThis->dev, 0x1040);
4027	PCIDevSetInterruptLine (&pThis->dev, 0x00);
4028	PCIDevSetInterruptPin (&pThis->dev, 0x01);
4029
4030	/*
4031	* Validate and read configuration.
4032	*/
4033	if (!CFGMR3AreValuesValid(pCfg,
4034	"GCEnabled\0"
4035	"R0Enabled\0"
4036	"Bootable\0"
4037	"ISACompat\0"))
4038	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4039	N_("BusLogic configuration error: unknown option specified"));
4040
4041	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
4042	if (RT_FAILURE(rc))
4043	return PDMDEV_SET_ERROR(pDevIns, rc,
4044	N_("BusLogic configuration error: failed to read GCEnabled as boolean"));
4045	Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
4046
4047	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
4048	if (RT_FAILURE(rc))
4049	return PDMDEV_SET_ERROR(pDevIns, rc,
4050	N_("BusLogic configuration error: failed to read R0Enabled as boolean"));
4051	Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
4052	rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
4053	if (RT_FAILURE(rc))
4054	return PDMDEV_SET_ERROR(pDevIns, rc,
4055	N_("BusLogic configuration error: failed to read Bootable as boolean"));
4056	Log(("%s: fBootable=%RTbool\n", __FUNCTION__, fBootable));
4057
4058	/* Only the first instance defaults to having the ISA compatibility ports enabled. */
4059	if (iInstance == 0)
4060	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Alternate");
4061	else
4062	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Disabled");
4063	if (RT_FAILURE(rc))
4064	return PDMDEV_SET_ERROR(pDevIns, rc,
4065	N_("BusLogic configuration error: failed to read ISACompat as string"));
4066	Log(("%s: ISACompat=%s\n", __FUNCTION__, achISACompat));
4067
4068	/* Grok the ISACompat setting. */
4069	if (!strcmp(achISACompat, "Disabled"))
4070	pThis->uDefaultISABaseCode = ISA_BASE_DISABLED;
4071	else if (!strcmp(achISACompat, "Primary"))
4072	pThis->uDefaultISABaseCode = 0; /* I/O base at 330h. */
4073	else if (!strcmp(achISACompat, "Alternate"))
4074	pThis->uDefaultISABaseCode = 1; /* I/O base at 334h. */
4075	else
4076	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4077	N_("BusLogic configuration error: invalid ISACompat setting"));
4078
4079	/*
4080	* Register the PCI device and its I/O regions.
4081	*/
4082	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
4083	if (RT_FAILURE(rc))
4084	return rc;
4085
4086	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 32, PCI_ADDRESS_SPACE_IO, buslogicR3MmioMap);
4087	if (RT_FAILURE(rc))
4088	return rc;
4089
4090	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 32, PCI_ADDRESS_SPACE_MEM, buslogicR3MmioMap);
4091	if (RT_FAILURE(rc))
4092	return rc;
4093
4094	if (fBootable)
4095	{
4096	/* Register I/O port space for BIOS access. */
4097	rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_BIOS_IO_PORT, 4, NULL,
4098	buslogicR3BiosIoPortWrite, buslogicR3BiosIoPortRead,
4099	buslogicR3BiosIoPortWriteStr, buslogicR3BiosIoPortReadStr,
4100	"BusLogic BIOS");
4101	if (RT_FAILURE(rc))
4102	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register BIOS I/O handlers"));
4103	}
4104
4105	/* Set up the compatibility I/O range. */
4106	rc = buslogicR3RegisterISARange(pThis, pThis->uDefaultISABaseCode);
4107	if (RT_FAILURE(rc))
4108	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register ISA I/O handlers"));
4109
4110	/* Initialize task cache. */
4111	rc = RTMemCacheCreate(&pThis->hTaskCache, sizeof(BUSLOGICTASKSTATE), 0, UINT32_MAX,
4112	NULL, NULL, NULL, 0);
4113	if (RT_FAILURE(rc))
4114	return PDMDEV_SET_ERROR(pDevIns, rc,
4115	N_("BusLogic: Failed to initialize task cache\n"));
4116
4117	/* Initialize task queue. */
4118	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0,
4119	buslogicR3NotifyQueueConsumer, true, "BusLogicTask", &pThis->pNotifierQueueR3);
4120	if (RT_FAILURE(rc))
4121	return rc;
4122	pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
4123	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
4124
4125	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectIntr, RT_SRC_POS, "BusLogic-Intr#%u", pDevIns->iInstance);
4126	if (RT_FAILURE(rc))
4127	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic: cannot create critical section"));
4128
4129	/*
4130	* Create event semaphore and worker thread.
4131	*/
4132	rc = SUPSemEventCreate(pThis->pSupDrvSession, &pThis->hEvtProcess);
4133	if (RT_FAILURE(rc))
4134	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
4135	N_("BusLogic: Failed to create SUP event semaphore"));
4136
4137	char szDevTag[20];
4138	RTStrPrintf(szDevTag, sizeof(szDevTag), "BUSLOGIC-%u", iInstance);
4139
4140	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pThreadWrk, pThis, buslogicR3Worker,
4141	buslogicR3WorkerWakeUp, 0, RTTHREADTYPE_IO, szDevTag);
4142	if (RT_FAILURE(rc))
4143	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
4144	N_("BusLogic: Failed to create worker thread %s"), szDevTag);
4145
4146	/* Initialize per device state. */
4147	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
4148	{
4149	char szName[24];
4150	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
4151
4152	RTStrPrintf(szName, sizeof(szName), "Device%u", i);
4153
4154	/* Initialize static parts of the device. */
4155	pDevice->iLUN = i;
4156	pDevice->pBusLogicR3 = pThis;
4157	pDevice->pBusLogicR0 = PDMINS_2_DATA_R0PTR(pDevIns);
4158	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
4159	pDevice->Led.u32Magic = PDMLED_MAGIC;
4160	pDevice->IBase.pfnQueryInterface = buslogicR3DeviceQueryInterface;
4161	pDevice->ISCSIPort.pfnSCSIRequestCompleted = buslogicR3DeviceSCSIRequestCompleted;
4162	pDevice->ISCSIPort.pfnQueryDeviceLocation = buslogicR3QueryDeviceLocation;
4163	pDevice->ILed.pfnQueryStatusLed = buslogicR3DeviceQueryStatusLed;
4164
4165	/* Attach SCSI driver. */
4166	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
4167	if (RT_SUCCESS(rc))
4168	{
4169	/* Get SCSI connector interface. */
4170	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
4171	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
4172
4173	pDevice->fPresent = true;
4174	}
4175	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4176	{
4177	pDevice->pDrvBase = NULL;
4178	pDevice->fPresent = false;
4179	rc = VINF_SUCCESS;
4180	Log(("BusLogic: no driver attached to device %s\n", szName));
4181	}
4182	else
4183	{
4184	AssertLogRelMsgFailed(("BusLogic: Failed to attach %s\n", szName));
4185	return rc;
4186	}
4187	}
4188
4189	/*
4190	* Attach status driver (optional).
4191	*/
4192	PPDMIBASE pBase;
4193	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
4194	if (RT_SUCCESS(rc))
4195	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
4196	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
4197	{
4198	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
4199	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot attach to status driver"));
4200	}
4201
4202	rc = PDMDevHlpSSMRegisterEx(pDevIns, BUSLOGIC_SAVED_STATE_MINOR_VERSION, sizeof(*pThis), NULL,
4203	NULL, buslogicR3LiveExec, NULL,
4204	NULL, buslogicR3SaveExec, NULL,
4205	NULL, buslogicR3LoadExec, buslogicR3LoadDone);
4206	if (RT_FAILURE(rc))
4207	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register save state handlers"));
4208
4209	/*
4210	* Register the debugger info callback.
4211	*/
4212	char szTmp[128];
4213	RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
4214	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "BusLogic HBA info", buslogicR3Info);
4215
4216	rc = buslogicR3HwReset(pThis, true);
4217	AssertMsgRC(rc, ("hardware reset of BusLogic host adapter failed rc=%Rrc\n", rc));
4218
4219	return rc;
4220	}
4221
4222	/**
4223	* The device registration structure.
4224	*/
4225	const PDMDEVREG g_DeviceBusLogic =
4226	{
4227	/* u32Version */
4228	PDM_DEVREG_VERSION,
4229	/* szName */
4230	"buslogic",
4231	/* szRCMod */
4232	"VBoxDDRC.rc",
4233	/* szR0Mod */
4234	"VBoxDDR0.r0",
4235	/* pszDescription */
4236	"BusLogic BT-958 SCSI host adapter.\n",
4237	/* fFlags */
4238	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
4239	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION \|
4240	PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
4241	/* fClass */
4242	PDM_DEVREG_CLASS_STORAGE,
4243	/* cMaxInstances */
4244	~0U,
4245	/* cbInstance */
4246	sizeof(BUSLOGIC),
4247	/* pfnConstruct */
4248	buslogicR3Construct,
4249	/* pfnDestruct */
4250	buslogicR3Destruct,
4251	/* pfnRelocate */
4252	buslogicR3Relocate,
4253	/* pfnMemSetup */
4254	NULL,
4255	/* pfnPowerOn */
4256	NULL,
4257	/* pfnReset */
4258	buslogicR3Reset,
4259	/* pfnSuspend */
4260	buslogicR3Suspend,
4261	/* pfnResume */
4262	buslogicR3Resume,
4263	/* pfnAttach */
4264	buslogicR3Attach,
4265	/* pfnDetach */
4266	buslogicR3Detach,
4267	/* pfnQueryInterface. */
4268	NULL,
4269	/* pfnInitComplete */
4270	NULL,
4271	/* pfnPowerOff */
4272	buslogicR3PowerOff,
4273	/* pfnSoftReset */
4274	NULL,
4275	/* u32VersionEnd */
4276	PDM_DEVREG_VERSION
4277	};
4278
4279	#endif /* IN_RING3 */
4280	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Storage/DevBusLogic.cpp@ 63289

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