DevPIC.cpp@ 11264

最後變更在這個檔案從11264是 11264,由 vboxsync 提交於 17 年前
DevPIC: pData -> pThis.
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1	/* $Id: DevPIC.cpp 11264 2008-08-08 15:52:17Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PIC
26	#include <VBox/pdmdev.h>
27	#include <VBox/log.h>
28	#include <iprt/assert.h>
29
30	#include "../vl_vbox.h"
31
32
33	/*******************************************************************************
34	* Defined Constants And Macros *
35	*******************************************************************************/
36	/** @def PIC_LOCK
37	* Acquires the PDM lock. This is a NOP if locking is disabled. */
38	/** @def PIC_UNLOCK
39	* Releases the PDM lock. This is a NOP if locking is disabled. */
40	#define PIC_LOCK(pThis, rc) \
41	do { \
42	int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
43	if (rc2 != VINF_SUCCESS) \
44	return rc2; \
45	} while (0)
46	#define PIC_UNLOCK(pThis) \
47	(pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
48
49
50	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
51	/*******************************************************************************
52	* Internal Functions *
53	*******************************************************************************/
54	__BEGIN_DECLS
55
56	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
57	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
58	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
59	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
60	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
61	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
62
63	__END_DECLS
64	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
65
66
67	/*
68	* QEMU 8259 interrupt controller emulation
69	*
70	* Copyright (c) 2003-2004 Fabrice Bellard
71	*
72	* Permission is hereby granted, free of charge, to any person obtaining a copy
73	* of this software and associated documentation files (the "Software"), to deal
74	* in the Software without restriction, including without limitation the rights
75	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
76	* copies of the Software, and to permit persons to whom the Software is
77	* furnished to do so, subject to the following conditions:
78	*
79	* The above copyright notice and this permission notice shall be included in
80	* all copies or substantial portions of the Software.
81	*
82	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
83	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
84	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
85	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
86	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
87	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
88	* THE SOFTWARE.
89	*/
90
91	/* debug PIC */
92	#define DEBUG_PIC
93
94	/#define DEBUG_IRQ_COUNT/
95
96	typedef struct PicState {
97	uint8_t last_irr; /* edge detection */
98	uint8_t irr; /* interrupt request register */
99	uint8_t imr; /* interrupt mask register */
100	uint8_t isr; /* interrupt service register */
101	uint8_t priority_add; /* highest irq priority */
102	uint8_t irq_base;
103	uint8_t read_reg_select;
104	uint8_t poll;
105	uint8_t special_mask;
106	uint8_t init_state;
107	uint8_t auto_eoi;
108	uint8_t rotate_on_auto_eoi;
109	uint8_t special_fully_nested_mode;
110	uint8_t init4; /* true if 4 byte init */
111	uint8_t elcr; /* PIIX edge/trigger selection*/
112	uint8_t elcr_mask;
113	/** Pointer to the device instance, R3 Ptr. */
114	PPDMDEVINSR3 pDevInsR3;
115	/** Pointer to the device instance, R0 Ptr. */
116	PPDMDEVINSR0 pDevInsR0;
117	/** Pointer to the device instance, RC Ptr. */
118	PPDMDEVINSRC pDevInsRC;
119	RTRCPTR Alignment0; /*< Structure size alignment. /
120	} PicState;
121
122	/**
123	* A PIC device instance data.
124	*/
125	typedef struct DEVPIC
126	{
127	/** The two interrupt controllers. */
128	PicState aPics[2];
129	/** Pointer to the device instance - R3 Ptr. */
130	PPDMDEVINSR3 pDevInsR3;
131	/** Pointer to the PIC R3 helpers. */
132	PCPDMPICHLPR3 pPicHlpR3;
133	/** Pointer to the device instance - R0 Ptr. */
134	PPDMDEVINSR0 pDevInsR0;
135	/** Pointer to the PIC R0 helpers. */
136	PCPDMPICHLPR0 pPicHlpR0;
137	/** Pointer to the device instance - RC Ptr. */
138	PPDMDEVINSRC pDevInsRC;
139	/** Pointer to the PIC RC helpers. */
140	PCPDMPICHLPRC pPicHlpRC;
141	#ifdef VBOX_WITH_STATISTICS
142	STAMCOUNTER StatSetIrqGC;
143	STAMCOUNTER StatSetIrqHC;
144	STAMCOUNTER StatClearedActiveIRQ2;
145	STAMCOUNTER StatClearedActiveMasterIRQ;
146	STAMCOUNTER StatClearedActiveSlaveIRQ;
147	#endif
148	} DEVPIC, *PDEVPIC;
149
150
151	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
152	#ifdef LOG_ENABLED
153	static inline void DumpPICState(PicState s, const char szFn)
154	{
155	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
156
157	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
158	szFn, (&pThis->aPics[0] == s) ? 0 : 1,
159	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
160	}
161	#else
162	# define DumpPICState(pThis, szFn) do { } while (0)
163	#endif
164
165	/* set irq level. If an edge is detected, then the IRR is set to 1 */
166	static inline void pic_set_irq1(PicState *s, int irq, int level)
167	{
168	int mask;
169	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
170	mask = 1 << irq;
171	if (s->elcr & mask) {
172	/* level triggered */
173	if (level) {
174	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr \| mask));
175	s->irr \|= mask;
176	s->last_irr \|= mask;
177	} else {
178	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
179	s->irr &= ~mask;
180	s->last_irr &= ~mask;
181	}
182	} else {
183	/* edge triggered */
184	if (level) {
185	if ((s->last_irr & mask) == 0)
186	{
187	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
188	s->irr \|= mask;
189	}
190	s->last_irr \|= mask;
191	} else {
192	s->last_irr &= ~mask;
193	}
194	}
195	DumpPICState(s, "pic_set_irq1");
196	}
197
198	/* return the highest priority found in mask (highest = smallest
199	number). Return 8 if no irq */
200	static inline int get_priority(PicState *s, int mask)
201	{
202	int priority;
203	if (mask == 0)
204	return 8;
205	priority = 0;
206	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
207	priority++;
208	return priority;
209	}
210
211	/* return the pic wanted interrupt. return -1 if none */
212	static int pic_get_irq(PicState *s)
213	{
214	PicState *pics = &(PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC))->aPics[0];
215	int mask, cur_priority, priority;
216	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
217	DumpPICState(s, "pic_get_irq");
218
219	mask = s->irr & ~s->imr;
220	priority = get_priority(s, mask);
221	Log(("pic_get_irq: priority=%x\n", priority));
222	if (priority == 8)
223	return -1;
224	/* compute current priority. If special fully nested mode on the
225	master, the IRQ coming from the slave is not taken into account
226	for the priority computation. */
227	mask = s->isr;
228	if (s->special_fully_nested_mode && s == &pics[0])
229	mask &= ~(1 << 2);
230	cur_priority = get_priority(s, mask);
231	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
232	if (priority < cur_priority) {
233	/* higher priority found: an irq should be generated */
234	return (priority + s->priority_add) & 7;
235	} else {
236	return -1;
237	}
238	}
239
240	/* raise irq to CPU if necessary. must be called every time the active
241	irq may change */
242	static int pic_update_irq(PDEVPIC pThis)
243	{
244	PicState *pics = &pThis->aPics[0];
245	int irq2, irq;
246
247	/* first look at slave pic */
248	irq2 = pic_get_irq(&pics[1]);
249	Log(("pic_update_irq irq2=%d\n", irq2));
250	if (irq2 >= 0) {
251	/* if irq request by slave pic, signal master PIC */
252	pic_set_irq1(&pics[0], 2, 1);
253	pic_set_irq1(&pics[0], 2, 0);
254	}
255	/* look at requested irq */
256	irq = pic_get_irq(&pics[0]);
257	if (irq >= 0)
258	{
259	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
260	* spurious slave interrupts in picGetInterrupt.
261	*/
262	if (irq != 2 \|\| irq2 != -1)
263	{
264	#if defined(DEBUG_PIC)
265	int i;
266	for(i = 0; i < 2; i++) {
267	Log(("pic%d: imr=%x irr=%x padd=%d\n",
268	i, pics[i].imr, pics[i].irr,
269	pics[i].priority_add));
270	}
271	Log(("pic: cpu_interrupt\n"));
272	#endif
273	pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
274	}
275	else
276	{
277	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
278	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
279	/* Clear it here, so lower priority interrupts can still be dispatched. */
280
281	/* if this was the only pending irq, then we must clear the interrupt ff flag */
282	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
283
284	/** @note Is this correct? */
285	pics[0].irr &= ~(1 << 2);
286
287	/* Call ourselves again just in case other interrupts are pending */
288	return pic_update_irq(pThis);
289	}
290	}
291	else
292	{
293	Log(("pic_update_irq: no interrupt is pending!!\n"));
294
295	/* we must clear the interrupt ff flag */
296	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
297	}
298	return VINF_SUCCESS;
299	}
300
301	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
302	static void pic_update_imr(PDEVPIC pThis, PicState *s, uint8_t val)
303	{
304	int irq, intno;
305	PicState *pActivePIC;
306
307	/* Query the current pending irq, if any. */
308	pActivePIC = &pThis->aPics[0];
309	intno = irq = pic_get_irq(pActivePIC);
310	if (irq == 2)
311	{
312	pActivePIC = &pThis->aPics[1];
313	irq = pic_get_irq(pActivePIC);
314	intno = irq + 8;
315	}
316
317	/* Update IMR */
318	s->imr = val;
319
320	/* If an interrupt is pending and now masked, then clear the FF flag. */
321	if ( irq >= 0
322	&& ((1 << irq) & ~pActivePIC->imr) == 0)
323	{
324	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
325	pThis->aPics[0].elcr, pThis->aPics[0].last_irr, pThis->aPics[0].irr, pThis->aPics[0].imr, pThis->aPics[0].isr, pThis->aPics[0].irq_base));
326	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
327	pThis->aPics[1].elcr, pThis->aPics[1].last_irr, pThis->aPics[1].irr, pThis->aPics[1].imr, pThis->aPics[1].isr, pThis->aPics[1].irq_base));
328
329	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
330	/** @todo Is this correct? */
331	if (intno > 7)
332	{
333	pThis->aPics[0].irr &= ~(1 << 2);
334	STAM_COUNTER_INC(&pThis->StatClearedActiveSlaveIRQ);
335	}
336	else
337	STAM_COUNTER_INC(&pThis->StatClearedActiveMasterIRQ);
338
339	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
340	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
341	}
342	}
343
344
345	/**
346	* Set the an IRQ.
347	*
348	* @param pDevIns Device instance of the PICs.
349	* @param iIrq IRQ number to set.
350	* @param iLevel IRQ level.
351	*/
352	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
353	{
354	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
355	Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
356	Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
357	Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
358	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
359
360	Log(("picSetIrq %d %d\n", iIrq, iLevel));
361	DumpPICState(&pThis->aPics[0], "picSetIrq");
362	DumpPICState(&pThis->aPics[1], "picSetIrq");
363	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
364	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
365	pic_update_irq(pThis);
366	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
367	{
368	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0);
369	pic_update_irq(pThis);
370	}
371	}
372
373
374	/* acknowledge interrupt 'irq' */
375	static inline void pic_intack(PicState *s, int irq)
376	{
377	if (s->auto_eoi) {
378	if (s->rotate_on_auto_eoi)
379	s->priority_add = (irq + 1) & 7;
380	} else {
381	s->isr \|= (1 << irq);
382	}
383	/* We don't clear a level sensitive interrupt here */
384	if (!(s->elcr & (1 << irq)))
385	{
386	Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
387	s->irr &= ~(1 << irq);
388	}
389	}
390
391
392	/**
393	* Get a pending interrupt.
394	*
395	* @returns Pending interrupt number.
396	* @param pDevIns Device instance of the PICs.
397	*/
398	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
399	{
400	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
401	int irq;
402	int irq2;
403	int intno;
404
405	/* read the irq from the PIC */
406	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
407	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
408
409	irq = pic_get_irq(&pThis->aPics[0]);
410	if (irq >= 0)
411	{
412	pic_intack(&pThis->aPics[0], irq);
413	if (irq == 2)
414	{
415	irq2 = pic_get_irq(&pThis->aPics[1]);
416	if (irq2 >= 0) {
417	pic_intack(&pThis->aPics[1], irq2);
418	}
419	else
420	{
421	/* spurious IRQ on slave controller (impossible) */
422	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
423	irq2 = 7;
424	}
425	intno = pThis->aPics[1].irq_base + irq2;
426	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pThis->aPics[1].irq_base, irq2));
427	irq = irq2 + 8;
428	}
429	else {
430	intno = pThis->aPics[0].irq_base + irq;
431	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pThis->aPics[0].irq_base, irq));
432	}
433	}
434	else
435	{
436	/* spurious IRQ on host controller (impossible) */
437	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
438	irq = 7;
439	intno = pThis->aPics[0].irq_base + irq;
440	}
441	pic_update_irq(pThis);
442
443	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
444
445	return intno;
446	}
447
448	static void pic_reset(PicState *s)
449	{
450	PPDMDEVINSR3 pDevInsR3 = s->pDevInsR3;
451	PPDMDEVINSR0 pDevInsR0 = s->pDevInsR0;
452	PPDMDEVINSRC pDevInsRC = s->pDevInsRC;
453	int elcr_mask = s->elcr_mask;
454	int elcr = s->elcr;
455
456	memset(s, 0, sizeof(PicState));
457
458	s->elcr = elcr;
459	s->elcr_mask = elcr_mask;
460	s->pDevInsRC = pDevInsRC;
461	s->pDevInsR0 = pDevInsR0;
462	s->pDevInsR3 = pDevInsR3;
463	}
464
465
466	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
467	{
468	PicState s = (PicState)opaque;
469	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
470	int rc = VINF_SUCCESS;
471	int priority, cmd, irq;
472
473	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
474	addr &= 1;
475	if (addr == 0) {
476	if (val & 0x10) {
477	/* init */
478	pic_reset(s);
479	/* deassert a pending interrupt */
480	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
481
482	s->init_state = 1;
483	s->init4 = val & 1;
484	if (val & 0x02)
485	AssertReleaseMsgFailed(("single mode not supported"));
486	if (val & 0x08)
487	AssertReleaseMsgFailed(("level sensitive irq not supported"));
488	} else if (val & 0x08) {
489	if (val & 0x04)
490	s->poll = 1;
491	if (val & 0x02)
492	s->read_reg_select = val & 1;
493	if (val & 0x40)
494	s->special_mask = (val >> 5) & 1;
495	} else {
496	cmd = val >> 5;
497	switch(cmd) {
498	case 0:
499	case 4:
500	s->rotate_on_auto_eoi = cmd >> 2;
501	break;
502	case 1: /* end of interrupt */
503	case 5:
504	{
505	priority = get_priority(s, s->isr);
506	if (priority != 8) {
507	irq = (priority + s->priority_add) & 7;
508	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
509	s->isr &= ~(1 << irq);
510	if (cmd == 5)
511	s->priority_add = (irq + 1) & 7;
512	rc = pic_update_irq(pThis);
513	Assert(rc == VINF_SUCCESS);
514	DumpPICState(s, "eoi");
515	}
516	break;
517	}
518	case 3:
519	{
520	irq = val & 7;
521	Log(("pic_write: EOI2 for irq %d\n", irq));
522	s->isr &= ~(1 << irq);
523	rc = pic_update_irq(pThis);
524	Assert(rc == VINF_SUCCESS);
525	DumpPICState(s, "eoi2");
526	break;
527	}
528	case 6:
529	{
530	s->priority_add = (val + 1) & 7;
531	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, s->priority_add));
532	rc = pic_update_irq(pThis);
533	Assert(rc == VINF_SUCCESS);
534	break;
535	}
536	case 7:
537	{
538	irq = val & 7;
539	Log(("pic_write: EOI3 for irq %d\n", irq));
540	s->isr &= ~(1 << irq);
541	s->priority_add = (irq + 1) & 7;
542	rc = pic_update_irq(pThis);
543	Assert(rc == VINF_SUCCESS);
544	DumpPICState(s, "eoi3");
545	break;
546	}
547	default:
548	/* no operation */
549	break;
550	}
551	}
552	} else {
553	switch(s->init_state) {
554	case 0:
555	{
556	/* normal mode */
557	pic_update_imr(pThis, s, val);
558
559	rc = pic_update_irq(pThis);
560	Assert(rc == VINF_SUCCESS);
561	break;
562	}
563	case 1:
564	s->irq_base = val & 0xf8;
565	s->init_state = 2;
566	Log(("pic_write: set irq base to %x\n", s->irq_base));
567	break;
568	case 2:
569	if (s->init4) {
570	s->init_state = 3;
571	} else {
572	s->init_state = 0;
573	}
574	break;
575	case 3:
576	s->special_fully_nested_mode = (val >> 4) & 1;
577	s->auto_eoi = (val >> 1) & 1;
578	s->init_state = 0;
579	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
580	break;
581	}
582	}
583	return rc;
584	}
585
586
587	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
588	{
589	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
590	PicState *pics = &pThis->aPics[0];
591	int ret;
592
593	ret = pic_get_irq(s);
594	if (ret >= 0) {
595	if (addr1 >> 7) {
596	Log2(("pic_poll_read: clear slave irq (isr)\n"));
597	pics[0].isr &= ~(1 << 2);
598	pics[0].irr &= ~(1 << 2);
599	}
600	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
601	s->irr &= ~(1 << ret);
602	s->isr &= ~(1 << ret);
603	if (addr1 >> 7 \|\| ret != 2)
604	pic_update_irq(pThis);
605	} else {
606	ret = 0x07;
607	pic_update_irq(pThis);
608	}
609
610	return ret;
611	}
612
613
614	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
615	{
616	PicState s = (PicState)opaque;
617	unsigned int addr;
618	int ret;
619
620	*pRC = VINF_SUCCESS;
621
622	addr = addr1;
623	addr &= 1;
624	if (s->poll) {
625	ret = pic_poll_read(s, addr1);
626	s->poll = 0;
627	} else {
628	if (addr == 0) {
629	if (s->read_reg_select)
630	ret = s->isr;
631	else
632	ret = s->irr;
633	} else {
634	ret = s->imr;
635	}
636	}
637	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
638	return ret;
639	}
640
641
642
643	#ifdef IN_RING3
644
645	static void pic_save(QEMUFile f, void opaque)
646	{
647	PicState s = (PicState)opaque;
648
649	qemu_put_8s(f, &s->last_irr);
650	qemu_put_8s(f, &s->irr);
651	qemu_put_8s(f, &s->imr);
652	qemu_put_8s(f, &s->isr);
653	qemu_put_8s(f, &s->priority_add);
654	qemu_put_8s(f, &s->irq_base);
655	qemu_put_8s(f, &s->read_reg_select);
656	qemu_put_8s(f, &s->poll);
657	qemu_put_8s(f, &s->special_mask);
658	qemu_put_8s(f, &s->init_state);
659	qemu_put_8s(f, &s->auto_eoi);
660	qemu_put_8s(f, &s->rotate_on_auto_eoi);
661	qemu_put_8s(f, &s->special_fully_nested_mode);
662	qemu_put_8s(f, &s->init4);
663	qemu_put_8s(f, &s->elcr);
664	}
665
666	static int pic_load(QEMUFile f, void opaque, int version_id)
667	{
668	PicState s = (PicState)opaque;
669
670	if (version_id != 1)
671	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
672
673	qemu_get_8s(f, &s->last_irr);
674	qemu_get_8s(f, &s->irr);
675	qemu_get_8s(f, &s->imr);
676	qemu_get_8s(f, &s->isr);
677	qemu_get_8s(f, &s->priority_add);
678	qemu_get_8s(f, &s->irq_base);
679	qemu_get_8s(f, &s->read_reg_select);
680	qemu_get_8s(f, &s->poll);
681	qemu_get_8s(f, &s->special_mask);
682	qemu_get_8s(f, &s->init_state);
683	qemu_get_8s(f, &s->auto_eoi);
684	qemu_get_8s(f, &s->rotate_on_auto_eoi);
685	qemu_get_8s(f, &s->special_fully_nested_mode);
686	qemu_get_8s(f, &s->init4);
687	qemu_get_8s(f, &s->elcr);
688	return 0;
689	}
690	#endif /* IN_RING3 */
691
692
693	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
694
695	/**
696	* Port I/O Handler for IN operations.
697	*
698	* @returns VBox status code.
699	*
700	* @param pDevIns The device instance.
701	* @param pvUser User argument - pointer to the PIC in question.
702	* @param uPort Port number used for the IN operation.
703	* @param pu32 Where to store the result.
704	* @param cb Number of bytes read.
705	*/
706	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
707	{
708	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
709	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
710
711	Assert(iPic == 0 \|\| iPic == 1);
712	if (cb == 1)
713	{
714	int rc;
715	PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_READ);
716	*pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
717	PIC_UNLOCK(pThis);
718	return rc;
719	}
720	return VERR_IOM_IOPORT_UNUSED;
721	}
722
723	/**
724	* Port I/O Handler for OUT operations.
725	*
726	* @returns VBox status code.
727	*
728	* @param pDevIns The device instance.
729	* @param pvUser User argument - pointer to the PIC in question.
730	* @param uPort Port number used for the IN operation.
731	* @param u32 The value to output.
732	* @param cb The value size in bytes.
733	*/
734	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
735	{
736	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
737	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
738
739	Assert(iPic == 0 \|\| iPic == 1);
740
741	if (cb == 1)
742	{
743	int rc;
744	PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_WRITE);
745	rc = pic_ioport_write(&pThis->aPics[iPic], Port, u32);
746	PIC_UNLOCK(pThis);
747	return rc;
748	}
749	return VINF_SUCCESS;
750	}
751
752
753	/**
754	* Port I/O Handler for IN operations.
755	*
756	* @returns VBox status code.
757	*
758	* @param pDevIns The device instance.
759	* @param pvUser User argument - pointer to the PIC in question.
760	* @param uPort Port number used for the IN operation.
761	* @param pu32 Where to store the result.
762	* @param cb Number of bytes read.
763	*/
764	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
765	{
766	if (cb == 1)
767	{
768	PicState s = (PicState)pvUser;
769	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
770	*pu32 = s->elcr;
771	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
772	return VINF_SUCCESS;
773	}
774	return VERR_IOM_IOPORT_UNUSED;
775	}
776
777	/**
778	* Port I/O Handler for OUT operations.
779	*
780	* @returns VBox status code.
781	*
782	* @param pDevIns The device instance.
783	* @param pvUser User argument - pointer to the PIC in question.
784	* @param uPort Port number used for the IN operation.
785	* @param u32 The value to output.
786	* @param cb The value size in bytes.
787	*/
788	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
789	{
790	if (cb == 1)
791	{
792	PicState s = (PicState)pvUser;
793	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
794	s->elcr = u32 & s->elcr_mask;
795	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
796	}
797	return VINF_SUCCESS;
798	}
799
800
801	#ifdef IN_RING3
802
803	#ifdef DEBUG
804	/**
805	* PIC status info callback.
806	*
807	* @param pDevIns The device instance.
808	* @param pHlp The output helpers.
809	* @param pszArgs The arguments.
810	*/
811	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
812	{
813	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
814
815	/*
816	* Show info.
817	*/
818	for (int i=0;i<2;i++)
819	{
820	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
821	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pThis->aPics[i].last_irr);
822	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pThis->aPics[i].irr);
823	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pThis->aPics[i].imr);
824	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pThis->aPics[i].isr);
825	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pThis->aPics[i].priority_add);
826	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pThis->aPics[i].irq_base);
827	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pThis->aPics[i].read_reg_select);
828	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pThis->aPics[i].poll);
829	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pThis->aPics[i].special_mask);
830	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pThis->aPics[i].init_state);
831	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pThis->aPics[i].auto_eoi);
832	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pThis->aPics[i].rotate_on_auto_eoi);
833	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pThis->aPics[i].special_fully_nested_mode);
834	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pThis->aPics[i].init4);
835	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pThis->aPics[i].elcr);
836	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pThis->aPics[i].elcr_mask);
837	}
838	}
839	#endif /* DEBUG */
840
841	/**
842	* Saves a state of the programmable interrupt controller device.
843	*
844	* @returns VBox status code.
845	* @param pDevIns The device instance.
846	* @param pSSMHandle The handle to save the state to.
847	*/
848	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
849	{
850	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
851	pic_save(pSSMHandle, &pThis->aPics[0]);
852	pic_save(pSSMHandle, &pThis->aPics[1]);
853	return VINF_SUCCESS;
854	}
855
856
857	/**
858	* Loads a saved programmable interrupt controller device state.
859	*
860	* @returns VBox status code.
861	* @param pDevIns The device instance.
862	* @param pSSMHandle The handle to the saved state.
863	* @param u32Version The data unit version number.
864	*/
865	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
866	{
867	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
868	int rc = pic_load(pSSMHandle, &pThis->aPics[0], u32Version);
869	if (RT_SUCCESS(rc))
870	rc = pic_load(pSSMHandle, &pThis->aPics[1], u32Version);
871	return rc;
872	}
873
874
875	/* -=-=-=-=-=- real code -=-=-=-=-=- */
876
877	/**
878	* Reset notification.
879	*
880	* @returns VBox status.
881	* @param pDevIns The device instance data.
882	*/
883	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
884	{
885	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
886	unsigned i;
887	LogFlow(("picReset:\n"));
888	pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
889
890	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
891	pic_reset(&pThis->aPics[i]);
892
893	PIC_UNLOCK(pThis);
894	}
895
896
897	/**
898	* @copydoc FNPDMDEVRELOCATE
899	*/
900	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
901	{
902	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
903	unsigned i;
904
905	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
906	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
907	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
908	pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
909	}
910
911
912	/**
913	* @copydoc FNPDMDEVCONSTRUCT
914	*/
915	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
916	{
917	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
918	PDMPICREG PicReg;
919	int rc;
920	bool fGCEnabled;
921	bool fR0Enabled;
922	Assert(iInstance == 0);
923
924	/*
925	* Validate and read configuration.
926	*/
927	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
928	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
929
930	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
931	if (RT_FAILURE(rc))
932	return PDMDEV_SET_ERROR(pDevIns, rc,
933	N_("Configuration error: failed to read GCEnabled as boolean"));
934
935	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
936	if (RT_FAILURE(rc))
937	return PDMDEV_SET_ERROR(pDevIns, rc,
938	N_("Configuration error: failed to read R0Enabled as boolean"));
939
940	Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
941
942	/*
943	* Init the data.
944	*/
945	Assert(RT_ELEMENTS(pThis->aPics) == 2);
946	pThis->pDevInsR3 = pDevIns;
947	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
948	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
949	pThis->aPics[0].elcr_mask = 0xf8;
950	pThis->aPics[1].elcr_mask = 0xde;
951	pThis->aPics[0].pDevInsR3 = pDevIns;
952	pThis->aPics[1].pDevInsR3 = pDevIns;
953	pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
954	pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
955	pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
956	pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
957
958	/*
959	* Register us as the PIC with PDM.
960	*/
961	PicReg.u32Version = PDM_PICREG_VERSION;
962	PicReg.pfnSetIrqR3 = picSetIrq;
963	PicReg.pfnGetInterruptR3 = picGetInterrupt;
964
965	if (fGCEnabled)
966	{
967	PicReg.pszSetIrqRC = "picSetIrq";
968	PicReg.pszGetInterruptRC = "picGetInterrupt";
969	}
970	else
971	{
972	PicReg.pszSetIrqRC = NULL;
973	PicReg.pszGetInterruptRC = NULL;
974	}
975
976	if (fR0Enabled)
977	{
978	PicReg.pszSetIrqR0 = "picSetIrq";
979	PicReg.pszGetInterruptR0 = "picGetInterrupt";
980	}
981	else
982	{
983	PicReg.pszSetIrqR0 = NULL;
984	PicReg.pszGetInterruptR0 = NULL;
985	}
986
987	Assert(pDevIns->pDevHlp->pfnPICRegister);
988	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
989	AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Vrc\n", rc), rc);
990	if (fGCEnabled)
991	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
992	if (fR0Enabled)
993	pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
994
995
996	/*
997	* Register I/O ports and save state.
998	*/
999	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
1000	if (RT_FAILURE(rc))
1001	return rc;
1002	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
1003	if (RT_FAILURE(rc))
1004	return rc;
1005	if (fGCEnabled)
1006	{
1007	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1008	if (RT_FAILURE(rc))
1009	return rc;
1010	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1011	if (RT_FAILURE(rc))
1012	return rc;
1013	}
1014	if (fR0Enabled)
1015	{
1016	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1017	if (RT_FAILURE(rc))
1018	return rc;
1019	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1020	if (RT_FAILURE(rc))
1021	return rc;
1022	}
1023
1024	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
1025	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1026	if (RT_FAILURE(rc))
1027	return rc;
1028	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
1029	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1030	if (RT_FAILURE(rc))
1031	return rc;
1032	if (fGCEnabled)
1033	{
1034	RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
1035	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
1036	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1037	if (RT_FAILURE(rc))
1038	return rc;
1039	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
1040	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1041	if (RT_FAILURE(rc))
1042	return rc;
1043	}
1044	if (fR0Enabled)
1045	{
1046	RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1047	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1048	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1049	if (RT_FAILURE(rc))
1050	return rc;
1051	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1052	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1053	if (RT_FAILURE(rc))
1054	return rc;
1055	}
1056
1057	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pThis),
1058	NULL, picSaveExec, NULL,
1059	NULL, picLoadExec, NULL);
1060	if (RT_FAILURE(rc))
1061	return rc;
1062
1063
1064	#ifdef DEBUG
1065	/*
1066	* Register the info item.
1067	*/
1068	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1069	#endif
1070
1071	/*
1072	* Initialize the device state.
1073	*/
1074	picReset(pDevIns);
1075
1076	#ifdef VBOX_WITH_STATISTICS
1077	/*
1078	* Statistics.
1079	*/
1080	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1081	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1082
1083	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1084	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1085	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1086	#endif
1087
1088	return VINF_SUCCESS;
1089	}
1090
1091
1092	/**
1093	* The device registration structure.
1094	*/
1095	const PDMDEVREG g_DeviceI8259 =
1096	{
1097	/* u32Version */
1098	PDM_DEVREG_VERSION,
1099	/* szDeviceName */
1100	"i8259",
1101	/* szGCMod */
1102	"VBoxDDGC.gc",
1103	/* szR0Mod */
1104	"VBoxDDR0.r0",
1105	/* pszDescription */
1106	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1107	/* fFlags */
1108	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1109	/* fClass */
1110	PDM_DEVREG_CLASS_PIC,
1111	/* cMaxInstances */
1112	1,
1113	/* cbInstance */
1114	sizeof(DEVPIC),
1115	/* pfnConstruct */
1116	picConstruct,
1117	/* pfnDestruct */
1118	NULL,
1119	/* pfnRelocate */
1120	picRelocate,
1121	/* pfnIOCtl */
1122	NULL,
1123	/* pfnPowerOn */
1124	NULL,
1125	/* pfnReset */
1126	picReset,
1127	/* pfnSuspend */
1128	NULL,
1129	/* pfnResume */
1130	NULL,
1131	/* pfnAttach */
1132	NULL,
1133	/* pfnDetach */
1134	NULL,
1135	/* pfnQueryInterface. */
1136	NULL
1137	};
1138
1139	#endif /* IN_RING3 */
1140	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1141

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 11264

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