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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 62966

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1/* $Id: DevDMA.cpp 62903 2016-08-03 11:03:45Z vboxsync $ */
2/** @file
3 * DevDMA - DMA Controller Device.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is loosely based on:
19 *
20 * QEMU DMA emulation
21 *
22 * Copyright (c) 2003 Vassili Karpov (malc)
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43
44/*********************************************************************************************************************************
45* Header Files *
46*********************************************************************************************************************************/
47#define LOG_GROUP LOG_GROUP_DEV_DMA
48#include <VBox/vmm/pdmdev.h>
49#include <VBox/err.h>
50
51#include <VBox/log.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54
55#include <stdio.h>
56#include <stdlib.h>
57
58#include "VBoxDD.h"
59
60
61/** @page pg_dev_dma DMA Overview and notes
62 *
63 * Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
64 * cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
65 * The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
66 * 74LS612 extends addressing to 24 bits. That leads to well known and
67 * inconvenient DMA limitations:
68 * - DMA can only access physical memory under the 16MB line
69 * - DMA transfers must occur within a 64KB/128KB 'page'
70 *
71 * The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
72 * left by one, including the control registers addresses. The DMA register
73 * offsets (except for the page registers) are therefore "double spaced".
74 *
75 * Due to the address shifting, the DMA controller decodes more addresses
76 * than are usually documented, with aliasing. See the ICH8 datasheet.
77 *
78 * In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
79 * preventing the use of memory-to-memory DMA transfers (which use channels
80 * 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
81 * However, it would transfer a single byte at a time, while the CPU can
82 * transfer two (on a 286) or four (on a 386+) bytes at a time. On many
83 * compatibles, memory-to-memory DMA is not even implemented at all, and
84 * therefore has no practical use.
85 *
86 * Auto-init mode is handled implicitly; a device's transfer handler may
87 * return an end count lower than the start count.
88 *
89 * Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
90 * while 'chidx' refers to a DMA channel index within a controller (0-3).
91 *
92 * References:
93 * - IBM Personal Computer AT Technical Reference, 1984
94 * - Intel 8237A-5 Datasheet, 1993
95 * - Frank van Gilluwe, The Undocumented PC, 1994
96 * - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
97 * - Intel ICH8 Datasheet, 2007
98 */
99
100
101/* Saved state versions. */
102#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
103#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
104
105/* State information for a single DMA channel. */
106typedef struct {
107 void *pvUser; /* User specific context. */
108 PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
109 uint16_t u16BaseAddr; /* Base address for transfers. */
110 uint16_t u16BaseCount; /* Base count for transfers. */
111 uint16_t u16CurAddr; /* Current address. */
112 uint16_t u16CurCount; /* Current count. */
113 uint8_t u8Mode; /* Channel mode. */
114} DMAChannel;
115
116/* State information for a DMA controller (DMA8 or DMA16). */
117typedef struct {
118 DMAChannel ChState[4]; /* Per-channel state. */
119 uint8_t au8Page[8]; /* Page registers (A16-A23). */
120 uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
121 uint8_t u8Command; /* Command register. */
122 uint8_t u8Status; /* Status register. */
123 uint8_t u8Mask; /* Mask register. */
124 uint8_t u8Temp; /* Temporary (mem/mem) register. */
125 uint8_t u8ModeCtr; /* Mode register counter for reads. */
126 bool fHiByte; /* Byte pointer (T/F -> high/low). */
127 uint32_t is16bit; /* True for 16-bit DMA. */
128} DMAControl;
129
130/* Complete DMA state information. */
131typedef struct {
132 PPDMDEVINS pDevIns; /* Device instance. */
133 PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
134 DMAControl DMAC[2]; /* Two DMA controllers. */
135} DMAState;
136
137/* DMA command register bits. */
138enum {
139 CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
140 CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
141 CMD_DISABLE = 0x04, /* Disable controller. */
142 CMD_COMPRTIME = 0x08, /* Compressed timing. */
143 CMD_ROTPRIO = 0x10, /* Rotating priority. */
144 CMD_EXTWR = 0x20, /* Extended write. */
145 CMD_DREQHI = 0x40, /* DREQ is active high if set. */
146 CMD_DACKHI = 0x80, /* DACK is active high if set. */
147 CMD_UNSUPPORTED = CMD_MEMTOMEM | CMD_ADRHOLD | CMD_COMPRTIME
148 | CMD_EXTWR | CMD_DREQHI | CMD_DACKHI
149};
150
151/* DMA control register offsets for read accesses. */
152enum {
153 CTL_R_STAT, /* Read status registers. */
154 CTL_R_DMAREQ, /* Read DRQ register. */
155 CTL_R_CMD, /* Read command register. */
156 CTL_R_MODE, /* Read mode register. */
157 CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
158 CTL_R_TEMP, /* Read temporary register. */
159 CTL_R_CLRMODE, /* Clear mode register counter. */
160 CTL_R_MASK /* Read all DRQ mask bits. */
161};
162
163/* DMA control register offsets for read accesses. */
164enum {
165 CTL_W_CMD, /* Write command register. */
166 CTL_W_DMAREQ, /* Write DRQ register. */
167 CTL_W_MASKONE, /* Write single DRQ mask bit. */
168 CTL_W_MODE, /* Write mode register. */
169 CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
170 CTL_W_MASTRCLR, /* Master clear. */
171 CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
172 CTL_W_MASK /* Write all DRQ mask bits. */
173};
174
175/* DMA transfer modes. */
176enum {
177 DMODE_DEMAND, /* Demand transfer mode. */
178 DMODE_SINGLE, /* Single transfer mode. */
179 DMODE_BLOCK, /* Block transfer mode. */
180 DMODE_CASCADE /* Cascade mode. */
181};
182
183/* DMA transfer types. */
184enum {
185 DTYPE_VERIFY, /* Verify transfer type. */
186 DTYPE_WRITE, /* Write transfer type. */
187 DTYPE_READ, /* Read transfer type. */
188 DTYPE_ILLEGAL /* Undefined. */
189};
190
191/* Convert DMA channel number (0-7) to controller number (0-1). */
192#define DMACH2C(c) (c < 4 ? 0 : 1)
193
194static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
195/* Map a DMA page register offset (0-7) to channel index (0-3). */
196#define DMAPG2CX(c) (dmaChannelMap[c])
197
198static int dmaMapChannel[4] = {7, 3, 1, 2};
199/* Map a channel index (0-3) to DMA page register offset (0-7). */
200#define DMACX2PG(c) (dmaMapChannel[c])
201/* Map a channel number (0-7) to DMA page register offset (0-7). */
202#define DMACH2PG(c) (dmaMapChannel[c & 3])
203
204/* Test the decrement bit of mode register. */
205#define IS_MODE_DEC(c) ((c) & 0x20)
206/* Test the auto-init bit of mode register. */
207#define IS_MODE_AI(c) ((c) & 0x10)
208/* Extract the transfer type bits of mode register. */
209#define GET_MODE_XTYP(c)(((c) & 0x0c) >> 2)
210
211
212/* Perform a master clear (reset) on a DMA controller. */
213static void dmaClear(DMAControl *dc)
214{
215 dc->u8Command = 0;
216 dc->u8Status = 0;
217 dc->u8Temp = 0;
218 dc->u8ModeCtr = 0;
219 dc->fHiByte = false;
220 dc->u8Mask = UINT8_MAX;
221}
222
223
224/** Read the byte pointer and flip it. */
225DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
226{
227 bool bHighByte;
228
229 bHighByte = !!dc->fHiByte;
230 dc->fHiByte ^= 1;
231 return bHighByte;
232}
233
234
235/* DMA address registers writes and reads. */
236
237/**
238 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
239 */
240static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
241{
242 RT_NOREF(pDevIns);
243 if (cb == 1)
244 {
245 DMAControl *dc = (DMAControl *)pvUser;
246 DMAChannel *ch;
247 int chidx, reg, is_count;
248
249 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
250 reg = (port >> dc->is16bit) & 0x0f;
251 chidx = reg >> 1;
252 is_count = reg & 1;
253 ch = &dc->ChState[chidx];
254 if (dmaReadBytePtr(dc))
255 {
256 /* Write the high byte. */
257 if (is_count)
258 ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
259 else
260 ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
261
262 ch->u16CurCount = 0;
263 ch->u16CurAddr = ch->u16BaseAddr;
264 }
265 else
266 {
267 /* Write the low byte. */
268 if (is_count)
269 ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
270 else
271 ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
272 }
273 Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
274 port, chidx, u32));
275 }
276 else
277 {
278 /* Likely a guest bug. */
279 Log(("Bad size write to count register %#x (size %d, data %#x)\n",
280 port, cb, u32));
281 }
282 return VINF_SUCCESS;
283}
284
285
286/**
287 * @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
288 */
289static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
290{
291 RT_NOREF(pDevIns);
292 if (cb == 1)
293 {
294 DMAControl *dc = (DMAControl *)pvUser;
295 DMAChannel *ch;
296 int chidx, reg, val, dir;
297 int bptr;
298
299 reg = (port >> dc->is16bit) & 0x0f;
300 chidx = reg >> 1;
301 ch = &dc->ChState[chidx];
302
303 dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
304 if (reg & 1)
305 val = ch->u16BaseCount - ch->u16CurCount;
306 else
307 val = ch->u16CurAddr + ch->u16CurCount * dir;
308
309 bptr = dmaReadBytePtr(dc);
310 *pu32 = RT_LOBYTE(val >> (bptr * 8));
311
312 Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
313 return VINF_SUCCESS;
314 }
315 return VERR_IOM_IOPORT_UNUSED;
316}
317
318/* DMA control registers writes and reads. */
319
320/**
321 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
322 */
323static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
324{
325 RT_NOREF(pDevIns);
326 if (cb == 1)
327 {
328 DMAControl *dc = (DMAControl *)pvUser;
329 int chidx = 0;
330 int reg;
331
332 reg = ((port >> dc->is16bit) & 0x0f) - 8;
333 Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
334 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
335
336 switch (reg) {
337 case CTL_W_CMD:
338 /* Unsupported commands are entirely ignored. */
339 if (u32 & CMD_UNSUPPORTED)
340 {
341 Log(("DMA command %#x is not supported, ignoring!\n", u32));
342 break;
343 }
344 dc->u8Command = u32;
345 break;
346 case CTL_W_DMAREQ:
347 chidx = u32 & 3;
348 if (u32 & 4)
349 dc->u8Status |= 1 << (chidx + 4);
350 else
351 dc->u8Status &= ~(1 << (chidx + 4));
352 dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
353 break;
354 case CTL_W_MASKONE:
355 chidx = u32 & 3;
356 if (u32 & 4)
357 dc->u8Mask |= 1 << chidx;
358 else
359 dc->u8Mask &= ~(1 << chidx);
360 break;
361 case CTL_W_MODE:
362 {
363 int op, opmode;
364
365 chidx = u32 & 3;
366 op = (u32 >> 2) & 3;
367 opmode = (u32 >> 6) & 3;
368 Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
369 chidx, op, IS_MODE_AI(u32) ? "" : "no ",
370 IS_MODE_DEC(u32) ? "de" : "in", opmode));
371
372 dc->ChState[chidx].u8Mode = u32;
373 break;
374 }
375 case CTL_W_CLRBPTR:
376 dc->fHiByte = false;
377 break;
378 case CTL_W_MASTRCLR:
379 dmaClear(dc);
380 break;
381 case CTL_W_CLRMASK:
382 dc->u8Mask = 0;
383 break;
384 case CTL_W_MASK:
385 dc->u8Mask = u32;
386 break;
387 default:
388 Assert(0);
389 break;
390 }
391 Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
392 port, chidx, u32));
393 }
394 else
395 {
396 /* Likely a guest bug. */
397 Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
398 port, cb, u32));
399 }
400 return VINF_SUCCESS;
401}
402
403
404/**
405 * @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
406 */
407static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
408{
409 RT_NOREF(pDevIns);
410 if (cb == 1)
411 {
412 DMAControl *dc = (DMAControl *)pvUser;
413 uint8_t val = 0;
414 int reg;
415
416 reg = ((port >> dc->is16bit) & 0x0f) - 8;
417 Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
418
419 switch (reg)
420 {
421 case CTL_R_STAT:
422 val = dc->u8Status;
423 dc->u8Status &= 0xf0; /* A read clears all TCs. */
424 break;
425 case CTL_R_DMAREQ:
426 val = (dc->u8Status >> 4) | 0xf0;
427 break;
428 case CTL_R_CMD:
429 val = dc->u8Command;
430 break;
431 case CTL_R_MODE:
432 val = dc->ChState[dc->u8ModeCtr].u8Mode | 3;
433 dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
434 case CTL_R_SETBPTR:
435 dc->fHiByte = true;
436 break;
437 case CTL_R_TEMP:
438 val = dc->u8Temp;
439 break;
440 case CTL_R_CLRMODE:
441 dc->u8ModeCtr = 0;
442 break;
443 case CTL_R_MASK:
444 val = dc->u8Mask;
445 break;
446 default:
447 Assert(0);
448 break;
449 }
450
451 Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
452 *pu32 = val;
453
454 return VINF_SUCCESS;
455 }
456 return VERR_IOM_IOPORT_UNUSED;
457}
458
459/**
460 */
461
462/**
463 * @callback_method_impl{FNIOMIOPORTIN,
464 * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
465 *
466 * There are 16 R/W page registers for compatibility with the IBM PC/AT; only
467 * some of those registers are used for DMA. The page register accessible via
468 * port 80h may be read to insert small delays or used as a scratch register by
469 * a BIOS.
470 */
471static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
472{
473 RT_NOREF(pDevIns);
474 DMAControl *dc = (DMAControl *)pvUser;
475 int reg;
476
477 if (cb == 1)
478 {
479 reg = port & 7;
480 *pu32 = dc->au8Page[reg];
481 Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
482 *pu32, port, DMAPG2CX(reg)));
483 return VINF_SUCCESS;
484 }
485
486 if (cb == 2)
487 {
488 reg = port & 7;
489 *pu32 = dc->au8Page[reg] | (dc->au8Page[(reg + 1) & 7] << 8);
490 Log2(("Read %#x (word) from page register %#x (channel %d)\n",
491 *pu32, port, DMAPG2CX(reg)));
492 return VINF_SUCCESS;
493 }
494
495 return VERR_IOM_IOPORT_UNUSED;
496}
497
498
499/**
500 * @callback_method_impl{FNIOMIOPORTOUT,
501 * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
502 */
503static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
504{
505 RT_NOREF(pDevIns);
506 DMAControl *dc = (DMAControl *)pvUser;
507 int reg;
508
509 if (cb == 1)
510 {
511 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
512 reg = port & 7;
513 dc->au8Page[reg] = u32;
514 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
515 Log2(("Wrote %#x to page register %#x (channel %d)\n",
516 u32, port, DMAPG2CX(reg)));
517 }
518 else if (cb == 2)
519 {
520 Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
521 reg = port & 7;
522 dc->au8Page[reg] = u32;
523 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
524 reg = (port + 1) & 7;
525 dc->au8Page[reg] = u32 >> 8;
526 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
527 }
528 else
529 {
530 /* Likely a guest bug. */
531 Log(("Bad size write to page register %#x (size %d, data %#x)\n",
532 port, cb, u32));
533 }
534 return VINF_SUCCESS;
535}
536
537
538/**
539 * @callback_method_impl{FNIOMIOPORTIN,
540 * EISA style high page registers, for extending the DMA addresses to cover
541 * the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
542 */
543static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
544{
545 RT_NOREF(pDevIns);
546 if (cb == 1)
547 {
548 DMAControl *dc = (DMAControl *)pvUser;
549 int reg;
550
551 reg = port & 7;
552 *pu32 = dc->au8PageHi[reg];
553 Log2(("Read %#x to from high page register %#x (channel %d)\n",
554 *pu32, port, DMAPG2CX(reg)));
555 return VINF_SUCCESS;
556 }
557 return VERR_IOM_IOPORT_UNUSED;
558}
559
560
561/**
562 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
563 */
564static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
565{
566 RT_NOREF(pDevIns);
567 if (cb == 1)
568 {
569 DMAControl *dc = (DMAControl *)pvUser;
570 int reg;
571
572 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
573 reg = port & 7;
574 dc->au8PageHi[reg] = u32;
575 Log2(("Wrote %#x to high page register %#x (channel %d)\n",
576 u32, port, DMAPG2CX(reg)));
577 }
578 else
579 {
580 /* Likely a guest bug. */
581 Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
582 port, cb, u32));
583 }
584 return VINF_SUCCESS;
585}
586
587/** Perform any pending transfers on a single DMA channel. */
588static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
589{
590 DMAControl *dc = &pThis->DMAC[ctlidx];
591 DMAChannel *ch = &dc->ChState[chidx];
592 uint32_t start_cnt, end_cnt;
593 int opmode;
594
595 opmode = (ch->u8Mode >> 6) & 3;
596
597 Log3(("DMA address %screment, mode %d\n",
598 IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
599 ch->u8Mode >> 6));
600
601 /* Addresses and counts are shifted for 16-bit channels. */
602 start_cnt = ch->u16CurCount << dc->is16bit;
603 /* NB: The device is responsible for examining the DMA mode and not
604 * transferring more than it should if auto-init is not in use.
605 */
606 end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
607 start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
608 ch->u16CurCount = end_cnt >> dc->is16bit;
609 /* Set the TC (Terminal Count) bit if transfer was completed. */
610 if (ch->u16CurCount == ch->u16BaseCount + 1)
611 switch (opmode)
612 {
613 case DMODE_DEMAND:
614 case DMODE_SINGLE:
615 case DMODE_BLOCK:
616 dc->u8Status |= RT_BIT(chidx);
617 Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
618 break;
619 default:
620 break;
621 }
622 Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
623}
624
625/**
626 * @interface_method_impl{PDMDMAREG,pfnRun}
627 */
628static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
629{
630 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
631 DMAControl *dc;
632 int ctlidx, chidx, mask;
633 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
634
635 /* Run all controllers and channels. */
636 for (ctlidx = 0; ctlidx < 2; ++ctlidx)
637 {
638 dc = &pThis->DMAC[ctlidx];
639
640 /* If controller is disabled, don't even bother. */
641 if (dc->u8Command & CMD_DISABLE)
642 continue;
643
644 for (chidx = 0; chidx < 4; ++chidx)
645 {
646 mask = 1 << chidx;
647 if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
648 dmaRunChannel(pThis, ctlidx, chidx);
649 }
650 }
651
652 PDMCritSectLeave(pDevIns->pCritSectRoR3);
653 return 0;
654}
655
656/**
657 * @interface_method_impl{PDMDMAREG,pfnRegister}
658 */
659static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
660 PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
661{
662 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
663 DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
664
665 LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
666
667 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
668 ch->pfnXferHandler = pfnTransferHandler;
669 ch->pvUser = pvUser;
670 PDMCritSectLeave(pDevIns->pCritSectRoR3);
671}
672
673/** Reverse the order of bytes in a memory buffer. */
674static void dmaReverseBuf8(void *buf, unsigned len)
675{
676 uint8_t *pBeg, *pEnd;
677 uint8_t temp;
678
679 pBeg = (uint8_t *)buf;
680 pEnd = pBeg + len - 1;
681 for (len = len / 2; len; --len)
682 {
683 temp = *pBeg;
684 *pBeg++ = *pEnd;
685 *pEnd-- = temp;
686 }
687}
688
689/** Reverse the order of words in a memory buffer. */
690static void dmaReverseBuf16(void *buf, unsigned len)
691{
692 uint16_t *pBeg, *pEnd;
693 uint16_t temp;
694
695 Assert(!(len & 1));
696 len /= 2; /* Convert to word count. */
697 pBeg = (uint16_t *)buf;
698 pEnd = pBeg + len - 1;
699 for (len = len / 2; len; --len)
700 {
701 temp = *pBeg;
702 *pBeg++ = *pEnd;
703 *pEnd-- = temp;
704 }
705}
706
707/**
708 * @interface_method_impl{PDMDMAREG,pfnReadMemory}
709 */
710static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
711 void *pvBuffer, uint32_t off, uint32_t cbBlock)
712{
713 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
714 DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
715 DMAChannel *ch = &dc->ChState[uChannel & 3];
716 uint32_t page, pagehi;
717 uint32_t addr;
718
719 LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
720
721 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
722
723 /* Build the address for this transfer. */
724 page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
725 pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
726 addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
727
728 if (IS_MODE_DEC(ch->u8Mode))
729 {
730 PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
731 if (dc->is16bit)
732 dmaReverseBuf16(pvBuffer, cbBlock);
733 else
734 dmaReverseBuf8(pvBuffer, cbBlock);
735 }
736 else
737 PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
738
739 PDMCritSectLeave(pDevIns->pCritSectRoR3);
740 return cbBlock;
741}
742
743/**
744 * @interface_method_impl{PDMDMAREG,pfnWriteMemory}
745 */
746static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
747 const void *pvBuffer, uint32_t off, uint32_t cbBlock)
748{
749 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
750 DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
751 DMAChannel *ch = &dc->ChState[uChannel & 3];
752 uint32_t page, pagehi;
753 uint32_t addr;
754
755 LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
756 if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
757 {
758 Log(("DMA verify transfer, ignoring write.\n"));
759 return cbBlock;
760 }
761
762 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
763
764 /* Build the address for this transfer. */
765 page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
766 pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
767 addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
768
769 if (IS_MODE_DEC(ch->u8Mode))
770 {
771 //@todo: This would need a temporary buffer.
772 Assert(0);
773#if 0
774 if (dc->is16bit)
775 dmaReverseBuf16(pvBuffer, cbBlock);
776 else
777 dmaReverseBuf8(pvBuffer, cbBlock);
778#endif
779 PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
780 }
781 else
782 PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
783
784 PDMCritSectLeave(pDevIns->pCritSectRoR3);
785 return cbBlock;
786}
787
788/**
789 * @interface_method_impl{PDMDMAREG,pfnSetDREQ}
790 */
791static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
792{
793 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
794 DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
795 int chidx;
796
797 LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
798
799 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
800 chidx = uChannel & 3;
801 if (uLevel)
802 dc->u8Status |= 1 << (chidx + 4);
803 else
804 dc->u8Status &= ~(1 << (chidx + 4));
805 PDMCritSectLeave(pDevIns->pCritSectRoR3);
806}
807
808/**
809 * @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
810 */
811static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
812{
813 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
814
815 LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
816
817 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
818 uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
819 PDMCritSectLeave(pDevIns->pCritSectRoR3);
820 return u8Mode;
821}
822
823
824/**
825 * @interface_method_impl{PDMDEVREG,pfnReset}
826 */
827static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
828{
829 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
830
831 LogFlow(("dmaReset: pThis=%p\n", pThis));
832
833 /* NB: The page and address registers are unaffected by a reset
834 * and in an undefined state after power-up.
835 */
836 dmaClear(&pThis->DMAC[0]);
837 dmaClear(&pThis->DMAC[1]);
838}
839
840/** Register DMA I/O port handlers. */
841static void dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
842{
843 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
844 DMAControl *dc8 = &pThis->DMAC[0];
845 DMAControl *dc16 = &pThis->DMAC[1];
846
847 dc8->is16bit = false;
848 dc16->is16bit = true;
849
850 /* Base and current address for each channel. */
851 PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
852 PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
853
854 /* Control registers for both DMA controllers. */
855 PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
856 PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
857
858 /* Page registers for each channel (plus a few unused ones). */
859 PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
860 PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
861
862 /* Optional EISA style high page registers (address bits 24-31). */
863 if (fHighPage)
864 {
865 PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
866 PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
867 }
868}
869
870static void dmaSaveController(PSSMHANDLE pSSM, DMAControl *dc)
871{
872 int chidx;
873
874 /* Save controller state... */
875 SSMR3PutU8(pSSM, dc->u8Command);
876 SSMR3PutU8(pSSM, dc->u8Mask);
877 SSMR3PutU8(pSSM, dc->fHiByte);
878 SSMR3PutU32(pSSM, dc->is16bit);
879 SSMR3PutU8(pSSM, dc->u8Status);
880 SSMR3PutU8(pSSM, dc->u8Temp);
881 SSMR3PutU8(pSSM, dc->u8ModeCtr);
882 SSMR3PutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
883 SSMR3PutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
884
885 /* ...and all four of its channels. */
886 for (chidx = 0; chidx < 4; ++chidx)
887 {
888 DMAChannel *ch = &dc->ChState[chidx];
889
890 SSMR3PutU16(pSSM, ch->u16CurAddr);
891 SSMR3PutU16(pSSM, ch->u16CurCount);
892 SSMR3PutU16(pSSM, ch->u16BaseAddr);
893 SSMR3PutU16(pSSM, ch->u16BaseCount);
894 SSMR3PutU8(pSSM, ch->u8Mode);
895 }
896}
897
898static int dmaLoadController(PSSMHANDLE pSSM, DMAControl *dc, int version)
899{
900 uint8_t u8val;
901 uint32_t u32val;
902 int chidx;
903
904 SSMR3GetU8(pSSM, &dc->u8Command);
905 SSMR3GetU8(pSSM, &dc->u8Mask);
906 SSMR3GetU8(pSSM, &u8val);
907 dc->fHiByte = !!u8val;
908 SSMR3GetU32(pSSM, &dc->is16bit);
909 if (version > DMA_SAVESTATE_OLD)
910 {
911 SSMR3GetU8(pSSM, &dc->u8Status);
912 SSMR3GetU8(pSSM, &dc->u8Temp);
913 SSMR3GetU8(pSSM, &dc->u8ModeCtr);
914 SSMR3GetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
915 SSMR3GetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
916 }
917
918 for (chidx = 0; chidx < 4; ++chidx)
919 {
920 DMAChannel *ch = &dc->ChState[chidx];
921
922 if (version == DMA_SAVESTATE_OLD)
923 {
924 /* Convert from 17-bit to 16-bit format. */
925 SSMR3GetU32(pSSM, &u32val);
926 ch->u16CurAddr = u32val >> dc->is16bit;
927 SSMR3GetU32(pSSM, &u32val);
928 ch->u16CurCount = u32val >> dc->is16bit;
929 }
930 else
931 {
932 SSMR3GetU16(pSSM, &ch->u16CurAddr);
933 SSMR3GetU16(pSSM, &ch->u16CurCount);
934 }
935 SSMR3GetU16(pSSM, &ch->u16BaseAddr);
936 SSMR3GetU16(pSSM, &ch->u16BaseCount);
937 SSMR3GetU8(pSSM, &ch->u8Mode);
938 /* Convert from old save state. */
939 if (version == DMA_SAVESTATE_OLD)
940 {
941 /* Remap page register contents. */
942 SSMR3GetU8(pSSM, &u8val);
943 dc->au8Page[DMACX2PG(chidx)] = u8val;
944 SSMR3GetU8(pSSM, &u8val);
945 dc->au8PageHi[DMACX2PG(chidx)] = u8val;
946 /* Throw away dack, eop. */
947 SSMR3GetU8(pSSM, &u8val);
948 SSMR3GetU8(pSSM, &u8val);
949 }
950 }
951 return 0;
952}
953
954/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
955static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
956{
957 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
958
959 dmaSaveController(pSSM, &pThis->DMAC[0]);
960 dmaSaveController(pSSM, &pThis->DMAC[1]);
961 return VINF_SUCCESS;
962}
963
964/** @callback_method_impl{FNSSMDEVLOADEXEC} */
965static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
966{
967 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
968
969 AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
970 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
971
972 dmaLoadController(pSSM, &pThis->DMAC[0], uVersion);
973 return dmaLoadController(pSSM, &pThis->DMAC[1], uVersion);
974}
975
976/**
977 * @interface_method_impl{PDMDEVREG,pfnConstruct}
978 */
979static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
980{
981 RT_NOREF(iInstance);
982 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *);
983
984 /*
985 * Initialize data.
986 */
987 pThis->pDevIns = pDevIns;
988
989 /*
990 * Validate configuration.
991 */
992 if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
993 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
994
995 bool bHighPage = false;
996#if 0
997 rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
998 if (RT_FAILURE (rc))
999 return rc;
1000#endif
1001
1002 dmaIORegister(pDevIns, bHighPage);
1003 dmaReset(pDevIns);
1004
1005 PDMDMACREG Reg;
1006 Reg.u32Version = PDM_DMACREG_VERSION;
1007 Reg.pfnRun = dmaRun;
1008 Reg.pfnRegister = dmaRegister;
1009 Reg.pfnReadMemory = dmaReadMemory;
1010 Reg.pfnWriteMemory = dmaWriteMemory;
1011 Reg.pfnSetDREQ = dmaSetDREQ;
1012 Reg.pfnGetChannelMode = dmaGetChannelMode;
1013
1014 int rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
1015 if (RT_FAILURE (rc))
1016 return rc;
1017
1018 rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
1019 if (RT_FAILURE(rc))
1020 return rc;
1021
1022 return VINF_SUCCESS;
1023}
1024
1025/**
1026 * The device registration structure.
1027 */
1028const PDMDEVREG g_DeviceDMA =
1029{
1030 /* u32Version */
1031 PDM_DEVREG_VERSION,
1032 /* szName */
1033 "8237A",
1034 /* szRCMod */
1035 "",
1036 /* szR0Mod */
1037 "",
1038 /* pszDescription */
1039 "DMA Controller Device",
1040 /* fFlags */
1041 PDM_DEVREG_FLAGS_DEFAULT_BITS,
1042 /* fClass */
1043 PDM_DEVREG_CLASS_DMA,
1044 /* cMaxInstances */
1045 1,
1046 /* cbInstance */
1047 sizeof(DMAState),
1048 /* pfnConstruct */
1049 dmaConstruct,
1050 /* pfnDestruct */
1051 NULL,
1052 /* pfnRelocate */
1053 NULL,
1054 /* pfnMemSetup */
1055 NULL,
1056 /* pfnPowerOn */
1057 NULL,
1058 /* pfnReset */
1059 dmaReset,
1060 /* pfnSuspend */
1061 NULL,
1062 /* pfnResume */
1063 NULL,
1064 /* pfnAttach */
1065 NULL,
1066 /* pfnDetach */
1067 NULL,
1068 /* pfnQueryInterface. */
1069 NULL,
1070 /* pfnInitComplete */
1071 NULL,
1072 /* pfnPowerOff */
1073 NULL,
1074 /* pfnSoftReset */
1075 NULL,
1076 /* u32VersionEnd */
1077 PDM_DEVREG_VERSION
1078};
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