DevAPIC.cpp@ 42537

最後變更在這個檔案從42537是 42537,由 vboxsync 提交於 13 年前
Devices/PC/DevAPIC: disabled an assertion for myself.
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1	/* $Id: DevAPIC.cpp 42537 2012-08-02 13:25:13Z vboxsync $ */
2	/** @file
3	* Advanced Programmable Interrupt Controller (APIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* apic.c revision 1.5 @@OSETODO
21	*
22	* APIC support
23	*
24	* Copyright (c) 2004-2005 Fabrice Bellard
25	*
26	* This library is free software; you can redistribute it and/or
27	* modify it under the terms of the GNU Lesser General Public
28	* License as published by the Free Software Foundation; either
29	* version 2 of the License, or (at your option) any later version.
30	*
31	* This library is distributed in the hope that it will be useful,
32	* but WITHOUT ANY WARRANTY; without even the implied warranty of
33	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34	* Lesser General Public License for more details.
35	*
36	* You should have received a copy of the GNU Lesser General Public
37	* License along with this library; if not, write to the Free Software
38	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39	*/
40
41	/*******************************************************************************
42	* Header Files *
43	*******************************************************************************/
44	#define LOG_GROUP LOG_GROUP_DEV_APIC
45	#include <VBox/vmm/pdmdev.h>
46
47	#include <VBox/log.h>
48	#include <VBox/vmm/stam.h>
49	#include <VBox/vmm/vmcpuset.h>
50	#include <iprt/asm.h>
51	#include <iprt/assert.h>
52
53	#include <VBox/msi.h>
54
55	#include "VBoxDD2.h"
56	#include "DevApic.h"
57
58
59	/*******************************************************************************
60	* Defined Constants And Macros *
61	*******************************************************************************/
62	#define MSR_IA32_APICBASE 0x1b
63	#define MSR_IA32_APICBASE_BSP (1<<8)
64	#define MSR_IA32_APICBASE_ENABLE (1<<11)
65	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
66	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
67
68	#ifdef _MSC_VER
69	# pragma warning(disable:4244)
70	#endif
71
72	/** The current saved state version.*/
73	#define APIC_SAVED_STATE_VERSION 3
74	/** The saved state version used by VirtualBox v3 and earlier.
75	* This does not include the config. */
76	#define APIC_SAVED_STATE_VERSION_VBOX_30 2
77	/** Some ancient version... */
78	#define APIC_SAVED_STATE_VERSION_ANCIENT 1
79
80	/* version 0x14: Pentium 4, Xeon; LVT count depends on that */
81	#define APIC_HW_VERSION 0x14
82
83	/** @def APIC_LOCK
84	* Acquires the PDM lock. */
85	#define APIC_LOCK(a_pDev, rcBusy) \
86	do { \
87	int rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
88	if (rc2 != VINF_SUCCESS) \
89	return rc2; \
90	} while (0)
91
92	/** @def APIC_LOCK_VOID
93	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
94	#define APIC_LOCK_VOID(a_pDev, rcBusy) \
95	do { \
96	int rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
97	AssertLogRelRCReturnVoid(rc2); \
98	} while (0)
99
100	/** @def APIC_UNLOCK
101	* Releases the PDM lock. */
102	#define APIC_UNLOCK(a_pDev) \
103	PDMCritSectLeave((a_pDev)->CTX_SUFF(pCritSect))
104
105	/** @def APIC_AND_TM_LOCK
106	* Acquires the virtual sync clock lock as well as the PDM lock. */
107	#define APIC_AND_TM_LOCK(a_pDev, a_pAcpi, rcBusy) \
108	do { \
109	int rc2 = TMTimerLock((a_pAcpi)->CTX_SUFF(pTimer), (rcBusy)); \
110	if (rc2 != VINF_SUCCESS) \
111	return rc2; \
112	rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
113	if (rc2 != VINF_SUCCESS) \
114	{ \
115	TMTimerUnlock((a_pAcpi)->CTX_SUFF(pTimer)); \
116	return rc2; \
117	} \
118	} while (0)
119
120	/** @def APIC_AND_TM_UNLOCK
121	* Releases the PDM lock as well as the TM virtual sync clock lock. */
122	#define APIC_AND_TM_UNLOCK(a_pDev, a_pAcpi) \
123	do { \
124	TMTimerUnlock((a_pAcpi)->CTX_SUFF(pTimer)); \
125	PDMCritSectLeave((a_pDev)->CTX_SUFF(pCritSect)); \
126	} while (0)
127
128	/**
129	* Begins an APIC enumeration block.
130	*
131	* Code placed between this and the APIC_FOREACH_END macro will be executed for
132	* each APIC instance present in the system.
133	*
134	* @param a_pDev The APIC device.
135	*/
136	#define APIC_FOREACH_BEGIN(a_pDev) \
137	do { \
138	VMCPUID const cApics = (a_pDev)->cCpus; \
139	APICState *pCurApic = (a_pDev)->CTX_SUFF(paLapics); \
140	for (VMCPUID iCurApic = 0; iCurApic < cApics; iCurApic++, pCurApic++) \
141	{ \
142	do { } while (0)
143
144	/**
145	* Begins an APIC enumeration block, given a destination set.
146	*
147	* Code placed between this and the APIC_FOREACH_END macro will be executed for
148	* each APIC instance present in @a a_pDstSet.
149	*
150	* @param a_pDev The APIC device.
151	* @param a_pDstSet The destination set.
152	*/
153	#define APIC_FOREACH_IN_SET_BEGIN(a_pDev, a_pDstSet) \
154	APIC_FOREACH_BEGIN(a_pDev); \
155	if (!VMCPUSET_IS_PRESENT((a_pDstSet), iCurApic)) \
156	continue; \
157	do { } while (0)
158
159
160	/** Counterpart to APIC_FOREACH_IN_SET_BEGIN and APIC_FOREACH_BEGIN. */
161	#define APIC_FOREACH_END() \
162	} \
163	} while (0)
164
165	#define DEBUG_APIC
166
167	/* APIC Local Vector Table */
168	#define APIC_LVT_TIMER 0
169	#define APIC_LVT_THERMAL 1
170	#define APIC_LVT_PERFORM 2
171	#define APIC_LVT_LINT0 3
172	#define APIC_LVT_LINT1 4
173	#define APIC_LVT_ERROR 5
174	#define APIC_LVT_NB 6
175
176	/* APIC delivery modes */
177	#define APIC_DM_FIXED 0
178	#define APIC_DM_LOWPRI 1
179	#define APIC_DM_SMI 2
180	#define APIC_DM_NMI 4
181	#define APIC_DM_INIT 5
182	#define APIC_DM_SIPI 6
183	#define APIC_DM_EXTINT 7
184
185	/* APIC destination mode */
186	#define APIC_DESTMODE_FLAT 0xf
187	#define APIC_DESTMODE_CLUSTER 0x0
188
189	#define APIC_TRIGGER_EDGE 0
190	#define APIC_TRIGGER_LEVEL 1
191
192	#define APIC_LVT_TIMER_PERIODIC (1<<17)
193	#define APIC_LVT_MASKED (1<<16)
194	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
195	#define APIC_LVT_REMOTE_IRR (1<<14)
196	#define APIC_INPUT_POLARITY (1<<13)
197	#define APIC_SEND_PENDING (1<<12)
198
199	#define ESR_ILLEGAL_ADDRESS (1 << 7)
200
201	#define APIC_SV_ENABLE (1 << 8)
202
203	#define APIC_MAX_PATCH_ATTEMPTS 100
204
205	typedef uint32_t PhysApicId;
206	typedef uint32_t LogApicId;
207
208
209	/*******************************************************************************
210	* Structures and Typedefs *
211	*******************************************************************************/
212	typedef struct APIC256BITREG
213	{
214	/** The bitmap data. */
215	uint32_t au32Bitmap[8 /256/32/];
216	} APIC256BITREG;
217	typedef APIC256BITREG *PAPIC256BITREG;
218	typedef APIC256BITREG const *PCAPIC256BITREG;
219
220	/**
221	* Tests if a bit in the 256-bit APIC register is set.
222	*
223	* @returns true if set, false if clear.
224	*
225	* @param pReg The register.
226	* @param iBit The bit to test for.
227	*/
228	DECLINLINE(bool) Apic256BitReg_IsBitSet(PCAPIC256BITREG pReg, unsigned iBit)
229	{
230	Assert(iBit < 256);
231	return ASMBitTest(&pReg->au32Bitmap[0], iBit);
232	}
233
234
235	/**
236	* Sets a bit in the 256-bit APIC register is set.
237	*
238	* @param pReg The register.
239	* @param iBit The bit to set.
240	*/
241	DECLINLINE(void) Apic256BitReg_SetBit(PAPIC256BITREG pReg, unsigned iBit)
242	{
243	Assert(iBit < 256);
244	return ASMBitSet(&pReg->au32Bitmap[0], iBit);
245	}
246
247
248	/**
249	* Clears a bit in the 256-bit APIC register is set.
250	*
251	* @param pReg The register.
252	* @param iBit The bit to clear.
253	*/
254	DECLINLINE(void) Apic256BitReg_ClearBit(PAPIC256BITREG pReg, unsigned iBit)
255	{
256	Assert(iBit < 256);
257	return ASMBitClear(&pReg->au32Bitmap[0], iBit);
258	}
259
260	/**
261	* Clears all bits in the 256-bit APIC register set.
262	*
263	* @param pReg The register.
264	*/
265	DECLINLINE(void) Apic256BitReg_Empty(PAPIC256BITREG pReg)
266	{
267	memset(&pReg->au32Bitmap[0], 0, sizeof(pReg->au32Bitmap));
268	}
269
270	/**
271	* Finds the last bit set in the register, i.e. the highest priority interrupt.
272	*
273	* @returns The index of the found bit, @a iRetAllClear if none was found.
274	*
275	* @param pReg The register.
276	* @param iRetAllClear What to return if all bits are clear.
277	*/
278	static int Apic256BitReg_FindLastSetBit(PCAPIC256BITREG pReg, int iRetAllClear)
279	{
280	uint32_t i = RT_ELEMENTS(pReg->au32Bitmap);
281	while (i-- > 0)
282	{
283	uint32_t u = pReg->au32Bitmap[i];
284	if (u)
285	{
286	u = ASMBitLastSetU32(u);
287	u--;
288	u \|= i << 5;
289	return (int)u;
290	}
291	}
292	return iRetAllClear;
293	}
294
295
296	typedef struct APICState
297	{
298	uint32_t apicbase;
299	/* Task priority register (interrupt level) */
300	uint32_t tpr;
301	/* Logical APIC id - user programmable */
302	LogApicId id;
303	/* Physical APIC id - not visible to user, constant */
304	PhysApicId phys_id;
305	/** @todo: is it logical or physical? Not really used anyway now. */
306	PhysApicId arb_id;
307	uint32_t spurious_vec;
308	uint8_t log_dest;
309	uint8_t dest_mode;
310	APIC256BITREG isr; /*< in service register /
311	APIC256BITREG tmr; /*< trigger mode register /
312	APIC256BITREG irr; /*< interrupt request register /
313	uint32_t lvt[APIC_LVT_NB];
314	uint32_t esr; /* error register */
315	uint32_t icr[2];
316	uint32_t divide_conf;
317	int count_shift;
318	uint32_t initial_count;
319	uint32_t Alignment0;
320
321	/** The time stamp of the initial_count load, i.e. when it was started. */
322	uint64_t initial_count_load_time;
323	/** The time stamp of the next timer callback. */
324	uint64_t next_time;
325	/** The APIC timer - R3 Ptr. */
326	PTMTIMERR3 pTimerR3;
327	/** The APIC timer - R0 Ptr. */
328	PTMTIMERR0 pTimerR0;
329	/** The APIC timer - RC Ptr. */
330	PTMTIMERRC pTimerRC;
331	/** Whether the timer is armed or not */
332	bool fTimerArmed;
333	/** Alignment */
334	bool afAlignment[3];
335	/** The initial_count value used for the current frequency hint. */
336	uint32_t uHintedInitialCount;
337	/** The count_shift value used for the current frequency hint. */
338	uint32_t uHintedCountShift;
339	/** Timer description timer. */
340	R3PTRTYPE(char *) pszDesc;
341
342	/** The IRQ tags and source IDs for each (tracing purposes). */
343	uint32_t auTags[256];
344
345	# ifdef VBOX_WITH_STATISTICS
346	# if HC_ARCH_BITS == 32
347	uint32_t u32Alignment0;
348	# endif
349	STAMCOUNTER StatTimerSetInitialCount;
350	STAMCOUNTER StatTimerSetInitialCountArm;
351	STAMCOUNTER StatTimerSetInitialCountDisarm;
352	STAMCOUNTER StatTimerSetLvt;
353	STAMCOUNTER StatTimerSetLvtClearPeriodic;
354	STAMCOUNTER StatTimerSetLvtPostponed;
355	STAMCOUNTER StatTimerSetLvtArmed;
356	STAMCOUNTER StatTimerSetLvtArm;
357	STAMCOUNTER StatTimerSetLvtArmRetries;
358	STAMCOUNTER StatTimerSetLvtNoRelevantChange;
359	# endif
360
361	} APICState;
362
363	AssertCompileMemberAlignment(APICState, initial_count_load_time, 8);
364	# ifdef VBOX_WITH_STATISTICS
365	AssertCompileMemberAlignment(APICState, StatTimerSetInitialCount, 8);
366	# endif
367
368	typedef struct
369	{
370	/** The device instance - R3 Ptr. */
371	PPDMDEVINSR3 pDevInsR3;
372	/** The APIC helpers - R3 Ptr. */
373	PCPDMAPICHLPR3 pApicHlpR3;
374	/** LAPICs states - R3 Ptr */
375	R3PTRTYPE(APICState *) paLapicsR3;
376	/** The critical section - R3 Ptr. */
377	R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
378
379	/** The device instance - R0 Ptr. */
380	PPDMDEVINSR0 pDevInsR0;
381	/** The APIC helpers - R0 Ptr. */
382	PCPDMAPICHLPR0 pApicHlpR0;
383	/** LAPICs states - R0 Ptr */
384	R0PTRTYPE(APICState *) paLapicsR0;
385	/** The critical section - R3 Ptr. */
386	R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
387
388	/** The device instance - RC Ptr. */
389	PPDMDEVINSRC pDevInsRC;
390	/** The APIC helpers - RC Ptr. */
391	PCPDMAPICHLPRC pApicHlpRC;
392	/** LAPICs states - RC Ptr */
393	RCPTRTYPE(APICState *) paLapicsRC;
394	/** The critical section - R3 Ptr. */
395	RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
396
397	/** APIC specification version in this virtual hardware configuration. */
398	PDMAPICVERSION enmVersion;
399
400	/** Number of attempts made to optimize TPR accesses. */
401	uint32_t cTPRPatchAttempts;
402
403	/** Number of CPUs on the system (same as LAPIC count). */
404	uint32_t cCpus;
405	/** Whether we've got an IO APIC or not. */
406	bool fIoApic;
407	/** Alignment padding. */
408	bool afPadding[3];
409
410	# ifdef VBOX_WITH_STATISTICS
411	STAMCOUNTER StatMMIOReadGC;
412	STAMCOUNTER StatMMIOReadHC;
413	STAMCOUNTER StatMMIOWriteGC;
414	STAMCOUNTER StatMMIOWriteHC;
415	STAMCOUNTER StatClearedActiveIrq;
416	# endif
417	} APICDeviceInfo;
418	# ifdef VBOX_WITH_STATISTICS
419	AssertCompileMemberAlignment(APICDeviceInfo, StatMMIOReadGC, 8);
420	# endif
421
422	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
423
424	/*******************************************************************************
425	* Internal Functions *
426	*******************************************************************************/
427	static void apic_update_tpr(APICDeviceInfo pDev, APICState s, uint32_t val);
428
429	static void apic_eoi(APICDeviceInfo pDev, APICState s); /* */
430	static PVMCPUSET apic_get_delivery_bitmask(APICDeviceInfo* pDev, uint8_t dest, uint8_t dest_mode, PVMCPUSET pDstSet);
431	static int apic_deliver(APICDeviceInfo* pDev, APICState *s,
432	uint8_t dest, uint8_t dest_mode,
433	uint8_t delivery_mode, uint8_t vector_num,
434	uint8_t polarity, uint8_t trigger_mode);
435	static int apic_get_arb_pri(APICState const *s);
436	static int apic_get_ppr(APICState const *s);
437	static uint32_t apic_get_current_count(APICDeviceInfo const pDev, APICState const s);
438	static void apicTimerSetInitialCount(APICDeviceInfo pDev, APICState s, uint32_t initial_count);
439	static void apicTimerSetLvt(APICDeviceInfo pDev, APICState pApic, uint32_t fNew);
440	static void apicSendInitIpi(APICDeviceInfo* pDev, APICState *s);
441
442	static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s);
443	static void apic_set_irq(APICDeviceInfo* pDev, APICState *s, int vector_num, int trigger_mode, uint32_t uTagSrc);
444	static bool apic_update_irq(APICDeviceInfo* pDev, APICState *s);
445
446
447	DECLINLINE(APICState) getLapicById(APICDeviceInfo pDev, VMCPUID id)
448	{
449	AssertFatalMsg(id < pDev->cCpus, ("CPU id %d out of range\n", id));
450	return &pDev->CTX_SUFF(paLapics)[id];
451	}
452
453	DECLINLINE(APICState) getLapic(APICDeviceInfo pDev)
454	{
455	/* LAPIC's array is indexed by CPU id */
456	VMCPUID id = pDev->CTX_SUFF(pApicHlp)->pfnGetCpuId(pDev->CTX_SUFF(pDevIns));
457	return getLapicById(pDev, id);
458	}
459
460	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* pDev, APICState *s)
461	{
462	/* for now we assume LAPIC physical id == CPU id */
463	return VMCPUID(s->phys_id);
464	}
465
466	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* pDev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
467	{
468	LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(pDev, s)));
469	pDev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
470	getCpuFromLapic(pDev, s));
471	}
472
473	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* pDev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
474	{
475	LogFlow(("apic: clear interrupt flag\n"));
476	pDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
477	getCpuFromLapic(pDev, s));
478	}
479
480	# ifdef IN_RING3
481
482	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* pDev, APICState *s, int vector)
483	{
484	Log2(("apic: send SIPI vector=%d\n", vector));
485
486	pDev->pApicHlpR3->pfnSendSipi(pDev->pDevInsR3,
487	getCpuFromLapic(pDev, s),
488	vector);
489	}
490
491	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* pDev, APICState *s)
492	{
493	Log2(("apic: send init IPI\n"));
494
495	pDev->pApicHlpR3->pfnSendInitIpi(pDev->pDevInsR3,
496	getCpuFromLapic(pDev, s));
497	}
498
499	# endif /* IN_RING3 */
500
501	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* pDev)
502	{
503	switch (pDev->enmVersion)
504	{
505	case PDMAPICVERSION_NONE:
506	return 0;
507	case PDMAPICVERSION_APIC:
508	return MSR_IA32_APICBASE_ENABLE;
509	case PDMAPICVERSION_X2APIC:
510	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
511	default:
512	AssertMsgFailed(("Unsupported APIC version %d\n", pDev->enmVersion));
513	return 0;
514	}
515	}
516
517	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
518	{
519	switch (((apic->apicbase) >> 10) & 0x3)
520	{
521	case 0:
522	return PDMAPICVERSION_NONE;
523	case 1:
524	default:
525	/* Invalid */
526	return PDMAPICVERSION_NONE;
527	case 2:
528	return PDMAPICVERSION_APIC;
529	case 3:
530	return PDMAPICVERSION_X2APIC;
531	}
532	}
533
534	static int apic_bus_deliver(APICDeviceInfo* pDev,
535	PCVMCPUSET pDstSet, uint8_t delivery_mode,
536	uint8_t vector_num, uint8_t polarity,
537	uint8_t trigger_mode, uint32_t uTagSrc)
538	{
539	LogFlow(("apic_bus_deliver mask=%R[vmcpuset] mode=%x vector=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n",
540	pDstSet, delivery_mode, vector_num, polarity, trigger_mode, uTagSrc));
541
542	switch (delivery_mode)
543	{
544	case APIC_DM_LOWPRI:
545	{
546	VMCPUID idDstCpu = VMCPUSET_FIND_FIRST_PRESENT(pDstSet);
547	if (idDstCpu != NIL_VMCPUID)
548	{
549	APICState *pApic = getLapicById(pDev, idDstCpu);
550	apic_set_irq(pDev, pApic, vector_num, trigger_mode, uTagSrc);
551	}
552	return VINF_SUCCESS;
553	}
554
555	case APIC_DM_FIXED:
556	/** @todo XXX: arbitration */
557	break;
558
559	case APIC_DM_SMI:
560	APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
561	cpuSetInterrupt(pDev, pCurApic, PDMAPICIRQ_SMI);
562	APIC_FOREACH_END();
563	return VINF_SUCCESS;
564
565	case APIC_DM_NMI:
566	APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
567	cpuSetInterrupt(pDev, pCurApic, PDMAPICIRQ_NMI);
568	APIC_FOREACH_END();
569	return VINF_SUCCESS;
570
571	case APIC_DM_INIT:
572	/* normal INIT IPI sent to processors */
573	#ifdef IN_RING3
574	APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
575	apicSendInitIpi(pDev, pCurApic);
576	APIC_FOREACH_END();
577	return VINF_SUCCESS;
578	#else
579	/* We shall send init IPI only in R3. */
580	return VINF_IOM_R3_MMIO_READ_WRITE;
581	#endif /* IN_RING3 */
582
583	case APIC_DM_EXTINT:
584	/* handled in I/O APIC code */
585	break;
586
587	default:
588	return VINF_SUCCESS;
589	}
590
591	APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
592	apic_set_irq(pDev, pCurApic, vector_num, trigger_mode, uTagSrc);
593	APIC_FOREACH_END();
594	return VINF_SUCCESS;
595	}
596
597
598	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
599	{
600	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
601	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
602	APICState s = getLapic(pDev); /* @todo fix interface */
603	Log(("apicSetBase: %016RX64\n", val));
604
605	/** @todo: do we need to lock here ? */
606	/* APIC_LOCK_VOID(pDev, VERR_INTERNAL_ERROR); */
607	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
608	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
609	PDMAPICVERSION oldMode = getApicMode(s);
610	s->apicbase =
611	(val & 0xfffff000) \| /* base */
612	(val & getApicEnableBits(pDev)) \| /* mode */
613	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
614	PDMAPICVERSION newMode = getApicMode(s);
615
616	if (oldMode != newMode)
617	{
618	switch (newMode)
619	{
620	case PDMAPICVERSION_NONE:
621	{
622	s->spurious_vec &= ~APIC_SV_ENABLE;
623	/* Clear any pending APIC interrupt action flag. */
624	cpuClearInterrupt(pDev, s);
625	/** @todo: why do we do that? */
626	pDev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
627	break;
628	}
629	case PDMAPICVERSION_APIC:
630	/** @todo: map MMIO ranges, if needed */
631	break;
632	case PDMAPICVERSION_X2APIC:
633	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
634	break;
635	default:
636	break;
637	}
638	}
639	/* APIC_UNLOCK(pDev); */
640	}
641
642	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
643	{
644	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
645	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
646	APICState s = getLapic(pDev); /* @todo fix interface */
647	LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
648	return s->apicbase;
649	}
650
651	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
652	{
653	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
654	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
655	APICState *s = getLapicById(pDev, idCpu);
656	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, val));
657	apic_update_tpr(pDev, s, val);
658	}
659
660	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
661	{
662	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
663	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
664	APICState *s = getLapicById(pDev, idCpu);
665	Log2(("apicGetTPR: returns %#x\n", s->tpr));
666	return s->tpr;
667	}
668
669
670	/**
671	* apicWriteRegister helper for dealing with invalid register access.
672	*
673	* @returns Strict VBox status code.
674	* @param pDev The PDM device instance.
675	* @param pApic The APIC being written to.
676	* @param iReg The APIC register index.
677	* @param u64Value The value being written.
678	* @param rcBusy The busy return code to employ. See
679	* PDMCritSectEnter for a description.
680	* @param fMsr Set if called via MSR, clear if MMIO.
681	*/
682	static int apicWriteRegisterInvalid(APICDeviceInfo pDev, APICState pApic, uint32_t iReg, uint64_t u64Value,
683	int rcBusy, bool fMsr)
684	{
685	Log(("apicWriteRegisterInvalid/%u: iReg=%#x fMsr=%RTbool u64Value=%#llx\n", pApic->phys_id, iReg, fMsr, u64Value));
686	int rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
687	"iReg=%#x fMsr=%RTbool u64Value=%#llx id=%u\n", iReg, fMsr, u64Value, pApic->phys_id);
688	APIC_LOCK(pDev, rcBusy);
689	pApic->esr \|= ESR_ILLEGAL_ADDRESS;
690	APIC_UNLOCK(pDev);
691	return rc;
692	}
693
694
695
696	/**
697	* Writes to an APIC register via MMIO or MSR.
698	*
699	* @returns Strict VBox status code.
700	* @param pDev The PDM device instance.
701	* @param pApic The APIC being written to.
702	* @param iReg The APIC register index.
703	* @param u64Value The value being written.
704	* @param rcBusy The busy return code to employ. See
705	* PDMCritSectEnter for a description.
706	* @param fMsr Set if called via MSR, clear if MMIO.
707	*/
708	static int apicWriteRegister(APICDeviceInfo pDev, APICState pApic, uint32_t iReg, uint64_t u64Value,
709	int rcBusy, bool fMsr)
710	{
711	Assert(!PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
712
713	int rc = VINF_SUCCESS;
714	switch (iReg)
715	{
716	case 0x02:
717	APIC_LOCK(pDev, rcBusy);
718	pApic->id = (u64Value >> 24); /** @todo r=bird: Is the range supposed to be 40 bits??? */
719	APIC_UNLOCK(pDev);
720	break;
721
722	case 0x03:
723	/* read only, ignore write. */
724	break;
725
726	case 0x08:
727	APIC_LOCK(pDev, rcBusy);
728	apic_update_tpr(pDev, pApic, u64Value);
729	APIC_UNLOCK(pDev);
730	break;
731
732	case 0x09: case 0x0a:
733	Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
734	break;
735
736	case 0x0b: /* EOI */
737	APIC_LOCK(pDev, rcBusy);
738	apic_eoi(pDev, pApic);
739	APIC_UNLOCK(pDev);
740	break;
741
742	case 0x0d:
743	APIC_LOCK(pDev, rcBusy);
744	pApic->log_dest = (u64Value >> 24) & 0xff;
745	APIC_UNLOCK(pDev);
746	break;
747
748	case 0x0e:
749	APIC_LOCK(pDev, rcBusy);
750	pApic->dest_mode = u64Value >> 28; /** @todo r=bird: range? This used to be 32-bit before morphed into an MSR handler. */
751	APIC_UNLOCK(pDev);
752	break;
753
754	case 0x0f:
755	APIC_LOCK(pDev, rcBusy);
756	pApic->spurious_vec = u64Value & 0x1ff;
757	apic_update_irq(pDev, pApic);
758	APIC_UNLOCK(pDev);
759	break;
760
761	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
762	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
763	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
764	case 0x28:
765	Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
766	break;
767
768	case 0x30:
769	APIC_LOCK(pDev, rcBusy);
770	pApic->icr[0] = (uint32_t)u64Value;
771	if (fMsr) /* Here one of the differences with regular APIC: ICR is single 64-bit register */
772	pApic->icr[1] = (uint32_t)(u64Value >> 32);
773	rc = apic_deliver(pDev, pApic, (pApic->icr[1] >> 24) & 0xff, (pApic->icr[0] >> 11) & 1,
774	(pApic->icr[0] >> 8) & 7, (pApic->icr[0] & 0xff),
775	(pApic->icr[0] >> 14) & 1, (pApic->icr[0] >> 15) & 1);
776	APIC_UNLOCK(pDev);
777	break;
778
779	case 0x31:
780	if (!fMsr)
781	{
782	APIC_LOCK(pDev, rcBusy);
783	pApic->icr[1] = (uint64_t)u64Value;
784	APIC_UNLOCK(pDev);
785	}
786	else
787	rc = apicWriteRegisterInvalid(pDev, pApic, iReg, u64Value, rcBusy, fMsr);
788	break;
789
790	case 0x32 + APIC_LVT_TIMER:
791	AssertCompile(APIC_LVT_TIMER == 0);
792	APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
793	apicTimerSetLvt(pDev, pApic, u64Value);
794	APIC_AND_TM_UNLOCK(pDev, pApic);
795	break;
796
797	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
798	APIC_LOCK(pDev, rcBusy);
799	pApic->lvt[iReg - 0x32] = u64Value;
800	APIC_UNLOCK(pDev);
801	break;
802
803	case 0x38:
804	APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
805	apicTimerSetInitialCount(pDev, pApic, u64Value);
806	APIC_AND_TM_UNLOCK(pDev, pApic);
807	break;
808
809	case 0x39:
810	Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
811	break;
812
813	case 0x3e:
814	{
815	APIC_LOCK(pDev, rcBusy);
816	pApic->divide_conf = u64Value & 0xb;
817	int v = (pApic->divide_conf & 3) \| ((pApic->divide_conf >> 1) & 4);
818	pApic->count_shift = (v + 1) & 7;
819	APIC_UNLOCK(pDev);
820	break;
821	}
822
823	case 0x3f:
824	if (fMsr)
825	{
826	/* Self IPI, see x2APIC book 2.4.5 */
827	APIC_LOCK(pDev, rcBusy);
828	int vector = u64Value & 0xff;
829	VMCPUSET SelfSet;
830	VMCPUSET_EMPTY(&SelfSet);
831	VMCPUSET_ADD(&SelfSet, pApic->id);
832	rc = apic_bus_deliver(pDev,
833	&SelfSet,
834	0 /* Delivery mode - fixed */,
835	vector,
836	0 /* Polarity - conform to the bus */,
837	0 /* Trigger mode - edge */,
838	pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDev->CTX_SUFF(pDevIns), PDM_IRQ_LEVEL_HIGH));
839	APIC_UNLOCK(pDev);
840	break;
841	}
842	/* else: fall thru */
843
844	default:
845	rc = apicWriteRegisterInvalid(pDev, pApic, iReg, u64Value, rcBusy, fMsr);
846	break;
847	}
848
849	return rc;
850	}
851
852
853	/**
854	* apicReadRegister helper for dealing with invalid register access.
855	*
856	* @returns Strict VBox status code.
857	* @param pDev The PDM device instance.
858	* @param pApic The APIC being read to.
859	* @param iReg The APIC register index.
860	* @param pu64Value Where to store the value we've read.
861	* @param rcBusy The busy return code to employ. See
862	* PDMCritSectEnter for a description.
863	* @param fMsr Set if called via MSR, clear if MMIO.
864	*/
865	static int apicReadRegisterInvalid(APICDeviceInfo pDev, APICState pApic, uint32_t iReg, uint64_t *pu64Value,
866	int rcBusy, bool fMsr)
867	{
868	Log(("apicReadRegisterInvalid/%u: iReg=%#x fMsr=%RTbool\n", pApic->phys_id, iReg, fMsr));
869	int rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
870	"iReg=%#x fMsr=%RTbool id=%u\n", iReg, fMsr, pApic->phys_id);
871	APIC_LOCK(pDev, rcBusy);
872	pApic->esr \|= ESR_ILLEGAL_ADDRESS;
873	APIC_UNLOCK(pDev);
874	*pu64Value = 0;
875	return rc;
876	}
877
878
879	/**
880	* Read from an APIC register via MMIO or MSR.
881	*
882	* @returns Strict VBox status code.
883	* @param pDev The PDM device instance.
884	* @param pApic The APIC being read to.
885	* @param iReg The APIC register index.
886	* @param pu64Value Where to store the value we've read.
887	* @param rcBusy The busy return code to employ. See
888	* PDMCritSectEnter for a description.
889	* @param fMsr Set if called via MSR, clear if MMIO.
890	*/
891	static int apicReadRegister(APICDeviceInfo pDev, APICState pApic, uint32_t iReg, uint64_t *pu64Value,
892	int rcBusy, bool fMsr)
893	{
894	Assert(!PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
895
896	int rc = VINF_SUCCESS;
897	switch (iReg)
898	{
899	case 0x02: /* id */
900	APIC_LOCK(pDev, rcBusy);
901	*pu64Value = pApic->id << 24;
902	APIC_UNLOCK(pDev);
903	break;
904
905	case 0x03: /* version */
906	APIC_LOCK(pDev, rcBusy);
907	*pu64Value = APIC_HW_VERSION
908	\| ((APIC_LVT_NB - 1) << 16) /* Max LVT index */
909	#if 0
910	\| (0 << 24) /* Support for EOI broadcast suppression */
911	#endif
912	;
913	APIC_UNLOCK(pDev);
914	break;
915
916	case 0x08:
917	APIC_LOCK(pDev, rcBusy);
918	*pu64Value = pApic->tpr;
919	APIC_UNLOCK(pDev);
920	break;
921
922	case 0x09:
923	*pu64Value = apic_get_arb_pri(pApic);
924	break;
925
926	case 0x0a:
927	/* ppr */
928	APIC_LOCK(pDev, rcBusy);
929	*pu64Value = apic_get_ppr(pApic);
930	APIC_UNLOCK(pDev);
931	break;
932
933	case 0x0b:
934	Log(("apicReadRegister: %x -> write only returning 0\n", iReg));
935	*pu64Value = 0;
936	break;
937
938	case 0x0d:
939	APIC_LOCK(pDev, rcBusy);
940	*pu64Value = (uint64_t)pApic->log_dest << 24;
941	APIC_UNLOCK(pDev);
942	break;
943
944	case 0x0e:
945	/* Bottom 28 bits are always 1 */
946	APIC_LOCK(pDev, rcBusy);
947	*pu64Value = ((uint64_t)pApic->dest_mode << 28) \| UINT32_C(0xfffffff);
948	APIC_UNLOCK(pDev);
949	break;
950
951	case 0x0f:
952	APIC_LOCK(pDev, rcBusy);
953	*pu64Value = pApic->spurious_vec;
954	APIC_UNLOCK(pDev);
955	break;
956
957	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
958	APIC_LOCK(pDev, rcBusy);
959	*pu64Value = pApic->isr.au32Bitmap[iReg & 7];
960	APIC_UNLOCK(pDev);
961	break;
962
963	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
964	APIC_LOCK(pDev, rcBusy);
965	*pu64Value = pApic->tmr.au32Bitmap[iReg & 7];
966	APIC_UNLOCK(pDev);
967	break;
968
969	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
970	APIC_LOCK(pDev, rcBusy);
971	*pu64Value = pApic->irr.au32Bitmap[iReg & 7];
972	APIC_UNLOCK(pDev);
973	break;
974
975	case 0x28:
976	APIC_LOCK(pDev, rcBusy);
977	*pu64Value = pApic->esr;
978	APIC_UNLOCK(pDev);
979	break;
980
981	case 0x30:
982	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
983	APIC_LOCK(pDev, rcBusy);
984	if (fMsr)
985	*pu64Value = RT_MAKE_U64(pApic->icr[0], pApic->icr[1]);
986	else
987	*pu64Value = pApic->icr[0];
988	APIC_UNLOCK(pDev);
989	break;
990
991	case 0x31:
992	if (fMsr)
993	rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
994	else
995	{
996	APIC_LOCK(pDev, rcBusy);
997	*pu64Value = pApic->icr[1];
998	APIC_UNLOCK(pDev);
999	}
1000	break;
1001
1002	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1003	APIC_LOCK(pDev, rcBusy);
1004	*pu64Value = pApic->lvt[iReg - 0x32];
1005	APIC_UNLOCK(pDev);
1006	break;
1007
1008	case 0x38:
1009	APIC_LOCK(pDev, rcBusy);
1010	*pu64Value = pApic->initial_count;
1011	APIC_UNLOCK(pDev);
1012	break;
1013
1014	case 0x39:
1015	APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
1016	*pu64Value = apic_get_current_count(pDev, pApic);
1017	APIC_AND_TM_UNLOCK(pDev, pApic);
1018	break;
1019
1020	case 0x3e:
1021	APIC_LOCK(pDev, rcBusy);
1022	*pu64Value = pApic->divide_conf;
1023	APIC_UNLOCK(pDev);
1024	break;
1025
1026	case 0x3f:
1027	if (fMsr)
1028	{
1029	/* Self IPI register is write only */
1030	Log(("apicReadMSR: read from write-only register %d ignored\n", iReg));
1031	*pu64Value = 0;
1032	}
1033	else
1034	rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
1035	break;
1036	case 0x2f: /** @todo Correctable machine check exception vector, implement me! */
1037	default:
1038	/**
1039	* @todo: according to spec when APIC writes to ESR it msut raise error interrupt,
1040	* i.e. LVT[5]
1041	*/
1042	rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
1043	break;
1044	}
1045	return rc;
1046	}
1047
1048	/**
1049	* @interface_method_impl{PDMAPICREG,pfnWriteMSRR3}
1050	*/
1051	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
1052	{
1053	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1054	if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
1055	return VERR_EM_INTERPRETER; /** @todo tell the caller to raise hell (\#GP(0)). */
1056
1057	APICState *pApic = getLapicById(pDev, idCpu);
1058	uint32_t iReg = (u32Reg - MSR_IA32_APIC_START) & 0xff;
1059	return apicWriteRegister(pDev, pApic, iReg, u64Value, VINF_SUCCESS /rcBusy/, true /fMsr/);
1060	}
1061
1062
1063	/**
1064	* @interface_method_impl{PDMAPICREG,pfnReadMSRR3}
1065	*/
1066	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
1067	{
1068	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1069	#ifndef DEBUG_michael /* See xTracker #6304. */
1070	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1071	#endif
1072
1073	if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
1074	return VERR_EM_INTERPRETER;
1075
1076	APICState *pApic = getLapicById(pDev, idCpu);
1077	uint32_t iReg = (u32Reg - MSR_IA32_APIC_START) & 0xff;
1078	return apicReadRegister(pDev, pApic, iReg, pu64Value, VINF_SUCCESS /rcBusy/, true /fMsr/);
1079	}
1080
1081	/**
1082	* More or less private interface between IOAPIC, only PDM is responsible
1083	* for connecting the two devices.
1084	*/
1085	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1086	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
1087	uint8_t u8TriggerMode, uint32_t uTagSrc)
1088	{
1089	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1090	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1091	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x uTagSrc=%#x\n",
1092	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
1093	VMCPUSET DstSet;
1094	return apic_bus_deliver(pDev, apic_get_delivery_bitmask(pDev, u8Dest, u8DestMode, &DstSet),
1095	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc);
1096	}
1097
1098	/**
1099	* Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
1100	* Normally used for 8259A PIC and NMI.
1101	*/
1102	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
1103	{
1104	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1105	APICState *s = getLapicById(pDev, 0);
1106
1107	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1108	LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x u8Level=%x\n", pDevIns, u8Pin, u8Level));
1109
1110	/* If LAPIC is disabled, go straight to the CPU. */
1111	if (!(s->spurious_vec & APIC_SV_ENABLE))
1112	{
1113	LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
1114	if (u8Level)
1115	cpuSetInterrupt(pDev, s, PDMAPICIRQ_EXTINT);
1116	else
1117	cpuClearInterrupt(pDev, s, PDMAPICIRQ_EXTINT);
1118
1119	return VINF_SUCCESS;
1120	}
1121
1122	/* If LAPIC is enabled, interrupts are subject to LVT programming. */
1123
1124	/* There are only two local interrupt pins. */
1125	AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
1126
1127	/* NB: We currently only deliver local interrupts to the first CPU. In theory they
1128	* should be delivered to all CPUs and it is the guest's responsibility to ensure
1129	* no more than one CPU has the interrupt unmasked.
1130	*/
1131	uint32_t u32Lvec;
1132
1133	u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin]; /* Fetch corresponding LVT entry. */
1134	/* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
1135	if (!(u32Lvec & APIC_LVT_MASKED))
1136	{ uint8_t u8Delivery;
1137	PDMAPICIRQ enmType;
1138
1139	u8Delivery = (u32Lvec >> 8) & 7;
1140	switch (u8Delivery)
1141	{
1142	case APIC_DM_EXTINT:
1143	Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
1144	enmType = PDMAPICIRQ_EXTINT;
1145	/* ExtINT can be both set and cleared, NMI/SMI/INIT can only be set. */
1146	LogFlow(("apicLocalInterrupt: %s ExtINT interrupt\n", u8Level ? "setting" : "clearing"));
1147	if (u8Level)
1148	cpuSetInterrupt(pDev, s, enmType);
1149	else
1150	cpuClearInterrupt(pDev, s, enmType);
1151	return VINF_SUCCESS;
1152	case APIC_DM_NMI:
1153	/* External NMI should be wired to LINT1, but Linux sometimes programs
1154	* LVT0 to NMI delivery mode as well.
1155	*/
1156	enmType = PDMAPICIRQ_NMI;
1157	/* Currently delivering NMIs through here causes problems with NMI watchdogs
1158	* on certain Linux kernels, e.g. 64-bit CentOS 5.3. Disable NMIs for now.
1159	*/
1160	return VINF_SUCCESS;
1161	case APIC_DM_SMI:
1162	enmType = PDMAPICIRQ_SMI;
1163	break;
1164	case APIC_DM_FIXED:
1165	{
1166	/** @todo implement APIC_DM_FIXED! */
1167	static unsigned s_c = 0;
1168	if (s_c++ < 5)
1169	LogRel(("delivery type APIC_DM_FIXED not implemented. u8Pin=%d u8Level=%d\n", u8Pin, u8Level));
1170	return VINF_SUCCESS;
1171	}
1172	case APIC_DM_INIT:
1173	/** @todo implement APIC_DM_INIT? */
1174	default:
1175	{
1176	static unsigned s_c = 0;
1177	if (s_c++ < 100)
1178	AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d\n", u8Delivery, u8Pin, u8Level));
1179	return VERR_INTERNAL_ERROR_4;
1180	}
1181	}
1182	LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
1183	cpuSetInterrupt(pDev, s, enmType);
1184	}
1185	return VINF_SUCCESS;
1186	}
1187
1188	static int apic_get_ppr(APICState const *s)
1189	{
1190	int ppr;
1191
1192	int tpr = (s->tpr >> 4);
1193	int isrv = Apic256BitReg_FindLastSetBit(&s->isr, 0);
1194	isrv >>= 4;
1195	if (tpr >= isrv)
1196	ppr = s->tpr;
1197	else
1198	ppr = isrv << 4;
1199	return ppr;
1200	}
1201
1202	static int apic_get_ppr_zero_tpr(APICState *s)
1203	{
1204	return Apic256BitReg_FindLastSetBit(&s->isr, 0);
1205	}
1206
1207	static int apic_get_arb_pri(APICState const *s)
1208	{
1209	/** @todo XXX: arbitration */
1210	return 0;
1211	}
1212
1213	/* signal the CPU if an irq is pending */
1214	static bool apic_update_irq(APICDeviceInfo pDev, APICState s)
1215	{
1216	if (!(s->spurious_vec & APIC_SV_ENABLE))
1217	{
1218	/* Clear any pending APIC interrupt action flag. */
1219	cpuClearInterrupt(pDev, s);
1220	return false;
1221	}
1222
1223	int irrv = Apic256BitReg_FindLastSetBit(&s->irr, -1);
1224	if (irrv < 0)
1225	return false;
1226	int ppr = apic_get_ppr(s);
1227	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1228	return false;
1229	cpuSetInterrupt(pDev, s);
1230	return true;
1231	}
1232
1233	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
1234	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
1235	{
1236	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1237	if (!pDev)
1238	return false;
1239
1240	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
1241
1242	APICState s = getLapic(pDev); /* @todo fix interface */
1243
1244	/*
1245	* All our callbacks now come from single IOAPIC, thus locking
1246	* seems to be excessive now
1247	*/
1248	/** @todo check excessive locking whatever... */
1249	int irrv = Apic256BitReg_FindLastSetBit(&s->irr, -1);
1250	if (irrv < 0)
1251	return false;
1252
1253	int ppr = apic_get_ppr_zero_tpr(s);
1254
1255	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1256	return false;
1257
1258	return true;
1259	}
1260
1261	static void apic_update_tpr(APICDeviceInfo pDev, APICState s, uint32_t val)
1262	{
1263	bool fIrqIsActive = false;
1264	bool fIrqWasActive = false;
1265
1266	fIrqWasActive = apic_update_irq(pDev, s);
1267	s->tpr = val;
1268	fIrqIsActive = apic_update_irq(pDev, s);
1269
1270	/* If an interrupt is pending and now masked, then clear the FF flag. */
1271	if (fIrqWasActive && !fIrqIsActive)
1272	{
1273	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1274	STAM_COUNTER_INC(&pDev->StatClearedActiveIrq);
1275	cpuClearInterrupt(pDev, s);
1276	}
1277	}
1278
1279	static void apic_set_irq(APICDeviceInfo pDev, APICState s, int vector_num, int trigger_mode, uint32_t uTagSrc)
1280	{
1281	LogFlow(("CPU%d: apic_set_irq vector=%x trigger_mode=%x uTagSrc=%#x\n", s->phys_id, vector_num, trigger_mode, uTagSrc));
1282
1283	Apic256BitReg_SetBit(&s->irr, vector_num);
1284	if (trigger_mode)
1285	Apic256BitReg_SetBit(&s->tmr, vector_num);
1286	else
1287	Apic256BitReg_ClearBit(&s->tmr, vector_num);
1288
1289	if (!s->auTags[vector_num])
1290	s->auTags[vector_num] = uTagSrc;
1291	else
1292	s->auTags[vector_num] \|= RT_BIT_32(31);
1293
1294	apic_update_irq(pDev, s);
1295	}
1296
1297	static void apic_eoi(APICDeviceInfo pDev, APICState s)
1298	{
1299	int isrv = Apic256BitReg_FindLastSetBit(&s->isr, -1);
1300	if (isrv < 0)
1301	return;
1302	Apic256BitReg_ClearBit(&s->isr, isrv);
1303	LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1304	/** @todo XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1305	* set the remote IRR bit for level triggered interrupts. */
1306	apic_update_irq(pDev, s);
1307	}
1308
1309	static PVMCPUSET apic_get_delivery_bitmask(APICDeviceInfo *pDev, uint8_t dest, uint8_t dest_mode, PVMCPUSET pDstSet)
1310	{
1311	VMCPUSET_EMPTY(pDstSet);
1312
1313	if (dest_mode == 0)
1314	{
1315	if (dest == 0xff) /* The broadcast ID. */
1316	VMCPUSET_FILL(pDstSet);
1317	else
1318	VMCPUSET_ADD(pDstSet, dest);
1319	}
1320	else
1321	{
1322	/** @todo XXX: cluster mode */
1323	APIC_FOREACH_BEGIN(pDev);
1324	if (pCurApic->dest_mode == APIC_DESTMODE_FLAT)
1325	{
1326	if (dest & pCurApic->log_dest)
1327	VMCPUSET_ADD(pDstSet, iCurApic);
1328	}
1329	else if (pCurApic->dest_mode == APIC_DESTMODE_CLUSTER)
1330	{
1331	if ( (dest & 0xf0) == (pCurApic->log_dest & 0xf0)
1332	&& (dest & pCurApic->log_dest & 0x0f))
1333	VMCPUSET_ADD(pDstSet, iCurApic);
1334	}
1335	APIC_FOREACH_END();
1336	}
1337
1338	return pDstSet;
1339	}
1340
1341	#ifdef IN_RING3
1342	static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s)
1343	{
1344	int i;
1345
1346	for(i = 0; i < APIC_LVT_NB; i++)
1347	s->lvt[i] = 1 << 16; /* mask LVT */
1348	s->tpr = 0;
1349	s->spurious_vec = 0xff;
1350	s->log_dest = 0;
1351	s->dest_mode = 0xff; /** @todo 0xff???? */
1352	Apic256BitReg_Empty(&s->isr);
1353	Apic256BitReg_Empty(&s->tmr);
1354	Apic256BitReg_Empty(&s->irr);
1355	s->esr = 0;
1356	memset(s->icr, 0, sizeof(s->icr));
1357	s->divide_conf = 0;
1358	s->count_shift = 1;
1359	s->initial_count = 0;
1360	s->initial_count_load_time = 0;
1361	s->next_time = 0;
1362	}
1363
1364
1365	static void apicSendInitIpi(APICDeviceInfo* pDev, APICState *s)
1366	{
1367	apic_init_ipi(pDev, s);
1368	cpuSendInitIpi(pDev, s);
1369	}
1370
1371	/* send a SIPI message to the CPU to start it */
1372	static void apic_startup(APICDeviceInfo* pDev, APICState *s, int vector_num)
1373	{
1374	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1375	cpuSendSipi(pDev, s, vector_num);
1376	}
1377	#endif /* IN_RING3 */
1378
1379	static int apic_deliver(APICDeviceInfo pDev, APICState s,
1380	uint8_t dest, uint8_t dest_mode,
1381	uint8_t delivery_mode, uint8_t vector_num,
1382	uint8_t polarity, uint8_t trigger_mode)
1383	{
1384	int dest_shorthand = (s->icr[0] >> 18) & 3;
1385	LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1386
1387	VMCPUSET DstSet;
1388	switch (dest_shorthand)
1389	{
1390	case 0:
1391	apic_get_delivery_bitmask(pDev, dest, dest_mode, &DstSet);
1392	break;
1393	case 1:
1394	VMCPUSET_EMPTY(&DstSet);
1395	VMCPUSET_ADD(&DstSet, s->id);
1396	break;
1397	case 2:
1398	VMCPUSET_FILL(&DstSet);
1399	break;
1400	case 3:
1401	VMCPUSET_FILL(&DstSet);
1402	VMCPUSET_DEL(&DstSet, s->id);
1403	break;
1404	}
1405
1406	switch (delivery_mode)
1407	{
1408	case APIC_DM_INIT:
1409	{
1410	uint32_t const trig_mode = (s->icr[0] >> 15) & 1;
1411	uint32_t const level = (s->icr[0] >> 14) & 1;
1412	if (level == 0 && trig_mode == 1)
1413	{
1414	APIC_FOREACH_IN_SET_BEGIN(pDev, &DstSet);
1415	pCurApic->arb_id = pCurApic->id;
1416	APIC_FOREACH_END();
1417	Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1418	return VINF_SUCCESS;
1419	}
1420	break;
1421	}
1422
1423	case APIC_DM_SIPI:
1424	# ifdef IN_RING3
1425	APIC_FOREACH_IN_SET_BEGIN(pDev, &DstSet);
1426	apic_startup(pDev, pCurApic, vector_num);
1427	APIC_FOREACH_END();
1428	return VINF_SUCCESS;
1429	# else
1430	/* We shall send SIPI only in R3, R0 calls should be
1431	rescheduled to R3 */
1432	return VINF_IOM_R3_MMIO_WRITE;
1433	# endif
1434	}
1435
1436	return apic_bus_deliver(pDev, &DstSet, delivery_mode, vector_num,
1437	polarity, trigger_mode,
1438	pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDev->CTX_SUFF(pDevIns), PDM_IRQ_LEVEL_HIGH));
1439	}
1440
1441
1442	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
1443	{
1444	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1445	/* if the APIC is not installed or enabled, we let the 8259 handle the
1446	IRQs */
1447	if (!pDev)
1448	{
1449	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1450	return -1;
1451	}
1452
1453	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1454
1455	APICState s = getLapic(pDev); /* @todo fix interface */
1456
1457	if (!(s->spurious_vec & APIC_SV_ENABLE))
1458	{
1459	Log(("CPU%d: apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n", s->phys_id));
1460	return -1;
1461	}
1462
1463	/** @todo XXX: spurious IRQ handling */
1464	int intno = Apic256BitReg_FindLastSetBit(&s->irr, -1);
1465	if (intno < 0)
1466	{
1467	Log(("CPU%d: apic_get_interrupt: returns -1 (irr)\n", s->phys_id));
1468	return -1;
1469	}
1470
1471	if (s->tpr && (uint32_t)intno <= s->tpr)
1472	{
1473	*puTagSrc = 0;
1474	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1475	return s->spurious_vec & 0xff;
1476	}
1477
1478	Apic256BitReg_ClearBit(&s->irr, intno);
1479	Apic256BitReg_SetBit(&s->isr, intno);
1480
1481	*puTagSrc = s->auTags[intno];
1482	s->auTags[intno] = 0;
1483
1484	apic_update_irq(pDev, s);
1485
1486	LogFlow(("CPU%d: apic_get_interrupt: returns %d / %#x\n", s->phys_id, intno, *puTagSrc));
1487	return intno;
1488	}
1489
1490	/**
1491	* @remarks Caller (apicReadRegister) takes both the TM and APIC locks before
1492	* calling this function.
1493	*/
1494	static uint32_t apic_get_current_count(APICDeviceInfo const pDev, APICState const pApic)
1495	{
1496	int64_t d = (TMTimerGet(pApic->CTX_SUFF(pTimer)) - pApic->initial_count_load_time)
1497	>> pApic->count_shift;
1498
1499	uint32_t val;
1500	if (pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1501	/* periodic */
1502	val = pApic->initial_count - (d % ((uint64_t)pApic->initial_count + 1));
1503	else if (d >= pApic->initial_count)
1504	val = 0;
1505	else
1506	val = pApic->initial_count - d;
1507
1508	return val;
1509	}
1510
1511	/**
1512	* Does the frequency hinting and logging.
1513	*
1514	* @param pApic The device state.
1515	*/
1516	DECLINLINE(void) apicDoFrequencyHinting(APICState *pApic)
1517	{
1518	if ( pApic->uHintedInitialCount != pApic->initial_count
1519	\|\| pApic->uHintedCountShift != (uint32_t)pApic->count_shift)
1520	{
1521	pApic->uHintedInitialCount = pApic->initial_count;
1522	pApic->uHintedCountShift = pApic->count_shift;
1523
1524	uint32_t uHz;
1525	if (pApic->initial_count > 0)
1526	{
1527	Assert((unsigned)pApic->count_shift < 30);
1528	uint64_t cTickPerPeriod = ((uint64_t)pApic->initial_count + 1) << pApic->count_shift;
1529	uHz = TMTimerGetFreq(pApic->CTX_SUFF(pTimer)) / cTickPerPeriod;
1530	}
1531	else
1532	uHz = 0;
1533	TMTimerSetFrequencyHint(pApic->CTX_SUFF(pTimer), uHz);
1534	Log(("apic: %u Hz\n", uHz));
1535	}
1536	}
1537
1538	/**
1539	* Implementation of the 0380h access: Timer reset + new initial count.
1540	*
1541	* @param pDev The device state.
1542	* @param pApic The APIC sub-device state.
1543	* @param u32NewInitialCount The new initial count for the timer.
1544	*/
1545	static void apicTimerSetInitialCount(APICDeviceInfo pDev, APICState pApic, uint32_t u32NewInitialCount)
1546	{
1547	STAM_COUNTER_INC(&pApic->StatTimerSetInitialCount);
1548	pApic->initial_count = u32NewInitialCount;
1549
1550	/*
1551	* Don't (re-)arm the timer if the it's masked or if it's
1552	* a zero length one-shot timer.
1553	*/
1554	if ( !(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)
1555	&& u32NewInitialCount > 0)
1556	{
1557	/*
1558	* Calculate the relative next time and perform a combined timer get/set
1559	* operation. This avoids racing the clock between get and set.
1560	*/
1561	uint64_t cTicksNext = u32NewInitialCount;
1562	cTicksNext += 1;
1563	cTicksNext <<= pApic->count_shift;
1564	TMTimerSetRelative(pApic->CTX_SUFF(pTimer), cTicksNext, &pApic->initial_count_load_time);
1565	pApic->next_time = pApic->initial_count_load_time + cTicksNext;
1566	pApic->fTimerArmed = true;
1567	apicDoFrequencyHinting(pApic);
1568	STAM_COUNTER_INC(&pApic->StatTimerSetInitialCountArm);
1569	Log(("apicTimerSetInitialCount: cTicksNext=%'llu (%#llx) ic=%#x sh=%#x nxt=%#llx\n",
1570	cTicksNext, cTicksNext, u32NewInitialCount, pApic->count_shift, pApic->next_time));
1571	}
1572	else
1573	{
1574	/* Stop it if necessary and record the load time for unmasking. */
1575	if (pApic->fTimerArmed)
1576	{
1577	STAM_COUNTER_INC(&pApic->StatTimerSetInitialCountDisarm);
1578	TMTimerStop(pApic->CTX_SUFF(pTimer));
1579	pApic->fTimerArmed = false;
1580	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1581	}
1582	pApic->initial_count_load_time = TMTimerGet(pApic->CTX_SUFF(pTimer));
1583	Log(("apicTimerSetInitialCount: ic=%#x sh=%#x iclt=%#llx\n", u32NewInitialCount, pApic->count_shift, pApic->initial_count_load_time));
1584	}
1585	}
1586
1587	/**
1588	* Implementation of the 0320h access: change the LVT flags.
1589	*
1590	* @param pDev The device state.
1591	* @param pApic The APIC sub-device state to operate on.
1592	* @param fNew The new flags.
1593	*/
1594	static void apicTimerSetLvt(APICDeviceInfo pDev, APICState pApic, uint32_t fNew)
1595	{
1596	STAM_COUNTER_INC(&pApic->StatTimerSetLvt);
1597
1598	/*
1599	* Make the flag change, saving the old ones so we can avoid
1600	* unnecessary work.
1601	*/
1602	uint32_t const fOld = pApic->lvt[APIC_LVT_TIMER];
1603	pApic->lvt[APIC_LVT_TIMER] = fNew;
1604
1605	/* Only the masked and peridic bits are relevant (see apic_timer_update). */
1606	if ( (fOld & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC))
1607	!= (fNew & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC)))
1608	{
1609	/*
1610	* If changed to one-shot from periodic, stop the timer if we're not
1611	* in the first period.
1612	*/
1613	/** @todo check how clearing the periodic flag really should behave when not
1614	* in period 1. The current code just mirrors the behavior of the
1615	* original implementation. */
1616	if ( (fOld & APIC_LVT_TIMER_PERIODIC)
1617	&& !(fNew & APIC_LVT_TIMER_PERIODIC))
1618	{
1619	STAM_COUNTER_INC(&pApic->StatTimerSetLvtClearPeriodic);
1620	uint64_t cTicks = (pApic->next_time - pApic->initial_count_load_time) >> pApic->count_shift;
1621	if (cTicks >= pApic->initial_count)
1622	{
1623	/* not first period, stop it. */
1624	TMTimerStop(pApic->CTX_SUFF(pTimer));
1625	pApic->fTimerArmed = false;
1626	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1627	}
1628	/* else: first period, let it fire normally. */
1629	}
1630
1631	/*
1632	* We postpone stopping the timer when it's masked, this way we can
1633	* avoid some timer work when the guest temporarily masks the timer.
1634	* (apicR3TimerCallback will stop it if still masked.)
1635	*/
1636	if (fNew & APIC_LVT_MASKED)
1637	STAM_COUNTER_INC(&pApic->StatTimerSetLvtPostponed);
1638	else if (pApic->fTimerArmed)
1639	STAM_COUNTER_INC(&pApic->StatTimerSetLvtArmed);
1640	/*
1641	* If unmasked, not armed and with a valid initial count value (according
1642	* to our interpretation of the spec), we will have to rearm the timer so
1643	* it will fire at the end of the current period.
1644	*
1645	* N.B. This is code is currently RACING the virtual sync clock!
1646	*/
1647	else if ( (fOld & APIC_LVT_MASKED)
1648	&& pApic->initial_count > 0)
1649	{
1650	STAM_COUNTER_INC(&pApic->StatTimerSetLvtArm);
1651	for (unsigned cTries = 0; ; cTries++)
1652	{
1653	uint64_t NextTS;
1654	uint64_t cTicks = (TMTimerGet(pApic->CTX_SUFF(pTimer)) - pApic->initial_count_load_time) >> pApic->count_shift;
1655	if (fNew & APIC_LVT_TIMER_PERIODIC)
1656	NextTS = ((cTicks / ((uint64_t)pApic->initial_count + 1)) + 1) * ((uint64_t)pApic->initial_count + 1);
1657	else
1658	{
1659	if (cTicks >= pApic->initial_count)
1660	break;
1661	NextTS = (uint64_t)pApic->initial_count + 1;
1662	}
1663	NextTS <<= pApic->count_shift;
1664	NextTS += pApic->initial_count_load_time;
1665
1666	/* Try avoid the assertion in TM.cpp... this isn't perfect! */
1667	if ( NextTS > TMTimerGet(pApic->CTX_SUFF(pTimer))
1668	\|\| cTries > 10)
1669	{
1670	TMTimerSet(pApic->CTX_SUFF(pTimer), NextTS);
1671	pApic->next_time = NextTS;
1672	pApic->fTimerArmed = true;
1673	apicDoFrequencyHinting(pApic);
1674	Log(("apicTimerSetLvt: ic=%#x sh=%#x nxt=%#llx\n", pApic->initial_count, pApic->count_shift, pApic->next_time));
1675	break;
1676	}
1677	STAM_COUNTER_INC(&pApic->StatTimerSetLvtArmRetries);
1678	}
1679	}
1680	}
1681	else
1682	STAM_COUNTER_INC(&pApic->StatTimerSetLvtNoRelevantChange);
1683	}
1684
1685	# ifdef IN_RING3
1686	/**
1687	* Timer callback function.
1688	*
1689	* @param pDevIns The device state.
1690	* @param pTimer The timer handle.
1691	* @param pvUser User argument pointing to the APIC instance.
1692	*/
1693	static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1694	{
1695	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1696	APICState pApic = (APICState )pvUser;
1697	Assert(pApic->pTimerR3 == pTimer);
1698	Assert(pApic->fTimerArmed);
1699	Assert(PDMCritSectIsOwner(pDev->pCritSectR3));
1700	Assert(TMTimerIsLockOwner(pTimer));
1701
1702	if (!(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1703	LogFlow(("apic_timer: trigger irq\n"));
1704	apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE,
1705	pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDevIns, PDM_IRQ_LEVEL_HIGH));
1706
1707	if ( (pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1708	&& pApic->initial_count > 0) {
1709	/* new interval. */
1710	pApic->next_time += (((uint64_t)pApic->initial_count + 1) << pApic->count_shift);
1711	TMTimerSet(pApic->CTX_SUFF(pTimer), pApic->next_time);
1712	pApic->fTimerArmed = true;
1713	apicDoFrequencyHinting(pApic);
1714	Log2(("apicR3TimerCallback: ic=%#x sh=%#x nxt=%#llx\n", pApic->initial_count, pApic->count_shift, pApic->next_time));
1715	} else {
1716	/* single shot or disabled. */
1717	pApic->fTimerArmed = false;
1718	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1719	}
1720	} else {
1721	/* masked, do not rearm. */
1722	pApic->fTimerArmed = false;
1723	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1724	}
1725	}
1726
1727	static void apic_save(SSMHANDLE* f, void *opaque)
1728	{
1729	APICState s = (APICState)opaque;
1730	int i;
1731
1732	SSMR3PutU32(f, s->apicbase);
1733	SSMR3PutU32(f, s->id);
1734	SSMR3PutU32(f, s->phys_id);
1735	SSMR3PutU32(f, s->arb_id);
1736	SSMR3PutU32(f, s->tpr);
1737	SSMR3PutU32(f, s->spurious_vec);
1738	SSMR3PutU8(f, s->log_dest);
1739	SSMR3PutU8(f, s->dest_mode);
1740	for (i = 0; i < 8; i++) {
1741	SSMR3PutU32(f, s->isr.au32Bitmap[i]);
1742	SSMR3PutU32(f, s->tmr.au32Bitmap[i]);
1743	SSMR3PutU32(f, s->irr.au32Bitmap[i]);
1744	}
1745	for (i = 0; i < APIC_LVT_NB; i++) {
1746	SSMR3PutU32(f, s->lvt[i]);
1747	}
1748	SSMR3PutU32(f, s->esr);
1749	SSMR3PutU32(f, s->icr[0]);
1750	SSMR3PutU32(f, s->icr[1]);
1751	SSMR3PutU32(f, s->divide_conf);
1752	SSMR3PutU32(f, s->count_shift);
1753	SSMR3PutU32(f, s->initial_count);
1754	SSMR3PutU64(f, s->initial_count_load_time);
1755	SSMR3PutU64(f, s->next_time);
1756
1757	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1758	}
1759
1760	static int apic_load(SSMHANDLE f, void opaque, int version_id)
1761	{
1762	APICState s = (APICState)opaque;
1763	int i;
1764
1765	/** @todo XXX: what if the base changes? (registered memory regions) */
1766	SSMR3GetU32(f, &s->apicbase);
1767
1768	switch (version_id)
1769	{
1770	case APIC_SAVED_STATE_VERSION_ANCIENT:
1771	{
1772	uint8_t val = 0;
1773	SSMR3GetU8(f, &val);
1774	s->id = val;
1775	/* UP only in old saved states */
1776	s->phys_id = 0;
1777	SSMR3GetU8(f, &val);
1778	s->arb_id = val;
1779	break;
1780	}
1781	case APIC_SAVED_STATE_VERSION:
1782	case APIC_SAVED_STATE_VERSION_VBOX_30:
1783	SSMR3GetU32(f, &s->id);
1784	SSMR3GetU32(f, &s->phys_id);
1785	SSMR3GetU32(f, &s->arb_id);
1786	break;
1787	default:
1788	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1789	}
1790	SSMR3GetU32(f, &s->tpr);
1791	SSMR3GetU32(f, &s->spurious_vec);
1792	SSMR3GetU8(f, &s->log_dest);
1793	SSMR3GetU8(f, &s->dest_mode);
1794	for (i = 0; i < 8; i++) {
1795	SSMR3GetU32(f, &s->isr.au32Bitmap[i]);
1796	SSMR3GetU32(f, &s->tmr.au32Bitmap[i]);
1797	SSMR3GetU32(f, &s->irr.au32Bitmap[i]);
1798	}
1799	for (i = 0; i < APIC_LVT_NB; i++) {
1800	SSMR3GetU32(f, &s->lvt[i]);
1801	}
1802	SSMR3GetU32(f, &s->esr);
1803	SSMR3GetU32(f, &s->icr[0]);
1804	SSMR3GetU32(f, &s->icr[1]);
1805	SSMR3GetU32(f, &s->divide_conf);
1806	SSMR3GetU32(f, (uint32_t *)&s->count_shift);
1807	SSMR3GetU32(f, (uint32_t *)&s->initial_count);
1808	SSMR3GetU64(f, (uint64_t *)&s->initial_count_load_time);
1809	SSMR3GetU64(f, (uint64_t *)&s->next_time);
1810
1811	int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1812	AssertRCReturn(rc, rc);
1813	s->uHintedCountShift = s->uHintedInitialCount = 0;
1814	s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
1815	if (s->fTimerArmed)
1816	apicDoFrequencyHinting(s);
1817
1818	return VINF_SUCCESS; /** @todo darn mess! */
1819	}
1820
1821	#endif /* IN_RING3 */
1822
1823	/* LAPIC */
1824	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1825	{
1826	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1827	APICState *s = getLapic(pDev);
1828
1829	Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
1830
1831	/** @todo add LAPIC range validity checks (different LAPICs can
1832	* theoretically have different physical addresses, see @bugref{3092}) */
1833
1834	STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIORead));
1835	switch (cb)
1836	{
1837	case 1:
1838	/** @todo this is not how recent APIC behave! We will fix
1839	* this via the IOM. */
1840	(uint8_t )pv = 0;
1841	break;
1842
1843	case 2:
1844	/** @todo this is not how recent APIC behave! */
1845	(uint16_t )pv = 0;
1846	break;
1847
1848	case 4:
1849	{
1850	#if 0 /** @note experimental */
1851	#ifndef IN_RING3
1852	uint32_t index = (GCPhysAddr >> 4) & 0xff;
1853
1854	if ( index == 0x08 /* TPR */
1855	&& ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
1856	{
1857	#ifdef IN_RC
1858	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
1859	#else
1860	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
1861	pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
1862	#endif
1863	return VINF_PATM_HC_MMIO_PATCH_READ;
1864	}
1865	#endif
1866	#endif /* experimental */
1867
1868	/* It does its own locking. */
1869	uint64_t u64Value = 0;
1870	int rc = apicReadRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, &u64Value,
1871	VINF_IOM_R3_MMIO_READ, false /fMsr/);
1872	(uint32_t )pv = (uint32_t)u64Value;
1873	return rc;
1874	}
1875
1876	default:
1877	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1878	return VERR_INTERNAL_ERROR;
1879	}
1880	return VINF_SUCCESS;
1881	}
1882
1883	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
1884	{
1885	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1886	APICState *s = getLapic(pDev);
1887
1888	Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
1889
1890	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
1891	* different physical addresses, see @bugref{3092}) */
1892
1893	STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIOWrite));
1894	switch (cb)
1895	{
1896	case 1:
1897	case 2:
1898	/* ignore */
1899	break;
1900
1901	case 4:
1902	/* It does its own locking. */
1903	return apicWriteRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, (uint32_t const )pv,
1904	VINF_IOM_R3_MMIO_WRITE, false /fMsr/);
1905
1906	default:
1907	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1908	return VERR_INTERNAL_ERROR;
1909	}
1910	return VINF_SUCCESS;
1911	}
1912
1913	#ifdef IN_RING3
1914
1915	/**
1916	* Wrapper around apicReadRegister.
1917	*
1918	* @returns 64-bit register value.
1919	* @param pDev The PDM device instance.
1920	* @param pApic The Local APIC in question.
1921	* @param iReg The APIC register index.
1922	*/
1923	static uint64_t apicR3InfoReadReg(APICDeviceInfo pDev, APICState pApic, uint32_t iReg)
1924	{
1925	uint64_t u64Value;
1926	int rc = apicReadRegister(pDev, pApic, iReg, &u64Value, VINF_SUCCESS, true /fMsr/);
1927	AssertRCReturn(rc, UINT64_MAX);
1928	return u64Value;
1929	}
1930
1931
1932	/**
1933	* Print a 8-DWORD Local APIC bit map (256 bits).
1934	*
1935	* @param pDev The PDM device instance.
1936	* @param pApic The Local APIC in question.
1937	* @param pHlp The output helper.
1938	* @param iStartReg The register to start at.
1939	*/
1940	static void apicR3DumpVec(APICDeviceInfo pDev, APICState pApic, PCDBGFINFOHLP pHlp, uint32_t iStartReg)
1941	{
1942	for (uint32_t i = 0; i < 8; i++)
1943	pHlp->pfnPrintf(pHlp, "%08x", apicR3InfoReadReg(pDev, pApic, iStartReg + i));
1944	pHlp->pfnPrintf(pHlp, "\n");
1945	}
1946
1947	/**
1948	* Print basic Local APIC state.
1949	*
1950	* @param pDev The PDM device instance.
1951	* @param pApic The Local APIC in question.
1952	* @param pHlp The output helper.
1953	*/
1954	static void apicR3InfoBasic(APICDeviceInfo pDev, APICState pApic, PCDBGFINFOHLP pHlp)
1955	{
1956	uint64_t u64;
1957
1958	pHlp->pfnPrintf(pHlp, "Local APIC at %08llx:\n", pApic->apicbase);
1959	u64 = apicR3InfoReadReg(pDev, pApic, 0x2);
1960	pHlp->pfnPrintf(pHlp, " LAPIC ID : %08llx\n", u64);
1961	pHlp->pfnPrintf(pHlp, " APIC ID = %02llx\n", (u64 >> 24) & 0xff);
1962	u64 = apicR3InfoReadReg(pDev, pApic, 0x3);
1963	pHlp->pfnPrintf(pHlp, " APIC VER : %08llx\n", u64);
1964	pHlp->pfnPrintf(pHlp, " version = %02x\n", (int)RT_BYTE1(u64));
1965	pHlp->pfnPrintf(pHlp, " lvts = %d\n", (int)RT_BYTE3(u64) + 1);
1966	u64 = apicR3InfoReadReg(pDev, pApic, 0x8);
1967	pHlp->pfnPrintf(pHlp, " TPR : %08llx\n", u64);
1968	pHlp->pfnPrintf(pHlp, " task pri = %lld/%lld\n", (u64 >> 4) & 0xf, u64 & 0xf);
1969	u64 = apicR3InfoReadReg(pDev, pApic, 0xA);
1970	pHlp->pfnPrintf(pHlp, " PPR : %08llx\n", u64);
1971	pHlp->pfnPrintf(pHlp, " cpu pri = %lld/%lld\n", (u64 >> 4) & 0xf, u64 & 0xf);
1972	u64 = apicR3InfoReadReg(pDev, pApic, 0xD);
1973	pHlp->pfnPrintf(pHlp, " LDR : %08llx\n", u64);
1974	pHlp->pfnPrintf(pHlp, " log id = %02llx\n", (u64 >> 24) & 0xff);
1975	pHlp->pfnPrintf(pHlp, " DFR : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0xE));
1976	u64 = apicR3InfoReadReg(pDev, pApic, 0xF);
1977	pHlp->pfnPrintf(pHlp, " SVR : %08llx\n", u64);
1978	pHlp->pfnPrintf(pHlp, " focus = %s\n", u64 & RT_BIT(9) ? "check off" : "check on");
1979	pHlp->pfnPrintf(pHlp, " lapic = %s\n", u64 & RT_BIT(8) ? "ENABLED" : "DISABLED");
1980	pHlp->pfnPrintf(pHlp, " vector = %02x\n", (unsigned)RT_BYTE1(u64));
1981	pHlp->pfnPrintf(pHlp, " ISR : ");
1982	apicR3DumpVec(pDev, pApic, pHlp, 0x10);
1983	int iMax = Apic256BitReg_FindLastSetBit(&pApic->isr, -1);
1984	pHlp->pfnPrintf(pHlp, " highest = %02x\n", iMax == -1 ? 0 : iMax);
1985	pHlp->pfnPrintf(pHlp, " IRR : ");
1986	apicR3DumpVec(pDev, pApic, pHlp, 0x20);
1987	iMax = Apic256BitReg_FindLastSetBit(&pApic->irr, -1);
1988	pHlp->pfnPrintf(pHlp, " highest = %02X\n", iMax == -1 ? 0 : iMax);
1989	}
1990
1991
1992	/**
1993	* Print the more interesting Local APIC LVT entries.
1994	*
1995	* @param pDev The PDM device instance.
1996	* @param pApic The Local APIC in question.
1997	* @param pHlp The output helper.
1998	*/
1999	static void apicR3InfoLVT(APICDeviceInfo pDev, APICState pApic, PCDBGFINFOHLP pHlp)
2000	{
2001	static const char * const s_apszDeliveryModes[] =
2002	{
2003	"Fixed ", "Reserved", "SMI", "Reserved", "NMI", "INIT", "Reserved", "ExtINT"
2004	};
2005	uint64_t u64;
2006
2007	u64 = apicR3InfoReadReg(pDev, pApic, 0x32);
2008	pHlp->pfnPrintf(pHlp, " LVT Timer : %08llx\n", u64);
2009	pHlp->pfnPrintf(pHlp, " mode = %s\n", u64 & RT_BIT(17) ? "periodic" : "one-shot");
2010	pHlp->pfnPrintf(pHlp, " mask = %llu\n", (u64 >> 16) & 1);
2011	pHlp->pfnPrintf(pHlp, " status = %s\n", u64 & RT_BIT(12) ? "pending" : "idle");
2012	pHlp->pfnPrintf(pHlp, " vector = %02llx\n", u64 & 0xff);
2013	u64 = apicR3InfoReadReg(pDev, pApic, 0x35);
2014	pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08llx\n", u64);
2015	pHlp->pfnPrintf(pHlp, " mask = %llu\n", (u64 >> 16) & 1);
2016	pHlp->pfnPrintf(pHlp, " trigger = %s\n", u64 & RT_BIT(15) ? "level" : "edge");
2017	pHlp->pfnPrintf(pHlp, " rem irr = %llu\n", (u64 >> 14) & 1);
2018	pHlp->pfnPrintf(pHlp, " polarty = %llu\n", (u64 >> 13) & 1);
2019	pHlp->pfnPrintf(pHlp, " status = %s\n", u64 & RT_BIT(12) ? "pending" : "idle");
2020	pHlp->pfnPrintf(pHlp, " delivry = %s\n", s_apszDeliveryModes[(u64 >> 8) & 7]);
2021	pHlp->pfnPrintf(pHlp, " vector = %02llx\n", u64 & 0xff);
2022	u64 = apicR3InfoReadReg(pDev, pApic, 0x36);
2023	pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08llx\n", u64);
2024	pHlp->pfnPrintf(pHlp, " mask = %llu\n", (u64 >> 16) & 1);
2025	pHlp->pfnPrintf(pHlp, " trigger = %s\n", u64 & RT_BIT(15) ? "level" : "edge");
2026	pHlp->pfnPrintf(pHlp, " rem irr = %lld\n", (u64 >> 14) & 1);
2027	pHlp->pfnPrintf(pHlp, " polarty = %lld\n", (u64 >> 13) & 1);
2028	pHlp->pfnPrintf(pHlp, " status = %s\n", u64 & RT_BIT(12) ? "pending" : "idle");
2029	pHlp->pfnPrintf(pHlp, " delivry = %s\n", s_apszDeliveryModes[(u64 >> 8) & 7]);
2030	pHlp->pfnPrintf(pHlp, " vector = %02llx\n", u64 & 0xff);
2031	}
2032
2033
2034	/**
2035	* Print LAPIC timer state.
2036	*
2037	* @param pDev The PDM device instance.
2038	* @param pApic The Local APIC in question.
2039	* @param pHlp The output helper.
2040	*/
2041	static void apicR3InfoTimer(APICDeviceInfo pDev, APICState pApic, PCDBGFINFOHLP pHlp)
2042	{
2043	pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
2044	pHlp->pfnPrintf(pHlp, " Initial count : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0x38));
2045	pHlp->pfnPrintf(pHlp, " Current count : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0x39));
2046	uint64_t u64 = apicR3InfoReadReg(pDev, pApic, 0x3e);
2047	pHlp->pfnPrintf(pHlp, " Divide config : %08llx\n", u64);
2048	unsigned uDivider = ((u64 >> 1) & 0x04) \| (u64 & 0x03);
2049	pHlp->pfnPrintf(pHlp, " divider = %u\n", uDivider == 7 ? 1 : 2 << uDivider);
2050	}
2051
2052
2053	/**
2054	* @callback_method_impl{FNDBGFHANDLERDEV,
2055	* Dumps the Local APIC state according to given argument.}
2056	*/
2057	static DECLCALLBACK(void) apicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2058	{
2059	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2060	APICState *pApic = getLapic(pDev);
2061
2062	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2063	apicR3InfoBasic(pDev, pApic, pHlp);
2064	else if (!strcmp(pszArgs, "lvt"))
2065	apicR3InfoLVT(pDev, pApic, pHlp);
2066	else if (!strcmp(pszArgs, "timer"))
2067	apicR3InfoTimer(pDev, pApic, pHlp);
2068	else
2069	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
2070	}
2071
2072
2073	/**
2074	* @copydoc FNSSMDEVLIVEEXEC
2075	*/
2076	static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
2077	{
2078	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2079
2080	SSMR3PutU32( pSSM, pDev->cCpus);
2081	SSMR3PutBool(pSSM, pDev->fIoApic);
2082	SSMR3PutU32( pSSM, pDev->enmVersion);
2083	AssertCompile(PDMAPICVERSION_APIC == 2);
2084
2085	return VINF_SSM_DONT_CALL_AGAIN;
2086	}
2087
2088
2089	/**
2090	* @copydoc FNSSMDEVSAVEEXEC
2091	*/
2092	static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2093	{
2094	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2095
2096	/* config */
2097	apicR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
2098
2099	/* save all APICs data / /* @todo: is it correct? */
2100	APIC_FOREACH_BEGIN(pDev);
2101	apic_save(pSSM, pCurApic);
2102	APIC_FOREACH_END();
2103
2104	return VINF_SUCCESS;
2105	}
2106
2107	/**
2108	* @copydoc FNSSMDEVLOADEXEC
2109	*/
2110	static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2111	{
2112	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2113
2114	if ( uVersion != APIC_SAVED_STATE_VERSION
2115	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
2116	&& uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
2117	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2118
2119	/* config */
2120	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
2121	{
2122	uint32_t cCpus;
2123	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2124	if (cCpus != pDev->cCpus)
2125	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pDev->cCpus);
2126
2127	bool fIoApic;
2128	rc = SSMR3GetBool(pSSM, &fIoApic); AssertRCReturn(rc, rc);
2129	if (fIoApic != pDev->fIoApic)
2130	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pDev->fIoApic);
2131
2132	uint32_t uApicVersion;
2133	rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
2134	if (uApicVersion != (uint32_t)pDev->enmVersion)
2135	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pDev->enmVersion);
2136	}
2137
2138	if (uPass != SSM_PASS_FINAL)
2139	return VINF_SUCCESS;
2140
2141	/* load all APICs data / /* @todo: is it correct? */
2142	APIC_LOCK(pDev, VERR_INTERNAL_ERROR_3);
2143
2144	int rc = VINF_SUCCESS;
2145	APIC_FOREACH_BEGIN(pDev);
2146	rc = apic_load(pSSM, pCurApic, uVersion);
2147	if (RT_FAILURE(rc))
2148	break;
2149	APIC_FOREACH_END();
2150
2151	APIC_UNLOCK(pDev);
2152	return rc;
2153	}
2154
2155	/**
2156	* @copydoc FNPDMDEVRESET
2157	*/
2158	static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
2159	{
2160	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2161	TMTimerLock(pDev->paLapicsR3[0].pTimerR3, VERR_IGNORED);
2162	APIC_LOCK_VOID(pDev, VERR_IGNORED);
2163
2164	/* Reset all APICs. */
2165	for (VMCPUID i = 0; i < pDev->cCpus; i++)
2166	{
2167	APICState *pApic = &pDev->CTX_SUFF(paLapics)[i];
2168	TMTimerStop(pApic->CTX_SUFF(pTimer));
2169
2170	/* Clear LAPIC state as if an INIT IPI was sent. */
2171	apic_init_ipi(pDev, pApic);
2172
2173	/* The IDs are not touched by apic_init_ipi() and must be reset now. */
2174	pApic->arb_id = pApic->id = i;
2175	Assert(pApic->id == pApic->phys_id); /* The two should match again. */
2176
2177	/* Reset should re-enable the APIC, see comment in msi.h */
2178	pApic->apicbase = VBOX_MSI_ADDR_BASE \| MSR_IA32_APICBASE_ENABLE;
2179	if (pApic->phys_id == 0)
2180	pApic->apicbase \|= MSR_IA32_APICBASE_BSP;
2181
2182	/* Clear any pending APIC interrupt action flag. */
2183	cpuClearInterrupt(pDev, pApic);
2184	}
2185	/** @todo r=bird: Why is this done everytime, while the constructor first
2186	* checks the CPUID? Who is right? */
2187	pDev->pApicHlpR3->pfnChangeFeature(pDev->pDevInsR3, pDev->enmVersion);
2188
2189	APIC_UNLOCK(pDev);
2190	TMTimerUnlock(pDev->paLapicsR3[0].pTimerR3);
2191	}
2192
2193
2194	/**
2195	* @copydoc FNPDMDEVRELOCATE
2196	*/
2197	static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2198	{
2199	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2200	pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2201	pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2202	pDev->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pDev->paLapicsR3);
2203	pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2204	for (uint32_t i = 0; i < pDev->cCpus; i++)
2205	pDev->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pDev->paLapicsR3[i].pTimerR3);
2206	}
2207
2208
2209	/**
2210	* Initializes the state of one local APIC.
2211	*
2212	* @param pApic The Local APIC state to init.
2213	* @param id The Local APIC ID.
2214	*/
2215	DECLINLINE(void) initApicData(APICState *pApic, uint8_t id)
2216	{
2217	memset(pApic, 0, sizeof(*pApic));
2218
2219	/* See comment in msi.h for LAPIC base info. */
2220	pApic->apicbase = VBOX_MSI_ADDR_BASE \| MSR_IA32_APICBASE_ENABLE;
2221	if (id == 0) /* Mark first CPU as BSP. */
2222	pApic->apicbase \|= MSR_IA32_APICBASE_BSP;
2223
2224	for (int i = 0; i < APIC_LVT_NB; i++)
2225	pApic->lvt[i] = RT_BIT_32(16); /* mask LVT */
2226
2227	pApic->spurious_vec = 0xff;
2228	pApic->phys_id = id;
2229	pApic->id = id;
2230	}
2231
2232
2233	/**
2234	* @copydoc FNPDMDEVCONSTRUCT
2235	*/
2236	static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2237	{
2238	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2239	uint32_t i;
2240
2241	/*
2242	* Only single device instance.
2243	*/
2244	Assert(iInstance == 0);
2245
2246	/*
2247	* Validate configuration.
2248	*/
2249	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC\|RZEnabled\|NumCPUs", "");
2250
2251	bool fIoApic;
2252	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fIoApic, true);
2253	if (RT_FAILURE(rc))
2254	return PDMDEV_SET_ERROR(pDevIns, rc,
2255	N_("Configuration error: Failed to read \"IOAPIC\""));
2256
2257	bool fRZEnabled;
2258	rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
2259	if (RT_FAILURE(rc))
2260	return PDMDEV_SET_ERROR(pDevIns, rc,
2261	N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
2262
2263	uint32_t cCpus;
2264	rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
2265	if (RT_FAILURE(rc))
2266	return PDMDEV_SET_ERROR(pDevIns, rc,
2267	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2268
2269	Log(("APIC: cCpus=%d fRZEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fRZEnabled, fIoApic));
2270	if (cCpus > 255)
2271	return PDMDEV_SET_ERROR(pDevIns, rc,
2272	N_("Configuration error: Invalid value for \"NumCPUs\""));
2273
2274	/*
2275	* Init the data.
2276	*/
2277	pDev->pDevInsR3 = pDevIns;
2278	pDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2279	pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2280	pDev->cCpus = cCpus;
2281	pDev->fIoApic = fIoApic;
2282	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2283	pDev->enmVersion = PDMAPICVERSION_APIC;
2284
2285	/* Disable locking in this device. */
2286	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2287	AssertRCReturn(rc, rc);
2288
2289	PVM pVM = PDMDevHlpGetVM(pDevIns);
2290
2291	/*
2292	* We are not freeing this memory, as it's automatically released when guest exits.
2293	*/
2294	rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->paLapicsR3);
2295	if (RT_FAILURE(rc))
2296	return VERR_NO_MEMORY;
2297	pDev->paLapicsR0 = MMHyperR3ToR0(pVM, pDev->paLapicsR3);
2298	pDev->paLapicsRC = MMHyperR3ToRC(pVM, pDev->paLapicsR3);
2299
2300	for (i = 0; i < cCpus; i++)
2301	initApicData(&pDev->paLapicsR3[i], i);
2302
2303	/*
2304	* Register the APIC.
2305	*/
2306	PDMAPICREG ApicReg;
2307	ApicReg.u32Version = PDM_APICREG_VERSION;
2308	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2309	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2310	ApicReg.pfnSetBaseR3 = apicSetBase;
2311	ApicReg.pfnGetBaseR3 = apicGetBase;
2312	ApicReg.pfnSetTPRR3 = apicSetTPR;
2313	ApicReg.pfnGetTPRR3 = apicGetTPR;
2314	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2315	ApicReg.pfnReadMSRR3 = apicReadMSR;
2316	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2317	ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
2318	if (fRZEnabled)
2319	{
2320	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2321	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2322	ApicReg.pszSetBaseRC = "apicSetBase";
2323	ApicReg.pszGetBaseRC = "apicGetBase";
2324	ApicReg.pszSetTPRRC = "apicSetTPR";
2325	ApicReg.pszGetTPRRC = "apicGetTPR";
2326	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2327	ApicReg.pszReadMSRRC = "apicReadMSR";
2328	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2329	ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
2330
2331	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2332	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2333	ApicReg.pszSetBaseR0 = "apicSetBase";
2334	ApicReg.pszGetBaseR0 = "apicGetBase";
2335	ApicReg.pszSetTPRR0 = "apicSetTPR";
2336	ApicReg.pszGetTPRR0 = "apicGetTPR";
2337	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2338	ApicReg.pszReadMSRR0 = "apicReadMSR";
2339	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2340	ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
2341	}
2342	else
2343	{
2344	ApicReg.pszGetInterruptRC = NULL;
2345	ApicReg.pszHasPendingIrqRC = NULL;
2346	ApicReg.pszSetBaseRC = NULL;
2347	ApicReg.pszGetBaseRC = NULL;
2348	ApicReg.pszSetTPRRC = NULL;
2349	ApicReg.pszGetTPRRC = NULL;
2350	ApicReg.pszWriteMSRRC = NULL;
2351	ApicReg.pszReadMSRRC = NULL;
2352	ApicReg.pszBusDeliverRC = NULL;
2353	ApicReg.pszLocalInterruptRC = NULL;
2354
2355	ApicReg.pszGetInterruptR0 = NULL;
2356	ApicReg.pszHasPendingIrqR0 = NULL;
2357	ApicReg.pszSetBaseR0 = NULL;
2358	ApicReg.pszGetBaseR0 = NULL;
2359	ApicReg.pszSetTPRR0 = NULL;
2360	ApicReg.pszGetTPRR0 = NULL;
2361	ApicReg.pszWriteMSRR0 = NULL;
2362	ApicReg.pszReadMSRR0 = NULL;
2363	ApicReg.pszBusDeliverR0 = NULL;
2364	ApicReg.pszLocalInterruptR0 = NULL;
2365	}
2366
2367	rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pDev->pApicHlpR3);
2368	AssertLogRelRCReturn(rc, rc);
2369	pDev->pCritSectR3 = pDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2370
2371	/*
2372	* The CPUID feature bit.
2373	*/
2374	/** @todo r=bird: See remark in the apicR3Reset. */
2375	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2376	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2377	if (u32Eax >= 1)
2378	{
2379	if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
2380	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2381	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2382	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2383	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2384	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2385	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2386	{
2387	LogRel(("Activating Local APIC\n"));
2388	pDev->pApicHlpR3->pfnChangeFeature(pDevIns, pDev->enmVersion);
2389	}
2390	}
2391
2392	/*
2393	* Register the MMIO range.
2394	*/
2395	/** @todo: shall reregister, if base changes. */
2396	uint32_t ApicBase = pDev->paLapicsR3[0].apicbase & ~0xfff;
2397	rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pDev,
2398	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2399	apicMMIOWrite, apicMMIORead, "APIC Memory");
2400	if (RT_FAILURE(rc))
2401	return rc;
2402
2403	if (fRZEnabled)
2404	{
2405	pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2406	pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2407	rc = PDMDevHlpMMIORegisterRC(pDevIns, ApicBase, 0x1000, NIL_RTRCPTR /pvUser/, "apicMMIOWrite", "apicMMIORead");
2408	if (RT_FAILURE(rc))
2409	return rc;
2410
2411	pDev->pApicHlpR0 = pDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2412	pDev->pCritSectR0 = pDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2413	rc = PDMDevHlpMMIORegisterR0(pDevIns, ApicBase, 0x1000, NIL_RTR0PTR /pvUser/, "apicMMIOWrite", "apicMMIORead");
2414	if (RT_FAILURE(rc))
2415	return rc;
2416	}
2417
2418	/*
2419	* Create the APIC timers.
2420	*/
2421	for (i = 0; i < cCpus; i++)
2422	{
2423	APICState *pApic = &pDev->paLapicsR3[i];
2424	pApic->pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_USER, "APIC Timer #%u", i);
2425	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pApic,
2426	TMTIMER_FLAGS_NO_CRIT_SECT, pApic->pszDesc, &pApic->pTimerR3);
2427	if (RT_FAILURE(rc))
2428	return rc;
2429	pApic->pTimerR0 = TMTimerR0Ptr(pApic->pTimerR3);
2430	pApic->pTimerRC = TMTimerRCPtr(pApic->pTimerR3);
2431	TMR3TimerSetCritSect(pApic->pTimerR3, pDev->pCritSectR3);
2432	}
2433
2434	/*
2435	* Saved state.
2436	*/
2437	rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pDev),
2438	apicR3LiveExec, apicR3SaveExec, apicR3LoadExec);
2439	if (RT_FAILURE(rc))
2440	return rc;
2441
2442	/*
2443	* Register debugger info callback.
2444	*/
2445	PDMDevHlpDBGFInfoRegister(pDevIns, "apic", "Display Local APIC state for current CPU. "
2446	"Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", apicR3Info);
2447
2448	#ifdef VBOX_WITH_STATISTICS
2449	/*
2450	* Statistics.
2451	*/
2452	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2453	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2454	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2455	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2456	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2457	for (i = 0; i < cCpus; i++)
2458	{
2459	APICState *pApic = &pDev->paLapicsR3[i];
2460	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
2461	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
2462	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
2463	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
2464	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
2465	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
2466	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
2467	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
2468	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
2469	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
2470	}
2471	#endif
2472
2473	return VINF_SUCCESS;
2474	}
2475
2476
2477	/**
2478	* APIC device registration structure.
2479	*/
2480	const PDMDEVREG g_DeviceAPIC =
2481	{
2482	/* u32Version */
2483	PDM_DEVREG_VERSION,
2484	/* szName */
2485	"apic",
2486	/* szRCMod */
2487	"VBoxDD2GC.gc",
2488	/* szR0Mod */
2489	"VBoxDD2R0.r0",
2490	/* pszDescription */
2491	"Advanced Programmable Interrupt Controller (APIC) Device",
2492	/* fFlags */
2493	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2494	/* fClass */
2495	PDM_DEVREG_CLASS_PIC,
2496	/* cMaxInstances */
2497	1,
2498	/* cbInstance */
2499	sizeof(APICState),
2500	/* pfnConstruct */
2501	apicR3Construct,
2502	/* pfnDestruct */
2503	NULL,
2504	/* pfnRelocate */
2505	apicR3Relocate,
2506	/* pfnIOCtl */
2507	NULL,
2508	/* pfnPowerOn */
2509	NULL,
2510	/* pfnReset */
2511	apicR3Reset,
2512	/* pfnSuspend */
2513	NULL,
2514	/* pfnResume */
2515	NULL,
2516	/* pfnAttach */
2517	NULL,
2518	/* pfnDetach */
2519	NULL,
2520	/* pfnQueryInterface. */
2521	NULL,
2522	/* pfnInitComplete */
2523	NULL,
2524	/* pfnPowerOff */
2525	NULL,
2526	/* pfnSoftReset */
2527	NULL,
2528	/* u32VersionEnd */
2529	PDM_DEVREG_VERSION
2530	};
2531
2532	#endif /* IN_RING3 */
2533	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2534

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 42537

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