| 1 | ;;
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| 2 | ;; Copyright (C) 2006-2015 Oracle Corporation
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| 3 | ;;
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| 4 | ;; This file is part of VirtualBox Open Source Edition (OSE), as
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| 5 | ;; available from http://www.alldomusa.eu.org. This file is free software;
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| 6 | ;; you can redistribute it and/or modify it under the terms of the GNU
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| 7 | ;; General Public License (GPL) as published by the Free Software
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| 8 | ;; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 9 | ;; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 10 | ;; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 11 | ;; --------------------------------------------------------------------
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| 12 | ;;
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| 13 | ;; This code is based on:
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| 14 | ;;
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| 15 | ;; ROM BIOS for use with Bochs/Plex86/QEMU emulation environment
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| 16 | ;;
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| 17 | ;; Copyright (C) 2002 MandrakeSoft S.A.
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| 18 | ;;
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| 19 | ;; MandrakeSoft S.A.
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| 20 | ;; 43, rue d'Aboukir
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| 21 | ;; 75002 Paris - France
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| 22 | ;; http://www.linux-mandrake.com/
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| 23 | ;; http://www.mandrakesoft.com/
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| 24 | ;;
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| 25 | ;; This library is free software; you can redistribute it and/or
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| 26 | ;; modify it under the terms of the GNU Lesser General Public
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| 27 | ;; License as published by the Free Software Foundation; either
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| 28 | ;; version 2 of the License, or (at your option) any later version.
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| 29 | ;;
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| 30 | ;; This library is distributed in the hope that it will be useful,
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| 31 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 32 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 33 | ;; Lesser General Public License for more details.
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| 34 | ;;
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| 35 | ;; You should have received a copy of the GNU Lesser General Public
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| 36 | ;; License along with this library; if not, write to the Free Software
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| 37 | ;; Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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| 38 | ;;
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| 39 | ;;
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| 40 |
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| 41 |
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| 42 | ; Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 43 | ; other than GPL or LGPL is available it will apply instead, Oracle elects to use only
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| 44 | ; the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 45 | ; a choice of LGPL license versions is made available with the language indicating
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| 46 | ; that LGPLv2 or any later version may be used, or where a choice of which version
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| 47 | ; of the LGPL is applied is otherwise unspecified.
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| 48 |
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| 49 | include pcicfg.inc
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| 50 |
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| 51 | if BX_PCIBIOS
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| 52 |
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| 53 | ifdef DEBUG
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| 54 |
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| 55 | ; Publics for easier debugging and disassembly
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| 56 |
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| 57 | public pcibios_init_iomem_bases
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| 58 | public pci_init_io_loop1
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| 59 | public pci_init_io_loop2
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| 60 | public init_io_base
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| 61 | public next_pci_base
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| 62 | public enable_iomem_space
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| 63 | public next_pci_dev
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| 64 | public pcibios_init_set_elcr
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| 65 | public is_master_pic
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| 66 | public pcibios_init_irqs
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| 67 | public pci_init_irq_loop1
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| 68 | public pci_init_irq_loop2
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| 69 | public pci_test_int_pin
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| 70 | public pirq_found
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| 71 | public next_pci_func
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| 72 | public next_pir_entry
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| 73 | public pci_init_end
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| 74 |
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| 75 | endif
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| 76 |
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| 77 | .386
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| 78 |
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| 79 | if not BX_ROMBIOS32
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| 80 | pci_irq_list:
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| 81 | db 11, 10, 9, 11
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| 82 |
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| 83 | pcibios_init_sel_reg:
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| 84 | push eax
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| 85 | mov eax, 800000h
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| 86 | mov ax, bx
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| 87 | shl eax, 8
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| 88 | and dl, 0FCh
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| 89 | or al, dl
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| 90 | mov dx, PCI_CFG1
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| 91 | out dx, eax
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| 92 | pop eax
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| 93 | ret
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| 94 |
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| 95 | pcibios_init_iomem_bases:
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| 96 | push bp
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| 97 | mov bp, sp
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| 98 | ifdef VBOX
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| 99 | mov eax,19200509
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| 100 | mov dx,410h
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| 101 | out dx, eax
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| 102 | else
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| 103 | ; This incomplete PCI resource setup code is less functional than the PCI
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| 104 | ; resource assignment created by the fake PCI BIOS and is therefore disabled.
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| 105 | ; Blindly enabling everything on the root bus (including bus mastering!) can
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| 106 | ; only be called buggy. It causes the trouble with AMD PCNet which it then
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| 107 | ; tries to work around, but that still contains a race.
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| 108 | mov eax, 0E0000000h ; base for memory init
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| 109 | push eax
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| 110 | mov ax, 0D000h ; base for i/o init
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| 111 | push ax
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| 112 | mov ax, 010h ; start at base address #0
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| 113 | push ax
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| 114 | mov bx, 8
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| 115 | pci_init_io_loop1:
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| 116 | mov dl, 0
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| 117 | call pcibios_init_sel_reg
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| 118 | mov dx, PCI_CFG2
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| 119 | in ax, dx
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| 120 | cmp ax, 0FFFFh
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| 121 | jz next_pci_dev
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| 122 |
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| 123 | ifndef VBOX ; This currently breaks restoring a previously saved state.
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| 124 | mov dl, 4 ; disable i/o and memory space access
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| 125 | call pcibios_init_sel_reg
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| 126 | mov dx, PCI_CFG2
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| 127 | in al, dx
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| 128 | and al, 0FCh
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| 129 | out dx, al
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| 130 | pci_init_io_loop2:
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| 131 | mov dl, [bp-8]
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| 132 | call pcibios_init_sel_reg
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| 133 | mov dx, PCI_CFG2
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| 134 | in eax, dx
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| 135 | test al, 1
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| 136 | jnz init_io_base
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| 137 |
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| 138 | mov ecx, eax
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| 139 | mov eax, 0FFFFFFFFh
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| 140 | out dx, eax
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| 141 | in eax, dx
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| 142 | cmp eax, ecx
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| 143 | je next_pci_base
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| 144 | xor eax, 0FFFFFFFFh
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| 145 | mov ecx, eax
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| 146 | mov eax, [bp-4]
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| 147 | out dx, eax
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| 148 | add eax, ecx ; calculate next free mem base
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| 149 | add eax, 01000000h
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| 150 | and eax, 0FF000000h
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| 151 | mov [bp-4], eax
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| 152 | jmp next_pci_base
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| 153 |
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| 154 | init_io_base:
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| 155 | mov cx, ax
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| 156 | mov ax, 0FFFFh
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| 157 | out dx, eax
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| 158 | in eax, dx
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| 159 | cmp ax, cx
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| 160 | je next_pci_base
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| 161 |
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| 162 | xor ax, 0FFFEh
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| 163 | mov cx, ax
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| 164 | mov ax, [bp-6]
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| 165 | out dx, eax
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| 166 | add ax, cx ; calculate next free i/o base
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| 167 | add ax, 00100h
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| 168 | and ax, 0FF00h
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| 169 | mov [bp-6], ax
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| 170 | next_pci_base:
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| 171 | mov al, [bp-8]
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| 172 | add al, 4
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| 173 | cmp al, 28h
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| 174 | je enable_iomem_space
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| 175 |
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| 176 | mov byte ptr[bp-8], al
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| 177 | jmp pci_init_io_loop2
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| 178 | endif ; !VBOX
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| 179 |
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| 180 | enable_iomem_space:
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| 181 | mov dl, 4 ;; enable i/o and memory space access if available
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| 182 | call pcibios_init_sel_reg
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| 183 | mov dx, PCI_CFG2
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| 184 | in al, dx
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| 185 | or al, 7
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| 186 | out dx, al
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| 187 | ifdef VBOX
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| 188 | mov dl, 0 ; check if PCI device is AMD PCNet
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| 189 | call pcibios_init_sel_reg
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| 190 | mov dx, PCI_CFG2
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| 191 | in eax, dx
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| 192 | cmp eax, 020001022h
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| 193 | jne next_pci_dev
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| 194 |
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| 195 | mov dl, 10h ; get I/O address
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| 196 | call pcibios_init_sel_reg
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| 197 | mov dx, PCI_CFG2
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| 198 | in ax, dx
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| 199 | and ax, 0FFFCh
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| 200 | mov cx, ax
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| 201 | mov dx, cx
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| 202 | add dx, 14h ; reset register if PCNet is in word I/O mode
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| 203 | in ax, dx ; reset is performed by reading the reset register
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| 204 | mov dx, cx
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| 205 | add dx, 18h ; reset register if PCNet is in word I/O mode
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| 206 | in eax, dx ; reset is performed by reading the reset register
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| 207 | endif ; VBOX
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| 208 | next_pci_dev:
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| 209 | mov byte ptr[bp-8], 10h
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| 210 | inc bx
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| 211 | cmp bx, 0100h
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| 212 | jne pci_init_io_loop1
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| 213 | endif ; !VBOX
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| 214 | mov sp, bp
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| 215 | pop bp
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| 216 | ret
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| 217 |
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| 218 | pcibios_init_set_elcr:
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| 219 | push ax
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| 220 | push cx
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| 221 | mov dx, 04D0h
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| 222 | test al, 8
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| 223 | jz is_master_pic
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| 224 |
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| 225 | inc dx
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| 226 | and al, 7
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| 227 | is_master_pic:
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| 228 | mov cl, al
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| 229 | mov bl, 1
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| 230 | shl bl, cl
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| 231 | in al, dx
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| 232 | or al, bl
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| 233 | out dx, al
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| 234 | pop cx
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| 235 | pop ax
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| 236 | ret
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| 237 |
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| 238 | pcibios_init_irqs:
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| 239 | push ds
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| 240 | push bp
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| 241 | mov ax, 0F000h
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| 242 | mov ds, ax
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| 243 | ifndef VBOX
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| 244 | ; this code works OK, but it's unnecessary effort since the fake PCI BIOS
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| 245 | ; already configured the IRQ lines and the ELCR correctly
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| 246 | mov dx, 04D0h ;; reset ELCR1 + ELCR2
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| 247 | mov al, 0
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| 248 | out dx, al
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| 249 | inc dx
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| 250 | out dx, al
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| 251 | mov si, pci_routing_table_structure
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| 252 | mov bh, [si+8]
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| 253 | mov bl, [si+9]
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| 254 | mov dl, 0
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| 255 | call pcibios_init_sel_reg
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| 256 | mov dx, PCI_CFG2
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| 257 | in eax, dx
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| 258 | cmp eax, [si+12] ;; check irq router
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| 259 | jne pci_init_end
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| 260 |
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| 261 | mov dl, [si+34]
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| 262 | call pcibios_init_sel_reg
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| 263 | push bx ;; save irq router bus + devfunc
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| 264 | mov dx, PCI_CFG2
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| 265 | mov ax, 8080h
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| 266 | out dx, ax ;; reset PIRQ route control
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| 267 | add dx, 2
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| 268 | out dx, ax
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| 269 | mov ax, [si+6]
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| 270 | sub ax, 20h
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| 271 | shr ax, 4
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| 272 | mov cx, ax
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| 273 | add si, 20h ;; set pointer to 1st entry
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| 274 | mov bp, sp
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| 275 | mov ax, pci_irq_list
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| 276 | push ax
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| 277 | xor ax, ax
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| 278 | push ax
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| 279 | pci_init_irq_loop1:
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| 280 | mov bh, [si]
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| 281 | mov bl, [si+1]
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| 282 | pci_init_irq_loop2:
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| 283 | mov dl, 0
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| 284 | call pcibios_init_sel_reg
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| 285 | mov dx, PCI_CFG2
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| 286 | in ax, dx
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| 287 | cmp ax, 0FFFFh
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| 288 | jnz pci_test_int_pin
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| 289 |
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| 290 | test bl, 7
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| 291 | jz next_pir_entry
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| 292 |
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| 293 | jmp next_pci_func
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| 294 |
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| 295 | pci_test_int_pin:
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| 296 | mov dl, 3Ch
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| 297 | call pcibios_init_sel_reg
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| 298 | mov dx, PCI_CFG2 + 1 ; access config space at 3Dh
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| 299 | in al, dx
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| 300 | and al, 7
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| 301 | jz next_pci_func
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| 302 |
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| 303 | dec al ;; determine pirq reg
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| 304 | mov dl, 3
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| 305 | mul dl
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| 306 | add al, 2
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| 307 | xor ah, ah
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| 308 | mov bx, ax
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| 309 | mov al, [si+bx]
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| 310 | mov dl, al
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| 311 | mov bx, [bp]
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| 312 | call pcibios_init_sel_reg
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| 313 | mov dx, PCI_CFG2
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| 314 | and al, 3
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| 315 | add dl, al
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| 316 | in al, dx
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| 317 | cmp al, 80h
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| 318 | jb pirq_found
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| 319 |
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| 320 | mov bx, [bp-2] ;; pci irq list pointer
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| 321 | mov al, [bx]
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| 322 | out dx, al
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| 323 | inc bx
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| 324 | mov [bp-2], bx
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| 325 | call pcibios_init_set_elcr
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| 326 | pirq_found:
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| 327 | mov bh, [si]
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| 328 | mov bl, [si+1]
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| 329 | add bl, [bp-3] ;; pci function number
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| 330 | mov dl, 3Ch
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| 331 | call pcibios_init_sel_reg
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| 332 | mov dx, PCI_CFG2
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| 333 | out dx, al
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| 334 | next_pci_func:
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| 335 | inc byte ptr[bp-3]
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| 336 | inc bl
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| 337 | test bl, 7
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| 338 | jnz pci_init_irq_loop2
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| 339 |
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| 340 | next_pir_entry:
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| 341 | add si, 10h
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| 342 | mov byte ptr[bp-3], 0
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| 343 | loop pci_init_irq_loop1
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| 344 |
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| 345 | mov sp, bp
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| 346 | pop bx
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| 347 | pci_init_end:
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| 348 | endif
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| 349 | pop bp
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| 350 | pop ds
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| 351 | ret
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| 352 |
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| 353 | endif ; !BX_ROMBIOS32
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| 354 |
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| 355 | endif ; BX_PCIBIOS
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| 356 |
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| 357 | SET_DEFAULT_CPU_286
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| 358 |
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