DevVGA-SVGA.cpp@ 88774

最後變更在這個檔案從88774是 88774,由 vboxsync 提交於 4 年前
3D/VMSVGA: Corrected VBE_DISPI_MAX_(X/Y)RES typo
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1	/* $Id: DevVGA-SVGA.cpp 88774 2021-04-29 09:59:31Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.alldomusa.eu.org. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
159	#ifdef VBOX_WITH_VMSVGA3D
160	# include "DevVGA-SVGA3d.h"
161	# ifdef RT_OS_DARWIN
162	# include "DevVGA-SVGA3d-cocoa.h"
163	# endif
164	# ifdef RT_OS_LINUX
165	# ifdef IN_RING3
166	# include "DevVGA-SVGA3d-glLdr.h"
167	# endif
168	# endif
169	#endif
170	#ifdef IN_RING3
171	#include "DevVGA-SVGA-internal.h"
172	#endif
173
174
175	/*********************************************************************************************************************************
176	* Defined Constants And Macros *
177	*********************************************************************************************************************************/
178	/**
179	* Macro for checking if a fixed FIFO register is valid according to the
180	* current FIFO configuration.
181	*
182	* @returns true / false.
183	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
184	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
185	*/
186	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
187
188
189	/*********************************************************************************************************************************
190	* Structures and Typedefs *
191	*********************************************************************************************************************************/
192
193
194	/*********************************************************************************************************************************
195	* Internal Functions *
196	*********************************************************************************************************************************/
197	#ifdef IN_RING3
198	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
199	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
200	# endif
201	# ifdef DEBUG_GMR_ACCESS
202	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
203	# endif
204	#endif
205
206
207	/*********************************************************************************************************************************
208	* Global Variables *
209	*********************************************************************************************************************************/
210	#ifdef IN_RING3
211
212	/**
213	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
214	*/
215	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
216	{
217	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
218	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
219	SSMFIELD_ENTRY_TERM()
220	};
221
222	/**
223	* SSM descriptor table for the GMR structure.
224	*/
225	static SSMFIELD const g_aGMRFields[] =
226	{
227	SSMFIELD_ENTRY( GMR, cMaxPages),
228	SSMFIELD_ENTRY( GMR, cbTotal),
229	SSMFIELD_ENTRY( GMR, numDescriptors),
230	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
231	SSMFIELD_ENTRY_TERM()
232	};
233
234	/**
235	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
236	*/
237	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
238	{
239	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
240	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
241	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
242	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
243	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
244	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
250	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
251	SSMFIELD_ENTRY_TERM()
252	};
253
254	/**
255	* SSM descriptor table for the VMSVGAR3STATE structure.
256	*/
257	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
258	{
259	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
260	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
261	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
262	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
263	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
264	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
265	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
267	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
269	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
270	#ifdef VMSVGA_USE_EMT_HALT_CODE
271	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
272	#else
273	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
274	#endif
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
276	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
278	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
280	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
338
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
343
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
351	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
353	# endif
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
358
359	SSMFIELD_ENTRY_TERM()
360	};
361
362	/**
363	* SSM descriptor table for the VGAState.svga structure.
364	*/
365	static SSMFIELD const g_aVGAStateSVGAFields[] =
366	{
367	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
368	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
369	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
370	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
371	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
372	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
373	SSMFIELD_ENTRY( VMSVGAState, fBusy),
374	SSMFIELD_ENTRY( VMSVGAState, fTraces),
375	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
376	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
377	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
378	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
379	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
380	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
381	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
382	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
383	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
387	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
388	SSMFIELD_ENTRY( VMSVGAState, uWidth),
389	SSMFIELD_ENTRY( VMSVGAState, uHeight),
390	SSMFIELD_ENTRY( VMSVGAState, uBpp),
391	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
392	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
393	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
394	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
395	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
396	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
397	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
398	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
399	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
400	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
401	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
405	SSMFIELD_ENTRY_TERM()
406	};
407	#endif /* IN_RING3 */
408
409
410	/*********************************************************************************************************************************
411	* Internal Functions *
412	*********************************************************************************************************************************/
413	#ifdef IN_RING3
414	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
415	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
416	uint32_t uVersion, uint32_t uPass);
417	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
418	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
419	#endif /* IN_RING3 */
420
421
422	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
423	#if defined(LOG_ENABLED)
424	/**
425	* Index register string name lookup
426	*
427	* @returns Index register string or "UNKNOWN"
428	* @param pThis The shared VGA/VMSVGA state.
429	* @param idxReg The index register.
430	*/
431	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
432	{
433	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
434	switch (idxReg)
435	{
436	SVGA_CASE_ID2STR(SVGA_REG_ID);
437	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
438	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
439	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
440	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
441	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
442	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
443	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
444	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
445	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
446	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
447	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
448	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
449	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
450	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
451	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
452	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
453
454	/* ID 0 implementation only had the above registers, then the palette */
455	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
456	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
457	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
458	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
459	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
460	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
461	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
462	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
463	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
464	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
465	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
466	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
467	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
468	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
469	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
470	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
471	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
472
473	/* Legacy multi-monitor support */
474	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
475	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
476	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
477	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
478	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
479	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
480	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
481
482	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
483	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
484	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
485	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
486
487	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
488	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
489	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
490	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
491	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
492	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
493	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
494	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
495	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
496	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
497	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
498	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
499	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
500	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
501	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
502	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
503	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
504	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
505	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
506	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
507	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
508	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
509	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
510	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
511	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
512	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
513	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
514	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
515	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
516	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
517	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
518	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
519	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
520
521	default:
522	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
523	return "SVGA_SCRATCH_BASE reg";
524	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
525	return "SVGA_PALETTE_BASE reg";
526	return "UNKNOWN";
527	}
528	}
529	#endif /* LOG_ENABLED */
530
531	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
532	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
533	{
534	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
535	switch (idxDevCap)
536	{
537	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
538	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
539	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
540	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
541	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
542	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
543	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
544	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
545	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
546	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
547	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
798
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
800
801	default:
802	break;
803	}
804	return "UNKNOWN";
805	}
806	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
807	#undef SVGA_CASE_ID2STR
808
809
810	#ifdef IN_RING3
811
812	/**
813	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
814	*/
815	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
816	{
817	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
818	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
819
820	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
821	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
822
823	/** @todo Test how it interacts with multiple screen objects. */
824	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
825	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
826	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
827
828	if (x < uWidth)
829	{
830	pThis->svga.viewport.x = x;
831	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
832	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
833	}
834	else
835	{
836	pThis->svga.viewport.x = uWidth;
837	pThis->svga.viewport.cx = 0;
838	pThis->svga.viewport.xRight = uWidth;
839	}
840	if (y < uHeight)
841	{
842	pThis->svga.viewport.y = y;
843	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
844	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
845	pThis->svga.viewport.yHighWC = uHeight - y;
846	}
847	else
848	{
849	pThis->svga.viewport.y = uHeight;
850	pThis->svga.viewport.cy = 0;
851	pThis->svga.viewport.yLowWC = 0;
852	pThis->svga.viewport.yHighWC = 0;
853	}
854
855	# ifdef VBOX_WITH_VMSVGA3D
856	/*
857	* Now inform the 3D backend.
858	*/
859	if (pThis->svga.f3DEnabled)
860	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
861	# else
862	RT_NOREF(OldViewport);
863	# endif
864	}
865
866
867	/**
868	* Updating screen information in API
869	*
870	* @param pThis The The shared VGA/VMSVGA instance data.
871	* @param pThisCC The VGA/VMSVGA state for ring-3.
872	*/
873	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
874	{
875	int rc;
876
877	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
878
879	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
880	{
881	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
882	if (!pScreen->fModified)
883	continue;
884
885	pScreen->fModified = false;
886
887	VBVAINFOVIEW view;
888	RT_ZERO(view);
889	view.u32ViewIndex = pScreen->idScreen;
890	// view.u32ViewOffset = 0;
891	view.u32ViewSize = pThis->vram_size;
892	view.u32MaxScreenSize = pThis->vram_size;
893
894	VBVAINFOSCREEN screen;
895	RT_ZERO(screen);
896	screen.u32ViewIndex = pScreen->idScreen;
897
898	if (pScreen->fDefined)
899	{
900	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
901	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
902	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
903	{
904	Assert(pThis->svga.fGFBRegisters);
905	continue;
906	}
907
908	screen.i32OriginX = pScreen->xOrigin;
909	screen.i32OriginY = pScreen->yOrigin;
910	screen.u32StartOffset = pScreen->offVRAM;
911	screen.u32LineSize = pScreen->cbPitch;
912	screen.u32Width = pScreen->cWidth;
913	screen.u32Height = pScreen->cHeight;
914	screen.u16BitsPerPixel = pScreen->cBpp;
915	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
916	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
917	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
918	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
919	}
920	else
921	{
922	/* Screen is destroyed. */
923	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
924	}
925
926	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
927	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
928	AssertRC(rc);
929	}
930	}
931
932
933	/**
934	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
935	*
936	* Used to update screen offsets (positions) since appearently vmwgfx fails to
937	* pass correct offsets thru FIFO.
938	*/
939	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
940	{
941	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
942	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
943	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
944
945	AssertReturnVoid(pSVGAState);
946
947	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
948	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
949	for (uint32_t i = 0; i < cPositions; ++i)
950	{
951	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
952	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
953	continue;
954
955	if (pSVGAState->aScreens[i].xOrigin == -1)
956	continue;
957	if (pSVGAState->aScreens[i].yOrigin == -1)
958	continue;
959
960	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
961	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
962	pSVGAState->aScreens[i].fModified = true;
963	}
964
965	vmsvgaR3VBVAResize(pThis, pThisCC);
966	}
967
968	#endif /* IN_RING3 */
969
970	/**
971	* Read port register
972	*
973	* @returns VBox status code.
974	* @param pDevIns The device instance.
975	* @param pThis The shared VGA/VMSVGA state.
976	* @param pu32 Where to store the read value
977	*/
978	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
979	{
980	#ifdef IN_RING3
981	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
982	#endif
983	int rc = VINF_SUCCESS;
984	*pu32 = 0;
985
986	/* Rough index register validation. */
987	uint32_t idxReg = pThis->svga.u32IndexReg;
988	#if !defined(IN_RING3) && defined(VBOX_STRICT)
989	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
990	VINF_IOM_R3_IOPORT_READ);
991	#else
992	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
993	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
994	VINF_SUCCESS);
995	#endif
996	RT_UNTRUSTED_VALIDATED_FENCE();
997
998	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
999	if ( idxReg >= SVGA_REG_ID_0_TOP
1000	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1001	{
1002	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1003	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1004	}
1005
1006	switch (idxReg)
1007	{
1008	case SVGA_REG_ID:
1009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1010	*pu32 = pThis->svga.u32SVGAId;
1011	break;
1012
1013	case SVGA_REG_ENABLE:
1014	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1015	*pu32 = pThis->svga.fEnabled;
1016	break;
1017
1018	case SVGA_REG_WIDTH:
1019	{
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1021	if ( pThis->svga.fEnabled
1022	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1023	*pu32 = pThis->svga.uWidth;
1024	else
1025	{
1026	#ifndef IN_RING3
1027	rc = VINF_IOM_R3_IOPORT_READ;
1028	#else
1029	*pu32 = pThisCC->pDrv->cx;
1030	#endif
1031	}
1032	break;
1033	}
1034
1035	case SVGA_REG_HEIGHT:
1036	{
1037	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1038	if ( pThis->svga.fEnabled
1039	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1040	*pu32 = pThis->svga.uHeight;
1041	else
1042	{
1043	#ifndef IN_RING3
1044	rc = VINF_IOM_R3_IOPORT_READ;
1045	#else
1046	*pu32 = pThisCC->pDrv->cy;
1047	#endif
1048	}
1049	break;
1050	}
1051
1052	case SVGA_REG_MAX_WIDTH:
1053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1054	*pu32 = pThis->svga.u32MaxWidth;
1055	break;
1056
1057	case SVGA_REG_MAX_HEIGHT:
1058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1059	*pu32 = pThis->svga.u32MaxHeight;
1060	break;
1061
1062	case SVGA_REG_DEPTH:
1063	/* This returns the color depth of the current mode. */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1065	switch (pThis->svga.uBpp)
1066	{
1067	case 15:
1068	case 16:
1069	case 24:
1070	*pu32 = pThis->svga.uBpp;
1071	break;
1072
1073	default:
1074	case 32:
1075	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1076	break;
1077	}
1078	break;
1079
1080	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1081	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1082	*pu32 = pThis->svga.uHostBpp;
1083	break;
1084
1085	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1086	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1087	*pu32 = pThis->svga.uBpp;
1088	break;
1089
1090	case SVGA_REG_PSEUDOCOLOR:
1091	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1092	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1093	break;
1094
1095	case SVGA_REG_RED_MASK:
1096	case SVGA_REG_GREEN_MASK:
1097	case SVGA_REG_BLUE_MASK:
1098	{
1099	uint32_t uBpp;
1100
1101	if (pThis->svga.fEnabled)
1102	uBpp = pThis->svga.uBpp;
1103	else
1104	uBpp = pThis->svga.uHostBpp;
1105
1106	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1107	switch (uBpp)
1108	{
1109	case 8:
1110	u32RedMask = 0x07;
1111	u32GreenMask = 0x38;
1112	u32BlueMask = 0xc0;
1113	break;
1114
1115	case 15:
1116	u32RedMask = 0x0000001f;
1117	u32GreenMask = 0x000003e0;
1118	u32BlueMask = 0x00007c00;
1119	break;
1120
1121	case 16:
1122	u32RedMask = 0x0000001f;
1123	u32GreenMask = 0x000007e0;
1124	u32BlueMask = 0x0000f800;
1125	break;
1126
1127	case 24:
1128	case 32:
1129	default:
1130	u32RedMask = 0x00ff0000;
1131	u32GreenMask = 0x0000ff00;
1132	u32BlueMask = 0x000000ff;
1133	break;
1134	}
1135	switch (idxReg)
1136	{
1137	case SVGA_REG_RED_MASK:
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1139	*pu32 = u32RedMask;
1140	break;
1141
1142	case SVGA_REG_GREEN_MASK:
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1144	*pu32 = u32GreenMask;
1145	break;
1146
1147	case SVGA_REG_BLUE_MASK:
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1149	*pu32 = u32BlueMask;
1150	break;
1151	}
1152	break;
1153	}
1154
1155	case SVGA_REG_BYTES_PER_LINE:
1156	{
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1158	if ( pThis->svga.fEnabled
1159	&& pThis->svga.cbScanline)
1160	*pu32 = pThis->svga.cbScanline;
1161	else
1162	{
1163	#ifndef IN_RING3
1164	rc = VINF_IOM_R3_IOPORT_READ;
1165	#else
1166	*pu32 = pThisCC->pDrv->cbScanline;
1167	#endif
1168	}
1169	break;
1170	}
1171
1172	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1174	*pu32 = pThis->vram_size;
1175	break;
1176
1177	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1179	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1180	*pu32 = pThis->GCPhysVRAM;
1181	break;
1182
1183	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1184	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1185	/* Always zero in our case. */
1186	*pu32 = 0;
1187	break;
1188
1189	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1190	{
1191	#ifndef IN_RING3
1192	rc = VINF_IOM_R3_IOPORT_READ;
1193	#else
1194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1195
1196	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1197	if ( pThis->svga.fEnabled
1198	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1199	{
1200	/* Hardware enabled; return real framebuffer size .*/
1201	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1202	}
1203	else
1204	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1205
1206	pu32 = RT_MIN(pThis->vram_size, pu32);
1207	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1208	#endif
1209	break;
1210	}
1211
1212	case SVGA_REG_CAPABILITIES:
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1214	*pu32 = pThis->svga.u32DeviceCaps;
1215	break;
1216
1217	case SVGA_REG_MEM_START: /* FIFO start */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1219	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1220	*pu32 = pThis->svga.GCPhysFIFO;
1221	break;
1222
1223	case SVGA_REG_MEM_SIZE: /* FIFO size */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1225	*pu32 = pThis->svga.cbFIFO;
1226	break;
1227
1228	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1230	*pu32 = pThis->svga.fConfigured;
1231	break;
1232
1233	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1234	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1235	*pu32 = 0;
1236	break;
1237
1238	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1239	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1240	if (pThis->svga.fBusy)
1241	{
1242	#ifndef IN_RING3
1243	/* Go to ring-3 and halt the CPU. */
1244	rc = VINF_IOM_R3_IOPORT_READ;
1245	RT_NOREF(pDevIns);
1246	break;
1247	#else
1248	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1249	/* The guest is basically doing a HLT via the device here, but with
1250	a special wake up condition on FIFO completion. */
1251	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1252	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1253	PVM pVM = PDMDevHlpGetVM(pDevIns);
1254	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1255	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1256	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1257	if (pThis->svga.fBusy)
1258	{
1259	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1260	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1261	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1262	}
1263	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1264	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1265	# else
1266
1267	/* Delay the EMT a bit so the FIFO and others can get some work done.
1268	This used to be a crude 50 ms sleep. The current code tries to be
1269	more efficient, but the consept is still very crude. */
1270	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1271	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1272	RTThreadYield();
1273	if (pThis->svga.fBusy)
1274	{
1275	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1276
1277	if (pThis->svga.fBusy && cRefs == 1)
1278	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1279	if (pThis->svga.fBusy)
1280	{
1281	/** @todo If this code is going to stay, we need to call into the halt/wait
1282	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1283	* suffer when the guest is polling on a busy FIFO. */
1284	uint64_t uIgnored1, uIgnored2;
1285	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1286	if (cNsMaxWait >= RT_NS_100US)
1287	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1288	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1289	RT_MIN(cNsMaxWait, RT_NS_10MS));
1290	}
1291
1292	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1293	}
1294	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1295	# endif
1296	*pu32 = pThis->svga.fBusy != 0;
1297	#endif
1298	}
1299	else
1300	*pu32 = false;
1301	break;
1302
1303	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1304	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1305	*pu32 = pThis->svga.u32GuestId;
1306	break;
1307
1308	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1309	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1310	*pu32 = pThis->svga.cScratchRegion;
1311	break;
1312
1313	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1314	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1315	*pu32 = SVGA_FIFO_NUM_REGS;
1316	break;
1317
1318	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1319	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1320	*pu32 = pThis->svga.u32PitchLock;
1321	break;
1322
1323	case SVGA_REG_IRQMASK: /* Interrupt mask */
1324	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1325	*pu32 = pThis->svga.u32IrqMask;
1326	break;
1327
1328	/* See "Guest memory regions" below. */
1329	case SVGA_REG_GMR_ID:
1330	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1331	*pu32 = pThis->svga.u32CurrentGMRId;
1332	break;
1333
1334	case SVGA_REG_GMR_DESCRIPTOR:
1335	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1336	/* Write only */
1337	*pu32 = 0;
1338	break;
1339
1340	case SVGA_REG_GMR_MAX_IDS:
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1342	*pu32 = pThis->svga.cGMR;
1343	break;
1344
1345	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1347	*pu32 = VMSVGA_MAX_GMR_PAGES;
1348	break;
1349
1350	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1351	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1352	*pu32 = pThis->svga.fTraces;
1353	break;
1354
1355	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1356	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1357	*pu32 = VMSVGA_MAX_GMR_PAGES;
1358	break;
1359
1360	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1361	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1362	*pu32 = VMSVGA_SURFACE_SIZE;
1363	break;
1364
1365	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1367	break;
1368
1369	/* Mouse cursor support. */
1370	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1372	*pu32 = pThis->svga.uCursorID;
1373	break;
1374
1375	case SVGA_REG_CURSOR_X:
1376	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1377	*pu32 = pThis->svga.uCursorX;
1378	break;
1379
1380	case SVGA_REG_CURSOR_Y:
1381	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1382	*pu32 = pThis->svga.uCursorY;
1383	break;
1384
1385	case SVGA_REG_CURSOR_ON:
1386	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1387	*pu32 = pThis->svga.uCursorOn;
1388	break;
1389
1390	/* Legacy multi-monitor support */
1391	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1392	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1393	*pu32 = 1;
1394	break;
1395
1396	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1397	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1398	*pu32 = 0;
1399	break;
1400
1401	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1402	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1403	*pu32 = 0;
1404	break;
1405
1406	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1407	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1408	*pu32 = 0;
1409	break;
1410
1411	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1412	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1413	*pu32 = 0;
1414	break;
1415
1416	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1417	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1418	*pu32 = pThis->svga.uWidth;
1419	break;
1420
1421	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1422	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1423	*pu32 = pThis->svga.uHeight;
1424	break;
1425
1426	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1427	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1428	/* We must return something sensible here otherwise the Linux driver
1429	will take a legacy code path without 3d support. This number also
1430	limits how many screens Linux guests will allow. */
1431	*pu32 = pThis->cMonitors;
1432	break;
1433
1434	/*
1435	* SVGA_CAP_GBOBJECTS+ registers.
1436	*/
1437	case SVGA_REG_COMMAND_LOW:
1438	/* Lower 32 bits of command buffer physical address. */
1439	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1440	*pu32 = pThis->svga.u32RegCommandLow;
1441	break;
1442
1443	case SVGA_REG_COMMAND_HIGH:
1444	/* Upper 32 bits of command buffer PA. */
1445	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1446	*pu32 = pThis->svga.u32RegCommandHigh;
1447	break;
1448
1449	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1450	/* Max primary (screen) memory. */
1451	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1452	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1453	break;
1454
1455	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1456	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1457	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1458	*pu32 = pThis->vram_size / 1024;
1459	break;
1460
1461	case SVGA_REG_DEV_CAP:
1462	/* Write dev cap index, read value */
1463	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1464	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1465	{
1466	RT_UNTRUSTED_VALIDATED_FENCE();
1467	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1468	}
1469	else
1470	*pu32 = 0;
1471	break;
1472
1473	case SVGA_REG_CMD_PREPEND_LOW:
1474	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1475	pu32 = 0; / Not supported. */
1476	break;
1477
1478	case SVGA_REG_CMD_PREPEND_HIGH:
1479	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1480	pu32 = 0; / Not supported. */
1481	break;
1482
1483	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1484	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1485	*pu32 = pThis->svga.u32MaxWidth;
1486	break;
1487
1488	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1489	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1490	*pu32 = pThis->svga.u32MaxHeight;
1491	break;
1492
1493	case SVGA_REG_MOB_MAX_SIZE:
1494	/* Essentially the max texture size */
1495	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1496	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1497	break;
1498
1499	default:
1500	{
1501	uint32_t offReg;
1502	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1503	{
1504	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1505	RT_UNTRUSTED_VALIDATED_FENCE();
1506	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1507	}
1508	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1509	{
1510	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1511	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1512	RT_UNTRUSTED_VALIDATED_FENCE();
1513	uint32_t u32 = pThis->last_palette[offReg / 3];
1514	switch (offReg % 3)
1515	{
1516	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1517	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1518	case 2: pu32 = u32 & 0xff; break; / blue */
1519	}
1520	}
1521	else
1522	{
1523	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1524	rc = VINF_IOM_R3_IOPORT_READ;
1525	#else
1526	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1527
1528	/* Do not assert. The guest might be reading all registers. */
1529	LogFunc(("Unknown reg=%#x\n", idxReg));
1530	#endif
1531	}
1532	break;
1533	}
1534	}
1535	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1536	return rc;
1537	}
1538
1539	#ifdef IN_RING3
1540	/**
1541	* Apply the current resolution settings to change the video mode.
1542	*
1543	* @returns VBox status code.
1544	* @param pThis The shared VGA state.
1545	* @param pThisCC The ring-3 VGA state.
1546	*/
1547	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1548	{
1549	/* Always do changemode on FIFO thread. */
1550	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1551
1552	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1553
1554	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1555
1556	if (pThis->svga.fGFBRegisters)
1557	{
1558	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1559	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1560	* deletes all screens other than screen #0, and redefines screen
1561	* #0 according to the specified mode. Drivers that use
1562	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1563	*/
1564
1565	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1566	pScreen->fDefined = true;
1567	pScreen->fModified = true;
1568	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1569	pScreen->idScreen = 0;
1570	pScreen->xOrigin = 0;
1571	pScreen->yOrigin = 0;
1572	pScreen->offVRAM = 0;
1573	pScreen->cbPitch = pThis->svga.cbScanline;
1574	pScreen->cWidth = pThis->svga.uWidth;
1575	pScreen->cHeight = pThis->svga.uHeight;
1576	pScreen->cBpp = pThis->svga.uBpp;
1577
1578	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1579	{
1580	/* Delete screen. */
1581	pScreen = &pSVGAState->aScreens[iScreen];
1582	if (pScreen->fDefined)
1583	{
1584	pScreen->fModified = true;
1585	pScreen->fDefined = false;
1586	}
1587	}
1588	}
1589	else
1590	{
1591	/* "If Screen Objects are supported, they can be used to fully
1592	* replace the functionality provided by the framebuffer registers
1593	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1594	*/
1595	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1596	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1597	pThis->svga.uBpp = pThis->svga.uHostBpp;
1598	}
1599
1600	vmsvgaR3VBVAResize(pThis, pThisCC);
1601
1602	/* Last stuff. For the VGA device screenshot. */
1603	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1604	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1605	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1606	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1607	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1608
1609	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1610	if ( pThis->svga.viewport.cx == 0
1611	&& pThis->svga.viewport.cy == 0)
1612	{
1613	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1614	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1615	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1616	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1617	pThis->svga.viewport.yLowWC = 0;
1618	}
1619
1620	return VINF_SUCCESS;
1621	}
1622
1623	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1624	{
1625	VBVACMDHDR cmd;
1626	cmd.x = (int16_t)(pScreen->xOrigin + x);
1627	cmd.y = (int16_t)(pScreen->yOrigin + y);
1628	cmd.w = (uint16_t)w;
1629	cmd.h = (uint16_t)h;
1630
1631	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1632	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1633	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1634	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1635
1636	return VINF_SUCCESS;
1637	}
1638
1639	#endif /* IN_RING3 */
1640	#if defined(IN_RING0) \|\| defined(IN_RING3)
1641
1642	/**
1643	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1644	*
1645	* @param pThis The shared VGA/VMSVGA instance data.
1646	* @param pThisCC The VGA/VMSVGA state for the current context.
1647	* @param fState The busy state.
1648	*/
1649	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1650	{
1651	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1652
1653	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1654	{
1655	/* Race / unfortunately scheduling. Highly unlikly. */
1656	uint32_t cLoops = 64;
1657	do
1658	{
1659	ASMNopPause();
1660	fState = (pThis->svga.fBusy != 0);
1661	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1662	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1663	}
1664	}
1665
1666
1667	/**
1668	* Update the scanline pitch in response to the guest changing mode
1669	* width/bpp.
1670	*
1671	* @param pThis The shared VGA/VMSVGA state.
1672	* @param pThisCC The VGA/VMSVGA state for the current context.
1673	*/
1674	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1675	{
1676	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1677	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1678	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1679	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1680
1681	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1682	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1683	* location but it has a different meaning.
1684	*/
1685	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1686	uFifoPitchLock = 0;
1687
1688	/* Sanitize values. */
1689	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1690	uFifoPitchLock = 0;
1691	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1692	uRegPitchLock = 0;
1693
1694	/* Prefer the register value to the FIFO value.*/
1695	if (uRegPitchLock)
1696	pThis->svga.cbScanline = uRegPitchLock;
1697	else if (uFifoPitchLock)
1698	pThis->svga.cbScanline = uFifoPitchLock;
1699	else
1700	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1701
1702	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1703	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1704	}
1705
1706	#endif /* IN_RING0 \|\| IN_RING3 */
1707
1708	#ifdef IN_RING3
1709
1710	/**
1711	* Sends cursor position and visibility information from legacy
1712	* SVGA registers to the front-end.
1713	*/
1714	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1715	{
1716	/*
1717	* Writing the X/Y/ID registers does not trigger changes; only writing the
1718	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1719	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1720	* register if they don't have to.
1721	*/
1722	uint32_t x, y, idScreen;
1723	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1724
1725	x = pThis->svga.uCursorX;
1726	y = pThis->svga.uCursorY;
1727	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1728
1729	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1730	* were extended as follows:
1731	*
1732	* SVGA_CURSOR_ON_HIDE 0
1733	* SVGA_CURSOR_ON_SHOW 1
1734	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1735	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1736	*
1737	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1738	* distinguish between the non-zero values but still remember them.
1739	*/
1740	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1741	{
1742	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1743	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1744	}
1745	pThis->svga.uCursorOn = uCursorOn;
1746	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1747	}
1748
1749	#endif /* IN_RING3 */
1750
1751
1752	/**
1753	* Write port register
1754	*
1755	* @returns Strict VBox status code.
1756	* @param pDevIns The device instance.
1757	* @param pThis The shared VGA/VMSVGA state.
1758	* @param pThisCC The VGA/VMSVGA state for the current context.
1759	* @param u32 Value to write
1760	*/
1761	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1762	{
1763	#ifdef IN_RING3
1764	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1765	#endif
1766	VBOXSTRICTRC rc = VINF_SUCCESS;
1767	RT_NOREF(pThisCC);
1768
1769	/* Rough index register validation. */
1770	uint32_t idxReg = pThis->svga.u32IndexReg;
1771	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1772	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1773	VINF_IOM_R3_IOPORT_WRITE);
1774	#else
1775	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1776	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1777	VINF_SUCCESS);
1778	#endif
1779	RT_UNTRUSTED_VALIDATED_FENCE();
1780
1781	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1782	if ( idxReg >= SVGA_REG_ID_0_TOP
1783	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1784	{
1785	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1786	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1787	}
1788	#ifdef LOG_ENABLED
1789	if (idxReg != SVGA_REG_DEV_CAP)
1790	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1791	else
1792	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1793	#endif
1794	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1795	switch (idxReg)
1796	{
1797	case SVGA_REG_WIDTH:
1798	case SVGA_REG_HEIGHT:
1799	case SVGA_REG_PITCHLOCK:
1800	case SVGA_REG_BITS_PER_PIXEL:
1801	pThis->svga.fGFBRegisters = true;
1802	break;
1803	default:
1804	break;
1805	}
1806
1807	switch (idxReg)
1808	{
1809	case SVGA_REG_ID:
1810	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1811	if ( u32 == SVGA_ID_0
1812	\|\| u32 == SVGA_ID_1
1813	\|\| u32 == SVGA_ID_2)
1814	pThis->svga.u32SVGAId = u32;
1815	else
1816	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1817	break;
1818
1819	case SVGA_REG_ENABLE:
1820	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1821	#ifdef IN_RING3
1822	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1823	&& pThis->svga.fEnabled == false)
1824	{
1825	/* Make a backup copy of the first 512kb in order to save font data etc. */
1826	/** @todo should probably swap here, rather than copy + zero */
1827	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1828	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1829	}
1830
1831	pThis->svga.fEnabled = u32;
1832	if (pThis->svga.fEnabled)
1833	{
1834	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1835	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1836	{
1837	/* Keep the current mode. */
1838	pThis->svga.uWidth = pThisCC->pDrv->cx;
1839	pThis->svga.uHeight = pThisCC->pDrv->cy;
1840	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1841	}
1842
1843	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1844	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1845	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1846	# ifdef LOG_ENABLED
1847	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1848	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1849	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1850	# endif
1851
1852	/* Disable or enable dirty page tracking according to the current fTraces value. */
1853	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1854
1855	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1856	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1857	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1858
1859	/* Make the cursor visible again as needed. */
1860	if (pSVGAState->Cursor.fActive)
1861	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1862	}
1863	else
1864	{
1865	/* Make sure the cursor is off. */
1866	if (pSVGAState->Cursor.fActive)
1867	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1868
1869	/* Restore the text mode backup. */
1870	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1871
1872	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1873
1874	/* Enable dirty page tracking again when going into legacy mode. */
1875	vmsvgaR3SetTraces(pDevIns, pThis, true);
1876
1877	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1878	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1879	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1880
1881	/* Clear the pitch lock. */
1882	pThis->svga.u32PitchLock = 0;
1883	}
1884	#else /* !IN_RING3 */
1885	rc = VINF_IOM_R3_IOPORT_WRITE;
1886	#endif /* !IN_RING3 */
1887	break;
1888
1889	case SVGA_REG_WIDTH:
1890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1891	if (u32 != pThis->svga.uWidth)
1892	{
1893	if (u32 <= pThis->svga.u32MaxWidth)
1894	{
1895	#if defined(IN_RING3) \|\| defined(IN_RING0)
1896	pThis->svga.uWidth = u32;
1897	vmsvgaHCUpdatePitch(pThis, pThisCC);
1898	if (pThis->svga.fEnabled)
1899	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1900	#else
1901	rc = VINF_IOM_R3_IOPORT_WRITE;
1902	#endif
1903	}
1904	else
1905	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
1906	}
1907	/* else: nop */
1908	break;
1909
1910	case SVGA_REG_HEIGHT:
1911	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1912	if (u32 != pThis->svga.uHeight)
1913	{
1914	if (u32 <= pThis->svga.u32MaxHeight)
1915	{
1916	pThis->svga.uHeight = u32;
1917	if (pThis->svga.fEnabled)
1918	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1919	}
1920	else
1921	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
1922	}
1923	/* else: nop */
1924	break;
1925
1926	case SVGA_REG_DEPTH:
1927	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1928	/** @todo read-only?? */
1929	break;
1930
1931	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1932	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1933	if (pThis->svga.uBpp != u32)
1934	{
1935	if (u32 <= 32)
1936	{
1937	#if defined(IN_RING3) \|\| defined(IN_RING0)
1938	pThis->svga.uBpp = u32;
1939	vmsvgaHCUpdatePitch(pThis, pThisCC);
1940	if (pThis->svga.fEnabled)
1941	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1942	#else
1943	rc = VINF_IOM_R3_IOPORT_WRITE;
1944	#endif
1945	}
1946	else
1947	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
1948	}
1949	/* else: nop */
1950	break;
1951
1952	case SVGA_REG_PSEUDOCOLOR:
1953	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1954	break;
1955
1956	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1957	#ifdef IN_RING3
1958	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1959	pThis->svga.fConfigured = u32;
1960	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1961	if (!pThis->svga.fConfigured)
1962	pThis->svga.fTraces = true;
1963	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1964	#else
1965	rc = VINF_IOM_R3_IOPORT_WRITE;
1966	#endif
1967	break;
1968
1969	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1970	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1971	if ( pThis->svga.fEnabled
1972	&& pThis->svga.fConfigured)
1973	{
1974	#if defined(IN_RING3) \|\| defined(IN_RING0)
1975	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1976	/*
1977	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1978	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1979	*/
1980	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1981	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1982	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1983
1984	/* Kick the FIFO thread to start processing commands again. */
1985	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1986	#else
1987	rc = VINF_IOM_R3_IOPORT_WRITE;
1988	#endif
1989	}
1990	/* else nothing to do. */
1991	else
1992	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1993
1994	break;
1995
1996	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1997	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1998	break;
1999
2000	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2002	pThis->svga.u32GuestId = u32;
2003	break;
2004
2005	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2006	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2007	pThis->svga.u32PitchLock = u32;
2008	/* Should this also update the FIFO pitch lock? Unclear. */
2009	break;
2010
2011	case SVGA_REG_IRQMASK: /* Interrupt mask */
2012	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2013	pThis->svga.u32IrqMask = u32;
2014
2015	/* Irq pending after the above change? */
2016	if (pThis->svga.u32IrqStatus & u32)
2017	{
2018	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2019	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2020	}
2021	else
2022	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2023	break;
2024
2025	/* Mouse cursor support */
2026	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2027	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2028	pThis->svga.uCursorID = u32;
2029	break;
2030
2031	case SVGA_REG_CURSOR_X:
2032	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2033	pThis->svga.uCursorX = u32;
2034	break;
2035
2036	case SVGA_REG_CURSOR_Y:
2037	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2038	pThis->svga.uCursorY = u32;
2039	break;
2040
2041	case SVGA_REG_CURSOR_ON:
2042	#ifdef IN_RING3
2043	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2045	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2046	#else
2047	rc = VINF_IOM_R3_IOPORT_WRITE;
2048	#endif
2049	break;
2050
2051	/* Legacy multi-monitor support */
2052	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2054	break;
2055	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2057	break;
2058	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2060	break;
2061	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2063	break;
2064	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2066	break;
2067	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2069	break;
2070	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2071	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2072	break;
2073	#ifdef VBOX_WITH_VMSVGA3D
2074	/* See "Guest memory regions" below. */
2075	case SVGA_REG_GMR_ID:
2076	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2077	pThis->svga.u32CurrentGMRId = u32;
2078	break;
2079
2080	case SVGA_REG_GMR_DESCRIPTOR:
2081	# ifndef IN_RING3
2082	rc = VINF_IOM_R3_IOPORT_WRITE;
2083	break;
2084	# else /* IN_RING3 */
2085	{
2086	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2087
2088	/* Validate current GMR id. */
2089	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2090	AssertBreak(idGMR < pThis->svga.cGMR);
2091	RT_UNTRUSTED_VALIDATED_FENCE();
2092
2093	/* Free the old GMR if present. */
2094	vmsvgaR3GmrFree(pThisCC, idGMR);
2095
2096	/* Just undefine the GMR? */
2097	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2098	if (GCPhys == 0)
2099	{
2100	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2101	break;
2102	}
2103
2104
2105	/* Never cross a page boundary automatically. */
2106	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2107	uint32_t cPagesTotal = 0;
2108	uint32_t iDesc = 0;
2109	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2110	uint32_t cLoops = 0;
2111	RTGCPHYS GCPhysBase = GCPhys;
2112	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2113	{
2114	/* Read descriptor. */
2115	SVGAGuestMemDescriptor desc;
2116	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2117	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2118
2119	if (desc.numPages != 0)
2120	{
2121	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2122	cPagesTotal += desc.numPages;
2123	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2124
2125	if ((iDesc & 15) == 0)
2126	{
2127	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2128	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2129	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2130	}
2131
2132	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2133	paDescs[iDesc++].numPages = desc.numPages;
2134
2135	/* Continue with the next descriptor. */
2136	GCPhys += sizeof(desc);
2137	}
2138	else if (desc.ppn == 0)
2139	break; /* terminator */
2140	else /* Pointer to the next physical page of descriptors. */
2141	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2142
2143	cLoops++;
2144	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2145	}
2146
2147	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2148	if (RT_SUCCESS(rc))
2149	{
2150	/* Commit the GMR. */
2151	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2152	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2153	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2154	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2155	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2156	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2157	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2158	}
2159	else
2160	{
2161	RTMemFree(paDescs);
2162	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2163	}
2164	break;
2165	}
2166	# endif /* IN_RING3 */
2167	#endif // VBOX_WITH_VMSVGA3D
2168
2169	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2171	if (pThis->svga.fTraces == u32)
2172	break; /* nothing to do */
2173
2174	#ifdef IN_RING3
2175	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2176	#else
2177	rc = VINF_IOM_R3_IOPORT_WRITE;
2178	#endif
2179	break;
2180
2181	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2183	break;
2184
2185	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2186	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2187	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2188	break;
2189
2190	/*
2191	* SVGA_CAP_GBOBJECTS+ registers.
2192	*/
2193	case SVGA_REG_COMMAND_LOW:
2194	{
2195	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2196	#ifdef IN_RING3
2197	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2198	pThis->svga.u32RegCommandLow = u32;
2199
2200	/* "lower 6 bits are used for the SVGACBContext" */
2201	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2202	GCPhysCB <<= 32;
2203	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2204	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2205	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2206	#else
2207	rc = VINF_IOM_R3_IOPORT_WRITE;
2208	#endif
2209	break;
2210	}
2211
2212	case SVGA_REG_COMMAND_HIGH:
2213	/* Upper 32 bits of command buffer PA. */
2214	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2215	pThis->svga.u32RegCommandHigh = u32;
2216	break;
2217
2218	case SVGA_REG_DEV_CAP:
2219	/* Write dev cap index, read value */
2220	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2221	pThis->svga.u32DevCapIndex = u32;
2222	break;
2223
2224	case SVGA_REG_CMD_PREPEND_LOW:
2225	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2226	/* Not supported. */
2227	break;
2228
2229	case SVGA_REG_CMD_PREPEND_HIGH:
2230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2231	/* Not supported. */
2232	break;
2233
2234	case SVGA_REG_FB_START:
2235	case SVGA_REG_MEM_START:
2236	case SVGA_REG_HOST_BITS_PER_PIXEL:
2237	case SVGA_REG_MAX_WIDTH:
2238	case SVGA_REG_MAX_HEIGHT:
2239	case SVGA_REG_VRAM_SIZE:
2240	case SVGA_REG_FB_SIZE:
2241	case SVGA_REG_CAPABILITIES:
2242	case SVGA_REG_MEM_SIZE:
2243	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2244	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2245	case SVGA_REG_BYTES_PER_LINE:
2246	case SVGA_REG_FB_OFFSET:
2247	case SVGA_REG_RED_MASK:
2248	case SVGA_REG_GREEN_MASK:
2249	case SVGA_REG_BLUE_MASK:
2250	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2251	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2252	case SVGA_REG_GMR_MAX_IDS:
2253	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2254	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2255	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2256	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2257	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2258	case SVGA_REG_MOB_MAX_SIZE:
2259	/* Read only - ignore. */
2260	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2261	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2262	break;
2263
2264	default:
2265	{
2266	uint32_t offReg;
2267	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2268	{
2269	RT_UNTRUSTED_VALIDATED_FENCE();
2270	pThis->svga.au32ScratchRegion[offReg] = u32;
2271	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2272	}
2273	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2274	{
2275	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2276	Btw, see rgb_to_pixel32. */
2277	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2278	u32 &= 0xff;
2279	RT_UNTRUSTED_VALIDATED_FENCE();
2280	uint32_t uRgb = pThis->last_palette[offReg / 3];
2281	switch (offReg % 3)
2282	{
2283	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2284	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2285	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2286	}
2287	pThis->last_palette[offReg / 3] = uRgb;
2288	}
2289	else
2290	{
2291	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2292	rc = VINF_IOM_R3_IOPORT_WRITE;
2293	#else
2294	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2295	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2296	#endif
2297	}
2298	break;
2299	}
2300	}
2301	return rc;
2302	}
2303
2304	/**
2305	* @callback_method_impl{FNIOMIOPORTNEWIN}
2306	*/
2307	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2308	{
2309	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2310	RT_NOREF_PV(pvUser);
2311
2312	/* Only dword accesses. */
2313	if (cb == 4)
2314	{
2315	switch (offPort)
2316	{
2317	case SVGA_INDEX_PORT:
2318	*pu32 = pThis->svga.u32IndexReg;
2319	break;
2320
2321	case SVGA_VALUE_PORT:
2322	return vmsvgaReadPort(pDevIns, pThis, pu32);
2323
2324	case SVGA_BIOS_PORT:
2325	Log(("Ignoring BIOS port read\n"));
2326	*pu32 = 0;
2327	break;
2328
2329	case SVGA_IRQSTATUS_PORT:
2330	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2331	*pu32 = pThis->svga.u32IrqStatus;
2332	break;
2333
2334	default:
2335	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2336	*pu32 = UINT32_MAX;
2337	break;
2338	}
2339	}
2340	else
2341	{
2342	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2343	*pu32 = UINT32_MAX;
2344	}
2345	return VINF_SUCCESS;
2346	}
2347
2348	/**
2349	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2350	*/
2351	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2352	{
2353	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2354	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2355	RT_NOREF_PV(pvUser);
2356
2357	/* Only dword accesses. */
2358	if (cb == 4)
2359	switch (offPort)
2360	{
2361	case SVGA_INDEX_PORT:
2362	pThis->svga.u32IndexReg = u32;
2363	break;
2364
2365	case SVGA_VALUE_PORT:
2366	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2367
2368	case SVGA_BIOS_PORT:
2369	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2370	break;
2371
2372	case SVGA_IRQSTATUS_PORT:
2373	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2374	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2375	/* Clear the irq in case all events have been cleared. */
2376	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2377	{
2378	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2379	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2380	}
2381	break;
2382
2383	default:
2384	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2385	break;
2386	}
2387	else
2388	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2389
2390	return VINF_SUCCESS;
2391	}
2392
2393	#ifdef IN_RING3
2394
2395	# ifdef DEBUG_FIFO_ACCESS
2396	/**
2397	* Handle FIFO memory access.
2398	* @returns VBox status code.
2399	* @param pVM VM handle.
2400	* @param pThis The shared VGA/VMSVGA instance data.
2401	* @param GCPhys The access physical address.
2402	* @param fWriteAccess Read or write access
2403	*/
2404	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2405	{
2406	RT_NOREF(pVM);
2407	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2408	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2409
2410	switch (GCPhysOffset >> 2)
2411	{
2412	case SVGA_FIFO_MIN:
2413	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2414	break;
2415	case SVGA_FIFO_MAX:
2416	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2417	break;
2418	case SVGA_FIFO_NEXT_CMD:
2419	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2420	break;
2421	case SVGA_FIFO_STOP:
2422	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2423	break;
2424	case SVGA_FIFO_CAPABILITIES:
2425	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2426	break;
2427	case SVGA_FIFO_FLAGS:
2428	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2429	break;
2430	case SVGA_FIFO_FENCE:
2431	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2432	break;
2433	case SVGA_FIFO_3D_HWVERSION:
2434	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2435	break;
2436	case SVGA_FIFO_PITCHLOCK:
2437	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2438	break;
2439	case SVGA_FIFO_CURSOR_ON:
2440	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2441	break;
2442	case SVGA_FIFO_CURSOR_X:
2443	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2444	break;
2445	case SVGA_FIFO_CURSOR_Y:
2446	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2447	break;
2448	case SVGA_FIFO_CURSOR_COUNT:
2449	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2450	break;
2451	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2452	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2453	break;
2454	case SVGA_FIFO_RESERVED:
2455	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2456	break;
2457	case SVGA_FIFO_CURSOR_SCREEN_ID:
2458	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2459	break;
2460	case SVGA_FIFO_DEAD:
2461	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2462	break;
2463	case SVGA_FIFO_3D_HWVERSION_REVISED:
2464	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2465	break;
2466	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2467	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2468	break;
2469	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2470	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2471	break;
2472	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2473	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2474	break;
2475	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2476	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2477	break;
2478	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2479	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2480	break;
2481	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2482	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2483	break;
2484	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2485	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2486	break;
2487	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2488	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2489	break;
2490	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2491	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2492	break;
2493	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2494	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2495	break;
2496	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2497	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2498	break;
2499	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2500	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2501	break;
2502	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2503	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2504	break;
2505	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2506	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2507	break;
2508	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2509	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2510	break;
2511	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2512	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2513	break;
2514	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2515	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2516	break;
2517	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2518	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2519	break;
2520	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2521	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2522	break;
2523	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2524	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2525	break;
2526	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2527	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2528	break;
2529	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2530	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2531	break;
2532	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2533	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2534	break;
2535	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2536	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2537	break;
2538	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2539	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2540	break;
2541	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2542	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2543	break;
2544	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2545	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2546	break;
2547	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2548	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2549	break;
2550	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2551	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2552	break;
2553	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2554	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2555	break;
2556	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2557	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2558	break;
2559	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2560	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2561	break;
2562	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2563	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2564	break;
2565	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2566	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2567	break;
2568	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2569	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2570	break;
2571	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2572	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2573	break;
2574	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2575	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2576	break;
2577	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2578	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2579	break;
2580	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2581	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2582	break;
2583	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2584	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2585	break;
2586	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2587	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2588	break;
2589	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2590	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2591	break;
2592	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2593	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2594	break;
2595	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2596	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2597	break;
2598	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2599	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2600	break;
2601	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2602	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2603	break;
2604	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2605	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2606	break;
2607	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2608	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2609	break;
2610	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2611	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2612	break;
2613	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2614	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2615	break;
2616	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2617	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2618	break;
2619	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2620	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2621	break;
2622	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2623	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2624	break;
2625	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2626	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2627	break;
2628	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2629	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2630	break;
2631	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2632	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2633	break;
2634	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2635	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2636	break;
2637	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2638	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2639	break;
2640	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2641	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2642	break;
2643	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2644	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2645	break;
2646	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2647	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2648	break;
2649	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2650	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2651	break;
2652	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2653	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2654	break;
2655	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2656	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2657	break;
2658	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2659	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2660	break;
2661	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2662	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2663	break;
2664	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2665	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2666	break;
2667	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2668	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2669	break;
2670	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2671	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2672	break;
2673	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2674	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2675	break;
2676	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2677	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2678	break;
2679	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2680	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2681	break;
2682	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2683	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2684	break;
2685	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2686	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2687	break;
2688	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2689	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2690	break;
2691	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2692	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2693	break;
2694	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2695	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2696	break;
2697	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2698	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2699	break;
2700	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2701	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2702	break;
2703	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2704	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2705	break;
2706	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2707	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2708	break;
2709	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2710	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2711	break;
2712	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2713	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2714	break;
2715	case SVGA_FIFO_3D_CAPS_LAST:
2716	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2717	break;
2718	case SVGA_FIFO_GUEST_3D_HWVERSION:
2719	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2720	break;
2721	case SVGA_FIFO_FENCE_GOAL:
2722	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2723	break;
2724	case SVGA_FIFO_BUSY:
2725	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2726	break;
2727	default:
2728	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2729	break;
2730	}
2731
2732	return VINF_EM_RAW_EMULATE_INSTR;
2733	}
2734	# endif /* DEBUG_FIFO_ACCESS */
2735
2736	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2737	/**
2738	* HC access handler for the FIFO.
2739	*
2740	* @returns VINF_SUCCESS if the handler have carried out the operation.
2741	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2742	* @param pVM VM Handle.
2743	* @param pVCpu The cross context CPU structure for the calling EMT.
2744	* @param GCPhys The physical address the guest is writing to.
2745	* @param pvPhys The HC mapping of that address.
2746	* @param pvBuf What the guest is reading/writing.
2747	* @param cbBuf How much it's reading/writing.
2748	* @param enmAccessType The access type.
2749	* @param enmOrigin Who is making the access.
2750	* @param pvUser User argument.
2751	*/
2752	static DECLCALLBACK(VBOXSTRICTRC)
2753	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2754	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2755	{
2756	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2757	PVGASTATE pThis = (PVGASTATE)pvUser;
2758	AssertPtr(pThis);
2759
2760	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2761	/*
2762	* Wake up the FIFO thread as it might have work to do now.
2763	*/
2764	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2765	AssertLogRelRC(rc);
2766	# endif
2767
2768	# ifdef DEBUG_FIFO_ACCESS
2769	/*
2770	* When in debug-fifo-access mode, we do not disable the access handler,
2771	* but leave it on as we wish to catch all access.
2772	*/
2773	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2774	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2775	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2776	/*
2777	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2778	*/
2779	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2780	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2781	# endif
2782	if (RT_SUCCESS(rc))
2783	return VINF_PGM_HANDLER_DO_DEFAULT;
2784	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2785	return rc;
2786	}
2787	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2788
2789	#endif /* IN_RING3 */
2790
2791	#ifdef DEBUG_GMR_ACCESS
2792	# ifdef IN_RING3
2793
2794	/**
2795	* HC access handler for GMRs.
2796	*
2797	* @returns VINF_SUCCESS if the handler have carried out the operation.
2798	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2799	* @param pVM VM Handle.
2800	* @param pVCpu The cross context CPU structure for the calling EMT.
2801	* @param GCPhys The physical address the guest is writing to.
2802	* @param pvPhys The HC mapping of that address.
2803	* @param pvBuf What the guest is reading/writing.
2804	* @param cbBuf How much it's reading/writing.
2805	* @param enmAccessType The access type.
2806	* @param enmOrigin Who is making the access.
2807	* @param pvUser User argument.
2808	*/
2809	static DECLCALLBACK(VBOXSTRICTRC)
2810	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2811	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2812	{
2813	PVGASTATE pThis = (PVGASTATE)pvUser;
2814	Assert(pThis);
2815	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2816	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2817
2818	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2819
2820	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2821	{
2822	PGMR pGMR = &pSVGAState->paGMR[i];
2823
2824	if (pGMR->numDescriptors)
2825	{
2826	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2827	{
2828	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2829	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2830	{
2831	/*
2832	* Turn off the write handler for this particular page and make it R/W.
2833	* Then return telling the caller to restart the guest instruction.
2834	*/
2835	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2836	AssertRC(rc);
2837	return VINF_PGM_HANDLER_DO_DEFAULT;
2838	}
2839	}
2840	}
2841	}
2842
2843	return VINF_PGM_HANDLER_DO_DEFAULT;
2844	}
2845
2846	/** Callback handler for VMR3ReqCallWaitU */
2847	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2848	{
2849	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2850	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2851	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2852	int rc;
2853
2854	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2855	{
2856	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2857	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2858	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2859	AssertRC(rc);
2860	}
2861	return VINF_SUCCESS;
2862	}
2863
2864	/** Callback handler for VMR3ReqCallWaitU */
2865	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2866	{
2867	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2868	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2869	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2870
2871	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2872	{
2873	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2874	AssertRC(rc);
2875	}
2876	return VINF_SUCCESS;
2877	}
2878
2879	/** Callback handler for VMR3ReqCallWaitU */
2880	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2881	{
2882	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2883
2884	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2885	{
2886	PGMR pGMR = &pSVGAState->paGMR[i];
2887
2888	if (pGMR->numDescriptors)
2889	{
2890	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2891	{
2892	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2893	AssertRC(rc);
2894	}
2895	}
2896	}
2897	return VINF_SUCCESS;
2898	}
2899
2900	# endif /* IN_RING3 */
2901	#endif /* DEBUG_GMR_ACCESS */
2902
2903	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2904
2905	#ifdef IN_RING3
2906
2907
2908	/*
2909	*
2910	* Command buffer submission.
2911	*
2912	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2913	*
2914	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2915	* and wakes up the FIFO thread.
2916	*
2917	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2918	* the buffer header back to the guest memory.
2919	*
2920	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2921	*
2922	*/
2923
2924
2925	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2926	*
2927	* @param pDevIns The device instance.
2928	* @param GCPhysCB Guest physical address of the command buffer header.
2929	* @param status Command buffer status (SVGA_CB_STATUS_*).
2930	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2931	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2932	* @thread FIFO or EMT.
2933	*/
2934	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2935	{
2936	SVGACBHeader hdr;
2937	hdr.status = status;
2938	hdr.errorOffset = errorOffset;
2939	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2940	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2941	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2942	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2943	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2944	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2945	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2946	}
2947
2948
2949	/** Raise an IRQ.
2950	*
2951	* @param pDevIns The device instance.
2952	* @param pThis The shared VGA/VMSVGA state.
2953	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2954	* @thread FIFO or EMT.
2955	*/
2956	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2957	{
2958	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2959	AssertRC(rc);
2960
2961	if (pThis->svga.u32IrqMask & u32IrqStatus)
2962	{
2963	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2964	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2965	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2966	}
2967
2968	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2969	}
2970
2971
2972	/** Allocate a command buffer structure.
2973	*
2974	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2975	* @return Pointer to the allocated command buffer structure.
2976	*/
2977	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2978	{
2979	if (!pCmdBufCtx)
2980	return NULL;
2981
2982	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2983	if (pCmdBuf)
2984	{
2985	// RT_ZERO(pCmdBuf->nodeBuffer);
2986	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2987	// pCmdBuf->GCPhysCB = 0;
2988	// RT_ZERO(pCmdBuf->hdr);
2989	// pCmdBuf->pvCommands = NULL;
2990	}
2991
2992	return pCmdBuf;
2993	}
2994
2995
2996	/** Free a command buffer structure.
2997	*
2998	* @param pCmdBuf The command buffer pointer.
2999	*/
3000	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3001	{
3002	if (pCmdBuf)
3003	RTMemFree(pCmdBuf->pvCommands);
3004	RTMemFree(pCmdBuf);
3005	}
3006
3007
3008	/** Initialize a command buffer context.
3009	*
3010	* @param pCmdBufCtx The command buffer context.
3011	*/
3012	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3013	{
3014	RTListInit(&pCmdBufCtx->listSubmitted);
3015	pCmdBufCtx->cSubmitted = 0;
3016	}
3017
3018
3019	/** Destroy a command buffer context.
3020	*
3021	* @param pCmdBufCtx The command buffer context pointer.
3022	*/
3023	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3024	{
3025	if (!pCmdBufCtx)
3026	return;
3027
3028	if (pCmdBufCtx->listSubmitted.pNext)
3029	{
3030	/* If the list has been initialized. */
3031	PVMSVGACMDBUF pIter, pNext;
3032	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3033	{
3034	RTListNodeRemove(&pIter->nodeBuffer);
3035	--pCmdBufCtx->cSubmitted;
3036	vmsvgaR3CmdBufFree(pIter);
3037	}
3038	}
3039	Assert(pCmdBufCtx->cSubmitted == 0);
3040	pCmdBufCtx->cSubmitted = 0;
3041	}
3042
3043
3044	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3045	*
3046	* @param pSvgaR3State VMSVGA R3 state.
3047	* @param pCmd The command data.
3048	* @return SVGACBStatus code.
3049	* @thread EMT
3050	*/
3051	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3052	{
3053	/* Create or destroy a regular command buffer context. */
3054	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3055	return SVGA_CB_STATUS_COMMAND_ERROR;
3056	RT_UNTRUSTED_VALIDATED_FENCE();
3057
3058	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3059
3060	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3061	AssertRC(rc);
3062	if (pCmd->enable)
3063	{
3064	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3065	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3066	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3067	else
3068	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3069	}
3070	else
3071	{
3072	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3073	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3074	}
3075	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3076
3077	return CBStatus;
3078	}
3079
3080
3081	/** Handles SVGA_DC_CMD_PREEMPT command.
3082	*
3083	* @param pDevIns The device instance.
3084	* @param pSvgaR3State VMSVGA R3 state.
3085	* @param pCmd The command data.
3086	* @return SVGACBStatus code.
3087	* @thread EMT
3088	*/
3089	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3090	{
3091	/* Remove buffers from the processing queue of the specified context. */
3092	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3093	return SVGA_CB_STATUS_COMMAND_ERROR;
3094	RT_UNTRUSTED_VALIDATED_FENCE();
3095
3096	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3097	RTLISTANCHOR listPreempted;
3098
3099	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3100	AssertRC(rc);
3101	if (pCmd->ignoreIDZero)
3102	{
3103	RTListInit(&listPreempted);
3104
3105	PVMSVGACMDBUF pIter, pNext;
3106	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3107	{
3108	if (pIter->hdr.id == 0)
3109	continue;
3110
3111	RTListNodeRemove(&pIter->nodeBuffer);
3112	--pCmdBufCtx->cSubmitted;
3113	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3114	}
3115	}
3116	else
3117	{
3118	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3119	}
3120	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3121
3122	PVMSVGACMDBUF pIter, pNext;
3123	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3124	{
3125	RTListNodeRemove(&pIter->nodeBuffer);
3126	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3127	vmsvgaR3CmdBufFree(pIter);
3128	}
3129
3130	return SVGA_CB_STATUS_COMPLETED;
3131	}
3132
3133
3134	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3135	* Increments the size of the command cbCmd by a_cbMore.
3136	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3137	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3138	*/
3139	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3140	if (1) { \
3141	cbCmd += (a_cbMore); \
3142	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3143	RT_UNTRUSTED_VALIDATED_FENCE(); \
3144	} else do {} while (0)
3145
3146
3147	/** Processes Device Context command buffer.
3148	*
3149	* @param pDevIns The device instance.
3150	* @param pSvgaR3State VMSVGA R3 state.
3151	* @param pvCommands Pointer to the command buffer.
3152	* @param cbCommands Size of the command buffer.
3153	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3154	* @return SVGACBStatus code.
3155	* @thread EMT
3156	*/
3157	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3158	{
3159	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3160
3161	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3162	uint32_t cbRemain = cbCommands;
3163	while (cbRemain)
3164	{
3165	/* Command identifier is a 32 bit value. */
3166	if (cbRemain < sizeof(uint32_t))
3167	{
3168	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3169	break;
3170	}
3171
3172	/* Fetch the command id. */
3173	uint32_t const cmdId = (uint32_t )pu8Cmd;
3174	uint32_t cbCmd = sizeof(uint32_t);
3175	switch (cmdId)
3176	{
3177	case SVGA_DC_CMD_NOP:
3178	{
3179	/* NOP */
3180	break;
3181	}
3182
3183	case SVGA_DC_CMD_START_STOP_CONTEXT:
3184	{
3185	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3186	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3187	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3188	break;
3189	}
3190
3191	case SVGA_DC_CMD_PREEMPT:
3192	{
3193	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3194	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3195	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3196	break;
3197	}
3198
3199	default:
3200	{
3201	/* Unsupported command. */
3202	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3203	break;
3204	}
3205	}
3206
3207	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3208	break;
3209
3210	pu8Cmd += cbCmd;
3211	cbRemain -= cbCmd;
3212	}
3213
3214	Assert(cbRemain <= cbCommands);
3215	*poffNextCmd = cbCommands - cbRemain;
3216	return CBstatus;
3217	}
3218
3219
3220	/** Submits a device context command buffer for synchronous processing.
3221	*
3222	* @param pDevIns The device instance.
3223	* @param pThisCC The VGA/VMSVGA state for the current context.
3224	* @param ppCmdBuf Pointer to the command buffer pointer.
3225	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3226	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3227	* @return SVGACBStatus code.
3228	* @thread EMT
3229	*/
3230	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3231	{
3232	/* Synchronously process the device context commands. */
3233	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3234	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3235	}
3236
3237	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3238	*
3239	* @param pDevIns The device instance.
3240	* @param pThis The shared VGA/VMSVGA state.
3241	* @param pThisCC The VGA/VMSVGA state for the current context.
3242	* @param ppCmdBuf Pointer to the command buffer pointer.
3243	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3244	* @return SVGACBStatus code.
3245	* @thread EMT
3246	*/
3247	static SVGACBStatus vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3248	{
3249	/* Command buffer submission. */
3250	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3251
3252	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3253
3254	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3255	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3256
3257	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3258	AssertRC(rc);
3259
3260	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3261	{
3262	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3263	++pCmdBufCtx->cSubmitted;
3264	ppCmdBuf = NULL; / Consume the buffer. */
3265	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3266	}
3267	else
3268	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3269
3270	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3271
3272	/* Inform the FIFO thread. */
3273	if (*ppCmdBuf == NULL)
3274	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3275
3276	return CBstatus;
3277	}
3278
3279
3280	/** SVGA_REG_COMMAND_LOW write handler.
3281	* Submits a command buffer to the FIFO thread or processes a device context command.
3282	*
3283	* @param pDevIns The device instance.
3284	* @param pThis The shared VGA/VMSVGA state.
3285	* @param pThisCC The VGA/VMSVGA state for the current context.
3286	* @param GCPhysCB Guest physical address of the command buffer header.
3287	* @param CBCtx Context the command buffer is submitted to.
3288	* @thread EMT
3289	*/
3290	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3291	{
3292	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3293
3294	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3295	uint32_t offNextCmd = 0;
3296	uint32_t fIRQ = 0;
3297
3298	/* Get the context if the device has the capability. */
3299	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3300	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3301	{
3302	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3303	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3304	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3305	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3306	RT_UNTRUSTED_VALIDATED_FENCE();
3307	}
3308
3309	/* Allocate a new command buffer. */
3310	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3311	if (RT_LIKELY(pCmdBuf))
3312	{
3313	pCmdBuf->GCPhysCB = GCPhysCB;
3314
3315	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3316	if (RT_SUCCESS(rc))
3317	{
3318	/* Verify the command buffer header. */
3319	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3320	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ)) == 0 /* No unexpected flags. */
3321	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3322	{
3323	RT_UNTRUSTED_VALIDATED_FENCE();
3324
3325	/* Read the command buffer content. */
3326	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3327	if (pCmdBuf->pvCommands)
3328	{
3329	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3330	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3331	if (RT_SUCCESS(rc))
3332	{
3333	/* Submit the buffer. Device context buffers will be processed synchronously. */
3334	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3335	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3336	CBstatus = vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, &pCmdBuf);
3337	else
3338	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3339	}
3340	else
3341	{
3342	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3343	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3344	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3345	}
3346	}
3347	else
3348	{
3349	/* No memory for commands. */
3350	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3351	}
3352	}
3353	else
3354	{
3355	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3356	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3357	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3358	}
3359	}
3360	else
3361	{
3362	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3363	ASSERT_GUEST_FAILED();
3364	/* Do not attempt to write the status. */
3365	}
3366
3367	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3368	vmsvgaR3CmdBufFree(pCmdBuf);
3369	}
3370	else
3371	{
3372	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3373	ASSERT_GUEST_FAILED();
3374	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3375	}
3376
3377	if (CBstatus != SVGA_CB_STATUS_NONE)
3378	{
3379	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf->hdr.length, fIRQ));
3380	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3381	if (fIRQ)
3382	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3383	}
3384	}
3385
3386
3387	/** Checks if there are some buffers to be processed.
3388	*
3389	* @param pThisCC The VGA/VMSVGA state for the current context.
3390	* @return true if buffers must be processed.
3391	* @thread FIFO
3392	*/
3393	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3394	{
3395	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3396	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3397	}
3398
3399
3400	/** Processes a command buffer.
3401	*
3402	* @param pDevIns The device instance.
3403	* @param pThis The shared VGA/VMSVGA state.
3404	* @param pThisCC The VGA/VMSVGA state for the current context.
3405	* @param pvCommands Pointer to the command buffer.
3406	* @param cbCommands Size of the command buffer.
3407	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3408	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3409	* @return SVGACBStatus code.
3410	* @thread FIFO
3411	*/
3412	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3413	{
3414	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3415	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3416
3417	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3418
3419	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3420	uint32_t cbRemain = cbCommands;
3421	while (cbRemain)
3422	{
3423	/* Command identifier is a 32 bit value. */
3424	if (cbRemain < sizeof(uint32_t))
3425	{
3426	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3427	break;
3428	}
3429
3430	/* Fetch the command id.
3431	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3432	* warning. Because we support some obsolete and deprecated commands, which are not included in
3433	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3434	*/
3435	uint32_t const cmdId = (uint32_t )pu8Cmd;
3436	uint32_t cbCmd = sizeof(uint32_t);
3437
3438	LogFlowFunc(("%s %d\n", vmsvgaR3FifoCmdToString(cmdId), cmdId));
3439
3440	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3441	* I.e. pu8Cmd + cbCmd must point to the next command.
3442	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3443	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3444	*/
3445	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3446	switch (cmdId)
3447	{
3448	case SVGA_CMD_INVALID_CMD:
3449	{
3450	/* Nothing to do. */
3451	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3452	break;
3453	}
3454
3455	case SVGA_CMD_FENCE:
3456	{
3457	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3458	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3459	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3460	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3461
3462	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3463	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3464	{
3465	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3466
3467	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3468	{
3469	Log(("any fence irq\n"));
3470	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3471	}
3472	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3473	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3474	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3475	{
3476	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3477	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3478	}
3479	}
3480	else
3481	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3482	break;
3483	}
3484
3485	case SVGA_CMD_UPDATE:
3486	{
3487	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3488	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3489	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3490	break;
3491	}
3492
3493	case SVGA_CMD_UPDATE_VERBOSE:
3494	{
3495	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3496	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3497	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3498	break;
3499	}
3500
3501	case SVGA_CMD_DEFINE_CURSOR:
3502	{
3503	/* Followed by bitmap data. */
3504	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3505	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3506
3507	/* Figure out the size of the bitmap data. */
3508	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3509	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3510	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3511	RT_UNTRUSTED_VALIDATED_FENCE();
3512
3513	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3514	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3515	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3516	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3517
3518	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3519	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3520	break;
3521	}
3522
3523	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3524	{
3525	/* Followed by bitmap data. */
3526	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3527	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3528
3529	/* Figure out the size of the bitmap data. */
3530	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3531
3532	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3533	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3534	break;
3535	}
3536
3537	case SVGA_CMD_MOVE_CURSOR:
3538	{
3539	/* Deprecated; there should be no driver which requires this command. However, if
3540	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3541	* alignment.
3542	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3543	*/
3544	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3545	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3546	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3547	break;
3548	}
3549
3550	case SVGA_CMD_DISPLAY_CURSOR:
3551	{
3552	/* Deprecated; there should be no driver which requires this command. However, if
3553	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3554	* alignment.
3555	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3556	*/
3557	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3558	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3559	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3560	break;
3561	}
3562
3563	case SVGA_CMD_RECT_FILL:
3564	{
3565	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3566	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3567	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3568	break;
3569	}
3570
3571	case SVGA_CMD_RECT_COPY:
3572	{
3573	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3574	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3575	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3576	break;
3577	}
3578
3579	case SVGA_CMD_RECT_ROP_COPY:
3580	{
3581	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3582	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3583	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3584	break;
3585	}
3586
3587	case SVGA_CMD_ESCAPE:
3588	{
3589	/* Followed by 'size' bytes of data. */
3590	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3591	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3592
3593	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3594	RT_UNTRUSTED_VALIDATED_FENCE();
3595
3596	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3597	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3598	break;
3599	}
3600	# ifdef VBOX_WITH_VMSVGA3D
3601	case SVGA_CMD_DEFINE_GMR2:
3602	{
3603	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3604	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3605	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3606	break;
3607	}
3608
3609	case SVGA_CMD_REMAP_GMR2:
3610	{
3611	/* Followed by page descriptors or guest ptr. */
3612	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3613	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3614
3615	/* Calculate the size of what comes after next and fetch it. */
3616	uint32_t cbMore = 0;
3617	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3618	cbMore = sizeof(SVGAGuestPtr);
3619	else
3620	{
3621	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3622	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3623	{
3624	cbMore = cbPageDesc;
3625	pCmd->numPages = 1;
3626	}
3627	else
3628	{
3629	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3630	cbMore = cbPageDesc * pCmd->numPages;
3631	}
3632	}
3633	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3634	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3635	# ifdef DEBUG_GMR_ACCESS
3636	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3637	# endif
3638	break;
3639	}
3640	# endif /* VBOX_WITH_VMSVGA3D */
3641	case SVGA_CMD_DEFINE_SCREEN:
3642	{
3643	/* The size of this command is specified by the guest and depends on capabilities. */
3644	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3645	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3646	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3647	RT_UNTRUSTED_VALIDATED_FENCE();
3648
3649	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3650	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3651	break;
3652	}
3653
3654	case SVGA_CMD_DESTROY_SCREEN:
3655	{
3656	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3657	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3658	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3659	break;
3660	}
3661
3662	case SVGA_CMD_DEFINE_GMRFB:
3663	{
3664	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3665	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3666	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3667	break;
3668	}
3669
3670	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3671	{
3672	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3673	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3674	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3675	break;
3676	}
3677
3678	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3679	{
3680	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3681	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3682	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3683	break;
3684	}
3685
3686	case SVGA_CMD_ANNOTATION_FILL:
3687	{
3688	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3689	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3690	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3691	break;
3692	}
3693
3694	case SVGA_CMD_ANNOTATION_COPY:
3695	{
3696	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3697	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3698	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3699	break;
3700	}
3701
3702	default:
3703	{
3704	# ifdef VBOX_WITH_VMSVGA3D
3705	if ( cmdId >= SVGA_3D_CMD_BASE
3706	&& cmdId < SVGA_3D_CMD_MAX)
3707	{
3708	RT_UNTRUSTED_VALIDATED_FENCE();
3709
3710	/* All 3d commands start with a common header, which defines the identifier and the size
3711	* of the command. The identifier has been already read. Fetch the size.
3712	*/
3713	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3714	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3715	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3716	if (RT_LIKELY(pThis->svga.f3DEnabled))
3717	{ /* likely */ }
3718	else
3719	{
3720	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3721	break;
3722	}
3723
3724	/* Command data begins after the 32 bit command length. */
3725	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3726	if (RT_SUCCESS(rc))
3727	{ /* likely */ }
3728	else
3729	{
3730	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3731	break;
3732	}
3733	}
3734	else
3735	# endif /* VBOX_WITH_VMSVGA3D */
3736	{
3737	/* Unsupported command. */
3738	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3739	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3740	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3741	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3742	break;
3743	}
3744	}
3745	}
3746
3747	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3748	break;
3749
3750	pu8Cmd += cbCmd;
3751	cbRemain -= cbCmd;
3752
3753	/* If this is not the last command in the buffer, then generate IRQ, if required.
3754	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3755	* in the buffer (usually the case).
3756	*/
3757	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3758	{ /* likely */ }
3759	else
3760	{
3761	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3762	*pu32IrqStatus = 0;
3763	}
3764	}
3765
3766	Assert(cbRemain <= cbCommands);
3767	*poffNextCmd = cbCommands - cbRemain;
3768	return CBstatus;
3769	}
3770
3771
3772	/** Process command buffers.
3773	*
3774	* @param pDevIns The device instance.
3775	* @param pThis The shared VGA/VMSVGA state.
3776	* @param pThisCC The VGA/VMSVGA state for the current context.
3777	* @param pThread Handle of the FIFO thread.
3778	* @thread FIFO
3779	*/
3780	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3781	{
3782	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3783
3784	for (;;)
3785	{
3786	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3787	break;
3788
3789	/* See if there is a submitted buffer. */
3790	PVMSVGACMDBUF pCmdBuf = NULL;
3791
3792	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3793	AssertRC(rc);
3794
3795	/* It seems that a higher queue index has a higher priority.
3796	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3797	*/
3798	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3799	{
3800	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3801	if (pCmdBufCtx)
3802	{
3803	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3804	if (pCmdBuf)
3805	{
3806	Assert(pCmdBufCtx->cSubmitted > 0);
3807	--pCmdBufCtx->cSubmitted;
3808	break;
3809	}
3810	}
3811	}
3812
3813	if (!pCmdBuf)
3814	{
3815	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3816	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3817	break;
3818	}
3819
3820	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3821
3822	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3823	uint32_t offNextCmd = 0;
3824	uint32_t u32IrqStatus = 0;
3825
3826	/* Process one buffer. */
3827	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3828
3829	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3830	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3831	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3832	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3833
3834	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3835	if (u32IrqStatus)
3836	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3837
3838	vmsvgaR3CmdBufFree(pCmdBuf);
3839	}
3840	}
3841
3842
3843	/**
3844	* Worker for vmsvgaR3FifoThread that handles an external command.
3845	*
3846	* @param pDevIns The device instance.
3847	* @param pThis The shared VGA/VMSVGA instance data.
3848	* @param pThisCC The VGA/VMSVGA state for ring-3.
3849	*/
3850	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3851	{
3852	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3853	switch (pThis->svga.u8FIFOExtCommand)
3854	{
3855	case VMSVGA_FIFO_EXTCMD_RESET:
3856	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3857	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3858
3859	vmsvgaR3ResetScreens(pThis, pThisCC);
3860	# ifdef VBOX_WITH_VMSVGA3D
3861	if (pThis->svga.f3DEnabled)
3862	{
3863	/* The 3d subsystem must be reset from the fifo thread. */
3864	vmsvga3dReset(pThisCC);
3865	}
3866	# endif
3867	break;
3868
3869	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3870	Log(("vmsvgaR3FifoLoop: power off.\n"));
3871	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3872
3873	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3874	vmsvgaR3ResetScreens(pThis, pThisCC);
3875	break;
3876
3877	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3878	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3879	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3880	# ifdef VBOX_WITH_VMSVGA3D
3881	if (pThis->svga.f3DEnabled)
3882	{
3883	/* The 3d subsystem must be shut down from the fifo thread. */
3884	vmsvga3dTerminate(pThisCC);
3885	}
3886	# endif
3887	break;
3888
3889	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3890	{
3891	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3892	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3893	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3894	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3895	# ifdef VBOX_WITH_VMSVGA3D
3896	if (pThis->svga.f3DEnabled)
3897	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3898	# endif
3899	break;
3900	}
3901
3902	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3903	{
3904	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3905	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3906	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3907	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3908	# ifdef VBOX_WITH_VMSVGA3D
3909	if (pThis->svga.f3DEnabled)
3910	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3911	# endif
3912	break;
3913	}
3914
3915	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3916	{
3917	# ifdef VBOX_WITH_VMSVGA3D
3918	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3919	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3920	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3921	# endif
3922	break;
3923	}
3924
3925
3926	default:
3927	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3928	break;
3929	}
3930
3931	/*
3932	* Signal the end of the external command.
3933	*/
3934	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3935	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3936	ASMMemoryFence(); /* paranoia^2 */
3937	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3938	AssertLogRelRC(rc);
3939	}
3940
3941	/**
3942	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3943	* doing a job on the FIFO thread (even when it's officially suspended).
3944	*
3945	* @returns VBox status code (fully asserted).
3946	* @param pDevIns The device instance.
3947	* @param pThis The shared VGA/VMSVGA instance data.
3948	* @param pThisCC The VGA/VMSVGA state for ring-3.
3949	* @param uExtCmd The command to execute on the FIFO thread.
3950	* @param pvParam Pointer to command parameters.
3951	* @param cMsWait The time to wait for the command, given in
3952	* milliseconds.
3953	*/
3954	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3955	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3956	{
3957	Assert(cMsWait >= RT_MS_1SEC * 5);
3958	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3959	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3960
3961	int rc;
3962	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3963	PDMTHREADSTATE enmState = pThread->enmState;
3964	if (enmState == PDMTHREADSTATE_SUSPENDED)
3965	{
3966	/*
3967	* The thread is suspended, we have to temporarily wake it up so it can
3968	* perform the task.
3969	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3970	*/
3971	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3972	/* Post the request. */
3973	pThis->svga.fFifoExtCommandWakeup = true;
3974	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3975	pThis->svga.u8FIFOExtCommand = uExtCmd;
3976	ASMMemoryFence(); /* paranoia^3 */
3977
3978	/* Resume the thread. */
3979	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3980	AssertLogRelRC(rc);
3981	if (RT_SUCCESS(rc))
3982	{
3983	/* Wait. Take care in case the semaphore was already posted (same as below). */
3984	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3985	if ( rc == VINF_SUCCESS
3986	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3987	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3988	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3989	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3990
3991	/* suspend the thread */
3992	pThis->svga.fFifoExtCommandWakeup = false;
3993	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3994	AssertLogRelRC(rc2);
3995	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3996	rc = rc2;
3997	}
3998	pThis->svga.fFifoExtCommandWakeup = false;
3999	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4000	}
4001	else if (enmState == PDMTHREADSTATE_RUNNING)
4002	{
4003	/*
4004	* The thread is running, should only happen during reset and vmsvga3dsfc.
4005	* We ASSUME not racing code here, both wrt thread state and ext commands.
4006	*/
4007	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4008	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4009
4010	/* Post the request. */
4011	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4012	pThis->svga.u8FIFOExtCommand = uExtCmd;
4013	ASMMemoryFence(); /* paranoia^2 */
4014	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4015	AssertLogRelRC(rc);
4016
4017	/* Wait. Take care in case the semaphore was already posted (same as above). */
4018	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4019	if ( rc == VINF_SUCCESS
4020	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4021	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4022	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4023	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4024
4025	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4026	}
4027	else
4028	{
4029	/*
4030	* Something is wrong with the thread!
4031	*/
4032	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4033	rc = VERR_INVALID_STATE;
4034	}
4035	return rc;
4036	}
4037
4038
4039	/**
4040	* Marks the FIFO non-busy, notifying any waiting EMTs.
4041	*
4042	* @param pDevIns The device instance.
4043	* @param pThis The shared VGA/VMSVGA instance data.
4044	* @param pThisCC The VGA/VMSVGA state for ring-3.
4045	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4046	* @param offFifoMin The start byte offset of the command FIFO.
4047	*/
4048	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4049	{
4050	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4051	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4052	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4053
4054	/* Wake up any waiting EMTs. */
4055	if (pSVGAState->cBusyDelayedEmts > 0)
4056	{
4057	# ifdef VMSVGA_USE_EMT_HALT_CODE
4058	PVM pVM = PDMDevHlpGetVM(pDevIns);
4059	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4060	if (idCpu != NIL_VMCPUID)
4061	{
4062	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4063	while (idCpu-- > 0)
4064	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4065	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4066	}
4067	# else
4068	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4069	AssertRC(rc2);
4070	# endif
4071	}
4072	}
4073
4074	/**
4075	* Reads (more) payload into the command buffer.
4076	*
4077	* @returns pbBounceBuf on success
4078	* @retval (void *)1 if the thread was requested to stop.
4079	* @retval NULL on FIFO error.
4080	*
4081	* @param cbPayloadReq The number of bytes of payload requested.
4082	* @param pFIFO The FIFO.
4083	* @param offCurrentCmd The FIFO byte offset of the current command.
4084	* @param offFifoMin The start byte offset of the command FIFO.
4085	* @param offFifoMax The end byte offset of the command FIFO.
4086	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4087	* always sufficient size.
4088	* @param pcbAlreadyRead How much payload we've already read into the bounce
4089	* buffer. (We will NEVER re-read anything.)
4090	* @param pThread The calling PDM thread handle.
4091	* @param pThis The shared VGA/VMSVGA instance data.
4092	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4093	* statistics collection.
4094	* @param pDevIns The device instance.
4095	*/
4096	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4097	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4098	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4099	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4100	{
4101	Assert(pbBounceBuf);
4102	Assert(pcbAlreadyRead);
4103	Assert(offFifoMin < offFifoMax);
4104	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4105	Assert(offFifoMax <= pThis->svga.cbFIFO);
4106
4107	/*
4108	* Check if the requested payload size has already been satisfied .
4109	* .
4110	* When called to read more, the caller is responsible for making sure the .
4111	* new command size (cbRequsted) never is smaller than what has already .
4112	* been read.
4113	*/
4114	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4115	if (cbPayloadReq <= cbAlreadyRead)
4116	{
4117	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4118	return pbBounceBuf;
4119	}
4120
4121	/*
4122	* Commands bigger than the fifo buffer are invalid.
4123	*/
4124	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4125	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4126	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4127	NULL);
4128
4129	/*
4130	* Move offCurrentCmd past the command dword.
4131	*/
4132	offCurrentCmd += sizeof(uint32_t);
4133	if (offCurrentCmd >= offFifoMax)
4134	offCurrentCmd = offFifoMin;
4135
4136	/*
4137	* Do we have sufficient payload data available already?
4138	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4139	*/
4140	uint32_t cbAfter, cbBefore;
4141	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4142	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4143	if (offNextCmd >= offCurrentCmd)
4144	{
4145	if (RT_LIKELY(offNextCmd < offFifoMax))
4146	cbAfter = offNextCmd - offCurrentCmd;
4147	else
4148	{
4149	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4150	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4151	offNextCmd, offFifoMin, offFifoMax));
4152	cbAfter = offFifoMax - offCurrentCmd;
4153	}
4154	cbBefore = 0;
4155	}
4156	else
4157	{
4158	cbAfter = offFifoMax - offCurrentCmd;
4159	if (offNextCmd >= offFifoMin)
4160	cbBefore = offNextCmd - offFifoMin;
4161	else
4162	{
4163	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4164	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4165	offNextCmd, offFifoMin, offFifoMax));
4166	cbBefore = 0;
4167	}
4168	}
4169	if (cbAfter + cbBefore < cbPayloadReq)
4170	{
4171	/*
4172	* Insufficient, must wait for it to arrive.
4173	*/
4174	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4175	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4176	for (uint32_t i = 0;; i++)
4177	{
4178	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4179	{
4180	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4181	return (void *)(uintptr_t)1;
4182	}
4183	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4184	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4185
4186	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4187
4188	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4189	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4190	if (offNextCmd >= offCurrentCmd)
4191	{
4192	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4193	cbBefore = 0;
4194	}
4195	else
4196	{
4197	cbAfter = offFifoMax - offCurrentCmd;
4198	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4199	}
4200
4201	if (cbAfter + cbBefore >= cbPayloadReq)
4202	break;
4203	}
4204	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4205	}
4206
4207	/*
4208	* Copy out the memory and update what pcbAlreadyRead points to.
4209	*/
4210	if (cbAfter >= cbPayloadReq)
4211	memcpy(pbBounceBuf + cbAlreadyRead,
4212	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4213	cbPayloadReq - cbAlreadyRead);
4214	else
4215	{
4216	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4217	if (cbAlreadyRead < cbAfter)
4218	{
4219	memcpy(pbBounceBuf + cbAlreadyRead,
4220	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4221	cbAfter - cbAlreadyRead);
4222	cbAlreadyRead = cbAfter;
4223	}
4224	memcpy(pbBounceBuf + cbAlreadyRead,
4225	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4226	cbPayloadReq - cbAlreadyRead);
4227	}
4228	*pcbAlreadyRead = cbPayloadReq;
4229	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4230	return pbBounceBuf;
4231	}
4232
4233
4234	/**
4235	* Sends cursor position and visibility information from the FIFO to the front-end.
4236	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4237	*/
4238	static uint32_t
4239	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4240	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4241	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4242	{
4243	/*
4244	* Check if the cursor update counter has changed and try get a stable
4245	* set of values if it has. This is race-prone, especially consindering
4246	* the screen ID, but little we can do about that.
4247	*/
4248	uint32_t x, y, fVisible, idScreen;
4249	for (uint32_t i = 0; ; i++)
4250	{
4251	x = pFIFO[SVGA_FIFO_CURSOR_X];
4252	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4253	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4254	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4255	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4256	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4257	\|\| i > 3)
4258	break;
4259	if (i == 0)
4260	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4261	ASMNopPause();
4262	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4263	}
4264
4265	/*
4266	* Check if anything has changed, as calling into pDrv is not light-weight.
4267	*/
4268	if ( *pxLast == x
4269	&& *pyLast == y
4270	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4271	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4272	else
4273	{
4274	/*
4275	* Detected changes.
4276	*
4277	* We handle global, not per-screen visibility information by sending
4278	* pfnVBVAMousePointerShape without shape data.
4279	*/
4280	*pxLast = x;
4281	*pyLast = y;
4282	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4283	if (idScreen != SVGA_ID_INVALID)
4284	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4285	else if (*pfLastVisible != fVisible)
4286	{
4287	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4288	*pfLastVisible = fVisible;
4289	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4290	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4291	}
4292	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4293	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4294	}
4295
4296	/*
4297	* Update done. Signal this to the guest.
4298	*/
4299	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4300
4301	return uCursorUpdateCount;
4302	}
4303
4304
4305	/**
4306	* Checks if there is work to be done, either cursor updating or FIFO commands.
4307	*
4308	* @returns true if pending work, false if not.
4309	* @param pThisCC The VGA/VMSVGA state for ring-3.
4310	* @param uLastCursorCount The last cursor update counter value.
4311	*/
4312	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4313	{
4314	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4315	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4316	AssertReturn(pFIFO, false);
4317
4318	if (vmsvgaR3CmdBufHasWork(pThisCC))
4319	return true;
4320
4321	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4322	return true;
4323
4324	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4325	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4326	return true;
4327
4328	return false;
4329	}
4330
4331
4332	/**
4333	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4334	*
4335	* @param pDevIns The device instance.
4336	* @param pThis The shared VGA/VMSVGA instance data.
4337	* @param pThisCC The VGA/VMSVGA state for ring-3.
4338	*/
4339	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4340	{
4341	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4342	to recheck it before doing the signalling. */
4343	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4344	&& pThis->svga.fFIFOThreadSleeping
4345	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4346	{
4347	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4348	AssertRC(rc);
4349	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4350	}
4351	}
4352
4353
4354	/**
4355	* Called by the FIFO thread to process pending actions.
4356	*
4357	* @param pDevIns The device instance.
4358	* @param pThis The shared VGA/VMSVGA instance data.
4359	* @param pThisCC The VGA/VMSVGA state for ring-3.
4360	*/
4361	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4362	{
4363	RT_NOREF(pDevIns);
4364
4365	/* Currently just mode changes. */
4366	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4367	{
4368	vmsvgaR3ChangeMode(pThis, pThisCC);
4369	# ifdef VBOX_WITH_VMSVGA3D
4370	if (pThisCC->svga.p3dState != NULL)
4371	vmsvga3dChangeMode(pThisCC);
4372	# endif
4373	}
4374	}
4375
4376
4377	/*
4378	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4379	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4380	*/
4381	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4382	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4383	*
4384	* Will break out of the switch on failure.
4385	* Will restart and quit the loop if the thread was requested to stop.
4386	*
4387	* @param a_PtrVar Request variable pointer.
4388	* @param a_Type Request typedef (not pointer) for casting.
4389	* @param a_cbPayloadReq How much payload to fetch.
4390	* @remarks Accesses a bunch of variables in the current scope!
4391	*/
4392	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4393	if (1) { \
4394	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4395	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4396	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4397	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4398	} else do {} while (0)
4399	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4400	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4401	* buffer after figuring out the actual command size.
4402	*
4403	* Will break out of the switch on failure.
4404	*
4405	* @param a_PtrVar Request variable pointer.
4406	* @param a_Type Request typedef (not pointer) for casting.
4407	* @param a_cbPayloadReq How much payload to fetch.
4408	* @remarks Accesses a bunch of variables in the current scope!
4409	*/
4410	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4411	if (1) { \
4412	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4413	} else do {} while (0)
4414
4415	/**
4416	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4417	*/
4418	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4419	{
4420	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4421	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4422	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4423	int rc;
4424
4425	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4426	if (pThis->svga.f3DEnabled)
4427	{
4428	/* The FIFO thread may use X API for accelerated screen output. */
4429	XInitThreads();
4430	}
4431	# endif
4432
4433	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4434	return VINF_SUCCESS;
4435
4436	/*
4437	* Special mode where we only execute an external command and the go back
4438	* to being suspended. Currently, all ext cmds ends up here, with the reset
4439	* one also being eligble for runtime execution further down as well.
4440	*/
4441	if (pThis->svga.fFifoExtCommandWakeup)
4442	{
4443	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4444	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4445	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4446	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4447	else
4448	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4449	return VINF_SUCCESS;
4450	}
4451
4452
4453	/*
4454	* Signal the semaphore to make sure we don't wait for 250ms after a
4455	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4456	*/
4457	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4458
4459	/*
4460	* Allocate a bounce buffer for command we get from the FIFO.
4461	* (All code must return via the end of the function to free this buffer.)
4462	*/
4463	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4464	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4465
4466	/*
4467	* Polling/sleep interval config.
4468	*
4469	* We wait for an a short interval if the guest has recently given us work
4470	* to do, but the interval increases the longer we're kept idle. Once we've
4471	* reached the refresh timer interval, we'll switch to extended waits,
4472	* depending on it or the guest to kick us into action when needed.
4473	*
4474	* Should the refresh time go fishing, we'll just continue increasing the
4475	* sleep length till we reaches the 250 ms max after about 16 seconds.
4476	*/
4477	RTMSINTERVAL const cMsMinSleep = 16;
4478	RTMSINTERVAL const cMsIncSleep = 2;
4479	RTMSINTERVAL const cMsMaxSleep = 250;
4480	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4481	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4482
4483	/*
4484	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4485	*
4486	* Initialize with values that will detect an update from the guest.
4487	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4488	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4489	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4490	*/
4491	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4492	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4493	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4494	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4495	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4496
4497	/*
4498	* The FIFO loop.
4499	*/
4500	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4501	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4502	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4503	{
4504	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4505	/*
4506	* Should service the run loop every so often.
4507	*/
4508	if (pThis->svga.f3DEnabled)
4509	vmsvga3dCocoaServiceRunLoop();
4510	# endif
4511
4512	/* First check any pending actions. */
4513	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4514
4515	/*
4516	* Unless there's already work pending, go to sleep for a short while.
4517	* (See polling/sleep interval config above.)
4518	*/
4519	if ( fBadOrDisabledFifo
4520	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4521	{
4522	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4523	Assert(pThis->cMilliesRefreshInterval > 0);
4524	if (cMsSleep < pThis->cMilliesRefreshInterval)
4525	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4526	else
4527	{
4528	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4529	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4530	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4531	# endif
4532	if ( !fBadOrDisabledFifo
4533	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4534	rc = VINF_SUCCESS;
4535	else
4536	{
4537	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4538	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4539	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4540	}
4541	}
4542	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4543	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4544	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4545	{
4546	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4547	break;
4548	}
4549	}
4550	else
4551	rc = VINF_SUCCESS;
4552	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4553	if (rc == VERR_TIMEOUT)
4554	{
4555	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4556	{
4557	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4558	continue;
4559	}
4560	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4561
4562	Log(("vmsvgaR3FifoLoop: timeout\n"));
4563	}
4564	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4565	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4566	cMsSleep = cMsMinSleep;
4567
4568	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4569	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4570	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4571
4572	/*
4573	* Handle external commands (currently only reset).
4574	*/
4575	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4576	{
4577	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4578	continue;
4579	}
4580
4581	/*
4582	* If guest misbehaves, then do nothing.
4583	*/
4584	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4585	{
4586	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4587	cMsSleep = cMsExtendedSleep;
4588	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4589	continue;
4590	}
4591
4592	/*
4593	* The device must be enabled and configured.
4594	*/
4595	if ( !pThis->svga.fEnabled
4596	\|\| !pThis->svga.fConfigured)
4597	{
4598	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4599	fBadOrDisabledFifo = true;
4600	cMsSleep = cMsMaxSleep; /* cheat */
4601	continue;
4602	}
4603
4604	/*
4605	* Get and check the min/max values. We ASSUME that they will remain
4606	* unchanged while we process requests. A further ASSUMPTION is that
4607	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4608	* we don't read it back while in the loop.
4609	*/
4610	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4611	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4612	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4613	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4614	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4615	\|\| offFifoMax <= offFifoMin
4616	\|\| offFifoMax > pThis->svga.cbFIFO
4617	\|\| (offFifoMax & 3) != 0
4618	\|\| (offFifoMin & 3) != 0
4619	\|\| offCurrentCmd < offFifoMin
4620	\|\| offCurrentCmd > offFifoMax))
4621	{
4622	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4623	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4624	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4625	fBadOrDisabledFifo = true;
4626	continue;
4627	}
4628	RT_UNTRUSTED_VALIDATED_FENCE();
4629	if (RT_UNLIKELY(offCurrentCmd & 3))
4630	{
4631	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4632	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4633	offCurrentCmd &= ~UINT32_C(3);
4634	}
4635
4636	/*
4637	* Update the cursor position before we start on the FIFO commands.
4638	*/
4639	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4640	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4641	{
4642	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4643	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4644	{ /* halfways likely */ }
4645	else
4646	{
4647	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4648	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4649	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4650	}
4651	}
4652
4653	/*
4654	* Mark the FIFO as busy.
4655	*/
4656	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4657	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4658	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4659
4660	/*
4661	* Process all submitted command buffers.
4662	*/
4663	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4664
4665	/*
4666	* Execute all queued FIFO commands.
4667	* Quit if pending external command or changes in the thread state.
4668	*/
4669	bool fDone = false;
4670	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4671	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4672	{
4673	uint32_t cbPayload = 0;
4674	uint32_t u32IrqStatus = 0;
4675
4676	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4677
4678	/* First check any pending actions. */
4679	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4680
4681	/* Check for pending external commands (reset). */
4682	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4683	break;
4684
4685	/*
4686	* Process the command.
4687	*/
4688	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4689	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4690	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4691	*/
4692	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4693	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4694	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4695	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4696	switch (enmCmdId)
4697	{
4698	case SVGA_CMD_INVALID_CMD:
4699	/* Nothing to do. */
4700	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4701	break;
4702
4703	case SVGA_CMD_FENCE:
4704	{
4705	SVGAFifoCmdFence *pCmdFence;
4706	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4707	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4708	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4709	{
4710	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4711	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4712
4713	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4714	{
4715	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4716	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4717	}
4718	else
4719	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4720	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4721	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4722	{
4723	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4724	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4725	}
4726	}
4727	else
4728	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4729	break;
4730	}
4731
4732	case SVGA_CMD_UPDATE:
4733	{
4734	SVGAFifoCmdUpdate *pCmd;
4735	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4736	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4737	break;
4738	}
4739
4740	case SVGA_CMD_UPDATE_VERBOSE:
4741	{
4742	SVGAFifoCmdUpdateVerbose *pCmd;
4743	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4744	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4745	break;
4746	}
4747
4748	case SVGA_CMD_DEFINE_CURSOR:
4749	{
4750	/* Followed by bitmap data. */
4751	SVGAFifoCmdDefineCursor *pCmd;
4752	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4753
4754	/* Figure out the size of the bitmap data. */
4755	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4756	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4757	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4758	RT_UNTRUSTED_VALIDATED_FENCE();
4759
4760	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4761	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4762	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4763	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4764
4765	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4766	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4767	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4768	break;
4769	}
4770
4771	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4772	{
4773	/* Followed by bitmap data. */
4774	SVGAFifoCmdDefineAlphaCursor *pCmd;
4775	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4776
4777	/* Figure out the size of the bitmap data. */
4778	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4779
4780	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4781	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4782	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4783	break;
4784	}
4785
4786	case SVGA_CMD_MOVE_CURSOR:
4787	{
4788	/* Deprecated; there should be no driver which requires this command. However, if
4789	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4790	* alignment.
4791	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4792	*/
4793	SVGAFifoCmdMoveCursor *pCmd;
4794	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4795	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4796	break;
4797	}
4798
4799	case SVGA_CMD_DISPLAY_CURSOR:
4800	{
4801	/* Deprecated; there should be no driver which requires this command. However, if
4802	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4803	* alignment.
4804	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4805	*/
4806	SVGAFifoCmdDisplayCursor *pCmd;
4807	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4808	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4809	break;
4810	}
4811
4812	case SVGA_CMD_RECT_FILL:
4813	{
4814	SVGAFifoCmdRectFill *pCmd;
4815	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4816	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4817	break;
4818	}
4819
4820	case SVGA_CMD_RECT_COPY:
4821	{
4822	SVGAFifoCmdRectCopy *pCmd;
4823	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4824	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4825	break;
4826	}
4827
4828	case SVGA_CMD_RECT_ROP_COPY:
4829	{
4830	SVGAFifoCmdRectRopCopy *pCmd;
4831	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4832	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4833	break;
4834	}
4835
4836	case SVGA_CMD_ESCAPE:
4837	{
4838	/* Followed by 'size' bytes of data. */
4839	SVGAFifoCmdEscape *pCmd;
4840	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4841
4842	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4843	RT_UNTRUSTED_VALIDATED_FENCE();
4844
4845	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4846	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4847	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4848	break;
4849	}
4850	# ifdef VBOX_WITH_VMSVGA3D
4851	case SVGA_CMD_DEFINE_GMR2:
4852	{
4853	SVGAFifoCmdDefineGMR2 *pCmd;
4854	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4855	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4856	break;
4857	}
4858
4859	case SVGA_CMD_REMAP_GMR2:
4860	{
4861	/* Followed by page descriptors or guest ptr. */
4862	SVGAFifoCmdRemapGMR2 *pCmd;
4863	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4864
4865	/* Calculate the size of what comes after next and fetch it. */
4866	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4867	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4868	cbCmd += sizeof(SVGAGuestPtr);
4869	else
4870	{
4871	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4872	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4873	{
4874	cbCmd += cbPageDesc;
4875	pCmd->numPages = 1;
4876	}
4877	else
4878	{
4879	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4880	cbCmd += cbPageDesc * pCmd->numPages;
4881	}
4882	}
4883	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4884	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4885	# ifdef DEBUG_GMR_ACCESS
4886	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4887	# endif
4888	break;
4889	}
4890	# endif // VBOX_WITH_VMSVGA3D
4891	case SVGA_CMD_DEFINE_SCREEN:
4892	{
4893	/* The size of this command is specified by the guest and depends on capabilities. */
4894	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4895
4896	SVGAFifoCmdDefineScreen *pCmd;
4897	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4898	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4899	RT_UNTRUSTED_VALIDATED_FENCE();
4900
4901	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4902	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4903	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4904	break;
4905	}
4906
4907	case SVGA_CMD_DESTROY_SCREEN:
4908	{
4909	SVGAFifoCmdDestroyScreen *pCmd;
4910	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4911	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4912	break;
4913	}
4914
4915	case SVGA_CMD_DEFINE_GMRFB:
4916	{
4917	SVGAFifoCmdDefineGMRFB *pCmd;
4918	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4919	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4920	break;
4921	}
4922
4923	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4924	{
4925	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4926	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4927	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4928	break;
4929	}
4930
4931	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4932	{
4933	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4934	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4935	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4936	break;
4937	}
4938
4939	case SVGA_CMD_ANNOTATION_FILL:
4940	{
4941	SVGAFifoCmdAnnotationFill *pCmd;
4942	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4943	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4944	break;
4945	}
4946
4947	case SVGA_CMD_ANNOTATION_COPY:
4948	{
4949	SVGAFifoCmdAnnotationCopy *pCmd;
4950	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4951	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4952	break;
4953	}
4954
4955	default:
4956	# ifdef VBOX_WITH_VMSVGA3D
4957	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4958	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4959	{
4960	RT_UNTRUSTED_VALIDATED_FENCE();
4961
4962	/* All 3d commands start with a common header, which defines the identifier and the size
4963	* of the command. The identifier has been already read from FIFO. Fetch the size.
4964	*/
4965	uint32_t *pcbCmd;
4966	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
4967	uint32_t const cbCmd = *pcbCmd;
4968	AssertBreak(cbCmd < pThis->svga.cbFIFO);
4969	uint32_t *pu32Cmd;
4970	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
4971	pu32Cmd++; /* Skip the command size. */
4972
4973	if (RT_LIKELY(pThis->svga.f3DEnabled))
4974	{ /* likely */ }
4975	else
4976	{
4977	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
4978	break;
4979	}
4980
4981	vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
4982	}
4983	else
4984	# endif // VBOX_WITH_VMSVGA3D
4985	{
4986	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4987	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4988	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
4989	}
4990	}
4991
4992	/* Go to the next slot */
4993	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4994	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4995	if (offCurrentCmd >= offFifoMax)
4996	{
4997	offCurrentCmd -= offFifoMax - offFifoMin;
4998	Assert(offCurrentCmd >= offFifoMin);
4999	Assert(offCurrentCmd < offFifoMax);
5000	}
5001	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5002	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5003
5004	/*
5005	* Raise IRQ if required. Must enter the critical section here
5006	* before making final decisions here, otherwise cubebench and
5007	* others may end up waiting forever.
5008	*/
5009	if ( u32IrqStatus
5010	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5011	{
5012	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5013	AssertRC(rc2);
5014
5015	/* FIFO progress might trigger an interrupt. */
5016	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5017	{
5018	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5019	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5020	}
5021
5022	/* Unmasked IRQ pending? */
5023	if (pThis->svga.u32IrqMask & u32IrqStatus)
5024	{
5025	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5026	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5027	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5028	}
5029
5030	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5031	}
5032	}
5033
5034	/* If really done, clear the busy flag. */
5035	if (fDone)
5036	{
5037	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5038	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5039	}
5040	}
5041
5042	/*
5043	* Free the bounce buffer. (There are no returns above!)
5044	*/
5045	RTMemFree(pbBounceBuf);
5046
5047	return VINF_SUCCESS;
5048	}
5049
5050	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5051	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5052
5053	/**
5054	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5055	* Unblock the FIFO I/O thread so it can respond to a state change.}
5056	*/
5057	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5058	{
5059	RT_NOREF(pDevIns);
5060	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5061	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5062	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5063	}
5064
5065	/**
5066	* Enables or disables dirty page tracking for the framebuffer
5067	*
5068	* @param pDevIns The device instance.
5069	* @param pThis The shared VGA/VMSVGA instance data.
5070	* @param fTraces Enable/disable traces
5071	*/
5072	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5073	{
5074	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5075	&& !fTraces)
5076	{
5077	//Assert(pThis->svga.fTraces);
5078	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5079	return;
5080	}
5081
5082	pThis->svga.fTraces = fTraces;
5083	if (pThis->svga.fTraces)
5084	{
5085	unsigned cbFrameBuffer = pThis->vram_size;
5086
5087	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5088	/** @todo How does this work with screens? */
5089	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5090	{
5091	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5092	Assert(pThis->svga.cbScanline);
5093	# endif
5094	/* Hardware enabled; return real framebuffer size .*/
5095	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5096	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5097	}
5098
5099	if (!pThis->svga.fVRAMTracking)
5100	{
5101	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5102	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5103	pThis->svga.fVRAMTracking = true;
5104	}
5105	}
5106	else
5107	{
5108	if (pThis->svga.fVRAMTracking)
5109	{
5110	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5111	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5112	pThis->svga.fVRAMTracking = false;
5113	}
5114	}
5115	}
5116
5117	/**
5118	* @callback_method_impl{FNPCIIOREGIONMAP}
5119	*/
5120	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5121	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5122	{
5123	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5124	int rc;
5125	RT_NOREF(pPciDev);
5126	Assert(pPciDev == pDevIns->apPciDevs[0]);
5127
5128	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5129	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5130	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5131	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5132	, VERR_INTERNAL_ERROR);
5133	if (GCPhysAddress != NIL_RTGCPHYS)
5134	{
5135	/*
5136	* Mapping the FIFO RAM.
5137	*/
5138	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5139	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5140	AssertRC(rc);
5141
5142	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5143	if (RT_SUCCESS(rc))
5144	{
5145	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5146	# ifdef DEBUG_FIFO_ACCESS
5147	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5148	# else
5149	GCPhysAddress + PAGE_SIZE - 1,
5150	# endif
5151	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5152	"VMSVGA FIFO");
5153	AssertRC(rc);
5154	}
5155	# endif
5156	if (RT_SUCCESS(rc))
5157	{
5158	pThis->svga.GCPhysFIFO = GCPhysAddress;
5159	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5160	}
5161	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5162	}
5163	else
5164	{
5165	Assert(pThis->svga.GCPhysFIFO);
5166	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5167	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5168	AssertRC(rc);
5169	# else
5170	rc = VINF_SUCCESS;
5171	# endif
5172	pThis->svga.GCPhysFIFO = 0;
5173	}
5174	return rc;
5175	}
5176
5177	# ifdef VBOX_WITH_VMSVGA3D
5178
5179	/**
5180	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5181	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5182	*
5183	* @param pDevIns The device instance.
5184	* @param pThis The The shared VGA/VMSVGA instance data.
5185	* @param pThisCC The VGA/VMSVGA state for ring-3.
5186	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5187	* UINT32_MAX is used, all surfaces are processed.
5188	*/
5189	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5190	{
5191	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5192	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5193	}
5194
5195
5196	/**
5197	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5198	*/
5199	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5200	{
5201	/* There might be a specific surface ID at the start of the
5202	arguments, if not show all surfaces. */
5203	uint32_t sid = UINT32_MAX;
5204	if (pszArgs)
5205	pszArgs = RTStrStripL(pszArgs);
5206	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5207	sid = RTStrToUInt32(pszArgs);
5208
5209	/* Verbose or terse display, we default to verbose. */
5210	bool fVerbose = true;
5211	if (RTStrIStr(pszArgs, "terse"))
5212	fVerbose = false;
5213
5214	/* The size of the ascii art (x direction, y is 3/4 of x). */
5215	uint32_t cxAscii = 80;
5216	if (RTStrIStr(pszArgs, "gigantic"))
5217	cxAscii = 300;
5218	else if (RTStrIStr(pszArgs, "huge"))
5219	cxAscii = 180;
5220	else if (RTStrIStr(pszArgs, "big"))
5221	cxAscii = 132;
5222	else if (RTStrIStr(pszArgs, "normal"))
5223	cxAscii = 80;
5224	else if (RTStrIStr(pszArgs, "medium"))
5225	cxAscii = 64;
5226	else if (RTStrIStr(pszArgs, "small"))
5227	cxAscii = 48;
5228	else if (RTStrIStr(pszArgs, "tiny"))
5229	cxAscii = 24;
5230
5231	/* Y invert the image when producing the ASCII art. */
5232	bool fInvY = false;
5233	if (RTStrIStr(pszArgs, "invy"))
5234	fInvY = true;
5235
5236	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5237	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5238	}
5239
5240
5241	/**
5242	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5243	*/
5244	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5245	{
5246	/* pszArg = "sid[>dir]"
5247	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5248	*/
5249	char *pszBitmapPath = NULL;
5250	uint32_t sid = UINT32_MAX;
5251	if (pszArgs)
5252	pszArgs = RTStrStripL(pszArgs);
5253	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5254	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5255	if ( pszBitmapPath
5256	&& *pszBitmapPath == '>')
5257	++pszBitmapPath;
5258
5259	const bool fVerbose = true;
5260	const uint32_t cxAscii = 0; /* No ASCII */
5261	const bool fInvY = false; /* Do not invert. */
5262	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5263	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5264	}
5265
5266	/**
5267	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5268	*/
5269	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5270	{
5271	/* There might be a specific surface ID at the start of the
5272	arguments, if not show all contexts. */
5273	uint32_t sid = UINT32_MAX;
5274	if (pszArgs)
5275	pszArgs = RTStrStripL(pszArgs);
5276	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5277	sid = RTStrToUInt32(pszArgs);
5278
5279	/* Verbose or terse display, we default to verbose. */
5280	bool fVerbose = true;
5281	if (RTStrIStr(pszArgs, "terse"))
5282	fVerbose = false;
5283
5284	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5285	}
5286	# endif /* VBOX_WITH_VMSVGA3D */
5287
5288	/**
5289	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5290	*/
5291	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5292	{
5293	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5294	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5295	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5296	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5297	RT_NOREF(pszArgs);
5298
5299	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5300	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5301	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5302	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5303	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5304	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5305	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5306	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5307	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5308	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5309	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5310	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5311	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5312	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5313	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5314	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5315	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5316	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5317	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5318	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5319	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5320	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5321	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5322	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5323	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5324
5325	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5326	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5327	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5328	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5329
5330	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5331	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5332
5333	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5334	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5335
5336	# ifdef VBOX_WITH_VMSVGA3D
5337	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5338	# endif
5339	if (pThisCC->pDrv)
5340	{
5341	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5342	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5343	}
5344
5345	/* Dump screen information. */
5346	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5347	{
5348	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5349	if (pScreen)
5350	{
5351	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5352	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5353	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5354	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5355	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5356	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5357	{
5358	pHlp->pfnPrintf(pHlp, " (");
5359	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5360	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5361	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5362	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5363	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5364	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5365	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5366	pHlp->pfnPrintf(pHlp, " BLANKING");
5367	pHlp->pfnPrintf(pHlp, " )");
5368	}
5369	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5370	}
5371	}
5372
5373	}
5374
5375	/**
5376	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5377	*/
5378	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5379	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5380	{
5381	RT_NOREF(uPass);
5382
5383	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5384	int rc;
5385
5386	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5387	{
5388	uint32_t cScreens = 0;
5389	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5390	AssertRCReturn(rc, rc);
5391	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5392	("cScreens=%#x\n", cScreens),
5393	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5394
5395	for (uint32_t i = 0; i < cScreens; ++i)
5396	{
5397	VMSVGASCREENOBJECT screen;
5398	RT_ZERO(screen);
5399
5400	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5401	AssertLogRelRCReturn(rc, rc);
5402
5403	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5404	{
5405	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5406	*pScreen = screen;
5407	pScreen->fModified = true;
5408	}
5409	else
5410	{
5411	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5412	}
5413	}
5414	}
5415	else
5416	{
5417	/* Try to setup at least the first screen. */
5418	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5419	pScreen->fDefined = true;
5420	pScreen->fModified = true;
5421	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5422	pScreen->idScreen = 0;
5423	pScreen->xOrigin = 0;
5424	pScreen->yOrigin = 0;
5425	pScreen->offVRAM = pThis->svga.uScreenOffset;
5426	pScreen->cbPitch = pThis->svga.cbScanline;
5427	pScreen->cWidth = pThis->svga.uWidth;
5428	pScreen->cHeight = pThis->svga.uHeight;
5429	pScreen->cBpp = pThis->svga.uBpp;
5430	}
5431
5432	return VINF_SUCCESS;
5433	}
5434
5435	/**
5436	* @copydoc FNSSMDEVLOADEXEC
5437	*/
5438	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5439	{
5440	RT_NOREF(uPass);
5441	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5442	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5443	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5444	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5445	int rc;
5446
5447	/* Load our part of the VGAState */
5448	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5449	AssertRCReturn(rc, rc);
5450
5451	/* Load the VGA framebuffer. */
5452	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5453	uint32_t cbVgaFramebuffer = _32K;
5454	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5455	{
5456	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5457	AssertRCReturn(rc, rc);
5458	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5459	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5460	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5461	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5462	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5463	}
5464	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5465	AssertRCReturn(rc, rc);
5466	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5467	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5468	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5469	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5470
5471	/* Load the VMSVGA state. */
5472	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5473	AssertRCReturn(rc, rc);
5474
5475	/* Load the active cursor bitmaps. */
5476	if (pSVGAState->Cursor.fActive)
5477	{
5478	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5479	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5480
5481	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5482	AssertRCReturn(rc, rc);
5483	}
5484
5485	/* Load the GMR state. */
5486	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5487	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5488	{
5489	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5490	AssertRCReturn(rc, rc);
5491	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5492	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5493	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5494	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5495	}
5496
5497	if (pThis->svga.cGMR != cGMR)
5498	{
5499	/* Reallocate GMR array. */
5500	Assert(pSVGAState->paGMR != NULL);
5501	RTMemFree(pSVGAState->paGMR);
5502	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5503	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5504	pThis->svga.cGMR = cGMR;
5505	}
5506
5507	for (uint32_t i = 0; i < cGMR; ++i)
5508	{
5509	PGMR pGMR = &pSVGAState->paGMR[i];
5510
5511	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5512	AssertRCReturn(rc, rc);
5513
5514	if (pGMR->numDescriptors)
5515	{
5516	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5517	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5518	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5519
5520	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5521	{
5522	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5523	AssertRCReturn(rc, rc);
5524	}
5525	}
5526	}
5527
5528	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5529	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5530	# endif
5531
5532	VMSVGA_STATE_LOAD LoadState;
5533	LoadState.pSSM = pSSM;
5534	LoadState.uVersion = uVersion;
5535	LoadState.uPass = uPass;
5536	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5537	AssertLogRelRCReturn(rc, rc);
5538
5539	return VINF_SUCCESS;
5540	}
5541
5542	/**
5543	* Reinit the video mode after the state has been loaded.
5544	*/
5545	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5546	{
5547	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5548	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5549	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5550
5551	/* Set the active cursor. */
5552	if (pSVGAState->Cursor.fActive)
5553	{
5554	/* We don't store the alpha flag, but we can take a guess that if
5555	* the old register interface was used, the cursor was B&W.
5556	*/
5557	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5558
5559	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5560	true /fVisible/,
5561	fAlpha,
5562	pSVGAState->Cursor.xHotspot,
5563	pSVGAState->Cursor.yHotspot,
5564	pSVGAState->Cursor.width,
5565	pSVGAState->Cursor.height,
5566	pSVGAState->Cursor.pData);
5567	AssertRC(rc);
5568
5569	if (pThis->svga.uCursorOn)
5570	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5571	}
5572
5573	/* If the VRAM handler should not be registered, we have to explicitly
5574	* unregister it here!
5575	*/
5576	if (!pThis->svga.fVRAMTracking)
5577	{
5578	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5579	}
5580
5581	/* Let the FIFO thread deal with changing the mode. */
5582	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5583
5584	return VINF_SUCCESS;
5585	}
5586
5587	/**
5588	* Portion of SVGA state which must be saved in the FIFO thread.
5589	*/
5590	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5591	{
5592	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5593	int rc;
5594
5595	/* Save the screen objects. */
5596	/* Count defined screen object. */
5597	uint32_t cScreens = 0;
5598	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5599	{
5600	if (pSVGAState->aScreens[i].fDefined)
5601	++cScreens;
5602	}
5603
5604	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5605	AssertLogRelRCReturn(rc, rc);
5606
5607	for (uint32_t i = 0; i < cScreens; ++i)
5608	{
5609	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5610
5611	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5612	AssertLogRelRCReturn(rc, rc);
5613	}
5614	return VINF_SUCCESS;
5615	}
5616
5617	/**
5618	* @copydoc FNSSMDEVSAVEEXEC
5619	*/
5620	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5621	{
5622	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5623	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5624	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5625	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5626	int rc;
5627
5628	/* Save our part of the VGAState */
5629	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5630	AssertLogRelRCReturn(rc, rc);
5631
5632	/* Save the framebuffer backup. */
5633	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5634	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5635	AssertLogRelRCReturn(rc, rc);
5636
5637	/* Save the VMSVGA state. */
5638	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5639	AssertLogRelRCReturn(rc, rc);
5640
5641	/* Save the active cursor bitmaps. */
5642	if (pSVGAState->Cursor.fActive)
5643	{
5644	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5645	AssertLogRelRCReturn(rc, rc);
5646	}
5647
5648	/* Save the GMR state */
5649	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5650	AssertLogRelRCReturn(rc, rc);
5651	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5652	{
5653	PGMR pGMR = &pSVGAState->paGMR[i];
5654
5655	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5656	AssertLogRelRCReturn(rc, rc);
5657
5658	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5659	{
5660	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5661	AssertLogRelRCReturn(rc, rc);
5662	}
5663	}
5664
5665	/*
5666	* Must save some state (3D in particular) in the FIFO thread.
5667	*/
5668	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5669	AssertLogRelRCReturn(rc, rc);
5670
5671	return VINF_SUCCESS;
5672	}
5673
5674	/**
5675	* Destructor for PVMSVGAR3STATE structure.
5676	*
5677	* @param pThis The shared VGA/VMSVGA instance data.
5678	* @param pSVGAState Pointer to the structure. It is not deallocated.
5679	*/
5680	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5681	{
5682	# ifndef VMSVGA_USE_EMT_HALT_CODE
5683	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5684	{
5685	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5686	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5687	}
5688	# endif
5689
5690	if (pSVGAState->Cursor.fActive)
5691	{
5692	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5693	pSVGAState->Cursor.pData = NULL;
5694	pSVGAState->Cursor.fActive = false;
5695	}
5696
5697	if (pSVGAState->paGMR)
5698	{
5699	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5700	if (pSVGAState->paGMR[i].paDesc)
5701	RTMemFree(pSVGAState->paGMR[i].paDesc);
5702
5703	RTMemFree(pSVGAState->paGMR);
5704	pSVGAState->paGMR = NULL;
5705	}
5706
5707	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
5708	{
5709	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
5710	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
5711	{
5712	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
5713	pSVGAState->apCmdBufCtxs[i] = NULL;
5714	}
5715	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
5716	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
5717	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
5718	}
5719
5720	# ifdef VBOX_WITH_VMSVGA3D
5721	RTMemFree(pSVGAState->pFuncsMap);
5722	pSVGAState->pFuncsMap = NULL;
5723	RTMemFree(pSVGAState->pFuncsGBO);
5724	pSVGAState->pFuncsGBO = NULL;
5725	RTMemFree(pSVGAState->pFuncsDX);
5726	pSVGAState->pFuncsDX = NULL;
5727	# endif
5728	}
5729
5730	/**
5731	* Constructor for PVMSVGAR3STATE structure.
5732	*
5733	* @returns VBox status code.
5734	* @param pDevIns The PDM device instance.
5735	* @param pThis The shared VGA/VMSVGA instance data.
5736	* @param pSVGAState Pointer to the structure. It is already allocated.
5737	*/
5738	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5739	{
5740	int rc = VINF_SUCCESS;
5741
5742	pSVGAState->pDevIns = pDevIns;
5743
5744	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5745	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5746
5747	# ifndef VMSVGA_USE_EMT_HALT_CODE
5748	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5749	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5750	AssertRCReturn(rc, rc);
5751	# endif
5752
5753	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
5754	AssertRCReturn(rc, rc);
5755
5756	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
5757
5758	RTListInit(&pSVGAState->MOBLRUList);
5759	return rc;
5760	}
5761
5762	# ifdef VBOX_WITH_VMSVGA3D
5763	/**
5764	* Initializes the optional host 3D backend interfaces.
5765	*
5766	* @returns VBox status code.
5767	* @param pThisCC The VGA/VMSVGA state for ring-3.
5768	*/
5769	static int vmsvgaR3Init3dInterfaces(PVGASTATECC pThisCC)
5770	{
5771	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5772
5773	int rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_DX, NULL, sizeof(VMSVGA3DBACKENDFUNCSDX));
5774	if (RT_SUCCESS(rc))
5775	{
5776	pSVGAState->pFuncsDX = (VMSVGA3DBACKENDFUNCSDX *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSDX));
5777	AssertReturn(pSVGAState->pFuncsDX, VERR_NO_MEMORY);
5778
5779	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_DX, pSVGAState->pFuncsDX, sizeof(VMSVGA3DBACKENDFUNCSDX));
5780	}
5781
5782	rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_MAP, NULL, sizeof(VMSVGA3DBACKENDFUNCSMAP));
5783	if (RT_SUCCESS(rc))
5784	{
5785	pSVGAState->pFuncsMap = (VMSVGA3DBACKENDFUNCSMAP *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSMAP));
5786	AssertReturn(pSVGAState->pFuncsMap, VERR_NO_MEMORY);
5787
5788	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_MAP, pSVGAState->pFuncsMap, sizeof(VMSVGA3DBACKENDFUNCSMAP));
5789	}
5790
5791	rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_GBO, NULL, sizeof(VMSVGA3DBACKENDFUNCSGBO));
5792	if (RT_SUCCESS(rc))
5793	{
5794	pSVGAState->pFuncsGBO = (VMSVGA3DBACKENDFUNCSGBO *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSGBO));
5795	AssertReturn(pSVGAState->pFuncsGBO, VERR_NO_MEMORY);
5796
5797	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_GBO, pSVGAState->pFuncsGBO, sizeof(VMSVGA3DBACKENDFUNCSGBO));
5798	}
5799
5800	return VINF_SUCCESS;
5801	}
5802	# endif
5803
5804	/**
5805	* Initializes the host capabilities: device and FIFO.
5806	*
5807	* @returns VBox status code.
5808	* @param pThis The shared VGA/VMSVGA instance data.
5809	* @param pThisCC The VGA/VMSVGA state for ring-3.
5810	*/
5811	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5812	{
5813	/* Device caps. */
5814	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
5815	\| SVGA_CAP_GMR2
5816	\| SVGA_CAP_CURSOR
5817	\| SVGA_CAP_CURSOR_BYPASS
5818	\| SVGA_CAP_CURSOR_BYPASS_2
5819	\| SVGA_CAP_EXTENDED_FIFO
5820	\| SVGA_CAP_IRQMASK
5821	\| SVGA_CAP_PITCHLOCK
5822	\| SVGA_CAP_RECT_COPY
5823	\| SVGA_CAP_TRACES
5824	\| SVGA_CAP_SCREEN_OBJECT_2
5825	\| SVGA_CAP_ALPHA_CURSOR;
5826
5827	/* VGPU10 capabilities. */
5828	if (pThis->fVMSVGA10)
5829	{
5830	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
5831	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
5832	;
5833
5834	# ifdef VBOX_WITH_VMSVGA3D
5835	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5836	if (pSVGAState->pFuncsGBO)
5837	pThis->svga.u32DeviceCaps \|= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
5838	if (pSVGAState->pFuncsDX)
5839	pThis->svga.u32DeviceCaps \|= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
5840	# endif
5841	}
5842
5843	# ifdef VBOX_WITH_VMSVGA3D
5844	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
5845	# endif
5846
5847	/* Clear the FIFO. */
5848	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5849
5850	/* Setup FIFO capabilities. */
5851	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5852	\| SVGA_FIFO_CAP_PITCHLOCK
5853	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5854	\| SVGA_FIFO_CAP_RESERVE
5855	\| SVGA_FIFO_CAP_GMR2
5856	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5857	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5858
5859	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5860	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5861	}
5862
5863	# ifdef VBOX_WITH_VMSVGA3D
5864	/**
5865	* Initializes the host 3D capabilities and writes them to FIFO memory.
5866	*
5867	* @returns VBox status code.
5868	* @param pThis The shared VGA/VMSVGA instance data.
5869	* @param pThisCC The VGA/VMSVGA state for ring-3.
5870	*/
5871	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5872	{
5873	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
5874	bool const fSavedBuffering = RTLogRelSetBuffering(true);
5875
5876	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
5877	{
5878	uint32_t val = 0;
5879	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
5880	if (RT_SUCCESS(rc))
5881	pThis->svga.au32DevCaps[i] = val;
5882	else
5883	pThis->svga.au32DevCaps[i] = 0;
5884
5885	/* LogRel the capability value. */
5886	if (i < SVGA3D_DEVCAP_MAX)
5887	{
5888	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
5889	if (RT_SUCCESS(rc))
5890	{
5891	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
5892	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
5893	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
5894	{
5895	float const fval = (float )&val;
5896	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
5897	}
5898	else
5899	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
5900	}
5901	else
5902	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
5903	}
5904	else
5905	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
5906	}
5907
5908	RTLogRelSetBuffering(fSavedBuffering);
5909
5910	/* 3d hardware version; latest and greatest */
5911	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5912	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5913
5914	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
5915	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
5916	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
5917	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
5918	*/
5919	SVGA3dCapsRecord *pCaps;
5920	SVGA3dCapPair *pData;
5921
5922	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
5923	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5924	pData = (SVGA3dCapPair *)&pCaps->data;
5925
5926	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
5927	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
5928	{
5929	pData[i][0] = i;
5930	pData[i][1] = pThis->svga.au32DevCaps[i];
5931	}
5932	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5933	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5934
5935	/* Mark end of record array (a zero word). */
5936	pCaps->header.length = 0;
5937	}
5938
5939	# endif
5940
5941	/**
5942	* Resets the SVGA hardware state
5943	*
5944	* @returns VBox status code.
5945	* @param pDevIns The device instance.
5946	*/
5947	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
5948	{
5949	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5950	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5951	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5952
5953	/* Reset before init? */
5954	if (!pSVGAState)
5955	return VINF_SUCCESS;
5956
5957	Log(("vmsvgaR3Reset\n"));
5958
5959	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5960	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5961	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5962
5963	/* Reset other stuff. */
5964	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5965	RT_ZERO(pThis->svga.au32ScratchRegion);
5966
5967	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
5968
5969	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
5970	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
5971
5972	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5973
5974	# ifdef VBOX_WITH_VMSVGA3D
5975	/* Device capabilities depend on this. */
5976	if (pThis->svga.f3DEnabled)
5977	vmsvgaR3Init3dInterfaces(pThisCC);
5978	# endif
5979
5980	/* Initialize FIFO and register capabilities. */
5981	vmsvgaR3InitCaps(pThis, pThisCC);
5982
5983	# ifdef VBOX_WITH_VMSVGA3D
5984	if (pThis->svga.f3DEnabled)
5985	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
5986	# endif
5987
5988	/* VRAM tracking is enabled by default during bootup. */
5989	pThis->svga.fVRAMTracking = true;
5990	pThis->svga.fEnabled = false;
5991
5992	/* Invalidate current settings. */
5993	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5994	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5995	pThis->svga.uBpp = pThis->svga.uHostBpp;
5996	pThis->svga.cbScanline = 0;
5997	pThis->svga.u32PitchLock = 0;
5998
5999	return rc;
6000	}
6001
6002	/**
6003	* Cleans up the SVGA hardware state
6004	*
6005	* @returns VBox status code.
6006	* @param pDevIns The device instance.
6007	*/
6008	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6009	{
6010	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6011	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6012
6013	/*
6014	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6015	*/
6016	if (pThisCC->svga.pFIFOIOThread)
6017	{
6018	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6019	NULL /pvParam/, 30000 /ms/);
6020	AssertLogRelRC(rc);
6021
6022	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6023	AssertLogRelRC(rc);
6024	pThisCC->svga.pFIFOIOThread = NULL;
6025	}
6026
6027	/*
6028	* Destroy the special SVGA state.
6029	*/
6030	if (pThisCC->svga.pSvgaR3State)
6031	{
6032	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6033
6034	RTMemFree(pThisCC->svga.pSvgaR3State);
6035	pThisCC->svga.pSvgaR3State = NULL;
6036	}
6037
6038	/*
6039	* Free our resources residing in the VGA state.
6040	*/
6041	if (pThisCC->svga.pbVgaFrameBufferR3)
6042	{
6043	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6044	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6045	}
6046	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6047	{
6048	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6049	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6050	}
6051	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6052	{
6053	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6054	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6055	}
6056
6057	return VINF_SUCCESS;
6058	}
6059
6060	/**
6061	* Initialize the SVGA hardware state
6062	*
6063	* @returns VBox status code.
6064	* @param pDevIns The device instance.
6065	*/
6066	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6067	{
6068	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6069	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6070	PVMSVGAR3STATE pSVGAState;
6071	int rc;
6072
6073	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6074	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6075
6076	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6077
6078	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6079	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6080	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6081
6082	/* Create event semaphore. */
6083	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6084	AssertRCReturn(rc, rc);
6085
6086	/* Create event semaphore. */
6087	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6088	AssertRCReturn(rc, rc);
6089
6090	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6091	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6092
6093	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6094	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6095
6096	pSVGAState = pThisCC->svga.pSvgaR3State;
6097
6098	/* Register the write-protected GBO access handler type. */
6099	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6100	vmsvgaR3GboAccessHandler,
6101	NULL, NULL, NULL,
6102	NULL, NULL, NULL,
6103	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6104	AssertRCReturn(rc, rc);
6105
6106	# ifdef VBOX_WITH_VMSVGA3D
6107	if (pThis->svga.f3DEnabled)
6108	{
6109	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6110	if (RT_SUCCESS(rc))
6111	{
6112	/* Device capabilities depend on this. */
6113	vmsvgaR3Init3dInterfaces(pThisCC);
6114	}
6115	else
6116	{
6117	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6118	pThis->svga.f3DEnabled = false;
6119	}
6120	}
6121	# endif
6122
6123	/* Initialize FIFO and register capabilities. */
6124	vmsvgaR3InitCaps(pThis, pThisCC);
6125
6126	/* VRAM tracking is enabled by default during bootup. */
6127	pThis->svga.fVRAMTracking = true;
6128
6129	/* Set up the host bpp. This value is as a default for the programmable
6130	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6131	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6132	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6133	*
6134	* NB: The driver cBits value is currently constant for the lifetime of the
6135	* VM. If that changes, the host bpp logic might need revisiting.
6136	*/
6137	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6138
6139	/* Invalidate current settings. */
6140	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6141	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6142	pThis->svga.uBpp = pThis->svga.uHostBpp;
6143	pThis->svga.cbScanline = 0;
6144
6145	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
6146	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
6147	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6148	{
6149	pThis->svga.u32MaxWidth -= 256;
6150	pThis->svga.u32MaxHeight -= 256;
6151	}
6152	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6153
6154	# ifdef DEBUG_GMR_ACCESS
6155	/* Register the GMR access handler type. */
6156	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6157	vmsvgaR3GmrAccessHandler,
6158	NULL, NULL, NULL,
6159	NULL, NULL, NULL,
6160	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6161	AssertRCReturn(rc, rc);
6162	# endif
6163
6164	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6165	/* Register the FIFO access handler type. In addition to
6166	debugging FIFO access, this is also used to facilitate
6167	extended fifo thread sleeps. */
6168	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6169	# ifdef DEBUG_FIFO_ACCESS
6170	PGMPHYSHANDLERKIND_ALL,
6171	# else
6172	PGMPHYSHANDLERKIND_WRITE,
6173	# endif
6174	vmsvgaR3FifoAccessHandler,
6175	NULL, NULL, NULL,
6176	NULL, NULL, NULL,
6177	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6178	AssertRCReturn(rc, rc);
6179	# endif
6180
6181	/* Create the async IO thread. */
6182	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6183	RTTHREADTYPE_IO, "VMSVGA FIFO");
6184	if (RT_FAILURE(rc))
6185	{
6186	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6187	return rc;
6188	}
6189
6190	/*
6191	* Statistics.
6192	*/
6193	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6194	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6195	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6196	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6197	# ifdef VBOX_WITH_STATISTICS
6198	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6199	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6200	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6201	# endif
6202	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6203	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6204	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6205	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6206	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6207	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6208	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6209	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6210	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6211	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6212	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6213	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6214	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6215	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6216	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6217	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6218	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6219	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6220	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6221	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6222	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6223	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6224	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6225	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6226	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6227	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6228	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6229	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6230	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6231	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6232	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6233	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6234	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6235	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6236	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6237	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6238	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6239	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6240	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6241	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6242	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6243	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6244	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6245	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6246	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6247	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6248	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6249	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6250	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6251	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6252	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6253	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6254	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6255	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6256	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6257	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6258	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6259	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6260	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6261
6262	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6263	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6264	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6265	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6266	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6267	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6268	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6269	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6270	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6271	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6272	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6273	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6274	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6275	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6276	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6277	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6278	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6279	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6280	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6281	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6282	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6283	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6284	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6285	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6286	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6287	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6288	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6289	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6290	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6291	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6292	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6293	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6294	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6295	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6296	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6297	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6298	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6299	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6300	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6301	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6302
6303	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6304	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6305	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6306	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6307	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6308	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6309	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6310	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6311	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6312	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6313	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6314	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6315	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6316	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6317	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6318	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6319	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6320	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6321	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6322	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6323	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6324	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6325	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6326	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6327	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6328	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6329	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6330	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6331	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6332	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6333	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6334	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6335	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6336	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6337	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6338	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6339	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6340	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6341	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6342	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6343	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6344	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6345	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6346	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6347	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6348	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6349	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6350	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6351	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6352	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6353	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6354	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6355	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6356	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6357	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6358	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6359	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6360	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6361	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6362	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6363	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6364	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6365
6366	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6367	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6368	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6369	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6370	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6371	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6372	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6373	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6374	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6375	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6376	# endif
6377	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6378	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6379	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6380	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6381	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6382
6383	# undef REG_CNT
6384	# undef REG_PRF
6385
6386	/*
6387	* Info handlers.
6388	*/
6389	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6390	# ifdef VBOX_WITH_VMSVGA3D
6391	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6392	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6393	"VMSVGA 3d surface details. "
6394	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6395	vmsvgaR3Info3dSurface);
6396	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6397	"VMSVGA 3d surface details and bitmap: "
6398	"sid[>dir]",
6399	vmsvgaR3Info3dSurfaceBmp);
6400	# endif
6401
6402	return VINF_SUCCESS;
6403	}
6404
6405	/**
6406	* Power On notification.
6407	*
6408	* @returns VBox status code.
6409	* @param pDevIns The device instance data.
6410	*
6411	* @remarks Caller enters the device critical section.
6412	*/
6413	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6414	{
6415	# ifdef VBOX_WITH_VMSVGA3D
6416	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6417	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6418	if (pThis->svga.f3DEnabled)
6419	{
6420	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6421	if (RT_SUCCESS(rc))
6422	{
6423	/* Initialize FIFO 3D capabilities. */
6424	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6425	}
6426	else {
6427	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
6428	pThis->svga.f3DEnabled = false;
6429	}
6430	}
6431	# else /* !VBOX_WITH_VMSVGA3D */
6432	RT_NOREF(pDevIns);
6433	# endif /* !VBOX_WITH_VMSVGA3D */
6434	}
6435
6436	/**
6437	* Power Off notification.
6438	*
6439	* @param pDevIns The device instance data.
6440	*
6441	* @remarks Caller enters the device critical section.
6442	*/
6443	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6444	{
6445	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6446	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6447
6448	/*
6449	* Notify the FIFO thread.
6450	*/
6451	if (pThisCC->svga.pFIFOIOThread)
6452	{
6453	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6454	NULL /pvParam/, 30000 /ms/);
6455	AssertLogRelRC(rc);
6456	}
6457	}
6458
6459	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 88774

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