DevVGA-SVGA.cpp@ 86905

最後變更在這個檔案從86905是 86905,由 vboxsync 提交於 4 年前
Devices/Graphics: use new vmsvga headers, stubs for more commands. bugref:9830
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1	/* $Id: DevVGA-SVGA.cpp 86905 2020-11-17 23:36:12Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.alldomusa.eu.org. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
159	#ifdef VBOX_WITH_VMSVGA3D
160	# include "DevVGA-SVGA3d.h"
161	# ifdef RT_OS_DARWIN
162	# include "DevVGA-SVGA3d-cocoa.h"
163	# endif
164	# ifdef RT_OS_LINUX
165	# ifdef IN_RING3
166	# include "DevVGA-SVGA3d-glLdr.h"
167	# endif
168	# endif
169	#endif
170	#ifdef IN_RING3
171	#include "DevVGA-SVGA-internal.h"
172	#endif
173
174
175	/*********************************************************************************************************************************
176	* Defined Constants And Macros *
177	*********************************************************************************************************************************/
178	/**
179	* Macro for checking if a fixed FIFO register is valid according to the
180	* current FIFO configuration.
181	*
182	* @returns true / false.
183	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
184	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
185	*/
186	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
187
188
189	/*********************************************************************************************************************************
190	* Structures and Typedefs *
191	*********************************************************************************************************************************/
192
193
194	/*********************************************************************************************************************************
195	* Internal Functions *
196	*********************************************************************************************************************************/
197	#ifdef IN_RING3
198	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
199	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
200	# endif
201	# ifdef DEBUG_GMR_ACCESS
202	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
203	# endif
204	#endif
205
206
207	/*********************************************************************************************************************************
208	* Global Variables *
209	*********************************************************************************************************************************/
210	#ifdef IN_RING3
211
212	/**
213	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
214	*/
215	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
216	{
217	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
218	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
219	SSMFIELD_ENTRY_TERM()
220	};
221
222	/**
223	* SSM descriptor table for the GMR structure.
224	*/
225	static SSMFIELD const g_aGMRFields[] =
226	{
227	SSMFIELD_ENTRY( GMR, cMaxPages),
228	SSMFIELD_ENTRY( GMR, cbTotal),
229	SSMFIELD_ENTRY( GMR, numDescriptors),
230	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
231	SSMFIELD_ENTRY_TERM()
232	};
233
234	/**
235	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
236	*/
237	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
238	{
239	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
240	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
241	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
242	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
243	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
244	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
250	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
251	SSMFIELD_ENTRY_TERM()
252	};
253
254	/**
255	* SSM descriptor table for the VMSVGAR3STATE structure.
256	*/
257	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
258	{
259	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
260	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
261	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
262	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
263	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
264	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
265	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
267	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
269	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
270	#ifdef VMSVGA_USE_EMT_HALT_CODE
271	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
272	#else
273	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
274	#endif
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
276	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
278	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
280	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
338
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
343
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
351	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
353	# endif
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
358
359	SSMFIELD_ENTRY_TERM()
360	};
361
362	/**
363	* SSM descriptor table for the VGAState.svga structure.
364	*/
365	static SSMFIELD const g_aVGAStateSVGAFields[] =
366	{
367	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
368	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
369	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
370	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
371	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
372	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
373	SSMFIELD_ENTRY( VMSVGAState, fBusy),
374	SSMFIELD_ENTRY( VMSVGAState, fTraces),
375	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
376	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
377	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
378	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
379	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
380	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
381	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
382	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
383	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
387	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
388	SSMFIELD_ENTRY( VMSVGAState, uWidth),
389	SSMFIELD_ENTRY( VMSVGAState, uHeight),
390	SSMFIELD_ENTRY( VMSVGAState, uBpp),
391	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
392	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
393	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
394	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
395	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
396	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
397	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
398	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
399	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
400	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
401	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
405	SSMFIELD_ENTRY_TERM()
406	};
407	#endif /* IN_RING3 */
408
409
410	/*********************************************************************************************************************************
411	* Internal Functions *
412	*********************************************************************************************************************************/
413	#ifdef IN_RING3
414	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
415	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
416	uint32_t uVersion, uint32_t uPass);
417	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
418	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
419	#endif /* IN_RING3 */
420
421
422	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
423	#if defined(LOG_ENABLED)
424	/**
425	* Index register string name lookup
426	*
427	* @returns Index register string or "UNKNOWN"
428	* @param pThis The shared VGA/VMSVGA state.
429	* @param idxReg The index register.
430	*/
431	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
432	{
433	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
434	switch (idxReg)
435	{
436	SVGA_CASE_ID2STR(SVGA_REG_ID);
437	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
438	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
439	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
440	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
441	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
442	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
443	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
444	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
445	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
446	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
447	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
448	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
449	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
450	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
451	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
452	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
453
454	/* ID 0 implementation only had the above registers, then the palette */
455	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
456	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
457	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
458	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
459	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
460	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
461	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
462	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
463	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
464	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
465	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
466	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
467	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
468	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
469	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
470	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
471	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
472
473	/* Legacy multi-monitor support */
474	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
475	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
476	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
477	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
478	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
479	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
480	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
481
482	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
483	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
484	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
485	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
486
487	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
488	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
489	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
490	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
491	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
492	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
493	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
494	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
495	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
496	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
497	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
498	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
499	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
500	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
501	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
502	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
503	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
504	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
505	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
506	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
507	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
508	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
509	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
510	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
511	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
512	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
513	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
514	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
515	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
516	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
517	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
518	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
519	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
520
521	default:
522	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
523	return "SVGA_SCRATCH_BASE reg";
524	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
525	return "SVGA_PALETTE_BASE reg";
526	return "UNKNOWN";
527	}
528	}
529	#endif /* LOG_ENABLED */
530
531	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
532	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
533	{
534	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
535	switch (idxDevCap)
536	{
537	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
538	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
539	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
540	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
541	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
542	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
543	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
544	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
545	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
546	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
547	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
798
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
800
801	default:
802	break;
803	}
804	return "UNKNOWN";
805	}
806	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
807	#undef SVGA_CASE_ID2STR
808
809
810	#ifdef IN_RING3
811
812	/**
813	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
814	*/
815	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
816	{
817	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
818	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
819
820	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
821	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
822
823	/** @todo Test how it interacts with multiple screen objects. */
824	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
825	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
826	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
827
828	if (x < uWidth)
829	{
830	pThis->svga.viewport.x = x;
831	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
832	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
833	}
834	else
835	{
836	pThis->svga.viewport.x = uWidth;
837	pThis->svga.viewport.cx = 0;
838	pThis->svga.viewport.xRight = uWidth;
839	}
840	if (y < uHeight)
841	{
842	pThis->svga.viewport.y = y;
843	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
844	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
845	pThis->svga.viewport.yHighWC = uHeight - y;
846	}
847	else
848	{
849	pThis->svga.viewport.y = uHeight;
850	pThis->svga.viewport.cy = 0;
851	pThis->svga.viewport.yLowWC = 0;
852	pThis->svga.viewport.yHighWC = 0;
853	}
854
855	# ifdef VBOX_WITH_VMSVGA3D
856	/*
857	* Now inform the 3D backend.
858	*/
859	if (pThis->svga.f3DEnabled)
860	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
861	# else
862	RT_NOREF(OldViewport);
863	# endif
864	}
865
866
867	/**
868	* Updating screen information in API
869	*
870	* @param pThis The The shared VGA/VMSVGA instance data.
871	* @param pThisCC The VGA/VMSVGA state for ring-3.
872	*/
873	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
874	{
875	int rc;
876
877	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
878
879	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
880	{
881	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
882	if (!pScreen->fModified)
883	continue;
884
885	pScreen->fModified = false;
886
887	VBVAINFOVIEW view;
888	RT_ZERO(view);
889	view.u32ViewIndex = pScreen->idScreen;
890	// view.u32ViewOffset = 0;
891	view.u32ViewSize = pThis->vram_size;
892	view.u32MaxScreenSize = pThis->vram_size;
893
894	VBVAINFOSCREEN screen;
895	RT_ZERO(screen);
896	screen.u32ViewIndex = pScreen->idScreen;
897
898	if (pScreen->fDefined)
899	{
900	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
901	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
902	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
903	{
904	Assert(pThis->svga.fGFBRegisters);
905	continue;
906	}
907
908	screen.i32OriginX = pScreen->xOrigin;
909	screen.i32OriginY = pScreen->yOrigin;
910	screen.u32StartOffset = pScreen->offVRAM;
911	screen.u32LineSize = pScreen->cbPitch;
912	screen.u32Width = pScreen->cWidth;
913	screen.u32Height = pScreen->cHeight;
914	screen.u16BitsPerPixel = pScreen->cBpp;
915	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
916	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
917	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
918	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
919	}
920	else
921	{
922	/* Screen is destroyed. */
923	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
924	}
925
926	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
927	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
928	AssertRC(rc);
929	}
930	}
931
932
933	/**
934	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
935	*
936	* Used to update screen offsets (positions) since appearently vmwgfx fails to
937	* pass correct offsets thru FIFO.
938	*/
939	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
940	{
941	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
942	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
943	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
944
945	AssertReturnVoid(pSVGAState);
946
947	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
948	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
949	for (uint32_t i = 0; i < cPositions; ++i)
950	{
951	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
952	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
953	continue;
954
955	if (pSVGAState->aScreens[i].xOrigin == -1)
956	continue;
957	if (pSVGAState->aScreens[i].yOrigin == -1)
958	continue;
959
960	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
961	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
962	pSVGAState->aScreens[i].fModified = true;
963	}
964
965	vmsvgaR3VBVAResize(pThis, pThisCC);
966	}
967
968	#endif /* IN_RING3 */
969
970	/**
971	* Read port register
972	*
973	* @returns VBox status code.
974	* @param pDevIns The device instance.
975	* @param pThis The shared VGA/VMSVGA state.
976	* @param pu32 Where to store the read value
977	*/
978	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
979	{
980	#ifdef IN_RING3
981	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
982	#endif
983	int rc = VINF_SUCCESS;
984	*pu32 = 0;
985
986	/* Rough index register validation. */
987	uint32_t idxReg = pThis->svga.u32IndexReg;
988	#if !defined(IN_RING3) && defined(VBOX_STRICT)
989	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
990	VINF_IOM_R3_IOPORT_READ);
991	#else
992	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
993	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
994	VINF_SUCCESS);
995	#endif
996	RT_UNTRUSTED_VALIDATED_FENCE();
997
998	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
999	if ( idxReg >= SVGA_REG_ID_0_TOP
1000	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1001	{
1002	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1003	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1004	}
1005
1006	switch (idxReg)
1007	{
1008	case SVGA_REG_ID:
1009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1010	*pu32 = pThis->svga.u32SVGAId;
1011	break;
1012
1013	case SVGA_REG_ENABLE:
1014	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1015	*pu32 = pThis->svga.fEnabled;
1016	break;
1017
1018	case SVGA_REG_WIDTH:
1019	{
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1021	if ( pThis->svga.fEnabled
1022	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1023	*pu32 = pThis->svga.uWidth;
1024	else
1025	{
1026	#ifndef IN_RING3
1027	rc = VINF_IOM_R3_IOPORT_READ;
1028	#else
1029	*pu32 = pThisCC->pDrv->cx;
1030	#endif
1031	}
1032	break;
1033	}
1034
1035	case SVGA_REG_HEIGHT:
1036	{
1037	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1038	if ( pThis->svga.fEnabled
1039	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1040	*pu32 = pThis->svga.uHeight;
1041	else
1042	{
1043	#ifndef IN_RING3
1044	rc = VINF_IOM_R3_IOPORT_READ;
1045	#else
1046	*pu32 = pThisCC->pDrv->cy;
1047	#endif
1048	}
1049	break;
1050	}
1051
1052	case SVGA_REG_MAX_WIDTH:
1053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1054	*pu32 = pThis->svga.u32MaxWidth;
1055	break;
1056
1057	case SVGA_REG_MAX_HEIGHT:
1058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1059	*pu32 = pThis->svga.u32MaxHeight;
1060	break;
1061
1062	case SVGA_REG_DEPTH:
1063	/* This returns the color depth of the current mode. */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1065	switch (pThis->svga.uBpp)
1066	{
1067	case 15:
1068	case 16:
1069	case 24:
1070	*pu32 = pThis->svga.uBpp;
1071	break;
1072
1073	default:
1074	case 32:
1075	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1076	break;
1077	}
1078	break;
1079
1080	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1081	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1082	*pu32 = pThis->svga.uHostBpp;
1083	break;
1084
1085	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1086	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1087	*pu32 = pThis->svga.uBpp;
1088	break;
1089
1090	case SVGA_REG_PSEUDOCOLOR:
1091	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1092	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1093	break;
1094
1095	case SVGA_REG_RED_MASK:
1096	case SVGA_REG_GREEN_MASK:
1097	case SVGA_REG_BLUE_MASK:
1098	{
1099	uint32_t uBpp;
1100
1101	if (pThis->svga.fEnabled)
1102	uBpp = pThis->svga.uBpp;
1103	else
1104	uBpp = pThis->svga.uHostBpp;
1105
1106	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1107	switch (uBpp)
1108	{
1109	case 8:
1110	u32RedMask = 0x07;
1111	u32GreenMask = 0x38;
1112	u32BlueMask = 0xc0;
1113	break;
1114
1115	case 15:
1116	u32RedMask = 0x0000001f;
1117	u32GreenMask = 0x000003e0;
1118	u32BlueMask = 0x00007c00;
1119	break;
1120
1121	case 16:
1122	u32RedMask = 0x0000001f;
1123	u32GreenMask = 0x000007e0;
1124	u32BlueMask = 0x0000f800;
1125	break;
1126
1127	case 24:
1128	case 32:
1129	default:
1130	u32RedMask = 0x00ff0000;
1131	u32GreenMask = 0x0000ff00;
1132	u32BlueMask = 0x000000ff;
1133	break;
1134	}
1135	switch (idxReg)
1136	{
1137	case SVGA_REG_RED_MASK:
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1139	*pu32 = u32RedMask;
1140	break;
1141
1142	case SVGA_REG_GREEN_MASK:
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1144	*pu32 = u32GreenMask;
1145	break;
1146
1147	case SVGA_REG_BLUE_MASK:
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1149	*pu32 = u32BlueMask;
1150	break;
1151	}
1152	break;
1153	}
1154
1155	case SVGA_REG_BYTES_PER_LINE:
1156	{
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1158	if ( pThis->svga.fEnabled
1159	&& pThis->svga.cbScanline)
1160	*pu32 = pThis->svga.cbScanline;
1161	else
1162	{
1163	#ifndef IN_RING3
1164	rc = VINF_IOM_R3_IOPORT_READ;
1165	#else
1166	*pu32 = pThisCC->pDrv->cbScanline;
1167	#endif
1168	}
1169	break;
1170	}
1171
1172	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1174	*pu32 = pThis->vram_size;
1175	break;
1176
1177	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1179	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1180	*pu32 = pThis->GCPhysVRAM;
1181	break;
1182
1183	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1184	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1185	/* Always zero in our case. */
1186	*pu32 = 0;
1187	break;
1188
1189	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1190	{
1191	#ifndef IN_RING3
1192	rc = VINF_IOM_R3_IOPORT_READ;
1193	#else
1194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1195
1196	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1197	if ( pThis->svga.fEnabled
1198	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1199	{
1200	/* Hardware enabled; return real framebuffer size .*/
1201	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1202	}
1203	else
1204	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1205
1206	pu32 = RT_MIN(pThis->vram_size, pu32);
1207	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1208	#endif
1209	break;
1210	}
1211
1212	case SVGA_REG_CAPABILITIES:
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1214	*pu32 = pThis->svga.u32DeviceCaps;
1215	break;
1216
1217	case SVGA_REG_MEM_START: /* FIFO start */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1219	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1220	*pu32 = pThis->svga.GCPhysFIFO;
1221	break;
1222
1223	case SVGA_REG_MEM_SIZE: /* FIFO size */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1225	*pu32 = pThis->svga.cbFIFO;
1226	break;
1227
1228	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1230	*pu32 = pThis->svga.fConfigured;
1231	break;
1232
1233	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1234	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1235	*pu32 = 0;
1236	break;
1237
1238	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1239	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1240	if (pThis->svga.fBusy)
1241	{
1242	#ifndef IN_RING3
1243	/* Go to ring-3 and halt the CPU. */
1244	rc = VINF_IOM_R3_IOPORT_READ;
1245	RT_NOREF(pDevIns);
1246	break;
1247	#else
1248	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1249	/* The guest is basically doing a HLT via the device here, but with
1250	a special wake up condition on FIFO completion. */
1251	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1252	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1253	PVM pVM = PDMDevHlpGetVM(pDevIns);
1254	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1255	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1256	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1257	if (pThis->svga.fBusy)
1258	{
1259	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1260	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1261	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1262	}
1263	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1264	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1265	# else
1266
1267	/* Delay the EMT a bit so the FIFO and others can get some work done.
1268	This used to be a crude 50 ms sleep. The current code tries to be
1269	more efficient, but the consept is still very crude. */
1270	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1271	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1272	RTThreadYield();
1273	if (pThis->svga.fBusy)
1274	{
1275	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1276
1277	if (pThis->svga.fBusy && cRefs == 1)
1278	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1279	if (pThis->svga.fBusy)
1280	{
1281	/** @todo If this code is going to stay, we need to call into the halt/wait
1282	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1283	* suffer when the guest is polling on a busy FIFO. */
1284	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1285	if (cNsMaxWait >= RT_NS_100US)
1286	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1287	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1288	RT_MIN(cNsMaxWait, RT_NS_10MS));
1289	}
1290
1291	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1292	}
1293	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1294	# endif
1295	*pu32 = pThis->svga.fBusy != 0;
1296	#endif
1297	}
1298	else
1299	*pu32 = false;
1300	break;
1301
1302	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1304	*pu32 = pThis->svga.u32GuestId;
1305	break;
1306
1307	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1308	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1309	*pu32 = pThis->svga.cScratchRegion;
1310	break;
1311
1312	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1313	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1314	*pu32 = SVGA_FIFO_NUM_REGS;
1315	break;
1316
1317	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1318	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1319	*pu32 = pThis->svga.u32PitchLock;
1320	break;
1321
1322	case SVGA_REG_IRQMASK: /* Interrupt mask */
1323	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1324	*pu32 = pThis->svga.u32IrqMask;
1325	break;
1326
1327	/* See "Guest memory regions" below. */
1328	case SVGA_REG_GMR_ID:
1329	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1330	*pu32 = pThis->svga.u32CurrentGMRId;
1331	break;
1332
1333	case SVGA_REG_GMR_DESCRIPTOR:
1334	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1335	/* Write only */
1336	*pu32 = 0;
1337	break;
1338
1339	case SVGA_REG_GMR_MAX_IDS:
1340	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1341	*pu32 = pThis->svga.cGMR;
1342	break;
1343
1344	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1345	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1346	*pu32 = VMSVGA_MAX_GMR_PAGES;
1347	break;
1348
1349	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1350	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1351	*pu32 = pThis->svga.fTraces;
1352	break;
1353
1354	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1355	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1356	*pu32 = VMSVGA_MAX_GMR_PAGES;
1357	break;
1358
1359	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1360	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1361	*pu32 = VMSVGA_SURFACE_SIZE;
1362	break;
1363
1364	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1365	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1366	break;
1367
1368	/* Mouse cursor support. */
1369	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1370	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1371	*pu32 = pThis->svga.uCursorID;
1372	break;
1373
1374	case SVGA_REG_CURSOR_X:
1375	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1376	*pu32 = pThis->svga.uCursorX;
1377	break;
1378
1379	case SVGA_REG_CURSOR_Y:
1380	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1381	*pu32 = pThis->svga.uCursorY;
1382	break;
1383
1384	case SVGA_REG_CURSOR_ON:
1385	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1386	*pu32 = pThis->svga.uCursorOn;
1387	break;
1388
1389	/* Legacy multi-monitor support */
1390	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1391	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1392	*pu32 = 1;
1393	break;
1394
1395	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1396	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1397	*pu32 = 0;
1398	break;
1399
1400	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1401	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1402	*pu32 = 0;
1403	break;
1404
1405	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1406	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1407	*pu32 = 0;
1408	break;
1409
1410	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1411	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1412	*pu32 = 0;
1413	break;
1414
1415	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1416	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1417	*pu32 = pThis->svga.uWidth;
1418	break;
1419
1420	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1421	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1422	*pu32 = pThis->svga.uHeight;
1423	break;
1424
1425	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1426	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1427	/* We must return something sensible here otherwise the Linux driver
1428	will take a legacy code path without 3d support. This number also
1429	limits how many screens Linux guests will allow. */
1430	*pu32 = pThis->cMonitors;
1431	break;
1432
1433	/*
1434	* SVGA_CAP_GBOBJECTS+ registers.
1435	*/
1436	case SVGA_REG_COMMAND_LOW:
1437	/* Lower 32 bits of command buffer physical address. */
1438	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1439	*pu32 = pThis->svga.u32RegCommandLow;
1440	break;
1441
1442	case SVGA_REG_COMMAND_HIGH:
1443	/* Upper 32 bits of command buffer PA. */
1444	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1445	*pu32 = pThis->svga.u32RegCommandHigh;
1446	break;
1447
1448	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1449	/* Max primary (screen) memory. */
1450	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1451	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1452	break;
1453
1454	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1455	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1456	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1457	*pu32 = pThis->vram_size / 1024;
1458	break;
1459
1460	case SVGA_REG_DEV_CAP:
1461	/* Write dev cap index, read value */
1462	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1463	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1464	{
1465	RT_UNTRUSTED_VALIDATED_FENCE();
1466	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1467	}
1468	else
1469	*pu32 = 0;
1470	break;
1471
1472	case SVGA_REG_CMD_PREPEND_LOW:
1473	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1474	pu32 = 0; / Not supported. */
1475	break;
1476
1477	case SVGA_REG_CMD_PREPEND_HIGH:
1478	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1479	pu32 = 0; / Not supported. */
1480	break;
1481
1482	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1483	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1484	*pu32 = pThis->svga.u32MaxWidth;
1485	break;
1486
1487	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1488	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1489	*pu32 = pThis->svga.u32MaxHeight;
1490	break;
1491
1492	case SVGA_REG_MOB_MAX_SIZE:
1493	/* Essentially the max texture size */
1494	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1495	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1496	break;
1497
1498	default:
1499	{
1500	uint32_t offReg;
1501	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1502	{
1503	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1504	RT_UNTRUSTED_VALIDATED_FENCE();
1505	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1506	}
1507	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1508	{
1509	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1510	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1511	RT_UNTRUSTED_VALIDATED_FENCE();
1512	uint32_t u32 = pThis->last_palette[offReg / 3];
1513	switch (offReg % 3)
1514	{
1515	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1516	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1517	case 2: pu32 = u32 & 0xff; break; / blue */
1518	}
1519	}
1520	else
1521	{
1522	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1523	rc = VINF_IOM_R3_IOPORT_READ;
1524	#else
1525	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1526
1527	/* Do not assert. The guest might be reading all registers. */
1528	LogFunc(("Unknown reg=%#x\n", idxReg));
1529	#endif
1530	}
1531	break;
1532	}
1533	}
1534	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1535	return rc;
1536	}
1537
1538	#ifdef IN_RING3
1539	/**
1540	* Apply the current resolution settings to change the video mode.
1541	*
1542	* @returns VBox status code.
1543	* @param pThis The shared VGA state.
1544	* @param pThisCC The ring-3 VGA state.
1545	*/
1546	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1547	{
1548	/* Always do changemode on FIFO thread. */
1549	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1550
1551	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1552
1553	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1554
1555	if (pThis->svga.fGFBRegisters)
1556	{
1557	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1558	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1559	* deletes all screens other than screen #0, and redefines screen
1560	* #0 according to the specified mode. Drivers that use
1561	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1562	*/
1563
1564	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1565	pScreen->fDefined = true;
1566	pScreen->fModified = true;
1567	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1568	pScreen->idScreen = 0;
1569	pScreen->xOrigin = 0;
1570	pScreen->yOrigin = 0;
1571	pScreen->offVRAM = 0;
1572	pScreen->cbPitch = pThis->svga.cbScanline;
1573	pScreen->cWidth = pThis->svga.uWidth;
1574	pScreen->cHeight = pThis->svga.uHeight;
1575	pScreen->cBpp = pThis->svga.uBpp;
1576
1577	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1578	{
1579	/* Delete screen. */
1580	pScreen = &pSVGAState->aScreens[iScreen];
1581	if (pScreen->fDefined)
1582	{
1583	pScreen->fModified = true;
1584	pScreen->fDefined = false;
1585	}
1586	}
1587	}
1588	else
1589	{
1590	/* "If Screen Objects are supported, they can be used to fully
1591	* replace the functionality provided by the framebuffer registers
1592	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1593	*/
1594	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1595	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1596	pThis->svga.uBpp = pThis->svga.uHostBpp;
1597	}
1598
1599	vmsvgaR3VBVAResize(pThis, pThisCC);
1600
1601	/* Last stuff. For the VGA device screenshot. */
1602	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1603	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1604	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1605	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1606	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1607
1608	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1609	if ( pThis->svga.viewport.cx == 0
1610	&& pThis->svga.viewport.cy == 0)
1611	{
1612	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1613	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1614	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1615	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1616	pThis->svga.viewport.yLowWC = 0;
1617	}
1618
1619	return VINF_SUCCESS;
1620	}
1621
1622	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1623	{
1624	VBVACMDHDR cmd;
1625	cmd.x = (int16_t)(pScreen->xOrigin + x);
1626	cmd.y = (int16_t)(pScreen->yOrigin + y);
1627	cmd.w = (uint16_t)w;
1628	cmd.h = (uint16_t)h;
1629
1630	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1631	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1632	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1633	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1634
1635	return VINF_SUCCESS;
1636	}
1637
1638	#endif /* IN_RING3 */
1639	#if defined(IN_RING0) \|\| defined(IN_RING3)
1640
1641	/**
1642	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1643	*
1644	* @param pThis The shared VGA/VMSVGA instance data.
1645	* @param pThisCC The VGA/VMSVGA state for the current context.
1646	* @param fState The busy state.
1647	*/
1648	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1649	{
1650	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1651
1652	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1653	{
1654	/* Race / unfortunately scheduling. Highly unlikly. */
1655	uint32_t cLoops = 64;
1656	do
1657	{
1658	ASMNopPause();
1659	fState = (pThis->svga.fBusy != 0);
1660	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1661	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1662	}
1663	}
1664
1665
1666	/**
1667	* Update the scanline pitch in response to the guest changing mode
1668	* width/bpp.
1669	*
1670	* @param pThis The shared VGA/VMSVGA state.
1671	* @param pThisCC The VGA/VMSVGA state for the current context.
1672	*/
1673	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1674	{
1675	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1676	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1677	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1678	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1679
1680	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1681	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1682	* location but it has a different meaning.
1683	*/
1684	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1685	uFifoPitchLock = 0;
1686
1687	/* Sanitize values. */
1688	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1689	uFifoPitchLock = 0;
1690	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1691	uRegPitchLock = 0;
1692
1693	/* Prefer the register value to the FIFO value.*/
1694	if (uRegPitchLock)
1695	pThis->svga.cbScanline = uRegPitchLock;
1696	else if (uFifoPitchLock)
1697	pThis->svga.cbScanline = uFifoPitchLock;
1698	else
1699	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1700
1701	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1702	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1703	}
1704
1705	#endif /* IN_RING0 \|\| IN_RING3 */
1706
1707	#ifdef IN_RING3
1708
1709	/**
1710	* Sends cursor position and visibility information from legacy
1711	* SVGA registers to the front-end.
1712	*/
1713	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1714	{
1715	/*
1716	* Writing the X/Y/ID registers does not trigger changes; only writing the
1717	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1718	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1719	* register if they don't have to.
1720	*/
1721	uint32_t x, y, idScreen;
1722	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1723
1724	x = pThis->svga.uCursorX;
1725	y = pThis->svga.uCursorY;
1726	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1727
1728	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1729	* were extended as follows:
1730	*
1731	* SVGA_CURSOR_ON_HIDE 0
1732	* SVGA_CURSOR_ON_SHOW 1
1733	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1734	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1735	*
1736	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1737	* distinguish between the non-zero values but still remember them.
1738	*/
1739	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1740	{
1741	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1742	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1743	}
1744	pThis->svga.uCursorOn = uCursorOn;
1745	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1746	}
1747
1748	#endif /* IN_RING3 */
1749
1750
1751	/**
1752	* Write port register
1753	*
1754	* @returns Strict VBox status code.
1755	* @param pDevIns The device instance.
1756	* @param pThis The shared VGA/VMSVGA state.
1757	* @param pThisCC The VGA/VMSVGA state for the current context.
1758	* @param u32 Value to write
1759	*/
1760	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1761	{
1762	#ifdef IN_RING3
1763	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1764	#endif
1765	VBOXSTRICTRC rc = VINF_SUCCESS;
1766	RT_NOREF(pThisCC);
1767
1768	/* Rough index register validation. */
1769	uint32_t idxReg = pThis->svga.u32IndexReg;
1770	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1771	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1772	VINF_IOM_R3_IOPORT_WRITE);
1773	#else
1774	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1775	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1776	VINF_SUCCESS);
1777	#endif
1778	RT_UNTRUSTED_VALIDATED_FENCE();
1779
1780	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1781	if ( idxReg >= SVGA_REG_ID_0_TOP
1782	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1783	{
1784	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1785	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1786	}
1787	#ifdef LOG_ENABLED
1788	if (idxReg != SVGA_REG_DEV_CAP)
1789	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1790	else
1791	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1792	#endif
1793	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1794	switch (idxReg)
1795	{
1796	case SVGA_REG_WIDTH:
1797	case SVGA_REG_HEIGHT:
1798	case SVGA_REG_PITCHLOCK:
1799	case SVGA_REG_BITS_PER_PIXEL:
1800	pThis->svga.fGFBRegisters = true;
1801	break;
1802	default:
1803	break;
1804	}
1805
1806	switch (idxReg)
1807	{
1808	case SVGA_REG_ID:
1809	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1810	if ( u32 == SVGA_ID_0
1811	\|\| u32 == SVGA_ID_1
1812	\|\| u32 == SVGA_ID_2)
1813	pThis->svga.u32SVGAId = u32;
1814	else
1815	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1816	break;
1817
1818	case SVGA_REG_ENABLE:
1819	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1820	#ifdef IN_RING3
1821	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1822	&& pThis->svga.fEnabled == false)
1823	{
1824	/* Make a backup copy of the first 512kb in order to save font data etc. */
1825	/** @todo should probably swap here, rather than copy + zero */
1826	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1827	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1828	}
1829
1830	pThis->svga.fEnabled = u32;
1831	if (pThis->svga.fEnabled)
1832	{
1833	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1834	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1835	{
1836	/* Keep the current mode. */
1837	pThis->svga.uWidth = pThisCC->pDrv->cx;
1838	pThis->svga.uHeight = pThisCC->pDrv->cy;
1839	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1840	}
1841
1842	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1843	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1844	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1845	# ifdef LOG_ENABLED
1846	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1847	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1848	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1849	# endif
1850
1851	/* Disable or enable dirty page tracking according to the current fTraces value. */
1852	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1853
1854	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1855	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1856	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1857
1858	/* Make the cursor visible again as needed. */
1859	if (pSVGAState->Cursor.fActive)
1860	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1861	}
1862	else
1863	{
1864	/* Make sure the cursor is off. */
1865	if (pSVGAState->Cursor.fActive)
1866	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1867
1868	/* Restore the text mode backup. */
1869	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1870
1871	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1872
1873	/* Enable dirty page tracking again when going into legacy mode. */
1874	vmsvgaR3SetTraces(pDevIns, pThis, true);
1875
1876	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1877	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1878	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1879
1880	/* Clear the pitch lock. */
1881	pThis->svga.u32PitchLock = 0;
1882	}
1883	#else /* !IN_RING3 */
1884	rc = VINF_IOM_R3_IOPORT_WRITE;
1885	#endif /* !IN_RING3 */
1886	break;
1887
1888	case SVGA_REG_WIDTH:
1889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1890	if (pThis->svga.uWidth != u32)
1891	{
1892	#if defined(IN_RING3) \|\| defined(IN_RING0)
1893	pThis->svga.uWidth = u32;
1894	vmsvgaHCUpdatePitch(pThis, pThisCC);
1895	if (pThis->svga.fEnabled)
1896	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1897	#else
1898	rc = VINF_IOM_R3_IOPORT_WRITE;
1899	#endif
1900	}
1901	/* else: nop */
1902	break;
1903
1904	case SVGA_REG_HEIGHT:
1905	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1906	if (pThis->svga.uHeight != u32)
1907	{
1908	pThis->svga.uHeight = u32;
1909	if (pThis->svga.fEnabled)
1910	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1911	}
1912	/* else: nop */
1913	break;
1914
1915	case SVGA_REG_DEPTH:
1916	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1917	/** @todo read-only?? */
1918	break;
1919
1920	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1921	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1922	if (pThis->svga.uBpp != u32)
1923	{
1924	#if defined(IN_RING3) \|\| defined(IN_RING0)
1925	pThis->svga.uBpp = u32;
1926	vmsvgaHCUpdatePitch(pThis, pThisCC);
1927	if (pThis->svga.fEnabled)
1928	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1929	#else
1930	rc = VINF_IOM_R3_IOPORT_WRITE;
1931	#endif
1932	}
1933	/* else: nop */
1934	break;
1935
1936	case SVGA_REG_PSEUDOCOLOR:
1937	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1938	break;
1939
1940	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1941	#ifdef IN_RING3
1942	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1943	pThis->svga.fConfigured = u32;
1944	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1945	if (!pThis->svga.fConfigured)
1946	pThis->svga.fTraces = true;
1947	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1948	#else
1949	rc = VINF_IOM_R3_IOPORT_WRITE;
1950	#endif
1951	break;
1952
1953	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1955	if ( pThis->svga.fEnabled
1956	&& pThis->svga.fConfigured)
1957	{
1958	#if defined(IN_RING3) \|\| defined(IN_RING0)
1959	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1960	/*
1961	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1962	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1963	*/
1964	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1965	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1966	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1967
1968	/* Kick the FIFO thread to start processing commands again. */
1969	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1970	#else
1971	rc = VINF_IOM_R3_IOPORT_WRITE;
1972	#endif
1973	}
1974	/* else nothing to do. */
1975	else
1976	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1977
1978	break;
1979
1980	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1982	break;
1983
1984	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1985	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1986	pThis->svga.u32GuestId = u32;
1987	break;
1988
1989	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1990	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1991	pThis->svga.u32PitchLock = u32;
1992	/* Should this also update the FIFO pitch lock? Unclear. */
1993	break;
1994
1995	case SVGA_REG_IRQMASK: /* Interrupt mask */
1996	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1997	pThis->svga.u32IrqMask = u32;
1998
1999	/* Irq pending after the above change? */
2000	if (pThis->svga.u32IrqStatus & u32)
2001	{
2002	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2003	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2004	}
2005	else
2006	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2007	break;
2008
2009	/* Mouse cursor support */
2010	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2011	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2012	pThis->svga.uCursorID = u32;
2013	break;
2014
2015	case SVGA_REG_CURSOR_X:
2016	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2017	pThis->svga.uCursorX = u32;
2018	break;
2019
2020	case SVGA_REG_CURSOR_Y:
2021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2022	pThis->svga.uCursorY = u32;
2023	break;
2024
2025	case SVGA_REG_CURSOR_ON:
2026	#ifdef IN_RING3
2027	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2028	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2029	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2030	#else
2031	rc = VINF_IOM_R3_IOPORT_WRITE;
2032	#endif
2033	break;
2034
2035	/* Legacy multi-monitor support */
2036	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2037	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2038	break;
2039	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2040	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2041	break;
2042	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2044	break;
2045	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2046	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2047	break;
2048	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2050	break;
2051	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2052	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2053	break;
2054	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2056	break;
2057	#ifdef VBOX_WITH_VMSVGA3D
2058	/* See "Guest memory regions" below. */
2059	case SVGA_REG_GMR_ID:
2060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2061	pThis->svga.u32CurrentGMRId = u32;
2062	break;
2063
2064	case SVGA_REG_GMR_DESCRIPTOR:
2065	# ifndef IN_RING3
2066	rc = VINF_IOM_R3_IOPORT_WRITE;
2067	break;
2068	# else /* IN_RING3 */
2069	{
2070	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2071
2072	/* Validate current GMR id. */
2073	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2074	AssertBreak(idGMR < pThis->svga.cGMR);
2075	RT_UNTRUSTED_VALIDATED_FENCE();
2076
2077	/* Free the old GMR if present. */
2078	vmsvgaR3GmrFree(pThisCC, idGMR);
2079
2080	/* Just undefine the GMR? */
2081	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2082	if (GCPhys == 0)
2083	{
2084	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2085	break;
2086	}
2087
2088
2089	/* Never cross a page boundary automatically. */
2090	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2091	uint32_t cPagesTotal = 0;
2092	uint32_t iDesc = 0;
2093	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2094	uint32_t cLoops = 0;
2095	RTGCPHYS GCPhysBase = GCPhys;
2096	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2097	{
2098	/* Read descriptor. */
2099	SVGAGuestMemDescriptor desc;
2100	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2101	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2102
2103	if (desc.numPages != 0)
2104	{
2105	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2106	cPagesTotal += desc.numPages;
2107	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2108
2109	if ((iDesc & 15) == 0)
2110	{
2111	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2112	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2113	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2114	}
2115
2116	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2117	paDescs[iDesc++].numPages = desc.numPages;
2118
2119	/* Continue with the next descriptor. */
2120	GCPhys += sizeof(desc);
2121	}
2122	else if (desc.ppn == 0)
2123	break; /* terminator */
2124	else /* Pointer to the next physical page of descriptors. */
2125	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2126
2127	cLoops++;
2128	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2129	}
2130
2131	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2132	if (RT_SUCCESS(rc))
2133	{
2134	/* Commit the GMR. */
2135	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2136	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2137	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2138	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2139	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2140	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2141	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2142	}
2143	else
2144	{
2145	RTMemFree(paDescs);
2146	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2147	}
2148	break;
2149	}
2150	# endif /* IN_RING3 */
2151	#endif // VBOX_WITH_VMSVGA3D
2152
2153	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2155	if (pThis->svga.fTraces == u32)
2156	break; /* nothing to do */
2157
2158	#ifdef IN_RING3
2159	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2160	#else
2161	rc = VINF_IOM_R3_IOPORT_WRITE;
2162	#endif
2163	break;
2164
2165	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2166	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2167	break;
2168
2169	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2171	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2172	break;
2173
2174	/*
2175	* SVGA_CAP_GBOBJECTS+ registers.
2176	*/
2177	case SVGA_REG_COMMAND_LOW:
2178	{
2179	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2180	#ifdef IN_RING3
2181	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2182	pThis->svga.u32RegCommandLow = u32;
2183
2184	/* "lower 6 bits are used for the SVGACBContext" */
2185	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2186	GCPhysCB <<= 32;
2187	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2188	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2189	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2190	#else
2191	rc = VINF_IOM_R3_IOPORT_WRITE;
2192	#endif
2193	break;
2194	}
2195
2196	case SVGA_REG_COMMAND_HIGH:
2197	/* Upper 32 bits of command buffer PA. */
2198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2199	pThis->svga.u32RegCommandHigh = u32;
2200	break;
2201
2202	case SVGA_REG_DEV_CAP:
2203	/* Write dev cap index, read value */
2204	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2205	pThis->svga.u32DevCapIndex = u32;
2206	break;
2207
2208	case SVGA_REG_CMD_PREPEND_LOW:
2209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2210	/* Not supported. */
2211	break;
2212
2213	case SVGA_REG_CMD_PREPEND_HIGH:
2214	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2215	/* Not supported. */
2216	break;
2217
2218	case SVGA_REG_FB_START:
2219	case SVGA_REG_MEM_START:
2220	case SVGA_REG_HOST_BITS_PER_PIXEL:
2221	case SVGA_REG_MAX_WIDTH:
2222	case SVGA_REG_MAX_HEIGHT:
2223	case SVGA_REG_VRAM_SIZE:
2224	case SVGA_REG_FB_SIZE:
2225	case SVGA_REG_CAPABILITIES:
2226	case SVGA_REG_MEM_SIZE:
2227	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2228	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2229	case SVGA_REG_BYTES_PER_LINE:
2230	case SVGA_REG_FB_OFFSET:
2231	case SVGA_REG_RED_MASK:
2232	case SVGA_REG_GREEN_MASK:
2233	case SVGA_REG_BLUE_MASK:
2234	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2235	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2236	case SVGA_REG_GMR_MAX_IDS:
2237	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2238	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2239	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2240	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2241	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2242	case SVGA_REG_MOB_MAX_SIZE:
2243	/* Read only - ignore. */
2244	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2245	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2246	break;
2247
2248	default:
2249	{
2250	uint32_t offReg;
2251	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2252	{
2253	RT_UNTRUSTED_VALIDATED_FENCE();
2254	pThis->svga.au32ScratchRegion[offReg] = u32;
2255	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2256	}
2257	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2258	{
2259	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2260	Btw, see rgb_to_pixel32. */
2261	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2262	u32 &= 0xff;
2263	RT_UNTRUSTED_VALIDATED_FENCE();
2264	uint32_t uRgb = pThis->last_palette[offReg / 3];
2265	switch (offReg % 3)
2266	{
2267	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2268	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2269	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2270	}
2271	pThis->last_palette[offReg / 3] = uRgb;
2272	}
2273	else
2274	{
2275	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2276	rc = VINF_IOM_R3_IOPORT_WRITE;
2277	#else
2278	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2279	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2280	#endif
2281	}
2282	break;
2283	}
2284	}
2285	return rc;
2286	}
2287
2288	/**
2289	* @callback_method_impl{FNIOMIOPORTNEWIN}
2290	*/
2291	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2292	{
2293	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2294	RT_NOREF_PV(pvUser);
2295
2296	/* Only dword accesses. */
2297	if (cb == 4)
2298	{
2299	switch (offPort)
2300	{
2301	case SVGA_INDEX_PORT:
2302	*pu32 = pThis->svga.u32IndexReg;
2303	break;
2304
2305	case SVGA_VALUE_PORT:
2306	return vmsvgaReadPort(pDevIns, pThis, pu32);
2307
2308	case SVGA_BIOS_PORT:
2309	Log(("Ignoring BIOS port read\n"));
2310	*pu32 = 0;
2311	break;
2312
2313	case SVGA_IRQSTATUS_PORT:
2314	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2315	*pu32 = pThis->svga.u32IrqStatus;
2316	break;
2317
2318	default:
2319	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2320	*pu32 = UINT32_MAX;
2321	break;
2322	}
2323	}
2324	else
2325	{
2326	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2327	*pu32 = UINT32_MAX;
2328	}
2329	return VINF_SUCCESS;
2330	}
2331
2332	/**
2333	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2334	*/
2335	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2336	{
2337	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2338	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2339	RT_NOREF_PV(pvUser);
2340
2341	/* Only dword accesses. */
2342	if (cb == 4)
2343	switch (offPort)
2344	{
2345	case SVGA_INDEX_PORT:
2346	pThis->svga.u32IndexReg = u32;
2347	break;
2348
2349	case SVGA_VALUE_PORT:
2350	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2351
2352	case SVGA_BIOS_PORT:
2353	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2354	break;
2355
2356	case SVGA_IRQSTATUS_PORT:
2357	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2358	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2359	/* Clear the irq in case all events have been cleared. */
2360	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2361	{
2362	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2363	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2364	}
2365	break;
2366
2367	default:
2368	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2369	break;
2370	}
2371	else
2372	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2373
2374	return VINF_SUCCESS;
2375	}
2376
2377	#ifdef IN_RING3
2378
2379	# ifdef DEBUG_FIFO_ACCESS
2380	/**
2381	* Handle FIFO memory access.
2382	* @returns VBox status code.
2383	* @param pVM VM handle.
2384	* @param pThis The shared VGA/VMSVGA instance data.
2385	* @param GCPhys The access physical address.
2386	* @param fWriteAccess Read or write access
2387	*/
2388	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2389	{
2390	RT_NOREF(pVM);
2391	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2392	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2393
2394	switch (GCPhysOffset >> 2)
2395	{
2396	case SVGA_FIFO_MIN:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_MAX:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_NEXT_CMD:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_STOP:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	case SVGA_FIFO_CAPABILITIES:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	case SVGA_FIFO_FLAGS:
2412	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2413	break;
2414	case SVGA_FIFO_FENCE:
2415	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2416	break;
2417	case SVGA_FIFO_3D_HWVERSION:
2418	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2419	break;
2420	case SVGA_FIFO_PITCHLOCK:
2421	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2422	break;
2423	case SVGA_FIFO_CURSOR_ON:
2424	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2425	break;
2426	case SVGA_FIFO_CURSOR_X:
2427	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2428	break;
2429	case SVGA_FIFO_CURSOR_Y:
2430	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2431	break;
2432	case SVGA_FIFO_CURSOR_COUNT:
2433	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2434	break;
2435	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	case SVGA_FIFO_RESERVED:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	case SVGA_FIFO_CURSOR_SCREEN_ID:
2442	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2443	break;
2444	case SVGA_FIFO_DEAD:
2445	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2446	break;
2447	case SVGA_FIFO_3D_HWVERSION_REVISED:
2448	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2449	break;
2450	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2451	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2452	break;
2453	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2454	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2455	break;
2456	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2457	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2458	break;
2459	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2460	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2461	break;
2462	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2463	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2464	break;
2465	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2466	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2467	break;
2468	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2469	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2470	break;
2471	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2472	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2473	break;
2474	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2475	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2476	break;
2477	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2478	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2479	break;
2480	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2481	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2482	break;
2483	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2484	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2485	break;
2486	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2487	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2488	break;
2489	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2490	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2491	break;
2492	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2493	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2494	break;
2495	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2496	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2497	break;
2498	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2499	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2500	break;
2501	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2502	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2503	break;
2504	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2505	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2506	break;
2507	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2508	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2509	break;
2510	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2511	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2512	break;
2513	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2514	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2515	break;
2516	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2517	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2518	break;
2519	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2520	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2521	break;
2522	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2523	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2524	break;
2525	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2526	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2527	break;
2528	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2529	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2530	break;
2531	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2532	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2533	break;
2534	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2535	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2536	break;
2537	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2538	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2539	break;
2540	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2541	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2542	break;
2543	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2544	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2545	break;
2546	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2547	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2548	break;
2549	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2550	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2551	break;
2552	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2553	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2554	break;
2555	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2556	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2557	break;
2558	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2559	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2560	break;
2561	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2562	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2563	break;
2564	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2565	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2566	break;
2567	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2568	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2569	break;
2570	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2571	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2572	break;
2573	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2574	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2575	break;
2576	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2577	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2578	break;
2579	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2580	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2581	break;
2582	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2583	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2584	break;
2585	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2586	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2587	break;
2588	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2589	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2590	break;
2591	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2592	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2593	break;
2594	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2595	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2596	break;
2597	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2598	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2599	break;
2600	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2601	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2602	break;
2603	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2604	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2605	break;
2606	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2607	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2608	break;
2609	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2610	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2611	break;
2612	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2613	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2614	break;
2615	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2616	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2617	break;
2618	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2619	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2620	break;
2621	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2622	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2623	break;
2624	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2625	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2626	break;
2627	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2628	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2629	break;
2630	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2631	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2632	break;
2633	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2634	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2635	break;
2636	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2637	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2638	break;
2639	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2640	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2641	break;
2642	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2643	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2644	break;
2645	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2646	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2647	break;
2648	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2649	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2650	break;
2651	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2652	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2653	break;
2654	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2655	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2656	break;
2657	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2658	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2659	break;
2660	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2661	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2662	break;
2663	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2664	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2665	break;
2666	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2667	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2668	break;
2669	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2670	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2671	break;
2672	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2673	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2674	break;
2675	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2676	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2677	break;
2678	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2679	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2680	break;
2681	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2682	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2683	break;
2684	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2685	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2686	break;
2687	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2688	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2689	break;
2690	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2691	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2692	break;
2693	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2694	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2695	break;
2696	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2697	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2698	break;
2699	case SVGA_FIFO_3D_CAPS_LAST:
2700	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2701	break;
2702	case SVGA_FIFO_GUEST_3D_HWVERSION:
2703	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2704	break;
2705	case SVGA_FIFO_FENCE_GOAL:
2706	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2707	break;
2708	case SVGA_FIFO_BUSY:
2709	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2710	break;
2711	default:
2712	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2713	break;
2714	}
2715
2716	return VINF_EM_RAW_EMULATE_INSTR;
2717	}
2718	# endif /* DEBUG_FIFO_ACCESS */
2719
2720	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2721	/**
2722	* HC access handler for the FIFO.
2723	*
2724	* @returns VINF_SUCCESS if the handler have carried out the operation.
2725	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2726	* @param pVM VM Handle.
2727	* @param pVCpu The cross context CPU structure for the calling EMT.
2728	* @param GCPhys The physical address the guest is writing to.
2729	* @param pvPhys The HC mapping of that address.
2730	* @param pvBuf What the guest is reading/writing.
2731	* @param cbBuf How much it's reading/writing.
2732	* @param enmAccessType The access type.
2733	* @param enmOrigin Who is making the access.
2734	* @param pvUser User argument.
2735	*/
2736	static DECLCALLBACK(VBOXSTRICTRC)
2737	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2738	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2739	{
2740	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2741	PVGASTATE pThis = (PVGASTATE)pvUser;
2742	AssertPtr(pThis);
2743
2744	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2745	/*
2746	* Wake up the FIFO thread as it might have work to do now.
2747	*/
2748	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2749	AssertLogRelRC(rc);
2750	# endif
2751
2752	# ifdef DEBUG_FIFO_ACCESS
2753	/*
2754	* When in debug-fifo-access mode, we do not disable the access handler,
2755	* but leave it on as we wish to catch all access.
2756	*/
2757	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2758	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2759	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2760	/*
2761	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2762	*/
2763	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2764	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2765	# endif
2766	if (RT_SUCCESS(rc))
2767	return VINF_PGM_HANDLER_DO_DEFAULT;
2768	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2769	return rc;
2770	}
2771	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2772
2773	#endif /* IN_RING3 */
2774
2775	#ifdef DEBUG_GMR_ACCESS
2776	# ifdef IN_RING3
2777
2778	/**
2779	* HC access handler for GMRs.
2780	*
2781	* @returns VINF_SUCCESS if the handler have carried out the operation.
2782	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2783	* @param pVM VM Handle.
2784	* @param pVCpu The cross context CPU structure for the calling EMT.
2785	* @param GCPhys The physical address the guest is writing to.
2786	* @param pvPhys The HC mapping of that address.
2787	* @param pvBuf What the guest is reading/writing.
2788	* @param cbBuf How much it's reading/writing.
2789	* @param enmAccessType The access type.
2790	* @param enmOrigin Who is making the access.
2791	* @param pvUser User argument.
2792	*/
2793	static DECLCALLBACK(VBOXSTRICTRC)
2794	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2795	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2796	{
2797	PVGASTATE pThis = (PVGASTATE)pvUser;
2798	Assert(pThis);
2799	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2800	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2801
2802	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2803
2804	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2805	{
2806	PGMR pGMR = &pSVGAState->paGMR[i];
2807
2808	if (pGMR->numDescriptors)
2809	{
2810	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2811	{
2812	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2813	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2814	{
2815	/*
2816	* Turn off the write handler for this particular page and make it R/W.
2817	* Then return telling the caller to restart the guest instruction.
2818	*/
2819	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2820	AssertRC(rc);
2821	return VINF_PGM_HANDLER_DO_DEFAULT;
2822	}
2823	}
2824	}
2825	}
2826
2827	return VINF_PGM_HANDLER_DO_DEFAULT;
2828	}
2829
2830	/** Callback handler for VMR3ReqCallWaitU */
2831	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2832	{
2833	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2834	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2835	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2836	int rc;
2837
2838	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2839	{
2840	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2841	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2842	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2843	AssertRC(rc);
2844	}
2845	return VINF_SUCCESS;
2846	}
2847
2848	/** Callback handler for VMR3ReqCallWaitU */
2849	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2850	{
2851	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2852	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2853	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2854
2855	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2856	{
2857	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2858	AssertRC(rc);
2859	}
2860	return VINF_SUCCESS;
2861	}
2862
2863	/** Callback handler for VMR3ReqCallWaitU */
2864	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2865	{
2866	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2867
2868	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2869	{
2870	PGMR pGMR = &pSVGAState->paGMR[i];
2871
2872	if (pGMR->numDescriptors)
2873	{
2874	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2875	{
2876	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2877	AssertRC(rc);
2878	}
2879	}
2880	}
2881	return VINF_SUCCESS;
2882	}
2883
2884	# endif /* IN_RING3 */
2885	#endif /* DEBUG_GMR_ACCESS */
2886
2887	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2888
2889	#ifdef IN_RING3
2890
2891
2892	/*
2893	*
2894	* Command buffer submission.
2895	*
2896	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2897	*
2898	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2899	* and wakes up the FIFO thread.
2900	*
2901	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2902	* the buffer header back to the guest memory.
2903	*
2904	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2905	*
2906	*/
2907
2908
2909	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2910	*
2911	* @param pDevIns The device instance.
2912	* @param GCPhysCB Guest physical address of the command buffer header.
2913	* @param status Command buffer status (SVGA_CB_STATUS_*).
2914	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2915	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2916	* @thread FIFO or EMT.
2917	*/
2918	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2919	{
2920	SVGACBHeader hdr;
2921	hdr.status = status;
2922	hdr.errorOffset = errorOffset;
2923	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2924	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2925	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2926	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2927	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2928	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2929	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2930	}
2931
2932
2933	/** Raise an IRQ.
2934	*
2935	* @param pDevIns The device instance.
2936	* @param pThis The shared VGA/VMSVGA state.
2937	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2938	* @thread FIFO or EMT.
2939	*/
2940	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2941	{
2942	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2943	AssertRC(rc);
2944
2945	if (pThis->svga.u32IrqMask & u32IrqStatus)
2946	{
2947	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2948	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2949	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2950	}
2951
2952	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2953	}
2954
2955
2956	/** Allocate a command buffer structure.
2957	*
2958	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2959	* @return Pointer to the allocated command buffer structure.
2960	*/
2961	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2962	{
2963	if (!pCmdBufCtx)
2964	return NULL;
2965
2966	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2967	if (pCmdBuf)
2968	{
2969	// RT_ZERO(pCmdBuf->nodeBuffer);
2970	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2971	// pCmdBuf->GCPhysCB = 0;
2972	// RT_ZERO(pCmdBuf->hdr);
2973	// pCmdBuf->pvCommands = NULL;
2974	}
2975
2976	return pCmdBuf;
2977	}
2978
2979
2980	/** Free a command buffer structure.
2981	*
2982	* @param pCmdBuf The command buffer pointer.
2983	*/
2984	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
2985	{
2986	if (pCmdBuf)
2987	RTMemFree(pCmdBuf->pvCommands);
2988	RTMemFree(pCmdBuf);
2989	}
2990
2991
2992	/** Initialize a command buffer context.
2993	*
2994	* @param pCmdBufCtx The command buffer context.
2995	*/
2996	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
2997	{
2998	RTListInit(&pCmdBufCtx->listSubmitted);
2999	pCmdBufCtx->cSubmitted = 0;
3000	}
3001
3002
3003	/** Destroy a command buffer context.
3004	*
3005	* @param pCmdBufCtx The command buffer context pointer.
3006	*/
3007	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3008	{
3009	if (!pCmdBufCtx)
3010	return;
3011
3012	if (pCmdBufCtx->listSubmitted.pNext)
3013	{
3014	/* If the list has been initialized. */
3015	PVMSVGACMDBUF pIter, pNext;
3016	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3017	{
3018	RTListNodeRemove(&pIter->nodeBuffer);
3019	--pCmdBufCtx->cSubmitted;
3020	vmsvgaR3CmdBufFree(pIter);
3021	}
3022	}
3023	Assert(pCmdBufCtx->cSubmitted == 0);
3024	pCmdBufCtx->cSubmitted = 0;
3025	}
3026
3027
3028	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3029	*
3030	* @param pSvgaR3State VMSVGA R3 state.
3031	* @param pCmd The command data.
3032	* @return SVGACBStatus code.
3033	* @thread EMT
3034	*/
3035	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3036	{
3037	/* Create or destroy a regular command buffer context. */
3038	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3039	return SVGA_CB_STATUS_COMMAND_ERROR;
3040	RT_UNTRUSTED_VALIDATED_FENCE();
3041
3042	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3043
3044	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3045	AssertRC(rc);
3046	if (pCmd->enable)
3047	{
3048	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3049	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3050	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3051	else
3052	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3053	}
3054	else
3055	{
3056	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3057	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3058	}
3059	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3060
3061	return CBStatus;
3062	}
3063
3064
3065	/** Handles SVGA_DC_CMD_PREEMPT command.
3066	*
3067	* @param pDevIns The device instance.
3068	* @param pSvgaR3State VMSVGA R3 state.
3069	* @param pCmd The command data.
3070	* @return SVGACBStatus code.
3071	* @thread EMT
3072	*/
3073	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3074	{
3075	/* Remove buffers from the processing queue of the specified context. */
3076	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3077	return SVGA_CB_STATUS_COMMAND_ERROR;
3078	RT_UNTRUSTED_VALIDATED_FENCE();
3079
3080	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3081	RTLISTANCHOR listPreempted;
3082
3083	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3084	AssertRC(rc);
3085	if (pCmd->ignoreIDZero)
3086	{
3087	RTListInit(&listPreempted);
3088
3089	PVMSVGACMDBUF pIter, pNext;
3090	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3091	{
3092	if (pIter->hdr.id == 0)
3093	continue;
3094
3095	RTListNodeRemove(&pIter->nodeBuffer);
3096	--pCmdBufCtx->cSubmitted;
3097	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3098	}
3099	}
3100	else
3101	{
3102	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3103	}
3104	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3105
3106	PVMSVGACMDBUF pIter, pNext;
3107	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3108	{
3109	RTListNodeRemove(&pIter->nodeBuffer);
3110	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3111	vmsvgaR3CmdBufFree(pIter);
3112	}
3113
3114	return SVGA_CB_STATUS_COMPLETED;
3115	}
3116
3117
3118	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3119	* Increments the size of the command cbCmd by a_cbMore.
3120	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3121	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3122	*/
3123	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3124	if (1) { \
3125	cbCmd += (a_cbMore); \
3126	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3127	RT_UNTRUSTED_VALIDATED_FENCE(); \
3128	} else do {} while (0)
3129
3130
3131	/** Processes Device Context command buffer.
3132	*
3133	* @param pDevIns The device instance.
3134	* @param pSvgaR3State VMSVGA R3 state.
3135	* @param pvCommands Pointer to the command buffer.
3136	* @param cbCommands Size of the command buffer.
3137	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3138	* @return SVGACBStatus code.
3139	* @thread EMT
3140	*/
3141	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3142	{
3143	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3144
3145	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3146	uint32_t cbRemain = cbCommands;
3147	while (cbRemain)
3148	{
3149	/* Command identifier is a 32 bit value. */
3150	if (cbRemain < sizeof(uint32_t))
3151	{
3152	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3153	break;
3154	}
3155
3156	/* Fetch the command id. */
3157	uint32_t const cmdId = (uint32_t )pu8Cmd;
3158	uint32_t cbCmd = sizeof(uint32_t);
3159	switch (cmdId)
3160	{
3161	case SVGA_DC_CMD_NOP:
3162	{
3163	/* NOP */
3164	break;
3165	}
3166
3167	case SVGA_DC_CMD_START_STOP_CONTEXT:
3168	{
3169	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3170	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3171	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3172	break;
3173	}
3174
3175	case SVGA_DC_CMD_PREEMPT:
3176	{
3177	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3178	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3179	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3180	break;
3181	}
3182
3183	default:
3184	{
3185	/* Unsupported command. */
3186	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3187	break;
3188	}
3189	}
3190
3191	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3192	break;
3193
3194	pu8Cmd += cbCmd;
3195	cbRemain -= cbCmd;
3196	}
3197
3198	Assert(cbRemain <= cbCommands);
3199	*poffNextCmd = cbCommands - cbRemain;
3200	return CBstatus;
3201	}
3202
3203
3204	/** Submits a device context command buffer for synchronous processing.
3205	*
3206	* @param pDevIns The device instance.
3207	* @param pThisCC The VGA/VMSVGA state for the current context.
3208	* @param ppCmdBuf Pointer to the command buffer pointer.
3209	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3210	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3211	* @return SVGACBStatus code.
3212	* @thread EMT
3213	*/
3214	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3215	{
3216	/* Synchronously process the device context commands. */
3217	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3218	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3219	}
3220
3221	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3222	*
3223	* @param pDevIns The device instance.
3224	* @param pThis The shared VGA/VMSVGA state.
3225	* @param pThisCC The VGA/VMSVGA state for the current context.
3226	* @param ppCmdBuf Pointer to the command buffer pointer.
3227	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3228	* @return SVGACBStatus code.
3229	* @thread EMT
3230	*/
3231	static SVGACBStatus vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3232	{
3233	/* Command buffer submission. */
3234	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3235
3236	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3237
3238	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3239	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3240
3241	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3242	AssertRC(rc);
3243
3244	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3245	{
3246	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3247	++pCmdBufCtx->cSubmitted;
3248	ppCmdBuf = NULL; / Consume the buffer. */
3249	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3250	}
3251	else
3252	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3253
3254	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3255
3256	/* Inform the FIFO thread. */
3257	if (*ppCmdBuf == NULL)
3258	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3259
3260	return CBstatus;
3261	}
3262
3263
3264	/** SVGA_REG_COMMAND_LOW write handler.
3265	* Submits a command buffer to the FIFO thread or processes a device context command.
3266	*
3267	* @param pDevIns The device instance.
3268	* @param pThis The shared VGA/VMSVGA state.
3269	* @param pThisCC The VGA/VMSVGA state for the current context.
3270	* @param GCPhysCB Guest physical address of the command buffer header.
3271	* @param CBCtx Context the command buffer is submitted to.
3272	* @thread EMT
3273	*/
3274	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3275	{
3276	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3277
3278	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3279	uint32_t offNextCmd = 0;
3280	uint32_t fIRQ = 0;
3281
3282	/* Get the context if the device has the capability. */
3283	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3284	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3285	{
3286	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3287	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3288	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3289	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3290	RT_UNTRUSTED_VALIDATED_FENCE();
3291	}
3292
3293	/* Allocate a new command buffer. */
3294	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3295	if (RT_LIKELY(pCmdBuf))
3296	{
3297	pCmdBuf->GCPhysCB = GCPhysCB;
3298
3299	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3300	if (RT_SUCCESS(rc))
3301	{
3302	/* Verify the command buffer header. */
3303	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3304	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ)) == 0 /* No unexpected flags. */
3305	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3306	{
3307	RT_UNTRUSTED_VALIDATED_FENCE();
3308
3309	/* Read the command buffer content. */
3310	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3311	if (pCmdBuf->pvCommands)
3312	{
3313	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3314	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3315	if (RT_SUCCESS(rc))
3316	{
3317	/* Submit the buffer. Device context buffers will be processed synchronously. */
3318	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3319	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3320	CBstatus = vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, &pCmdBuf);
3321	else
3322	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3323	}
3324	else
3325	{
3326	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3327	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3328	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3329	}
3330	}
3331	else
3332	{
3333	/* No memory for commands. */
3334	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3335	}
3336	}
3337	else
3338	{
3339	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3340	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3341	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3342	}
3343	}
3344	else
3345	{
3346	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3347	ASSERT_GUEST_FAILED();
3348	/* Do not attempt to write the status. */
3349	}
3350
3351	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3352	vmsvgaR3CmdBufFree(pCmdBuf);
3353	}
3354	else
3355	{
3356	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3357	ASSERT_GUEST_FAILED();
3358	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3359	}
3360
3361	if (CBstatus != SVGA_CB_STATUS_NONE)
3362	{
3363	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf->hdr.length, fIRQ));
3364	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3365	if (fIRQ)
3366	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3367	}
3368	}
3369
3370
3371	/** Checks if there are some buffers to be processed.
3372	*
3373	* @param pThisCC The VGA/VMSVGA state for the current context.
3374	* @return true if buffers must be processed.
3375	* @thread FIFO
3376	*/
3377	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3378	{
3379	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3380	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3381	}
3382
3383
3384	/** Processes a command buffer.
3385	*
3386	* @param pDevIns The device instance.
3387	* @param pThis The shared VGA/VMSVGA state.
3388	* @param pThisCC The VGA/VMSVGA state for the current context.
3389	* @param pvCommands Pointer to the command buffer.
3390	* @param cbCommands Size of the command buffer.
3391	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3392	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3393	* @return SVGACBStatus code.
3394	* @thread FIFO
3395	*/
3396	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3397	{
3398	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3399	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3400
3401	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3402
3403	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3404	uint32_t cbRemain = cbCommands;
3405	while (cbRemain)
3406	{
3407	/* Command identifier is a 32 bit value. */
3408	if (cbRemain < sizeof(uint32_t))
3409	{
3410	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3411	break;
3412	}
3413
3414	/* Fetch the command id.
3415	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3416	* warning. Because we support some obsolete and deprecated commands, which are not included in
3417	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3418	*/
3419	uint32_t const cmdId = (uint32_t )pu8Cmd;
3420	uint32_t cbCmd = sizeof(uint32_t);
3421
3422	LogFlowFunc(("%s %d\n", vmsvgaR3FifoCmdToString(cmdId), cmdId));
3423
3424	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3425	* I.e. pu8Cmd + cbCmd must point to the next command.
3426	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3427	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3428	*/
3429	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3430	switch (cmdId)
3431	{
3432	case SVGA_CMD_INVALID_CMD:
3433	{
3434	/* Nothing to do. */
3435	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3436	break;
3437	}
3438
3439	case SVGA_CMD_FENCE:
3440	{
3441	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3442	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3443	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3444	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3445
3446	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3447	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3448	{
3449	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3450
3451	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3452	{
3453	Log(("any fence irq\n"));
3454	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3455	}
3456	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3457	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3458	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3459	{
3460	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3461	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3462	}
3463	}
3464	else
3465	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3466	break;
3467	}
3468
3469	case SVGA_CMD_UPDATE:
3470	{
3471	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3472	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3473	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3474	break;
3475	}
3476
3477	case SVGA_CMD_UPDATE_VERBOSE:
3478	{
3479	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3480	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3481	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3482	break;
3483	}
3484
3485	case SVGA_CMD_DEFINE_CURSOR:
3486	{
3487	/* Followed by bitmap data. */
3488	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3489	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3490
3491	/* Figure out the size of the bitmap data. */
3492	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3493	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3494	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3495	RT_UNTRUSTED_VALIDATED_FENCE();
3496
3497	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3498	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3499	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3500	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3501
3502	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3503	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3504	break;
3505	}
3506
3507	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3508	{
3509	/* Followed by bitmap data. */
3510	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3511	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3512
3513	/* Figure out the size of the bitmap data. */
3514	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3515
3516	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3517	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3518	break;
3519	}
3520
3521	case SVGA_CMD_MOVE_CURSOR:
3522	{
3523	/* Deprecated; there should be no driver which requires this command. However, if
3524	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3525	* alignment.
3526	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3527	*/
3528	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3529	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3530	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3531	break;
3532	}
3533
3534	case SVGA_CMD_DISPLAY_CURSOR:
3535	{
3536	/* Deprecated; there should be no driver which requires this command. However, if
3537	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3538	* alignment.
3539	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3540	*/
3541	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3542	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3543	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3544	break;
3545	}
3546
3547	case SVGA_CMD_RECT_FILL:
3548	{
3549	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3550	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3551	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3552	break;
3553	}
3554
3555	case SVGA_CMD_RECT_COPY:
3556	{
3557	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3558	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3559	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3560	break;
3561	}
3562
3563	case SVGA_CMD_RECT_ROP_COPY:
3564	{
3565	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3566	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3567	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3568	break;
3569	}
3570
3571	case SVGA_CMD_ESCAPE:
3572	{
3573	/* Followed by 'size' bytes of data. */
3574	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3575	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3576
3577	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3578	RT_UNTRUSTED_VALIDATED_FENCE();
3579
3580	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3581	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3582	break;
3583	}
3584	# ifdef VBOX_WITH_VMSVGA3D
3585	case SVGA_CMD_DEFINE_GMR2:
3586	{
3587	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3588	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3589	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3590	break;
3591	}
3592
3593	case SVGA_CMD_REMAP_GMR2:
3594	{
3595	/* Followed by page descriptors or guest ptr. */
3596	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3597	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3598
3599	/* Calculate the size of what comes after next and fetch it. */
3600	uint32_t cbMore = 0;
3601	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3602	cbMore = sizeof(SVGAGuestPtr);
3603	else
3604	{
3605	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3606	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3607	{
3608	cbMore = cbPageDesc;
3609	pCmd->numPages = 1;
3610	}
3611	else
3612	{
3613	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3614	cbMore = cbPageDesc * pCmd->numPages;
3615	}
3616	}
3617	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3618	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3619	# ifdef DEBUG_GMR_ACCESS
3620	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3621	# endif
3622	break;
3623	}
3624	# endif /* VBOX_WITH_VMSVGA3D */
3625	case SVGA_CMD_DEFINE_SCREEN:
3626	{
3627	/* The size of this command is specified by the guest and depends on capabilities. */
3628	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3629	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3630	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3631	RT_UNTRUSTED_VALIDATED_FENCE();
3632
3633	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3634	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3635	break;
3636	}
3637
3638	case SVGA_CMD_DESTROY_SCREEN:
3639	{
3640	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3641	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3642	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3643	break;
3644	}
3645
3646	case SVGA_CMD_DEFINE_GMRFB:
3647	{
3648	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3649	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3650	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3651	break;
3652	}
3653
3654	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3655	{
3656	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3657	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3658	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3659	break;
3660	}
3661
3662	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3663	{
3664	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3665	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3666	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3667	break;
3668	}
3669
3670	case SVGA_CMD_ANNOTATION_FILL:
3671	{
3672	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3673	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3674	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3675	break;
3676	}
3677
3678	case SVGA_CMD_ANNOTATION_COPY:
3679	{
3680	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3681	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3682	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3683	break;
3684	}
3685
3686	default:
3687	{
3688	# ifdef VBOX_WITH_VMSVGA3D
3689	if ( cmdId >= SVGA_3D_CMD_BASE
3690	&& cmdId < SVGA_3D_CMD_MAX)
3691	{
3692	RT_UNTRUSTED_VALIDATED_FENCE();
3693
3694	/* All 3d commands start with a common header, which defines the identifier and the size
3695	* of the command. The identifier has been already read. Fetch the size.
3696	*/
3697	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3698	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3699	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3700	if (RT_LIKELY(pThis->svga.f3DEnabled))
3701	{ /* likely */ }
3702	else
3703	{
3704	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3705	break;
3706	}
3707
3708	/* Command data begins after the 32 bit command length. */
3709	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3710	if (RT_SUCCESS(rc))
3711	{ /* likely */ }
3712	else
3713	{
3714	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3715	break;
3716	}
3717	}
3718	else
3719	# endif /* VBOX_WITH_VMSVGA3D */
3720	{
3721	/* Unsupported command. */
3722	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3723	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3724	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3725	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3726	break;
3727	}
3728	}
3729	}
3730
3731	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3732	break;
3733
3734	pu8Cmd += cbCmd;
3735	cbRemain -= cbCmd;
3736
3737	/* If this is not the last command in the buffer, then generate IRQ, if required.
3738	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3739	* in the buffer (usually the case).
3740	*/
3741	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3742	{ /* likely */ }
3743	else
3744	{
3745	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3746	*pu32IrqStatus = 0;
3747	}
3748	}
3749
3750	Assert(cbRemain <= cbCommands);
3751	*poffNextCmd = cbCommands - cbRemain;
3752	return CBstatus;
3753	}
3754
3755
3756	/** Process command buffers.
3757	*
3758	* @param pDevIns The device instance.
3759	* @param pThis The shared VGA/VMSVGA state.
3760	* @param pThisCC The VGA/VMSVGA state for the current context.
3761	* @param pThread Handle of the FIFO thread.
3762	* @thread FIFO
3763	*/
3764	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3765	{
3766	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3767
3768	for (;;)
3769	{
3770	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3771	break;
3772
3773	/* See if there is a submitted buffer. */
3774	PVMSVGACMDBUF pCmdBuf = NULL;
3775
3776	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3777	AssertRC(rc);
3778
3779	/* It seems that a higher queue index has a higher priority.
3780	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3781	*/
3782	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3783	{
3784	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3785	if (pCmdBufCtx)
3786	{
3787	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3788	if (pCmdBuf)
3789	{
3790	Assert(pCmdBufCtx->cSubmitted > 0);
3791	--pCmdBufCtx->cSubmitted;
3792	break;
3793	}
3794	}
3795	}
3796
3797	if (!pCmdBuf)
3798	{
3799	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3800	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3801	break;
3802	}
3803
3804	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3805
3806	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3807	uint32_t offNextCmd = 0;
3808	uint32_t u32IrqStatus = 0;
3809
3810	/* Process one buffer. */
3811	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3812
3813	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3814	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3815	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3816	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3817
3818	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3819	if (u32IrqStatus)
3820	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3821
3822	vmsvgaR3CmdBufFree(pCmdBuf);
3823	}
3824	}
3825
3826
3827	/**
3828	* Worker for vmsvgaR3FifoThread that handles an external command.
3829	*
3830	* @param pDevIns The device instance.
3831	* @param pThis The shared VGA/VMSVGA instance data.
3832	* @param pThisCC The VGA/VMSVGA state for ring-3.
3833	*/
3834	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3835	{
3836	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3837	switch (pThis->svga.u8FIFOExtCommand)
3838	{
3839	case VMSVGA_FIFO_EXTCMD_RESET:
3840	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3841	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3842
3843	vmsvgaR3ResetScreens(pThis, pThisCC);
3844	# ifdef VBOX_WITH_VMSVGA3D
3845	if (pThis->svga.f3DEnabled)
3846	{
3847	/* The 3d subsystem must be reset from the fifo thread. */
3848	vmsvga3dReset(pThisCC);
3849	}
3850	# endif
3851	break;
3852
3853	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3854	Log(("vmsvgaR3FifoLoop: power off.\n"));
3855	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3856
3857	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3858	vmsvgaR3ResetScreens(pThis, pThisCC);
3859	break;
3860
3861	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3862	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3863	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3864	# ifdef VBOX_WITH_VMSVGA3D
3865	if (pThis->svga.f3DEnabled)
3866	{
3867	/* The 3d subsystem must be shut down from the fifo thread. */
3868	vmsvga3dTerminate(pThisCC);
3869	}
3870	# endif
3871	break;
3872
3873	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3874	{
3875	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3876	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3877	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3878	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3879	# ifdef VBOX_WITH_VMSVGA3D
3880	if (pThis->svga.f3DEnabled)
3881	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3882	# endif
3883	break;
3884	}
3885
3886	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3887	{
3888	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3889	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3890	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3891	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3892	# ifdef VBOX_WITH_VMSVGA3D
3893	if (pThis->svga.f3DEnabled)
3894	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3895	# endif
3896	break;
3897	}
3898
3899	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3900	{
3901	# ifdef VBOX_WITH_VMSVGA3D
3902	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3903	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3904	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3905	# endif
3906	break;
3907	}
3908
3909
3910	default:
3911	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3912	break;
3913	}
3914
3915	/*
3916	* Signal the end of the external command.
3917	*/
3918	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3919	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3920	ASMMemoryFence(); /* paranoia^2 */
3921	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3922	AssertLogRelRC(rc);
3923	}
3924
3925	/**
3926	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3927	* doing a job on the FIFO thread (even when it's officially suspended).
3928	*
3929	* @returns VBox status code (fully asserted).
3930	* @param pDevIns The device instance.
3931	* @param pThis The shared VGA/VMSVGA instance data.
3932	* @param pThisCC The VGA/VMSVGA state for ring-3.
3933	* @param uExtCmd The command to execute on the FIFO thread.
3934	* @param pvParam Pointer to command parameters.
3935	* @param cMsWait The time to wait for the command, given in
3936	* milliseconds.
3937	*/
3938	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3939	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3940	{
3941	Assert(cMsWait >= RT_MS_1SEC * 5);
3942	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3943	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3944
3945	int rc;
3946	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3947	PDMTHREADSTATE enmState = pThread->enmState;
3948	if (enmState == PDMTHREADSTATE_SUSPENDED)
3949	{
3950	/*
3951	* The thread is suspended, we have to temporarily wake it up so it can
3952	* perform the task.
3953	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3954	*/
3955	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3956	/* Post the request. */
3957	pThis->svga.fFifoExtCommandWakeup = true;
3958	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3959	pThis->svga.u8FIFOExtCommand = uExtCmd;
3960	ASMMemoryFence(); /* paranoia^3 */
3961
3962	/* Resume the thread. */
3963	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3964	AssertLogRelRC(rc);
3965	if (RT_SUCCESS(rc))
3966	{
3967	/* Wait. Take care in case the semaphore was already posted (same as below). */
3968	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3969	if ( rc == VINF_SUCCESS
3970	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3971	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3972	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3973	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3974
3975	/* suspend the thread */
3976	pThis->svga.fFifoExtCommandWakeup = false;
3977	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3978	AssertLogRelRC(rc2);
3979	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3980	rc = rc2;
3981	}
3982	pThis->svga.fFifoExtCommandWakeup = false;
3983	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3984	}
3985	else if (enmState == PDMTHREADSTATE_RUNNING)
3986	{
3987	/*
3988	* The thread is running, should only happen during reset and vmsvga3dsfc.
3989	* We ASSUME not racing code here, both wrt thread state and ext commands.
3990	*/
3991	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3992	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
3993
3994	/* Post the request. */
3995	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3996	pThis->svga.u8FIFOExtCommand = uExtCmd;
3997	ASMMemoryFence(); /* paranoia^2 */
3998	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3999	AssertLogRelRC(rc);
4000
4001	/* Wait. Take care in case the semaphore was already posted (same as above). */
4002	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4003	if ( rc == VINF_SUCCESS
4004	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4005	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4006	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4007	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4008
4009	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4010	}
4011	else
4012	{
4013	/*
4014	* Something is wrong with the thread!
4015	*/
4016	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4017	rc = VERR_INVALID_STATE;
4018	}
4019	return rc;
4020	}
4021
4022
4023	/**
4024	* Marks the FIFO non-busy, notifying any waiting EMTs.
4025	*
4026	* @param pDevIns The device instance.
4027	* @param pThis The shared VGA/VMSVGA instance data.
4028	* @param pThisCC The VGA/VMSVGA state for ring-3.
4029	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4030	* @param offFifoMin The start byte offset of the command FIFO.
4031	*/
4032	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4033	{
4034	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4035	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4036	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4037
4038	/* Wake up any waiting EMTs. */
4039	if (pSVGAState->cBusyDelayedEmts > 0)
4040	{
4041	# ifdef VMSVGA_USE_EMT_HALT_CODE
4042	PVM pVM = PDMDevHlpGetVM(pDevIns);
4043	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4044	if (idCpu != NIL_VMCPUID)
4045	{
4046	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4047	while (idCpu-- > 0)
4048	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4049	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4050	}
4051	# else
4052	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4053	AssertRC(rc2);
4054	# endif
4055	}
4056	}
4057
4058	/**
4059	* Reads (more) payload into the command buffer.
4060	*
4061	* @returns pbBounceBuf on success
4062	* @retval (void *)1 if the thread was requested to stop.
4063	* @retval NULL on FIFO error.
4064	*
4065	* @param cbPayloadReq The number of bytes of payload requested.
4066	* @param pFIFO The FIFO.
4067	* @param offCurrentCmd The FIFO byte offset of the current command.
4068	* @param offFifoMin The start byte offset of the command FIFO.
4069	* @param offFifoMax The end byte offset of the command FIFO.
4070	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4071	* always sufficient size.
4072	* @param pcbAlreadyRead How much payload we've already read into the bounce
4073	* buffer. (We will NEVER re-read anything.)
4074	* @param pThread The calling PDM thread handle.
4075	* @param pThis The shared VGA/VMSVGA instance data.
4076	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4077	* statistics collection.
4078	* @param pDevIns The device instance.
4079	*/
4080	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4081	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4082	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4083	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4084	{
4085	Assert(pbBounceBuf);
4086	Assert(pcbAlreadyRead);
4087	Assert(offFifoMin < offFifoMax);
4088	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4089	Assert(offFifoMax <= pThis->svga.cbFIFO);
4090
4091	/*
4092	* Check if the requested payload size has already been satisfied .
4093	* .
4094	* When called to read more, the caller is responsible for making sure the .
4095	* new command size (cbRequsted) never is smaller than what has already .
4096	* been read.
4097	*/
4098	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4099	if (cbPayloadReq <= cbAlreadyRead)
4100	{
4101	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4102	return pbBounceBuf;
4103	}
4104
4105	/*
4106	* Commands bigger than the fifo buffer are invalid.
4107	*/
4108	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4109	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4110	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4111	NULL);
4112
4113	/*
4114	* Move offCurrentCmd past the command dword.
4115	*/
4116	offCurrentCmd += sizeof(uint32_t);
4117	if (offCurrentCmd >= offFifoMax)
4118	offCurrentCmd = offFifoMin;
4119
4120	/*
4121	* Do we have sufficient payload data available already?
4122	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4123	*/
4124	uint32_t cbAfter, cbBefore;
4125	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4126	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4127	if (offNextCmd >= offCurrentCmd)
4128	{
4129	if (RT_LIKELY(offNextCmd < offFifoMax))
4130	cbAfter = offNextCmd - offCurrentCmd;
4131	else
4132	{
4133	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4134	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4135	offNextCmd, offFifoMin, offFifoMax));
4136	cbAfter = offFifoMax - offCurrentCmd;
4137	}
4138	cbBefore = 0;
4139	}
4140	else
4141	{
4142	cbAfter = offFifoMax - offCurrentCmd;
4143	if (offNextCmd >= offFifoMin)
4144	cbBefore = offNextCmd - offFifoMin;
4145	else
4146	{
4147	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4148	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4149	offNextCmd, offFifoMin, offFifoMax));
4150	cbBefore = 0;
4151	}
4152	}
4153	if (cbAfter + cbBefore < cbPayloadReq)
4154	{
4155	/*
4156	* Insufficient, must wait for it to arrive.
4157	*/
4158	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4159	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4160	for (uint32_t i = 0;; i++)
4161	{
4162	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4163	{
4164	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4165	return (void *)(uintptr_t)1;
4166	}
4167	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4168	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4169
4170	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4171
4172	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4173	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4174	if (offNextCmd >= offCurrentCmd)
4175	{
4176	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4177	cbBefore = 0;
4178	}
4179	else
4180	{
4181	cbAfter = offFifoMax - offCurrentCmd;
4182	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4183	}
4184
4185	if (cbAfter + cbBefore >= cbPayloadReq)
4186	break;
4187	}
4188	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4189	}
4190
4191	/*
4192	* Copy out the memory and update what pcbAlreadyRead points to.
4193	*/
4194	if (cbAfter >= cbPayloadReq)
4195	memcpy(pbBounceBuf + cbAlreadyRead,
4196	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4197	cbPayloadReq - cbAlreadyRead);
4198	else
4199	{
4200	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4201	if (cbAlreadyRead < cbAfter)
4202	{
4203	memcpy(pbBounceBuf + cbAlreadyRead,
4204	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4205	cbAfter - cbAlreadyRead);
4206	cbAlreadyRead = cbAfter;
4207	}
4208	memcpy(pbBounceBuf + cbAlreadyRead,
4209	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4210	cbPayloadReq - cbAlreadyRead);
4211	}
4212	*pcbAlreadyRead = cbPayloadReq;
4213	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4214	return pbBounceBuf;
4215	}
4216
4217
4218	/**
4219	* Sends cursor position and visibility information from the FIFO to the front-end.
4220	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4221	*/
4222	static uint32_t
4223	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4224	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4225	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4226	{
4227	/*
4228	* Check if the cursor update counter has changed and try get a stable
4229	* set of values if it has. This is race-prone, especially consindering
4230	* the screen ID, but little we can do about that.
4231	*/
4232	uint32_t x, y, fVisible, idScreen;
4233	for (uint32_t i = 0; ; i++)
4234	{
4235	x = pFIFO[SVGA_FIFO_CURSOR_X];
4236	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4237	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4238	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4239	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4240	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4241	\|\| i > 3)
4242	break;
4243	if (i == 0)
4244	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4245	ASMNopPause();
4246	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4247	}
4248
4249	/*
4250	* Check if anything has changed, as calling into pDrv is not light-weight.
4251	*/
4252	if ( *pxLast == x
4253	&& *pyLast == y
4254	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4255	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4256	else
4257	{
4258	/*
4259	* Detected changes.
4260	*
4261	* We handle global, not per-screen visibility information by sending
4262	* pfnVBVAMousePointerShape without shape data.
4263	*/
4264	*pxLast = x;
4265	*pyLast = y;
4266	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4267	if (idScreen != SVGA_ID_INVALID)
4268	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4269	else if (*pfLastVisible != fVisible)
4270	{
4271	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4272	*pfLastVisible = fVisible;
4273	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4274	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4275	}
4276	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4277	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4278	}
4279
4280	/*
4281	* Update done. Signal this to the guest.
4282	*/
4283	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4284
4285	return uCursorUpdateCount;
4286	}
4287
4288
4289	/**
4290	* Checks if there is work to be done, either cursor updating or FIFO commands.
4291	*
4292	* @returns true if pending work, false if not.
4293	* @param pThisCC The VGA/VMSVGA state for ring-3.
4294	* @param uLastCursorCount The last cursor update counter value.
4295	*/
4296	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4297	{
4298	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4299	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4300	AssertReturn(pFIFO, false);
4301
4302	if (vmsvgaR3CmdBufHasWork(pThisCC))
4303	return true;
4304
4305	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4306	return true;
4307
4308	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4309	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4310	return true;
4311
4312	return false;
4313	}
4314
4315
4316	/**
4317	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4318	*
4319	* @param pDevIns The device instance.
4320	* @param pThis The shared VGA/VMSVGA instance data.
4321	* @param pThisCC The VGA/VMSVGA state for ring-3.
4322	*/
4323	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4324	{
4325	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4326	to recheck it before doing the signalling. */
4327	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4328	&& pThis->svga.fFIFOThreadSleeping
4329	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4330	{
4331	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4332	AssertRC(rc);
4333	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4334	}
4335	}
4336
4337
4338	/**
4339	* Called by the FIFO thread to process pending actions.
4340	*
4341	* @param pDevIns The device instance.
4342	* @param pThis The shared VGA/VMSVGA instance data.
4343	* @param pThisCC The VGA/VMSVGA state for ring-3.
4344	*/
4345	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4346	{
4347	RT_NOREF(pDevIns);
4348
4349	/* Currently just mode changes. */
4350	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4351	{
4352	vmsvgaR3ChangeMode(pThis, pThisCC);
4353	# ifdef VBOX_WITH_VMSVGA3D
4354	if (pThisCC->svga.p3dState != NULL)
4355	vmsvga3dChangeMode(pThisCC);
4356	# endif
4357	}
4358	}
4359
4360
4361	/*
4362	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4363	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4364	*/
4365	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4366	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4367	*
4368	* Will break out of the switch on failure.
4369	* Will restart and quit the loop if the thread was requested to stop.
4370	*
4371	* @param a_PtrVar Request variable pointer.
4372	* @param a_Type Request typedef (not pointer) for casting.
4373	* @param a_cbPayloadReq How much payload to fetch.
4374	* @remarks Accesses a bunch of variables in the current scope!
4375	*/
4376	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4377	if (1) { \
4378	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4379	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4380	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4381	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4382	} else do {} while (0)
4383	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4384	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4385	* buffer after figuring out the actual command size.
4386	*
4387	* Will break out of the switch on failure.
4388	*
4389	* @param a_PtrVar Request variable pointer.
4390	* @param a_Type Request typedef (not pointer) for casting.
4391	* @param a_cbPayloadReq How much payload to fetch.
4392	* @remarks Accesses a bunch of variables in the current scope!
4393	*/
4394	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4395	if (1) { \
4396	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4397	} else do {} while (0)
4398
4399	/**
4400	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4401	*/
4402	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4403	{
4404	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4405	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4406	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4407	int rc;
4408
4409	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4410	if (pThis->svga.f3DEnabled)
4411	{
4412	/* The FIFO thread may use X API for accelerated screen output. */
4413	XInitThreads();
4414	}
4415	# endif
4416
4417	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4418	return VINF_SUCCESS;
4419
4420	/*
4421	* Special mode where we only execute an external command and the go back
4422	* to being suspended. Currently, all ext cmds ends up here, with the reset
4423	* one also being eligble for runtime execution further down as well.
4424	*/
4425	if (pThis->svga.fFifoExtCommandWakeup)
4426	{
4427	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4428	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4429	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4430	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4431	else
4432	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4433	return VINF_SUCCESS;
4434	}
4435
4436
4437	/*
4438	* Signal the semaphore to make sure we don't wait for 250ms after a
4439	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4440	*/
4441	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4442
4443	/*
4444	* Allocate a bounce buffer for command we get from the FIFO.
4445	* (All code must return via the end of the function to free this buffer.)
4446	*/
4447	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4448	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4449
4450	/*
4451	* Polling/sleep interval config.
4452	*
4453	* We wait for an a short interval if the guest has recently given us work
4454	* to do, but the interval increases the longer we're kept idle. Once we've
4455	* reached the refresh timer interval, we'll switch to extended waits,
4456	* depending on it or the guest to kick us into action when needed.
4457	*
4458	* Should the refresh time go fishing, we'll just continue increasing the
4459	* sleep length till we reaches the 250 ms max after about 16 seconds.
4460	*/
4461	RTMSINTERVAL const cMsMinSleep = 16;
4462	RTMSINTERVAL const cMsIncSleep = 2;
4463	RTMSINTERVAL const cMsMaxSleep = 250;
4464	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4465	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4466
4467	/*
4468	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4469	*
4470	* Initialize with values that will detect an update from the guest.
4471	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4472	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4473	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4474	*/
4475	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4476	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4477	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4478	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4479	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4480
4481	/*
4482	* The FIFO loop.
4483	*/
4484	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4485	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4486	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4487	{
4488	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4489	/*
4490	* Should service the run loop every so often.
4491	*/
4492	if (pThis->svga.f3DEnabled)
4493	vmsvga3dCocoaServiceRunLoop();
4494	# endif
4495
4496	/* First check any pending actions. */
4497	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4498
4499	/*
4500	* Unless there's already work pending, go to sleep for a short while.
4501	* (See polling/sleep interval config above.)
4502	*/
4503	if ( fBadOrDisabledFifo
4504	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4505	{
4506	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4507	Assert(pThis->cMilliesRefreshInterval > 0);
4508	if (cMsSleep < pThis->cMilliesRefreshInterval)
4509	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4510	else
4511	{
4512	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4513	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4514	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4515	# endif
4516	if ( !fBadOrDisabledFifo
4517	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4518	rc = VINF_SUCCESS;
4519	else
4520	{
4521	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4522	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4523	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4524	}
4525	}
4526	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4527	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4528	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4529	{
4530	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4531	break;
4532	}
4533	}
4534	else
4535	rc = VINF_SUCCESS;
4536	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4537	if (rc == VERR_TIMEOUT)
4538	{
4539	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4540	{
4541	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4542	continue;
4543	}
4544	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4545
4546	Log(("vmsvgaR3FifoLoop: timeout\n"));
4547	}
4548	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4549	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4550	cMsSleep = cMsMinSleep;
4551
4552	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4553	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4554	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4555
4556	/*
4557	* Handle external commands (currently only reset).
4558	*/
4559	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4560	{
4561	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4562	continue;
4563	}
4564
4565	/*
4566	* If guest misbehaves, then do nothing.
4567	*/
4568	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4569	{
4570	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4571	cMsSleep = cMsExtendedSleep;
4572	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4573	continue;
4574	}
4575
4576	/*
4577	* The device must be enabled and configured.
4578	*/
4579	if ( !pThis->svga.fEnabled
4580	\|\| !pThis->svga.fConfigured)
4581	{
4582	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4583	fBadOrDisabledFifo = true;
4584	cMsSleep = cMsMaxSleep; /* cheat */
4585	continue;
4586	}
4587
4588	/*
4589	* Get and check the min/max values. We ASSUME that they will remain
4590	* unchanged while we process requests. A further ASSUMPTION is that
4591	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4592	* we don't read it back while in the loop.
4593	*/
4594	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4595	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4596	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4597	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4598	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4599	\|\| offFifoMax <= offFifoMin
4600	\|\| offFifoMax > pThis->svga.cbFIFO
4601	\|\| (offFifoMax & 3) != 0
4602	\|\| (offFifoMin & 3) != 0
4603	\|\| offCurrentCmd < offFifoMin
4604	\|\| offCurrentCmd > offFifoMax))
4605	{
4606	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4607	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4608	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4609	fBadOrDisabledFifo = true;
4610	continue;
4611	}
4612	RT_UNTRUSTED_VALIDATED_FENCE();
4613	if (RT_UNLIKELY(offCurrentCmd & 3))
4614	{
4615	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4616	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4617	offCurrentCmd &= ~UINT32_C(3);
4618	}
4619
4620	/*
4621	* Update the cursor position before we start on the FIFO commands.
4622	*/
4623	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4624	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4625	{
4626	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4627	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4628	{ /* halfways likely */ }
4629	else
4630	{
4631	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4632	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4633	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4634	}
4635	}
4636
4637	/*
4638	* Mark the FIFO as busy.
4639	*/
4640	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4641	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4642	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4643
4644	/*
4645	* Process all submitted command buffers.
4646	*/
4647	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4648
4649	/*
4650	* Execute all queued FIFO commands.
4651	* Quit if pending external command or changes in the thread state.
4652	*/
4653	bool fDone = false;
4654	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4655	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4656	{
4657	uint32_t cbPayload = 0;
4658	uint32_t u32IrqStatus = 0;
4659
4660	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4661
4662	/* First check any pending actions. */
4663	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4664
4665	/* Check for pending external commands (reset). */
4666	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4667	break;
4668
4669	/*
4670	* Process the command.
4671	*/
4672	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4673	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4674	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4675	*/
4676	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4677	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4678	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4679	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4680	switch (enmCmdId)
4681	{
4682	case SVGA_CMD_INVALID_CMD:
4683	/* Nothing to do. */
4684	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4685	break;
4686
4687	case SVGA_CMD_FENCE:
4688	{
4689	SVGAFifoCmdFence *pCmdFence;
4690	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4691	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4692	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4693	{
4694	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4695	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4696
4697	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4698	{
4699	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4700	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4701	}
4702	else
4703	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4704	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4705	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4706	{
4707	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4708	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4709	}
4710	}
4711	else
4712	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4713	break;
4714	}
4715
4716	case SVGA_CMD_UPDATE:
4717	{
4718	SVGAFifoCmdUpdate *pCmd;
4719	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4720	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4721	break;
4722	}
4723
4724	case SVGA_CMD_UPDATE_VERBOSE:
4725	{
4726	SVGAFifoCmdUpdateVerbose *pCmd;
4727	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4728	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4729	break;
4730	}
4731
4732	case SVGA_CMD_DEFINE_CURSOR:
4733	{
4734	/* Followed by bitmap data. */
4735	SVGAFifoCmdDefineCursor *pCmd;
4736	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4737
4738	/* Figure out the size of the bitmap data. */
4739	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4740	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4741	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4742	RT_UNTRUSTED_VALIDATED_FENCE();
4743
4744	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4745	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4746	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4747	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4748
4749	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4750	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4751	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4752	break;
4753	}
4754
4755	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4756	{
4757	/* Followed by bitmap data. */
4758	SVGAFifoCmdDefineAlphaCursor *pCmd;
4759	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4760
4761	/* Figure out the size of the bitmap data. */
4762	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4763
4764	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4765	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4766	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4767	break;
4768	}
4769
4770	case SVGA_CMD_MOVE_CURSOR:
4771	{
4772	/* Deprecated; there should be no driver which requires this command. However, if
4773	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4774	* alignment.
4775	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4776	*/
4777	SVGAFifoCmdMoveCursor *pCmd;
4778	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4779	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4780	break;
4781	}
4782
4783	case SVGA_CMD_DISPLAY_CURSOR:
4784	{
4785	/* Deprecated; there should be no driver which requires this command. However, if
4786	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4787	* alignment.
4788	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4789	*/
4790	SVGAFifoCmdDisplayCursor *pCmd;
4791	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4792	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4793	break;
4794	}
4795
4796	case SVGA_CMD_RECT_FILL:
4797	{
4798	SVGAFifoCmdRectFill *pCmd;
4799	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4800	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4801	break;
4802	}
4803
4804	case SVGA_CMD_RECT_COPY:
4805	{
4806	SVGAFifoCmdRectCopy *pCmd;
4807	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4808	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4809	break;
4810	}
4811
4812	case SVGA_CMD_RECT_ROP_COPY:
4813	{
4814	SVGAFifoCmdRectRopCopy *pCmd;
4815	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4816	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4817	break;
4818	}
4819
4820	case SVGA_CMD_ESCAPE:
4821	{
4822	/* Followed by 'size' bytes of data. */
4823	SVGAFifoCmdEscape *pCmd;
4824	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4825
4826	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4827	RT_UNTRUSTED_VALIDATED_FENCE();
4828
4829	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4830	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4831	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4832	break;
4833	}
4834	# ifdef VBOX_WITH_VMSVGA3D
4835	case SVGA_CMD_DEFINE_GMR2:
4836	{
4837	SVGAFifoCmdDefineGMR2 *pCmd;
4838	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4839	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4840	break;
4841	}
4842
4843	case SVGA_CMD_REMAP_GMR2:
4844	{
4845	/* Followed by page descriptors or guest ptr. */
4846	SVGAFifoCmdRemapGMR2 *pCmd;
4847	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4848
4849	/* Calculate the size of what comes after next and fetch it. */
4850	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4851	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4852	cbCmd += sizeof(SVGAGuestPtr);
4853	else
4854	{
4855	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4856	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4857	{
4858	cbCmd += cbPageDesc;
4859	pCmd->numPages = 1;
4860	}
4861	else
4862	{
4863	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4864	cbCmd += cbPageDesc * pCmd->numPages;
4865	}
4866	}
4867	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4868	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4869	# ifdef DEBUG_GMR_ACCESS
4870	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4871	# endif
4872	break;
4873	}
4874	# endif // VBOX_WITH_VMSVGA3D
4875	case SVGA_CMD_DEFINE_SCREEN:
4876	{
4877	/* The size of this command is specified by the guest and depends on capabilities. */
4878	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4879
4880	SVGAFifoCmdDefineScreen *pCmd;
4881	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4882	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4883	RT_UNTRUSTED_VALIDATED_FENCE();
4884
4885	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4886	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4887	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4888	break;
4889	}
4890
4891	case SVGA_CMD_DESTROY_SCREEN:
4892	{
4893	SVGAFifoCmdDestroyScreen *pCmd;
4894	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4895	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4896	break;
4897	}
4898
4899	case SVGA_CMD_DEFINE_GMRFB:
4900	{
4901	SVGAFifoCmdDefineGMRFB *pCmd;
4902	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4903	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4904	break;
4905	}
4906
4907	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4908	{
4909	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4910	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4911	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4912	break;
4913	}
4914
4915	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4916	{
4917	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4918	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4919	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4920	break;
4921	}
4922
4923	case SVGA_CMD_ANNOTATION_FILL:
4924	{
4925	SVGAFifoCmdAnnotationFill *pCmd;
4926	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4927	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4928	break;
4929	}
4930
4931	case SVGA_CMD_ANNOTATION_COPY:
4932	{
4933	SVGAFifoCmdAnnotationCopy *pCmd;
4934	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4935	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4936	break;
4937	}
4938
4939	default:
4940	# ifdef VBOX_WITH_VMSVGA3D
4941	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4942	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4943	{
4944	RT_UNTRUSTED_VALIDATED_FENCE();
4945
4946	/* All 3d commands start with a common header, which defines the identifier and the size
4947	* of the command. The identifier has been already read from FIFO. Fetch the size.
4948	*/
4949	uint32_t *pcbCmd;
4950	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
4951	uint32_t const cbCmd = *pcbCmd;
4952	AssertBreak(cbCmd < pThis->svga.cbFIFO);
4953	uint32_t *pu32Cmd;
4954	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
4955	pu32Cmd++; /* Skip the command size. */
4956
4957	if (RT_LIKELY(pThis->svga.f3DEnabled))
4958	{ /* likely */ }
4959	else
4960	{
4961	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
4962	break;
4963	}
4964
4965	vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
4966	}
4967	else
4968	# endif // VBOX_WITH_VMSVGA3D
4969	{
4970	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4971	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4972	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
4973	}
4974	}
4975
4976	/* Go to the next slot */
4977	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4978	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4979	if (offCurrentCmd >= offFifoMax)
4980	{
4981	offCurrentCmd -= offFifoMax - offFifoMin;
4982	Assert(offCurrentCmd >= offFifoMin);
4983	Assert(offCurrentCmd < offFifoMax);
4984	}
4985	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4986	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4987
4988	/*
4989	* Raise IRQ if required. Must enter the critical section here
4990	* before making final decisions here, otherwise cubebench and
4991	* others may end up waiting forever.
4992	*/
4993	if ( u32IrqStatus
4994	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4995	{
4996	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4997	AssertRC(rc2);
4998
4999	/* FIFO progress might trigger an interrupt. */
5000	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5001	{
5002	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5003	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5004	}
5005
5006	/* Unmasked IRQ pending? */
5007	if (pThis->svga.u32IrqMask & u32IrqStatus)
5008	{
5009	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5010	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5011	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5012	}
5013
5014	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5015	}
5016	}
5017
5018	/* If really done, clear the busy flag. */
5019	if (fDone)
5020	{
5021	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5022	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5023	}
5024	}
5025
5026	/*
5027	* Free the bounce buffer. (There are no returns above!)
5028	*/
5029	RTMemFree(pbBounceBuf);
5030
5031	return VINF_SUCCESS;
5032	}
5033
5034	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5035	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5036
5037	/**
5038	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5039	* Unblock the FIFO I/O thread so it can respond to a state change.}
5040	*/
5041	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5042	{
5043	RT_NOREF(pDevIns);
5044	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5045	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5046	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5047	}
5048
5049	/**
5050	* Enables or disables dirty page tracking for the framebuffer
5051	*
5052	* @param pDevIns The device instance.
5053	* @param pThis The shared VGA/VMSVGA instance data.
5054	* @param fTraces Enable/disable traces
5055	*/
5056	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5057	{
5058	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5059	&& !fTraces)
5060	{
5061	//Assert(pThis->svga.fTraces);
5062	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5063	return;
5064	}
5065
5066	pThis->svga.fTraces = fTraces;
5067	if (pThis->svga.fTraces)
5068	{
5069	unsigned cbFrameBuffer = pThis->vram_size;
5070
5071	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5072	/** @todo How does this work with screens? */
5073	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5074	{
5075	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5076	Assert(pThis->svga.cbScanline);
5077	# endif
5078	/* Hardware enabled; return real framebuffer size .*/
5079	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5080	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5081	}
5082
5083	if (!pThis->svga.fVRAMTracking)
5084	{
5085	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5086	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5087	pThis->svga.fVRAMTracking = true;
5088	}
5089	}
5090	else
5091	{
5092	if (pThis->svga.fVRAMTracking)
5093	{
5094	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5095	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5096	pThis->svga.fVRAMTracking = false;
5097	}
5098	}
5099	}
5100
5101	/**
5102	* @callback_method_impl{FNPCIIOREGIONMAP}
5103	*/
5104	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5105	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5106	{
5107	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5108	int rc;
5109	RT_NOREF(pPciDev);
5110	Assert(pPciDev == pDevIns->apPciDevs[0]);
5111
5112	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5113	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5114	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5115	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5116	, VERR_INTERNAL_ERROR);
5117	if (GCPhysAddress != NIL_RTGCPHYS)
5118	{
5119	/*
5120	* Mapping the FIFO RAM.
5121	*/
5122	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5123	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5124	AssertRC(rc);
5125
5126	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5127	if (RT_SUCCESS(rc))
5128	{
5129	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5130	# ifdef DEBUG_FIFO_ACCESS
5131	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5132	# else
5133	GCPhysAddress + PAGE_SIZE - 1,
5134	# endif
5135	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5136	"VMSVGA FIFO");
5137	AssertRC(rc);
5138	}
5139	# endif
5140	if (RT_SUCCESS(rc))
5141	{
5142	pThis->svga.GCPhysFIFO = GCPhysAddress;
5143	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5144	}
5145	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5146	}
5147	else
5148	{
5149	Assert(pThis->svga.GCPhysFIFO);
5150	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5151	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5152	AssertRC(rc);
5153	# else
5154	rc = VINF_SUCCESS;
5155	# endif
5156	pThis->svga.GCPhysFIFO = 0;
5157	}
5158	return rc;
5159	}
5160
5161	# ifdef VBOX_WITH_VMSVGA3D
5162
5163	/**
5164	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5165	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5166	*
5167	* @param pDevIns The device instance.
5168	* @param pThis The The shared VGA/VMSVGA instance data.
5169	* @param pThisCC The VGA/VMSVGA state for ring-3.
5170	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5171	* UINT32_MAX is used, all surfaces are processed.
5172	*/
5173	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5174	{
5175	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5176	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5177	}
5178
5179
5180	/**
5181	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5182	*/
5183	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5184	{
5185	/* There might be a specific surface ID at the start of the
5186	arguments, if not show all surfaces. */
5187	uint32_t sid = UINT32_MAX;
5188	if (pszArgs)
5189	pszArgs = RTStrStripL(pszArgs);
5190	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5191	sid = RTStrToUInt32(pszArgs);
5192
5193	/* Verbose or terse display, we default to verbose. */
5194	bool fVerbose = true;
5195	if (RTStrIStr(pszArgs, "terse"))
5196	fVerbose = false;
5197
5198	/* The size of the ascii art (x direction, y is 3/4 of x). */
5199	uint32_t cxAscii = 80;
5200	if (RTStrIStr(pszArgs, "gigantic"))
5201	cxAscii = 300;
5202	else if (RTStrIStr(pszArgs, "huge"))
5203	cxAscii = 180;
5204	else if (RTStrIStr(pszArgs, "big"))
5205	cxAscii = 132;
5206	else if (RTStrIStr(pszArgs, "normal"))
5207	cxAscii = 80;
5208	else if (RTStrIStr(pszArgs, "medium"))
5209	cxAscii = 64;
5210	else if (RTStrIStr(pszArgs, "small"))
5211	cxAscii = 48;
5212	else if (RTStrIStr(pszArgs, "tiny"))
5213	cxAscii = 24;
5214
5215	/* Y invert the image when producing the ASCII art. */
5216	bool fInvY = false;
5217	if (RTStrIStr(pszArgs, "invy"))
5218	fInvY = true;
5219
5220	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5221	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5222	}
5223
5224
5225	/**
5226	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5227	*/
5228	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5229	{
5230	/* pszArg = "sid[>dir]"
5231	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5232	*/
5233	char *pszBitmapPath = NULL;
5234	uint32_t sid = UINT32_MAX;
5235	if (pszArgs)
5236	pszArgs = RTStrStripL(pszArgs);
5237	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5238	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5239	if ( pszBitmapPath
5240	&& *pszBitmapPath == '>')
5241	++pszBitmapPath;
5242
5243	const bool fVerbose = true;
5244	const uint32_t cxAscii = 0; /* No ASCII */
5245	const bool fInvY = false; /* Do not invert. */
5246	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5247	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5248	}
5249
5250	/**
5251	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5252	*/
5253	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5254	{
5255	/* There might be a specific surface ID at the start of the
5256	arguments, if not show all contexts. */
5257	uint32_t sid = UINT32_MAX;
5258	if (pszArgs)
5259	pszArgs = RTStrStripL(pszArgs);
5260	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5261	sid = RTStrToUInt32(pszArgs);
5262
5263	/* Verbose or terse display, we default to verbose. */
5264	bool fVerbose = true;
5265	if (RTStrIStr(pszArgs, "terse"))
5266	fVerbose = false;
5267
5268	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5269	}
5270	# endif /* VBOX_WITH_VMSVGA3D */
5271
5272	/**
5273	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5274	*/
5275	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5276	{
5277	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5278	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5279	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5280	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5281	RT_NOREF(pszArgs);
5282
5283	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5284	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5285	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5286	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5287	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5288	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5289	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5290	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5291	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5292	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5293	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5294	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5295	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5296	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5297	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5298	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5299	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5300	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5301	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5302	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5303	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5304	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5305	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5306	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5307	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5308
5309	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5310	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5311	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5312	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5313
5314	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5315	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5316
5317	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5318	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5319
5320	# ifdef VBOX_WITH_VMSVGA3D
5321	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5322	# endif
5323	if (pThisCC->pDrv)
5324	{
5325	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5326	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5327	}
5328
5329	/* Dump screen information. */
5330	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5331	{
5332	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5333	if (pScreen)
5334	{
5335	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5336	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5337	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5338	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5339	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5340	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5341	{
5342	pHlp->pfnPrintf(pHlp, " (");
5343	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5344	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5345	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5346	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5347	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5348	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5349	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5350	pHlp->pfnPrintf(pHlp, " BLANKING");
5351	pHlp->pfnPrintf(pHlp, " )");
5352	}
5353	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5354	}
5355	}
5356
5357	}
5358
5359	/**
5360	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5361	*/
5362	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5363	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5364	{
5365	RT_NOREF(uPass);
5366
5367	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5368	int rc;
5369
5370	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5371	{
5372	uint32_t cScreens = 0;
5373	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5374	AssertRCReturn(rc, rc);
5375	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5376	("cScreens=%#x\n", cScreens),
5377	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5378
5379	for (uint32_t i = 0; i < cScreens; ++i)
5380	{
5381	VMSVGASCREENOBJECT screen;
5382	RT_ZERO(screen);
5383
5384	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5385	AssertLogRelRCReturn(rc, rc);
5386
5387	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5388	{
5389	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5390	*pScreen = screen;
5391	pScreen->fModified = true;
5392	}
5393	else
5394	{
5395	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5396	}
5397	}
5398	}
5399	else
5400	{
5401	/* Try to setup at least the first screen. */
5402	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5403	pScreen->fDefined = true;
5404	pScreen->fModified = true;
5405	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5406	pScreen->idScreen = 0;
5407	pScreen->xOrigin = 0;
5408	pScreen->yOrigin = 0;
5409	pScreen->offVRAM = pThis->svga.uScreenOffset;
5410	pScreen->cbPitch = pThis->svga.cbScanline;
5411	pScreen->cWidth = pThis->svga.uWidth;
5412	pScreen->cHeight = pThis->svga.uHeight;
5413	pScreen->cBpp = pThis->svga.uBpp;
5414	}
5415
5416	return VINF_SUCCESS;
5417	}
5418
5419	/**
5420	* @copydoc FNSSMDEVLOADEXEC
5421	*/
5422	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5423	{
5424	RT_NOREF(uPass);
5425	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5426	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5427	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5428	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5429	int rc;
5430
5431	/* Load our part of the VGAState */
5432	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5433	AssertRCReturn(rc, rc);
5434
5435	/* Load the VGA framebuffer. */
5436	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5437	uint32_t cbVgaFramebuffer = _32K;
5438	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5439	{
5440	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5441	AssertRCReturn(rc, rc);
5442	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5443	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5444	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5445	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5446	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5447	}
5448	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5449	AssertRCReturn(rc, rc);
5450	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5451	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5452	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5453	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5454
5455	/* Load the VMSVGA state. */
5456	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5457	AssertRCReturn(rc, rc);
5458
5459	/* Load the active cursor bitmaps. */
5460	if (pSVGAState->Cursor.fActive)
5461	{
5462	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5463	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5464
5465	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5466	AssertRCReturn(rc, rc);
5467	}
5468
5469	/* Load the GMR state. */
5470	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5471	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5472	{
5473	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5474	AssertRCReturn(rc, rc);
5475	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5476	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5477	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5478	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5479	}
5480
5481	if (pThis->svga.cGMR != cGMR)
5482	{
5483	/* Reallocate GMR array. */
5484	Assert(pSVGAState->paGMR != NULL);
5485	RTMemFree(pSVGAState->paGMR);
5486	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5487	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5488	pThis->svga.cGMR = cGMR;
5489	}
5490
5491	for (uint32_t i = 0; i < cGMR; ++i)
5492	{
5493	PGMR pGMR = &pSVGAState->paGMR[i];
5494
5495	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5496	AssertRCReturn(rc, rc);
5497
5498	if (pGMR->numDescriptors)
5499	{
5500	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5501	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5502	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5503
5504	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5505	{
5506	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5507	AssertRCReturn(rc, rc);
5508	}
5509	}
5510	}
5511
5512	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5513	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5514	# endif
5515
5516	VMSVGA_STATE_LOAD LoadState;
5517	LoadState.pSSM = pSSM;
5518	LoadState.uVersion = uVersion;
5519	LoadState.uPass = uPass;
5520	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5521	AssertLogRelRCReturn(rc, rc);
5522
5523	return VINF_SUCCESS;
5524	}
5525
5526	/**
5527	* Reinit the video mode after the state has been loaded.
5528	*/
5529	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5530	{
5531	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5532	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5533	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5534
5535	/* Set the active cursor. */
5536	if (pSVGAState->Cursor.fActive)
5537	{
5538	/* We don't store the alpha flag, but we can take a guess that if
5539	* the old register interface was used, the cursor was B&W.
5540	*/
5541	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5542
5543	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5544	true /fVisible/,
5545	fAlpha,
5546	pSVGAState->Cursor.xHotspot,
5547	pSVGAState->Cursor.yHotspot,
5548	pSVGAState->Cursor.width,
5549	pSVGAState->Cursor.height,
5550	pSVGAState->Cursor.pData);
5551	AssertRC(rc);
5552
5553	if (pThis->svga.uCursorOn)
5554	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5555	}
5556
5557	/* If the VRAM handler should not be registered, we have to explicitly
5558	* unregister it here!
5559	*/
5560	if (!pThis->svga.fVRAMTracking)
5561	{
5562	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5563	}
5564
5565	/* Let the FIFO thread deal with changing the mode. */
5566	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5567
5568	return VINF_SUCCESS;
5569	}
5570
5571	/**
5572	* Portion of SVGA state which must be saved in the FIFO thread.
5573	*/
5574	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5575	{
5576	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5577	int rc;
5578
5579	/* Save the screen objects. */
5580	/* Count defined screen object. */
5581	uint32_t cScreens = 0;
5582	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5583	{
5584	if (pSVGAState->aScreens[i].fDefined)
5585	++cScreens;
5586	}
5587
5588	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5589	AssertLogRelRCReturn(rc, rc);
5590
5591	for (uint32_t i = 0; i < cScreens; ++i)
5592	{
5593	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5594
5595	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5596	AssertLogRelRCReturn(rc, rc);
5597	}
5598	return VINF_SUCCESS;
5599	}
5600
5601	/**
5602	* @copydoc FNSSMDEVSAVEEXEC
5603	*/
5604	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5605	{
5606	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5607	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5608	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5609	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5610	int rc;
5611
5612	/* Save our part of the VGAState */
5613	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5614	AssertLogRelRCReturn(rc, rc);
5615
5616	/* Save the framebuffer backup. */
5617	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5618	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5619	AssertLogRelRCReturn(rc, rc);
5620
5621	/* Save the VMSVGA state. */
5622	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5623	AssertLogRelRCReturn(rc, rc);
5624
5625	/* Save the active cursor bitmaps. */
5626	if (pSVGAState->Cursor.fActive)
5627	{
5628	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5629	AssertLogRelRCReturn(rc, rc);
5630	}
5631
5632	/* Save the GMR state */
5633	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5634	AssertLogRelRCReturn(rc, rc);
5635	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5636	{
5637	PGMR pGMR = &pSVGAState->paGMR[i];
5638
5639	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5640	AssertLogRelRCReturn(rc, rc);
5641
5642	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5643	{
5644	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5645	AssertLogRelRCReturn(rc, rc);
5646	}
5647	}
5648
5649	/*
5650	* Must save some state (3D in particular) in the FIFO thread.
5651	*/
5652	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5653	AssertLogRelRCReturn(rc, rc);
5654
5655	return VINF_SUCCESS;
5656	}
5657
5658	/**
5659	* Destructor for PVMSVGAR3STATE structure.
5660	*
5661	* @param pThis The shared VGA/VMSVGA instance data.
5662	* @param pSVGAState Pointer to the structure. It is not deallocated.
5663	*/
5664	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5665	{
5666	# ifndef VMSVGA_USE_EMT_HALT_CODE
5667	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5668	{
5669	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5670	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5671	}
5672	# endif
5673
5674	if (pSVGAState->Cursor.fActive)
5675	{
5676	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5677	pSVGAState->Cursor.pData = NULL;
5678	pSVGAState->Cursor.fActive = false;
5679	}
5680
5681	if (pSVGAState->paGMR)
5682	{
5683	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5684	if (pSVGAState->paGMR[i].paDesc)
5685	RTMemFree(pSVGAState->paGMR[i].paDesc);
5686
5687	RTMemFree(pSVGAState->paGMR);
5688	pSVGAState->paGMR = NULL;
5689	}
5690
5691	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
5692	{
5693	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
5694	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
5695	{
5696	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
5697	pSVGAState->apCmdBufCtxs[i] = NULL;
5698	}
5699	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
5700	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
5701	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
5702	}
5703
5704	# ifdef VBOX_WITH_VMSVGA3D
5705	RTMemFree(pSVGAState->pFuncsMap);
5706	pSVGAState->pFuncsMap = NULL;
5707	RTMemFree(pSVGAState->pFuncsGBO);
5708	pSVGAState->pFuncsGBO = NULL;
5709	RTMemFree(pSVGAState->pFuncsDX);
5710	pSVGAState->pFuncsDX = NULL;
5711	# endif
5712	}
5713
5714	/**
5715	* Constructor for PVMSVGAR3STATE structure.
5716	*
5717	* @returns VBox status code.
5718	* @param pDevIns The PDM device instance.
5719	* @param pThis The shared VGA/VMSVGA instance data.
5720	* @param pSVGAState Pointer to the structure. It is already allocated.
5721	*/
5722	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5723	{
5724	int rc = VINF_SUCCESS;
5725
5726	pSVGAState->pDevIns = pDevIns;
5727
5728	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5729	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5730
5731	# ifndef VMSVGA_USE_EMT_HALT_CODE
5732	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5733	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5734	AssertRCReturn(rc, rc);
5735	# endif
5736
5737	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
5738	AssertRCReturn(rc, rc);
5739
5740	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
5741
5742	RTListInit(&pSVGAState->MOBLRUList);
5743	return rc;
5744	}
5745
5746	# ifdef VBOX_WITH_VMSVGA3D
5747	/**
5748	* Initializes the optional host 3D backend interfaces.
5749	*
5750	* @returns VBox status code.
5751	* @param pThisCC The VGA/VMSVGA state for ring-3.
5752	*/
5753	static int vmsvgaR3Init3dInterfaces(PVGASTATECC pThisCC)
5754	{
5755	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5756
5757	int rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_DX, NULL, sizeof(VMSVGA3DBACKENDFUNCSDX));
5758	if (RT_SUCCESS(rc))
5759	{
5760	pSVGAState->pFuncsDX = (VMSVGA3DBACKENDFUNCSDX *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSDX));
5761	AssertReturn(pSVGAState->pFuncsDX, VERR_NO_MEMORY);
5762
5763	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_DX, pSVGAState->pFuncsDX, sizeof(VMSVGA3DBACKENDFUNCSDX));
5764	}
5765
5766	rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_MAP, NULL, sizeof(VMSVGA3DBACKENDFUNCSMAP));
5767	if (RT_SUCCESS(rc))
5768	{
5769	pSVGAState->pFuncsMap = (VMSVGA3DBACKENDFUNCSMAP *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSMAP));
5770	AssertReturn(pSVGAState->pFuncsMap, VERR_NO_MEMORY);
5771
5772	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_MAP, pSVGAState->pFuncsMap, sizeof(VMSVGA3DBACKENDFUNCSMAP));
5773	}
5774
5775	rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_GBO, NULL, sizeof(VMSVGA3DBACKENDFUNCSGBO));
5776	if (RT_SUCCESS(rc))
5777	{
5778	pSVGAState->pFuncsGBO = (VMSVGA3DBACKENDFUNCSGBO *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSGBO));
5779	AssertReturn(pSVGAState->pFuncsGBO, VERR_NO_MEMORY);
5780
5781	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_GBO, pSVGAState->pFuncsGBO, sizeof(VMSVGA3DBACKENDFUNCSGBO));
5782	}
5783
5784	return VINF_SUCCESS;
5785	}
5786	# endif
5787
5788	/**
5789	* Initializes the host capabilities: device and FIFO.
5790	*
5791	* @returns VBox status code.
5792	* @param pThis The shared VGA/VMSVGA instance data.
5793	* @param pThisCC The VGA/VMSVGA state for ring-3.
5794	*/
5795	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5796	{
5797	/* Device caps. */
5798	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
5799	\| SVGA_CAP_GMR2
5800	\| SVGA_CAP_CURSOR
5801	\| SVGA_CAP_CURSOR_BYPASS
5802	\| SVGA_CAP_CURSOR_BYPASS_2
5803	\| SVGA_CAP_EXTENDED_FIFO
5804	\| SVGA_CAP_IRQMASK
5805	\| SVGA_CAP_PITCHLOCK
5806	\| SVGA_CAP_RECT_COPY
5807	\| SVGA_CAP_TRACES
5808	\| SVGA_CAP_SCREEN_OBJECT_2
5809	\| SVGA_CAP_ALPHA_CURSOR;
5810
5811	/* VGPU10 capabilities. */
5812	if (pThis->fVMSVGA10)
5813	{
5814	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
5815	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
5816	;
5817
5818	# ifdef VBOX_WITH_VMSVGA3D
5819	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5820	if (pSVGAState->pFuncsGBO)
5821	pThis->svga.u32DeviceCaps \|= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
5822	if (pSVGAState->pFuncsDX)
5823	pThis->svga.u32DeviceCaps \|= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
5824	# endif
5825	}
5826
5827	# ifdef VBOX_WITH_VMSVGA3D
5828	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
5829	# endif
5830
5831	/* Clear the FIFO. */
5832	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5833
5834	/* Setup FIFO capabilities. */
5835	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5836	\| SVGA_FIFO_CAP_PITCHLOCK
5837	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5838	\| SVGA_FIFO_CAP_RESERVE
5839	\| SVGA_FIFO_CAP_GMR2
5840	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5841	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5842
5843	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5844	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5845	}
5846
5847	# ifdef VBOX_WITH_VMSVGA3D
5848	/**
5849	* Initializes the host 3D capabilities and writes them to FIFO memory.
5850	*
5851	* @returns VBox status code.
5852	* @param pThis The shared VGA/VMSVGA instance data.
5853	* @param pThisCC The VGA/VMSVGA state for ring-3.
5854	*/
5855	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5856	{
5857	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
5858	bool const fSavedBuffering = RTLogRelSetBuffering(true);
5859
5860	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
5861	{
5862	uint32_t val = 0;
5863	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
5864	if (RT_SUCCESS(rc))
5865	pThis->svga.au32DevCaps[i] = val;
5866	else
5867	pThis->svga.au32DevCaps[i] = 0;
5868
5869	/* LogRel the capability value. */
5870	if (i < SVGA3D_DEVCAP_MAX)
5871	{
5872	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
5873	if (RT_SUCCESS(rc))
5874	{
5875	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
5876	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
5877	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
5878	{
5879	float const fval = (float )&val;
5880	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
5881	}
5882	else
5883	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
5884	}
5885	else
5886	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
5887	}
5888	else
5889	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
5890	}
5891
5892	RTLogRelSetBuffering(fSavedBuffering);
5893
5894	/* 3d hardware version; latest and greatest */
5895	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5896	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5897
5898	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
5899	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
5900	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
5901	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
5902	*/
5903	SVGA3dCapsRecord *pCaps;
5904	SVGA3dCapPair *pData;
5905
5906	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
5907	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5908	pData = (SVGA3dCapPair *)&pCaps->data;
5909
5910	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
5911	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
5912	{
5913	pData[i][0] = i;
5914	pData[i][1] = pThis->svga.au32DevCaps[i];
5915	}
5916	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5917	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5918
5919	/* Mark end of record array (a zero word). */
5920	pCaps->header.length = 0;
5921	}
5922
5923	# endif
5924
5925	/**
5926	* Resets the SVGA hardware state
5927	*
5928	* @returns VBox status code.
5929	* @param pDevIns The device instance.
5930	*/
5931	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
5932	{
5933	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5934	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5935	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5936
5937	/* Reset before init? */
5938	if (!pSVGAState)
5939	return VINF_SUCCESS;
5940
5941	Log(("vmsvgaR3Reset\n"));
5942
5943	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5944	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5945	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5946
5947	/* Reset other stuff. */
5948	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5949	RT_ZERO(pThis->svga.au32ScratchRegion);
5950
5951	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
5952
5953	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
5954	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
5955
5956	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5957
5958	# ifdef VBOX_WITH_VMSVGA3D
5959	/* Device capabilities depend on this. */
5960	if (pThis->svga.f3DEnabled)
5961	vmsvgaR3Init3dInterfaces(pThisCC);
5962	# endif
5963
5964	/* Initialize FIFO and register capabilities. */
5965	vmsvgaR3InitCaps(pThis, pThisCC);
5966
5967	# ifdef VBOX_WITH_VMSVGA3D
5968	if (pThis->svga.f3DEnabled)
5969	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
5970	# endif
5971
5972	/* VRAM tracking is enabled by default during bootup. */
5973	pThis->svga.fVRAMTracking = true;
5974	pThis->svga.fEnabled = false;
5975
5976	/* Invalidate current settings. */
5977	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5978	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5979	pThis->svga.uBpp = pThis->svga.uHostBpp;
5980	pThis->svga.cbScanline = 0;
5981	pThis->svga.u32PitchLock = 0;
5982
5983	return rc;
5984	}
5985
5986	/**
5987	* Cleans up the SVGA hardware state
5988	*
5989	* @returns VBox status code.
5990	* @param pDevIns The device instance.
5991	*/
5992	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
5993	{
5994	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5995	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5996
5997	/*
5998	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5999	*/
6000	if (pThisCC->svga.pFIFOIOThread)
6001	{
6002	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6003	NULL /pvParam/, 30000 /ms/);
6004	AssertLogRelRC(rc);
6005
6006	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6007	AssertLogRelRC(rc);
6008	pThisCC->svga.pFIFOIOThread = NULL;
6009	}
6010
6011	/*
6012	* Destroy the special SVGA state.
6013	*/
6014	if (pThisCC->svga.pSvgaR3State)
6015	{
6016	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6017
6018	RTMemFree(pThisCC->svga.pSvgaR3State);
6019	pThisCC->svga.pSvgaR3State = NULL;
6020	}
6021
6022	/*
6023	* Free our resources residing in the VGA state.
6024	*/
6025	if (pThisCC->svga.pbVgaFrameBufferR3)
6026	{
6027	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6028	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6029	}
6030	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6031	{
6032	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6033	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6034	}
6035	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6036	{
6037	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6038	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6039	}
6040
6041	return VINF_SUCCESS;
6042	}
6043
6044	/**
6045	* Initialize the SVGA hardware state
6046	*
6047	* @returns VBox status code.
6048	* @param pDevIns The device instance.
6049	*/
6050	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6051	{
6052	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6053	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6054	PVMSVGAR3STATE pSVGAState;
6055	int rc;
6056
6057	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6058	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6059
6060	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6061
6062	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6063	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6064	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6065
6066	/* Create event semaphore. */
6067	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6068	AssertRCReturn(rc, rc);
6069
6070	/* Create event semaphore. */
6071	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6072	AssertRCReturn(rc, rc);
6073
6074	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6075	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6076
6077	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6078	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6079
6080	pSVGAState = pThisCC->svga.pSvgaR3State;
6081
6082	/* Register the write-protected GBO access handler type. */
6083	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6084	vmsvgaR3GboAccessHandler,
6085	NULL, NULL, NULL,
6086	NULL, NULL, NULL,
6087	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6088	AssertRCReturn(rc, rc);
6089
6090	# ifdef VBOX_WITH_VMSVGA3D
6091	if (pThis->svga.f3DEnabled)
6092	{
6093	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6094	if (RT_SUCCESS(rc))
6095	{
6096	/* Device capabilities depend on this. */
6097	vmsvgaR3Init3dInterfaces(pThisCC);
6098	}
6099	else
6100	{
6101	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6102	pThis->svga.f3DEnabled = false;
6103	}
6104	}
6105	# endif
6106
6107	/* Initialize FIFO and register capabilities. */
6108	vmsvgaR3InitCaps(pThis, pThisCC);
6109
6110	/* VRAM tracking is enabled by default during bootup. */
6111	pThis->svga.fVRAMTracking = true;
6112
6113	/* Set up the host bpp. This value is as a default for the programmable
6114	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6115	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6116	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6117	*
6118	* NB: The driver cBits value is currently constant for the lifetime of the
6119	* VM. If that changes, the host bpp logic might need revisiting.
6120	*/
6121	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6122
6123	/* Invalidate current settings. */
6124	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6125	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6126	pThis->svga.uBpp = pThis->svga.uHostBpp;
6127	pThis->svga.cbScanline = 0;
6128
6129	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6130	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6131	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6132	{
6133	pThis->svga.u32MaxWidth -= 256;
6134	pThis->svga.u32MaxHeight -= 256;
6135	}
6136	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6137
6138	# ifdef DEBUG_GMR_ACCESS
6139	/* Register the GMR access handler type. */
6140	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6141	vmsvgaR3GmrAccessHandler,
6142	NULL, NULL, NULL,
6143	NULL, NULL, NULL,
6144	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6145	AssertRCReturn(rc, rc);
6146	# endif
6147
6148	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6149	/* Register the FIFO access handler type. In addition to
6150	debugging FIFO access, this is also used to facilitate
6151	extended fifo thread sleeps. */
6152	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6153	# ifdef DEBUG_FIFO_ACCESS
6154	PGMPHYSHANDLERKIND_ALL,
6155	# else
6156	PGMPHYSHANDLERKIND_WRITE,
6157	# endif
6158	vmsvgaR3FifoAccessHandler,
6159	NULL, NULL, NULL,
6160	NULL, NULL, NULL,
6161	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6162	AssertRCReturn(rc, rc);
6163	# endif
6164
6165	/* Create the async IO thread. */
6166	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6167	RTTHREADTYPE_IO, "VMSVGA FIFO");
6168	if (RT_FAILURE(rc))
6169	{
6170	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6171	return rc;
6172	}
6173
6174	/*
6175	* Statistics.
6176	*/
6177	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6178	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6179	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6180	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6181	# ifdef VBOX_WITH_STATISTICS
6182	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6183	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6184	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6185	# endif
6186	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6187	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6188	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6189	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6190	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6191	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6192	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6193	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6194	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6195	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6196	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6197	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6198	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6199	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6200	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6201	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6202	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6203	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6204	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6205	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6206	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6207	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6208	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6209	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6210	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6211	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6212	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6213	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6214	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6215	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6216	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6217	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6218	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6219	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6220	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6221	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6222	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6223	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6224	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6225	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6226	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6227	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6228	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6229	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6230	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6231	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6232	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6233	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6234	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6235	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6236	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6237	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6238	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6239	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6240	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6241	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6242	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6243	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6244	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6245
6246	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6247	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6248	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6249	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6250	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6251	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6252	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6253	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6254	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6255	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6256	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6257	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6258	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6259	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6260	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6261	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6262	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6263	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6264	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6265	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6266	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6267	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6268	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6269	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6270	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6271	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6272	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6273	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6274	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6275	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6276	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6277	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6278	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6279	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6280	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6281	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6282	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6283	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6284	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6285	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6286
6287	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6288	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6289	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6290	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6291	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6292	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6293	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6294	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6295	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6296	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6297	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6298	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6299	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6300	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6301	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6302	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6303	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6304	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6305	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6306	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6307	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6308	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6309	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6310	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6311	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6312	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6313	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6314	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6315	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6316	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6317	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6318	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6319	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6320	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6321	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6322	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6323	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6324	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6325	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6326	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6327	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6328	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6329	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6330	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6331	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6332	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6333	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6334	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6335	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6336	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6337	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6338	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6339	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6340	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6341	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6342	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6343	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6344	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6345	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6346	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6347	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6348	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6349
6350	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6351	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6352	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6353	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6354	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6355	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6356	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6357	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6358	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6359	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6360	# endif
6361	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6362	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6363	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6364	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6365	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6366
6367	# undef REG_CNT
6368	# undef REG_PRF
6369
6370	/*
6371	* Info handlers.
6372	*/
6373	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6374	# ifdef VBOX_WITH_VMSVGA3D
6375	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6376	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6377	"VMSVGA 3d surface details. "
6378	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6379	vmsvgaR3Info3dSurface);
6380	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6381	"VMSVGA 3d surface details and bitmap: "
6382	"sid[>dir]",
6383	vmsvgaR3Info3dSurfaceBmp);
6384	# endif
6385
6386	return VINF_SUCCESS;
6387	}
6388
6389	/**
6390	* Power On notification.
6391	*
6392	* @returns VBox status code.
6393	* @param pDevIns The device instance data.
6394	*
6395	* @remarks Caller enters the device critical section.
6396	*/
6397	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6398	{
6399	# ifdef VBOX_WITH_VMSVGA3D
6400	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6401	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6402	if (pThis->svga.f3DEnabled)
6403	{
6404	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6405	if (RT_SUCCESS(rc))
6406	{
6407	/* Initialize FIFO 3D capabilities. */
6408	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6409	}
6410	}
6411	# else /* !VBOX_WITH_VMSVGA3D */
6412	RT_NOREF(pDevIns);
6413	# endif /* !VBOX_WITH_VMSVGA3D */
6414	}
6415
6416	/**
6417	* Power Off notification.
6418	*
6419	* @param pDevIns The device instance data.
6420	*
6421	* @remarks Caller enters the device critical section.
6422	*/
6423	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6424	{
6425	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6426	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6427
6428	/*
6429	* Notify the FIFO thread.
6430	*/
6431	if (pThisCC->svga.pFIFOIOThread)
6432	{
6433	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6434	NULL /pvParam/, 30000 /ms/);
6435	AssertLogRelRC(rc);
6436	}
6437	}
6438
6439	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 86905

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