DevVGA-SVGA.cpp@ 86237

最後變更在這個檔案從86237是 86237,由 vboxsync 提交於 4 年前
Devices/Graphics: stubs for SVGA_CAP_GBOBJECTS commands. Make sure that SVGA structures are properly packed.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 380.0 KB

行
1	/* $Id: DevVGA-SVGA.cpp 86237 2020-09-23 13:00:37Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.alldomusa.eu.org. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#define VMSVGA_USE_EMT_HALT_CODE
133	#include <VBox/vmm/pdmdev.h>
134	#include <VBox/version.h>
135	#include <VBox/err.h>
136	#include <VBox/log.h>
137	#include <VBox/vmm/pgm.h>
138	#ifdef VMSVGA_USE_EMT_HALT_CODE
139	# include <VBox/vmm/vmapi.h>
140	# include <VBox/vmm/vmcpuset.h>
141	#endif
142	#include <VBox/sup.h>
143
144	#include <iprt/assert.h>
145	#include <iprt/semaphore.h>
146	#include <iprt/uuid.h>
147	#ifdef IN_RING3
148	# include <iprt/ctype.h>
149	# include <iprt/mem.h>
150	# ifdef VBOX_STRICT
151	# include <iprt/time.h>
152	# endif
153	#endif
154
155	#include <VBox/AssertGuest.h>
156	#include <VBox/VMMDev.h>
157	#include <VBoxVideo.h>
158	#include <VBox/bioslogo.h>
159
160	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
161	#include "DevVGA.h"
162
163	#include "DevVGA-SVGA.h"
164	#ifdef VBOX_WITH_VMSVGA3D
165	# include "DevVGA-SVGA3d.h"
166	# ifdef RT_OS_DARWIN
167	# include "DevVGA-SVGA3d-cocoa.h"
168	# endif
169	# ifdef RT_OS_LINUX
170	# ifdef IN_RING3
171	#include "DevVGA-SVGA3d-glLdr.h"
172	# endif
173	# endif
174	#endif
175
176
177	/*********************************************************************************************************************************
178	* Defined Constants And Macros *
179	*********************************************************************************************************************************/
180	/**
181	* Macro for checking if a fixed FIFO register is valid according to the
182	* current FIFO configuration.
183	*
184	* @returns true / false.
185	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
186	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
187	*/
188	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
189
190
191	/*********************************************************************************************************************************
192	* Structures and Typedefs *
193	*********************************************************************************************************************************/
194	/**
195	* 64-bit GMR descriptor.
196	*/
197	typedef struct
198	{
199	RTGCPHYS GCPhys;
200	uint64_t numPages;
201	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
202
203	/**
204	* GMR slot
205	*/
206	typedef struct
207	{
208	uint32_t cMaxPages;
209	uint32_t cbTotal;
210	uint32_t numDescriptors;
211	PVMSVGAGMRDESCRIPTOR paDesc;
212	} GMR, *PGMR;
213
214	#ifdef IN_RING3
215	typedef struct VMSVGACMDBUF *PVMSVGACMDBUF;
216	typedef struct VMSVGACMDBUFCTX *PVMSVGACMDBUFCTX;
217
218	/* Command buffer. */
219	typedef struct VMSVGACMDBUF
220	{
221	RTLISTNODE nodeBuffer;
222	/* Context of the buffer. */
223	PVMSVGACMDBUFCTX pCmdBufCtx;
224	/* PA of the buffer. */
225	RTGCPHYS GCPhysCB;
226	/* A copy of the buffer header. */
227	SVGACBHeader hdr;
228	/* A copy of the commands. Size of the memory buffer is hdr.length */
229	void *pvCommands;
230	} VMSVGACMDBUF;
231
232	/* Command buffer context. */
233	typedef struct VMSVGACMDBUFCTX
234	{
235	/* Buffers submitted to processing for the FIFO thread. */
236	RTLISTANCHOR listSubmitted;
237	/* How many buffers in the queue. */
238	uint32_t cSubmitted;
239	} VMSVGACMDBUFCTX;
240
241	/**
242	* Internal SVGA ring-3 only state.
243	*/
244	typedef struct VMSVGAR3STATE
245	{
246	GMR *paGMR; // [VMSVGAState::cGMR]
247	struct
248	{
249	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
250	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
251	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
252	} GMRFB;
253	struct
254	{
255	bool fActive;
256	uint32_t xHotspot;
257	uint32_t yHotspot;
258	uint32_t width;
259	uint32_t height;
260	uint32_t cbData;
261	void *pData;
262	} Cursor;
263	SVGAColorBGRX colorAnnotation;
264
265	# ifdef VMSVGA_USE_EMT_HALT_CODE
266	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
267	uint32_t volatile cBusyDelayedEmts;
268	/** Set of EMTs that are */
269	VMCPUSET BusyDelayedEmts;
270	# else
271	/** Number of EMTs waiting on hBusyDelayedEmts. */
272	uint32_t volatile cBusyDelayedEmts;
273	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
274	* busy (ugly). */
275	RTSEMEVENTMULTI hBusyDelayedEmts;
276	# endif
277
278	/** Information about screens. */
279	VMSVGASCREENOBJECT aScreens[64];
280
281	/** Command buffer contexts. */
282	PVMSVGACMDBUFCTX apCmdBufCtxs[SVGA_CB_CONTEXT_MAX];
283	/** The special Device Context for synchronous commands. */
284	VMSVGACMDBUFCTX CmdBufCtxDC;
285	/** Flag which indicates that there are buffers to be processed. */
286	uint32_t volatile fCmdBuf;
287	/** Critical section for accessing the command buffer data. */
288	RTCRITSECT CritSectCmdBuf;
289
290	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
291	STAMPROFILE StatBusyDelayEmts;
292
293	STAMPROFILE StatR3Cmd3dPresentProf;
294	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
295	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
296	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
297	STAMCOUNTER StatR3CmdDefineGmr2;
298	STAMCOUNTER StatR3CmdDefineGmr2Free;
299	STAMCOUNTER StatR3CmdDefineGmr2Modify;
300	STAMCOUNTER StatR3CmdRemapGmr2;
301	STAMCOUNTER StatR3CmdRemapGmr2Modify;
302	STAMCOUNTER StatR3CmdInvalidCmd;
303	STAMCOUNTER StatR3CmdFence;
304	STAMCOUNTER StatR3CmdUpdate;
305	STAMCOUNTER StatR3CmdUpdateVerbose;
306	STAMCOUNTER StatR3CmdDefineCursor;
307	STAMCOUNTER StatR3CmdDefineAlphaCursor;
308	STAMCOUNTER StatR3CmdMoveCursor;
309	STAMCOUNTER StatR3CmdDisplayCursor;
310	STAMCOUNTER StatR3CmdRectFill;
311	STAMCOUNTER StatR3CmdRectCopy;
312	STAMCOUNTER StatR3CmdRectRopCopy;
313	STAMCOUNTER StatR3CmdEscape;
314	STAMCOUNTER StatR3CmdDefineScreen;
315	STAMCOUNTER StatR3CmdDestroyScreen;
316	STAMCOUNTER StatR3CmdDefineGmrFb;
317	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
318	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
319	STAMCOUNTER StatR3CmdAnnotationFill;
320	STAMCOUNTER StatR3CmdAnnotationCopy;
321	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
322	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
323	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
324	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
325	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
326	STAMCOUNTER StatR3Cmd3dSurfaceDma;
327	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
328	STAMCOUNTER StatR3Cmd3dContextDefine;
329	STAMCOUNTER StatR3Cmd3dContextDestroy;
330	STAMCOUNTER StatR3Cmd3dSetTransform;
331	STAMCOUNTER StatR3Cmd3dSetZRange;
332	STAMCOUNTER StatR3Cmd3dSetRenderState;
333	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
334	STAMCOUNTER StatR3Cmd3dSetTextureState;
335	STAMCOUNTER StatR3Cmd3dSetMaterial;
336	STAMCOUNTER StatR3Cmd3dSetLightData;
337	STAMCOUNTER StatR3Cmd3dSetLightEnable;
338	STAMCOUNTER StatR3Cmd3dSetViewPort;
339	STAMCOUNTER StatR3Cmd3dSetClipPlane;
340	STAMCOUNTER StatR3Cmd3dClear;
341	STAMCOUNTER StatR3Cmd3dPresent;
342	STAMCOUNTER StatR3Cmd3dPresentReadBack;
343	STAMCOUNTER StatR3Cmd3dShaderDefine;
344	STAMCOUNTER StatR3Cmd3dShaderDestroy;
345	STAMCOUNTER StatR3Cmd3dSetShader;
346	STAMCOUNTER StatR3Cmd3dSetShaderConst;
347	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
348	STAMCOUNTER StatR3Cmd3dSetScissorRect;
349	STAMCOUNTER StatR3Cmd3dBeginQuery;
350	STAMCOUNTER StatR3Cmd3dEndQuery;
351	STAMCOUNTER StatR3Cmd3dWaitForQuery;
352	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
353	STAMCOUNTER StatR3Cmd3dActivateSurface;
354	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
355
356	STAMCOUNTER StatR3RegConfigDoneWr;
357	STAMCOUNTER StatR3RegGmrDescriptorWr;
358	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
359	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
360
361	STAMCOUNTER StatFifoCommands;
362	STAMCOUNTER StatFifoErrors;
363	STAMCOUNTER StatFifoUnkCmds;
364	STAMCOUNTER StatFifoTodoTimeout;
365	STAMCOUNTER StatFifoTodoWoken;
366	STAMPROFILE StatFifoStalls;
367	STAMPROFILE StatFifoExtendedSleep;
368	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
369	STAMCOUNTER StatFifoAccessHandler;
370	# endif
371	STAMCOUNTER StatFifoCursorFetchAgain;
372	STAMCOUNTER StatFifoCursorNoChange;
373	STAMCOUNTER StatFifoCursorPosition;
374	STAMCOUNTER StatFifoCursorVisiblity;
375	STAMCOUNTER StatFifoWatchdogWakeUps;
376	} VMSVGAR3STATE, *PVMSVGAR3STATE;
377	#endif /* IN_RING3 */
378
379
380	/*********************************************************************************************************************************
381	* Internal Functions *
382	*********************************************************************************************************************************/
383	#ifdef IN_RING3
384	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
385	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
386	# endif
387	# ifdef DEBUG_GMR_ACCESS
388	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
389	# endif
390	#endif
391
392
393	/*********************************************************************************************************************************
394	* Global Variables *
395	*********************************************************************************************************************************/
396	#ifdef IN_RING3
397
398	/**
399	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
400	*/
401	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
402	{
403	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
404	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
405	SSMFIELD_ENTRY_TERM()
406	};
407
408	/**
409	* SSM descriptor table for the GMR structure.
410	*/
411	static SSMFIELD const g_aGMRFields[] =
412	{
413	SSMFIELD_ENTRY( GMR, cMaxPages),
414	SSMFIELD_ENTRY( GMR, cbTotal),
415	SSMFIELD_ENTRY( GMR, numDescriptors),
416	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
417	SSMFIELD_ENTRY_TERM()
418	};
419
420	/**
421	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
422	*/
423	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
424	{
425	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
426	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
427	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
428	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
429	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
430	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
431	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
432	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
433	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
434	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
435	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
436	SSMFIELD_ENTRY_TERM()
437	};
438
439	/**
440	* SSM descriptor table for the VMSVGAR3STATE structure.
441	*/
442	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
443	{
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
445	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
446	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
447	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
448	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
449	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
450	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
451	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
452	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
453	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
455	#ifdef VMSVGA_USE_EMT_HALT_CODE
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
457	#else
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
459	#endif
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
498	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
499	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
500	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
501	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
502	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
504	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
508	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
509	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
510	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
511	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
512	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
513	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
514	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
515	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
516	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
517	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
518	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
519	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
523
524	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
528
529	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
530	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
531	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
532	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
533	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
534	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
535	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
536	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
537	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
538	# endif
539	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
542	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
543
544	SSMFIELD_ENTRY_TERM()
545	};
546
547	/**
548	* SSM descriptor table for the VGAState.svga structure.
549	*/
550	static SSMFIELD const g_aVGAStateSVGAFields[] =
551	{
552	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
553	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
554	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
555	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
556	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
557	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
558	SSMFIELD_ENTRY( VMSVGAState, fBusy),
559	SSMFIELD_ENTRY( VMSVGAState, fTraces),
560	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
561	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
562	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
563	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
564	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
565	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
566	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
567	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
568	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
569	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
570	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
571	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
572	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
573	SSMFIELD_ENTRY( VMSVGAState, uWidth),
574	SSMFIELD_ENTRY( VMSVGAState, uHeight),
575	SSMFIELD_ENTRY( VMSVGAState, uBpp),
576	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
577	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
578	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
579	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
580	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
581	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
582	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
583	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
584	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
585	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
586	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
587	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
588	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
589	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
590	SSMFIELD_ENTRY_TERM()
591	};
592	#endif /* IN_RING3 */
593
594
595	/*********************************************************************************************************************************
596	* Internal Functions *
597	*********************************************************************************************************************************/
598	#ifdef IN_RING3
599	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
600	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
601	uint32_t uVersion, uint32_t uPass);
602	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
603	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
604	# ifdef VBOX_WITH_VMSVGA3D
605	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
606	# endif /* VBOX_WITH_VMSVGA3D */
607	#endif /* IN_RING3 */
608
609
610
611	#ifdef IN_RING3
612	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
613	{
614	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
615	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
616	&& pSVGAState
617	&& pSVGAState->aScreens[idScreen].fDefined)
618	{
619	return &pSVGAState->aScreens[idScreen];
620	}
621	return NULL;
622	}
623
624	void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
625	{
626	# ifdef VBOX_WITH_VMSVGA3D
627	if (pThis->svga.f3DEnabled)
628	{
629	for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
630	{
631	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
632	if (pScreen)
633	vmsvga3dDestroyScreen(pThisCC, pScreen);
634	}
635	}
636	# else
637	RT_NOREF(pThis, pThisCC);
638	# endif
639	}
640	#endif /* IN_RING3 */
641
642	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
643
644	#ifdef LOG_ENABLED
645
646	/**
647	* Index register string name lookup
648	*
649	* @returns Index register string or "UNKNOWN"
650	* @param pThis The shared VGA/VMSVGA state.
651	* @param idxReg The index register.
652	*/
653	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
654	{
655	switch (idxReg)
656	{
657	SVGA_CASE_ID2STR(SVGA_REG_ID);
658	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
659	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
660	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
661	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
662	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
663	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
664	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
665	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
666	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
667	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
668	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
669	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
670	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
671	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
672	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
673	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
674
675	/* ID 0 implementation only had the above registers, then the palette */
676	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
677	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
678	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
679	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
680	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
681	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
682	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
683	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ID); /* (Deprecated) */
684	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
685	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
686	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
687	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
688	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
689	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
690	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
691	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
692	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
693
694	/* Legacy multi-monitor support */
695	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
696	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
697	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
698	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
699	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
700	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
701	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
702
703	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
704	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
705	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
706	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
707
708	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
709	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
710	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
711	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
712	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
713	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
714	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
715	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
716	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
717	SVGA_CASE_ID2STR(SVGA_REG_iCMD_PREPEND_HIGH);
718	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
719	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
720	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
721	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
722
723	default:
724	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
725	return "SVGA_SCRATCH_BASE reg";
726	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
727	return "SVGA_PALETTE_BASE reg";
728	return "UNKNOWN";
729	}
730	}
731
732	#ifdef IN_RING3
733	/**
734	* FIFO command name lookup
735	*
736	* @returns FIFO command string or "UNKNOWN"
737	* @param u32Cmd FIFO command
738	*/
739	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
740	{
741	switch (u32Cmd)
742	{
743	SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
744	SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
745	SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
746	SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
747	SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
748	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
749	SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
750	SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
751	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
752	SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
753	SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
754	SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
755	SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
756	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
757	SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
758	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
759	SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
760	SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
761	SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
762	SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
763	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
764	SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
765	SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
766	SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
767	SVGA_CASE_ID2STR(SVGA_CMD_NOP);
768	SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
769	SVGA_CASE_ID2STR(SVGA_CMD_MAX);
770	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
771	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
772	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
773	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
774	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
775	SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
776	SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
777	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
778	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
779	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
780	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
781	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
782	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
783	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
784	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
785	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
786	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
787	SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
788	SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
789	SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
790	SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
791	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
792	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
793	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
794	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
795	SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
796	SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
797	SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
798	SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
799	SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
800	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
801	SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
802	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_CREATE_DECODER);
803	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DESTROY_DECODER);
804	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR);
805	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR);
806	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_START_FRAME);
807	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_RENDER);
808	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_END_FRAME);
809	SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_PROCESS_FRAME);
810	SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
811	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
812	SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
813	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
814	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
815	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
816	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
817	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
818	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
819	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
820	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
821	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
822	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
823	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
824	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
825	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
826	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
827	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
828	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
829	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
830	SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
831	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
832	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
833	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
834	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
835	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
836	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
837	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
838	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
839	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
840	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
841	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
842	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
843	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
844	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
845	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
846	SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
847	SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
848	SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
849	SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
850	SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
851	SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
852	SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
853	SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
854	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
855	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
856	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
857	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
858	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
859	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
860	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
861	SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
862	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
863	SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
864	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
865	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
866	SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
867	SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
868	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
869	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
870	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
871	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
872	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
873	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
874	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
875	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
876	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
877	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
878	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
879	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
880	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
881	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
882	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
883	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
884	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
885	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
886	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
887	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
888	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
889	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
890	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
891	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
892	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
893	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
894	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
895	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
896	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
897	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
898	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
899	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
900	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
901	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
902	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
903	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
904	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
905	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
906	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
907	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
908	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
909	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
910	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_STRETCHBLT);
911	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
912	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
913	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
914	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
915	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
916	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
917	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
918	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
919	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
920	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
921	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
922	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
923	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
924	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
925	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
926	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
927	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
928	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
929	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
930	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
931	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
932	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
933	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
934	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
935	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
936	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
937	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
938	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
939	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
940	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
941	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
942	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
943	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
944	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
945	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
946	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
947	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
948	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
949	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
950	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
951	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
952	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
953	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED1);
954	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED2);
955	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED3);
956	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
957	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MAX);
958	default: return "UNKNOWN";
959	}
960	}
961	# endif /* IN_RING3 */
962
963	#endif /* LOG_ENABLED */
964	#ifdef IN_RING3
965
966	/**
967	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
968	*/
969	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
970	{
971	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
972	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
973
974	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
975	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
976
977	/** @todo Test how it interacts with multiple screen objects. */
978	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
979	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
980	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
981
982	if (x < uWidth)
983	{
984	pThis->svga.viewport.x = x;
985	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
986	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
987	}
988	else
989	{
990	pThis->svga.viewport.x = uWidth;
991	pThis->svga.viewport.cx = 0;
992	pThis->svga.viewport.xRight = uWidth;
993	}
994	if (y < uHeight)
995	{
996	pThis->svga.viewport.y = y;
997	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
998	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
999	pThis->svga.viewport.yHighWC = uHeight - y;
1000	}
1001	else
1002	{
1003	pThis->svga.viewport.y = uHeight;
1004	pThis->svga.viewport.cy = 0;
1005	pThis->svga.viewport.yLowWC = 0;
1006	pThis->svga.viewport.yHighWC = 0;
1007	}
1008
1009	# ifdef VBOX_WITH_VMSVGA3D
1010	/*
1011	* Now inform the 3D backend.
1012	*/
1013	if (pThis->svga.f3DEnabled)
1014	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
1015	# else
1016	RT_NOREF(OldViewport);
1017	# endif
1018	}
1019
1020
1021	/**
1022	* Updating screen information in API
1023	*
1024	* @param pThis The The shared VGA/VMSVGA instance data.
1025	* @param pThisCC The VGA/VMSVGA state for ring-3.
1026	*/
1027	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
1028	{
1029	int rc;
1030
1031	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1032
1033	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1034	{
1035	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1036	if (!pScreen->fModified)
1037	continue;
1038
1039	pScreen->fModified = false;
1040
1041	VBVAINFOVIEW view;
1042	RT_ZERO(view);
1043	view.u32ViewIndex = pScreen->idScreen;
1044	// view.u32ViewOffset = 0;
1045	view.u32ViewSize = pThis->vram_size;
1046	view.u32MaxScreenSize = pThis->vram_size;
1047
1048	VBVAINFOSCREEN screen;
1049	RT_ZERO(screen);
1050	screen.u32ViewIndex = pScreen->idScreen;
1051
1052	if (pScreen->fDefined)
1053	{
1054	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1055	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1056	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1057	{
1058	Assert(pThis->svga.fGFBRegisters);
1059	continue;
1060	}
1061
1062	screen.i32OriginX = pScreen->xOrigin;
1063	screen.i32OriginY = pScreen->yOrigin;
1064	screen.u32StartOffset = pScreen->offVRAM;
1065	screen.u32LineSize = pScreen->cbPitch;
1066	screen.u32Width = pScreen->cWidth;
1067	screen.u32Height = pScreen->cHeight;
1068	screen.u16BitsPerPixel = pScreen->cBpp;
1069	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1070	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1071	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1072	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1073	}
1074	else
1075	{
1076	/* Screen is destroyed. */
1077	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1078	}
1079
1080	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
1081	AssertRC(rc);
1082	}
1083	}
1084
1085
1086	/**
1087	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
1088	*
1089	* Used to update screen offsets (positions) since appearently vmwgfx fails to
1090	* pass correct offsets thru FIFO.
1091	*/
1092	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
1093	{
1094	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
1095	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
1096	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1097
1098	AssertReturnVoid(pSVGAState);
1099
1100	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
1101	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
1102	for (uint32_t i = 0; i < cPositions; ++i)
1103	{
1104	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
1105	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
1106	continue;
1107
1108	if (pSVGAState->aScreens[i].xOrigin == -1)
1109	continue;
1110	if (pSVGAState->aScreens[i].yOrigin == -1)
1111	continue;
1112
1113	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
1114	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
1115	pSVGAState->aScreens[i].fModified = true;
1116	}
1117
1118	vmsvgaR3VBVAResize(pThis, pThisCC);
1119	}
1120
1121	#endif /* IN_RING3 */
1122
1123	/**
1124	* Read port register
1125	*
1126	* @returns VBox status code.
1127	* @param pDevIns The device instance.
1128	* @param pThis The shared VGA/VMSVGA state.
1129	* @param pu32 Where to store the read value
1130	*/
1131	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
1132	{
1133	#ifdef IN_RING3
1134	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
1135	#endif
1136	int rc = VINF_SUCCESS;
1137	*pu32 = 0;
1138
1139	/* Rough index register validation. */
1140	uint32_t idxReg = pThis->svga.u32IndexReg;
1141	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1142	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1143	VINF_IOM_R3_IOPORT_READ);
1144	#else
1145	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1146	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1147	VINF_SUCCESS);
1148	#endif
1149	RT_UNTRUSTED_VALIDATED_FENCE();
1150
1151	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1152	if ( idxReg >= SVGA_REG_ID_0_TOP
1153	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1154	{
1155	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1156	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1157	}
1158
1159	switch (idxReg)
1160	{
1161	case SVGA_REG_ID:
1162	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1163	*pu32 = pThis->svga.u32SVGAId;
1164	break;
1165
1166	case SVGA_REG_ENABLE:
1167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1168	*pu32 = pThis->svga.fEnabled;
1169	break;
1170
1171	case SVGA_REG_WIDTH:
1172	{
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1174	if ( pThis->svga.fEnabled
1175	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1176	*pu32 = pThis->svga.uWidth;
1177	else
1178	{
1179	#ifndef IN_RING3
1180	rc = VINF_IOM_R3_IOPORT_READ;
1181	#else
1182	*pu32 = pThisCC->pDrv->cx;
1183	#endif
1184	}
1185	break;
1186	}
1187
1188	case SVGA_REG_HEIGHT:
1189	{
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1191	if ( pThis->svga.fEnabled
1192	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1193	*pu32 = pThis->svga.uHeight;
1194	else
1195	{
1196	#ifndef IN_RING3
1197	rc = VINF_IOM_R3_IOPORT_READ;
1198	#else
1199	*pu32 = pThisCC->pDrv->cy;
1200	#endif
1201	}
1202	break;
1203	}
1204
1205	case SVGA_REG_MAX_WIDTH:
1206	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1207	*pu32 = pThis->svga.u32MaxWidth;
1208	break;
1209
1210	case SVGA_REG_MAX_HEIGHT:
1211	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1212	*pu32 = pThis->svga.u32MaxHeight;
1213	break;
1214
1215	case SVGA_REG_DEPTH:
1216	/* This returns the color depth of the current mode. */
1217	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1218	switch (pThis->svga.uBpp)
1219	{
1220	case 15:
1221	case 16:
1222	case 24:
1223	*pu32 = pThis->svga.uBpp;
1224	break;
1225
1226	default:
1227	case 32:
1228	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1229	break;
1230	}
1231	break;
1232
1233	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1234	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1235	*pu32 = pThis->svga.uHostBpp;
1236	break;
1237
1238	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1239	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1240	*pu32 = pThis->svga.uBpp;
1241	break;
1242
1243	case SVGA_REG_PSEUDOCOLOR:
1244	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1245	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1246	break;
1247
1248	case SVGA_REG_RED_MASK:
1249	case SVGA_REG_GREEN_MASK:
1250	case SVGA_REG_BLUE_MASK:
1251	{
1252	uint32_t uBpp;
1253
1254	if (pThis->svga.fEnabled)
1255	uBpp = pThis->svga.uBpp;
1256	else
1257	uBpp = pThis->svga.uHostBpp;
1258
1259	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1260	switch (uBpp)
1261	{
1262	case 8:
1263	u32RedMask = 0x07;
1264	u32GreenMask = 0x38;
1265	u32BlueMask = 0xc0;
1266	break;
1267
1268	case 15:
1269	u32RedMask = 0x0000001f;
1270	u32GreenMask = 0x000003e0;
1271	u32BlueMask = 0x00007c00;
1272	break;
1273
1274	case 16:
1275	u32RedMask = 0x0000001f;
1276	u32GreenMask = 0x000007e0;
1277	u32BlueMask = 0x0000f800;
1278	break;
1279
1280	case 24:
1281	case 32:
1282	default:
1283	u32RedMask = 0x00ff0000;
1284	u32GreenMask = 0x0000ff00;
1285	u32BlueMask = 0x000000ff;
1286	break;
1287	}
1288	switch (idxReg)
1289	{
1290	case SVGA_REG_RED_MASK:
1291	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1292	*pu32 = u32RedMask;
1293	break;
1294
1295	case SVGA_REG_GREEN_MASK:
1296	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1297	*pu32 = u32GreenMask;
1298	break;
1299
1300	case SVGA_REG_BLUE_MASK:
1301	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1302	*pu32 = u32BlueMask;
1303	break;
1304	}
1305	break;
1306	}
1307
1308	case SVGA_REG_BYTES_PER_LINE:
1309	{
1310	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1311	if ( pThis->svga.fEnabled
1312	&& pThis->svga.cbScanline)
1313	*pu32 = pThis->svga.cbScanline;
1314	else
1315	{
1316	#ifndef IN_RING3
1317	rc = VINF_IOM_R3_IOPORT_READ;
1318	#else
1319	*pu32 = pThisCC->pDrv->cbScanline;
1320	#endif
1321	}
1322	break;
1323	}
1324
1325	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1326	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1327	*pu32 = pThis->vram_size;
1328	break;
1329
1330	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1332	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1333	*pu32 = pThis->GCPhysVRAM;
1334	break;
1335
1336	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1337	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1338	/* Always zero in our case. */
1339	*pu32 = 0;
1340	break;
1341
1342	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1343	{
1344	#ifndef IN_RING3
1345	rc = VINF_IOM_R3_IOPORT_READ;
1346	#else
1347	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1348
1349	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1350	if ( pThis->svga.fEnabled
1351	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1352	{
1353	/* Hardware enabled; return real framebuffer size .*/
1354	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1355	}
1356	else
1357	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1358
1359	pu32 = RT_MIN(pThis->vram_size, pu32);
1360	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1361	#endif
1362	break;
1363	}
1364
1365	case SVGA_REG_CAPABILITIES:
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1367	*pu32 = pThis->svga.u32DeviceCaps;
1368	break;
1369
1370	case SVGA_REG_MEM_START: /* FIFO start */
1371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1372	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1373	*pu32 = pThis->svga.GCPhysFIFO;
1374	break;
1375
1376	case SVGA_REG_MEM_SIZE: /* FIFO size */
1377	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1378	*pu32 = pThis->svga.cbFIFO;
1379	break;
1380
1381	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1382	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1383	*pu32 = pThis->svga.fConfigured;
1384	break;
1385
1386	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1387	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1388	*pu32 = 0;
1389	break;
1390
1391	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1392	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1393	if (pThis->svga.fBusy)
1394	{
1395	#ifndef IN_RING3
1396	/* Go to ring-3 and halt the CPU. */
1397	rc = VINF_IOM_R3_IOPORT_READ;
1398	RT_NOREF(pDevIns);
1399	break;
1400	#else
1401	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1402	/* The guest is basically doing a HLT via the device here, but with
1403	a special wake up condition on FIFO completion. */
1404	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1405	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1406	PVM pVM = PDMDevHlpGetVM(pDevIns);
1407	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1408	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1409	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1410	if (pThis->svga.fBusy)
1411	{
1412	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1413	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1414	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1415	}
1416	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1417	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1418	# else
1419
1420	/* Delay the EMT a bit so the FIFO and others can get some work done.
1421	This used to be a crude 50 ms sleep. The current code tries to be
1422	more efficient, but the consept is still very crude. */
1423	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1424	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1425	RTThreadYield();
1426	if (pThis->svga.fBusy)
1427	{
1428	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1429
1430	if (pThis->svga.fBusy && cRefs == 1)
1431	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1432	if (pThis->svga.fBusy)
1433	{
1434	/** @todo If this code is going to stay, we need to call into the halt/wait
1435	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1436	* suffer when the guest is polling on a busy FIFO. */
1437	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1438	if (cNsMaxWait >= RT_NS_100US)
1439	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1440	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1441	RT_MIN(cNsMaxWait, RT_NS_10MS));
1442	}
1443
1444	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1445	}
1446	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1447	# endif
1448	*pu32 = pThis->svga.fBusy != 0;
1449	#endif
1450	}
1451	else
1452	*pu32 = false;
1453	break;
1454
1455	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1456	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1457	*pu32 = pThis->svga.u32GuestId;
1458	break;
1459
1460	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1461	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1462	*pu32 = pThis->svga.cScratchRegion;
1463	break;
1464
1465	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1466	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1467	*pu32 = SVGA_FIFO_NUM_REGS;
1468	break;
1469
1470	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1471	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1472	*pu32 = pThis->svga.u32PitchLock;
1473	break;
1474
1475	case SVGA_REG_IRQMASK: /* Interrupt mask */
1476	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1477	*pu32 = pThis->svga.u32IrqMask;
1478	break;
1479
1480	/* See "Guest memory regions" below. */
1481	case SVGA_REG_GMR_ID:
1482	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1483	*pu32 = pThis->svga.u32CurrentGMRId;
1484	break;
1485
1486	case SVGA_REG_GMR_DESCRIPTOR:
1487	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1488	/* Write only */
1489	*pu32 = 0;
1490	break;
1491
1492	case SVGA_REG_GMR_MAX_IDS:
1493	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1494	*pu32 = pThis->svga.cGMR;
1495	break;
1496
1497	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1498	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1499	*pu32 = VMSVGA_MAX_GMR_PAGES;
1500	break;
1501
1502	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1503	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1504	*pu32 = pThis->svga.fTraces;
1505	break;
1506
1507	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1508	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1509	*pu32 = VMSVGA_MAX_GMR_PAGES;
1510	break;
1511
1512	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1513	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1514	*pu32 = VMSVGA_SURFACE_SIZE;
1515	break;
1516
1517	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1518	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1519	break;
1520
1521	/* Mouse cursor support. */
1522	case SVGA_REG_CURSOR_ID:
1523	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1524	*pu32 = pThis->svga.uCursorID;
1525	break;
1526
1527	case SVGA_REG_CURSOR_X:
1528	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1529	*pu32 = pThis->svga.uCursorX;
1530	break;
1531
1532	case SVGA_REG_CURSOR_Y:
1533	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1534	*pu32 = pThis->svga.uCursorY;
1535	break;
1536
1537	case SVGA_REG_CURSOR_ON:
1538	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1539	*pu32 = pThis->svga.uCursorOn;
1540	break;
1541
1542	/* Legacy multi-monitor support */
1543	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1544	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1545	*pu32 = 1;
1546	break;
1547
1548	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1549	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1550	*pu32 = 0;
1551	break;
1552
1553	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1554	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1555	*pu32 = 0;
1556	break;
1557
1558	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1559	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1560	*pu32 = 0;
1561	break;
1562
1563	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1564	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1565	*pu32 = 0;
1566	break;
1567
1568	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1569	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1570	*pu32 = pThis->svga.uWidth;
1571	break;
1572
1573	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1574	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1575	*pu32 = pThis->svga.uHeight;
1576	break;
1577
1578	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1579	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1580	/* We must return something sensible here otherwise the Linux driver
1581	will take a legacy code path without 3d support. This number also
1582	limits how many screens Linux guests will allow. */
1583	*pu32 = pThis->cMonitors;
1584	break;
1585
1586	/*
1587	* SVGA_CAP_GBOBJECTS+ registers.
1588	*/
1589	case SVGA_REG_COMMAND_LOW:
1590	/* Lower 32 bits of command buffer physical address. */
1591	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1592	*pu32 = pThis->svga.u32RegCommandLow;
1593	break;
1594
1595	case SVGA_REG_COMMAND_HIGH:
1596	/* Upper 32 bits of command buffer PA. */
1597	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1598	*pu32 = pThis->svga.u32RegCommandHigh;
1599	break;
1600
1601	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1602	/* Max primary (screen) memory. */
1603	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1604	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1605	break;
1606
1607	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1608	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1609	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1610	*pu32 = pThis->vram_size / 1024;
1611	break;
1612
1613	case SVGA_REG_DEV_CAP:
1614	/* Write dev cap index, read value */
1615	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1616	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1617	{
1618	RT_UNTRUSTED_VALIDATED_FENCE();
1619	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1620	}
1621	else
1622	*pu32 = 0;
1623	break;
1624
1625	case SVGA_REG_CMD_PREPEND_LOW:
1626	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1627	pu32 = 0; / Not supported. */
1628	break;
1629
1630	case SVGA_REG_iCMD_PREPEND_HIGH:
1631	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1632	pu32 = 0; / Not supported. */
1633	break;
1634
1635	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1636	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1637	*pu32 = pThis->svga.u32MaxWidth;
1638	break;
1639
1640	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1641	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1642	*pu32 = pThis->svga.u32MaxHeight;
1643	break;
1644
1645	case SVGA_REG_MOB_MAX_SIZE:
1646	/* Essentially the max texture size */
1647	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1648	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1649	break;
1650
1651	default:
1652	{
1653	uint32_t offReg;
1654	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1655	{
1656	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1657	RT_UNTRUSTED_VALIDATED_FENCE();
1658	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1659	}
1660	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1661	{
1662	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1663	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1664	RT_UNTRUSTED_VALIDATED_FENCE();
1665	uint32_t u32 = pThis->last_palette[offReg / 3];
1666	switch (offReg % 3)
1667	{
1668	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1669	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1670	case 2: pu32 = u32 & 0xff; break; / blue */
1671	}
1672	}
1673	else
1674	{
1675	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1676	rc = VINF_IOM_R3_IOPORT_READ;
1677	#else
1678	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1679
1680	/* Do not assert. The guest might be reading all registers. */
1681	LogFunc(("Unknown reg=%#x\n", idxReg));
1682	#endif
1683	}
1684	break;
1685	}
1686	}
1687	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1688	return rc;
1689	}
1690
1691	#ifdef IN_RING3
1692	/**
1693	* Apply the current resolution settings to change the video mode.
1694	*
1695	* @returns VBox status code.
1696	* @param pThis The shared VGA state.
1697	* @param pThisCC The ring-3 VGA state.
1698	*/
1699	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1700	{
1701	/* Always do changemode on FIFO thread. */
1702	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1703
1704	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1705
1706	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1707
1708	if (pThis->svga.fGFBRegisters)
1709	{
1710	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1711	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1712	* deletes all screens other than screen #0, and redefines screen
1713	* #0 according to the specified mode. Drivers that use
1714	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1715	*/
1716
1717	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1718	pScreen->fDefined = true;
1719	pScreen->fModified = true;
1720	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1721	pScreen->idScreen = 0;
1722	pScreen->xOrigin = 0;
1723	pScreen->yOrigin = 0;
1724	pScreen->offVRAM = 0;
1725	pScreen->cbPitch = pThis->svga.cbScanline;
1726	pScreen->cWidth = pThis->svga.uWidth;
1727	pScreen->cHeight = pThis->svga.uHeight;
1728	pScreen->cBpp = pThis->svga.uBpp;
1729
1730	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1731	{
1732	/* Delete screen. */
1733	pScreen = &pSVGAState->aScreens[iScreen];
1734	if (pScreen->fDefined)
1735	{
1736	pScreen->fModified = true;
1737	pScreen->fDefined = false;
1738	}
1739	}
1740	}
1741	else
1742	{
1743	/* "If Screen Objects are supported, they can be used to fully
1744	* replace the functionality provided by the framebuffer registers
1745	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1746	*/
1747	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1748	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1749	pThis->svga.uBpp = pThis->svga.uHostBpp;
1750	}
1751
1752	vmsvgaR3VBVAResize(pThis, pThisCC);
1753
1754	/* Last stuff. For the VGA device screenshot. */
1755	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1756	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1757	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1758	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1759	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1760
1761	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1762	if ( pThis->svga.viewport.cx == 0
1763	&& pThis->svga.viewport.cy == 0)
1764	{
1765	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1766	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1767	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1768	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1769	pThis->svga.viewport.yLowWC = 0;
1770	}
1771
1772	return VINF_SUCCESS;
1773	}
1774
1775	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1776	{
1777	VBVACMDHDR cmd;
1778	cmd.x = (int16_t)(pScreen->xOrigin + x);
1779	cmd.y = (int16_t)(pScreen->yOrigin + y);
1780	cmd.w = (uint16_t)w;
1781	cmd.h = (uint16_t)h;
1782
1783	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1784	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1785	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1786	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1787
1788	return VINF_SUCCESS;
1789	}
1790
1791	#endif /* IN_RING3 */
1792	#if defined(IN_RING0) \|\| defined(IN_RING3)
1793
1794	/**
1795	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1796	*
1797	* @param pThis The shared VGA/VMSVGA instance data.
1798	* @param pThisCC The VGA/VMSVGA state for the current context.
1799	* @param fState The busy state.
1800	*/
1801	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1802	{
1803	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1804
1805	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1806	{
1807	/* Race / unfortunately scheduling. Highly unlikly. */
1808	uint32_t cLoops = 64;
1809	do
1810	{
1811	ASMNopPause();
1812	fState = (pThis->svga.fBusy != 0);
1813	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1814	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1815	}
1816	}
1817
1818
1819	/**
1820	* Update the scanline pitch in response to the guest changing mode
1821	* width/bpp.
1822	*
1823	* @param pThis The shared VGA/VMSVGA state.
1824	* @param pThisCC The VGA/VMSVGA state for the current context.
1825	*/
1826	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1827	{
1828	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1829	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1830	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1831	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1832
1833	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1834	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1835	* location but it has a different meaning.
1836	*/
1837	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1838	uFifoPitchLock = 0;
1839
1840	/* Sanitize values. */
1841	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1842	uFifoPitchLock = 0;
1843	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1844	uRegPitchLock = 0;
1845
1846	/* Prefer the register value to the FIFO value.*/
1847	if (uRegPitchLock)
1848	pThis->svga.cbScanline = uRegPitchLock;
1849	else if (uFifoPitchLock)
1850	pThis->svga.cbScanline = uFifoPitchLock;
1851	else
1852	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1853
1854	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1855	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1856	}
1857
1858	#endif /* IN_RING0 \|\| IN_RING3 */
1859
1860	#ifdef IN_RING3
1861
1862	/**
1863	* Sends cursor position and visibility information from legacy
1864	* SVGA registers to the front-end.
1865	*/
1866	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1867	{
1868	/*
1869	* Writing the X/Y/ID registers does not trigger changes; only writing the
1870	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1871	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1872	* register if they don't have to.
1873	*/
1874	uint32_t x, y, idScreen;
1875	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1876
1877	x = pThis->svga.uCursorX;
1878	y = pThis->svga.uCursorY;
1879	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1880
1881	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1882	* were extended as follows:
1883	*
1884	* SVGA_CURSOR_ON_HIDE 0
1885	* SVGA_CURSOR_ON_SHOW 1
1886	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1887	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1888	*
1889	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1890	* distinguish between the non-zero values but still remember them.
1891	*/
1892	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1893	{
1894	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1895	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1896	}
1897	pThis->svga.uCursorOn = uCursorOn;
1898	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1899	}
1900
1901
1902	/**
1903	* Copy a rectangle of pixels within guest VRAM.
1904	*/
1905	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1906	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1907	{
1908	if (!width \|\| !height)
1909	return; /* Nothing to do, don't even bother. */
1910
1911	/*
1912	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1913	* corresponding to the current display mode.
1914	*/
1915	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1916	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1917	uint8_t const *pSrc;
1918	uint8_t *pDst;
1919	unsigned const cbRectWidth = width * cbPixel;
1920	unsigned uMaxOffset;
1921
1922	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1923	if (uMaxOffset >= cbFrameBuffer)
1924	{
1925	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1926	return; /* Just don't listen to a bad guest. */
1927	}
1928
1929	pSrc = pDst = pThisCC->pbVRam;
1930	pSrc += srcY * cbScanline + srcX * cbPixel;
1931	pDst += dstY * cbScanline + dstX * cbPixel;
1932
1933	if (srcY >= dstY)
1934	{
1935	/* Source below destination, copy top to bottom. */
1936	for (; height > 0; height--)
1937	{
1938	memmove(pDst, pSrc, cbRectWidth);
1939	pSrc += cbScanline;
1940	pDst += cbScanline;
1941	}
1942	}
1943	else
1944	{
1945	/* Source above destination, copy bottom to top. */
1946	pSrc += cbScanline * (height - 1);
1947	pDst += cbScanline * (height - 1);
1948	for (; height > 0; height--)
1949	{
1950	memmove(pDst, pSrc, cbRectWidth);
1951	pSrc -= cbScanline;
1952	pDst -= cbScanline;
1953	}
1954	}
1955	}
1956
1957	#endif /* IN_RING3 */
1958
1959
1960	/**
1961	* Write port register
1962	*
1963	* @returns Strict VBox status code.
1964	* @param pDevIns The device instance.
1965	* @param pThis The shared VGA/VMSVGA state.
1966	* @param pThisCC The VGA/VMSVGA state for the current context.
1967	* @param u32 Value to write
1968	*/
1969	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1970	{
1971	#ifdef IN_RING3
1972	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1973	#endif
1974	VBOXSTRICTRC rc = VINF_SUCCESS;
1975	RT_NOREF(pThisCC);
1976
1977	/* Rough index register validation. */
1978	uint32_t idxReg = pThis->svga.u32IndexReg;
1979	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1980	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1981	VINF_IOM_R3_IOPORT_WRITE);
1982	#else
1983	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1984	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1985	VINF_SUCCESS);
1986	#endif
1987	RT_UNTRUSTED_VALIDATED_FENCE();
1988
1989	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1990	if ( idxReg >= SVGA_REG_ID_0_TOP
1991	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1992	{
1993	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1994	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1995	}
1996	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1997	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1998	switch (idxReg)
1999	{
2000	case SVGA_REG_WIDTH:
2001	case SVGA_REG_HEIGHT:
2002	case SVGA_REG_PITCHLOCK:
2003	case SVGA_REG_BITS_PER_PIXEL:
2004	pThis->svga.fGFBRegisters = true;
2005	break;
2006	default:
2007	break;
2008	}
2009
2010	switch (idxReg)
2011	{
2012	case SVGA_REG_ID:
2013	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
2014	if ( u32 == SVGA_ID_0
2015	\|\| u32 == SVGA_ID_1
2016	\|\| u32 == SVGA_ID_2)
2017	pThis->svga.u32SVGAId = u32;
2018	else
2019	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
2020	break;
2021
2022	case SVGA_REG_ENABLE:
2023	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
2024	#ifdef IN_RING3
2025	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
2026	&& pThis->svga.fEnabled == false)
2027	{
2028	/* Make a backup copy of the first 512kb in order to save font data etc. */
2029	/** @todo should probably swap here, rather than copy + zero */
2030	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
2031	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
2032	}
2033
2034	pThis->svga.fEnabled = u32;
2035	if (pThis->svga.fEnabled)
2036	{
2037	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
2038	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
2039	{
2040	/* Keep the current mode. */
2041	pThis->svga.uWidth = pThisCC->pDrv->cx;
2042	pThis->svga.uHeight = pThisCC->pDrv->cy;
2043	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
2044	}
2045
2046	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
2047	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
2048	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2049	# ifdef LOG_ENABLED
2050	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2051	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
2052	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2053	# endif
2054
2055	/* Disable or enable dirty page tracking according to the current fTraces value. */
2056	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2057
2058	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
2059	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
2060	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
2061
2062	/* Make the cursor visible again as needed. */
2063	if (pSVGAState->Cursor.fActive)
2064	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
2065	}
2066	else
2067	{
2068	/* Make sure the cursor is off. */
2069	if (pSVGAState->Cursor.fActive)
2070	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
2071
2072	/* Restore the text mode backup. */
2073	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
2074
2075	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
2076
2077	/* Enable dirty page tracking again when going into legacy mode. */
2078	vmsvgaR3SetTraces(pDevIns, pThis, true);
2079
2080	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
2081	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
2082	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
2083
2084	/* Clear the pitch lock. */
2085	pThis->svga.u32PitchLock = 0;
2086	}
2087	#else /* !IN_RING3 */
2088	rc = VINF_IOM_R3_IOPORT_WRITE;
2089	#endif /* !IN_RING3 */
2090	break;
2091
2092	case SVGA_REG_WIDTH:
2093	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
2094	if (pThis->svga.uWidth != u32)
2095	{
2096	#if defined(IN_RING3) \|\| defined(IN_RING0)
2097	pThis->svga.uWidth = u32;
2098	vmsvgaHCUpdatePitch(pThis, pThisCC);
2099	if (pThis->svga.fEnabled)
2100	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2101	#else
2102	rc = VINF_IOM_R3_IOPORT_WRITE;
2103	#endif
2104	}
2105	/* else: nop */
2106	break;
2107
2108	case SVGA_REG_HEIGHT:
2109	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
2110	if (pThis->svga.uHeight != u32)
2111	{
2112	pThis->svga.uHeight = u32;
2113	if (pThis->svga.fEnabled)
2114	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2115	}
2116	/* else: nop */
2117	break;
2118
2119	case SVGA_REG_DEPTH:
2120	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
2121	/** @todo read-only?? */
2122	break;
2123
2124	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
2125	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
2126	if (pThis->svga.uBpp != u32)
2127	{
2128	#if defined(IN_RING3) \|\| defined(IN_RING0)
2129	pThis->svga.uBpp = u32;
2130	vmsvgaHCUpdatePitch(pThis, pThisCC);
2131	if (pThis->svga.fEnabled)
2132	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2133	#else
2134	rc = VINF_IOM_R3_IOPORT_WRITE;
2135	#endif
2136	}
2137	/* else: nop */
2138	break;
2139
2140	case SVGA_REG_PSEUDOCOLOR:
2141	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
2142	break;
2143
2144	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
2145	#ifdef IN_RING3
2146	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
2147	pThis->svga.fConfigured = u32;
2148	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
2149	if (!pThis->svga.fConfigured)
2150	pThis->svga.fTraces = true;
2151	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2152	#else
2153	rc = VINF_IOM_R3_IOPORT_WRITE;
2154	#endif
2155	break;
2156
2157	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
2158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
2159	if ( pThis->svga.fEnabled
2160	&& pThis->svga.fConfigured)
2161	{
2162	#if defined(IN_RING3) \|\| defined(IN_RING0)
2163	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
2164	/*
2165	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
2166	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
2167	*/
2168	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
2169	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
2170	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
2171
2172	/* Kick the FIFO thread to start processing commands again. */
2173	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2174	#else
2175	rc = VINF_IOM_R3_IOPORT_WRITE;
2176	#endif
2177	}
2178	/* else nothing to do. */
2179	else
2180	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2181
2182	break;
2183
2184	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2186	break;
2187
2188	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2189	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2190	pThis->svga.u32GuestId = u32;
2191	break;
2192
2193	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2195	pThis->svga.u32PitchLock = u32;
2196	/* Should this also update the FIFO pitch lock? Unclear. */
2197	break;
2198
2199	case SVGA_REG_IRQMASK: /* Interrupt mask */
2200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2201	pThis->svga.u32IrqMask = u32;
2202
2203	/* Irq pending after the above change? */
2204	if (pThis->svga.u32IrqStatus & u32)
2205	{
2206	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2207	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2208	}
2209	else
2210	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2211	break;
2212
2213	/* Mouse cursor support */
2214	case SVGA_REG_CURSOR_ID:
2215	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2216	pThis->svga.uCursorID = u32;
2217	break;
2218
2219	case SVGA_REG_CURSOR_X:
2220	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2221	pThis->svga.uCursorX = u32;
2222	break;
2223
2224	case SVGA_REG_CURSOR_Y:
2225	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2226	pThis->svga.uCursorY = u32;
2227	break;
2228
2229	case SVGA_REG_CURSOR_ON:
2230	#ifdef IN_RING3
2231	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2232	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2233	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2234	#else
2235	rc = VINF_IOM_R3_IOPORT_WRITE;
2236	#endif
2237	break;
2238
2239	/* Legacy multi-monitor support */
2240	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2241	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2242	break;
2243	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2244	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2245	break;
2246	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2247	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2248	break;
2249	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2250	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2251	break;
2252	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2253	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2254	break;
2255	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2256	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2257	break;
2258	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2260	break;
2261	#ifdef VBOX_WITH_VMSVGA3D
2262	/* See "Guest memory regions" below. */
2263	case SVGA_REG_GMR_ID:
2264	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2265	pThis->svga.u32CurrentGMRId = u32;
2266	break;
2267
2268	case SVGA_REG_GMR_DESCRIPTOR:
2269	# ifndef IN_RING3
2270	rc = VINF_IOM_R3_IOPORT_WRITE;
2271	break;
2272	# else /* IN_RING3 */
2273	{
2274	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2275
2276	/* Validate current GMR id. */
2277	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2278	AssertBreak(idGMR < pThis->svga.cGMR);
2279	RT_UNTRUSTED_VALIDATED_FENCE();
2280
2281	/* Free the old GMR if present. */
2282	vmsvgaR3GmrFree(pThisCC, idGMR);
2283
2284	/* Just undefine the GMR? */
2285	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2286	if (GCPhys == 0)
2287	{
2288	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2289	break;
2290	}
2291
2292
2293	/* Never cross a page boundary automatically. */
2294	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2295	uint32_t cPagesTotal = 0;
2296	uint32_t iDesc = 0;
2297	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2298	uint32_t cLoops = 0;
2299	RTGCPHYS GCPhysBase = GCPhys;
2300	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2301	{
2302	/* Read descriptor. */
2303	SVGAGuestMemDescriptor desc;
2304	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2305	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2306
2307	if (desc.numPages != 0)
2308	{
2309	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2310	cPagesTotal += desc.numPages;
2311	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2312
2313	if ((iDesc & 15) == 0)
2314	{
2315	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2316	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2317	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2318	}
2319
2320	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2321	paDescs[iDesc++].numPages = desc.numPages;
2322
2323	/* Continue with the next descriptor. */
2324	GCPhys += sizeof(desc);
2325	}
2326	else if (desc.ppn == 0)
2327	break; /* terminator */
2328	else /* Pointer to the next physical page of descriptors. */
2329	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2330
2331	cLoops++;
2332	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2333	}
2334
2335	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2336	if (RT_SUCCESS(rc))
2337	{
2338	/* Commit the GMR. */
2339	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2340	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2341	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2342	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2343	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2344	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2345	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2346	}
2347	else
2348	{
2349	RTMemFree(paDescs);
2350	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2351	}
2352	break;
2353	}
2354	# endif /* IN_RING3 */
2355	#endif // VBOX_WITH_VMSVGA3D
2356
2357	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2358	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2359	if (pThis->svga.fTraces == u32)
2360	break; /* nothing to do */
2361
2362	#ifdef IN_RING3
2363	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2364	#else
2365	rc = VINF_IOM_R3_IOPORT_WRITE;
2366	#endif
2367	break;
2368
2369	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2370	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2371	break;
2372
2373	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2374	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2375	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2376	break;
2377
2378	/*
2379	* SVGA_CAP_GBOBJECTS+ registers.
2380	*/
2381	case SVGA_REG_COMMAND_LOW:
2382	{
2383	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2384	#ifdef IN_RING3
2385	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2386	pThis->svga.u32RegCommandLow = u32;
2387
2388	/* "lower 6 bits are used for the SVGACBContext" */
2389	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2390	GCPhysCB <<= 32;
2391	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2392	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2393	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2394	#else
2395	rc = VINF_IOM_R3_IOPORT_WRITE;
2396	#endif
2397	break;
2398	}
2399
2400	case SVGA_REG_COMMAND_HIGH:
2401	/* Upper 32 bits of command buffer PA. */
2402	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2403	pThis->svga.u32RegCommandHigh = u32;
2404	break;
2405
2406	case SVGA_REG_DEV_CAP:
2407	/* Write dev cap index, read value */
2408	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2409	pThis->svga.u32DevCapIndex = u32;
2410	break;
2411
2412	case SVGA_REG_CMD_PREPEND_LOW:
2413	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2414	/* Not supported. */
2415	break;
2416
2417	case SVGA_REG_iCMD_PREPEND_HIGH:
2418	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2419	/* Not supported. */
2420	break;
2421
2422	case SVGA_REG_FB_START:
2423	case SVGA_REG_MEM_START:
2424	case SVGA_REG_HOST_BITS_PER_PIXEL:
2425	case SVGA_REG_MAX_WIDTH:
2426	case SVGA_REG_MAX_HEIGHT:
2427	case SVGA_REG_VRAM_SIZE:
2428	case SVGA_REG_FB_SIZE:
2429	case SVGA_REG_CAPABILITIES:
2430	case SVGA_REG_MEM_SIZE:
2431	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2432	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2433	case SVGA_REG_BYTES_PER_LINE:
2434	case SVGA_REG_FB_OFFSET:
2435	case SVGA_REG_RED_MASK:
2436	case SVGA_REG_GREEN_MASK:
2437	case SVGA_REG_BLUE_MASK:
2438	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2439	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2440	case SVGA_REG_GMR_MAX_IDS:
2441	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2442	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2443	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2444	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2445	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2446	case SVGA_REG_MOB_MAX_SIZE:
2447	/* Read only - ignore. */
2448	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2449	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2450	break;
2451
2452	default:
2453	{
2454	uint32_t offReg;
2455	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2456	{
2457	RT_UNTRUSTED_VALIDATED_FENCE();
2458	pThis->svga.au32ScratchRegion[offReg] = u32;
2459	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2460	}
2461	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2462	{
2463	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2464	Btw, see rgb_to_pixel32. */
2465	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2466	u32 &= 0xff;
2467	RT_UNTRUSTED_VALIDATED_FENCE();
2468	uint32_t uRgb = pThis->last_palette[offReg / 3];
2469	switch (offReg % 3)
2470	{
2471	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2472	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2473	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2474	}
2475	pThis->last_palette[offReg / 3] = uRgb;
2476	}
2477	else
2478	{
2479	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2480	rc = VINF_IOM_R3_IOPORT_WRITE;
2481	#else
2482	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2483	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2484	#endif
2485	}
2486	break;
2487	}
2488	}
2489	return rc;
2490	}
2491
2492	/**
2493	* @callback_method_impl{FNIOMIOPORTNEWIN}
2494	*/
2495	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2496	{
2497	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2498	RT_NOREF_PV(pvUser);
2499
2500	/* Only dword accesses. */
2501	if (cb == 4)
2502	{
2503	switch (offPort)
2504	{
2505	case SVGA_INDEX_PORT:
2506	*pu32 = pThis->svga.u32IndexReg;
2507	break;
2508
2509	case SVGA_VALUE_PORT:
2510	return vmsvgaReadPort(pDevIns, pThis, pu32);
2511
2512	case SVGA_BIOS_PORT:
2513	Log(("Ignoring BIOS port read\n"));
2514	*pu32 = 0;
2515	break;
2516
2517	case SVGA_IRQSTATUS_PORT:
2518	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2519	*pu32 = pThis->svga.u32IrqStatus;
2520	break;
2521
2522	default:
2523	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2524	*pu32 = UINT32_MAX;
2525	break;
2526	}
2527	}
2528	else
2529	{
2530	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2531	*pu32 = UINT32_MAX;
2532	}
2533	return VINF_SUCCESS;
2534	}
2535
2536	/**
2537	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2538	*/
2539	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2540	{
2541	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2542	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2543	RT_NOREF_PV(pvUser);
2544
2545	/* Only dword accesses. */
2546	if (cb == 4)
2547	switch (offPort)
2548	{
2549	case SVGA_INDEX_PORT:
2550	pThis->svga.u32IndexReg = u32;
2551	break;
2552
2553	case SVGA_VALUE_PORT:
2554	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2555
2556	case SVGA_BIOS_PORT:
2557	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2558	break;
2559
2560	case SVGA_IRQSTATUS_PORT:
2561	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2562	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2563	/* Clear the irq in case all events have been cleared. */
2564	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2565	{
2566	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2567	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2568	}
2569	break;
2570
2571	default:
2572	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2573	break;
2574	}
2575	else
2576	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2577
2578	return VINF_SUCCESS;
2579	}
2580
2581	#ifdef IN_RING3
2582
2583	# ifdef DEBUG_FIFO_ACCESS
2584	/**
2585	* Handle FIFO memory access.
2586	* @returns VBox status code.
2587	* @param pVM VM handle.
2588	* @param pThis The shared VGA/VMSVGA instance data.
2589	* @param GCPhys The access physical address.
2590	* @param fWriteAccess Read or write access
2591	*/
2592	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2593	{
2594	RT_NOREF(pVM);
2595	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2596	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2597
2598	switch (GCPhysOffset >> 2)
2599	{
2600	case SVGA_FIFO_MIN:
2601	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2602	break;
2603	case SVGA_FIFO_MAX:
2604	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2605	break;
2606	case SVGA_FIFO_NEXT_CMD:
2607	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2608	break;
2609	case SVGA_FIFO_STOP:
2610	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2611	break;
2612	case SVGA_FIFO_CAPABILITIES:
2613	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2614	break;
2615	case SVGA_FIFO_FLAGS:
2616	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2617	break;
2618	case SVGA_FIFO_FENCE:
2619	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2620	break;
2621	case SVGA_FIFO_3D_HWVERSION:
2622	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2623	break;
2624	case SVGA_FIFO_PITCHLOCK:
2625	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2626	break;
2627	case SVGA_FIFO_CURSOR_ON:
2628	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2629	break;
2630	case SVGA_FIFO_CURSOR_X:
2631	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2632	break;
2633	case SVGA_FIFO_CURSOR_Y:
2634	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2635	break;
2636	case SVGA_FIFO_CURSOR_COUNT:
2637	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2638	break;
2639	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2640	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2641	break;
2642	case SVGA_FIFO_RESERVED:
2643	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2644	break;
2645	case SVGA_FIFO_CURSOR_SCREEN_ID:
2646	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2647	break;
2648	case SVGA_FIFO_DEAD:
2649	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2650	break;
2651	case SVGA_FIFO_3D_HWVERSION_REVISED:
2652	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2653	break;
2654	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2655	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2656	break;
2657	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2658	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2659	break;
2660	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2661	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2662	break;
2663	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2664	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2665	break;
2666	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2667	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2668	break;
2669	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2670	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2671	break;
2672	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2673	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2674	break;
2675	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2676	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2677	break;
2678	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2679	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2680	break;
2681	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2682	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2683	break;
2684	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2685	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2686	break;
2687	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2688	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2689	break;
2690	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2691	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2692	break;
2693	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2694	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2695	break;
2696	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2697	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2698	break;
2699	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2700	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2701	break;
2702	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2703	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2704	break;
2705	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2706	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2707	break;
2708	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2709	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2710	break;
2711	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2712	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2713	break;
2714	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2715	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2716	break;
2717	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2718	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2719	break;
2720	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2721	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2722	break;
2723	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2724	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2725	break;
2726	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2727	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2728	break;
2729	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2730	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2731	break;
2732	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2733	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2734	break;
2735	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2736	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2737	break;
2738	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2739	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2740	break;
2741	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2742	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2743	break;
2744	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2745	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2746	break;
2747	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2748	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2749	break;
2750	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2751	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2752	break;
2753	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2754	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2755	break;
2756	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2757	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2758	break;
2759	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2760	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2761	break;
2762	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2763	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2764	break;
2765	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2766	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2767	break;
2768	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2769	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2770	break;
2771	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2772	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2773	break;
2774	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2775	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2776	break;
2777	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2778	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2779	break;
2780	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2781	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2782	break;
2783	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2784	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2785	break;
2786	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2787	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2788	break;
2789	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2790	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2791	break;
2792	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2793	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2794	break;
2795	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2796	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2797	break;
2798	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2799	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2800	break;
2801	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2802	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2803	break;
2804	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2805	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2806	break;
2807	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2808	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2809	break;
2810	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2811	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2812	break;
2813	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2814	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2815	break;
2816	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2817	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2818	break;
2819	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2820	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2821	break;
2822	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2823	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2824	break;
2825	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2826	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2827	break;
2828	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2829	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2830	break;
2831	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2832	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2833	break;
2834	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2835	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2836	break;
2837	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2838	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2839	break;
2840	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2841	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2842	break;
2843	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2844	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2845	break;
2846	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2847	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2848	break;
2849	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2850	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2851	break;
2852	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2853	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2854	break;
2855	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2856	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2857	break;
2858	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2859	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2860	break;
2861	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2862	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2863	break;
2864	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2865	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2866	break;
2867	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2868	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2869	break;
2870	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2871	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2872	break;
2873	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2874	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2875	break;
2876	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2877	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2878	break;
2879	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2880	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2881	break;
2882	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2883	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2884	break;
2885	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2886	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2887	break;
2888	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2889	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2890	break;
2891	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2892	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2893	break;
2894	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2895	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2896	break;
2897	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2898	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2899	break;
2900	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2901	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2902	break;
2903	case SVGA_FIFO_3D_CAPS_LAST:
2904	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2905	break;
2906	case SVGA_FIFO_GUEST_3D_HWVERSION:
2907	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2908	break;
2909	case SVGA_FIFO_FENCE_GOAL:
2910	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2911	break;
2912	case SVGA_FIFO_BUSY:
2913	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2914	break;
2915	default:
2916	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2917	break;
2918	}
2919
2920	return VINF_EM_RAW_EMULATE_INSTR;
2921	}
2922	# endif /* DEBUG_FIFO_ACCESS */
2923
2924	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2925	/**
2926	* HC access handler for the FIFO.
2927	*
2928	* @returns VINF_SUCCESS if the handler have carried out the operation.
2929	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2930	* @param pVM VM Handle.
2931	* @param pVCpu The cross context CPU structure for the calling EMT.
2932	* @param GCPhys The physical address the guest is writing to.
2933	* @param pvPhys The HC mapping of that address.
2934	* @param pvBuf What the guest is reading/writing.
2935	* @param cbBuf How much it's reading/writing.
2936	* @param enmAccessType The access type.
2937	* @param enmOrigin Who is making the access.
2938	* @param pvUser User argument.
2939	*/
2940	static DECLCALLBACK(VBOXSTRICTRC)
2941	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2942	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2943	{
2944	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2945	PVGASTATE pThis = (PVGASTATE)pvUser;
2946	AssertPtr(pThis);
2947
2948	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2949	/*
2950	* Wake up the FIFO thread as it might have work to do now.
2951	*/
2952	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2953	AssertLogRelRC(rc);
2954	# endif
2955
2956	# ifdef DEBUG_FIFO_ACCESS
2957	/*
2958	* When in debug-fifo-access mode, we do not disable the access handler,
2959	* but leave it on as we wish to catch all access.
2960	*/
2961	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2962	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2963	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2964	/*
2965	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2966	*/
2967	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2968	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2969	# endif
2970	if (RT_SUCCESS(rc))
2971	return VINF_PGM_HANDLER_DO_DEFAULT;
2972	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2973	return rc;
2974	}
2975	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2976
2977	#endif /* IN_RING3 */
2978
2979	#ifdef DEBUG_GMR_ACCESS
2980	# ifdef IN_RING3
2981
2982	/**
2983	* HC access handler for the FIFO.
2984	*
2985	* @returns VINF_SUCCESS if the handler have carried out the operation.
2986	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2987	* @param pVM VM Handle.
2988	* @param pVCpu The cross context CPU structure for the calling EMT.
2989	* @param GCPhys The physical address the guest is writing to.
2990	* @param pvPhys The HC mapping of that address.
2991	* @param pvBuf What the guest is reading/writing.
2992	* @param cbBuf How much it's reading/writing.
2993	* @param enmAccessType The access type.
2994	* @param enmOrigin Who is making the access.
2995	* @param pvUser User argument.
2996	*/
2997	static DECLCALLBACK(VBOXSTRICTRC)
2998	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2999	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3000	{
3001	PVGASTATE pThis = (PVGASTATE)pvUser;
3002	Assert(pThis);
3003	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3004	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
3005
3006	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
3007
3008	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3009	{
3010	PGMR pGMR = &pSVGAState->paGMR[i];
3011
3012	if (pGMR->numDescriptors)
3013	{
3014	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3015	{
3016	if ( GCPhys >= pGMR->paDesc[j].GCPhys
3017	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
3018	{
3019	/*
3020	* Turn off the write handler for this particular page and make it R/W.
3021	* Then return telling the caller to restart the guest instruction.
3022	*/
3023	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
3024	AssertRC(rc);
3025	return VINF_PGM_HANDLER_DO_DEFAULT;
3026	}
3027	}
3028	}
3029	}
3030
3031	return VINF_PGM_HANDLER_DO_DEFAULT;
3032	}
3033
3034	/** Callback handler for VMR3ReqCallWaitU */
3035	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3036	{
3037	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3038	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3039	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3040	int rc;
3041
3042	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3043	{
3044	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
3045	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
3046	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
3047	AssertRC(rc);
3048	}
3049	return VINF_SUCCESS;
3050	}
3051
3052	/** Callback handler for VMR3ReqCallWaitU */
3053	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3054	{
3055	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3056	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3057	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3058
3059	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3060	{
3061	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
3062	AssertRC(rc);
3063	}
3064	return VINF_SUCCESS;
3065	}
3066
3067	/** Callback handler for VMR3ReqCallWaitU */
3068	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
3069	{
3070	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3071
3072	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3073	{
3074	PGMR pGMR = &pSVGAState->paGMR[i];
3075
3076	if (pGMR->numDescriptors)
3077	{
3078	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3079	{
3080	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
3081	AssertRC(rc);
3082	}
3083	}
3084	}
3085	return VINF_SUCCESS;
3086	}
3087
3088	# endif /* IN_RING3 */
3089	#endif /* DEBUG_GMR_ACCESS */
3090
3091	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3092
3093	#ifdef IN_RING3
3094
3095
3096	/**
3097	* Common worker for changing the pointer shape.
3098	*
3099	* @param pThisCC The VGA/VMSVGA state for ring-3.
3100	* @param pSVGAState The VMSVGA ring-3 instance data.
3101	* @param fAlpha Whether there is alpha or not.
3102	* @param xHot Hotspot x coordinate.
3103	* @param yHot Hotspot y coordinate.
3104	* @param cx Width.
3105	* @param cy Height.
3106	* @param pbData Heap copy of the cursor data. Consumed.
3107	* @param cbData The size of the data.
3108	*/
3109	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
3110	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
3111	{
3112	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
3113	# ifdef LOG_ENABLED
3114	if (LogIs2Enabled())
3115	{
3116	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
3117	if (!fAlpha)
3118	{
3119	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
3120	for (uint32_t y = 0; y < cy; y++)
3121	{
3122	Log2(("%3u:", y));
3123	uint8_t const pbLine = &pbData[y cbAndLine];
3124	for (uint32_t x = 0; x < cx; x += 8)
3125	{
3126	uint8_t b = pbLine[x / 8];
3127	char szByte[12];
3128	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
3129	szByte[1] = b & 0x40 ? '*' : ' ';
3130	szByte[2] = b & 0x20 ? '*' : ' ';
3131	szByte[3] = b & 0x10 ? '*' : ' ';
3132	szByte[4] = b & 0x08 ? '*' : ' ';
3133	szByte[5] = b & 0x04 ? '*' : ' ';
3134	szByte[6] = b & 0x02 ? '*' : ' ';
3135	szByte[7] = b & 0x01 ? '*' : ' ';
3136	szByte[8] = '\0';
3137	Log2(("%s", szByte));
3138	}
3139	Log2(("\n"));
3140	}
3141	}
3142
3143	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
3144	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
3145	for (uint32_t y = 0; y < cy; y++)
3146	{
3147	Log2(("%3u:", y));
3148	uint32_t const pu32Line = &pu32Xor[y cx];
3149	for (uint32_t x = 0; x < cx; x++)
3150	Log2((" %08x", pu32Line[x]));
3151	Log2(("\n"));
3152	}
3153	}
3154	# endif
3155
3156	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
3157	AssertRC(rc);
3158
3159	if (pSVGAState->Cursor.fActive)
3160	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3161
3162	pSVGAState->Cursor.fActive = true;
3163	pSVGAState->Cursor.xHotspot = xHot;
3164	pSVGAState->Cursor.yHotspot = yHot;
3165	pSVGAState->Cursor.width = cx;
3166	pSVGAState->Cursor.height = cy;
3167	pSVGAState->Cursor.cbData = cbData;
3168	pSVGAState->Cursor.pData = pbData;
3169	}
3170
3171
3172	# ifdef VBOX_WITH_VMSVGA3D
3173	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3174	* Check that the 3D command has at least a_cbMin of payload bytes after the
3175	* header. Will break out of the switch if it doesn't.
3176	*/
3177	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3178	if (1) { \
3179	AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3180	RT_UNTRUSTED_VALIDATED_FENCE(); \
3181	} else do {} while (0)
3182
3183	# define VMSVGA_3D_CMD_NOTIMPL() \
3184	if (1) { \
3185	AssertMsgFailed(("Not implemented %d %s\n", cmdId, vmsvgaR3FifoCmdToString(cmdId))); \
3186	} else do {} while (0)
3187
3188	/** SVGA_3D_CMD_* handler.
3189	* This function parses the command and calls the corresponding command handler.
3190	*
3191	* @param pThis The shared VGA/VMSVGA state.
3192	* @param pThisCC The VGA/VMSVGA state for the current context.
3193	* @param cmdId SVGA_3D_CMD_* command identifier.
3194	* @param cbCmd Size of the command in bytes.
3195	* @param pvCmd Pointer to the command.
3196	* @returns VBox status code if an error was detected parsing a command.
3197	*/
3198	static int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t cmdId, uint32_t cbCmd, void const *pvCmd)
3199	{
3200	int rcParse = VINF_SUCCESS;
3201	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
3202
3203	switch (cmdId)
3204	{
3205	case SVGA_3D_CMD_SURFACE_DEFINE:
3206	{
3207	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )pvCmd;
3208	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3209	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
3210
3211	uint32_t const cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3212	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3213	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3214	# ifdef DEBUG_GMR_ACCESS
3215	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3216	# endif
3217	break;
3218	}
3219
3220	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3221	{
3222	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )pvCmd;
3223	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3224	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
3225
3226	uint32_t const cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3227	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3228	pCmd->multisampleCount, pCmd->autogenFilter,
3229	cMipLevels, (SVGA3dSize *)(pCmd + 1));
3230	break;
3231	}
3232
3233	case SVGA_3D_CMD_SURFACE_DESTROY:
3234	{
3235	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )pvCmd;
3236	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3237	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
3238
3239	vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3240	break;
3241	}
3242
3243	case SVGA_3D_CMD_SURFACE_COPY:
3244	{
3245	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )pvCmd;
3246	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3247	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
3248
3249	uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3250	vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3251	break;
3252	}
3253
3254	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3255	{
3256	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )pvCmd;
3257	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3258	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
3259
3260	vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3261	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
3262	break;
3263	}
3264
3265	case SVGA_3D_CMD_SURFACE_DMA:
3266	{
3267	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )pvCmd;
3268	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3269	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
3270
3271	uint64_t u64NanoTS = 0;
3272	if (LogRelIs3Enabled())
3273	u64NanoTS = RTTimeNanoTS();
3274	uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3275	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3276	vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3277	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3278	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3279	if (LogRelIs3Enabled())
3280	{
3281	if (cCopyBoxes)
3282	{
3283	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
3284	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3285	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3286	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3287	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3288	}
3289	}
3290	break;
3291	}
3292
3293	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3294	{
3295	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )pvCmd;
3296	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3297	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
3298
3299	static uint64_t u64FrameStartNanoTS = 0;
3300	static uint64_t u64ElapsedPerSecNano = 0;
3301	static int cFrames = 0;
3302	uint64_t u64NanoTS = 0;
3303	if (LogRelIs3Enabled())
3304	u64NanoTS = RTTimeNanoTS();
3305	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3306	STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3307	vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3308	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3309	STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3310	if (LogRelIs3Enabled())
3311	{
3312	uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3313	u64ElapsedPerSecNano += u64ElapsedNano;
3314
3315	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
3316	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3317	(u64ElapsedNano) / 1000ULL, cRects,
3318	pFirstRect->left, pFirstRect->top,
3319	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3320
3321	++cFrames;
3322	if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3323	{
3324	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3325	cFrames, u64ElapsedPerSecNano / 1000ULL));
3326	u64FrameStartNanoTS = u64NanoTS;
3327	cFrames = 0;
3328	u64ElapsedPerSecNano = 0;
3329	}
3330	}
3331	break;
3332	}
3333
3334	case SVGA_3D_CMD_CONTEXT_DEFINE:
3335	{
3336	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )pvCmd;
3337	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3338	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
3339
3340	vmsvga3dContextDefine(pThisCC, pCmd->cid);
3341	break;
3342	}
3343
3344	case SVGA_3D_CMD_CONTEXT_DESTROY:
3345	{
3346	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )pvCmd;
3347	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3348	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
3349
3350	vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3351	break;
3352	}
3353
3354	case SVGA_3D_CMD_SETTRANSFORM:
3355	{
3356	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )pvCmd;
3357	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3358	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
3359
3360	vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3361	break;
3362	}
3363
3364	case SVGA_3D_CMD_SETZRANGE:
3365	{
3366	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )pvCmd;
3367	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3368	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
3369
3370	vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3371	break;
3372	}
3373
3374	case SVGA_3D_CMD_SETRENDERSTATE:
3375	{
3376	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )pvCmd;
3377	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3378	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
3379
3380	uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3381	vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3382	break;
3383	}
3384
3385	case SVGA_3D_CMD_SETRENDERTARGET:
3386	{
3387	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )pvCmd;
3388	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3389	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
3390
3391	vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3392	break;
3393	}
3394
3395	case SVGA_3D_CMD_SETTEXTURESTATE:
3396	{
3397	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )pvCmd;
3398	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3399	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
3400
3401	uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3402	vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3403	break;
3404	}
3405
3406	case SVGA_3D_CMD_SETMATERIAL:
3407	{
3408	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )pvCmd;
3409	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3410	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
3411
3412	vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
3413	break;
3414	}
3415
3416	case SVGA_3D_CMD_SETLIGHTDATA:
3417	{
3418	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )pvCmd;
3419	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3420	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
3421
3422	vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
3423	break;
3424	}
3425
3426	case SVGA_3D_CMD_SETLIGHTENABLED:
3427	{
3428	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )pvCmd;
3429	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3430	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
3431
3432	vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
3433	break;
3434	}
3435
3436	case SVGA_3D_CMD_SETVIEWPORT:
3437	{
3438	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )pvCmd;
3439	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3440	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
3441
3442	vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
3443	break;
3444	}
3445
3446	case SVGA_3D_CMD_SETCLIPPLANE:
3447	{
3448	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )pvCmd;
3449	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3450	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
3451
3452	vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
3453	break;
3454	}
3455
3456	case SVGA_3D_CMD_CLEAR:
3457	{
3458	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )pvCmd;
3459	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3460	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
3461
3462	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3463	vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3464	break;
3465	}
3466
3467	case SVGA_3D_CMD_PRESENT:
3468	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3469	{
3470	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )pvCmd;
3471	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3472	if (cmdId == SVGA_3D_CMD_PRESENT)
3473	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
3474	else
3475	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
3476
3477	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3478	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
3479	vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3480	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
3481	break;
3482	}
3483
3484	case SVGA_3D_CMD_SHADER_DEFINE:
3485	{
3486	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )pvCmd;
3487	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3488	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
3489
3490	uint32_t const cbData = (cbCmd - sizeof(*pCmd));
3491	vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3492	break;
3493	}
3494
3495	case SVGA_3D_CMD_SHADER_DESTROY:
3496	{
3497	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )pvCmd;
3498	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3499	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
3500
3501	vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
3502	break;
3503	}
3504
3505	case SVGA_3D_CMD_SET_SHADER:
3506	{
3507	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )pvCmd;
3508	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3509	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
3510
3511	vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3512	break;
3513	}
3514
3515	case SVGA_3D_CMD_SET_SHADER_CONST:
3516	{
3517	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )pvCmd;
3518	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3519	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
3520
3521	uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3522	vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3523	break;
3524	}
3525
3526	case SVGA_3D_CMD_DRAW_PRIMITIVES:
3527	{
3528	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )pvCmd;
3529	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3530	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
3531
3532	ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
3533	ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
3534	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
3535	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
3536	ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
3537
3538	uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
3539	ASSERT_GUEST_STMT_BREAK(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
3540	RT_UNTRUSTED_VALIDATED_FENCE();
3541
3542	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
3543	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
3544	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
3545
3546	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
3547	vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
3548	pNumRange, cVertexDivisor, pVertexDivisor);
3549	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
3550	break;
3551	}
3552
3553	case SVGA_3D_CMD_SETSCISSORRECT:
3554	{
3555	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )pvCmd;
3556	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3557	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
3558
3559	vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
3560	break;
3561	}
3562
3563	case SVGA_3D_CMD_BEGIN_QUERY:
3564	{
3565	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )pvCmd;
3566	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3567	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
3568
3569	vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
3570	break;
3571	}
3572
3573	case SVGA_3D_CMD_END_QUERY:
3574	{
3575	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )pvCmd;
3576	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3577	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
3578
3579	vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3580	break;
3581	}
3582
3583	case SVGA_3D_CMD_WAIT_FOR_QUERY:
3584	{
3585	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )pvCmd;
3586	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3587	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
3588
3589	vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3590	break;
3591	}
3592
3593	case SVGA_3D_CMD_GENERATE_MIPMAPS:
3594	{
3595	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )pvCmd;
3596	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3597	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
3598
3599	vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
3600	break;
3601	}
3602
3603	case SVGA_3D_CMD_ACTIVATE_SURFACE:
3604	/* context id + surface id? */
3605	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
3606	break;
3607
3608	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3609	/* context id + surface id? */
3610	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
3611	break;
3612
3613	/*
3614	*
3615	* VPGU10: SVGA_CAP_GBOBJECTS+ commands.
3616	*
3617	*/
3618	case SVGA_3D_CMD_SCREEN_DMA:
3619	{
3620	SVGA3dCmdScreenDMA pCmd = (SVGA3dCmdScreenDMA )pvCmd;
3621	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3622	VMSVGA_3D_CMD_NOTIMPL();
3623	break;
3624	}
3625
3626	case SVGA_3D_CMD_DEAD1:
3627	case SVGA_3D_CMD_DEAD2:
3628	{
3629	VMSVGA_3D_CMD_NOTIMPL();
3630	break;
3631	}
3632
3633	case SVGA_3D_CMD_LOGICOPS_BITBLT:
3634	{
3635	SVGA3dCmdLogicOpsBitBlt pCmd = (SVGA3dCmdLogicOpsBitBlt )pvCmd;
3636	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3637	VMSVGA_3D_CMD_NOTIMPL();
3638	break;
3639	}
3640
3641	case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
3642	{
3643	SVGA3dCmdLogicOpsTransBlt pCmd = (SVGA3dCmdLogicOpsTransBlt )pvCmd;
3644	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3645	VMSVGA_3D_CMD_NOTIMPL();
3646	break;
3647	}
3648
3649	case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
3650	{
3651	SVGA3dCmdLogicOpsStretchBlt pCmd = (SVGA3dCmdLogicOpsStretchBlt )pvCmd;
3652	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3653	VMSVGA_3D_CMD_NOTIMPL();
3654	break;
3655	}
3656
3657	case SVGA_3D_CMD_LOGICOPS_COLORFILL:
3658	{
3659	SVGA3dCmdLogicOpsColorFill pCmd = (SVGA3dCmdLogicOpsColorFill )pvCmd;
3660	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3661	VMSVGA_3D_CMD_NOTIMPL();
3662	break;
3663	}
3664
3665	case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
3666	{
3667	SVGA3dCmdLogicOpsAlphaBlend pCmd = (SVGA3dCmdLogicOpsAlphaBlend )pvCmd;
3668	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3669	VMSVGA_3D_CMD_NOTIMPL();
3670	break;
3671	}
3672
3673	case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
3674	{
3675	SVGA3dCmdLogicOpsClearTypeBlend pCmd = (SVGA3dCmdLogicOpsClearTypeBlend )pvCmd;
3676	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3677	VMSVGA_3D_CMD_NOTIMPL();
3678	break;
3679	}
3680
3681	case SVGA_3D_CMD_SET_OTABLE_BASE:
3682	{
3683	SVGA3dCmdSetOTableBase pCmd = (SVGA3dCmdSetOTableBase )pvCmd;
3684	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3685	VMSVGA_3D_CMD_NOTIMPL();
3686	break;
3687	}
3688
3689	case SVGA_3D_CMD_READBACK_OTABLE:
3690	{
3691	SVGA3dCmdReadbackOTable pCmd = (SVGA3dCmdReadbackOTable )pvCmd;
3692	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3693	VMSVGA_3D_CMD_NOTIMPL();
3694	break;
3695	}
3696
3697	case SVGA_3D_CMD_DEFINE_GB_MOB:
3698	{
3699	SVGA3dCmdDefineGBMob pCmd = (SVGA3dCmdDefineGBMob )pvCmd;
3700	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3701	VMSVGA_3D_CMD_NOTIMPL();
3702	break;
3703	}
3704
3705	case SVGA_3D_CMD_DESTROY_GB_MOB:
3706	{
3707	SVGA3dCmdDestroyGBMob pCmd = (SVGA3dCmdDestroyGBMob )pvCmd;
3708	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3709	VMSVGA_3D_CMD_NOTIMPL();
3710	break;
3711	}
3712
3713	case SVGA_3D_CMD_DEAD3:
3714	{
3715	VMSVGA_3D_CMD_NOTIMPL();
3716	break;
3717	}
3718
3719	case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
3720	{
3721	SVGA3dCmdUpdateGBMobMapping pCmd = (SVGA3dCmdUpdateGBMobMapping )pvCmd;
3722	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3723	VMSVGA_3D_CMD_NOTIMPL();
3724	break;
3725	}
3726
3727	case SVGA_3D_CMD_DEFINE_GB_SURFACE:
3728	{
3729	SVGA3dCmdDefineGBSurface pCmd = (SVGA3dCmdDefineGBSurface )pvCmd;
3730	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3731	VMSVGA_3D_CMD_NOTIMPL();
3732	break;
3733	}
3734
3735	case SVGA_3D_CMD_DESTROY_GB_SURFACE:
3736	{
3737	SVGA3dCmdDestroyGBSurface pCmd = (SVGA3dCmdDestroyGBSurface )pvCmd;
3738	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3739	VMSVGA_3D_CMD_NOTIMPL();
3740	break;
3741	}
3742
3743	case SVGA_3D_CMD_BIND_GB_SURFACE:
3744	{
3745	SVGA3dCmdBindGBSurface pCmd = (SVGA3dCmdBindGBSurface )pvCmd;
3746	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3747	VMSVGA_3D_CMD_NOTIMPL();
3748	break;
3749	}
3750
3751	case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
3752	{
3753	SVGA3dCmdCondBindGBSurface pCmd = (SVGA3dCmdCondBindGBSurface )pvCmd;
3754	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3755	VMSVGA_3D_CMD_NOTIMPL();
3756	break;
3757	}
3758
3759	case SVGA_3D_CMD_UPDATE_GB_IMAGE:
3760	{
3761	SVGA3dCmdUpdateGBImage pCmd = (SVGA3dCmdUpdateGBImage )pvCmd;
3762	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3763	VMSVGA_3D_CMD_NOTIMPL();
3764	break;
3765	}
3766
3767	case SVGA_3D_CMD_UPDATE_GB_SURFACE:
3768	{
3769	SVGA3dCmdUpdateGBSurface pCmd = (SVGA3dCmdUpdateGBSurface )pvCmd;
3770	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3771	VMSVGA_3D_CMD_NOTIMPL();
3772	break;
3773	}
3774
3775	case SVGA_3D_CMD_READBACK_GB_IMAGE:
3776	{
3777	SVGA3dCmdReadbackGBImage pCmd = (SVGA3dCmdReadbackGBImage )pvCmd;
3778	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3779	VMSVGA_3D_CMD_NOTIMPL();
3780	break;
3781	}
3782
3783	case SVGA_3D_CMD_READBACK_GB_SURFACE:
3784	{
3785	SVGA3dCmdReadbackGBSurface pCmd = (SVGA3dCmdReadbackGBSurface )pvCmd;
3786	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3787	VMSVGA_3D_CMD_NOTIMPL();
3788	break;
3789	}
3790
3791	case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
3792	{
3793	SVGA3dCmdInvalidateGBImage pCmd = (SVGA3dCmdInvalidateGBImage )pvCmd;
3794	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3795	VMSVGA_3D_CMD_NOTIMPL();
3796	break;
3797	}
3798
3799	case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
3800	{
3801	SVGA3dCmdInvalidateGBSurface pCmd = (SVGA3dCmdInvalidateGBSurface )pvCmd;
3802	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3803	VMSVGA_3D_CMD_NOTIMPL();
3804	break;
3805	}
3806
3807	case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
3808	{
3809	SVGA3dCmdDefineGBContext pCmd = (SVGA3dCmdDefineGBContext )pvCmd;
3810	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3811	VMSVGA_3D_CMD_NOTIMPL();
3812	break;
3813	}
3814
3815	case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
3816	{
3817	SVGA3dCmdDestroyGBContext pCmd = (SVGA3dCmdDestroyGBContext )pvCmd;
3818	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3819	VMSVGA_3D_CMD_NOTIMPL();
3820	break;
3821	}
3822
3823	case SVGA_3D_CMD_BIND_GB_CONTEXT:
3824	{
3825	SVGA3dCmdBindGBContext pCmd = (SVGA3dCmdBindGBContext )pvCmd;
3826	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3827	VMSVGA_3D_CMD_NOTIMPL();
3828	break;
3829	}
3830
3831	case SVGA_3D_CMD_READBACK_GB_CONTEXT:
3832	{
3833	SVGA3dCmdReadbackGBContext pCmd = (SVGA3dCmdReadbackGBContext )pvCmd;
3834	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3835	VMSVGA_3D_CMD_NOTIMPL();
3836	break;
3837	}
3838
3839	case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
3840	{
3841	SVGA3dCmdInvalidateGBContext pCmd = (SVGA3dCmdInvalidateGBContext )pvCmd;
3842	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3843	VMSVGA_3D_CMD_NOTIMPL();
3844	break;
3845	}
3846
3847	case SVGA_3D_CMD_DEFINE_GB_SHADER:
3848	{
3849	SVGA3dCmdDefineGBShader pCmd = (SVGA3dCmdDefineGBShader )pvCmd;
3850	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3851	VMSVGA_3D_CMD_NOTIMPL();
3852	break;
3853	}
3854
3855	case SVGA_3D_CMD_DESTROY_GB_SHADER:
3856	{
3857	SVGA3dCmdDestroyGBShader pCmd = (SVGA3dCmdDestroyGBShader )pvCmd;
3858	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3859	VMSVGA_3D_CMD_NOTIMPL();
3860	break;
3861	}
3862
3863	case SVGA_3D_CMD_BIND_GB_SHADER:
3864	{
3865	SVGA3dCmdBindGBShader pCmd = (SVGA3dCmdBindGBShader )pvCmd;
3866	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3867	VMSVGA_3D_CMD_NOTIMPL();
3868	break;
3869	}
3870
3871	case SVGA_3D_CMD_SET_OTABLE_BASE64:
3872	{
3873	SVGA3dCmdSetOTableBase64 pCmd = (SVGA3dCmdSetOTableBase64 )pvCmd;
3874	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3875	VMSVGA_3D_CMD_NOTIMPL();
3876	break;
3877	}
3878
3879	case SVGA_3D_CMD_BEGIN_GB_QUERY:
3880	{
3881	SVGA3dCmdBeginGBQuery pCmd = (SVGA3dCmdBeginGBQuery )pvCmd;
3882	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3883	VMSVGA_3D_CMD_NOTIMPL();
3884	break;
3885	}
3886
3887	case SVGA_3D_CMD_END_GB_QUERY:
3888	{
3889	SVGA3dCmdEndGBQuery pCmd = (SVGA3dCmdEndGBQuery )pvCmd;
3890	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3891	VMSVGA_3D_CMD_NOTIMPL();
3892	break;
3893	}
3894
3895	case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
3896	{
3897	SVGA3dCmdWaitForGBQuery pCmd = (SVGA3dCmdWaitForGBQuery )pvCmd;
3898	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3899	VMSVGA_3D_CMD_NOTIMPL();
3900	break;
3901	}
3902
3903	case SVGA_3D_CMD_NOP:
3904	{
3905	/* Apparently there is nothing to do. */
3906	break;
3907	}
3908
3909	case SVGA_3D_CMD_ENABLE_GART:
3910	{
3911	SVGA3dCmdEnableGart pCmd = (SVGA3dCmdEnableGart )pvCmd;
3912	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3913	VMSVGA_3D_CMD_NOTIMPL();
3914	break;
3915	}
3916
3917	case SVGA_3D_CMD_DISABLE_GART:
3918	{
3919	/* No corresponding SVGA3dCmd structure. */
3920	VMSVGA_3D_CMD_NOTIMPL();
3921	break;
3922	}
3923
3924	case SVGA_3D_CMD_MAP_MOB_INTO_GART:
3925	{
3926	SVGA3dCmdMapMobIntoGart pCmd = (SVGA3dCmdMapMobIntoGart )pvCmd;
3927	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3928	VMSVGA_3D_CMD_NOTIMPL();
3929	break;
3930	}
3931
3932	case SVGA_3D_CMD_UNMAP_GART_RANGE:
3933	{
3934	SVGA3dCmdUnmapGartRange pCmd = (SVGA3dCmdUnmapGartRange )pvCmd;
3935	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3936	VMSVGA_3D_CMD_NOTIMPL();
3937	break;
3938	}
3939
3940	case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
3941	{
3942	SVGA3dCmdDefineGBScreenTarget pCmd = (SVGA3dCmdDefineGBScreenTarget )pvCmd;
3943	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3944	VMSVGA_3D_CMD_NOTIMPL();
3945	break;
3946	}
3947
3948	case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
3949	{
3950	SVGA3dCmdDestroyGBScreenTarget pCmd = (SVGA3dCmdDestroyGBScreenTarget )pvCmd;
3951	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3952	VMSVGA_3D_CMD_NOTIMPL();
3953	break;
3954	}
3955
3956	case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
3957	{
3958	SVGA3dCmdBindGBScreenTarget pCmd = (SVGA3dCmdBindGBScreenTarget )pvCmd;
3959	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3960	VMSVGA_3D_CMD_NOTIMPL();
3961	break;
3962	}
3963
3964	case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
3965	{
3966	SVGA3dCmdUpdateGBScreenTarget pCmd = (SVGA3dCmdUpdateGBScreenTarget )pvCmd;
3967	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3968	VMSVGA_3D_CMD_NOTIMPL();
3969	break;
3970	}
3971
3972	case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
3973	{
3974	SVGA3dCmdReadbackGBImagePartial pCmd = (SVGA3dCmdReadbackGBImagePartial )pvCmd;
3975	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3976	VMSVGA_3D_CMD_NOTIMPL();
3977	break;
3978	}
3979
3980	case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
3981	{
3982	SVGA3dCmdInvalidateGBImagePartial pCmd = (SVGA3dCmdInvalidateGBImagePartial )pvCmd;
3983	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3984	VMSVGA_3D_CMD_NOTIMPL();
3985	break;
3986	}
3987
3988	case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
3989	{
3990	SVGA3dCmdSetGBShaderConstInline pCmd = (SVGA3dCmdSetGBShaderConstInline )pvCmd;
3991	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3992	VMSVGA_3D_CMD_NOTIMPL();
3993	break;
3994	}
3995
3996	case SVGA_3D_CMD_GB_SCREEN_DMA:
3997	{
3998	SVGA3dCmdGBScreenDMA pCmd = (SVGA3dCmdGBScreenDMA )pvCmd;
3999	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4000	VMSVGA_3D_CMD_NOTIMPL();
4001	break;
4002	}
4003
4004	case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4005	{
4006	SVGA3dCmdBindGBSurfaceWithPitch pCmd = (SVGA3dCmdBindGBSurfaceWithPitch )pvCmd;
4007	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4008	VMSVGA_3D_CMD_NOTIMPL();
4009	break;
4010	}
4011
4012	case SVGA_3D_CMD_GB_MOB_FENCE:
4013	{
4014	SVGA3dCmdGBMobFence pCmd = (SVGA3dCmdGBMobFence )pvCmd;
4015	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4016	VMSVGA_3D_CMD_NOTIMPL();
4017	break;
4018	}
4019
4020	case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4021	{
4022	/// @todo SVGA3dCmdDefineGBSurface_v2 is not defined in Mesa 17 header. Mesa 20 has it.
4023	//SVGA3dCmdDefineGBSurface_v2 pCmd = (SVGA3dCmdDefineGBSurface_v2 )pvCmd;
4024	//VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4025	VMSVGA_3D_CMD_NOTIMPL();
4026	break;
4027	}
4028
4029	case SVGA_3D_CMD_DEFINE_GB_MOB64:
4030	{
4031	SVGA3dCmdDefineGBMob64 pCmd = (SVGA3dCmdDefineGBMob64 )pvCmd;
4032	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4033	VMSVGA_3D_CMD_NOTIMPL();
4034	break;
4035	}
4036
4037	case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4038	{
4039	SVGA3dCmdRedefineGBMob64 pCmd = (SVGA3dCmdRedefineGBMob64 )pvCmd;
4040	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4041	VMSVGA_3D_CMD_NOTIMPL();
4042	break;
4043	}
4044
4045	case SVGA_3D_CMD_NOP_ERROR:
4046	{
4047	/* Apparently there is nothing to do. */
4048	break;
4049	}
4050
4051	case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4052	{
4053	SVGA3dCmdSetVertexStreams pCmd = (SVGA3dCmdSetVertexStreams )pvCmd;
4054	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4055	VMSVGA_3D_CMD_NOTIMPL();
4056	break;
4057	}
4058
4059	case SVGA_3D_CMD_SET_VERTEX_DECLS:
4060	{
4061	SVGA3dCmdSetVertexDecls pCmd = (SVGA3dCmdSetVertexDecls )pvCmd;
4062	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4063	VMSVGA_3D_CMD_NOTIMPL();
4064	break;
4065	}
4066
4067	case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4068	{
4069	SVGA3dCmdSetVertexDivisors pCmd = (SVGA3dCmdSetVertexDivisors )pvCmd;
4070	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4071	VMSVGA_3D_CMD_NOTIMPL();
4072	break;
4073	}
4074
4075	case SVGA_3D_CMD_DRAW:
4076	{
4077	/* No corresponding SVGA3dCmd structure. */
4078	VMSVGA_3D_CMD_NOTIMPL();
4079	break;
4080	}
4081
4082	case SVGA_3D_CMD_DRAW_INDEXED:
4083	{
4084	/* No corresponding SVGA3dCmd structure. */
4085	VMSVGA_3D_CMD_NOTIMPL();
4086	break;
4087	}
4088
4089	default:
4090	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
4091	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
4092	rcParse = VERR_NOT_IMPLEMENTED;
4093	break;
4094	}
4095
4096	return rcParse;
4097	}
4098	# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4099	# endif // VBOX_WITH_VMSVGA3D
4100
4101
4102	/*
4103	*
4104	* Handlers for FIFO commands.
4105	*
4106	* Every handler takes the following parameters:
4107	*
4108	* pThis The shared VGA/VMSVGA state.
4109	* pThisCC The VGA/VMSVGA state for ring-3.
4110	* pCmd The command data.
4111	*/
4112
4113
4114	/* SVGA_CMD_UPDATE */
4115	static void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
4116	{
4117	RT_NOREF(pThis);
4118	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4119
4120	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
4121	Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
4122
4123	/** @todo Multiple screens? */
4124	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4125	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
4126	return;
4127
4128	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
4129	}
4130
4131
4132	/* SVGA_CMD_UPDATE_VERBOSE */
4133	static void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
4134	{
4135	RT_NOREF(pThis);
4136	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4137
4138	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
4139	Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
4140
4141	/** @todo Multiple screens? */
4142	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4143	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
4144	return;
4145
4146	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
4147	}
4148
4149
4150	/* SVGA_CMD_RECT_FILL */
4151	static void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
4152	{
4153	RT_NOREF(pThis, pCmd);
4154	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4155
4156	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
4157	Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
4158	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
4159	}
4160
4161
4162	/* SVGA_CMD_RECT_COPY */
4163	static void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
4164	{
4165	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4166
4167	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
4168	Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
4169
4170	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4171	AssertPtrReturnVoid(pScreen);
4172
4173	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4174	ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
4175	ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
4176	ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
4177	ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
4178	ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
4179	ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
4180
4181	vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
4182	pCmd->width, pCmd->height, pThis->vram_size);
4183	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
4184	}
4185
4186
4187	/* SVGA_CMD_RECT_ROP_COPY */
4188	static void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
4189	{
4190	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4191
4192	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
4193	Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
4194
4195	if (pCmd->rop != SVGA_ROP_COPY)
4196	{
4197	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
4198	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
4199	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
4200	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
4201	*/
4202	LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
4203	pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
4204	return;
4205	}
4206
4207	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4208	AssertPtrReturnVoid(pScreen);
4209
4210	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4211	ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
4212	ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
4213	ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
4214	ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
4215	ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
4216	ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
4217
4218	vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
4219	pCmd->width, pCmd->height, pThis->vram_size);
4220	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
4221	}
4222
4223
4224	/* SVGA_CMD_DISPLAY_CURSOR */
4225	static void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
4226	{
4227	RT_NOREF(pThis, pCmd);
4228	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4229
4230	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
4231	Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
4232	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
4233	}
4234
4235
4236	/* SVGA_CMD_MOVE_CURSOR */
4237	static void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
4238	{
4239	RT_NOREF(pThis, pCmd);
4240	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4241
4242	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
4243	Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
4244	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
4245	}
4246
4247
4248	/* SVGA_CMD_DEFINE_CURSOR */
4249	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
4250	{
4251	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4252
4253	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
4254	Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
4255	pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
4256
4257	ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
4258	ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
4259	ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
4260	RT_UNTRUSTED_VALIDATED_FENCE();
4261
4262	uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4263	uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
4264	uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4265
4266	uint8_t const pbSrcAndMask = (uint8_t const )(pCmd + 1);
4267	uint8_t const pbSrcXorMask = (uint8_t const )(pCmd + 1) + cbSrcAndMask;
4268
4269	uint32_t const cx = pCmd->width;
4270	uint32_t const cy = pCmd->height;
4271
4272	/*
4273	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
4274	* The AND data uses 8-bit aligned scanlines.
4275	* The XOR data must be starting on a 32-bit boundrary.
4276	*/
4277	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
4278	uint32_t cbDstAndMask = cbDstAndLine * cy;
4279	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
4280	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
4281
4282	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
4283	AssertReturnVoid(pbCopy);
4284
4285	/* Convert the AND mask. */
4286	uint8_t *pbDst = pbCopy;
4287	uint8_t const *pbSrc = pbSrcAndMask;
4288	switch (pCmd->andMaskDepth)
4289	{
4290	case 1:
4291	if (cbSrcAndLine == cbDstAndLine)
4292	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
4293	else
4294	{
4295	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
4296	for (uint32_t y = 0; y < cy; y++)
4297	{
4298	memcpy(pbDst, pbSrc, cbDstAndLine);
4299	pbDst += cbDstAndLine;
4300	pbSrc += cbSrcAndLine;
4301	}
4302	}
4303	break;
4304	/* Should take the XOR mask into account for the multi-bit AND mask. */
4305	case 8:
4306	for (uint32_t y = 0; y < cy; y++)
4307	{
4308	for (uint32_t x = 0; x < cx; )
4309	{
4310	uint8_t bDst = 0;
4311	uint8_t fBit = 0x80;
4312	do
4313	{
4314	uintptr_t const idxPal = pbSrc[x] * 3;
4315	if ((( pThis->last_palette[idxPal]
4316	\| (pThis->last_palette[idxPal] >> 8)
4317	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
4318	bDst \|= fBit;
4319	fBit >>= 1;
4320	x++;
4321	} while (x < cx && (x & 7));
4322	pbDst[(x - 1) / 8] = bDst;
4323	}
4324	pbDst += cbDstAndLine;
4325	pbSrc += cbSrcAndLine;
4326	}
4327	break;
4328	case 15:
4329	for (uint32_t y = 0; y < cy; y++)
4330	{
4331	for (uint32_t x = 0; x < cx; )
4332	{
4333	uint8_t bDst = 0;
4334	uint8_t fBit = 0x80;
4335	do
4336	{
4337	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
4338	bDst \|= fBit;
4339	fBit >>= 1;
4340	x++;
4341	} while (x < cx && (x & 7));
4342	pbDst[(x - 1) / 8] = bDst;
4343	}
4344	pbDst += cbDstAndLine;
4345	pbSrc += cbSrcAndLine;
4346	}
4347	break;
4348	case 16:
4349	for (uint32_t y = 0; y < cy; y++)
4350	{
4351	for (uint32_t x = 0; x < cx; )
4352	{
4353	uint8_t bDst = 0;
4354	uint8_t fBit = 0x80;
4355	do
4356	{
4357	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
4358	bDst \|= fBit;
4359	fBit >>= 1;
4360	x++;
4361	} while (x < cx && (x & 7));
4362	pbDst[(x - 1) / 8] = bDst;
4363	}
4364	pbDst += cbDstAndLine;
4365	pbSrc += cbSrcAndLine;
4366	}
4367	break;
4368	case 24:
4369	for (uint32_t y = 0; y < cy; y++)
4370	{
4371	for (uint32_t x = 0; x < cx; )
4372	{
4373	uint8_t bDst = 0;
4374	uint8_t fBit = 0x80;
4375	do
4376	{
4377	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
4378	bDst \|= fBit;
4379	fBit >>= 1;
4380	x++;
4381	} while (x < cx && (x & 7));
4382	pbDst[(x - 1) / 8] = bDst;
4383	}
4384	pbDst += cbDstAndLine;
4385	pbSrc += cbSrcAndLine;
4386	}
4387	break;
4388	case 32:
4389	for (uint32_t y = 0; y < cy; y++)
4390	{
4391	for (uint32_t x = 0; x < cx; )
4392	{
4393	uint8_t bDst = 0;
4394	uint8_t fBit = 0x80;
4395	do
4396	{
4397	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
4398	bDst \|= fBit;
4399	fBit >>= 1;
4400	x++;
4401	} while (x < cx && (x & 7));
4402	pbDst[(x - 1) / 8] = bDst;
4403	}
4404	pbDst += cbDstAndLine;
4405	pbSrc += cbSrcAndLine;
4406	}
4407	break;
4408	default:
4409	RTMemFreeZ(pbCopy, cbCopy);
4410	AssertFailedReturnVoid();
4411	}
4412
4413	/* Convert the XOR mask. */
4414	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
4415	pbSrc = pbSrcXorMask;
4416	switch (pCmd->xorMaskDepth)
4417	{
4418	case 1:
4419	for (uint32_t y = 0; y < cy; y++)
4420	{
4421	for (uint32_t x = 0; x < cx; )
4422	{
4423	/* most significant bit is the left most one. */
4424	uint8_t bSrc = pbSrc[x / 8];
4425	do
4426	{
4427	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
4428	bSrc <<= 1;
4429	x++;
4430	} while ((x & 7) && x < cx);
4431	}
4432	pbSrc += cbSrcXorLine;
4433	}
4434	break;
4435	case 8:
4436	for (uint32_t y = 0; y < cy; y++)
4437	{
4438	for (uint32_t x = 0; x < cx; x++)
4439	{
4440	uint32_t u = pThis->last_palette[pbSrc[x]];
4441	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
4442	}
4443	pbSrc += cbSrcXorLine;
4444	}
4445	break;
4446	case 15: /* Src: RGB-5-5-5 */
4447	for (uint32_t y = 0; y < cy; y++)
4448	{
4449	for (uint32_t x = 0; x < cx; x++)
4450	{
4451	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
4452	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
4453	((uValue >> 5) & 0x1f) << 3,
4454	((uValue >> 10) & 0x1f) << 3, 0);
4455	}
4456	pbSrc += cbSrcXorLine;
4457	}
4458	break;
4459	case 16: /* Src: RGB-5-6-5 */
4460	for (uint32_t y = 0; y < cy; y++)
4461	{
4462	for (uint32_t x = 0; x < cx; x++)
4463	{
4464	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
4465	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
4466	((uValue >> 5) & 0x3f) << 2,
4467	((uValue >> 11) & 0x1f) << 3, 0);
4468	}
4469	pbSrc += cbSrcXorLine;
4470	}
4471	break;
4472	case 24:
4473	for (uint32_t y = 0; y < cy; y++)
4474	{
4475	for (uint32_t x = 0; x < cx; x++)
4476	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
4477	pbSrc += cbSrcXorLine;
4478	}
4479	break;
4480	case 32:
4481	for (uint32_t y = 0; y < cy; y++)
4482	{
4483	for (uint32_t x = 0; x < cx; x++)
4484	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
4485	pbSrc += cbSrcXorLine;
4486	}
4487	break;
4488	default:
4489	RTMemFreeZ(pbCopy, cbCopy);
4490	AssertFailedReturnVoid();
4491	}
4492
4493	/*
4494	* Pass it to the frontend/whatever.
4495	*/
4496	vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /fAlpha/, pCmd->hotspotX, pCmd->hotspotY,
4497	cx, cy, pbCopy, cbCopy);
4498	}
4499
4500
4501	/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
4502	static void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
4503	{
4504	RT_NOREF(pThis);
4505	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4506
4507	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
4508	Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
4509
4510	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
4511	ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
4512	RT_UNTRUSTED_VALIDATED_FENCE();
4513
4514	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
4515	uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
4516	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
4517	uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
4518	uint32_t cbCursorShape = cbAndMask + cbXorMask;
4519
4520	uint8_t pCursorCopy = (uint8_t )RTMemAlloc(cbCursorShape);
4521	AssertPtrReturnVoid(pCursorCopy);
4522
4523	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
4524	memset(pCursorCopy, 0xff, cbAndMask);
4525	/* Colour data */
4526	memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
4527
4528	vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /fAlpha/, pCmd->hotspotX, pCmd->hotspotY,
4529	pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
4530	}
4531
4532
4533	/* SVGA_CMD_ESCAPE */
4534	static void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
4535	{
4536	RT_NOREF(pThis);
4537	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4538
4539	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
4540
4541	if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
4542	{
4543	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
4544	RT_UNTRUSTED_VALIDATED_FENCE();
4545
4546	uint32_t const cmd = (uint32_t )(pCmd + 1);
4547	Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
4548
4549	switch (cmd)
4550	{
4551	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
4552	{
4553	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pCmd + 1);
4554	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
4555	RT_UNTRUSTED_VALIDATED_FENCE();
4556
4557	uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
4558
4559	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
4560	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
4561	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
4562	RT_NOREF_PV(pVideoCmd);
4563	break;
4564	}
4565
4566	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4567	{
4568	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pCmd + 1);
4569	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
4570	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
4571	RT_NOREF_PV(pVideoCmd);
4572	break;
4573	}
4574
4575	default:
4576	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
4577	break;
4578	}
4579	}
4580	else
4581	Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
4582	}
4583
4584
4585	/* SVGA_CMD_DEFINE_SCREEN */
4586	static void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
4587	{
4588	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4589
4590	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
4591	Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4592	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4593	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4594
4595	uint32_t const idScreen = pCmd->screen.id;
4596	ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
4597
4598	uint32_t const uWidth = pCmd->screen.size.width;
4599	ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
4600
4601	uint32_t const uHeight = pCmd->screen.size.height;
4602	ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
4603
4604	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4605	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4606	ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
4607
4608	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4609	ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
4610
4611	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4612	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4613	ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
4614	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4615	RT_UNTRUSTED_VALIDATED_FENCE();
4616
4617	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
4618	pScreen->fDefined = true;
4619	pScreen->fModified = true;
4620	pScreen->fuScreen = pCmd->screen.flags;
4621	pScreen->idScreen = idScreen;
4622	if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING)))
4623	{
4624	/* Not blanked. */
4625	ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
4626	RT_UNTRUSTED_VALIDATED_FENCE();
4627
4628	pScreen->xOrigin = pCmd->screen.root.x;
4629	pScreen->yOrigin = pCmd->screen.root.y;
4630	pScreen->cWidth = uWidth;
4631	pScreen->cHeight = uHeight;
4632	pScreen->offVRAM = uScreenOffset;
4633	pScreen->cbPitch = cbPitch;
4634	pScreen->cBpp = 32;
4635	}
4636	else
4637	{
4638	/* Screen blanked. Keep old values. */
4639	}
4640
4641	pThis->svga.fGFBRegisters = false;
4642	vmsvgaR3ChangeMode(pThis, pThisCC);
4643
4644	# ifdef VBOX_WITH_VMSVGA3D
4645	if (RT_LIKELY(pThis->svga.f3DEnabled))
4646	vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
4647	# endif
4648	}
4649
4650
4651	/* SVGA_CMD_DESTROY_SCREEN */
4652	static void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
4653	{
4654	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4655
4656	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
4657	Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4658
4659	uint32_t const idScreen = pCmd->screenId;
4660	ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
4661	RT_UNTRUSTED_VALIDATED_FENCE();
4662
4663	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
4664	pScreen->fModified = true;
4665	pScreen->fDefined = false;
4666	pScreen->idScreen = idScreen;
4667
4668	# ifdef VBOX_WITH_VMSVGA3D
4669	if (RT_LIKELY(pThis->svga.f3DEnabled))
4670	vmsvga3dDestroyScreen(pThisCC, pScreen);
4671	# endif
4672	vmsvgaR3ChangeMode(pThis, pThisCC);
4673	}
4674
4675
4676	/* SVGA_CMD_DEFINE_GMRFB */
4677	static void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
4678	{
4679	RT_NOREF(pThis);
4680	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4681
4682	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
4683	Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
4684	pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
4685
4686	pSvgaR3State->GMRFB.ptr = pCmd->ptr;
4687	pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4688	pSvgaR3State->GMRFB.format = pCmd->format;
4689	}
4690
4691
4692	/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
4693	static void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
4694	{
4695	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4696
4697	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
4698	Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4699	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4700
4701	ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
4702	RT_UNTRUSTED_VALIDATED_FENCE();
4703
4704	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4705	AssertPtrReturnVoid(pScreen);
4706
4707	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
4708	AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
4709
4710	/* Clip destRect to the screen dimensions. */
4711	SVGASignedRect screenRect;
4712	screenRect.left = 0;
4713	screenRect.top = 0;
4714	screenRect.right = pScreen->cWidth;
4715	screenRect.bottom = pScreen->cHeight;
4716	SVGASignedRect clipRect = pCmd->destRect;
4717	vmsvgaR3ClipRect(&screenRect, &clipRect);
4718	RT_UNTRUSTED_VALIDATED_FENCE();
4719
4720	uint32_t const width = clipRect.right - clipRect.left;
4721	uint32_t const height = clipRect.bottom - clipRect.top;
4722
4723	if ( width == 0
4724	\|\| height == 0)
4725	return; /* Nothing to do. */
4726
4727	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4728	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4729
4730	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4731	* Prepare parameters for vmsvgaR3GmrTransfer.
4732	*/
4733	AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4734
4735	/* Destination: host buffer which describes the screen 0 VRAM.
4736	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4737	*/
4738	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4739	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4740	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4741	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4742	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4743	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4744	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4745	+ cbScanline * clipRect.top;
4746	int32_t const cbHstPitch = cbScanline;
4747
4748	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4749	SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
4750	uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
4751	+ pSvgaR3State->GMRFB.bytesPerLine * srcy;
4752	int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
4753
4754	int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4755	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4756	gstPtr, offGst, cbGstPitch,
4757	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4758	AssertRC(rc);
4759	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4760	}
4761
4762
4763	/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
4764	static void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
4765	{
4766	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4767
4768	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
4769	/* Note! This can fetch 3d render results as well!! */
4770	Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4771	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4772
4773	ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
4774	RT_UNTRUSTED_VALIDATED_FENCE();
4775
4776	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4777	AssertPtrReturnVoid(pScreen);
4778
4779	/** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
4780	AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
4781
4782	/* Clip destRect to the screen dimensions. */
4783	SVGASignedRect screenRect;
4784	screenRect.left = 0;
4785	screenRect.top = 0;
4786	screenRect.right = pScreen->cWidth;
4787	screenRect.bottom = pScreen->cHeight;
4788	SVGASignedRect clipRect = pCmd->srcRect;
4789	vmsvgaR3ClipRect(&screenRect, &clipRect);
4790	RT_UNTRUSTED_VALIDATED_FENCE();
4791
4792	uint32_t const width = clipRect.right - clipRect.left;
4793	uint32_t const height = clipRect.bottom - clipRect.top;
4794
4795	if ( width == 0
4796	\|\| height == 0)
4797	return; /* Nothing to do. */
4798
4799	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4800	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4801
4802	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4803	* Prepare parameters for vmsvgaR3GmrTransfer.
4804	*/
4805	AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4806
4807	/* Source: host buffer which describes the screen 0 VRAM.
4808	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4809	*/
4810	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4811	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4812	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4813	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4814	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4815	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4816	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4817	+ cbScanline * clipRect.top;
4818	int32_t const cbHstPitch = cbScanline;
4819
4820	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4821	SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
4822	uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
4823	+ pSvgaR3State->GMRFB.bytesPerLine * dsty;
4824	int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
4825
4826	int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4827	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4828	gstPtr, offGst, cbGstPitch,
4829	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4830	AssertRC(rc);
4831	}
4832
4833
4834	/* SVGA_CMD_ANNOTATION_FILL */
4835	static void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
4836	{
4837	RT_NOREF(pThis);
4838	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4839
4840	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
4841	Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
4842
4843	pSvgaR3State->colorAnnotation = pCmd->color;
4844	}
4845
4846
4847	/* SVGA_CMD_ANNOTATION_COPY */
4848	static void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
4849	{
4850	RT_NOREF(pThis, pCmd);
4851	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4852
4853	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
4854	Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
4855
4856	AssertFailed();
4857	}
4858
4859
4860	# ifdef VBOX_WITH_VMSVGA3D
4861	/* SVGA_CMD_DEFINE_GMR2 */
4862	static void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
4863	{
4864	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4865
4866	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
4867	Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
4868
4869	/* Validate current GMR id. */
4870	ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
4871	ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4872	RT_UNTRUSTED_VALIDATED_FENCE();
4873
4874	if (!pCmd->numPages)
4875	{
4876	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
4877	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4878	}
4879	else
4880	{
4881	PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
4882	if (pGMR->cMaxPages)
4883	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
4884
4885	/* Not sure if we should always free the descriptor, but for simplicity
4886	we do so if the new size is smaller than the current. */
4887	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4888	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4889	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4890
4891	pGMR->cMaxPages = pCmd->numPages;
4892	/* The rest is done by the REMAP_GMR2 command. */
4893	}
4894	}
4895
4896
4897	/* SVGA_CMD_REMAP_GMR2 */
4898	static void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
4899	{
4900	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4901
4902	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
4903	Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4904
4905	/* Validate current GMR id and size. */
4906	ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
4907	RT_UNTRUSTED_VALIDATED_FENCE();
4908	PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
4909	ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
4910	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4911	ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4912
4913	if (pCmd->numPages == 0)
4914	return;
4915	RT_UNTRUSTED_VALIDATED_FENCE();
4916
4917	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4918	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4919
4920	/*
4921	* We flatten the existing descriptors into a page array, overwrite the
4922	* pages specified in this command and then recompress the descriptor.
4923	*/
4924	/** @todo Optimize the GMR remap algorithm! */
4925
4926	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4927	uint64_t *paNewPage64 = NULL;
4928	if (pGMR->paDesc)
4929	{
4930	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
4931
4932	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4933	AssertPtrReturnVoid(paNewPage64);
4934
4935	uint32_t idxPage = 0;
4936	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4937	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4938	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4939	AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4940	RT_UNTRUSTED_VALIDATED_FENCE();
4941	}
4942
4943	/* Free the old GMR if present. */
4944	if (pGMR->paDesc)
4945	RTMemFree(pGMR->paDesc);
4946
4947	/* Allocate the maximum amount possible (everything non-continuous) */
4948	PVMSVGAGMRDESCRIPTOR paDescs;
4949	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4950	AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
4951
4952	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4953	{
4954	/** @todo */
4955	AssertFailed();
4956	pGMR->numDescriptors = 0;
4957	}
4958	else
4959	{
4960	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4961	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4962	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4963
4964	uint32_t cPages;
4965	if (paNewPage64)
4966	{
4967	/* Overwrite the old page array with the new page values. */
4968	if (fGCPhys64)
4969	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4970	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4971	else
4972	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4973	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4974
4975	/* Use the updated page array instead of the command data. */
4976	fGCPhys64 = true;
4977	paPages64 = paNewPage64;
4978	cPages = cNewTotalPages;
4979	}
4980	else
4981	cPages = pCmd->numPages;
4982
4983	/* The first page. */
4984	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4985	* applied to paNewPage64. */
4986	RTGCPHYS GCPhys;
4987	if (fGCPhys64)
4988	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4989	else
4990	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4991	paDescs[0].GCPhys = GCPhys;
4992	paDescs[0].numPages = 1;
4993
4994	/* Subsequent pages. */
4995	uint32_t iDescriptor = 0;
4996	for (uint32_t i = 1; i < cPages; i++)
4997	{
4998	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4999	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
5000	else
5001	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
5002
5003	/* Continuous physical memory? */
5004	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
5005	{
5006	Assert(paDescs[iDescriptor].numPages);
5007	paDescs[iDescriptor].numPages++;
5008	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
5009	}
5010	else
5011	{
5012	iDescriptor++;
5013	paDescs[iDescriptor].GCPhys = GCPhys;
5014	paDescs[iDescriptor].numPages = 1;
5015	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
5016	}
5017	}
5018
5019	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
5020	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
5021	pGMR->numDescriptors = iDescriptor + 1;
5022	}
5023
5024	if (paNewPage64)
5025	RTMemFree(paNewPage64);
5026	}
5027	# endif // VBOX_WITH_VMSVGA3D
5028
5029
5030	/*
5031	*
5032	* Command buffer submission.
5033	*
5034	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
5035	*
5036	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
5037	* and wakes up the FIFO thread.
5038	*
5039	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
5040	* the buffer header back to the guest memory.
5041	*
5042	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
5043	*
5044	*/
5045
5046
5047	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
5048	*
5049	* @param pDevIns The device instance.
5050	* @param GCPhysCB Guest physical address of the command buffer header.
5051	* @param status Command buffer status (SVGA_CB_STATUS_*).
5052	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
5053	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
5054	* @thread FIFO or EMT.
5055	*/
5056	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
5057	{
5058	SVGACBHeader hdr;
5059	hdr.status = status;
5060	hdr.errorOffset = errorOffset;
5061	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
5062	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
5063	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
5064	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
5065	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
5066	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
5067	PDMDevHlpPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
5068	}
5069
5070
5071	/** Raise an IRQ.
5072	*
5073	* @param pDevIns The device instance.
5074	* @param pThis The shared VGA/VMSVGA state.
5075	* @param fIRQ SVGA_IRQFLAG_* bits.
5076	* @thread FIFO or EMT.
5077	*/
5078	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t fIRQ)
5079	{
5080	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5081	AssertRC(rc);
5082
5083	if (pThis->svga.u32IrqMask & fIRQ)
5084	{
5085	LogFunc(("Trigger interrupt with status %#x\n", fIRQ));
5086	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, fIRQ);
5087	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5088	}
5089
5090	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5091	}
5092
5093
5094	/** Allocate a command buffer structure.
5095	*
5096	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
5097	* @return Pointer to the allocated command buffer structure.
5098	*/
5099	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
5100	{
5101	if (!pCmdBufCtx)
5102	return NULL;
5103
5104	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
5105	if (pCmdBuf)
5106	{
5107	// RT_ZERO(pCmdBuf->nodeBuffer);
5108	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
5109	// pCmdBuf->GCPhysCB = 0;
5110	// RT_ZERO(pCmdBuf->hdr);
5111	// pCmdBuf->pvCommands = NULL;
5112	}
5113
5114	return pCmdBuf;
5115	}
5116
5117
5118	/** Free a command buffer structure.
5119	*
5120	* @param pCmdBuf The command buffer pointer.
5121	*/
5122	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
5123	{
5124	if (pCmdBuf)
5125	RTMemFree(pCmdBuf->pvCommands);
5126	RTMemFree(pCmdBuf);
5127	}
5128
5129
5130	/** Initialize a command buffer context.
5131	*
5132	* @param pCmdBufCtx The command buffer context.
5133	*/
5134	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
5135	{
5136	RTListInit(&pCmdBufCtx->listSubmitted);
5137	pCmdBufCtx->cSubmitted = 0;
5138	}
5139
5140
5141	/** Destroy a command buffer context.
5142	*
5143	* @param pCmdBufCtx The command buffer context pointer.
5144	*/
5145	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
5146	{
5147	if (!pCmdBufCtx)
5148	return;
5149
5150	if (pCmdBufCtx->listSubmitted.pNext)
5151	{
5152	/* If the list has been initialized. */
5153	PVMSVGACMDBUF pIter, pNext;
5154	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
5155	{
5156	RTListNodeRemove(&pIter->nodeBuffer);
5157	--pCmdBufCtx->cSubmitted;
5158	vmsvgaR3CmdBufFree(pIter);
5159	}
5160	}
5161	Assert(pCmdBufCtx->cSubmitted == 0);
5162	pCmdBufCtx->cSubmitted = 0;
5163	}
5164
5165
5166	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
5167	*
5168	* @param pSvgaR3State VMSVGA R3 state.
5169	* @param pCmd The command data.
5170	* @return SVGACBStatus code.
5171	* @thread EMT
5172	*/
5173	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
5174	{
5175	/* Create or destroy a regular command buffer context. */
5176	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
5177	return SVGA_CB_STATUS_COMMAND_ERROR;
5178	RT_UNTRUSTED_VALIDATED_FENCE();
5179
5180	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
5181
5182	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
5183	AssertRC(rc);
5184	if (pCmd->enable)
5185	{
5186	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
5187	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
5188	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
5189	else
5190	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
5191	}
5192	else
5193	{
5194	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
5195	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
5196	}
5197	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
5198
5199	return CBStatus;
5200	}
5201
5202
5203	/** Handles SVGA_DC_CMD_PREEMPT command.
5204	*
5205	* @param pDevIns The device instance.
5206	* @param pSvgaR3State VMSVGA R3 state.
5207	* @param pCmd The command data.
5208	* @return SVGACBStatus code.
5209	* @thread EMT
5210	*/
5211	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
5212	{
5213	/* Remove buffers from the processing queue of the specified context. */
5214	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
5215	return SVGA_CB_STATUS_COMMAND_ERROR;
5216	RT_UNTRUSTED_VALIDATED_FENCE();
5217
5218	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
5219	RTLISTANCHOR listPreempted;
5220
5221	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
5222	AssertRC(rc);
5223	if (pCmd->ignoreIDZero)
5224	{
5225	RTListInit(&listPreempted);
5226
5227	PVMSVGACMDBUF pIter, pNext;
5228	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
5229	{
5230	if (pIter->hdr.id == 0)
5231	continue;
5232
5233	RTListNodeRemove(&pIter->nodeBuffer);
5234	--pCmdBufCtx->cSubmitted;
5235	RTListAppend(&listPreempted, &pIter->nodeBuffer);
5236	}
5237	}
5238	else
5239	{
5240	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
5241	}
5242	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
5243
5244	PVMSVGACMDBUF pIter, pNext;
5245	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
5246	{
5247	RTListNodeRemove(&pIter->nodeBuffer);
5248	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
5249	vmsvgaR3CmdBufFree(pIter);
5250	}
5251
5252	return SVGA_CB_STATUS_COMPLETED;
5253	}
5254
5255
5256	/** @def VMSVGA_INC_CMD_SIZE_BREAK
5257	* Increments the size of the command cbCmd by a_cbMore.
5258	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
5259	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
5260	*/
5261	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
5262	if (1) { \
5263	cbCmd += (a_cbMore); \
5264	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
5265	RT_UNTRUSTED_VALIDATED_FENCE(); \
5266	} else do {} while (0)
5267
5268
5269	/** Processes Device Context command buffer.
5270	*
5271	* @param pDevIns The device instance.
5272	* @param pSvgaR3State VMSVGA R3 state.
5273	* @param pvCommands Pointer to the command buffer.
5274	* @param cbCommands Size of the command buffer.
5275	* @param poffNextCmd Where to store the offset of the first unprocessed command.
5276	* @return SVGACBStatus code.
5277	* @thread EMT
5278	*/
5279	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
5280	{
5281	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
5282
5283	uint8_t const pu8Cmd = (uint8_t )pvCommands;
5284	uint32_t cbRemain = cbCommands;
5285	while (cbRemain)
5286	{
5287	/* Command identifier is a 32 bit value. */
5288	if (cbRemain < sizeof(uint32_t))
5289	{
5290	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
5291	break;
5292	}
5293
5294	/* Fetch the command id. */
5295	uint32_t const cmdId = (uint32_t )pu8Cmd;
5296	uint32_t cbCmd = sizeof(uint32_t);
5297	switch (cmdId)
5298	{
5299	case SVGA_DC_CMD_NOP:
5300	{
5301	/* NOP */
5302	break;
5303	}
5304
5305	case SVGA_DC_CMD_START_STOP_CONTEXT:
5306	{
5307	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
5308	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5309	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
5310	break;
5311	}
5312
5313	case SVGA_DC_CMD_PREEMPT:
5314	{
5315	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
5316	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5317	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
5318	break;
5319	}
5320
5321	default:
5322	{
5323	/* Unsupported command. */
5324	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
5325	break;
5326	}
5327	}
5328
5329	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
5330	break;
5331
5332	pu8Cmd += cbCmd;
5333	cbRemain -= cbCmd;
5334	}
5335
5336	Assert(cbRemain <= cbCommands);
5337	*poffNextCmd = cbCommands - cbRemain;
5338	return CBstatus;
5339	}
5340
5341
5342	/** Submits a device context command buffer for synchronous processing.
5343	*
5344	* @param pDevIns The device instance.
5345	* @param pThisCC The VGA/VMSVGA state for the current context.
5346	* @param ppCmdBuf Pointer to the command buffer pointer.
5347	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
5348	* @param poffNextCmd Where to store the offset of the first unprocessed command.
5349	* @return SVGACBStatus code.
5350	* @thread EMT
5351	*/
5352	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
5353	{
5354	/* Synchronously process the device context commands. */
5355	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5356	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
5357	}
5358
5359	/** Submits a command buffer for asynchronous processing by the FIFO thread.
5360	*
5361	* @param pDevIns The device instance.
5362	* @param pThis The shared VGA/VMSVGA state.
5363	* @param pThisCC The VGA/VMSVGA state for the current context.
5364	* @param ppCmdBuf Pointer to the command buffer pointer.
5365	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
5366	* @return SVGACBStatus code.
5367	* @thread EMT
5368	*/
5369	static SVGACBStatus vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
5370	{
5371	/* Command buffer submission. */
5372	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5373
5374	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
5375
5376	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
5377	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
5378
5379	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
5380	AssertRC(rc);
5381
5382	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
5383	{
5384	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
5385	++pCmdBufCtx->cSubmitted;
5386	ppCmdBuf = NULL; / Consume the buffer. */
5387	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
5388	}
5389	else
5390	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
5391
5392	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
5393
5394	/* Inform the FIFO thread. */
5395	if (*ppCmdBuf == NULL)
5396	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5397
5398	return CBstatus;
5399	}
5400
5401
5402	/** SVGA_REG_COMMAND_LOW write handler.
5403	* Submits a command buffer to the FIFO thread or processes a device context command.
5404	*
5405	* @param pDevIns The device instance.
5406	* @param pThis The shared VGA/VMSVGA state.
5407	* @param pThisCC The VGA/VMSVGA state for the current context.
5408	* @param GCPhysCB Guest physical address of the command buffer header.
5409	* @param CBCtx Context the command buffer is submitted to.
5410	* @thread EMT
5411	*/
5412	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
5413	{
5414	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5415
5416	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
5417	uint32_t offNextCmd = 0;
5418	uint32_t fIRQ = 0;
5419
5420	/* Get the context if the device has the capability. */
5421	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
5422	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
5423	{
5424	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
5425	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
5426	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
5427	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
5428	RT_UNTRUSTED_VALIDATED_FENCE();
5429	}
5430
5431	/* Allocate a new command buffer. */
5432	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
5433	if (RT_LIKELY(pCmdBuf))
5434	{
5435	pCmdBuf->GCPhysCB = GCPhysCB;
5436
5437	int rc = PDMDevHlpPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
5438	if (RT_SUCCESS(rc))
5439	{
5440	/* Verify the command buffer header. */
5441	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
5442	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ)) == 0 /* No unexpected flags. */
5443	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
5444	{
5445	RT_UNTRUSTED_VALIDATED_FENCE();
5446
5447	/* Read the command buffer content. */
5448	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
5449	if (pCmdBuf->pvCommands)
5450	{
5451	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
5452	rc = PDMDevHlpPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
5453	if (RT_SUCCESS(rc))
5454	{
5455	/* Submit the buffer. Device context buffers will be processed synchronously. */
5456	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
5457	/* This usually processes the CB async and sets pCmbBuf to NULL. */
5458	CBstatus = vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, &pCmdBuf);
5459	else
5460	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
5461	}
5462	else
5463	{
5464	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
5465	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
5466	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
5467	}
5468	}
5469	else
5470	{
5471	/* No memory for commands. */
5472	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
5473	}
5474	}
5475	else
5476	{
5477	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
5478	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
5479	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
5480	}
5481	}
5482	else
5483	{
5484	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
5485	ASSERT_GUEST_FAILED();
5486	/* Do not attempt to write the status. */
5487	}
5488
5489	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
5490	vmsvgaR3CmdBufFree(pCmdBuf);
5491	}
5492	else
5493	{
5494	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
5495	ASSERT_GUEST_FAILED();
5496	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
5497	}
5498
5499	if (CBstatus != SVGA_CB_STATUS_NONE)
5500	{
5501	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf->hdr.length, fIRQ));
5502	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
5503	if (fIRQ)
5504	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
5505	}
5506	}
5507
5508
5509	/** Checks if there are some buffers to be processed.
5510	*
5511	* @param pThisCC The VGA/VMSVGA state for the current context.
5512	* @return true if buffers must be processed.
5513	* @thread FIFO
5514	*/
5515	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
5516	{
5517	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5518	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
5519	}
5520
5521
5522	/** Processes a command buffer.
5523	*
5524	* @param pDevIns The device instance.
5525	* @param pThis The shared VGA/VMSVGA state.
5526	* @param pThisCC The VGA/VMSVGA state for the current context.
5527	* @param pvCommands Pointer to the command buffer.
5528	* @param cbCommands Size of the command buffer.
5529	* @param poffNextCmd Where to store the offset of the first unprocessed command.
5530	* @return SVGACBStatus code.
5531	* @thread FIFO
5532	*/
5533	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
5534	{
5535	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
5536	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5537
5538	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
5539
5540	uint8_t const pu8Cmd = (uint8_t )pvCommands;
5541	uint32_t cbRemain = cbCommands;
5542	while (cbRemain)
5543	{
5544	/* Command identifier is a 32 bit value. */
5545	if (cbRemain < sizeof(uint32_t))
5546	{
5547	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
5548	break;
5549	}
5550
5551	/* Fetch the command id.
5552	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
5553	* warning. Because we support some obsolete and deprecated commands, which are not included in
5554	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
5555	*/
5556	uint32_t const cmdId = (uint32_t )pu8Cmd;
5557	uint32_t cbCmd = sizeof(uint32_t);
5558
5559	LogFlowFunc(("%s %d\n", vmsvgaR3FifoCmdToString(cmdId), cmdId));
5560
5561	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
5562	* I.e. pu8Cmd + cbCmd must point to the next command.
5563	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
5564	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
5565	*/
5566	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
5567	switch (cmdId)
5568	{
5569	case SVGA_CMD_INVALID_CMD:
5570	{
5571	/* Nothing to do. */
5572	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
5573	break;
5574	}
5575
5576	case SVGA_CMD_FENCE:
5577	{
5578	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
5579	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5580	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
5581	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
5582
5583	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
5584	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
5585	{
5586	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
5587
5588	uint32_t u32IrqStatus = 0;
5589	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
5590	{
5591	Log(("any fence irq\n"));
5592	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
5593	}
5594	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
5595	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
5596	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
5597	{
5598	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
5599	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
5600	}
5601
5602	if (u32IrqStatus)
5603	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
5604	}
5605	else
5606	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
5607	break;
5608	}
5609
5610	case SVGA_CMD_UPDATE:
5611	{
5612	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
5613	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5614	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
5615	break;
5616	}
5617
5618	case SVGA_CMD_UPDATE_VERBOSE:
5619	{
5620	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
5621	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5622	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
5623	break;
5624	}
5625
5626	case SVGA_CMD_DEFINE_CURSOR:
5627	{
5628	/* Followed by bitmap data. */
5629	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
5630	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5631
5632	/* Figure out the size of the bitmap data. */
5633	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5634	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5635	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5636	RT_UNTRUSTED_VALIDATED_FENCE();
5637
5638	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5639	uint32_t const cbAndMask = cbAndLine * pCmd->height;
5640	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5641	uint32_t const cbXorMask = cbXorLine * pCmd->height;
5642
5643	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
5644	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
5645	break;
5646	}
5647
5648	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
5649	{
5650	/* Followed by bitmap data. */
5651	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
5652	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5653
5654	/* Figure out the size of the bitmap data. */
5655	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5656
5657	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
5658	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
5659	break;
5660	}
5661
5662	case SVGA_CMD_MOVE_CURSOR:
5663	{
5664	/* Deprecated; there should be no driver which requires this command. However, if
5665	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
5666	* alignment.
5667	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5668	*/
5669	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
5670	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5671	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
5672	break;
5673	}
5674
5675	case SVGA_CMD_DISPLAY_CURSOR:
5676	{
5677	/* Deprecated; there should be no driver which requires this command. However, if
5678	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
5679	* alignment.
5680	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5681	*/
5682	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
5683	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5684	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
5685	break;
5686	}
5687
5688	case SVGA_CMD_RECT_FILL:
5689	{
5690	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
5691	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5692	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
5693	break;
5694	}
5695
5696	case SVGA_CMD_RECT_COPY:
5697	{
5698	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
5699	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5700	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
5701	break;
5702	}
5703
5704	case SVGA_CMD_RECT_ROP_COPY:
5705	{
5706	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
5707	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5708	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
5709	break;
5710	}
5711
5712	case SVGA_CMD_ESCAPE:
5713	{
5714	/* Followed by 'size' bytes of data. */
5715	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
5716	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5717
5718	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5719	RT_UNTRUSTED_VALIDATED_FENCE();
5720
5721	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
5722	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
5723	break;
5724	}
5725	# ifdef VBOX_WITH_VMSVGA3D
5726	case SVGA_CMD_DEFINE_GMR2:
5727	{
5728	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
5729	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5730	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
5731	break;
5732	}
5733
5734	case SVGA_CMD_REMAP_GMR2:
5735	{
5736	/* Followed by page descriptors or guest ptr. */
5737	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
5738	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5739
5740	/* Calculate the size of what comes after next and fetch it. */
5741	uint32_t cbMore = 0;
5742	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
5743	cbMore = sizeof(SVGAGuestPtr);
5744	else
5745	{
5746	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
5747	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
5748	{
5749	cbMore = cbPageDesc;
5750	pCmd->numPages = 1;
5751	}
5752	else
5753	{
5754	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5755	cbMore = cbPageDesc * pCmd->numPages;
5756	}
5757	}
5758	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
5759	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
5760	# ifdef DEBUG_GMR_ACCESS
5761	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
5762	# endif
5763	break;
5764	}
5765	# endif // VBOX_WITH_VMSVGA3D
5766	case SVGA_CMD_DEFINE_SCREEN:
5767	{
5768	/* The size of this command is specified by the guest and depends on capabilities. */
5769	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
5770	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
5771	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5772	RT_UNTRUSTED_VALIDATED_FENCE();
5773
5774	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
5775	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
5776	break;
5777	}
5778
5779	case SVGA_CMD_DESTROY_SCREEN:
5780	{
5781	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
5782	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5783	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
5784	break;
5785	}
5786
5787	case SVGA_CMD_DEFINE_GMRFB:
5788	{
5789	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
5790	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5791	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
5792	break;
5793	}
5794
5795	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
5796	{
5797	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
5798	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5799	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
5800	break;
5801	}
5802
5803	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
5804	{
5805	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
5806	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5807	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
5808	break;
5809	}
5810
5811	case SVGA_CMD_ANNOTATION_FILL:
5812	{
5813	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
5814	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5815	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
5816	break;
5817	}
5818
5819	case SVGA_CMD_ANNOTATION_COPY:
5820	{
5821	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
5822	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5823	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
5824	break;
5825	}
5826
5827	default:
5828	{
5829	# ifdef VBOX_WITH_VMSVGA3D
5830	if ( cmdId >= SVGA_3D_CMD_BASE
5831	&& cmdId < SVGA_3D_CMD_MAX)
5832	{
5833	RT_UNTRUSTED_VALIDATED_FENCE();
5834
5835	/* All 3d commands start with a common header, which defines the identifier and the size
5836	* of the command. The identifier has been already read. Fetch the size.
5837	*/
5838	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
5839	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
5840	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
5841	if (RT_LIKELY(pThis->svga.f3DEnabled))
5842	{ /* likely */ }
5843	else
5844	{
5845	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
5846	break;
5847	}
5848
5849	/* Command data begins after the 32 bit command length. */
5850	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, cmdId, *pcbMore, pcbMore + 1);
5851	if (RT_SUCCESS(rc))
5852	{ /* likely */ }
5853	else
5854	{
5855	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
5856	break;
5857	}
5858	}
5859	else
5860	# endif // VBOX_WITH_VMSVGA3D
5861	{
5862	/* Unsupported command. */
5863	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5864	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
5865	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
5866	break;
5867	}
5868	}
5869	}
5870
5871	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
5872	break;
5873
5874	pu8Cmd += cbCmd;
5875	cbRemain -= cbCmd;
5876	}
5877
5878	Assert(cbRemain <= cbCommands);
5879	*poffNextCmd = cbCommands - cbRemain;
5880	return CBstatus;
5881	}
5882
5883
5884	/** Process command buffers.
5885	*
5886	* @param pDevIns The device instance.
5887	* @param pThis The shared VGA/VMSVGA state.
5888	* @param pThisCC The VGA/VMSVGA state for the current context.
5889	* @param pThread Handle of the FIFO thread.
5890	* @thread FIFO
5891	*/
5892	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
5893	{
5894	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5895
5896	for (;;)
5897	{
5898	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
5899	break;
5900
5901	/* See if there is a submitted buffer. */
5902	PVMSVGACMDBUF pCmdBuf = NULL;
5903
5904	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
5905	AssertRC(rc);
5906
5907	/* It seems that a higher queue index has a higher priority.
5908	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
5909	*/
5910	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
5911	{
5912	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
5913	if (pCmdBufCtx)
5914	{
5915	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
5916	if (pCmdBuf)
5917	{
5918	Assert(pCmdBufCtx->cSubmitted > 0);
5919	--pCmdBufCtx->cSubmitted;
5920	break;
5921	}
5922	}
5923	}
5924
5925	if (!pCmdBuf)
5926	{
5927	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
5928	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
5929	break;
5930	}
5931
5932	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
5933
5934	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
5935	uint32_t offNextCmd = 0;
5936
5937	/* Process one buffer. */
5938	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd);
5939
5940	uint32_t fIRQ = 0;
5941	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
5942	fIRQ \|= SVGA_IRQFLAG_COMMAND_BUFFER;
5943	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
5944	fIRQ \|= SVGA_IRQFLAG_ERROR;
5945
5946	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
5947	if (fIRQ)
5948	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
5949
5950	vmsvgaR3CmdBufFree(pCmdBuf);
5951	}
5952	}
5953
5954
5955	/**
5956	* Worker for vmsvgaR3FifoThread that handles an external command.
5957	*
5958	* @param pDevIns The device instance.
5959	* @param pThis The shared VGA/VMSVGA instance data.
5960	* @param pThisCC The VGA/VMSVGA state for ring-3.
5961	*/
5962	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
5963	{
5964	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
5965	switch (pThis->svga.u8FIFOExtCommand)
5966	{
5967	case VMSVGA_FIFO_EXTCMD_RESET:
5968	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
5969	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
5970
5971	vmsvgaR3ResetScreens(pThis, pThisCC);
5972	# ifdef VBOX_WITH_VMSVGA3D
5973	if (pThis->svga.f3DEnabled)
5974	{
5975	/* The 3d subsystem must be reset from the fifo thread. */
5976	vmsvga3dReset(pThisCC);
5977	}
5978	# endif
5979	break;
5980
5981	case VMSVGA_FIFO_EXTCMD_POWEROFF:
5982	Log(("vmsvgaR3FifoLoop: power off.\n"));
5983	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
5984
5985	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
5986	vmsvgaR3ResetScreens(pThis, pThisCC);
5987	break;
5988
5989	case VMSVGA_FIFO_EXTCMD_TERMINATE:
5990	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
5991	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
5992	# ifdef VBOX_WITH_VMSVGA3D
5993	if (pThis->svga.f3DEnabled)
5994	{
5995	/* The 3d subsystem must be shut down from the fifo thread. */
5996	vmsvga3dTerminate(pThisCC);
5997	}
5998	# endif
5999	break;
6000
6001	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
6002	{
6003	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
6004	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
6005	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
6006	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
6007	# ifdef VBOX_WITH_VMSVGA3D
6008	if (pThis->svga.f3DEnabled)
6009	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
6010	# endif
6011	break;
6012	}
6013
6014	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
6015	{
6016	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
6017	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
6018	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
6019	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
6020	# ifdef VBOX_WITH_VMSVGA3D
6021	if (pThis->svga.f3DEnabled)
6022	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
6023	# endif
6024	break;
6025	}
6026
6027	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
6028	{
6029	# ifdef VBOX_WITH_VMSVGA3D
6030	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
6031	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
6032	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
6033	# endif
6034	break;
6035	}
6036
6037
6038	default:
6039	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
6040	break;
6041	}
6042
6043	/*
6044	* Signal the end of the external command.
6045	*/
6046	pThisCC->svga.pvFIFOExtCmdParam = NULL;
6047	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
6048	ASMMemoryFence(); /* paranoia^2 */
6049	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
6050	AssertLogRelRC(rc);
6051	}
6052
6053	/**
6054	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
6055	* doing a job on the FIFO thread (even when it's officially suspended).
6056	*
6057	* @returns VBox status code (fully asserted).
6058	* @param pDevIns The device instance.
6059	* @param pThis The shared VGA/VMSVGA instance data.
6060	* @param pThisCC The VGA/VMSVGA state for ring-3.
6061	* @param uExtCmd The command to execute on the FIFO thread.
6062	* @param pvParam Pointer to command parameters.
6063	* @param cMsWait The time to wait for the command, given in
6064	* milliseconds.
6065	*/
6066	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
6067	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
6068	{
6069	Assert(cMsWait >= RT_MS_1SEC * 5);
6070	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
6071	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
6072
6073	int rc;
6074	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
6075	PDMTHREADSTATE enmState = pThread->enmState;
6076	if (enmState == PDMTHREADSTATE_SUSPENDED)
6077	{
6078	/*
6079	* The thread is suspended, we have to temporarily wake it up so it can
6080	* perform the task.
6081	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
6082	*/
6083	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
6084	/* Post the request. */
6085	pThis->svga.fFifoExtCommandWakeup = true;
6086	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
6087	pThis->svga.u8FIFOExtCommand = uExtCmd;
6088	ASMMemoryFence(); /* paranoia^3 */
6089
6090	/* Resume the thread. */
6091	rc = PDMDevHlpThreadResume(pDevIns, pThread);
6092	AssertLogRelRC(rc);
6093	if (RT_SUCCESS(rc))
6094	{
6095	/* Wait. Take care in case the semaphore was already posted (same as below). */
6096	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
6097	if ( rc == VINF_SUCCESS
6098	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
6099	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
6100	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
6101	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
6102
6103	/* suspend the thread */
6104	pThis->svga.fFifoExtCommandWakeup = false;
6105	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
6106	AssertLogRelRC(rc2);
6107	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
6108	rc = rc2;
6109	}
6110	pThis->svga.fFifoExtCommandWakeup = false;
6111	pThisCC->svga.pvFIFOExtCmdParam = NULL;
6112	}
6113	else if (enmState == PDMTHREADSTATE_RUNNING)
6114	{
6115	/*
6116	* The thread is running, should only happen during reset and vmsvga3dsfc.
6117	* We ASSUME not racing code here, both wrt thread state and ext commands.
6118	*/
6119	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
6120	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
6121
6122	/* Post the request. */
6123	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
6124	pThis->svga.u8FIFOExtCommand = uExtCmd;
6125	ASMMemoryFence(); /* paranoia^2 */
6126	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
6127	AssertLogRelRC(rc);
6128
6129	/* Wait. Take care in case the semaphore was already posted (same as above). */
6130	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
6131	if ( rc == VINF_SUCCESS
6132	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
6133	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
6134	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
6135	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
6136
6137	pThisCC->svga.pvFIFOExtCmdParam = NULL;
6138	}
6139	else
6140	{
6141	/*
6142	* Something is wrong with the thread!
6143	*/
6144	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
6145	rc = VERR_INVALID_STATE;
6146	}
6147	return rc;
6148	}
6149
6150
6151	/**
6152	* Marks the FIFO non-busy, notifying any waiting EMTs.
6153	*
6154	* @param pDevIns The device instance.
6155	* @param pThis The shared VGA/VMSVGA instance data.
6156	* @param pThisCC The VGA/VMSVGA state for ring-3.
6157	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
6158	* @param offFifoMin The start byte offset of the command FIFO.
6159	*/
6160	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
6161	{
6162	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
6163	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
6164	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
6165
6166	/* Wake up any waiting EMTs. */
6167	if (pSVGAState->cBusyDelayedEmts > 0)
6168	{
6169	# ifdef VMSVGA_USE_EMT_HALT_CODE
6170	PVM pVM = PDMDevHlpGetVM(pDevIns);
6171	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
6172	if (idCpu != NIL_VMCPUID)
6173	{
6174	VMR3NotifyCpuDeviceReady(pVM, idCpu);
6175	while (idCpu-- > 0)
6176	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
6177	VMR3NotifyCpuDeviceReady(pVM, idCpu);
6178	}
6179	# else
6180	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
6181	AssertRC(rc2);
6182	# endif
6183	}
6184	}
6185
6186	/**
6187	* Reads (more) payload into the command buffer.
6188	*
6189	* @returns pbBounceBuf on success
6190	* @retval (void *)1 if the thread was requested to stop.
6191	* @retval NULL on FIFO error.
6192	*
6193	* @param cbPayloadReq The number of bytes of payload requested.
6194	* @param pFIFO The FIFO.
6195	* @param offCurrentCmd The FIFO byte offset of the current command.
6196	* @param offFifoMin The start byte offset of the command FIFO.
6197	* @param offFifoMax The end byte offset of the command FIFO.
6198	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
6199	* always sufficient size.
6200	* @param pcbAlreadyRead How much payload we've already read into the bounce
6201	* buffer. (We will NEVER re-read anything.)
6202	* @param pThread The calling PDM thread handle.
6203	* @param pThis The shared VGA/VMSVGA instance data.
6204	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
6205	* statistics collection.
6206	* @param pDevIns The device instance.
6207	*/
6208	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
6209	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
6210	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
6211	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
6212	{
6213	Assert(pbBounceBuf);
6214	Assert(pcbAlreadyRead);
6215	Assert(offFifoMin < offFifoMax);
6216	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
6217	Assert(offFifoMax <= pThis->svga.cbFIFO);
6218
6219	/*
6220	* Check if the requested payload size has already been satisfied .
6221	* .
6222	* When called to read more, the caller is responsible for making sure the .
6223	* new command size (cbRequsted) never is smaller than what has already .
6224	* been read.
6225	*/
6226	uint32_t cbAlreadyRead = *pcbAlreadyRead;
6227	if (cbPayloadReq <= cbAlreadyRead)
6228	{
6229	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
6230	return pbBounceBuf;
6231	}
6232
6233	/*
6234	* Commands bigger than the fifo buffer are invalid.
6235	*/
6236	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
6237	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
6238	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
6239	NULL);
6240
6241	/*
6242	* Move offCurrentCmd past the command dword.
6243	*/
6244	offCurrentCmd += sizeof(uint32_t);
6245	if (offCurrentCmd >= offFifoMax)
6246	offCurrentCmd = offFifoMin;
6247
6248	/*
6249	* Do we have sufficient payload data available already?
6250	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
6251	*/
6252	uint32_t cbAfter, cbBefore;
6253	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
6254	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
6255	if (offNextCmd >= offCurrentCmd)
6256	{
6257	if (RT_LIKELY(offNextCmd < offFifoMax))
6258	cbAfter = offNextCmd - offCurrentCmd;
6259	else
6260	{
6261	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
6262	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
6263	offNextCmd, offFifoMin, offFifoMax));
6264	cbAfter = offFifoMax - offCurrentCmd;
6265	}
6266	cbBefore = 0;
6267	}
6268	else
6269	{
6270	cbAfter = offFifoMax - offCurrentCmd;
6271	if (offNextCmd >= offFifoMin)
6272	cbBefore = offNextCmd - offFifoMin;
6273	else
6274	{
6275	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
6276	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
6277	offNextCmd, offFifoMin, offFifoMax));
6278	cbBefore = 0;
6279	}
6280	}
6281	if (cbAfter + cbBefore < cbPayloadReq)
6282	{
6283	/*
6284	* Insufficient, must wait for it to arrive.
6285	*/
6286	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
6287	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
6288	for (uint32_t i = 0;; i++)
6289	{
6290	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
6291	{
6292	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
6293	return (void *)(uintptr_t)1;
6294	}
6295	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
6296	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
6297
6298	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
6299
6300	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
6301	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
6302	if (offNextCmd >= offCurrentCmd)
6303	{
6304	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
6305	cbBefore = 0;
6306	}
6307	else
6308	{
6309	cbAfter = offFifoMax - offCurrentCmd;
6310	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
6311	}
6312
6313	if (cbAfter + cbBefore >= cbPayloadReq)
6314	break;
6315	}
6316	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
6317	}
6318
6319	/*
6320	* Copy out the memory and update what pcbAlreadyRead points to.
6321	*/
6322	if (cbAfter >= cbPayloadReq)
6323	memcpy(pbBounceBuf + cbAlreadyRead,
6324	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
6325	cbPayloadReq - cbAlreadyRead);
6326	else
6327	{
6328	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
6329	if (cbAlreadyRead < cbAfter)
6330	{
6331	memcpy(pbBounceBuf + cbAlreadyRead,
6332	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
6333	cbAfter - cbAlreadyRead);
6334	cbAlreadyRead = cbAfter;
6335	}
6336	memcpy(pbBounceBuf + cbAlreadyRead,
6337	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
6338	cbPayloadReq - cbAlreadyRead);
6339	}
6340	*pcbAlreadyRead = cbPayloadReq;
6341	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
6342	return pbBounceBuf;
6343	}
6344
6345
6346	/**
6347	* Sends cursor position and visibility information from the FIFO to the front-end.
6348	* @returns SVGA_FIFO_CURSOR_COUNT value used.
6349	*/
6350	static uint32_t
6351	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
6352	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
6353	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
6354	{
6355	/*
6356	* Check if the cursor update counter has changed and try get a stable
6357	* set of values if it has. This is race-prone, especially consindering
6358	* the screen ID, but little we can do about that.
6359	*/
6360	uint32_t x, y, fVisible, idScreen;
6361	for (uint32_t i = 0; ; i++)
6362	{
6363	x = pFIFO[SVGA_FIFO_CURSOR_X];
6364	y = pFIFO[SVGA_FIFO_CURSOR_Y];
6365	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
6366	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
6367	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
6368	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
6369	\|\| i > 3)
6370	break;
6371	if (i == 0)
6372	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
6373	ASMNopPause();
6374	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
6375	}
6376
6377	/*
6378	* Check if anything has changed, as calling into pDrv is not light-weight.
6379	*/
6380	if ( *pxLast == x
6381	&& *pyLast == y
6382	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
6383	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
6384	else
6385	{
6386	/*
6387	* Detected changes.
6388	*
6389	* We handle global, not per-screen visibility information by sending
6390	* pfnVBVAMousePointerShape without shape data.
6391	*/
6392	*pxLast = x;
6393	*pyLast = y;
6394	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
6395	if (idScreen != SVGA_ID_INVALID)
6396	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
6397	else if (*pfLastVisible != fVisible)
6398	{
6399	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
6400	*pfLastVisible = fVisible;
6401	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
6402	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
6403	}
6404	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
6405	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
6406	}
6407
6408	/*
6409	* Update done. Signal this to the guest.
6410	*/
6411	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
6412
6413	return uCursorUpdateCount;
6414	}
6415
6416
6417	/**
6418	* Checks if there is work to be done, either cursor updating or FIFO commands.
6419	*
6420	* @returns true if pending work, false if not.
6421	* @param pThisCC The VGA/VMSVGA state for ring-3.
6422	* @param uLastCursorCount The last cursor update counter value.
6423	*/
6424	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
6425	{
6426	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
6427	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
6428	AssertReturn(pFIFO, false);
6429
6430	if (vmsvgaR3CmdBufHasWork(pThisCC))
6431	return true;
6432
6433	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
6434	return true;
6435
6436	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
6437	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
6438	return true;
6439
6440	return false;
6441	}
6442
6443
6444	/**
6445	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
6446	*
6447	* @param pDevIns The device instance.
6448	* @param pThis The shared VGA/VMSVGA instance data.
6449	* @param pThisCC The VGA/VMSVGA state for ring-3.
6450	*/
6451	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
6452	{
6453	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
6454	to recheck it before doing the signalling. */
6455	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
6456	&& pThis->svga.fFIFOThreadSleeping)
6457	{
6458	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
6459	AssertRC(rc);
6460	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
6461	}
6462	}
6463
6464
6465	/**
6466	* Called by the FIFO thread to process pending actions.
6467	*
6468	* @param pDevIns The device instance.
6469	* @param pThis The shared VGA/VMSVGA instance data.
6470	* @param pThisCC The VGA/VMSVGA state for ring-3.
6471	*/
6472	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
6473	{
6474	RT_NOREF(pDevIns);
6475
6476	/* Currently just mode changes. */
6477	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
6478	{
6479	vmsvgaR3ChangeMode(pThis, pThisCC);
6480	# ifdef VBOX_WITH_VMSVGA3D
6481	if (pThisCC->svga.p3dState != NULL)
6482	vmsvga3dChangeMode(pThisCC);
6483	# endif
6484	}
6485	}
6486
6487
6488	/*
6489	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
6490	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
6491	*/
6492	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
6493	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
6494	*
6495	* Will break out of the switch on failure.
6496	* Will restart and quit the loop if the thread was requested to stop.
6497	*
6498	* @param a_PtrVar Request variable pointer.
6499	* @param a_Type Request typedef (not pointer) for casting.
6500	* @param a_cbPayloadReq How much payload to fetch.
6501	* @remarks Accesses a bunch of variables in the current scope!
6502	*/
6503	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
6504	if (1) { \
6505	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
6506	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
6507	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
6508	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
6509	} else do {} while (0)
6510	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
6511	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
6512	* buffer after figuring out the actual command size.
6513	*
6514	* Will break out of the switch on failure.
6515	*
6516	* @param a_PtrVar Request variable pointer.
6517	* @param a_Type Request typedef (not pointer) for casting.
6518	* @param a_cbPayloadReq How much payload to fetch.
6519	* @remarks Accesses a bunch of variables in the current scope!
6520	*/
6521	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
6522	if (1) { \
6523	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
6524	} else do {} while (0)
6525
6526	/**
6527	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
6528	*/
6529	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
6530	{
6531	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6532	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6533	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6534	int rc;
6535
6536	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
6537	if (pThis->svga.f3DEnabled)
6538	{
6539	/* The FIFO thread may use X API for accelerated screen output. */
6540	XInitThreads();
6541	}
6542	# endif
6543
6544	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
6545	return VINF_SUCCESS;
6546
6547	/*
6548	* Special mode where we only execute an external command and the go back
6549	* to being suspended. Currently, all ext cmds ends up here, with the reset
6550	* one also being eligble for runtime execution further down as well.
6551	*/
6552	if (pThis->svga.fFifoExtCommandWakeup)
6553	{
6554	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
6555	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
6556	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
6557	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
6558	else
6559	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
6560	return VINF_SUCCESS;
6561	}
6562
6563
6564	/*
6565	* Signal the semaphore to make sure we don't wait for 250ms after a
6566	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
6567	*/
6568	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
6569
6570	/*
6571	* Allocate a bounce buffer for command we get from the FIFO.
6572	* (All code must return via the end of the function to free this buffer.)
6573	*/
6574	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
6575	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
6576
6577	/*
6578	* Polling/sleep interval config.
6579	*
6580	* We wait for an a short interval if the guest has recently given us work
6581	* to do, but the interval increases the longer we're kept idle. Once we've
6582	* reached the refresh timer interval, we'll switch to extended waits,
6583	* depending on it or the guest to kick us into action when needed.
6584	*
6585	* Should the refresh time go fishing, we'll just continue increasing the
6586	* sleep length till we reaches the 250 ms max after about 16 seconds.
6587	*/
6588	RTMSINTERVAL const cMsMinSleep = 16;
6589	RTMSINTERVAL const cMsIncSleep = 2;
6590	RTMSINTERVAL const cMsMaxSleep = 250;
6591	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
6592	RTMSINTERVAL cMsSleep = cMsMaxSleep;
6593
6594	/*
6595	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
6596	*
6597	* Initialize with values that will detect an update from the guest.
6598	* Make sure that if the guest never updates the cursor position, then the device does not report it.
6599	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
6600	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
6601	*/
6602	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
6603	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
6604	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
6605	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
6606	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
6607
6608	/*
6609	* The FIFO loop.
6610	*/
6611	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
6612	bool fBadOrDisabledFifo = false;
6613	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
6614	{
6615	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
6616	/*
6617	* Should service the run loop every so often.
6618	*/
6619	if (pThis->svga.f3DEnabled)
6620	vmsvga3dCocoaServiceRunLoop();
6621	# endif
6622
6623	/* First check any pending actions. */
6624	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
6625
6626	/*
6627	* Unless there's already work pending, go to sleep for a short while.
6628	* (See polling/sleep interval config above.)
6629	*/
6630	if ( fBadOrDisabledFifo
6631	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6632	{
6633	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
6634	Assert(pThis->cMilliesRefreshInterval > 0);
6635	if (cMsSleep < pThis->cMilliesRefreshInterval)
6636	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
6637	else
6638	{
6639	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
6640	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
6641	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
6642	# endif
6643	if ( !fBadOrDisabledFifo
6644	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6645	rc = VINF_SUCCESS;
6646	else
6647	{
6648	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
6649	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
6650	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
6651	}
6652	}
6653	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
6654	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
6655	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
6656	{
6657	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
6658	break;
6659	}
6660	}
6661	else
6662	rc = VINF_SUCCESS;
6663	fBadOrDisabledFifo = false;
6664	if (rc == VERR_TIMEOUT)
6665	{
6666	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6667	{
6668	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
6669	continue;
6670	}
6671	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
6672
6673	Log(("vmsvgaR3FifoLoop: timeout\n"));
6674	}
6675	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6676	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
6677	cMsSleep = cMsMinSleep;
6678
6679	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
6680	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
6681	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
6682
6683	/*
6684	* Handle external commands (currently only reset).
6685	*/
6686	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
6687	{
6688	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
6689	continue;
6690	}
6691
6692	/*
6693	* The device must be enabled and configured.
6694	*/
6695	if ( !pThis->svga.fEnabled
6696	\|\| !pThis->svga.fConfigured)
6697	{
6698	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
6699	fBadOrDisabledFifo = true;
6700	cMsSleep = cMsMaxSleep; /* cheat */
6701	continue;
6702	}
6703
6704	/*
6705	* Get and check the min/max values. We ASSUME that they will remain
6706	* unchanged while we process requests. A further ASSUMPTION is that
6707	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
6708	* we don't read it back while in the loop.
6709	*/
6710	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
6711	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
6712	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
6713	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
6714	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
6715	\|\| offFifoMax <= offFifoMin
6716	\|\| offFifoMax > pThis->svga.cbFIFO
6717	\|\| (offFifoMax & 3) != 0
6718	\|\| (offFifoMin & 3) != 0
6719	\|\| offCurrentCmd < offFifoMin
6720	\|\| offCurrentCmd > offFifoMax))
6721	{
6722	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
6723	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
6724	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
6725	fBadOrDisabledFifo = true;
6726	continue;
6727	}
6728	RT_UNTRUSTED_VALIDATED_FENCE();
6729	if (RT_UNLIKELY(offCurrentCmd & 3))
6730	{
6731	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
6732	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
6733	offCurrentCmd &= ~UINT32_C(3);
6734	}
6735
6736	/*
6737	* Update the cursor position before we start on the FIFO commands.
6738	*/
6739	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
6740	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
6741	{
6742	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
6743	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
6744	{ /* halfways likely */ }
6745	else
6746	{
6747	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
6748	&xLastCursor, &yLastCursor, &fLastCursorVisible);
6749	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
6750	}
6751	}
6752
6753	/*
6754	* Mark the FIFO as busy.
6755	*/
6756	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
6757	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
6758	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
6759
6760	/*
6761	* Process all submitted command buffers.
6762	*/
6763	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
6764
6765	/*
6766	* Execute all queued FIFO commands.
6767	* Quit if pending external command or changes in the thread state.
6768	*/
6769	bool fDone = false;
6770	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
6771	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
6772	{
6773	uint32_t cbPayload = 0;
6774	uint32_t u32IrqStatus = 0;
6775
6776	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
6777
6778	/* First check any pending actions. */
6779	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
6780
6781	/* Check for pending external commands (reset). */
6782	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
6783	break;
6784
6785	/*
6786	* Process the command.
6787	*/
6788	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
6789	* warning. Because we implement some obsolete and deprecated commands, which are not included in
6790	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
6791	*/
6792	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
6793	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
6794	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
6795	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
6796	switch (enmCmdId)
6797	{
6798	case SVGA_CMD_INVALID_CMD:
6799	/* Nothing to do. */
6800	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
6801	break;
6802
6803	case SVGA_CMD_FENCE:
6804	{
6805	SVGAFifoCmdFence *pCmdFence;
6806	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
6807	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
6808	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
6809	{
6810	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
6811	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
6812
6813	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
6814	{
6815	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
6816	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
6817	}
6818	else
6819	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
6820	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
6821	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
6822	{
6823	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
6824	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
6825	}
6826	}
6827	else
6828	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
6829	break;
6830	}
6831
6832	case SVGA_CMD_UPDATE:
6833	{
6834	SVGAFifoCmdUpdate *pCmd;
6835	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
6836	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
6837	break;
6838	}
6839
6840	case SVGA_CMD_UPDATE_VERBOSE:
6841	{
6842	SVGAFifoCmdUpdateVerbose *pCmd;
6843	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
6844	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
6845	break;
6846	}
6847
6848	case SVGA_CMD_DEFINE_CURSOR:
6849	{
6850	/* Followed by bitmap data. */
6851	SVGAFifoCmdDefineCursor *pCmd;
6852	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
6853
6854	/* Figure out the size of the bitmap data. */
6855	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
6856	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
6857	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
6858	RT_UNTRUSTED_VALIDATED_FENCE();
6859
6860	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6861	uint32_t const cbAndMask = cbAndLine * pCmd->height;
6862	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6863	uint32_t const cbXorMask = cbXorLine * pCmd->height;
6864
6865	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
6866	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
6867	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
6868	break;
6869	}
6870
6871	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
6872	{
6873	/* Followed by bitmap data. */
6874	SVGAFifoCmdDefineAlphaCursor *pCmd;
6875	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
6876
6877	/* Figure out the size of the bitmap data. */
6878	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
6879
6880	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
6881	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
6882	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
6883	break;
6884	}
6885
6886	case SVGA_CMD_MOVE_CURSOR:
6887	{
6888	/* Deprecated; there should be no driver which requires this command. However, if
6889	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
6890	* alignment.
6891	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
6892	*/
6893	SVGAFifoCmdMoveCursor *pCmd;
6894	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
6895	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
6896	break;
6897	}
6898
6899	case SVGA_CMD_DISPLAY_CURSOR:
6900	{
6901	/* Deprecated; there should be no driver which requires this command. However, if
6902	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
6903	* alignment.
6904	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
6905	*/
6906	SVGAFifoCmdDisplayCursor *pCmd;
6907	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
6908	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
6909	break;
6910	}
6911
6912	case SVGA_CMD_RECT_FILL:
6913	{
6914	SVGAFifoCmdRectFill *pCmd;
6915	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
6916	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
6917	break;
6918	}
6919
6920	case SVGA_CMD_RECT_COPY:
6921	{
6922	SVGAFifoCmdRectCopy *pCmd;
6923	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
6924	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
6925	break;
6926	}
6927
6928	case SVGA_CMD_RECT_ROP_COPY:
6929	{
6930	SVGAFifoCmdRectRopCopy *pCmd;
6931	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
6932	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
6933	break;
6934	}
6935
6936	case SVGA_CMD_ESCAPE:
6937	{
6938	/* Followed by 'size' bytes of data. */
6939	SVGAFifoCmdEscape *pCmd;
6940	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
6941
6942	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
6943	RT_UNTRUSTED_VALIDATED_FENCE();
6944
6945	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
6946	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
6947	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
6948	break;
6949	}
6950	# ifdef VBOX_WITH_VMSVGA3D
6951	case SVGA_CMD_DEFINE_GMR2:
6952	{
6953	SVGAFifoCmdDefineGMR2 *pCmd;
6954	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
6955	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
6956	break;
6957	}
6958
6959	case SVGA_CMD_REMAP_GMR2:
6960	{
6961	/* Followed by page descriptors or guest ptr. */
6962	SVGAFifoCmdRemapGMR2 *pCmd;
6963	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
6964
6965	/* Calculate the size of what comes after next and fetch it. */
6966	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
6967	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6968	cbCmd += sizeof(SVGAGuestPtr);
6969	else
6970	{
6971	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
6972	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
6973	{
6974	cbCmd += cbPageDesc;
6975	pCmd->numPages = 1;
6976	}
6977	else
6978	{
6979	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
6980	cbCmd += cbPageDesc * pCmd->numPages;
6981	}
6982	}
6983	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
6984	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
6985	# ifdef DEBUG_GMR_ACCESS
6986	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
6987	# endif
6988	break;
6989	}
6990	# endif // VBOX_WITH_VMSVGA3D
6991	case SVGA_CMD_DEFINE_SCREEN:
6992	{
6993	/* The size of this command is specified by the guest and depends on capabilities. */
6994	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
6995
6996	SVGAFifoCmdDefineScreen *pCmd;
6997	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
6998	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
6999	RT_UNTRUSTED_VALIDATED_FENCE();
7000
7001	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
7002	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
7003	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
7004	break;
7005	}
7006
7007	case SVGA_CMD_DESTROY_SCREEN:
7008	{
7009	SVGAFifoCmdDestroyScreen *pCmd;
7010	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
7011	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
7012	break;
7013	}
7014
7015	case SVGA_CMD_DEFINE_GMRFB:
7016	{
7017	SVGAFifoCmdDefineGMRFB *pCmd;
7018	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
7019	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
7020	break;
7021	}
7022
7023	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
7024	{
7025	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
7026	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
7027	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
7028	break;
7029	}
7030
7031	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
7032	{
7033	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
7034	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
7035	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
7036	break;
7037	}
7038
7039	case SVGA_CMD_ANNOTATION_FILL:
7040	{
7041	SVGAFifoCmdAnnotationFill *pCmd;
7042	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
7043	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
7044	break;
7045	}
7046
7047	case SVGA_CMD_ANNOTATION_COPY:
7048	{
7049	SVGAFifoCmdAnnotationCopy *pCmd;
7050	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
7051	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
7052	break;
7053	}
7054
7055	default:
7056	# ifdef VBOX_WITH_VMSVGA3D
7057	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
7058	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
7059	{
7060	RT_UNTRUSTED_VALIDATED_FENCE();
7061
7062	/* All 3d commands start with a common header, which defines the identifier and the size
7063	* of the command. The identifier has been already read from FIFO. Fetch the size.
7064	*/
7065	uint32_t *pcbCmd;
7066	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
7067	uint32_t const cbCmd = *pcbCmd;
7068	AssertBreak(cbCmd < pThis->svga.cbFIFO);
7069	uint32_t *pu32Cmd;
7070	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
7071	pu32Cmd++; /* Skip the command size. */
7072
7073	if (RT_LIKELY(pThis->svga.f3DEnabled))
7074	{ /* likely */ }
7075	else
7076	{
7077	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
7078	break;
7079	}
7080
7081	vmsvgaR3Process3dCmd(pThis, pThisCC, enmCmdId, cbCmd, pu32Cmd);
7082	}
7083	else
7084	# endif // VBOX_WITH_VMSVGA3D
7085	{
7086	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
7087	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
7088	}
7089	}
7090
7091	/* Go to the next slot */
7092	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
7093	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
7094	if (offCurrentCmd >= offFifoMax)
7095	{
7096	offCurrentCmd -= offFifoMax - offFifoMin;
7097	Assert(offCurrentCmd >= offFifoMin);
7098	Assert(offCurrentCmd < offFifoMax);
7099	}
7100	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
7101	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
7102
7103	/*
7104	* Raise IRQ if required. Must enter the critical section here
7105	* before making final decisions here, otherwise cubebench and
7106	* others may end up waiting forever.
7107	*/
7108	if ( u32IrqStatus
7109	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
7110	{
7111	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
7112	AssertRC(rc2);
7113
7114	/* FIFO progress might trigger an interrupt. */
7115	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
7116	{
7117	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
7118	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
7119	}
7120
7121	/* Unmasked IRQ pending? */
7122	if (pThis->svga.u32IrqMask & u32IrqStatus)
7123	{
7124	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
7125	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
7126	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
7127	}
7128
7129	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
7130	}
7131	}
7132
7133	/* If really done, clear the busy flag. */
7134	if (fDone)
7135	{
7136	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
7137	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
7138	}
7139	}
7140
7141	/*
7142	* Free the bounce buffer. (There are no returns above!)
7143	*/
7144	RTMemFree(pbBounceBuf);
7145
7146	return VINF_SUCCESS;
7147	}
7148
7149	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
7150	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
7151
7152	#ifdef VBOX_WITH_VMSVGA3D
7153	/**
7154	* Free the specified GMR
7155	*
7156	* @param pThisCC The VGA/VMSVGA state for ring-3.
7157	* @param idGMR GMR id
7158	*/
7159	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7160	{
7161	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7162
7163	/* Free the old descriptor if present. */
7164	PGMR pGMR = &pSVGAState->paGMR[idGMR];
7165	if ( pGMR->numDescriptors
7166	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7167	{
7168	# ifdef DEBUG_GMR_ACCESS
7169	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7170	# endif
7171
7172	Assert(pGMR->paDesc);
7173	RTMemFree(pGMR->paDesc);
7174	pGMR->paDesc = NULL;
7175	pGMR->numDescriptors = 0;
7176	pGMR->cbTotal = 0;
7177	pGMR->cMaxPages = 0;
7178	}
7179	Assert(!pGMR->cMaxPages);
7180	Assert(!pGMR->cbTotal);
7181	}
7182	#endif /* VBOX_WITH_VMSVGA3D */
7183
7184	/**
7185	* Copy between a GMR and a host memory buffer.
7186	*
7187	* @returns VBox status code.
7188	* @param pThis The shared VGA/VMSVGA instance data.
7189	* @param pThisCC The VGA/VMSVGA state for ring-3.
7190	* @param enmTransferType Transfer type (read/write)
7191	* @param pbHstBuf Host buffer pointer (valid)
7192	* @param cbHstBuf Size of host buffer (valid)
7193	* @param offHst Host buffer offset of the first scanline
7194	* @param cbHstPitch Destination buffer pitch
7195	* @param gstPtr GMR description
7196	* @param offGst Guest buffer offset of the first scanline
7197	* @param cbGstPitch Guest buffer pitch
7198	* @param cbWidth Width in bytes to copy
7199	* @param cHeight Number of scanllines to copy
7200	*/
7201	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7202	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7203	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7204	uint32_t cbWidth, uint32_t cHeight)
7205	{
7206	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7207	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7208	int rc;
7209
7210	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7211	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7212	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7213	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7214	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7215
7216	PGMR pGMR;
7217	uint32_t cbGmr; /* The GMR size in bytes. */
7218	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7219	{
7220	pGMR = NULL;
7221	cbGmr = pThis->vram_size;
7222	}
7223	else
7224	{
7225	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7226	RT_UNTRUSTED_VALIDATED_FENCE();
7227	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7228	cbGmr = pGMR->cbTotal;
7229	}
7230
7231	/*
7232	* GMR
7233	*/
7234	/* Calculate GMR offset of the data to be copied. */
7235	AssertMsgReturn(gstPtr.offset < cbGmr,
7236	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7237	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7238	VERR_INVALID_PARAMETER);
7239	RT_UNTRUSTED_VALIDATED_FENCE();
7240	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7241	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7242	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7243	VERR_INVALID_PARAMETER);
7244	RT_UNTRUSTED_VALIDATED_FENCE();
7245	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7246
7247	/* Verify that cbWidth is less than scanline and fits into the GMR. */
7248	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7249	AssertMsgReturn(cbGmrScanline != 0,
7250	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7251	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7252	VERR_INVALID_PARAMETER);
7253	RT_UNTRUSTED_VALIDATED_FENCE();
7254	AssertMsgReturn(cbWidth <= cbGmrScanline,
7255	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7256	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7257	VERR_INVALID_PARAMETER);
7258	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7259	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7260	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7261	VERR_INVALID_PARAMETER);
7262	RT_UNTRUSTED_VALIDATED_FENCE();
7263
7264	/* How many bytes are available for the data in the GMR. */
7265	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7266
7267	/* How many scanlines would fit into the available data. */
7268	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7269	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7270	if (cbWidth <= cbGmrLastScanline)
7271	++cGmrScanlines;
7272
7273	if (cHeight > cGmrScanlines)
7274	cHeight = cGmrScanlines;
7275
7276	AssertMsgReturn(cHeight > 0,
7277	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7278	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7279	VERR_INVALID_PARAMETER);
7280	RT_UNTRUSTED_VALIDATED_FENCE();
7281
7282	/*
7283	* Host buffer.
7284	*/
7285	AssertMsgReturn(offHst < cbHstBuf,
7286	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7287	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7288	VERR_INVALID_PARAMETER);
7289
7290	/* Verify that cbWidth is less than scanline and fits into the buffer. */
7291	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7292	AssertMsgReturn(cbHstScanline != 0,
7293	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7294	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7295	VERR_INVALID_PARAMETER);
7296	AssertMsgReturn(cbWidth <= cbHstScanline,
7297	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7298	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7299	VERR_INVALID_PARAMETER);
7300	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7301	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7302	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7303	VERR_INVALID_PARAMETER);
7304
7305	/* How many bytes are available for the data in the buffer. */
7306	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7307
7308	/* How many scanlines would fit into the available data. */
7309	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7310	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7311	if (cbWidth <= cbHstLastScanline)
7312	++cHstScanlines;
7313
7314	if (cHeight > cHstScanlines)
7315	cHeight = cHstScanlines;
7316
7317	AssertMsgReturn(cHeight > 0,
7318	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7319	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7320	VERR_INVALID_PARAMETER);
7321
7322	uint8_t *pbHst = pbHstBuf + offHst;
7323
7324	/* Shortcut for the framebuffer. */
7325	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7326	{
7327	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7328
7329	uint8_t const *pbSrc;
7330	int32_t cbSrcPitch;
7331	uint8_t *pbDst;
7332	int32_t cbDstPitch;
7333
7334	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7335	{
7336	pbSrc = pbHst;
7337	cbSrcPitch = cbHstPitch;
7338	pbDst = pbGst;
7339	cbDstPitch = cbGstPitch;
7340	}
7341	else
7342	{
7343	pbSrc = pbGst;
7344	cbSrcPitch = cbGstPitch;
7345	pbDst = pbHst;
7346	cbDstPitch = cbHstPitch;
7347	}
7348
7349	if ( cbWidth == (uint32_t)cbGstPitch
7350	&& cbGstPitch == cbHstPitch)
7351	{
7352	/* Entire scanlines, positive pitch. */
7353	memcpy(pbDst, pbSrc, cbWidth * cHeight);
7354	}
7355	else
7356	{
7357	for (uint32_t i = 0; i < cHeight; ++i)
7358	{
7359	memcpy(pbDst, pbSrc, cbWidth);
7360
7361	pbDst += cbDstPitch;
7362	pbSrc += cbSrcPitch;
7363	}
7364	}
7365	return VINF_SUCCESS;
7366	}
7367
7368	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7369	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7370
7371	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7372	uint32_t iDesc = 0; /* Index in the descriptor array. */
7373	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7374	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7375	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
7376	for (uint32_t i = 0; i < cHeight; ++i)
7377	{
7378	uint32_t cbCurrentWidth = cbWidth;
7379	uint32_t offGmrCurrent = offGmrScanline;
7380	uint8_t *pbCurrentHost = pbHstScanline;
7381
7382	/* Find the right descriptor */
7383	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
7384	{
7385	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
7386	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7387	++iDesc;
7388	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7389	}
7390
7391	while (cbCurrentWidth)
7392	{
7393	uint32_t cbToCopy;
7394
7395	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
7396	{
7397	cbToCopy = cbCurrentWidth;
7398	}
7399	else
7400	{
7401	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
7402	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7403	}
7404
7405	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7406
7407	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7408
7409	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7410	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7411	else
7412	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7413	AssertRCBreak(rc);
7414
7415	cbCurrentWidth -= cbToCopy;
7416	offGmrCurrent += cbToCopy;
7417	pbCurrentHost += cbToCopy;
7418
7419	/* Go to the next descriptor if there's anything left. */
7420	if (cbCurrentWidth)
7421	{
7422	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
7423	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7424	++iDesc;
7425	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7426	}
7427	}
7428
7429	offGmrScanline += cbGstPitch;
7430	pbHstScanline += cbHstPitch;
7431	}
7432
7433	return VINF_SUCCESS;
7434	}
7435
7436
7437	/**
7438	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7439	*
7440	* @param pSizeSrc Source surface dimensions.
7441	* @param pSizeDest Destination surface dimensions.
7442	* @param pBox Coordinates to be clipped.
7443	*/
7444	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
7445	{
7446	/* Src x, w */
7447	if (pBox->srcx > pSizeSrc->width)
7448	pBox->srcx = pSizeSrc->width;
7449	if (pBox->w > pSizeSrc->width - pBox->srcx)
7450	pBox->w = pSizeSrc->width - pBox->srcx;
7451
7452	/* Src y, h */
7453	if (pBox->srcy > pSizeSrc->height)
7454	pBox->srcy = pSizeSrc->height;
7455	if (pBox->h > pSizeSrc->height - pBox->srcy)
7456	pBox->h = pSizeSrc->height - pBox->srcy;
7457
7458	/* Src z, d */
7459	if (pBox->srcz > pSizeSrc->depth)
7460	pBox->srcz = pSizeSrc->depth;
7461	if (pBox->d > pSizeSrc->depth - pBox->srcz)
7462	pBox->d = pSizeSrc->depth - pBox->srcz;
7463
7464	/* Dest x, w */
7465	if (pBox->x > pSizeDest->width)
7466	pBox->x = pSizeDest->width;
7467	if (pBox->w > pSizeDest->width - pBox->x)
7468	pBox->w = pSizeDest->width - pBox->x;
7469
7470	/* Dest y, h */
7471	if (pBox->y > pSizeDest->height)
7472	pBox->y = pSizeDest->height;
7473	if (pBox->h > pSizeDest->height - pBox->y)
7474	pBox->h = pSizeDest->height - pBox->y;
7475
7476	/* Dest z, d */
7477	if (pBox->z > pSizeDest->depth)
7478	pBox->z = pSizeDest->depth;
7479	if (pBox->d > pSizeDest->depth - pBox->z)
7480	pBox->d = pSizeDest->depth - pBox->z;
7481	}
7482
7483	/**
7484	* Unsigned coordinates in pBox. Clip to [0; pSize).
7485	*
7486	* @param pSize Source surface dimensions.
7487	* @param pBox Coordinates to be clipped.
7488	*/
7489	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
7490	{
7491	/* x, w */
7492	if (pBox->x > pSize->width)
7493	pBox->x = pSize->width;
7494	if (pBox->w > pSize->width - pBox->x)
7495	pBox->w = pSize->width - pBox->x;
7496
7497	/* y, h */
7498	if (pBox->y > pSize->height)
7499	pBox->y = pSize->height;
7500	if (pBox->h > pSize->height - pBox->y)
7501	pBox->h = pSize->height - pBox->y;
7502
7503	/* z, d */
7504	if (pBox->z > pSize->depth)
7505	pBox->z = pSize->depth;
7506	if (pBox->d > pSize->depth - pBox->z)
7507	pBox->d = pSize->depth - pBox->z;
7508	}
7509
7510	/**
7511	* Clip.
7512	*
7513	* @param pBound Bounding rectangle.
7514	* @param pRect Rectangle to be clipped.
7515	*/
7516	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
7517	{
7518	int32_t left;
7519	int32_t top;
7520	int32_t right;
7521	int32_t bottom;
7522
7523	/* Right order. */
7524	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7525	if (pRect->left < pRect->right)
7526	{
7527	left = pRect->left;
7528	right = pRect->right;
7529	}
7530	else
7531	{
7532	left = pRect->right;
7533	right = pRect->left;
7534	}
7535	if (pRect->top < pRect->bottom)
7536	{
7537	top = pRect->top;
7538	bottom = pRect->bottom;
7539	}
7540	else
7541	{
7542	top = pRect->bottom;
7543	bottom = pRect->top;
7544	}
7545
7546	if (left < pBound->left)
7547	left = pBound->left;
7548	if (right < pBound->left)
7549	right = pBound->left;
7550
7551	if (left > pBound->right)
7552	left = pBound->right;
7553	if (right > pBound->right)
7554	right = pBound->right;
7555
7556	if (top < pBound->top)
7557	top = pBound->top;
7558	if (bottom < pBound->top)
7559	bottom = pBound->top;
7560
7561	if (top > pBound->bottom)
7562	top = pBound->bottom;
7563	if (bottom > pBound->bottom)
7564	bottom = pBound->bottom;
7565
7566	pRect->left = left;
7567	pRect->right = right;
7568	pRect->top = top;
7569	pRect->bottom = bottom;
7570	}
7571
7572	/**
7573	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
7574	* Unblock the FIFO I/O thread so it can respond to a state change.}
7575	*/
7576	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7577	{
7578	RT_NOREF(pDevIns);
7579	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
7580	Log(("vmsvgaR3FifoLoopWakeUp\n"));
7581	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
7582	}
7583
7584	/**
7585	* Enables or disables dirty page tracking for the framebuffer
7586	*
7587	* @param pDevIns The device instance.
7588	* @param pThis The shared VGA/VMSVGA instance data.
7589	* @param fTraces Enable/disable traces
7590	*/
7591	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
7592	{
7593	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
7594	&& !fTraces)
7595	{
7596	//Assert(pThis->svga.fTraces);
7597	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
7598	return;
7599	}
7600
7601	pThis->svga.fTraces = fTraces;
7602	if (pThis->svga.fTraces)
7603	{
7604	unsigned cbFrameBuffer = pThis->vram_size;
7605
7606	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
7607	/** @todo How does this work with screens? */
7608	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
7609	{
7610	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
7611	Assert(pThis->svga.cbScanline);
7612	# endif
7613	/* Hardware enabled; return real framebuffer size .*/
7614	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
7615	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
7616	}
7617
7618	if (!pThis->svga.fVRAMTracking)
7619	{
7620	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
7621	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
7622	pThis->svga.fVRAMTracking = true;
7623	}
7624	}
7625	else
7626	{
7627	if (pThis->svga.fVRAMTracking)
7628	{
7629	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
7630	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
7631	pThis->svga.fVRAMTracking = false;
7632	}
7633	}
7634	}
7635
7636	/**
7637	* @callback_method_impl{FNPCIIOREGIONMAP}
7638	*/
7639	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7640	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
7641	{
7642	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7643	int rc;
7644	RT_NOREF(pPciDev);
7645	Assert(pPciDev == pDevIns->apPciDevs[0]);
7646
7647	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
7648	AssertReturn( iRegion == pThis->pciRegions.iFIFO
7649	&& ( enmType == PCI_ADDRESS_SPACE_MEM
7650	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
7651	, VERR_INTERNAL_ERROR);
7652	if (GCPhysAddress != NIL_RTGCPHYS)
7653	{
7654	/*
7655	* Mapping the FIFO RAM.
7656	*/
7657	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
7658	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
7659	AssertRC(rc);
7660
7661	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
7662	if (RT_SUCCESS(rc))
7663	{
7664	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
7665	# ifdef DEBUG_FIFO_ACCESS
7666	GCPhysAddress + (pThis->svga.cbFIFO - 1),
7667	# else
7668	GCPhysAddress + PAGE_SIZE - 1,
7669	# endif
7670	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
7671	"VMSVGA FIFO");
7672	AssertRC(rc);
7673	}
7674	# endif
7675	if (RT_SUCCESS(rc))
7676	{
7677	pThis->svga.GCPhysFIFO = GCPhysAddress;
7678	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
7679	}
7680	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
7681	}
7682	else
7683	{
7684	Assert(pThis->svga.GCPhysFIFO);
7685	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
7686	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
7687	AssertRC(rc);
7688	# else
7689	rc = VINF_SUCCESS;
7690	# endif
7691	pThis->svga.GCPhysFIFO = 0;
7692	}
7693	return rc;
7694	}
7695
7696	# ifdef VBOX_WITH_VMSVGA3D
7697
7698	/**
7699	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
7700	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
7701	*
7702	* @param pDevIns The device instance.
7703	* @param pThis The The shared VGA/VMSVGA instance data.
7704	* @param pThisCC The VGA/VMSVGA state for ring-3.
7705	* @param sid Either UINT32_MAX or the ID of a specific surface. If
7706	* UINT32_MAX is used, all surfaces are processed.
7707	*/
7708	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
7709	{
7710	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
7711	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
7712	}
7713
7714
7715	/**
7716	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
7717	*/
7718	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7719	{
7720	/* There might be a specific surface ID at the start of the
7721	arguments, if not show all surfaces. */
7722	uint32_t sid = UINT32_MAX;
7723	if (pszArgs)
7724	pszArgs = RTStrStripL(pszArgs);
7725	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
7726	sid = RTStrToUInt32(pszArgs);
7727
7728	/* Verbose or terse display, we default to verbose. */
7729	bool fVerbose = true;
7730	if (RTStrIStr(pszArgs, "terse"))
7731	fVerbose = false;
7732
7733	/* The size of the ascii art (x direction, y is 3/4 of x). */
7734	uint32_t cxAscii = 80;
7735	if (RTStrIStr(pszArgs, "gigantic"))
7736	cxAscii = 300;
7737	else if (RTStrIStr(pszArgs, "huge"))
7738	cxAscii = 180;
7739	else if (RTStrIStr(pszArgs, "big"))
7740	cxAscii = 132;
7741	else if (RTStrIStr(pszArgs, "normal"))
7742	cxAscii = 80;
7743	else if (RTStrIStr(pszArgs, "medium"))
7744	cxAscii = 64;
7745	else if (RTStrIStr(pszArgs, "small"))
7746	cxAscii = 48;
7747	else if (RTStrIStr(pszArgs, "tiny"))
7748	cxAscii = 24;
7749
7750	/* Y invert the image when producing the ASCII art. */
7751	bool fInvY = false;
7752	if (RTStrIStr(pszArgs, "invy"))
7753	fInvY = true;
7754
7755	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
7756	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
7757	}
7758
7759
7760	/**
7761	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
7762	*/
7763	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7764	{
7765	/* pszArg = "sid[>dir]"
7766	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
7767	*/
7768	char *pszBitmapPath = NULL;
7769	uint32_t sid = UINT32_MAX;
7770	if (pszArgs)
7771	pszArgs = RTStrStripL(pszArgs);
7772	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
7773	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
7774	if ( pszBitmapPath
7775	&& *pszBitmapPath == '>')
7776	++pszBitmapPath;
7777
7778	const bool fVerbose = true;
7779	const uint32_t cxAscii = 0; /* No ASCII */
7780	const bool fInvY = false; /* Do not invert. */
7781	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
7782	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
7783	}
7784
7785	/**
7786	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
7787	*/
7788	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7789	{
7790	/* There might be a specific surface ID at the start of the
7791	arguments, if not show all contexts. */
7792	uint32_t sid = UINT32_MAX;
7793	if (pszArgs)
7794	pszArgs = RTStrStripL(pszArgs);
7795	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
7796	sid = RTStrToUInt32(pszArgs);
7797
7798	/* Verbose or terse display, we default to verbose. */
7799	bool fVerbose = true;
7800	if (RTStrIStr(pszArgs, "terse"))
7801	fVerbose = false;
7802
7803	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
7804	}
7805	# endif /* VBOX_WITH_VMSVGA3D */
7806
7807	/**
7808	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
7809	*/
7810	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7811	{
7812	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7813	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7814	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7815	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
7816	RT_NOREF(pszArgs);
7817
7818	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
7819	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
7820	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
7821	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
7822	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
7823	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
7824	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
7825	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
7826	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
7827	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
7828	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
7829	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
7830	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
7831	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
7832	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
7833	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
7834	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
7835	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
7836	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
7837	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
7838	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
7839	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
7840	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
7841	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
7842	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
7843
7844	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
7845	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
7846	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
7847	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
7848
7849	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
7850	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
7851
7852	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
7853	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
7854
7855	# ifdef VBOX_WITH_VMSVGA3D
7856	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
7857	# endif
7858	if (pThisCC->pDrv)
7859	{
7860	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
7861	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
7862	}
7863
7864	/* Dump screen information. */
7865	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
7866	{
7867	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
7868	if (pScreen)
7869	{
7870	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
7871	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
7872	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
7873	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
7874	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
7875	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
7876	{
7877	pHlp->pfnPrintf(pHlp, " (");
7878	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
7879	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
7880	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
7881	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
7882	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
7883	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
7884	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
7885	pHlp->pfnPrintf(pHlp, " BLANKING");
7886	pHlp->pfnPrintf(pHlp, " )");
7887	}
7888	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
7889	}
7890	}
7891
7892	}
7893
7894	/**
7895	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
7896	*/
7897	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
7898	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7899	{
7900	RT_NOREF(uPass);
7901
7902	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7903	int rc;
7904
7905	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
7906	{
7907	uint32_t cScreens = 0;
7908	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
7909	AssertRCReturn(rc, rc);
7910	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
7911	("cScreens=%#x\n", cScreens),
7912	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
7913
7914	for (uint32_t i = 0; i < cScreens; ++i)
7915	{
7916	VMSVGASCREENOBJECT screen;
7917	RT_ZERO(screen);
7918
7919	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
7920	AssertLogRelRCReturn(rc, rc);
7921
7922	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
7923	{
7924	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
7925	*pScreen = screen;
7926	pScreen->fModified = true;
7927	}
7928	else
7929	{
7930	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
7931	}
7932	}
7933	}
7934	else
7935	{
7936	/* Try to setup at least the first screen. */
7937	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
7938	pScreen->fDefined = true;
7939	pScreen->fModified = true;
7940	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
7941	pScreen->idScreen = 0;
7942	pScreen->xOrigin = 0;
7943	pScreen->yOrigin = 0;
7944	pScreen->offVRAM = pThis->svga.uScreenOffset;
7945	pScreen->cbPitch = pThis->svga.cbScanline;
7946	pScreen->cWidth = pThis->svga.uWidth;
7947	pScreen->cHeight = pThis->svga.uHeight;
7948	pScreen->cBpp = pThis->svga.uBpp;
7949	}
7950
7951	return VINF_SUCCESS;
7952	}
7953
7954	/**
7955	* @copydoc FNSSMDEVLOADEXEC
7956	*/
7957	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7958	{
7959	RT_NOREF(uPass);
7960	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7961	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7962	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7963	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7964	int rc;
7965
7966	/* Load our part of the VGAState */
7967	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
7968	AssertRCReturn(rc, rc);
7969
7970	/* Load the VGA framebuffer. */
7971	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
7972	uint32_t cbVgaFramebuffer = _32K;
7973	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
7974	{
7975	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
7976	AssertRCReturn(rc, rc);
7977	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
7978	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
7979	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
7980	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
7981	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
7982	}
7983	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
7984	AssertRCReturn(rc, rc);
7985	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
7986	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
7987	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
7988	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
7989
7990	/* Load the VMSVGA state. */
7991	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
7992	AssertRCReturn(rc, rc);
7993
7994	/* Load the active cursor bitmaps. */
7995	if (pSVGAState->Cursor.fActive)
7996	{
7997	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
7998	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
7999
8000	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
8001	AssertRCReturn(rc, rc);
8002	}
8003
8004	/* Load the GMR state. */
8005	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
8006	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
8007	{
8008	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
8009	AssertRCReturn(rc, rc);
8010	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
8011	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
8012	("cGMR=%#x - expected 256B..1MB\n", cGMR),
8013	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
8014	}
8015
8016	if (pThis->svga.cGMR != cGMR)
8017	{
8018	/* Reallocate GMR array. */
8019	Assert(pSVGAState->paGMR != NULL);
8020	RTMemFree(pSVGAState->paGMR);
8021	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
8022	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
8023	pThis->svga.cGMR = cGMR;
8024	}
8025
8026	for (uint32_t i = 0; i < cGMR; ++i)
8027	{
8028	PGMR pGMR = &pSVGAState->paGMR[i];
8029
8030	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
8031	AssertRCReturn(rc, rc);
8032
8033	if (pGMR->numDescriptors)
8034	{
8035	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
8036	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
8037	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
8038
8039	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
8040	{
8041	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
8042	AssertRCReturn(rc, rc);
8043	}
8044	}
8045	}
8046
8047	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
8048	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
8049	# endif
8050
8051	VMSVGA_STATE_LOAD LoadState;
8052	LoadState.pSSM = pSSM;
8053	LoadState.uVersion = uVersion;
8054	LoadState.uPass = uPass;
8055	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
8056	AssertLogRelRCReturn(rc, rc);
8057
8058	return VINF_SUCCESS;
8059	}
8060
8061	/**
8062	* Reinit the video mode after the state has been loaded.
8063	*/
8064	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
8065	{
8066	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8067	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8068	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
8069
8070	/* Set the active cursor. */
8071	if (pSVGAState->Cursor.fActive)
8072	{
8073	/* We don't store the alpha flag, but we can take a guess that if
8074	* the old register interface was used, the cursor was B&W.
8075	*/
8076	bool fAlpha = pThis->svga.uCursorOn ? false : true;
8077
8078	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
8079	true /fVisible/,
8080	fAlpha,
8081	pSVGAState->Cursor.xHotspot,
8082	pSVGAState->Cursor.yHotspot,
8083	pSVGAState->Cursor.width,
8084	pSVGAState->Cursor.height,
8085	pSVGAState->Cursor.pData);
8086	AssertRC(rc);
8087
8088	if (pThis->svga.uCursorOn)
8089	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
8090	}
8091
8092	/* If the VRAM handler should not be registered, we have to explicitly
8093	* unregister it here!
8094	*/
8095	if (!pThis->svga.fVRAMTracking)
8096	{
8097	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
8098	}
8099
8100	/* Let the FIFO thread deal with changing the mode. */
8101	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
8102
8103	return VINF_SUCCESS;
8104	}
8105
8106	/**
8107	* Portion of SVGA state which must be saved in the FIFO thread.
8108	*/
8109	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
8110	{
8111	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
8112	int rc;
8113
8114	/* Save the screen objects. */
8115	/* Count defined screen object. */
8116	uint32_t cScreens = 0;
8117	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
8118	{
8119	if (pSVGAState->aScreens[i].fDefined)
8120	++cScreens;
8121	}
8122
8123	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
8124	AssertLogRelRCReturn(rc, rc);
8125
8126	for (uint32_t i = 0; i < cScreens; ++i)
8127	{
8128	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
8129
8130	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
8131	AssertLogRelRCReturn(rc, rc);
8132	}
8133	return VINF_SUCCESS;
8134	}
8135
8136	/**
8137	* @copydoc FNSSMDEVSAVEEXEC
8138	*/
8139	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
8140	{
8141	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8142	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8143	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
8144	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
8145	int rc;
8146
8147	/* Save our part of the VGAState */
8148	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
8149	AssertLogRelRCReturn(rc, rc);
8150
8151	/* Save the framebuffer backup. */
8152	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
8153	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
8154	AssertLogRelRCReturn(rc, rc);
8155
8156	/* Save the VMSVGA state. */
8157	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
8158	AssertLogRelRCReturn(rc, rc);
8159
8160	/* Save the active cursor bitmaps. */
8161	if (pSVGAState->Cursor.fActive)
8162	{
8163	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
8164	AssertLogRelRCReturn(rc, rc);
8165	}
8166
8167	/* Save the GMR state */
8168	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
8169	AssertLogRelRCReturn(rc, rc);
8170	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
8171	{
8172	PGMR pGMR = &pSVGAState->paGMR[i];
8173
8174	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
8175	AssertLogRelRCReturn(rc, rc);
8176
8177	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
8178	{
8179	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
8180	AssertLogRelRCReturn(rc, rc);
8181	}
8182	}
8183
8184	/*
8185	* Must save some state (3D in particular) in the FIFO thread.
8186	*/
8187	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
8188	AssertLogRelRCReturn(rc, rc);
8189
8190	return VINF_SUCCESS;
8191	}
8192
8193	/**
8194	* Destructor for PVMSVGAR3STATE structure.
8195	*
8196	* @param pThis The shared VGA/VMSVGA instance data.
8197	* @param pSVGAState Pointer to the structure. It is not deallocated.
8198	*/
8199	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
8200	{
8201	# ifndef VMSVGA_USE_EMT_HALT_CODE
8202	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
8203	{
8204	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
8205	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
8206	}
8207	# endif
8208
8209	if (pSVGAState->Cursor.fActive)
8210	{
8211	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
8212	pSVGAState->Cursor.pData = NULL;
8213	pSVGAState->Cursor.fActive = false;
8214	}
8215
8216	if (pSVGAState->paGMR)
8217	{
8218	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
8219	if (pSVGAState->paGMR[i].paDesc)
8220	RTMemFree(pSVGAState->paGMR[i].paDesc);
8221
8222	RTMemFree(pSVGAState->paGMR);
8223	pSVGAState->paGMR = NULL;
8224	}
8225
8226	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
8227	{
8228	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
8229	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
8230	{
8231	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
8232	pSVGAState->apCmdBufCtxs[i] = NULL;
8233	}
8234	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
8235	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
8236	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
8237	}
8238	}
8239
8240	/**
8241	* Constructor for PVMSVGAR3STATE structure.
8242	*
8243	* @returns VBox status code.
8244	* @param pThis The shared VGA/VMSVGA instance data.
8245	* @param pSVGAState Pointer to the structure. It is already allocated.
8246	*/
8247	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
8248	{
8249	int rc = VINF_SUCCESS;
8250	RT_ZERO(*pSVGAState);
8251
8252	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
8253	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
8254
8255	# ifndef VMSVGA_USE_EMT_HALT_CODE
8256	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
8257	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
8258	AssertRCReturn(rc, rc);
8259	# endif
8260
8261	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
8262	AssertRCReturn(rc, rc);
8263
8264	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
8265	return rc;
8266	}
8267
8268	/**
8269	* Initializes the host capabilities: device and FIFO.
8270	*
8271	* @returns VBox status code.
8272	* @param pThis The shared VGA/VMSVGA instance data.
8273	* @param pThisCC The VGA/VMSVGA state for ring-3.
8274	*/
8275	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
8276	{
8277	/* Device caps. */
8278	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
8279	\| SVGA_CAP_GMR2
8280	\| SVGA_CAP_CURSOR
8281	\| SVGA_CAP_CURSOR_BYPASS
8282	\| SVGA_CAP_CURSOR_BYPASS_2
8283	\| SVGA_CAP_EXTENDED_FIFO
8284	\| SVGA_CAP_IRQMASK
8285	\| SVGA_CAP_PITCHLOCK
8286	\| SVGA_CAP_RECT_COPY
8287	\| SVGA_CAP_TRACES
8288	\| SVGA_CAP_SCREEN_OBJECT_2
8289	\| SVGA_CAP_ALPHA_CURSOR;
8290
8291	/* VGPU10 capabilities. */
8292	if (pThis->fVMSVGA10)
8293	{
8294	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
8295	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
8296	// \| SVGA_CAP_GBOBJECTS /* Enable guest-backed objects and surfaces. */
8297	// \| SVGA_CAP_CMD_BUFFERS_3 /* AKA SVGA_CAP_DX. Enable support for DX commands, and command buffers in a mob. */
8298	;
8299	}
8300
8301	# ifdef VBOX_WITH_VMSVGA3D
8302	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
8303	# endif
8304
8305	/* Clear the FIFO. */
8306	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
8307
8308	/* Setup FIFO capabilities. */
8309	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
8310	\| SVGA_FIFO_CAP_PITCHLOCK
8311	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
8312	\| SVGA_FIFO_CAP_RESERVE
8313	\| SVGA_FIFO_CAP_GMR2
8314	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
8315	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
8316
8317	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
8318	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
8319	}
8320
8321	# ifdef VBOX_WITH_VMSVGA3D
8322	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
8323	static const char * const g_apszVmSvgaDevCapNames[] =
8324	{
8325	"x3D", /* = 0 */
8326	"xMAX_LIGHTS",
8327	"xMAX_TEXTURES",
8328	"xMAX_CLIP_PLANES",
8329	"xVERTEX_SHADER_VERSION",
8330	"xVERTEX_SHADER",
8331	"xFRAGMENT_SHADER_VERSION",
8332	"xFRAGMENT_SHADER",
8333	"xMAX_RENDER_TARGETS",
8334	"xS23E8_TEXTURES",
8335	"xS10E5_TEXTURES",
8336	"xMAX_FIXED_VERTEXBLEND",
8337	"xD16_BUFFER_FORMAT",
8338	"xD24S8_BUFFER_FORMAT",
8339	"xD24X8_BUFFER_FORMAT",
8340	"xQUERY_TYPES",
8341	"xTEXTURE_GRADIENT_SAMPLING",
8342	"rMAX_POINT_SIZE",
8343	"xMAX_SHADER_TEXTURES",
8344	"xMAX_TEXTURE_WIDTH",
8345	"xMAX_TEXTURE_HEIGHT",
8346	"xMAX_VOLUME_EXTENT",
8347	"xMAX_TEXTURE_REPEAT",
8348	"xMAX_TEXTURE_ASPECT_RATIO",
8349	"xMAX_TEXTURE_ANISOTROPY",
8350	"xMAX_PRIMITIVE_COUNT",
8351	"xMAX_VERTEX_INDEX",
8352	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
8353	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
8354	"xMAX_VERTEX_SHADER_TEMPS",
8355	"xMAX_FRAGMENT_SHADER_TEMPS",
8356	"xTEXTURE_OPS",
8357	"xSURFACEFMT_X8R8G8B8",
8358	"xSURFACEFMT_A8R8G8B8",
8359	"xSURFACEFMT_A2R10G10B10",
8360	"xSURFACEFMT_X1R5G5B5",
8361	"xSURFACEFMT_A1R5G5B5",
8362	"xSURFACEFMT_A4R4G4B4",
8363	"xSURFACEFMT_R5G6B5",
8364	"xSURFACEFMT_LUMINANCE16",
8365	"xSURFACEFMT_LUMINANCE8_ALPHA8",
8366	"xSURFACEFMT_ALPHA8",
8367	"xSURFACEFMT_LUMINANCE8",
8368	"xSURFACEFMT_Z_D16",
8369	"xSURFACEFMT_Z_D24S8",
8370	"xSURFACEFMT_Z_D24X8",
8371	"xSURFACEFMT_DXT1",
8372	"xSURFACEFMT_DXT2",
8373	"xSURFACEFMT_DXT3",
8374	"xSURFACEFMT_DXT4",
8375	"xSURFACEFMT_DXT5",
8376	"xSURFACEFMT_BUMPX8L8V8U8",
8377	"xSURFACEFMT_A2W10V10U10",
8378	"xSURFACEFMT_BUMPU8V8",
8379	"xSURFACEFMT_Q8W8V8U8",
8380	"xSURFACEFMT_CxV8U8",
8381	"xSURFACEFMT_R_S10E5",
8382	"xSURFACEFMT_R_S23E8",
8383	"xSURFACEFMT_RG_S10E5",
8384	"xSURFACEFMT_RG_S23E8",
8385	"xSURFACEFMT_ARGB_S10E5",
8386	"xSURFACEFMT_ARGB_S23E8",
8387	"xMISSING62",
8388	"xMAX_VERTEX_SHADER_TEXTURES",
8389	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
8390	"xSURFACEFMT_V16U16",
8391	"xSURFACEFMT_G16R16",
8392	"xSURFACEFMT_A16B16G16R16",
8393	"xSURFACEFMT_UYVY",
8394	"xSURFACEFMT_YUY2",
8395	"xMULTISAMPLE_NONMASKABLESAMPLES",
8396	"xMULTISAMPLE_MASKABLESAMPLES",
8397	"xALPHATOCOVERAGE",
8398	"xSUPERSAMPLE",
8399	"xAUTOGENMIPMAPS",
8400	"xSURFACEFMT_NV12",
8401	"xSURFACEFMT_AYUV",
8402	"xMAX_CONTEXT_IDS",
8403	"xMAX_SURFACE_IDS",
8404	"xSURFACEFMT_Z_DF16",
8405	"xSURFACEFMT_Z_DF24",
8406	"xSURFACEFMT_Z_D24S8_INT",
8407	"xSURFACEFMT_ATI1",
8408	"xSURFACEFMT_ATI2", /* 83 */
8409	"xDEAD1",
8410	"xVIDEO_DECODE",
8411	"xVIDEO_PROCESS",
8412	"xLINE_AA",
8413	"xLINE_STIPPLE",
8414	"rMAX_LINE_WIDTH",
8415	"rMAX_AA_LINE_WIDTH",
8416	"xSURFACEFMT_YV12",
8417	"xLOGICOPS",
8418	"xTS_COLOR_KEY",
8419	"xDEAD2",
8420	"xDX",
8421	"xMAX_TEXTURE_ARRAY_SIZE",
8422	"xDX_MAX_VERTEXBUFFERS",
8423	"xDX_MAX_CONSTANT_BUFFERS",
8424	"xDX_PROVOKING_VERTEX",
8425	"xDXFMT_X8R8G8B8",
8426	"xDXFMT_A8R8G8B8",
8427	"xDXFMT_R5G6B5",
8428	"xDXFMT_X1R5G5B5",
8429	"xDXFMT_A1R5G5B5",
8430	"xDXFMT_A4R4G4B4",
8431	"xDXFMT_Z_D32",
8432	"xDXFMT_Z_D16",
8433	"xDXFMT_Z_D24S8",
8434	"xDXFMT_Z_D15S1",
8435	"xDXFMT_LUMINANCE8",
8436	"xDXFMT_LUMINANCE4_ALPHA4",
8437	"xDXFMT_LUMINANCE16",
8438	"xDXFMT_LUMINANCE8_ALPHA8",
8439	"xDXFMT_DXT1",
8440	"xDXFMT_DXT2",
8441	"xDXFMT_DXT3",
8442	"xDXFMT_DXT4",
8443	"xDXFMT_DXT5",
8444	"xDXFMT_BUMPU8V8",
8445	"xDXFMT_BUMPL6V5U5",
8446	"xDXFMT_BUMPX8L8V8U8",
8447	"xDXFMT_FORMAT_DEAD1",
8448	"xDXFMT_ARGB_S10E5",
8449	"xDXFMT_ARGB_S23E8",
8450	"xDXFMT_A2R10G10B10",
8451	"xDXFMT_V8U8",
8452	"xDXFMT_Q8W8V8U8",
8453	"xDXFMT_CxV8U8",
8454	"xDXFMT_X8L8V8U8",
8455	"xDXFMT_A2W10V10U10",
8456	"xDXFMT_ALPHA8",
8457	"xDXFMT_R_S10E5",
8458	"xDXFMT_R_S23E8",
8459	"xDXFMT_RG_S10E5",
8460	"xDXFMT_RG_S23E8",
8461	"xDXFMT_BUFFER",
8462	"xDXFMT_Z_D24X8",
8463	"xDXFMT_V16U16",
8464	"xDXFMT_G16R16",
8465	"xDXFMT_A16B16G16R16",
8466	"xDXFMT_UYVY",
8467	"xDXFMT_YUY2",
8468	"xDXFMT_NV12",
8469	"xDXFMT_AYUV",
8470	"xDXFMT_R32G32B32A32_TYPELESS",
8471	"xDXFMT_R32G32B32A32_UINT",
8472	"xDXFMT_R32G32B32A32_SINT",
8473	"xDXFMT_R32G32B32_TYPELESS",
8474	"xDXFMT_R32G32B32_FLOAT",
8475	"xDXFMT_R32G32B32_UINT",
8476	"xDXFMT_R32G32B32_SINT",
8477	"xDXFMT_R16G16B16A16_TYPELESS",
8478	"xDXFMT_R16G16B16A16_UINT",
8479	"xDXFMT_R16G16B16A16_SNORM",
8480	"xDXFMT_R16G16B16A16_SINT",
8481	"xDXFMT_R32G32_TYPELESS",
8482	"xDXFMT_R32G32_UINT",
8483	"xDXFMT_R32G32_SINT",
8484	"xDXFMT_R32G8X24_TYPELESS",
8485	"xDXFMT_D32_FLOAT_S8X24_UINT",
8486	"xDXFMT_R32_FLOAT_X8X24_TYPELESS",
8487	"xDXFMT_X32_TYPELESS_G8X24_UINT",
8488	"xDXFMT_R10G10B10A2_TYPELESS",
8489	"xDXFMT_R10G10B10A2_UINT",
8490	"xDXFMT_R11G11B10_FLOAT",
8491	"xDXFMT_R8G8B8A8_TYPELESS",
8492	"xDXFMT_R8G8B8A8_UNORM",
8493	"xDXFMT_R8G8B8A8_UNORM_SRGB",
8494	"xDXFMT_R8G8B8A8_UINT",
8495	"xDXFMT_R8G8B8A8_SINT",
8496	"xDXFMT_R16G16_TYPELESS",
8497	"xDXFMT_R16G16_UINT",
8498	"xDXFMT_R16G16_SINT",
8499	"xDXFMT_R32_TYPELESS",
8500	"xDXFMT_D32_FLOAT",
8501	"xDXFMT_R32_UINT",
8502	"xDXFMT_R32_SINT",
8503	"xDXFMT_R24G8_TYPELESS",
8504	"xDXFMT_D24_UNORM_S8_UINT",
8505	"xDXFMT_R24_UNORM_X8_TYPELESS",
8506	"xDXFMT_X24_TYPELESS_G8_UINT",
8507	"xDXFMT_R8G8_TYPELESS",
8508	"xDXFMT_R8G8_UNORM",
8509	"xDXFMT_R8G8_UINT",
8510	"xDXFMT_R8G8_SINT",
8511	"xDXFMT_R16_TYPELESS",
8512	"xDXFMT_R16_UNORM",
8513	"xDXFMT_R16_UINT",
8514	"xDXFMT_R16_SNORM",
8515	"xDXFMT_R16_SINT",
8516	"xDXFMT_R8_TYPELESS",
8517	"xDXFMT_R8_UNORM",
8518	"xDXFMT_R8_UINT",
8519	"xDXFMT_R8_SNORM",
8520	"xDXFMT_R8_SINT",
8521	"xDXFMT_P8",
8522	"xDXFMT_R9G9B9E5_SHAREDEXP",
8523	"xDXFMT_R8G8_B8G8_UNORM",
8524	"xDXFMT_G8R8_G8B8_UNORM",
8525	"xDXFMT_BC1_TYPELESS",
8526	"xDXFMT_BC1_UNORM_SRGB",
8527	"xDXFMT_BC2_TYPELESS",
8528	"xDXFMT_BC2_UNORM_SRGB",
8529	"xDXFMT_BC3_TYPELESS",
8530	"xDXFMT_BC3_UNORM_SRGB",
8531	"xDXFMT_BC4_TYPELESS",
8532	"xDXFMT_ATI1",
8533	"xDXFMT_BC4_SNORM",
8534	"xDXFMT_BC5_TYPELESS",
8535	"xDXFMT_ATI2",
8536	"xDXFMT_BC5_SNORM",
8537	"xDXFMT_R10G10B10_XR_BIAS_A2_UNORM",
8538	"xDXFMT_B8G8R8A8_TYPELESS",
8539	"xDXFMT_B8G8R8A8_UNORM_SRGB",
8540	"xDXFMT_B8G8R8X8_TYPELESS",
8541	"xDXFMT_B8G8R8X8_UNORM_SRGB",
8542	"xDXFMT_Z_DF16",
8543	"xDXFMT_Z_DF24",
8544	"xDXFMT_Z_D24S8_INT",
8545	"xDXFMT_YV12",
8546	"xDXFMT_R32G32B32A32_FLOAT",
8547	"xDXFMT_R16G16B16A16_FLOAT",
8548	"xDXFMT_R16G16B16A16_UNORM",
8549	"xDXFMT_R32G32_FLOAT",
8550	"xDXFMT_R10G10B10A2_UNORM",
8551	"xDXFMT_R8G8B8A8_SNORM",
8552	"xDXFMT_R16G16_FLOAT",
8553	"xDXFMT_R16G16_UNORM",
8554	"xDXFMT_R16G16_SNORM",
8555	"xDXFMT_R32_FLOAT",
8556	"xDXFMT_R8G8_SNORM",
8557	"xDXFMT_R16_FLOAT",
8558	"xDXFMT_D16_UNORM",
8559	"xDXFMT_A8_UNORM",
8560	"xDXFMT_BC1_UNORM",
8561	"xDXFMT_BC2_UNORM",
8562	"xDXFMT_BC3_UNORM",
8563	"xDXFMT_B5G6R5_UNORM",
8564	"xDXFMT_B5G5R5A1_UNORM",
8565	"xDXFMT_B8G8R8A8_UNORM",
8566	"xDXFMT_B8G8R8X8_UNORM",
8567	"xDXFMT_BC4_UNORM",
8568	"xDXFMT_BC5_UNORM",
8569	};
8570
8571	/**
8572	* Initializes the host 3D capabilities and writes them to FIFO memory.
8573	*
8574	* @returns VBox status code.
8575	* @param pThis The shared VGA/VMSVGA instance data.
8576	* @param pThisCC The VGA/VMSVGA state for ring-3.
8577	*/
8578	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
8579	{
8580	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
8581	bool const fSavedBuffering = RTLogRelSetBuffering(true);
8582
8583	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
8584	{
8585	uint32_t val = 0;
8586	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
8587	if (RT_SUCCESS(rc))
8588	pThis->svga.au32DevCaps[i] = val;
8589	else
8590	pThis->svga.au32DevCaps[i] = 0;
8591
8592	/* LogRel the capability value. */
8593	if (i < RT_ELEMENTS(g_apszVmSvgaDevCapNames))
8594	{
8595	if (RT_SUCCESS(rc))
8596	{
8597	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
8598	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
8599	else
8600	{
8601	float const fval = (float )&val;
8602	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), &g_apszVmSvgaDevCapNames[i][1]));
8603	}
8604	}
8605	else
8606	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
8607	}
8608	else
8609	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
8610	}
8611
8612	RTLogRelSetBuffering(fSavedBuffering);
8613
8614	/* 3d hardware version; latest and greatest */
8615	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
8616	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
8617
8618	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
8619	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
8620	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
8621	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
8622	*/
8623	SVGA3dCapsRecord *pCaps;
8624	SVGA3dCapPair *pData;
8625
8626	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
8627	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
8628	pData = (SVGA3dCapPair *)&pCaps->data;
8629
8630	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
8631	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
8632	{
8633	pData[i][0] = i;
8634	pData[i][1] = pThis->svga.au32DevCaps[i];
8635	}
8636	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
8637	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
8638
8639	/* Mark end of record array (a zero word). */
8640	pCaps->header.length = 0;
8641	}
8642
8643	# endif
8644
8645	/**
8646	* Resets the SVGA hardware state
8647	*
8648	* @returns VBox status code.
8649	* @param pDevIns The device instance.
8650	*/
8651	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
8652	{
8653	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8654	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8655	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
8656
8657	/* Reset before init? */
8658	if (!pSVGAState)
8659	return VINF_SUCCESS;
8660
8661	Log(("vmsvgaR3Reset\n"));
8662
8663	/* Reset the FIFO processing as well as the 3d state (if we have one). */
8664	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
8665	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
8666
8667	/* Reset other stuff. */
8668	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
8669	RT_ZERO(pThis->svga.au32ScratchRegion);
8670
8671	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
8672	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
8673
8674	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
8675
8676	/* Initialize FIFO and register capabilities. */
8677	vmsvgaR3InitCaps(pThis, pThisCC);
8678
8679	# ifdef VBOX_WITH_VMSVGA3D
8680	if (pThis->svga.f3DEnabled)
8681	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
8682	# endif
8683
8684	/* VRAM tracking is enabled by default during bootup. */
8685	pThis->svga.fVRAMTracking = true;
8686	pThis->svga.fEnabled = false;
8687
8688	/* Invalidate current settings. */
8689	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
8690	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
8691	pThis->svga.uBpp = pThis->svga.uHostBpp;
8692	pThis->svga.cbScanline = 0;
8693	pThis->svga.u32PitchLock = 0;
8694
8695	return rc;
8696	}
8697
8698	/**
8699	* Cleans up the SVGA hardware state
8700	*
8701	* @returns VBox status code.
8702	* @param pDevIns The device instance.
8703	*/
8704	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
8705	{
8706	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8707	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8708
8709	/*
8710	* Ask the FIFO thread to terminate the 3d state and then terminate it.
8711	*/
8712	if (pThisCC->svga.pFIFOIOThread)
8713	{
8714	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
8715	NULL /pvParam/, 30000 /ms/);
8716	AssertLogRelRC(rc);
8717
8718	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
8719	AssertLogRelRC(rc);
8720	pThisCC->svga.pFIFOIOThread = NULL;
8721	}
8722
8723	/*
8724	* Destroy the special SVGA state.
8725	*/
8726	if (pThisCC->svga.pSvgaR3State)
8727	{
8728	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
8729
8730	RTMemFree(pThisCC->svga.pSvgaR3State);
8731	pThisCC->svga.pSvgaR3State = NULL;
8732	}
8733
8734	/*
8735	* Free our resources residing in the VGA state.
8736	*/
8737	if (pThisCC->svga.pbVgaFrameBufferR3)
8738	{
8739	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
8740	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
8741	}
8742	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
8743	{
8744	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
8745	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
8746	}
8747	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
8748	{
8749	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
8750	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
8751	}
8752
8753	return VINF_SUCCESS;
8754	}
8755
8756	/**
8757	* Initialize the SVGA hardware state
8758	*
8759	* @returns VBox status code.
8760	* @param pDevIns The device instance.
8761	*/
8762	int vmsvgaR3Init(PPDMDEVINS pDevIns)
8763	{
8764	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8765	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8766	PVMSVGAR3STATE pSVGAState;
8767	int rc;
8768
8769	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
8770	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
8771
8772	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
8773
8774	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
8775	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
8776	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
8777
8778	/* Create event semaphore. */
8779	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
8780	AssertRCReturn(rc, rc);
8781
8782	/* Create event semaphore. */
8783	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
8784	AssertRCReturn(rc, rc);
8785
8786	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
8787	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
8788
8789	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
8790	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
8791
8792	pSVGAState = pThisCC->svga.pSvgaR3State;
8793
8794	/* Initialize FIFO and register capabilities. */
8795	vmsvgaR3InitCaps(pThis, pThisCC);
8796
8797	# ifdef VBOX_WITH_VMSVGA3D
8798	if (pThis->svga.f3DEnabled)
8799	{
8800	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
8801	if (RT_FAILURE(rc))
8802	{
8803	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
8804	pThis->svga.f3DEnabled = false;
8805	}
8806	}
8807	# endif
8808	/* VRAM tracking is enabled by default during bootup. */
8809	pThis->svga.fVRAMTracking = true;
8810
8811	/* Set up the host bpp. This value is as a default for the programmable
8812	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
8813	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
8814	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
8815	*
8816	* NB: The driver cBits value is currently constant for the lifetime of the
8817	* VM. If that changes, the host bpp logic might need revisiting.
8818	*/
8819	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
8820
8821	/* Invalidate current settings. */
8822	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
8823	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
8824	pThis->svga.uBpp = pThis->svga.uHostBpp;
8825	pThis->svga.cbScanline = 0;
8826
8827	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
8828	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
8829	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
8830	{
8831	pThis->svga.u32MaxWidth -= 256;
8832	pThis->svga.u32MaxHeight -= 256;
8833	}
8834	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
8835
8836	# ifdef DEBUG_GMR_ACCESS
8837	/* Register the GMR access handler type. */
8838	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
8839	vmsvgaR3GmrAccessHandler,
8840	NULL, NULL, NULL,
8841	NULL, NULL, NULL,
8842	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
8843	AssertRCReturn(rc, rc);
8844	# endif
8845
8846	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
8847	/* Register the FIFO access handler type. In addition to
8848	debugging FIFO access, this is also used to facilitate
8849	extended fifo thread sleeps. */
8850	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
8851	# ifdef DEBUG_FIFO_ACCESS
8852	PGMPHYSHANDLERKIND_ALL,
8853	# else
8854	PGMPHYSHANDLERKIND_WRITE,
8855	# endif
8856	vmsvgaR3FifoAccessHandler,
8857	NULL, NULL, NULL,
8858	NULL, NULL, NULL,
8859	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
8860	AssertRCReturn(rc, rc);
8861	# endif
8862
8863	/* Create the async IO thread. */
8864	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
8865	RTTHREADTYPE_IO, "VMSVGA FIFO");
8866	if (RT_FAILURE(rc))
8867	{
8868	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
8869	return rc;
8870	}
8871
8872	/*
8873	* Statistics.
8874	*/
8875	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
8876	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
8877	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
8878	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
8879	# ifdef VBOX_WITH_STATISTICS
8880	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
8881	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
8882	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
8883	# endif
8884	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
8885	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
8886	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
8887	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
8888	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
8889	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
8890	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
8891	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
8892	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
8893	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
8894	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
8895	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
8896	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
8897	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
8898	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
8899	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
8900	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
8901	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
8902	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
8903	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
8904	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
8905	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
8906	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
8907	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
8908	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
8909	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
8910	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
8911	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
8912	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
8913	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
8914	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
8915	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
8916	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
8917	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
8918	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
8919	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
8920	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
8921	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
8922	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
8923	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
8924	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
8925	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
8926	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
8927	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
8928	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
8929	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
8930	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
8931	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
8932	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
8933	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
8934	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
8935	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
8936	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
8937	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
8938	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
8939	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
8940	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
8941	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
8942	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
8943
8944	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
8945	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
8946	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
8947	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
8948	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
8949	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
8950	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
8951	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
8952	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
8953	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
8954	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
8955	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
8956	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
8957	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
8958	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
8959	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
8960	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
8961	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
8962	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
8963	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
8964	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
8965	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
8966	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
8967	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
8968	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
8969	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
8970	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
8971	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
8972	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
8973	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
8974	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
8975	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
8976	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
8977	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
8978	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
8979	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
8980	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
8981	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
8982	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
8983	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_iCMD_PREPEND_HIGH writes.");
8984
8985	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
8986	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
8987	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
8988	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
8989	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
8990	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
8991	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
8992	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
8993	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
8994	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
8995	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
8996	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
8997	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
8998	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
8999	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
9000	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
9001	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
9002	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
9003	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
9004	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
9005	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
9006	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
9007	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
9008	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
9009	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
9010	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
9011	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
9012	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
9013	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
9014	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
9015	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
9016	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
9017	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
9018	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
9019	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
9020	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
9021	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
9022	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
9023	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
9024	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
9025	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
9026	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
9027	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
9028	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
9029	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
9030	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
9031	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
9032	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
9033	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
9034	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
9035	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
9036	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
9037	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
9038	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
9039	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
9040	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
9041	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
9042	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
9043	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_iCMD_PREPEND_HIGH reads.");
9044	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
9045	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
9046	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
9047
9048	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
9049	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
9050	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
9051	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
9052	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
9053	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
9054	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
9055	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
9056	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
9057	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
9058	# endif
9059	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
9060	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
9061	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
9062	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
9063	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
9064
9065	# undef REG_CNT
9066	# undef REG_PRF
9067
9068	/*
9069	* Info handlers.
9070	*/
9071	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
9072	# ifdef VBOX_WITH_VMSVGA3D
9073	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
9074	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
9075	"VMSVGA 3d surface details. "
9076	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
9077	vmsvgaR3Info3dSurface);
9078	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
9079	"VMSVGA 3d surface details and bitmap: "
9080	"sid[>dir]",
9081	vmsvgaR3Info3dSurfaceBmp);
9082	# endif
9083
9084	return VINF_SUCCESS;
9085	}
9086
9087	/**
9088	* Power On notification.
9089	*
9090	* @returns VBox status code.
9091	* @param pDevIns The device instance data.
9092	*
9093	* @remarks Caller enters the device critical section.
9094	*/
9095	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
9096	{
9097	# ifdef VBOX_WITH_VMSVGA3D
9098	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
9099	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
9100	if (pThis->svga.f3DEnabled)
9101	{
9102	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
9103	if (RT_SUCCESS(rc))
9104	{
9105	/* Initialize FIFO 3D capabilities. */
9106	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
9107	}
9108	}
9109	# else /* !VBOX_WITH_VMSVGA3D */
9110	RT_NOREF(pDevIns);
9111	# endif /* !VBOX_WITH_VMSVGA3D */
9112	}
9113
9114	/**
9115	* Power Off notification.
9116	*
9117	* @param pDevIns The device instance data.
9118	*
9119	* @remarks Caller enters the device critical section.
9120	*/
9121	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
9122	{
9123	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
9124	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
9125
9126	/*
9127	* Notify the FIFO thread.
9128	*/
9129	if (pThisCC->svga.pFIFOIOThread)
9130	{
9131	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
9132	NULL /pvParam/, 30000 /ms/);
9133	AssertLogRelRC(rc);
9134	}
9135	}
9136
9137	#endif /* IN_RING3 */

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 86237

以其他格式下載: