DevVGA-SVGA.cpp@ 82110

最後變更在這個檔案從82110是 82110,由 vboxsync 提交於 5 年前
DevVGA: Darwin fixes. bugref:9218
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1	/* $Id: DevVGA-SVGA.cpp 82110 2019-11-22 20:40:12Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.alldomusa.eu.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFOExtCmdSem),
524	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
527	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
528	SSMFIELD_ENTRY( VMSVGAState, uWidth),
529	SSMFIELD_ENTRY( VMSVGAState, uHeight),
530	SSMFIELD_ENTRY( VMSVGAState, uBpp),
531	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
532	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
533	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
535	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
536	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
537	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
538	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
541	SSMFIELD_ENTRY_TERM()
542	};
543	#endif /* IN_RING3 */
544
545
546	/*********************************************************************************************************************************
547	* Internal Functions *
548	*********************************************************************************************************************************/
549	#ifdef IN_RING3
550	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
551	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
552	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM);
553	#endif /* IN_RING3 */
554
555
556
557	#ifdef IN_RING3
558	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATE pThis, uint32_t idScreen)
559	{
560	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
561	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
562	&& pSVGAState
563	&& pSVGAState->aScreens[idScreen].fDefined)
564	{
565	return &pSVGAState->aScreens[idScreen];
566	}
567	return NULL;
568	}
569	#endif /* IN_RING3 */
570
571	#ifdef LOG_ENABLED
572
573	/**
574	* Index register string name lookup
575	*
576	* @returns Index register string or "UNKNOWN"
577	* @param pThis The shared VGA/VMSVGA state.
578	* @param idxReg The index register.
579	*/
580	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
581	{
582	switch (idxReg)
583	{
584	case SVGA_REG_ID: return "SVGA_REG_ID";
585	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
586	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
587	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
588	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
589	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
590	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
591	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
592	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
593	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
594	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
595	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
596	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
597	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
598	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
599	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
600	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
601	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
602	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
603	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
604	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
605	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
606	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
607	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
608	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
609	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
610	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
611	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
612	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
613	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
614	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
615	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
616	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
617	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
618	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
619	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
620	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
621	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
622	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
623	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
624	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
625	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
626	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
627	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
628	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
629	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
630	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
631	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
632	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
633	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
634
635	default:
636	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
637	return "SVGA_SCRATCH_BASE reg";
638	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
639	return "SVGA_PALETTE_BASE reg";
640	return "UNKNOWN";
641	}
642	}
643
644	#ifdef IN_RING3
645	/**
646	* FIFO command name lookup
647	*
648	* @returns FIFO command string or "UNKNOWN"
649	* @param u32Cmd FIFO command
650	*/
651	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
652	{
653	switch (u32Cmd)
654	{
655	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
656	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
657	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
658	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
659	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
660	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
661	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
662	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
663	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
664	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
665	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
666	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
667	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
668	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
669	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
670	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
671	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
672	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
673	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
674	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
675	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
676	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
677	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
678	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
679	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
680	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
681	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
682	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
683	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
684	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
685	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
686	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
687	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
688	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
689	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
690	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
691	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
692	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
693	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
694	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
695	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
696	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
697	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
698	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
699	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
700	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
701	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
702	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
703	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
704	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
705	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
706	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
707	default: return "UNKNOWN";
708	}
709	}
710	# endif /* IN_RING3 */
711
712	#endif /* LOG_ENABLED */
713
714	#ifdef IN_RING3
715	/**
716	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
717	*/
718	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
719	{
720	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
721	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
722
723	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
724	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
725
726	/** @todo Test how it interacts with multiple screen objects. */
727	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, idScreen);
728	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
729	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
730
731	if (x < uWidth)
732	{
733	pThis->svga.viewport.x = x;
734	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
735	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
736	}
737	else
738	{
739	pThis->svga.viewport.x = uWidth;
740	pThis->svga.viewport.cx = 0;
741	pThis->svga.viewport.xRight = uWidth;
742	}
743	if (y < uHeight)
744	{
745	pThis->svga.viewport.y = y;
746	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
747	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
748	pThis->svga.viewport.yHighWC = uHeight - y;
749	}
750	else
751	{
752	pThis->svga.viewport.y = uHeight;
753	pThis->svga.viewport.cy = 0;
754	pThis->svga.viewport.yLowWC = 0;
755	pThis->svga.viewport.yHighWC = 0;
756	}
757
758	# ifdef VBOX_WITH_VMSVGA3D
759	/*
760	* Now inform the 3D backend.
761	*/
762	if (pThis->svga.f3DEnabled)
763	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
764	# else
765	RT_NOREF(OldViewport);
766	# endif
767	}
768	#endif /* IN_RING3 */
769
770	/**
771	* Read port register
772	*
773	* @returns VBox status code.
774	* @param pDevIns The device instance.
775	* @param pThis The shared VGA/VMSVGA state.
776	* @param pu32 Where to store the read value
777	*/
778	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
779	{
780	#ifdef IN_RING3
781	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
782	#endif
783	int rc = VINF_SUCCESS;
784	*pu32 = 0;
785
786	/* Rough index register validation. */
787	uint32_t idxReg = pThis->svga.u32IndexReg;
788	#if !defined(IN_RING3) && defined(VBOX_STRICT)
789	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
790	VINF_IOM_R3_IOPORT_READ);
791	#else
792	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
793	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
794	VINF_SUCCESS);
795	#endif
796	RT_UNTRUSTED_VALIDATED_FENCE();
797
798	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
799	if ( idxReg >= SVGA_REG_CAPABILITIES
800	&& pThis->svga.u32SVGAId == SVGA_ID_0)
801	{
802	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
803	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
804	}
805
806	switch (idxReg)
807	{
808	case SVGA_REG_ID:
809	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
810	*pu32 = pThis->svga.u32SVGAId;
811	break;
812
813	case SVGA_REG_ENABLE:
814	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
815	*pu32 = pThis->svga.fEnabled;
816	break;
817
818	case SVGA_REG_WIDTH:
819	{
820	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
821	if ( pThis->svga.fEnabled
822	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
823	*pu32 = pThis->svga.uWidth;
824	else
825	{
826	#ifndef IN_RING3
827	rc = VINF_IOM_R3_IOPORT_READ;
828	#else
829	*pu32 = pThisCC->pDrv->cx;
830	#endif
831	}
832	break;
833	}
834
835	case SVGA_REG_HEIGHT:
836	{
837	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
838	if ( pThis->svga.fEnabled
839	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
840	*pu32 = pThis->svga.uHeight;
841	else
842	{
843	#ifndef IN_RING3
844	rc = VINF_IOM_R3_IOPORT_READ;
845	#else
846	*pu32 = pThisCC->pDrv->cy;
847	#endif
848	}
849	break;
850	}
851
852	case SVGA_REG_MAX_WIDTH:
853	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
854	*pu32 = pThis->svga.u32MaxWidth;
855	break;
856
857	case SVGA_REG_MAX_HEIGHT:
858	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
859	*pu32 = pThis->svga.u32MaxHeight;
860	break;
861
862	case SVGA_REG_DEPTH:
863	/* This returns the color depth of the current mode. */
864	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
865	switch (pThis->svga.uBpp)
866	{
867	case 15:
868	case 16:
869	case 24:
870	*pu32 = pThis->svga.uBpp;
871	break;
872
873	default:
874	case 32:
875	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
876	break;
877	}
878	break;
879
880	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
881	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
882	if ( pThis->svga.fEnabled
883	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
884	*pu32 = pThis->svga.uBpp;
885	else
886	{
887	#ifndef IN_RING3
888	rc = VINF_IOM_R3_IOPORT_READ;
889	#else
890	*pu32 = pThisCC->pDrv->cBits;
891	#endif
892	}
893	break;
894
895	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
896	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
897	if ( pThis->svga.fEnabled
898	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
899	*pu32 = (pThis->svga.uBpp + 7) & ~7;
900	else
901	{
902	#ifndef IN_RING3
903	rc = VINF_IOM_R3_IOPORT_READ;
904	#else
905	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
906	#endif
907	}
908	break;
909
910	case SVGA_REG_PSEUDOCOLOR:
911	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
912	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
913	break;
914
915	case SVGA_REG_RED_MASK:
916	case SVGA_REG_GREEN_MASK:
917	case SVGA_REG_BLUE_MASK:
918	{
919	uint32_t uBpp;
920
921	if ( pThis->svga.fEnabled
922	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
923	{
924	uBpp = pThis->svga.uBpp;
925	}
926	else
927	{
928	#ifndef IN_RING3
929	rc = VINF_IOM_R3_IOPORT_READ;
930	break;
931	#else
932	uBpp = pThisCC->pDrv->cBits;
933	#endif
934	}
935	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
936	switch (uBpp)
937	{
938	case 8:
939	u32RedMask = 0x07;
940	u32GreenMask = 0x38;
941	u32BlueMask = 0xc0;
942	break;
943
944	case 15:
945	u32RedMask = 0x0000001f;
946	u32GreenMask = 0x000003e0;
947	u32BlueMask = 0x00007c00;
948	break;
949
950	case 16:
951	u32RedMask = 0x0000001f;
952	u32GreenMask = 0x000007e0;
953	u32BlueMask = 0x0000f800;
954	break;
955
956	case 24:
957	case 32:
958	default:
959	u32RedMask = 0x00ff0000;
960	u32GreenMask = 0x0000ff00;
961	u32BlueMask = 0x000000ff;
962	break;
963	}
964	switch (idxReg)
965	{
966	case SVGA_REG_RED_MASK:
967	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
968	*pu32 = u32RedMask;
969	break;
970
971	case SVGA_REG_GREEN_MASK:
972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
973	*pu32 = u32GreenMask;
974	break;
975
976	case SVGA_REG_BLUE_MASK:
977	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
978	*pu32 = u32BlueMask;
979	break;
980	}
981	break;
982	}
983
984	case SVGA_REG_BYTES_PER_LINE:
985	{
986	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
987	if ( pThis->svga.fEnabled
988	&& pThis->svga.cbScanline)
989	*pu32 = pThis->svga.cbScanline;
990	else
991	{
992	#ifndef IN_RING3
993	rc = VINF_IOM_R3_IOPORT_READ;
994	#else
995	*pu32 = pThisCC->pDrv->cbScanline;
996	#endif
997	}
998	break;
999	}
1000
1001	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1002	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1003	*pu32 = pThis->vram_size;
1004	break;
1005
1006	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1007	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1008	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1009	*pu32 = pThis->GCPhysVRAM;
1010	break;
1011
1012	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1013	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1014	/* Always zero in our case. */
1015	*pu32 = 0;
1016	break;
1017
1018	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1019	{
1020	#ifndef IN_RING3
1021	rc = VINF_IOM_R3_IOPORT_READ;
1022	#else
1023	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1024
1025	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1026	if ( pThis->svga.fEnabled
1027	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1028	{
1029	/* Hardware enabled; return real framebuffer size .*/
1030	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1031	}
1032	else
1033	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1034
1035	pu32 = RT_MIN(pThis->vram_size, pu32);
1036	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1037	#endif
1038	break;
1039	}
1040
1041	case SVGA_REG_CAPABILITIES:
1042	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1043	*pu32 = pThis->svga.u32RegCaps;
1044	break;
1045
1046	case SVGA_REG_MEM_START: /* FIFO start */
1047	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1048	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1049	*pu32 = pThis->svga.GCPhysFIFO;
1050	break;
1051
1052	case SVGA_REG_MEM_SIZE: /* FIFO size */
1053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1054	*pu32 = pThis->svga.cbFIFO;
1055	break;
1056
1057	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1059	*pu32 = pThis->svga.fConfigured;
1060	break;
1061
1062	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1063	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1064	*pu32 = 0;
1065	break;
1066
1067	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1069	if (pThis->svga.fBusy)
1070	{
1071	#ifndef IN_RING3
1072	/* Go to ring-3 and halt the CPU. */
1073	rc = VINF_IOM_R3_IOPORT_READ;
1074	RT_NOREF(pDevIns);
1075	break;
1076	#else
1077	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1078	/* The guest is basically doing a HLT via the device here, but with
1079	a special wake up condition on FIFO completion. */
1080	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1081	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1082	PVM pVM = PDMDevHlpGetVM(pDevIns);
1083	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1084	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1085	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1086	if (pThis->svga.fBusy)
1087	{
1088	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1089	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1090	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1091	}
1092	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1093	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1094	# else
1095
1096	/* Delay the EMT a bit so the FIFO and others can get some work done.
1097	This used to be a crude 50 ms sleep. The current code tries to be
1098	more efficient, but the consept is still very crude. */
1099	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1100	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1101	RTThreadYield();
1102	if (pThis->svga.fBusy)
1103	{
1104	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1105
1106	if (pThis->svga.fBusy && cRefs == 1)
1107	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1108	if (pThis->svga.fBusy)
1109	{
1110	/** @todo If this code is going to stay, we need to call into the halt/wait
1111	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1112	* suffer when the guest is polling on a busy FIFO. */
1113	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1114	if (cNsMaxWait >= RT_NS_100US)
1115	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1116	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1117	RT_MIN(cNsMaxWait, RT_NS_10MS));
1118	}
1119
1120	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1121	}
1122	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1123	# endif
1124	*pu32 = pThis->svga.fBusy != 0;
1125	#endif
1126	}
1127	else
1128	*pu32 = false;
1129	break;
1130
1131	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1132	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1133	*pu32 = pThis->svga.u32GuestId;
1134	break;
1135
1136	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1137	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1138	*pu32 = pThis->svga.cScratchRegion;
1139	break;
1140
1141	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1142	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1143	*pu32 = SVGA_FIFO_NUM_REGS;
1144	break;
1145
1146	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1147	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1148	*pu32 = pThis->svga.u32PitchLock;
1149	break;
1150
1151	case SVGA_REG_IRQMASK: /* Interrupt mask */
1152	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1153	*pu32 = pThis->svga.u32IrqMask;
1154	break;
1155
1156	/* See "Guest memory regions" below. */
1157	case SVGA_REG_GMR_ID:
1158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1159	*pu32 = pThis->svga.u32CurrentGMRId;
1160	break;
1161
1162	case SVGA_REG_GMR_DESCRIPTOR:
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1164	/* Write only */
1165	*pu32 = 0;
1166	break;
1167
1168	case SVGA_REG_GMR_MAX_IDS:
1169	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1170	*pu32 = pThis->svga.cGMR;
1171	break;
1172
1173	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1174	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1175	*pu32 = VMSVGA_MAX_GMR_PAGES;
1176	break;
1177
1178	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1180	*pu32 = pThis->svga.fTraces;
1181	break;
1182
1183	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1184	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1185	*pu32 = VMSVGA_MAX_GMR_PAGES;
1186	break;
1187
1188	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1189	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1190	*pu32 = VMSVGA_SURFACE_SIZE;
1191	break;
1192
1193	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1195	break;
1196
1197	/* Mouse cursor support. */
1198	case SVGA_REG_CURSOR_ID:
1199	case SVGA_REG_CURSOR_X:
1200	case SVGA_REG_CURSOR_Y:
1201	case SVGA_REG_CURSOR_ON:
1202	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1203	break;
1204
1205	/* Legacy multi-monitor support */
1206	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1207	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1208	*pu32 = 1;
1209	break;
1210
1211	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1212	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1213	*pu32 = 0;
1214	break;
1215
1216	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1217	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1218	*pu32 = 0;
1219	break;
1220
1221	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1222	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1223	*pu32 = 0;
1224	break;
1225
1226	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1227	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1228	*pu32 = 0;
1229	break;
1230
1231	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1232	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1233	*pu32 = pThis->svga.uWidth;
1234	break;
1235
1236	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1237	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1238	*pu32 = pThis->svga.uHeight;
1239	break;
1240
1241	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1242	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1243	/* We must return something sensible here otherwise the Linux driver
1244	will take a legacy code path without 3d support. This number also
1245	limits how many screens Linux guests will allow. */
1246	*pu32 = pThis->cMonitors;
1247	break;
1248
1249	default:
1250	{
1251	uint32_t offReg;
1252	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1253	{
1254	RT_UNTRUSTED_VALIDATED_FENCE();
1255	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1256	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1257	}
1258	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1259	{
1260	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1261	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1262	RT_UNTRUSTED_VALIDATED_FENCE();
1263	uint32_t u32 = pThis->last_palette[offReg / 3];
1264	switch (offReg % 3)
1265	{
1266	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1267	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1268	case 2: pu32 = u32 & 0xff; break; / blue */
1269	}
1270	}
1271	else
1272	{
1273	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1274	rc = VINF_IOM_R3_IOPORT_READ;
1275	#else
1276	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1277
1278	/* Do not assert. The guest might be reading all registers. */
1279	LogFunc(("Unknown reg=%#x\n", idxReg));
1280	#endif
1281	}
1282	break;
1283	}
1284	}
1285	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1286	return rc;
1287	}
1288
1289	#ifdef IN_RING3
1290	/**
1291	* Apply the current resolution settings to change the video mode.
1292	*
1293	* @returns VBox status code.
1294	* @param pThis The shared VGA state.
1295	* @param pThisCC The ring-3 VGA state.
1296	*/
1297	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1298	{
1299	int rc;
1300
1301	/* Always do changemode on FIFO thread. */
1302	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1303
1304	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1305
1306	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1307
1308	if (pThis->svga.fGFBRegisters)
1309	{
1310	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1311	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1312	* deletes all screens other than screen #0, and redefines screen
1313	* #0 according to the specified mode. Drivers that use
1314	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1315	*/
1316
1317	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1318	pScreen->fDefined = true;
1319	pScreen->fModified = true;
1320	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1321	pScreen->idScreen = 0;
1322	pScreen->xOrigin = 0;
1323	pScreen->yOrigin = 0;
1324	pScreen->offVRAM = 0;
1325	pScreen->cbPitch = pThis->svga.cbScanline;
1326	pScreen->cWidth = pThis->svga.uWidth;
1327	pScreen->cHeight = pThis->svga.uHeight;
1328	pScreen->cBpp = pThis->svga.uBpp;
1329
1330	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1331	{
1332	/* Delete screen. */
1333	pScreen = &pSVGAState->aScreens[iScreen];
1334	if (pScreen->fDefined)
1335	{
1336	pScreen->fModified = true;
1337	pScreen->fDefined = false;
1338	}
1339	}
1340	}
1341	else
1342	{
1343	/* "If Screen Objects are supported, they can be used to fully
1344	* replace the functionality provided by the framebuffer registers
1345	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1346	*/
1347	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1348	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1349	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1350	}
1351
1352	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1353	{
1354	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1355	if (!pScreen->fModified)
1356	continue;
1357
1358	pScreen->fModified = false;
1359
1360	VBVAINFOVIEW view;
1361	RT_ZERO(view);
1362	view.u32ViewIndex = pScreen->idScreen;
1363	// view.u32ViewOffset = 0;
1364	view.u32ViewSize = pThis->vram_size;
1365	view.u32MaxScreenSize = pThis->vram_size;
1366
1367	VBVAINFOSCREEN screen;
1368	RT_ZERO(screen);
1369	screen.u32ViewIndex = pScreen->idScreen;
1370
1371	if (pScreen->fDefined)
1372	{
1373	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1374	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1375	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1376	{
1377	Assert(pThis->svga.fGFBRegisters);
1378	continue;
1379	}
1380
1381	screen.i32OriginX = pScreen->xOrigin;
1382	screen.i32OriginY = pScreen->yOrigin;
1383	screen.u32StartOffset = pScreen->offVRAM;
1384	screen.u32LineSize = pScreen->cbPitch;
1385	screen.u32Width = pScreen->cWidth;
1386	screen.u32Height = pScreen->cHeight;
1387	screen.u16BitsPerPixel = pScreen->cBpp;
1388	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1389	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1390	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1391	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1392	}
1393	else
1394	{
1395	/* Screen is destroyed. */
1396	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1397	}
1398
1399	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
1400	AssertRC(rc);
1401	}
1402
1403	/* Last stuff. For the VGA device screenshot. */
1404	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1405	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1406	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1407	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1408	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1409
1410	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1411	if ( pThis->svga.viewport.cx == 0
1412	&& pThis->svga.viewport.cy == 0)
1413	{
1414	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1415	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1416	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1417	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1418	pThis->svga.viewport.yLowWC = 0;
1419	}
1420
1421	return VINF_SUCCESS;
1422	}
1423
1424	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1425	{
1426	VBVACMDHDR cmd;
1427	cmd.x = (int16_t)(pScreen->xOrigin + x);
1428	cmd.y = (int16_t)(pScreen->yOrigin + y);
1429	cmd.w = (uint16_t)w;
1430	cmd.h = (uint16_t)h;
1431
1432	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1433	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1434	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1435	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1436
1437	return VINF_SUCCESS;
1438	}
1439
1440	#endif /* IN_RING3 */
1441	#if defined(IN_RING0) \|\| defined(IN_RING3)
1442
1443	/**
1444	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1445	*
1446	* @param pThis The VMSVGA state.
1447	* @param fState The busy state.
1448	*/
1449	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1450	{
1451	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1452
1453	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1454	{
1455	/* Race / unfortunately scheduling. Highly unlikly. */
1456	uint32_t cLoops = 64;
1457	do
1458	{
1459	ASMNopPause();
1460	fState = (pThis->svga.fBusy != 0);
1461	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1462	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1463	}
1464	}
1465
1466
1467	/**
1468	* Update the scanline pitch in response to the guest changing mode
1469	* width/bpp.
1470	*
1471	* @param pThis The shared VGA/VMSVGA state.
1472	*/
1473	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis)
1474	{
1475	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1476	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1477	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1478	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1479
1480	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1481	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1482	* location but it has a different meaning.
1483	*/
1484	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1485	uFifoPitchLock = 0;
1486
1487	/* Sanitize values. */
1488	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1489	uFifoPitchLock = 0;
1490	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1491	uRegPitchLock = 0;
1492
1493	/* Prefer the register value to the FIFO value.*/
1494	if (uRegPitchLock)
1495	pThis->svga.cbScanline = uRegPitchLock;
1496	else if (uFifoPitchLock)
1497	pThis->svga.cbScanline = uFifoPitchLock;
1498	else
1499	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1500
1501	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1502	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1503	}
1504
1505	#endif /* IN_RING0 \|\| IN_RING3 */
1506
1507
1508	/**
1509	* Write port register
1510	*
1511	* @returns Strict VBox status code.
1512	* @param pDevIns The device instance.
1513	* @param pThis The shared VGA/VMSVGA state.
1514	* @param pThisC The VGA/VMSVGA state for the current context.
1515	* @param u32 Value to write
1516	*/
1517	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1518	{
1519	#ifdef IN_RING3
1520	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1521	#endif
1522	VBOXSTRICTRC rc = VINF_SUCCESS;
1523	RT_NOREF(pThisCC);
1524
1525	/* Rough index register validation. */
1526	uint32_t idxReg = pThis->svga.u32IndexReg;
1527	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1528	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1529	VINF_IOM_R3_IOPORT_WRITE);
1530	#else
1531	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1532	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1533	VINF_SUCCESS);
1534	#endif
1535	RT_UNTRUSTED_VALIDATED_FENCE();
1536
1537	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1538	if ( idxReg >= SVGA_REG_CAPABILITIES
1539	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1540	{
1541	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1542	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1543	}
1544	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1545	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1546	switch (idxReg)
1547	{
1548	case SVGA_REG_WIDTH:
1549	case SVGA_REG_HEIGHT:
1550	case SVGA_REG_PITCHLOCK:
1551	case SVGA_REG_BITS_PER_PIXEL:
1552	pThis->svga.fGFBRegisters = true;
1553	break;
1554	default:
1555	break;
1556	}
1557
1558	switch (idxReg)
1559	{
1560	case SVGA_REG_ID:
1561	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1562	if ( u32 == SVGA_ID_0
1563	\|\| u32 == SVGA_ID_1
1564	\|\| u32 == SVGA_ID_2)
1565	pThis->svga.u32SVGAId = u32;
1566	else
1567	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1568	break;
1569
1570	case SVGA_REG_ENABLE:
1571	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1572	#ifdef IN_RING3
1573	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1574	&& pThis->svga.fEnabled == false)
1575	{
1576	/* Make a backup copy of the first 512kb in order to save font data etc. */
1577	/** @todo should probably swap here, rather than copy + zero */
1578	memcpy(pThis->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1579	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1580	}
1581
1582	pThis->svga.fEnabled = u32;
1583	if (pThis->svga.fEnabled)
1584	{
1585	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1586	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1587	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1588	{
1589	/* Keep the current mode. */
1590	pThis->svga.uWidth = pThisCC->pDrv->cx;
1591	pThis->svga.uHeight = pThisCC->pDrv->cy;
1592	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1593	}
1594
1595	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1596	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1597	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1598	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1599	# ifdef LOG_ENABLED
1600	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1601	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1602	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1603	# endif
1604
1605	/* Disable or enable dirty page tracking according to the current fTraces value. */
1606	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1607
1608	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1609	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1610	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1611	}
1612	else
1613	{
1614	/* Restore the text mode backup. */
1615	memcpy(pThisCC->pbVRam, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1616
1617	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1618
1619	/* Enable dirty page tracking again when going into legacy mode. */
1620	vmsvgaR3SetTraces(pDevIns, pThis, true);
1621
1622	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1623	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1624	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1625
1626	/* Clear the pitch lock. */
1627	pThis->svga.u32PitchLock = 0;
1628	}
1629	#else /* !IN_RING3 */
1630	rc = VINF_IOM_R3_IOPORT_WRITE;
1631	#endif /* !IN_RING3 */
1632	break;
1633
1634	case SVGA_REG_WIDTH:
1635	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1636	if (pThis->svga.uWidth != u32)
1637	{
1638	#if defined(IN_RING3) \|\| defined(IN_RING0)
1639	pThis->svga.uWidth = u32;
1640	vmsvgaHCUpdatePitch(pThis);
1641	if (pThis->svga.fEnabled)
1642	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1643	#else
1644	rc = VINF_IOM_R3_IOPORT_WRITE;
1645	#endif
1646	}
1647	/* else: nop */
1648	break;
1649
1650	case SVGA_REG_HEIGHT:
1651	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1652	if (pThis->svga.uHeight != u32)
1653	{
1654	pThis->svga.uHeight = u32;
1655	if (pThis->svga.fEnabled)
1656	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1657	}
1658	/* else: nop */
1659	break;
1660
1661	case SVGA_REG_DEPTH:
1662	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1663	/** @todo read-only?? */
1664	break;
1665
1666	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1667	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1668	if (pThis->svga.uBpp != u32)
1669	{
1670	#if defined(IN_RING3) \|\| defined(IN_RING0)
1671	pThis->svga.uBpp = u32;
1672	vmsvgaHCUpdatePitch(pThis);
1673	if (pThis->svga.fEnabled)
1674	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1675	#else
1676	rc = VINF_IOM_R3_IOPORT_WRITE;
1677	#endif
1678	}
1679	/* else: nop */
1680	break;
1681
1682	case SVGA_REG_PSEUDOCOLOR:
1683	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1684	break;
1685
1686	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1687	#ifdef IN_RING3
1688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1689	pThis->svga.fConfigured = u32;
1690	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1691	if (!pThis->svga.fConfigured)
1692	pThis->svga.fTraces = true;
1693	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1694	#else
1695	rc = VINF_IOM_R3_IOPORT_WRITE;
1696	#endif
1697	break;
1698
1699	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1700	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1701	if ( pThis->svga.fEnabled
1702	&& pThis->svga.fConfigured)
1703	{
1704	#if defined(IN_RING3) \|\| defined(IN_RING0)
1705	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1706	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1707	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1708	vmsvgaHCSafeFifoBusyRegUpdate(pThis, true);
1709
1710	/* Kick the FIFO thread to start processing commands again. */
1711	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1712	#else
1713	rc = VINF_IOM_R3_IOPORT_WRITE;
1714	#endif
1715	}
1716	/* else nothing to do. */
1717	else
1718	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1719
1720	break;
1721
1722	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1723	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1724	break;
1725
1726	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1727	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1728	pThis->svga.u32GuestId = u32;
1729	break;
1730
1731	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1732	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1733	pThis->svga.u32PitchLock = u32;
1734	/* Should this also update the FIFO pitch lock? Unclear. */
1735	break;
1736
1737	case SVGA_REG_IRQMASK: /* Interrupt mask */
1738	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1739	pThis->svga.u32IrqMask = u32;
1740
1741	/* Irq pending after the above change? */
1742	if (pThis->svga.u32IrqStatus & u32)
1743	{
1744	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1745	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1746	}
1747	else
1748	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1749	break;
1750
1751	/* Mouse cursor support */
1752	case SVGA_REG_CURSOR_ID:
1753	case SVGA_REG_CURSOR_X:
1754	case SVGA_REG_CURSOR_Y:
1755	case SVGA_REG_CURSOR_ON:
1756	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1757	break;
1758
1759	/* Legacy multi-monitor support */
1760	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1761	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1762	break;
1763	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1764	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1765	break;
1766	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1767	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1768	break;
1769	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1770	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1771	break;
1772	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1773	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1774	break;
1775	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1776	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1777	break;
1778	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1779	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1780	break;
1781	#ifdef VBOX_WITH_VMSVGA3D
1782	/* See "Guest memory regions" below. */
1783	case SVGA_REG_GMR_ID:
1784	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1785	pThis->svga.u32CurrentGMRId = u32;
1786	break;
1787
1788	case SVGA_REG_GMR_DESCRIPTOR:
1789	# ifndef IN_RING3
1790	rc = VINF_IOM_R3_IOPORT_WRITE;
1791	break;
1792	# else /* IN_RING3 */
1793	{
1794	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1795
1796	/* Validate current GMR id. */
1797	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1798	AssertBreak(idGMR < pThis->svga.cGMR);
1799	RT_UNTRUSTED_VALIDATED_FENCE();
1800
1801	/* Free the old GMR if present. */
1802	vmsvgaR3GmrFree(pThis, idGMR);
1803
1804	/* Just undefine the GMR? */
1805	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1806	if (GCPhys == 0)
1807	{
1808	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1809	break;
1810	}
1811
1812
1813	/* Never cross a page boundary automatically. */
1814	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1815	uint32_t cPagesTotal = 0;
1816	uint32_t iDesc = 0;
1817	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1818	uint32_t cLoops = 0;
1819	RTGCPHYS GCPhysBase = GCPhys;
1820	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1821	{
1822	/* Read descriptor. */
1823	SVGAGuestMemDescriptor desc;
1824	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1825	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1826
1827	if (desc.numPages != 0)
1828	{
1829	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1830	cPagesTotal += desc.numPages;
1831	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1832
1833	if ((iDesc & 15) == 0)
1834	{
1835	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1836	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1837	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1838	}
1839
1840	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1841	paDescs[iDesc++].numPages = desc.numPages;
1842
1843	/* Continue with the next descriptor. */
1844	GCPhys += sizeof(desc);
1845	}
1846	else if (desc.ppn == 0)
1847	break; /* terminator */
1848	else /* Pointer to the next physical page of descriptors. */
1849	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1850
1851	cLoops++;
1852	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1853	}
1854
1855	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1856	if (RT_SUCCESS(rc))
1857	{
1858	/* Commit the GMR. */
1859	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1860	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1861	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1862	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1863	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1864	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1865	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1866	}
1867	else
1868	{
1869	RTMemFree(paDescs);
1870	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1871	}
1872	break;
1873	}
1874	# endif /* IN_RING3 */
1875	#endif // VBOX_WITH_VMSVGA3D
1876
1877	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1878	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1879	if (pThis->svga.fTraces == u32)
1880	break; /* nothing to do */
1881
1882	#ifdef IN_RING3
1883	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1884	#else
1885	rc = VINF_IOM_R3_IOPORT_WRITE;
1886	#endif
1887	break;
1888
1889	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1891	break;
1892
1893	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1894	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1895	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1896	break;
1897
1898	case SVGA_REG_FB_START:
1899	case SVGA_REG_MEM_START:
1900	case SVGA_REG_HOST_BITS_PER_PIXEL:
1901	case SVGA_REG_MAX_WIDTH:
1902	case SVGA_REG_MAX_HEIGHT:
1903	case SVGA_REG_VRAM_SIZE:
1904	case SVGA_REG_FB_SIZE:
1905	case SVGA_REG_CAPABILITIES:
1906	case SVGA_REG_MEM_SIZE:
1907	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1908	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1909	case SVGA_REG_BYTES_PER_LINE:
1910	case SVGA_REG_FB_OFFSET:
1911	case SVGA_REG_RED_MASK:
1912	case SVGA_REG_GREEN_MASK:
1913	case SVGA_REG_BLUE_MASK:
1914	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1915	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1916	case SVGA_REG_GMR_MAX_IDS:
1917	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1918	/* Read only - ignore. */
1919	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1920	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1921	break;
1922
1923	default:
1924	{
1925	uint32_t offReg;
1926	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1927	{
1928	RT_UNTRUSTED_VALIDATED_FENCE();
1929	pThis->svga.au32ScratchRegion[offReg] = u32;
1930	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1931	}
1932	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1933	{
1934	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1935	Btw, see rgb_to_pixel32. */
1936	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1937	u32 &= 0xff;
1938	RT_UNTRUSTED_VALIDATED_FENCE();
1939	uint32_t uRgb = pThis->last_palette[offReg / 3];
1940	switch (offReg % 3)
1941	{
1942	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1943	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1944	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1945	}
1946	pThis->last_palette[offReg / 3] = uRgb;
1947	}
1948	else
1949	{
1950	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1951	rc = VINF_IOM_R3_IOPORT_WRITE;
1952	#else
1953	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1954	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1955	#endif
1956	}
1957	break;
1958	}
1959	}
1960	return rc;
1961	}
1962
1963	/**
1964	* @callback_method_impl{FNIOMIOPORTNEWIN}
1965	*/
1966	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1967	{
1968	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
1969	RT_NOREF_PV(pvUser);
1970
1971	/* Only dword accesses. */
1972	if (cb == 4)
1973	{
1974	switch (offPort)
1975	{
1976	case SVGA_INDEX_PORT:
1977	*pu32 = pThis->svga.u32IndexReg;
1978	break;
1979
1980	case SVGA_VALUE_PORT:
1981	return vmsvgaReadPort(pDevIns, pThis, pu32);
1982
1983	case SVGA_BIOS_PORT:
1984	Log(("Ignoring BIOS port read\n"));
1985	*pu32 = 0;
1986	break;
1987
1988	case SVGA_IRQSTATUS_PORT:
1989	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1990	*pu32 = pThis->svga.u32IrqStatus;
1991	break;
1992
1993	default:
1994	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1995	*pu32 = UINT32_MAX;
1996	break;
1997	}
1998	}
1999	else
2000	{
2001	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2002	*pu32 = UINT32_MAX;
2003	}
2004	return VINF_SUCCESS;
2005	}
2006
2007	/**
2008	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2009	*/
2010	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2011	{
2012	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2013	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2014	RT_NOREF_PV(pvUser);
2015
2016	/* Only dword accesses. */
2017	if (cb == 4)
2018	switch (offPort)
2019	{
2020	case SVGA_INDEX_PORT:
2021	pThis->svga.u32IndexReg = u32;
2022	break;
2023
2024	case SVGA_VALUE_PORT:
2025	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2026
2027	case SVGA_BIOS_PORT:
2028	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2029	break;
2030
2031	case SVGA_IRQSTATUS_PORT:
2032	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2033	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2034	/* Clear the irq in case all events have been cleared. */
2035	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2036	{
2037	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2038	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2039	}
2040	break;
2041
2042	default:
2043	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2044	break;
2045	}
2046	else
2047	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2048
2049	return VINF_SUCCESS;
2050	}
2051
2052	#ifdef IN_RING3
2053
2054	# ifdef DEBUG_FIFO_ACCESS
2055	/**
2056	* Handle FIFO memory access.
2057	* @returns VBox status code.
2058	* @param pVM VM handle.
2059	* @param pThis The shared VGA/VMSVGA instance data.
2060	* @param GCPhys The access physical address.
2061	* @param fWriteAccess Read or write access
2062	*/
2063	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2064	{
2065	RT_NOREF(pVM);
2066	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2067	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2068
2069	switch (GCPhysOffset >> 2)
2070	{
2071	case SVGA_FIFO_MIN:
2072	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2073	break;
2074	case SVGA_FIFO_MAX:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_NEXT_CMD:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_STOP:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_CAPABILITIES:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_FLAGS:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_FENCE:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_3D_HWVERSION:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_PITCHLOCK:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_CURSOR_ON:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_CURSOR_X:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_CURSOR_Y:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_CURSOR_COUNT:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_RESERVED:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_CURSOR_SCREEN_ID:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_DEAD:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_3D_HWVERSION_REVISED:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_3D_CAPS_LAST:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_GUEST_3D_HWVERSION:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_FENCE_GOAL:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_BUSY:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	default:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	}
2390
2391	return VINF_EM_RAW_EMULATE_INSTR;
2392	}
2393	# endif /* DEBUG_FIFO_ACCESS */
2394
2395	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2396	/**
2397	* HC access handler for the FIFO.
2398	*
2399	* @returns VINF_SUCCESS if the handler have carried out the operation.
2400	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2401	* @param pVM VM Handle.
2402	* @param pVCpu The cross context CPU structure for the calling EMT.
2403	* @param GCPhys The physical address the guest is writing to.
2404	* @param pvPhys The HC mapping of that address.
2405	* @param pvBuf What the guest is reading/writing.
2406	* @param cbBuf How much it's reading/writing.
2407	* @param enmAccessType The access type.
2408	* @param enmOrigin Who is making the access.
2409	* @param pvUser User argument.
2410	*/
2411	static DECLCALLBACK(VBOXSTRICTRC)
2412	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2413	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2414	{
2415	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2416	PVGASTATE pThis = (PVGASTATE)pvUser;
2417	AssertPtr(pThis);
2418
2419	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2420	/*
2421	* Wake up the FIFO thread as it might have work to do now.
2422	*/
2423	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2424	AssertLogRelRC(rc);
2425	# endif
2426
2427	# ifdef DEBUG_FIFO_ACCESS
2428	/*
2429	* When in debug-fifo-access mode, we do not disable the access handler,
2430	* but leave it on as we wish to catch all access.
2431	*/
2432	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2433	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2434	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2435	/*
2436	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2437	*/
2438	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2439	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2440	# endif
2441	if (RT_SUCCESS(rc))
2442	return VINF_PGM_HANDLER_DO_DEFAULT;
2443	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2444	return rc;
2445	}
2446	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2447
2448	#endif /* IN_RING3 */
2449
2450	#ifdef DEBUG_GMR_ACCESS
2451	# ifdef IN_RING3
2452
2453	/**
2454	* HC access handler for the FIFO.
2455	*
2456	* @returns VINF_SUCCESS if the handler have carried out the operation.
2457	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2458	* @param pVM VM Handle.
2459	* @param pVCpu The cross context CPU structure for the calling EMT.
2460	* @param GCPhys The physical address the guest is writing to.
2461	* @param pvPhys The HC mapping of that address.
2462	* @param pvBuf What the guest is reading/writing.
2463	* @param cbBuf How much it's reading/writing.
2464	* @param enmAccessType The access type.
2465	* @param enmOrigin Who is making the access.
2466	* @param pvUser User argument.
2467	*/
2468	static DECLCALLBACK(VBOXSTRICTRC)
2469	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2470	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2471	{
2472	PVGASTATE pThis = (PVGASTATE)pvUser;
2473	Assert(pThis);
2474	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2475	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2476
2477	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2478
2479	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2480	{
2481	PGMR pGMR = &pSVGAState->paGMR[i];
2482
2483	if (pGMR->numDescriptors)
2484	{
2485	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2486	{
2487	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2488	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2489	{
2490	/*
2491	* Turn off the write handler for this particular page and make it R/W.
2492	* Then return telling the caller to restart the guest instruction.
2493	*/
2494	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2495	AssertRC(rc);
2496	return VINF_PGM_HANDLER_DO_DEFAULT;
2497	}
2498	}
2499	}
2500	}
2501
2502	return VINF_PGM_HANDLER_DO_DEFAULT;
2503	}
2504
2505	/** Callback handler for VMR3ReqCallWaitU */
2506	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2507	{
2508	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2509	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2510	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2511	int rc;
2512
2513	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2514	{
2515	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2516	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2517	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2518	AssertRC(rc);
2519	}
2520	return VINF_SUCCESS;
2521	}
2522
2523	/** Callback handler for VMR3ReqCallWaitU */
2524	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2525	{
2526	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2527	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2528	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2529
2530	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2531	{
2532	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2533	AssertRC(rc);
2534	}
2535	return VINF_SUCCESS;
2536	}
2537
2538	/** Callback handler for VMR3ReqCallWaitU */
2539	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2540	{
2541	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2542
2543	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2544	{
2545	PGMR pGMR = &pSVGAState->paGMR[i];
2546
2547	if (pGMR->numDescriptors)
2548	{
2549	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2550	{
2551	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2552	AssertRC(rc);
2553	}
2554	}
2555	}
2556	return VINF_SUCCESS;
2557	}
2558
2559	# endif /* IN_RING3 */
2560	#endif /* DEBUG_GMR_ACCESS */
2561
2562	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2563
2564	#ifdef IN_RING3
2565
2566
2567	/**
2568	* Common worker for changing the pointer shape.
2569	*
2570	* @param pThisCC The VGA/VMSVGA state for ring-3.
2571	* @param pSVGAState The VMSVGA ring-3 instance data.
2572	* @param fAlpha Whether there is alpha or not.
2573	* @param xHot Hotspot x coordinate.
2574	* @param yHot Hotspot y coordinate.
2575	* @param cx Width.
2576	* @param cy Height.
2577	* @param pbData Heap copy of the cursor data. Consumed.
2578	* @param cbData The size of the data.
2579	*/
2580	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2581	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2582	{
2583	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2584	# ifdef LOG_ENABLED
2585	if (LogIs2Enabled())
2586	{
2587	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2588	if (!fAlpha)
2589	{
2590	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2591	for (uint32_t y = 0; y < cy; y++)
2592	{
2593	Log2(("%3u:", y));
2594	uint8_t const pbLine = &pbData[y cbAndLine];
2595	for (uint32_t x = 0; x < cx; x += 8)
2596	{
2597	uint8_t b = pbLine[x / 8];
2598	char szByte[12];
2599	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2600	szByte[1] = b & 0x40 ? '*' : ' ';
2601	szByte[2] = b & 0x20 ? '*' : ' ';
2602	szByte[3] = b & 0x10 ? '*' : ' ';
2603	szByte[4] = b & 0x08 ? '*' : ' ';
2604	szByte[5] = b & 0x04 ? '*' : ' ';
2605	szByte[6] = b & 0x02 ? '*' : ' ';
2606	szByte[7] = b & 0x01 ? '*' : ' ';
2607	szByte[8] = '\0';
2608	Log2(("%s", szByte));
2609	}
2610	Log2(("\n"));
2611	}
2612	}
2613
2614	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2615	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2616	for (uint32_t y = 0; y < cy; y++)
2617	{
2618	Log2(("%3u:", y));
2619	uint32_t const pu32Line = &pu32Xor[y cx];
2620	for (uint32_t x = 0; x < cx; x++)
2621	Log2((" %08x", pu32Line[x]));
2622	Log2(("\n"));
2623	}
2624	}
2625	# endif
2626
2627	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2628	AssertRC(rc);
2629
2630	if (pSVGAState->Cursor.fActive)
2631	RTMemFree(pSVGAState->Cursor.pData);
2632
2633	pSVGAState->Cursor.fActive = true;
2634	pSVGAState->Cursor.xHotspot = xHot;
2635	pSVGAState->Cursor.yHotspot = yHot;
2636	pSVGAState->Cursor.width = cx;
2637	pSVGAState->Cursor.height = cy;
2638	pSVGAState->Cursor.cbData = cbData;
2639	pSVGAState->Cursor.pData = pbData;
2640	}
2641
2642
2643	/**
2644	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2645	*
2646	* @param pThis The shared VGA/VMSVGA state.
2647	* @param pThisCC The VGA/VMSVGA state for ring-3.
2648	* @param pSVGAState The VMSVGA ring-3 instance data.
2649	* @param pCursor The cursor.
2650	* @param pbSrcAndMask The AND mask.
2651	* @param cbSrcAndLine The scanline length of the AND mask.
2652	* @param pbSrcXorMask The XOR mask.
2653	* @param cbSrcXorLine The scanline length of the XOR mask.
2654	*/
2655	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2656	SVGAFifoCmdDefineCursor const *pCursor,
2657	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2658	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2659	{
2660	uint32_t const cx = pCursor->width;
2661	uint32_t const cy = pCursor->height;
2662
2663	/*
2664	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2665	* The AND data uses 8-bit aligned scanlines.
2666	* The XOR data must be starting on a 32-bit boundrary.
2667	*/
2668	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2669	uint32_t cbDstAndMask = cbDstAndLine * cy;
2670	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2671	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2672
2673	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2674	AssertReturnVoid(pbCopy);
2675
2676	/* Convert the AND mask. */
2677	uint8_t *pbDst = pbCopy;
2678	uint8_t const *pbSrc = pbSrcAndMask;
2679	switch (pCursor->andMaskDepth)
2680	{
2681	case 1:
2682	if (cbSrcAndLine == cbDstAndLine)
2683	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2684	else
2685	{
2686	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2687	for (uint32_t y = 0; y < cy; y++)
2688	{
2689	memcpy(pbDst, pbSrc, cbDstAndLine);
2690	pbDst += cbDstAndLine;
2691	pbSrc += cbSrcAndLine;
2692	}
2693	}
2694	break;
2695	/* Should take the XOR mask into account for the multi-bit AND mask. */
2696	case 8:
2697	for (uint32_t y = 0; y < cy; y++)
2698	{
2699	for (uint32_t x = 0; x < cx; )
2700	{
2701	uint8_t bDst = 0;
2702	uint8_t fBit = 1;
2703	do
2704	{
2705	uintptr_t const idxPal = pbSrc[x] * 3;
2706	if ((( pThis->last_palette[idxPal]
2707	\| (pThis->last_palette[idxPal] >> 8)
2708	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2709	bDst \|= fBit;
2710	fBit <<= 1;
2711	x++;
2712	} while (x < cx && (x & 7));
2713	pbDst[(x - 1) / 8] = bDst;
2714	}
2715	pbDst += cbDstAndLine;
2716	pbSrc += cbSrcAndLine;
2717	}
2718	break;
2719	case 15:
2720	for (uint32_t y = 0; y < cy; y++)
2721	{
2722	for (uint32_t x = 0; x < cx; )
2723	{
2724	uint8_t bDst = 0;
2725	uint8_t fBit = 1;
2726	do
2727	{
2728	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2729	bDst \|= fBit;
2730	fBit <<= 1;
2731	x++;
2732	} while (x < cx && (x & 7));
2733	pbDst[(x - 1) / 8] = bDst;
2734	}
2735	pbDst += cbDstAndLine;
2736	pbSrc += cbSrcAndLine;
2737	}
2738	break;
2739	case 16:
2740	for (uint32_t y = 0; y < cy; y++)
2741	{
2742	for (uint32_t x = 0; x < cx; )
2743	{
2744	uint8_t bDst = 0;
2745	uint8_t fBit = 1;
2746	do
2747	{
2748	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2749	bDst \|= fBit;
2750	fBit <<= 1;
2751	x++;
2752	} while (x < cx && (x & 7));
2753	pbDst[(x - 1) / 8] = bDst;
2754	}
2755	pbDst += cbDstAndLine;
2756	pbSrc += cbSrcAndLine;
2757	}
2758	break;
2759	case 24:
2760	for (uint32_t y = 0; y < cy; y++)
2761	{
2762	for (uint32_t x = 0; x < cx; )
2763	{
2764	uint8_t bDst = 0;
2765	uint8_t fBit = 1;
2766	do
2767	{
2768	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2769	bDst \|= fBit;
2770	fBit <<= 1;
2771	x++;
2772	} while (x < cx && (x & 7));
2773	pbDst[(x - 1) / 8] = bDst;
2774	}
2775	pbDst += cbDstAndLine;
2776	pbSrc += cbSrcAndLine;
2777	}
2778	break;
2779	case 32:
2780	for (uint32_t y = 0; y < cy; y++)
2781	{
2782	for (uint32_t x = 0; x < cx; )
2783	{
2784	uint8_t bDst = 0;
2785	uint8_t fBit = 1;
2786	do
2787	{
2788	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2789	bDst \|= fBit;
2790	fBit <<= 1;
2791	x++;
2792	} while (x < cx && (x & 7));
2793	pbDst[(x - 1) / 8] = bDst;
2794	}
2795	pbDst += cbDstAndLine;
2796	pbSrc += cbSrcAndLine;
2797	}
2798	break;
2799	default:
2800	RTMemFree(pbCopy);
2801	AssertFailedReturnVoid();
2802	}
2803
2804	/* Convert the XOR mask. */
2805	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2806	pbSrc = pbSrcXorMask;
2807	switch (pCursor->xorMaskDepth)
2808	{
2809	case 1:
2810	for (uint32_t y = 0; y < cy; y++)
2811	{
2812	for (uint32_t x = 0; x < cx; )
2813	{
2814	/* most significant bit is the left most one. */
2815	uint8_t bSrc = pbSrc[x / 8];
2816	do
2817	{
2818	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2819	bSrc <<= 1;
2820	x++;
2821	} while ((x & 7) && x < cx);
2822	}
2823	pbSrc += cbSrcXorLine;
2824	}
2825	break;
2826	case 8:
2827	for (uint32_t y = 0; y < cy; y++)
2828	{
2829	for (uint32_t x = 0; x < cx; x++)
2830	{
2831	uint32_t u = pThis->last_palette[pbSrc[x]];
2832	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2833	}
2834	pbSrc += cbSrcXorLine;
2835	}
2836	break;
2837	case 15: /* Src: RGB-5-5-5 */
2838	for (uint32_t y = 0; y < cy; y++)
2839	{
2840	for (uint32_t x = 0; x < cx; x++)
2841	{
2842	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2843	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2844	((uValue >> 5) & 0x1f) << 3,
2845	((uValue >> 10) & 0x1f) << 3, 0);
2846	}
2847	pbSrc += cbSrcXorLine;
2848	}
2849	break;
2850	case 16: /* Src: RGB-5-6-5 */
2851	for (uint32_t y = 0; y < cy; y++)
2852	{
2853	for (uint32_t x = 0; x < cx; x++)
2854	{
2855	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2856	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2857	((uValue >> 5) & 0x3f) << 2,
2858	((uValue >> 11) & 0x1f) << 3, 0);
2859	}
2860	pbSrc += cbSrcXorLine;
2861	}
2862	break;
2863	case 24:
2864	for (uint32_t y = 0; y < cy; y++)
2865	{
2866	for (uint32_t x = 0; x < cx; x++)
2867	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2868	pbSrc += cbSrcXorLine;
2869	}
2870	break;
2871	case 32:
2872	for (uint32_t y = 0; y < cy; y++)
2873	{
2874	for (uint32_t x = 0; x < cx; x++)
2875	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2876	pbSrc += cbSrcXorLine;
2877	}
2878	break;
2879	default:
2880	RTMemFree(pbCopy);
2881	AssertFailedReturnVoid();
2882	}
2883
2884	/*
2885	* Pass it to the frontend/whatever.
2886	*/
2887	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2888	}
2889
2890
2891	/**
2892	* Worker for vmsvgaR3FifoThread that handles an external command.
2893	*
2894	* @param pDevIns The device instance.
2895	* @param pThis The shared VGA/VMSVGA instance data.
2896	* @param pThisCC The VGA/VMSVGA state for ring-3.
2897	*/
2898	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
2899	{
2900	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2901	switch (pThis->svga.u8FIFOExtCommand)
2902	{
2903	case VMSVGA_FIFO_EXTCMD_RESET:
2904	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2905	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2906	# ifdef VBOX_WITH_VMSVGA3D
2907	if (pThis->svga.f3DEnabled)
2908	{
2909	/* The 3d subsystem must be reset from the fifo thread. */
2910	vmsvga3dReset(pThis);
2911	}
2912	# endif
2913	break;
2914
2915	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2916	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2917	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2918	# ifdef VBOX_WITH_VMSVGA3D
2919	if (pThis->svga.f3DEnabled)
2920	{
2921	/* The 3d subsystem must be shut down from the fifo thread. */
2922	vmsvga3dTerminate(pThis);
2923	}
2924	# endif
2925	break;
2926
2927	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2928	{
2929	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2930	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2931	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2932	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThis, pSSM);
2933	# ifdef VBOX_WITH_VMSVGA3D
2934	if (pThis->svga.f3DEnabled)
2935	vmsvga3dSaveExec(pDevIns, pThis, pSSM);
2936	# endif
2937	break;
2938	}
2939
2940	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2941	{
2942	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2943	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2944	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2945	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2946	# ifdef VBOX_WITH_VMSVGA3D
2947	if (pThis->svga.f3DEnabled)
2948	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2949	# endif
2950	break;
2951	}
2952
2953	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2954	{
2955	# ifdef VBOX_WITH_VMSVGA3D
2956	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2957	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2958	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2959	# endif
2960	break;
2961	}
2962
2963
2964	default:
2965	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2966	break;
2967	}
2968
2969	/*
2970	* Signal the end of the external command.
2971	*/
2972	pThis->svga.pvFIFOExtCmdParam = NULL;
2973	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2974	ASMMemoryFence(); /* paranoia^2 */
2975	int rc = RTSemEventSignal(pThis->svga.hFIFOExtCmdSem);
2976	AssertLogRelRC(rc);
2977	}
2978
2979	/**
2980	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2981	* doing a job on the FIFO thread (even when it's officially suspended).
2982	*
2983	* @returns VBox status code (fully asserted).
2984	* @param pDevIns The device instance.
2985	* @param pThis The shared VGA/VMSVGA instance data.
2986	* @param uExtCmd The command to execute on the FIFO thread.
2987	* @param pvParam Pointer to command parameters.
2988	* @param cMsWait The time to wait for the command, given in
2989	* milliseconds.
2990	*/
2991	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis,
2992	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2993	{
2994	Assert(cMsWait >= RT_MS_1SEC * 5);
2995	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2996	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2997
2998	int rc;
2999	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
3000	PDMTHREADSTATE enmState = pThread->enmState;
3001	if (enmState == PDMTHREADSTATE_SUSPENDED)
3002	{
3003	/*
3004	* The thread is suspended, we have to temporarily wake it up so it can
3005	* perform the task.
3006	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3007	*/
3008	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3009	/* Post the request. */
3010	pThis->svga.fFifoExtCommandWakeup = true;
3011	pThis->svga.pvFIFOExtCmdParam = pvParam;
3012	pThis->svga.u8FIFOExtCommand = uExtCmd;
3013	ASMMemoryFence(); /* paranoia^3 */
3014
3015	/* Resume the thread. */
3016	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3017	AssertLogRelRC(rc);
3018	if (RT_SUCCESS(rc))
3019	{
3020	/* Wait. Take care in case the semaphore was already posted (same as below). */
3021	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3022	if ( rc == VINF_SUCCESS
3023	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3024	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3025	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3026	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3027
3028	/* suspend the thread */
3029	pThis->svga.fFifoExtCommandWakeup = false;
3030	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3031	AssertLogRelRC(rc2);
3032	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3033	rc = rc2;
3034	}
3035	pThis->svga.fFifoExtCommandWakeup = false;
3036	pThis->svga.pvFIFOExtCmdParam = NULL;
3037	}
3038	else if (enmState == PDMTHREADSTATE_RUNNING)
3039	{
3040	/*
3041	* The thread is running, should only happen during reset and vmsvga3dsfc.
3042	* We ASSUME not racing code here, both wrt thread state and ext commands.
3043	*/
3044	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3045	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3046
3047	/* Post the request. */
3048	pThis->svga.pvFIFOExtCmdParam = pvParam;
3049	pThis->svga.u8FIFOExtCommand = uExtCmd;
3050	ASMMemoryFence(); /* paranoia^2 */
3051	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3052	AssertLogRelRC(rc);
3053
3054	/* Wait. Take care in case the semaphore was already posted (same as above). */
3055	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3056	if ( rc == VINF_SUCCESS
3057	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3058	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3059	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3060	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3061
3062	pThis->svga.pvFIFOExtCmdParam = NULL;
3063	}
3064	else
3065	{
3066	/*
3067	* Something is wrong with the thread!
3068	*/
3069	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3070	rc = VERR_INVALID_STATE;
3071	}
3072	return rc;
3073	}
3074
3075
3076	/**
3077	* Marks the FIFO non-busy, notifying any waiting EMTs.
3078	*
3079	* @param pDevIns The device instance.
3080	* @param pThis The shared VGA/VMSVGA instance data.
3081	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3082	* @param offFifoMin The start byte offset of the command FIFO.
3083	*/
3084	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3085	{
3086	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3087	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3088	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3089
3090	/* Wake up any waiting EMTs. */
3091	if (pSVGAState->cBusyDelayedEmts > 0)
3092	{
3093	# ifdef VMSVGA_USE_EMT_HALT_CODE
3094	PVM pVM = PDMDevHlpGetVM(pDevIns);
3095	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3096	if (idCpu != NIL_VMCPUID)
3097	{
3098	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3099	while (idCpu-- > 0)
3100	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3101	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3102	}
3103	# else
3104	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3105	AssertRC(rc2);
3106	# endif
3107	}
3108	}
3109
3110	/**
3111	* Reads (more) payload into the command buffer.
3112	*
3113	* @returns pbBounceBuf on success
3114	* @retval (void *)1 if the thread was requested to stop.
3115	* @retval NULL on FIFO error.
3116	*
3117	* @param cbPayloadReq The number of bytes of payload requested.
3118	* @param pFIFO The FIFO.
3119	* @param offCurrentCmd The FIFO byte offset of the current command.
3120	* @param offFifoMin The start byte offset of the command FIFO.
3121	* @param offFifoMax The end byte offset of the command FIFO.
3122	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3123	* always sufficient size.
3124	* @param pcbAlreadyRead How much payload we've already read into the bounce
3125	* buffer. (We will NEVER re-read anything.)
3126	* @param pThread The calling PDM thread handle.
3127	* @param pThis The shared VGA/VMSVGA instance data.
3128	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3129	* statistics collection.
3130	*/
3131	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3132	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3133	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3134	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3135	{
3136	Assert(pbBounceBuf);
3137	Assert(pcbAlreadyRead);
3138	Assert(offFifoMin < offFifoMax);
3139	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3140	Assert(offFifoMax <= pThis->svga.cbFIFO);
3141
3142	/*
3143	* Check if the requested payload size has already been satisfied .
3144	* .
3145	* When called to read more, the caller is responsible for making sure the .
3146	* new command size (cbRequsted) never is smaller than what has already .
3147	* been read.
3148	*/
3149	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3150	if (cbPayloadReq <= cbAlreadyRead)
3151	{
3152	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3153	return pbBounceBuf;
3154	}
3155
3156	/*
3157	* Commands bigger than the fifo buffer are invalid.
3158	*/
3159	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3160	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3161	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3162	NULL);
3163
3164	/*
3165	* Move offCurrentCmd past the command dword.
3166	*/
3167	offCurrentCmd += sizeof(uint32_t);
3168	if (offCurrentCmd >= offFifoMax)
3169	offCurrentCmd = offFifoMin;
3170
3171	/*
3172	* Do we have sufficient payload data available already?
3173	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3174	*/
3175	uint32_t cbAfter, cbBefore;
3176	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3177	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3178	if (offNextCmd >= offCurrentCmd)
3179	{
3180	if (RT_LIKELY(offNextCmd < offFifoMax))
3181	cbAfter = offNextCmd - offCurrentCmd;
3182	else
3183	{
3184	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3185	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3186	offNextCmd, offFifoMin, offFifoMax));
3187	cbAfter = offFifoMax - offCurrentCmd;
3188	}
3189	cbBefore = 0;
3190	}
3191	else
3192	{
3193	cbAfter = offFifoMax - offCurrentCmd;
3194	if (offNextCmd >= offFifoMin)
3195	cbBefore = offNextCmd - offFifoMin;
3196	else
3197	{
3198	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3199	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3200	offNextCmd, offFifoMin, offFifoMax));
3201	cbBefore = 0;
3202	}
3203	}
3204	if (cbAfter + cbBefore < cbPayloadReq)
3205	{
3206	/*
3207	* Insufficient, must wait for it to arrive.
3208	*/
3209	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3210	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3211	for (uint32_t i = 0;; i++)
3212	{
3213	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3214	{
3215	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3216	return (void *)(uintptr_t)1;
3217	}
3218	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3219	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3220
3221	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3222
3223	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3224	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3225	if (offNextCmd >= offCurrentCmd)
3226	{
3227	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3228	cbBefore = 0;
3229	}
3230	else
3231	{
3232	cbAfter = offFifoMax - offCurrentCmd;
3233	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3234	}
3235
3236	if (cbAfter + cbBefore >= cbPayloadReq)
3237	break;
3238	}
3239	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3240	}
3241
3242	/*
3243	* Copy out the memory and update what pcbAlreadyRead points to.
3244	*/
3245	if (cbAfter >= cbPayloadReq)
3246	memcpy(pbBounceBuf + cbAlreadyRead,
3247	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3248	cbPayloadReq - cbAlreadyRead);
3249	else
3250	{
3251	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3252	if (cbAlreadyRead < cbAfter)
3253	{
3254	memcpy(pbBounceBuf + cbAlreadyRead,
3255	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3256	cbAfter - cbAlreadyRead);
3257	cbAlreadyRead = cbAfter;
3258	}
3259	memcpy(pbBounceBuf + cbAlreadyRead,
3260	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3261	cbPayloadReq - cbAlreadyRead);
3262	}
3263	*pcbAlreadyRead = cbPayloadReq;
3264	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3265	return pbBounceBuf;
3266	}
3267
3268
3269	/**
3270	* Sends cursor position and visibility information from the FIFO to the front-end.
3271	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3272	*/
3273	static uint32_t
3274	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3275	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3276	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3277	{
3278	/*
3279	* Check if the cursor update counter has changed and try get a stable
3280	* set of values if it has. This is race-prone, especially consindering
3281	* the screen ID, but little we can do about that.
3282	*/
3283	uint32_t x, y, fVisible, idScreen;
3284	for (uint32_t i = 0; ; i++)
3285	{
3286	x = pFIFO[SVGA_FIFO_CURSOR_X];
3287	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3288	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3289	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3290	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3291	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3292	\|\| i > 3)
3293	break;
3294	if (i == 0)
3295	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3296	ASMNopPause();
3297	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3298	}
3299
3300	/*
3301	* Check if anything has changed, as calling into pDrv is not light-weight.
3302	*/
3303	if ( *pxLast == x
3304	&& *pyLast == y
3305	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3306	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3307	else
3308	{
3309	/*
3310	* Detected changes.
3311	*
3312	* We handle global, not per-screen visibility information by sending
3313	* pfnVBVAMousePointerShape without shape data.
3314	*/
3315	*pxLast = x;
3316	*pyLast = y;
3317	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3318	if (idScreen != SVGA_ID_INVALID)
3319	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3320	else if (*pfLastVisible != fVisible)
3321	{
3322	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3323	*pfLastVisible = fVisible;
3324	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3325	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3326	}
3327	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3328	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3329	}
3330
3331	/*
3332	* Update done. Signal this to the guest.
3333	*/
3334	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3335
3336	return uCursorUpdateCount;
3337	}
3338
3339
3340	/**
3341	* Checks if there is work to be done, either cursor updating or FIFO commands.
3342	*
3343	* @returns true if pending work, false if not.
3344	* @param pFIFO The FIFO to examine.
3345	* @param uLastCursorCount The last cursor update counter value.
3346	*/
3347	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3348	{
3349	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3350	return true;
3351
3352	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3353	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3354	return true;
3355
3356	return false;
3357	}
3358
3359
3360	/**
3361	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3362	*
3363	* @param pThis The shared VGA/VMSVGA instance data.
3364	*/
3365	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis)
3366	{
3367	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3368	to recheck it before doing the signalling. */
3369	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3370	AssertReturnVoid(pFIFO);
3371	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3372	&& pThis->svga.fFIFOThreadSleeping)
3373	{
3374	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3375	AssertRC(rc);
3376	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3377	}
3378	}
3379
3380
3381	/**
3382	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3383	*/
3384	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3385	{
3386	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3387	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3388	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3389	int rc;
3390
3391	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3392	return VINF_SUCCESS;
3393
3394	/*
3395	* Special mode where we only execute an external command and the go back
3396	* to being suspended. Currently, all ext cmds ends up here, with the reset
3397	* one also being eligble for runtime execution further down as well.
3398	*/
3399	if (pThis->svga.fFifoExtCommandWakeup)
3400	{
3401	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3402	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3403	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3404	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3405	else
3406	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3407	return VINF_SUCCESS;
3408	}
3409
3410
3411	/*
3412	* Signal the semaphore to make sure we don't wait for 250ms after a
3413	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3414	*/
3415	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3416
3417	/*
3418	* Allocate a bounce buffer for command we get from the FIFO.
3419	* (All code must return via the end of the function to free this buffer.)
3420	*/
3421	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3422	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3423
3424	/*
3425	* Polling/sleep interval config.
3426	*
3427	* We wait for an a short interval if the guest has recently given us work
3428	* to do, but the interval increases the longer we're kept idle. Once we've
3429	* reached the refresh timer interval, we'll switch to extended waits,
3430	* depending on it or the guest to kick us into action when needed.
3431	*
3432	* Should the refresh time go fishing, we'll just continue increasing the
3433	* sleep length till we reaches the 250 ms max after about 16 seconds.
3434	*/
3435	RTMSINTERVAL const cMsMinSleep = 16;
3436	RTMSINTERVAL const cMsIncSleep = 2;
3437	RTMSINTERVAL const cMsMaxSleep = 250;
3438	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3439	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3440
3441	/*
3442	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3443	*
3444	* Initialize with values that will detect an update from the guest.
3445	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3446	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3447	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3448	*/
3449	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3450	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3451	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3452	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3453	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3454
3455	/*
3456	* The FIFO loop.
3457	*/
3458	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3459	bool fBadOrDisabledFifo = false;
3460	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3461	{
3462	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3463	/*
3464	* Should service the run loop every so often.
3465	*/
3466	if (pThis->svga.f3DEnabled)
3467	vmsvga3dCocoaServiceRunLoop();
3468	# endif
3469
3470	/*
3471	* Unless there's already work pending, go to sleep for a short while.
3472	* (See polling/sleep interval config above.)
3473	*/
3474	if ( fBadOrDisabledFifo
3475	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3476	{
3477	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3478	Assert(pThis->cMilliesRefreshInterval > 0);
3479	if (cMsSleep < pThis->cMilliesRefreshInterval)
3480	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3481	else
3482	{
3483	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3484	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3485	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3486	# endif
3487	if ( !fBadOrDisabledFifo
3488	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3489	rc = VINF_SUCCESS;
3490	else
3491	{
3492	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3493	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3494	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3495	}
3496	}
3497	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3498	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3499	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3500	{
3501	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3502	break;
3503	}
3504	}
3505	else
3506	rc = VINF_SUCCESS;
3507	fBadOrDisabledFifo = false;
3508	if (rc == VERR_TIMEOUT)
3509	{
3510	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3511	{
3512	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3513	continue;
3514	}
3515	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3516
3517	Log(("vmsvgaR3FifoLoop: timeout\n"));
3518	}
3519	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3520	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3521	cMsSleep = cMsMinSleep;
3522
3523	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3524	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3525	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3526
3527	/*
3528	* Handle external commands (currently only reset).
3529	*/
3530	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3531	{
3532	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3533	continue;
3534	}
3535
3536	/*
3537	* The device must be enabled and configured.
3538	*/
3539	if ( !pThis->svga.fEnabled
3540	\|\| !pThis->svga.fConfigured)
3541	{
3542	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3543	fBadOrDisabledFifo = true;
3544	cMsSleep = cMsMaxSleep; /* cheat */
3545	continue;
3546	}
3547
3548	/*
3549	* Get and check the min/max values. We ASSUME that they will remain
3550	* unchanged while we process requests. A further ASSUMPTION is that
3551	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3552	* we don't read it back while in the loop.
3553	*/
3554	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3555	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3556	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3557	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3558	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3559	\|\| offFifoMax <= offFifoMin
3560	\|\| offFifoMax > pThis->svga.cbFIFO
3561	\|\| (offFifoMax & 3) != 0
3562	\|\| (offFifoMin & 3) != 0
3563	\|\| offCurrentCmd < offFifoMin
3564	\|\| offCurrentCmd > offFifoMax))
3565	{
3566	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3567	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3568	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pSVGAState, offFifoMin);
3569	fBadOrDisabledFifo = true;
3570	continue;
3571	}
3572	RT_UNTRUSTED_VALIDATED_FENCE();
3573	if (RT_UNLIKELY(offCurrentCmd & 3))
3574	{
3575	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3576	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3577	offCurrentCmd &= ~UINT32_C(3);
3578	}
3579
3580	/*
3581	* Update the cursor position before we start on the FIFO commands.
3582	*/
3583	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3584	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3585	{
3586	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3587	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3588	{ /* halfways likely */ }
3589	else
3590	{
3591	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3592	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3593	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3594	}
3595	}
3596
3597	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3598	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3599	*
3600	* Will break out of the switch on failure.
3601	* Will restart and quit the loop if the thread was requested to stop.
3602	*
3603	* @param a_PtrVar Request variable pointer.
3604	* @param a_Type Request typedef (not pointer) for casting.
3605	* @param a_cbPayloadReq How much payload to fetch.
3606	* @remarks Accesses a bunch of variables in the current scope!
3607	*/
3608	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3609	if (1) { \
3610	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3611	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3612	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3613	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3614	} else do {} while (0)
3615	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3616	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3617	* buffer after figuring out the actual command size.
3618	*
3619	* Will break out of the switch on failure.
3620	*
3621	* @param a_PtrVar Request variable pointer.
3622	* @param a_Type Request typedef (not pointer) for casting.
3623	* @param a_cbPayloadReq How much payload to fetch.
3624	* @remarks Accesses a bunch of variables in the current scope!
3625	*/
3626	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3627	if (1) { \
3628	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3629	} else do {} while (0)
3630
3631	/*
3632	* Mark the FIFO as busy.
3633	*/
3634	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3635	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3636	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3637
3638	/*
3639	* Execute all queued FIFO commands.
3640	* Quit if pending external command or changes in the thread state.
3641	*/
3642	bool fDone = false;
3643	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3644	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3645	{
3646	uint32_t cbPayload = 0;
3647	uint32_t u32IrqStatus = 0;
3648
3649	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3650
3651	/* First check any pending actions. */
3652	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3653	{
3654	vmsvgaR3ChangeMode(pThis, pThisCC);
3655	# ifdef VBOX_WITH_VMSVGA3D
3656	if (pThis->svga.p3dState != NULL)
3657	vmsvga3dChangeMode(pThis);
3658	# endif
3659	}
3660
3661	/* Check for pending external commands (reset). */
3662	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3663	break;
3664
3665	/*
3666	* Process the command.
3667	*/
3668	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3669	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3670	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3671	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3672	switch (enmCmdId)
3673	{
3674	case SVGA_CMD_INVALID_CMD:
3675	/* Nothing to do. */
3676	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3677	break;
3678
3679	case SVGA_CMD_FENCE:
3680	{
3681	SVGAFifoCmdFence *pCmdFence;
3682	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3683	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3684	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3685	{
3686	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3687	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3688
3689	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3690	{
3691	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3692	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3693	}
3694	else
3695	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3696	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3697	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3698	{
3699	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3700	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3701	}
3702	}
3703	else
3704	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3705	break;
3706	}
3707	case SVGA_CMD_UPDATE:
3708	case SVGA_CMD_UPDATE_VERBOSE:
3709	{
3710	SVGAFifoCmdUpdate *pUpdate;
3711	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3712	if (enmCmdId == SVGA_CMD_UPDATE)
3713	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3714	else
3715	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3716	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3717	/** @todo Multiple screens? */
3718	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, 0);
3719	AssertBreak(pScreen);
3720	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3721	break;
3722	}
3723
3724	case SVGA_CMD_DEFINE_CURSOR:
3725	{
3726	/* Followed by bitmap data. */
3727	SVGAFifoCmdDefineCursor *pCursor;
3728	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3729	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3730
3731	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3732	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3733	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3734	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3735	AssertBreak(pCursor->andMaskDepth <= 32);
3736	AssertBreak(pCursor->xorMaskDepth <= 32);
3737	RT_UNTRUSTED_VALIDATED_FENCE();
3738
3739	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3740	uint32_t cbAndMask = cbAndLine * pCursor->height;
3741	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3742	uint32_t cbXorMask = cbXorLine * pCursor->height;
3743	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3744
3745	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3746	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3747	break;
3748	}
3749
3750	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3751	{
3752	/* Followed by bitmap data. */
3753	uint32_t cbCursorShape, cbAndMask;
3754	uint8_t *pCursorCopy;
3755	uint32_t cbCmd;
3756
3757	SVGAFifoCmdDefineAlphaCursor *pCursor;
3758	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3759	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3760
3761	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3762
3763	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3764	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3765	RT_UNTRUSTED_VALIDATED_FENCE();
3766
3767	/* Refetch the bitmap data as well. */
3768	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3769	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3770	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3771
3772	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3773	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3774	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3775	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3776
3777	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3778	AssertBreak(pCursorCopy);
3779
3780	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3781	memset(pCursorCopy, 0xff, cbAndMask);
3782	/* Colour data */
3783	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3784
3785	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3786	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3787	break;
3788	}
3789
3790	case SVGA_CMD_ESCAPE:
3791	{
3792	/* Followed by nsize bytes of data. */
3793	SVGAFifoCmdEscape *pEscape;
3794	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3795	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3796
3797	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3798	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3799	RT_UNTRUSTED_VALIDATED_FENCE();
3800	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3801	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3802
3803	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3804	{
3805	AssertBreak(pEscape->size >= sizeof(uint32_t));
3806	RT_UNTRUSTED_VALIDATED_FENCE();
3807	uint32_t cmd = (uint32_t )(pEscape + 1);
3808	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3809
3810	switch (cmd)
3811	{
3812	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3813	{
3814	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3815	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3816	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3817
3818	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3819	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3820	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3821
3822	RT_NOREF_PV(pVideoCmd);
3823	break;
3824
3825	}
3826
3827	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3828	{
3829	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3830	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3831	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3832	RT_NOREF_PV(pVideoCmd);
3833	break;
3834	}
3835
3836	default:
3837	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3838	break;
3839	}
3840	}
3841	else
3842	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3843
3844	break;
3845	}
3846	# ifdef VBOX_WITH_VMSVGA3D
3847	case SVGA_CMD_DEFINE_GMR2:
3848	{
3849	SVGAFifoCmdDefineGMR2 *pCmd;
3850	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3851	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3852	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3853
3854	/* Validate current GMR id. */
3855	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3856	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3857	RT_UNTRUSTED_VALIDATED_FENCE();
3858
3859	if (!pCmd->numPages)
3860	{
3861	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3862	vmsvgaR3GmrFree(pThis, pCmd->gmrId);
3863	}
3864	else
3865	{
3866	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3867	if (pGMR->cMaxPages)
3868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3869
3870	/* Not sure if we should always free the descriptor, but for simplicity
3871	we do so if the new size is smaller than the current. */
3872	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3873	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3874	vmsvgaR3GmrFree(pThis, pCmd->gmrId);
3875
3876	pGMR->cMaxPages = pCmd->numPages;
3877	/* The rest is done by the REMAP_GMR2 command. */
3878	}
3879	break;
3880	}
3881
3882	case SVGA_CMD_REMAP_GMR2:
3883	{
3884	/* Followed by page descriptors or guest ptr. */
3885	SVGAFifoCmdRemapGMR2 *pCmd;
3886	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3887	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3888
3889	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3890	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3891	RT_UNTRUSTED_VALIDATED_FENCE();
3892
3893	/* Calculate the size of what comes after next and fetch it. */
3894	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3895	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3896	cbCmd += sizeof(SVGAGuestPtr);
3897	else
3898	{
3899	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3900	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3901	{
3902	cbCmd += cbPageDesc;
3903	pCmd->numPages = 1;
3904	}
3905	else
3906	{
3907	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3908	cbCmd += cbPageDesc * pCmd->numPages;
3909	}
3910	}
3911	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3912
3913	/* Validate current GMR id and size. */
3914	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3915	RT_UNTRUSTED_VALIDATED_FENCE();
3916	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3917	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3918	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3919	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3920
3921	if (pCmd->numPages == 0)
3922	break;
3923
3924	/** @todo Move to a separate function vmsvgaGMRRemap() */
3925
3926	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3927	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3928
3929	/*
3930	* We flatten the existing descriptors into a page array, overwrite the
3931	* pages specified in this command and then recompress the descriptor.
3932	*/
3933	/** @todo Optimize the GMR remap algorithm! */
3934
3935	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3936	uint64_t *paNewPage64 = NULL;
3937	if (pGMR->paDesc)
3938	{
3939	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3940
3941	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3942	AssertBreak(paNewPage64);
3943
3944	uint32_t idxPage = 0;
3945	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3946	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3947	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3948	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3949	RT_UNTRUSTED_VALIDATED_FENCE();
3950	}
3951
3952	/* Free the old GMR if present. */
3953	if (pGMR->paDesc)
3954	RTMemFree(pGMR->paDesc);
3955
3956	/* Allocate the maximum amount possible (everything non-continuous) */
3957	PVMSVGAGMRDESCRIPTOR paDescs;
3958	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3959	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3960
3961	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3962	{
3963	/** @todo */
3964	AssertFailed();
3965	pGMR->numDescriptors = 0;
3966	}
3967	else
3968	{
3969	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3970	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3971	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3972
3973	if (paNewPage64)
3974	{
3975	/* Overwrite the old page array with the new page values. */
3976	if (fGCPhys64)
3977	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3978	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3979	else
3980	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3981	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3982
3983	/* Use the updated page array instead of the command data. */
3984	fGCPhys64 = true;
3985	paPages64 = paNewPage64;
3986	pCmd->numPages = cNewTotalPages;
3987	}
3988
3989	/* The first page. */
3990	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3991	* applied to paNewPage64. */
3992	RTGCPHYS GCPhys;
3993	if (fGCPhys64)
3994	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3995	else
3996	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3997	paDescs[0].GCPhys = GCPhys;
3998	paDescs[0].numPages = 1;
3999
4000	/* Subsequent pages. */
4001	uint32_t iDescriptor = 0;
4002	for (uint32_t i = 1; i < pCmd->numPages; i++)
4003	{
4004	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4005	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4006	else
4007	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4008
4009	/* Continuous physical memory? */
4010	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4011	{
4012	Assert(paDescs[iDescriptor].numPages);
4013	paDescs[iDescriptor].numPages++;
4014	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4015	}
4016	else
4017	{
4018	iDescriptor++;
4019	paDescs[iDescriptor].GCPhys = GCPhys;
4020	paDescs[iDescriptor].numPages = 1;
4021	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4022	}
4023	}
4024
4025	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4026	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4027	pGMR->numDescriptors = iDescriptor + 1;
4028	}
4029
4030	if (paNewPage64)
4031	RTMemFree(paNewPage64);
4032
4033	# ifdef DEBUG_GMR_ACCESS
4034	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4035	# endif
4036	break;
4037	}
4038	# endif // VBOX_WITH_VMSVGA3D
4039	case SVGA_CMD_DEFINE_SCREEN:
4040	{
4041	/* The size of this command is specified by the guest and depends on capabilities. */
4042	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4043
4044	SVGAFifoCmdDefineScreen *pCmd;
4045	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4046	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4047	RT_UNTRUSTED_VALIDATED_FENCE();
4048
4049	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4050	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4051	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4052
4053	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4054	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4055	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4056
4057	uint32_t const idScreen = pCmd->screen.id;
4058	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4059
4060	uint32_t const uWidth = pCmd->screen.size.width;
4061	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4062
4063	uint32_t const uHeight = pCmd->screen.size.height;
4064	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4065
4066	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4067	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4068	AssertBreak(cbWidth <= cbPitch);
4069
4070	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4071	AssertBreak(uScreenOffset < pThis->vram_size);
4072
4073	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4074	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4075	AssertBreak( (uHeight == 0 && cbPitch == 0)
4076	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4077	RT_UNTRUSTED_VALIDATED_FENCE();
4078
4079	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4080
4081	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4082
4083	pScreen->fDefined = true;
4084	pScreen->fModified = true;
4085	pScreen->fuScreen = pCmd->screen.flags;
4086	pScreen->idScreen = idScreen;
4087	if (!fBlank)
4088	{
4089	AssertBreak(uWidth > 0 && uHeight > 0);
4090
4091	pScreen->xOrigin = pCmd->screen.root.x;
4092	pScreen->yOrigin = pCmd->screen.root.y;
4093	pScreen->cWidth = uWidth;
4094	pScreen->cHeight = uHeight;
4095	pScreen->offVRAM = uScreenOffset;
4096	pScreen->cbPitch = cbPitch;
4097	pScreen->cBpp = 32;
4098	}
4099	else
4100	{
4101	/* Keep old values. */
4102	}
4103
4104	pThis->svga.fGFBRegisters = false;
4105	vmsvgaR3ChangeMode(pThis, pThisCC);
4106	break;
4107	}
4108
4109	case SVGA_CMD_DESTROY_SCREEN:
4110	{
4111	SVGAFifoCmdDestroyScreen *pCmd;
4112	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4113	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4114
4115	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4116
4117	uint32_t const idScreen = pCmd->screenId;
4118	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4119	RT_UNTRUSTED_VALIDATED_FENCE();
4120
4121	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4122	pScreen->fModified = true;
4123	pScreen->fDefined = false;
4124	pScreen->idScreen = idScreen;
4125
4126	vmsvgaR3ChangeMode(pThis, pThisCC);
4127	break;
4128	}
4129
4130	case SVGA_CMD_DEFINE_GMRFB:
4131	{
4132	SVGAFifoCmdDefineGMRFB *pCmd;
4133	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4134	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4135
4136	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4137	pSVGAState->GMRFB.ptr = pCmd->ptr;
4138	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4139	pSVGAState->GMRFB.format = pCmd->format;
4140	break;
4141	}
4142
4143	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4144	{
4145	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4146	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4147	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4148
4149	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4150	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4151
4152	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4153	RT_UNTRUSTED_VALIDATED_FENCE();
4154
4155	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, pCmd->destScreenId);
4156	AssertBreak(pScreen);
4157
4158	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4159	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4160
4161	/* Clip destRect to the screen dimensions. */
4162	SVGASignedRect screenRect;
4163	screenRect.left = 0;
4164	screenRect.top = 0;
4165	screenRect.right = pScreen->cWidth;
4166	screenRect.bottom = pScreen->cHeight;
4167	SVGASignedRect clipRect = pCmd->destRect;
4168	vmsvgaR3ClipRect(&screenRect, &clipRect);
4169	RT_UNTRUSTED_VALIDATED_FENCE();
4170
4171	uint32_t const width = clipRect.right - clipRect.left;
4172	uint32_t const height = clipRect.bottom - clipRect.top;
4173
4174	if ( width == 0
4175	\|\| height == 0)
4176	break; /* Nothing to do. */
4177
4178	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4179	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4180
4181	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4182	* Prepare parameters for vmsvgaR3GmrTransfer.
4183	*/
4184	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4185
4186	/* Destination: host buffer which describes the screen 0 VRAM.
4187	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4188	*/
4189	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4190	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4191	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4192	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4193	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4194	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4195	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4196	+ cbScanline * clipRect.top;
4197	int32_t const cbHstPitch = cbScanline;
4198
4199	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4200	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4201	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4202	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4203	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4204
4205	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4206	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4207	gstPtr, offGst, cbGstPitch,
4208	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4209	AssertRC(rc);
4210	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4211	break;
4212	}
4213
4214	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4215	{
4216	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4217	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4218	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4219
4220	/* Note! This can fetch 3d render results as well!! */
4221	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4222	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4223
4224	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4225	RT_UNTRUSTED_VALIDATED_FENCE();
4226
4227	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, pCmd->srcScreenId);
4228	AssertBreak(pScreen);
4229
4230	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4231	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4232
4233	/* Clip destRect to the screen dimensions. */
4234	SVGASignedRect screenRect;
4235	screenRect.left = 0;
4236	screenRect.top = 0;
4237	screenRect.right = pScreen->cWidth;
4238	screenRect.bottom = pScreen->cHeight;
4239	SVGASignedRect clipRect = pCmd->srcRect;
4240	vmsvgaR3ClipRect(&screenRect, &clipRect);
4241	RT_UNTRUSTED_VALIDATED_FENCE();
4242
4243	uint32_t const width = clipRect.right - clipRect.left;
4244	uint32_t const height = clipRect.bottom - clipRect.top;
4245
4246	if ( width == 0
4247	\|\| height == 0)
4248	break; /* Nothing to do. */
4249
4250	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4251	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4252
4253	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4254	* Prepare parameters for vmsvgaR3GmrTransfer.
4255	*/
4256	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4257
4258	/* Source: host buffer which describes the screen 0 VRAM.
4259	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4260	*/
4261	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4262	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4263	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4264	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4265	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4266	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4267	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4268	+ cbScanline * clipRect.top;
4269	int32_t const cbHstPitch = cbScanline;
4270
4271	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4272	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4273	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4274	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4275	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4276
4277	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4278	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4279	gstPtr, offGst, cbGstPitch,
4280	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4281	AssertRC(rc);
4282	break;
4283	}
4284
4285	case SVGA_CMD_ANNOTATION_FILL:
4286	{
4287	SVGAFifoCmdAnnotationFill *pCmd;
4288	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4289	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4290
4291	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4292	pSVGAState->colorAnnotation = pCmd->color;
4293	break;
4294	}
4295
4296	case SVGA_CMD_ANNOTATION_COPY:
4297	{
4298	SVGAFifoCmdAnnotationCopy *pCmd;
4299	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4300	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4301
4302	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4303	AssertFailed();
4304	break;
4305	}
4306
4307	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4308
4309	default:
4310	# ifdef VBOX_WITH_VMSVGA3D
4311	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4312	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4313	{
4314	RT_UNTRUSTED_VALIDATED_FENCE();
4315
4316	/* All 3d commands start with a common header, which defines the size of the command. */
4317	SVGA3dCmdHeader *pHdr;
4318	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4319	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4320	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4321	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4322
4323	if (RT_LIKELY(pThis->svga.f3DEnabled))
4324	{ /* likely */ }
4325	else
4326	{
4327	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4328	break;
4329	}
4330
4331	/**
4332	* Check that the 3D command has at least a_cbMin of payload bytes after the
4333	* header. Will break out of the switch if it doesn't.
4334	*/
4335	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4336	if (1) { \
4337	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4338	RT_UNTRUSTED_VALIDATED_FENCE(); \
4339	} else do {} while (0)
4340	switch ((int)enmCmdId)
4341	{
4342	case SVGA_3D_CMD_SURFACE_DEFINE:
4343	{
4344	uint32_t cMipLevels;
4345	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4346	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4347	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4348
4349	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4350	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4351	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4352	# ifdef DEBUG_GMR_ACCESS
4353	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4354	# endif
4355	break;
4356	}
4357
4358	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4359	{
4360	uint32_t cMipLevels;
4361	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4362	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4363	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4364
4365	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4366	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4367	pCmd->multisampleCount, pCmd->autogenFilter,
4368	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4369	break;
4370	}
4371
4372	case SVGA_3D_CMD_SURFACE_DESTROY:
4373	{
4374	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4375	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4376	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4377	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4378	break;
4379	}
4380
4381	case SVGA_3D_CMD_SURFACE_COPY:
4382	{
4383	uint32_t cCopyBoxes;
4384	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4385	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4386	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4387
4388	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4389	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4390	break;
4391	}
4392
4393	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4394	{
4395	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4396	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4397	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4398
4399	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4400	break;
4401	}
4402
4403	case SVGA_3D_CMD_SURFACE_DMA:
4404	{
4405	uint32_t cCopyBoxes;
4406	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4407	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4408	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4409
4410	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4411	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4412	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4413	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4414	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4415	break;
4416	}
4417
4418	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4419	{
4420	uint32_t cRects;
4421	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4422	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4423	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4424
4425	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4426	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4427	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4428	break;
4429	}
4430
4431	case SVGA_3D_CMD_CONTEXT_DEFINE:
4432	{
4433	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4434	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4435	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4436
4437	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4438	break;
4439	}
4440
4441	case SVGA_3D_CMD_CONTEXT_DESTROY:
4442	{
4443	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4444	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4446
4447	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4448	break;
4449	}
4450
4451	case SVGA_3D_CMD_SETTRANSFORM:
4452	{
4453	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4454	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4455	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4456
4457	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4458	break;
4459	}
4460
4461	case SVGA_3D_CMD_SETZRANGE:
4462	{
4463	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4464	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4465	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4466
4467	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4468	break;
4469	}
4470
4471	case SVGA_3D_CMD_SETRENDERSTATE:
4472	{
4473	uint32_t cRenderStates;
4474	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4475	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4476	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4477
4478	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4479	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4480	break;
4481	}
4482
4483	case SVGA_3D_CMD_SETRENDERTARGET:
4484	{
4485	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4486	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4487	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4488
4489	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4490	break;
4491	}
4492
4493	case SVGA_3D_CMD_SETTEXTURESTATE:
4494	{
4495	uint32_t cTextureStates;
4496	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4497	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4498	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4499
4500	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4501	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4502	break;
4503	}
4504
4505	case SVGA_3D_CMD_SETMATERIAL:
4506	{
4507	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4508	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4509	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4510
4511	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4512	break;
4513	}
4514
4515	case SVGA_3D_CMD_SETLIGHTDATA:
4516	{
4517	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4518	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4519	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4520
4521	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4522	break;
4523	}
4524
4525	case SVGA_3D_CMD_SETLIGHTENABLED:
4526	{
4527	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4528	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4529	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4530
4531	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4532	break;
4533	}
4534
4535	case SVGA_3D_CMD_SETVIEWPORT:
4536	{
4537	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4538	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4539	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4540
4541	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4542	break;
4543	}
4544
4545	case SVGA_3D_CMD_SETCLIPPLANE:
4546	{
4547	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4548	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4549	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4550
4551	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4552	break;
4553	}
4554
4555	case SVGA_3D_CMD_CLEAR:
4556	{
4557	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4558	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4559	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4560
4561	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4562	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4563	break;
4564	}
4565
4566	case SVGA_3D_CMD_PRESENT:
4567	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4568	{
4569	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4570	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4571	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4572	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4573	else
4574	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4575
4576	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4577
4578	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4579	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4580	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4581	break;
4582	}
4583
4584	case SVGA_3D_CMD_SHADER_DEFINE:
4585	{
4586	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4587	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4588	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4589
4590	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4591	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4592	break;
4593	}
4594
4595	case SVGA_3D_CMD_SHADER_DESTROY:
4596	{
4597	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4598	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4599	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4600
4601	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4602	break;
4603	}
4604
4605	case SVGA_3D_CMD_SET_SHADER:
4606	{
4607	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4608	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4609	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4610
4611	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4612	break;
4613	}
4614
4615	case SVGA_3D_CMD_SET_SHADER_CONST:
4616	{
4617	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4618	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4619	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4620
4621	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4622	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4623	break;
4624	}
4625
4626	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4627	{
4628	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4629	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4630	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4631
4632	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4633	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4634	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4635	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4636	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4637
4638	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4639	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4640
4641	RT_UNTRUSTED_VALIDATED_FENCE();
4642
4643	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4644	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4645	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4646
4647	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4648	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4649	pNumRange, cVertexDivisor, pVertexDivisor);
4650	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4651	break;
4652	}
4653
4654	case SVGA_3D_CMD_SETSCISSORRECT:
4655	{
4656	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4657	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4658	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4659
4660	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4661	break;
4662	}
4663
4664	case SVGA_3D_CMD_BEGIN_QUERY:
4665	{
4666	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4667	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4668	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4669
4670	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4671	break;
4672	}
4673
4674	case SVGA_3D_CMD_END_QUERY:
4675	{
4676	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4677	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4678	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4679
4680	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4681	break;
4682	}
4683
4684	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4685	{
4686	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4687	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4689
4690	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4691	break;
4692	}
4693
4694	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4695	{
4696	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4697	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4698	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4699
4700	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4701	break;
4702	}
4703
4704	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4705	/* context id + surface id? */
4706	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4707	break;
4708	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4709	/* context id + surface id? */
4710	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4711	break;
4712
4713	default:
4714	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4715	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4716	break;
4717	}
4718	}
4719	else
4720	# endif // VBOX_WITH_VMSVGA3D
4721	{
4722	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4723	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4724	}
4725	}
4726
4727	/* Go to the next slot */
4728	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4729	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4730	if (offCurrentCmd >= offFifoMax)
4731	{
4732	offCurrentCmd -= offFifoMax - offFifoMin;
4733	Assert(offCurrentCmd >= offFifoMin);
4734	Assert(offCurrentCmd < offFifoMax);
4735	}
4736	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4737	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4738
4739	/*
4740	* Raise IRQ if required. Must enter the critical section here
4741	* before making final decisions here, otherwise cubebench and
4742	* others may end up waiting forever.
4743	*/
4744	if ( u32IrqStatus
4745	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4746	{
4747	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4748	AssertRC(rc2);
4749
4750	/* FIFO progress might trigger an interrupt. */
4751	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4752	{
4753	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4754	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4755	}
4756
4757	/* Unmasked IRQ pending? */
4758	if (pThis->svga.u32IrqMask & u32IrqStatus)
4759	{
4760	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4761	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4762	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4763	}
4764
4765	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4766	}
4767	}
4768
4769	/* If really done, clear the busy flag. */
4770	if (fDone)
4771	{
4772	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4773	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pSVGAState, offFifoMin);
4774	}
4775	}
4776
4777	/*
4778	* Free the bounce buffer. (There are no returns above!)
4779	*/
4780	RTMemFree(pbBounceBuf);
4781
4782	return VINF_SUCCESS;
4783	}
4784
4785	/**
4786	* Free the specified GMR
4787	*
4788	* @param pThis The shared VGA/VMSVGA instance data.
4789	* @param idGMR GMR id
4790	*/
4791	void vmsvgaR3GmrFree(PVGASTATE pThis, uint32_t idGMR)
4792	{
4793	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4794
4795	/* Free the old descriptor if present. */
4796	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4797	if ( pGMR->numDescriptors
4798	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4799	{
4800	# ifdef DEBUG_GMR_ACCESS
4801	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4802	# endif
4803
4804	Assert(pGMR->paDesc);
4805	RTMemFree(pGMR->paDesc);
4806	pGMR->paDesc = NULL;
4807	pGMR->numDescriptors = 0;
4808	pGMR->cbTotal = 0;
4809	pGMR->cMaxPages = 0;
4810	}
4811	Assert(!pGMR->cMaxPages);
4812	Assert(!pGMR->cbTotal);
4813	}
4814
4815	/**
4816	* Copy between a GMR and a host memory buffer.
4817	*
4818	* @returns VBox status code.
4819	* @param pThis The shared VGA/VMSVGA instance data.
4820	* @param pThisCC The VGA/VMSVGA state for ring-3.
4821	* @param enmTransferType Transfer type (read/write)
4822	* @param pbHstBuf Host buffer pointer (valid)
4823	* @param cbHstBuf Size of host buffer (valid)
4824	* @param offHst Host buffer offset of the first scanline
4825	* @param cbHstPitch Destination buffer pitch
4826	* @param gstPtr GMR description
4827	* @param offGst Guest buffer offset of the first scanline
4828	* @param cbGstPitch Guest buffer pitch
4829	* @param cbWidth Width in bytes to copy
4830	* @param cHeight Number of scanllines to copy
4831	*/
4832	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
4833	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4834	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4835	uint32_t cbWidth, uint32_t cHeight)
4836	{
4837	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4838	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
4839	int rc;
4840
4841	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4842	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4843	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4844	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4845	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4846
4847	PGMR pGMR;
4848	uint32_t cbGmr; /* The GMR size in bytes. */
4849	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4850	{
4851	pGMR = NULL;
4852	cbGmr = pThis->vram_size;
4853	}
4854	else
4855	{
4856	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4857	RT_UNTRUSTED_VALIDATED_FENCE();
4858	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4859	cbGmr = pGMR->cbTotal;
4860	}
4861
4862	/*
4863	* GMR
4864	*/
4865	/* Calculate GMR offset of the data to be copied. */
4866	AssertMsgReturn(gstPtr.offset < cbGmr,
4867	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4868	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4869	VERR_INVALID_PARAMETER);
4870	RT_UNTRUSTED_VALIDATED_FENCE();
4871	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4872	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4873	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4874	VERR_INVALID_PARAMETER);
4875	RT_UNTRUSTED_VALIDATED_FENCE();
4876	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4877
4878	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4879	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4880	AssertMsgReturn(cbGmrScanline != 0,
4881	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4882	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4883	VERR_INVALID_PARAMETER);
4884	RT_UNTRUSTED_VALIDATED_FENCE();
4885	AssertMsgReturn(cbWidth <= cbGmrScanline,
4886	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4887	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4888	VERR_INVALID_PARAMETER);
4889	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4890	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4891	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4892	VERR_INVALID_PARAMETER);
4893	RT_UNTRUSTED_VALIDATED_FENCE();
4894
4895	/* How many bytes are available for the data in the GMR. */
4896	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4897
4898	/* How many scanlines would fit into the available data. */
4899	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4900	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4901	if (cbWidth <= cbGmrLastScanline)
4902	++cGmrScanlines;
4903
4904	if (cHeight > cGmrScanlines)
4905	cHeight = cGmrScanlines;
4906
4907	AssertMsgReturn(cHeight > 0,
4908	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4909	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4910	VERR_INVALID_PARAMETER);
4911	RT_UNTRUSTED_VALIDATED_FENCE();
4912
4913	/*
4914	* Host buffer.
4915	*/
4916	AssertMsgReturn(offHst < cbHstBuf,
4917	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4918	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4919	VERR_INVALID_PARAMETER);
4920
4921	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4922	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4923	AssertMsgReturn(cbHstScanline != 0,
4924	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4925	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4926	VERR_INVALID_PARAMETER);
4927	AssertMsgReturn(cbWidth <= cbHstScanline,
4928	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4929	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4930	VERR_INVALID_PARAMETER);
4931	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4932	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4933	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4934	VERR_INVALID_PARAMETER);
4935
4936	/* How many bytes are available for the data in the buffer. */
4937	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4938
4939	/* How many scanlines would fit into the available data. */
4940	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4941	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4942	if (cbWidth <= cbHstLastScanline)
4943	++cHstScanlines;
4944
4945	if (cHeight > cHstScanlines)
4946	cHeight = cHstScanlines;
4947
4948	AssertMsgReturn(cHeight > 0,
4949	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4950	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4951	VERR_INVALID_PARAMETER);
4952
4953	uint8_t *pbHst = pbHstBuf + offHst;
4954
4955	/* Shortcut for the framebuffer. */
4956	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4957	{
4958	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
4959
4960	uint8_t const *pbSrc;
4961	int32_t cbSrcPitch;
4962	uint8_t *pbDst;
4963	int32_t cbDstPitch;
4964
4965	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4966	{
4967	pbSrc = pbHst;
4968	cbSrcPitch = cbHstPitch;
4969	pbDst = pbGst;
4970	cbDstPitch = cbGstPitch;
4971	}
4972	else
4973	{
4974	pbSrc = pbGst;
4975	cbSrcPitch = cbGstPitch;
4976	pbDst = pbHst;
4977	cbDstPitch = cbHstPitch;
4978	}
4979
4980	if ( cbWidth == (uint32_t)cbGstPitch
4981	&& cbGstPitch == cbHstPitch)
4982	{
4983	/* Entire scanlines, positive pitch. */
4984	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4985	}
4986	else
4987	{
4988	for (uint32_t i = 0; i < cHeight; ++i)
4989	{
4990	memcpy(pbDst, pbSrc, cbWidth);
4991
4992	pbDst += cbDstPitch;
4993	pbSrc += cbSrcPitch;
4994	}
4995	}
4996	return VINF_SUCCESS;
4997	}
4998
4999	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5000	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5001
5002	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5003	uint32_t iDesc = 0; /* Index in the descriptor array. */
5004	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5005	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5006	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5007	for (uint32_t i = 0; i < cHeight; ++i)
5008	{
5009	uint32_t cbCurrentWidth = cbWidth;
5010	uint32_t offGmrCurrent = offGmrScanline;
5011	uint8_t *pbCurrentHost = pbHstScanline;
5012
5013	/* Find the right descriptor */
5014	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5015	{
5016	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5017	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5018	++iDesc;
5019	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5020	}
5021
5022	while (cbCurrentWidth)
5023	{
5024	uint32_t cbToCopy;
5025
5026	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5027	{
5028	cbToCopy = cbCurrentWidth;
5029	}
5030	else
5031	{
5032	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5033	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5034	}
5035
5036	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5037
5038	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5039
5040	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5041	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5042	else
5043	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5044	AssertRCBreak(rc);
5045
5046	cbCurrentWidth -= cbToCopy;
5047	offGmrCurrent += cbToCopy;
5048	pbCurrentHost += cbToCopy;
5049
5050	/* Go to the next descriptor if there's anything left. */
5051	if (cbCurrentWidth)
5052	{
5053	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5054	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5055	++iDesc;
5056	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5057	}
5058	}
5059
5060	offGmrScanline += cbGstPitch;
5061	pbHstScanline += cbHstPitch;
5062	}
5063
5064	return VINF_SUCCESS;
5065	}
5066
5067
5068	/**
5069	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5070	*
5071	* @param pSizeSrc Source surface dimensions.
5072	* @param pSizeDest Destination surface dimensions.
5073	* @param pBox Coordinates to be clipped.
5074	*/
5075	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5076	{
5077	/* Src x, w */
5078	if (pBox->srcx > pSizeSrc->width)
5079	pBox->srcx = pSizeSrc->width;
5080	if (pBox->w > pSizeSrc->width - pBox->srcx)
5081	pBox->w = pSizeSrc->width - pBox->srcx;
5082
5083	/* Src y, h */
5084	if (pBox->srcy > pSizeSrc->height)
5085	pBox->srcy = pSizeSrc->height;
5086	if (pBox->h > pSizeSrc->height - pBox->srcy)
5087	pBox->h = pSizeSrc->height - pBox->srcy;
5088
5089	/* Src z, d */
5090	if (pBox->srcz > pSizeSrc->depth)
5091	pBox->srcz = pSizeSrc->depth;
5092	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5093	pBox->d = pSizeSrc->depth - pBox->srcz;
5094
5095	/* Dest x, w */
5096	if (pBox->x > pSizeDest->width)
5097	pBox->x = pSizeDest->width;
5098	if (pBox->w > pSizeDest->width - pBox->x)
5099	pBox->w = pSizeDest->width - pBox->x;
5100
5101	/* Dest y, h */
5102	if (pBox->y > pSizeDest->height)
5103	pBox->y = pSizeDest->height;
5104	if (pBox->h > pSizeDest->height - pBox->y)
5105	pBox->h = pSizeDest->height - pBox->y;
5106
5107	/* Dest z, d */
5108	if (pBox->z > pSizeDest->depth)
5109	pBox->z = pSizeDest->depth;
5110	if (pBox->d > pSizeDest->depth - pBox->z)
5111	pBox->d = pSizeDest->depth - pBox->z;
5112	}
5113
5114	/**
5115	* Unsigned coordinates in pBox. Clip to [0; pSize).
5116	*
5117	* @param pSize Source surface dimensions.
5118	* @param pBox Coordinates to be clipped.
5119	*/
5120	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5121	{
5122	/* x, w */
5123	if (pBox->x > pSize->width)
5124	pBox->x = pSize->width;
5125	if (pBox->w > pSize->width - pBox->x)
5126	pBox->w = pSize->width - pBox->x;
5127
5128	/* y, h */
5129	if (pBox->y > pSize->height)
5130	pBox->y = pSize->height;
5131	if (pBox->h > pSize->height - pBox->y)
5132	pBox->h = pSize->height - pBox->y;
5133
5134	/* z, d */
5135	if (pBox->z > pSize->depth)
5136	pBox->z = pSize->depth;
5137	if (pBox->d > pSize->depth - pBox->z)
5138	pBox->d = pSize->depth - pBox->z;
5139	}
5140
5141	/**
5142	* Clip.
5143	*
5144	* @param pBound Bounding rectangle.
5145	* @param pRect Rectangle to be clipped.
5146	*/
5147	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5148	{
5149	int32_t left;
5150	int32_t top;
5151	int32_t right;
5152	int32_t bottom;
5153
5154	/* Right order. */
5155	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5156	if (pRect->left < pRect->right)
5157	{
5158	left = pRect->left;
5159	right = pRect->right;
5160	}
5161	else
5162	{
5163	left = pRect->right;
5164	right = pRect->left;
5165	}
5166	if (pRect->top < pRect->bottom)
5167	{
5168	top = pRect->top;
5169	bottom = pRect->bottom;
5170	}
5171	else
5172	{
5173	top = pRect->bottom;
5174	bottom = pRect->top;
5175	}
5176
5177	if (left < pBound->left)
5178	left = pBound->left;
5179	if (right < pBound->left)
5180	right = pBound->left;
5181
5182	if (left > pBound->right)
5183	left = pBound->right;
5184	if (right > pBound->right)
5185	right = pBound->right;
5186
5187	if (top < pBound->top)
5188	top = pBound->top;
5189	if (bottom < pBound->top)
5190	bottom = pBound->top;
5191
5192	if (top > pBound->bottom)
5193	top = pBound->bottom;
5194	if (bottom > pBound->bottom)
5195	bottom = pBound->bottom;
5196
5197	pRect->left = left;
5198	pRect->right = right;
5199	pRect->top = top;
5200	pRect->bottom = bottom;
5201	}
5202
5203	/**
5204	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5205	* Unblock the FIFO I/O thread so it can respond to a state change.}
5206	*/
5207	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5208	{
5209	RT_NOREF(pDevIns);
5210	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5211	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5212	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5213	}
5214
5215	/**
5216	* Enables or disables dirty page tracking for the framebuffer
5217	*
5218	* @param pDevIns The device instance.
5219	* @param pThis The shared VGA/VMSVGA instance data.
5220	* @param fTraces Enable/disable traces
5221	*/
5222	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5223	{
5224	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5225	&& !fTraces)
5226	{
5227	//Assert(pThis->svga.fTraces);
5228	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5229	return;
5230	}
5231
5232	pThis->svga.fTraces = fTraces;
5233	if (pThis->svga.fTraces)
5234	{
5235	unsigned cbFrameBuffer = pThis->vram_size;
5236
5237	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5238	/** @todo How does this work with screens? */
5239	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5240	{
5241	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5242	Assert(pThis->svga.cbScanline);
5243	# endif
5244	/* Hardware enabled; return real framebuffer size .*/
5245	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5246	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5247	}
5248
5249	if (!pThis->svga.fVRAMTracking)
5250	{
5251	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5252	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5253	pThis->svga.fVRAMTracking = true;
5254	}
5255	}
5256	else
5257	{
5258	if (pThis->svga.fVRAMTracking)
5259	{
5260	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5261	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5262	pThis->svga.fVRAMTracking = false;
5263	}
5264	}
5265	}
5266
5267	/**
5268	* @callback_method_impl{FNPCIIOREGIONMAP}
5269	*/
5270	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5271	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5272	{
5273	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5274	int rc;
5275	RT_NOREF(pPciDev);
5276	Assert(pPciDev == pDevIns->apPciDevs[0]);
5277
5278	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5279	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5280	if (GCPhysAddress != NIL_RTGCPHYS)
5281	{
5282	/*
5283	* Mapping the FIFO RAM.
5284	*/
5285	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5286	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5287	AssertRC(rc);
5288
5289	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5290	if (RT_SUCCESS(rc))
5291	{
5292	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5293	# ifdef DEBUG_FIFO_ACCESS
5294	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5295	# else
5296	GCPhysAddress + PAGE_SIZE - 1,
5297	# endif
5298	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5299	"VMSVGA FIFO");
5300	AssertRC(rc);
5301	}
5302	# endif
5303	if (RT_SUCCESS(rc))
5304	{
5305	pThis->svga.GCPhysFIFO = GCPhysAddress;
5306	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5307	}
5308	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5309	}
5310	else
5311	{
5312	Assert(pThis->svga.GCPhysFIFO);
5313	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5314	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5315	AssertRC(rc);
5316	# else
5317	rc = VINF_SUCCESS;
5318	# endif
5319	pThis->svga.GCPhysFIFO = 0;
5320	}
5321	return rc;
5322	}
5323
5324	# ifdef VBOX_WITH_VMSVGA3D
5325
5326	/**
5327	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5328	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5329	*
5330	* @param pDevIns The device instance.
5331	* @param pThis The The shared VGA/VMSVGA instance data.
5332	* @param sid Either UINT32_MAX or the ID of a specific
5333	* surface. If UINT32_MAX is used, all surfaces
5334	* are processed.
5335	*/
5336	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid)
5337	{
5338	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5339	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5340	}
5341
5342
5343	/**
5344	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5345	*/
5346	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5347	{
5348	/* There might be a specific surface ID at the start of the
5349	arguments, if not show all surfaces. */
5350	uint32_t sid = UINT32_MAX;
5351	if (pszArgs)
5352	pszArgs = RTStrStripL(pszArgs);
5353	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5354	sid = RTStrToUInt32(pszArgs);
5355
5356	/* Verbose or terse display, we default to verbose. */
5357	bool fVerbose = true;
5358	if (RTStrIStr(pszArgs, "terse"))
5359	fVerbose = false;
5360
5361	/* The size of the ascii art (x direction, y is 3/4 of x). */
5362	uint32_t cxAscii = 80;
5363	if (RTStrIStr(pszArgs, "gigantic"))
5364	cxAscii = 300;
5365	else if (RTStrIStr(pszArgs, "huge"))
5366	cxAscii = 180;
5367	else if (RTStrIStr(pszArgs, "big"))
5368	cxAscii = 132;
5369	else if (RTStrIStr(pszArgs, "normal"))
5370	cxAscii = 80;
5371	else if (RTStrIStr(pszArgs, "medium"))
5372	cxAscii = 64;
5373	else if (RTStrIStr(pszArgs, "small"))
5374	cxAscii = 48;
5375	else if (RTStrIStr(pszArgs, "tiny"))
5376	cxAscii = 24;
5377
5378	/* Y invert the image when producing the ASCII art. */
5379	bool fInvY = false;
5380	if (RTStrIStr(pszArgs, "invy"))
5381	fInvY = true;
5382
5383	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5384	}
5385
5386
5387	/**
5388	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5389	*/
5390	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5391	{
5392	/* pszArg = "sid[>dir]"
5393	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5394	*/
5395	char *pszBitmapPath = NULL;
5396	uint32_t sid = UINT32_MAX;
5397	if (pszArgs)
5398	pszArgs = RTStrStripL(pszArgs);
5399	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5400	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5401	if ( pszBitmapPath
5402	&& *pszBitmapPath == '>')
5403	++pszBitmapPath;
5404
5405	const bool fVerbose = true;
5406	const uint32_t cxAscii = 0; /* No ASCII */
5407	const bool fInvY = false; /* Do not invert. */
5408	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5409	}
5410
5411
5412	/**
5413	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5414	*/
5415	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5416	{
5417	/* There might be a specific surface ID at the start of the
5418	arguments, if not show all contexts. */
5419	uint32_t sid = UINT32_MAX;
5420	if (pszArgs)
5421	pszArgs = RTStrStripL(pszArgs);
5422	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5423	sid = RTStrToUInt32(pszArgs);
5424
5425	/* Verbose or terse display, we default to verbose. */
5426	bool fVerbose = true;
5427	if (RTStrIStr(pszArgs, "terse"))
5428	fVerbose = false;
5429
5430	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5431	}
5432
5433	# endif /* VBOX_WITH_VMSVGA3D */
5434
5435	/**
5436	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5437	*/
5438	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5439	{
5440	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5441	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5442	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5443	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5444	RT_NOREF(pszArgs);
5445
5446	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5447	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5448	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5449	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5450	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5451	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5452	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5453	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5454	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5455	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5456	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5457	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5458	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5459	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5460	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5461	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5462	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5463	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5464	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5465	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5466	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5467	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5468	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5469	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5470	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5471
5472	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5473	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5474	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5475	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5476
5477	# ifdef VBOX_WITH_VMSVGA3D
5478	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5479	# endif
5480	if (pThisCC->pDrv)
5481	{
5482	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5483	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5484	}
5485	}
5486
5487	/**
5488	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5489	*/
5490	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5491	{
5492	RT_NOREF(uPass);
5493
5494	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5495	int rc;
5496
5497	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5498	{
5499	uint32_t cScreens = 0;
5500	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5501	AssertRCReturn(rc, rc);
5502	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5503	("cScreens=%#x\n", cScreens),
5504	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5505
5506	for (uint32_t i = 0; i < cScreens; ++i)
5507	{
5508	VMSVGASCREENOBJECT screen;
5509	RT_ZERO(screen);
5510
5511	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5512	AssertLogRelRCReturn(rc, rc);
5513
5514	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5515	{
5516	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5517	*pScreen = screen;
5518	pScreen->fModified = true;
5519	}
5520	else
5521	{
5522	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5523	}
5524	}
5525	}
5526	else
5527	{
5528	/* Try to setup at least the first screen. */
5529	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5530	pScreen->fDefined = true;
5531	pScreen->fModified = true;
5532	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5533	pScreen->idScreen = 0;
5534	pScreen->xOrigin = 0;
5535	pScreen->yOrigin = 0;
5536	pScreen->offVRAM = pThis->svga.uScreenOffset;
5537	pScreen->cbPitch = pThis->svga.cbScanline;
5538	pScreen->cWidth = pThis->svga.uWidth;
5539	pScreen->cHeight = pThis->svga.uHeight;
5540	pScreen->cBpp = pThis->svga.uBpp;
5541	}
5542
5543	return VINF_SUCCESS;
5544	}
5545
5546	/**
5547	* @copydoc FNSSMDEVLOADEXEC
5548	*/
5549	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5550	{
5551	RT_NOREF(uPass);
5552	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5553	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5554	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5555	int rc;
5556
5557	/* Load our part of the VGAState */
5558	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5559	AssertRCReturn(rc, rc);
5560
5561	/* Load the VGA framebuffer. */
5562	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5563	uint32_t cbVgaFramebuffer = _32K;
5564	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5565	{
5566	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5567	AssertRCReturn(rc, rc);
5568	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5569	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5570	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5571	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5572	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5573	}
5574	rc = pHlp->pfnSSMGetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5575	AssertRCReturn(rc, rc);
5576	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5577	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5578	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5579	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5580
5581	/* Load the VMSVGA state. */
5582	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5583	AssertRCReturn(rc, rc);
5584
5585	/* Load the active cursor bitmaps. */
5586	if (pSVGAState->Cursor.fActive)
5587	{
5588	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5589	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5590
5591	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5592	AssertRCReturn(rc, rc);
5593	}
5594
5595	/* Load the GMR state. */
5596	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5597	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5598	{
5599	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5600	AssertRCReturn(rc, rc);
5601	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5602	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5603	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5604	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5605	}
5606
5607	if (pThis->svga.cGMR != cGMR)
5608	{
5609	/* Reallocate GMR array. */
5610	Assert(pSVGAState->paGMR != NULL);
5611	RTMemFree(pSVGAState->paGMR);
5612	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5613	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5614	pThis->svga.cGMR = cGMR;
5615	}
5616
5617	for (uint32_t i = 0; i < cGMR; ++i)
5618	{
5619	PGMR pGMR = &pSVGAState->paGMR[i];
5620
5621	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5622	AssertRCReturn(rc, rc);
5623
5624	if (pGMR->numDescriptors)
5625	{
5626	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5627	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5628	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5629
5630	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5631	{
5632	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5633	AssertRCReturn(rc, rc);
5634	}
5635	}
5636	}
5637
5638	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5639	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5640	# endif
5641
5642	VMSVGA_STATE_LOAD LoadState;
5643	LoadState.pSSM = pSSM;
5644	LoadState.uVersion = uVersion;
5645	LoadState.uPass = uPass;
5646	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5647	AssertLogRelRCReturn(rc, rc);
5648
5649	return VINF_SUCCESS;
5650	}
5651
5652	/**
5653	* Reinit the video mode after the state has been loaded.
5654	*/
5655	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5656	{
5657	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5658	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5659	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5660
5661	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5662
5663	/* Set the active cursor. */
5664	if (pSVGAState->Cursor.fActive)
5665	{
5666	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5667	true /fVisible/,
5668	true /fAlpha/,
5669	pSVGAState->Cursor.xHotspot,
5670	pSVGAState->Cursor.yHotspot,
5671	pSVGAState->Cursor.width,
5672	pSVGAState->Cursor.height,
5673	pSVGAState->Cursor.pData);
5674	AssertRC(rc);
5675	}
5676	return VINF_SUCCESS;
5677	}
5678
5679	/**
5680	* Portion of SVGA state which must be saved in the FIFO thread.
5681	*/
5682	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5683	{
5684	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5685	int rc;
5686
5687	/* Save the screen objects. */
5688	/* Count defined screen object. */
5689	uint32_t cScreens = 0;
5690	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5691	{
5692	if (pSVGAState->aScreens[i].fDefined)
5693	++cScreens;
5694	}
5695
5696	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5697	AssertLogRelRCReturn(rc, rc);
5698
5699	for (uint32_t i = 0; i < cScreens; ++i)
5700	{
5701	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5702
5703	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5704	AssertLogRelRCReturn(rc, rc);
5705	}
5706	return VINF_SUCCESS;
5707	}
5708
5709	/**
5710	* @copydoc FNSSMDEVSAVEEXEC
5711	*/
5712	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5713	{
5714	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5715	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5716	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5717	int rc;
5718
5719	/* Save our part of the VGAState */
5720	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5721	AssertLogRelRCReturn(rc, rc);
5722
5723	/* Save the framebuffer backup. */
5724	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5725	rc = pHlp->pfnSSMPutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5726	AssertLogRelRCReturn(rc, rc);
5727
5728	/* Save the VMSVGA state. */
5729	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5730	AssertLogRelRCReturn(rc, rc);
5731
5732	/* Save the active cursor bitmaps. */
5733	if (pSVGAState->Cursor.fActive)
5734	{
5735	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5736	AssertLogRelRCReturn(rc, rc);
5737	}
5738
5739	/* Save the GMR state */
5740	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5741	AssertLogRelRCReturn(rc, rc);
5742	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5743	{
5744	PGMR pGMR = &pSVGAState->paGMR[i];
5745
5746	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5747	AssertLogRelRCReturn(rc, rc);
5748
5749	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5750	{
5751	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5752	AssertLogRelRCReturn(rc, rc);
5753	}
5754	}
5755
5756	/*
5757	* Must save some state (3D in particular) in the FIFO thread.
5758	*/
5759	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5760	AssertLogRelRCReturn(rc, rc);
5761
5762	return VINF_SUCCESS;
5763	}
5764
5765	/**
5766	* Destructor for PVMSVGAR3STATE structure.
5767	*
5768	* @param pThis The VGA instance.
5769	* @param pSVGAState Pointer to the structure. It is not deallocated.
5770	*/
5771	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5772	{
5773	# ifndef VMSVGA_USE_EMT_HALT_CODE
5774	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5775	{
5776	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5777	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5778	}
5779	# endif
5780
5781	if (pSVGAState->Cursor.fActive)
5782	{
5783	RTMemFree(pSVGAState->Cursor.pData);
5784	pSVGAState->Cursor.pData = NULL;
5785	pSVGAState->Cursor.fActive = false;
5786	}
5787
5788	if (pSVGAState->paGMR)
5789	{
5790	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5791	if (pSVGAState->paGMR[i].paDesc)
5792	RTMemFree(pSVGAState->paGMR[i].paDesc);
5793
5794	RTMemFree(pSVGAState->paGMR);
5795	pSVGAState->paGMR = NULL;
5796	}
5797	}
5798
5799	/**
5800	* Constructor for PVMSVGAR3STATE structure.
5801	*
5802	* @returns VBox status code.
5803	* @param pThis The VGA instance.
5804	* @param pSVGAState Pointer to the structure. It is already allocated.
5805	*/
5806	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5807	{
5808	int rc = VINF_SUCCESS;
5809	RT_ZERO(*pSVGAState);
5810
5811	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5812	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5813
5814	# ifndef VMSVGA_USE_EMT_HALT_CODE
5815	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5816	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5817	AssertRCReturn(rc, rc);
5818	# endif
5819
5820	return rc;
5821	}
5822
5823	/**
5824	* Initializes the host capabilities: registers and FIFO.
5825	*
5826	* @returns VBox status code.
5827	* @param pThis The VGA instance.
5828	*/
5829	static void vmsvgaR3InitCaps(PVGASTATE pThis)
5830	{
5831	/* Register caps. */
5832	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5833	\| SVGA_CAP_GMR2
5834	\| SVGA_CAP_CURSOR
5835	\| SVGA_CAP_CURSOR_BYPASS_2
5836	\| SVGA_CAP_EXTENDED_FIFO
5837	\| SVGA_CAP_IRQMASK
5838	\| SVGA_CAP_PITCHLOCK
5839	\| SVGA_CAP_TRACES
5840	\| SVGA_CAP_SCREEN_OBJECT_2
5841	\| SVGA_CAP_ALPHA_CURSOR;
5842	# ifdef VBOX_WITH_VMSVGA3D
5843	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5844	# endif
5845
5846	/* Clear the FIFO. */
5847	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5848
5849	/* Setup FIFO capabilities. */
5850	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5851	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5852	\| SVGA_FIFO_CAP_GMR2
5853	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5854	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5855	\| SVGA_FIFO_CAP_RESERVE
5856	\| SVGA_FIFO_CAP_PITCHLOCK;
5857
5858	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5859	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5860	}
5861
5862	# ifdef VBOX_WITH_VMSVGA3D
5863	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5864	static const char * const g_apszVmSvgaDevCapNames[] =
5865	{
5866	"x3D", /* = 0 */
5867	"xMAX_LIGHTS",
5868	"xMAX_TEXTURES",
5869	"xMAX_CLIP_PLANES",
5870	"xVERTEX_SHADER_VERSION",
5871	"xVERTEX_SHADER",
5872	"xFRAGMENT_SHADER_VERSION",
5873	"xFRAGMENT_SHADER",
5874	"xMAX_RENDER_TARGETS",
5875	"xS23E8_TEXTURES",
5876	"xS10E5_TEXTURES",
5877	"xMAX_FIXED_VERTEXBLEND",
5878	"xD16_BUFFER_FORMAT",
5879	"xD24S8_BUFFER_FORMAT",
5880	"xD24X8_BUFFER_FORMAT",
5881	"xQUERY_TYPES",
5882	"xTEXTURE_GRADIENT_SAMPLING",
5883	"rMAX_POINT_SIZE",
5884	"xMAX_SHADER_TEXTURES",
5885	"xMAX_TEXTURE_WIDTH",
5886	"xMAX_TEXTURE_HEIGHT",
5887	"xMAX_VOLUME_EXTENT",
5888	"xMAX_TEXTURE_REPEAT",
5889	"xMAX_TEXTURE_ASPECT_RATIO",
5890	"xMAX_TEXTURE_ANISOTROPY",
5891	"xMAX_PRIMITIVE_COUNT",
5892	"xMAX_VERTEX_INDEX",
5893	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5894	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5895	"xMAX_VERTEX_SHADER_TEMPS",
5896	"xMAX_FRAGMENT_SHADER_TEMPS",
5897	"xTEXTURE_OPS",
5898	"xSURFACEFMT_X8R8G8B8",
5899	"xSURFACEFMT_A8R8G8B8",
5900	"xSURFACEFMT_A2R10G10B10",
5901	"xSURFACEFMT_X1R5G5B5",
5902	"xSURFACEFMT_A1R5G5B5",
5903	"xSURFACEFMT_A4R4G4B4",
5904	"xSURFACEFMT_R5G6B5",
5905	"xSURFACEFMT_LUMINANCE16",
5906	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5907	"xSURFACEFMT_ALPHA8",
5908	"xSURFACEFMT_LUMINANCE8",
5909	"xSURFACEFMT_Z_D16",
5910	"xSURFACEFMT_Z_D24S8",
5911	"xSURFACEFMT_Z_D24X8",
5912	"xSURFACEFMT_DXT1",
5913	"xSURFACEFMT_DXT2",
5914	"xSURFACEFMT_DXT3",
5915	"xSURFACEFMT_DXT4",
5916	"xSURFACEFMT_DXT5",
5917	"xSURFACEFMT_BUMPX8L8V8U8",
5918	"xSURFACEFMT_A2W10V10U10",
5919	"xSURFACEFMT_BUMPU8V8",
5920	"xSURFACEFMT_Q8W8V8U8",
5921	"xSURFACEFMT_CxV8U8",
5922	"xSURFACEFMT_R_S10E5",
5923	"xSURFACEFMT_R_S23E8",
5924	"xSURFACEFMT_RG_S10E5",
5925	"xSURFACEFMT_RG_S23E8",
5926	"xSURFACEFMT_ARGB_S10E5",
5927	"xSURFACEFMT_ARGB_S23E8",
5928	"xMISSING62",
5929	"xMAX_VERTEX_SHADER_TEXTURES",
5930	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5931	"xSURFACEFMT_V16U16",
5932	"xSURFACEFMT_G16R16",
5933	"xSURFACEFMT_A16B16G16R16",
5934	"xSURFACEFMT_UYVY",
5935	"xSURFACEFMT_YUY2",
5936	"xMULTISAMPLE_NONMASKABLESAMPLES",
5937	"xMULTISAMPLE_MASKABLESAMPLES",
5938	"xALPHATOCOVERAGE",
5939	"xSUPERSAMPLE",
5940	"xAUTOGENMIPMAPS",
5941	"xSURFACEFMT_NV12",
5942	"xSURFACEFMT_AYUV",
5943	"xMAX_CONTEXT_IDS",
5944	"xMAX_SURFACE_IDS",
5945	"xSURFACEFMT_Z_DF16",
5946	"xSURFACEFMT_Z_DF24",
5947	"xSURFACEFMT_Z_D24S8_INT",
5948	"xSURFACEFMT_BC4_UNORM",
5949	"xSURFACEFMT_BC5_UNORM", /* 83 */
5950	};
5951
5952	/**
5953	* Initializes the host 3D capabilities in FIFO.
5954	*
5955	* @returns VBox status code.
5956	* @param pThis The VGA instance.
5957	*/
5958	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis)
5959	{
5960	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5961	bool fSavedBuffering = RTLogRelSetBuffering(true);
5962	SVGA3dCapsRecord *pCaps;
5963	SVGA3dCapPair *pData;
5964	uint32_t idxCap = 0;
5965
5966	/* 3d hardware version; latest and greatest */
5967	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5968	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5969
5970	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5971	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5972	pData = (SVGA3dCapPair *)&pCaps->data;
5973
5974	/* Fill out all 3d capabilities. */
5975	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5976	{
5977	uint32_t val = 0;
5978
5979	int rc = vmsvga3dQueryCaps(pThis, i, &val);
5980	if (RT_SUCCESS(rc))
5981	{
5982	pData[idxCap][0] = i;
5983	pData[idxCap][1] = val;
5984	idxCap++;
5985	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5986	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5987	else
5988	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5989	&g_apszVmSvgaDevCapNames[i][1]));
5990	}
5991	else
5992	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5993	}
5994	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5995	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5996
5997	/* Mark end of record array. */
5998	pCaps->header.length = 0;
5999
6000	RTLogRelSetBuffering(fSavedBuffering);
6001	}
6002
6003	# endif
6004
6005	/**
6006	* Resets the SVGA hardware state
6007	*
6008	* @returns VBox status code.
6009	* @param pDevIns The device instance.
6010	*/
6011	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6012	{
6013	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6014	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
6015
6016	/* Reset before init? */
6017	if (!pSVGAState)
6018	return VINF_SUCCESS;
6019
6020	Log(("vmsvgaR3Reset\n"));
6021
6022	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6023	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6024	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6025
6026	/* Reset other stuff. */
6027	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6028	RT_ZERO(pThis->svga.au32ScratchRegion);
6029
6030	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6031	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6032
6033	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6034
6035	/* Initialize FIFO and register capabilities. */
6036	vmsvgaR3InitCaps(pThis);
6037
6038	# ifdef VBOX_WITH_VMSVGA3D
6039	if (pThis->svga.f3DEnabled)
6040	vmsvgaR3InitFifo3DCaps(pThis);
6041	# endif
6042
6043	/* VRAM tracking is enabled by default during bootup. */
6044	pThis->svga.fVRAMTracking = true;
6045	pThis->svga.fEnabled = false;
6046
6047	/* Invalidate current settings. */
6048	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6049	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6050	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6051	pThis->svga.cbScanline = 0;
6052	pThis->svga.u32PitchLock = 0;
6053
6054	return rc;
6055	}
6056
6057	/**
6058	* Cleans up the SVGA hardware state
6059	*
6060	* @returns VBox status code.
6061	* @param pDevIns The device instance.
6062	*/
6063	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6064	{
6065	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6066
6067	/*
6068	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6069	*/
6070	if (pThis->svga.pFIFOIOThread)
6071	{
6072	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6073	AssertLogRelRC(rc);
6074
6075	rc = PDMDevHlpThreadDestroy(pDevIns, pThis->svga.pFIFOIOThread, NULL);
6076	AssertLogRelRC(rc);
6077	pThis->svga.pFIFOIOThread = NULL;
6078	}
6079
6080	/*
6081	* Destroy the special SVGA state.
6082	*/
6083	if (pThis->svga.pSvgaR3State)
6084	{
6085	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6086
6087	RTMemFree(pThis->svga.pSvgaR3State);
6088	pThis->svga.pSvgaR3State = NULL;
6089	}
6090
6091	/*
6092	* Free our resources residing in the VGA state.
6093	*/
6094	if (pThis->svga.pbVgaFrameBufferR3)
6095	{
6096	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6097	pThis->svga.pbVgaFrameBufferR3 = NULL;
6098	}
6099	if (pThis->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6100	{
6101	RTSemEventDestroy(pThis->svga.hFIFOExtCmdSem);
6102	pThis->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6103	}
6104	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6105	{
6106	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6107	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6108	}
6109
6110	return VINF_SUCCESS;
6111	}
6112
6113	/**
6114	* Initialize the SVGA hardware state
6115	*
6116	* @returns VBox status code.
6117	* @param pDevIns The device instance.
6118	*/
6119	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6120	{
6121	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6122	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6123	PVMSVGAR3STATE pSVGAState;
6124	int rc;
6125
6126	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6127	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6128
6129	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6130
6131	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6132	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6133	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6134
6135	/* Create event semaphore. */
6136	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6137	AssertRCReturn(rc, rc);
6138
6139	/* Create event semaphore. */
6140	rc = RTSemEventCreate(&pThis->svga.hFIFOExtCmdSem);
6141	AssertRCReturn(rc, rc);
6142
6143	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6144	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6145
6146	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6147	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6148
6149	pSVGAState = pThis->svga.pSvgaR3State;
6150
6151	/* Initialize FIFO and register capabilities. */
6152	vmsvgaR3InitCaps(pThis);
6153
6154	# ifdef VBOX_WITH_VMSVGA3D
6155	if (pThis->svga.f3DEnabled)
6156	{
6157	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6158	if (RT_FAILURE(rc))
6159	{
6160	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6161	pThis->svga.f3DEnabled = false;
6162	}
6163	}
6164	# endif
6165	/* VRAM tracking is enabled by default during bootup. */
6166	pThis->svga.fVRAMTracking = true;
6167
6168	/* Invalidate current settings. */
6169	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6170	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6171	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6172	pThis->svga.cbScanline = 0;
6173
6174	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6175	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6176	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6177	{
6178	pThis->svga.u32MaxWidth -= 256;
6179	pThis->svga.u32MaxHeight -= 256;
6180	}
6181	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6182
6183	# ifdef DEBUG_GMR_ACCESS
6184	/* Register the GMR access handler type. */
6185	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6186	vmsvgaR3GmrAccessHandler,
6187	NULL, NULL, NULL,
6188	NULL, NULL, NULL,
6189	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6190	AssertRCReturn(rc, rc);
6191	# endif
6192
6193	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6194	/* Register the FIFO access handler type. In addition to
6195	debugging FIFO access, this is also used to facilitate
6196	extended fifo thread sleeps. */
6197	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6198	# ifdef DEBUG_FIFO_ACCESS
6199	PGMPHYSHANDLERKIND_ALL,
6200	# else
6201	PGMPHYSHANDLERKIND_WRITE,
6202	# endif
6203	vmsvgaR3FifoAccessHandler,
6204	NULL, NULL, NULL,
6205	NULL, NULL, NULL,
6206	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6207	AssertRCReturn(rc, rc);
6208	# endif
6209
6210	/* Create the async IO thread. */
6211	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6212	RTTHREADTYPE_IO, "VMSVGA FIFO");
6213	if (RT_FAILURE(rc))
6214	{
6215	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6216	return rc;
6217	}
6218
6219	/*
6220	* Statistics.
6221	*/
6222	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6223	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6224	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6225	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6226	# ifdef VBOX_WITH_STATISTICS
6227	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6228	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6229	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6230	# endif
6231	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6232	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6233	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6234	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6235	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6236	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6237	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6238	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6239	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6240	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6241	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6242	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6243	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6244	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6245	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6246	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6247	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6248	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6249	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6250	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6251	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6252	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6253	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6254	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6255	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6256	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6257	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6258	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6259	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6260	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6261	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6262	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6263	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6264	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6265	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6266	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6267	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6268	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6269	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6270	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6271	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6272	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6273	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6274	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6275	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6276	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6277	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6278	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6279	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6280	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6281	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6282	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6283	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6284
6285	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6286	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6287	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6288	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6289	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6290	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6291	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6292	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6293	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6294	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6295	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6296	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6297	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6298	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6299	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6300	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6301	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6302	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6303	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6304	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6305	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6306	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6307	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6308	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6309	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6310	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6311	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6312	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6313	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6314	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6315	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6316	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6317
6318	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6319	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6320	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6321	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6322	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6323	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6324	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6325	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6326	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6327	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6328	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6329	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6330	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6331	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6332	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6333	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6334	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6335	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6336	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6337	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6338	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6339	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6340	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6341	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6342	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6343	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6344	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6345	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6346	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6347	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6348	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6349	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6350	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6351	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6352	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6353	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6354	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6355	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6356	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6357	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6358	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6359	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6360	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6361	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6362	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6363	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6364	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6365	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6366	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6367
6368	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6369	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6370	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6371	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6372	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6373	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6374	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6375	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6376	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6377	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6378	# endif
6379	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6380	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6381	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6382	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6383	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6384
6385	# undef REG_CNT
6386	# undef REG_PRF
6387
6388	/*
6389	* Info handlers.
6390	*/
6391	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6392	# ifdef VBOX_WITH_VMSVGA3D
6393	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6394	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6395	"VMSVGA 3d surface details. "
6396	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6397	vmsvgaR3Info3dSurface);
6398	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6399	"VMSVGA 3d surface details and bitmap: "
6400	"sid[>dir]",
6401	vmsvgaR3Info3dSurfaceBmp);
6402	# endif
6403
6404	return VINF_SUCCESS;
6405	}
6406
6407	/**
6408	* Power On notification.
6409	*
6410	* @returns VBox status code.
6411	* @param pDevIns The device instance data.
6412	*
6413	* @remarks Caller enters the device critical section.
6414	*/
6415	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6416	{
6417	# ifdef VBOX_WITH_VMSVGA3D
6418	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6419	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6420	if (pThis->svga.f3DEnabled)
6421	{
6422	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6423
6424	if (RT_SUCCESS(rc))
6425	{
6426	/* Initialize FIFO 3D capabilities. */
6427	vmsvgaR3InitFifo3DCaps(pThis);
6428	}
6429	}
6430	# else /* !VBOX_WITH_VMSVGA3D */
6431	RT_NOREF(pDevIns);
6432	# endif /* !VBOX_WITH_VMSVGA3D */
6433	}
6434
6435	#endif /* IN_RING3 */
6436

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82110

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