DevVGA-SVGA.cpp@ 82089

最後變更在這個檔案從82089是 82089,由 vboxsync 提交於 5 年前
DevVGA: Mark functions with R3 where appropriate, adding docs and doing other minor cleaning up. bugref:9218
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1	/* $Id: DevVGA-SVGA.cpp 82089 2019-11-21 22:18:59Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.alldomusa.eu.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFOExtCmdSem),
524	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
527	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
528	SSMFIELD_ENTRY( VMSVGAState, uWidth),
529	SSMFIELD_ENTRY( VMSVGAState, uHeight),
530	SSMFIELD_ENTRY( VMSVGAState, uBpp),
531	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
532	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
533	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
535	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
536	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
537	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
538	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
541	SSMFIELD_ENTRY_TERM()
542	};
543	#endif /* IN_RING3 */
544
545
546	/*********************************************************************************************************************************
547	* Internal Functions *
548	*********************************************************************************************************************************/
549	#ifdef IN_RING3
550	static void vmsvgaR3SetTraces(PVGASTATE pThis, bool fTraces);
551	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
552	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM);
553	#endif /* IN_RING3 */
554
555
556
557	#ifdef IN_RING3
558	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATE pThis, uint32_t idScreen)
559	{
560	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
561	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
562	&& pSVGAState
563	&& pSVGAState->aScreens[idScreen].fDefined)
564	{
565	return &pSVGAState->aScreens[idScreen];
566	}
567	return NULL;
568	}
569	#endif /* IN_RING3 */
570
571	#ifdef LOG_ENABLED
572
573	/**
574	* Index register string name lookup
575	*
576	* @returns Index register string or "UNKNOWN"
577	* @param pThis VMSVGA State
578	* @param idxReg The index register.
579	*/
580	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
581	{
582	switch (idxReg)
583	{
584	case SVGA_REG_ID: return "SVGA_REG_ID";
585	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
586	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
587	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
588	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
589	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
590	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
591	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
592	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
593	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
594	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
595	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
596	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
597	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
598	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
599	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
600	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
601	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
602	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
603	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
604	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
605	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
606	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
607	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
608	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
609	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
610	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
611	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
612	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
613	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
614	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
615	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
616	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
617	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
618	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
619	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
620	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
621	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
622	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
623	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
624	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
625	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
626	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
627	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
628	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
629	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
630	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
631	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
632	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
633	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
634
635	default:
636	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
637	return "SVGA_SCRATCH_BASE reg";
638	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
639	return "SVGA_PALETTE_BASE reg";
640	return "UNKNOWN";
641	}
642	}
643
644	#ifdef IN_RING3
645	/**
646	* FIFO command name lookup
647	*
648	* @returns FIFO command string or "UNKNOWN"
649	* @param u32Cmd FIFO command
650	*/
651	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
652	{
653	switch (u32Cmd)
654	{
655	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
656	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
657	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
658	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
659	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
660	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
661	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
662	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
663	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
664	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
665	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
666	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
667	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
668	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
669	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
670	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
671	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
672	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
673	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
674	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
675	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
676	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
677	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
678	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
679	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
680	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
681	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
682	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
683	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
684	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
685	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
686	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
687	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
688	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
689	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
690	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
691	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
692	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
693	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
694	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
695	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
696	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
697	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
698	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
699	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
700	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
701	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
702	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
703	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
704	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
705	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
706	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
707	default: return "UNKNOWN";
708	}
709	}
710	# endif /* IN_RING3 */
711
712	#endif /* LOG_ENABLED */
713
714	#ifdef IN_RING3
715	/**
716	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
717	*/
718	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
719	{
720	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
721
722	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
723	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
724
725	/** @todo Test how it interacts with multiple screen objects. */
726	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, idScreen);
727	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
728	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
729
730	if (x < uWidth)
731	{
732	pThis->svga.viewport.x = x;
733	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
734	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
735	}
736	else
737	{
738	pThis->svga.viewport.x = uWidth;
739	pThis->svga.viewport.cx = 0;
740	pThis->svga.viewport.xRight = uWidth;
741	}
742	if (y < uHeight)
743	{
744	pThis->svga.viewport.y = y;
745	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
746	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
747	pThis->svga.viewport.yHighWC = uHeight - y;
748	}
749	else
750	{
751	pThis->svga.viewport.y = uHeight;
752	pThis->svga.viewport.cy = 0;
753	pThis->svga.viewport.yLowWC = 0;
754	pThis->svga.viewport.yHighWC = 0;
755	}
756
757	# ifdef VBOX_WITH_VMSVGA3D
758	/*
759	* Now inform the 3D backend.
760	*/
761	if (pThis->svga.f3DEnabled)
762	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
763	# else
764	RT_NOREF(OldViewport);
765	# endif
766	}
767	#endif /* IN_RING3 */
768
769	/**
770	* Read port register
771	*
772	* @returns VBox status code.
773	* @param pDevIns The device instance.
774	* @param pThis VMSVGA State
775	* @param pu32 Where to store the read value
776	*/
777	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
778	{
779	int rc = VINF_SUCCESS;
780	*pu32 = 0;
781
782	/* Rough index register validation. */
783	uint32_t idxReg = pThis->svga.u32IndexReg;
784	#if !defined(IN_RING3) && defined(VBOX_STRICT)
785	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
786	VINF_IOM_R3_IOPORT_READ);
787	#else
788	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
789	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
790	VINF_SUCCESS);
791	#endif
792	RT_UNTRUSTED_VALIDATED_FENCE();
793
794	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
795	if ( idxReg >= SVGA_REG_CAPABILITIES
796	&& pThis->svga.u32SVGAId == SVGA_ID_0)
797	{
798	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
799	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
800	}
801
802	switch (idxReg)
803	{
804	case SVGA_REG_ID:
805	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
806	*pu32 = pThis->svga.u32SVGAId;
807	break;
808
809	case SVGA_REG_ENABLE:
810	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
811	*pu32 = pThis->svga.fEnabled;
812	break;
813
814	case SVGA_REG_WIDTH:
815	{
816	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
817	if ( pThis->svga.fEnabled
818	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
819	*pu32 = pThis->svga.uWidth;
820	else
821	{
822	#ifndef IN_RING3
823	rc = VINF_IOM_R3_IOPORT_READ;
824	#else
825	*pu32 = pThis->pDrv->cx;
826	#endif
827	}
828	break;
829	}
830
831	case SVGA_REG_HEIGHT:
832	{
833	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
834	if ( pThis->svga.fEnabled
835	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
836	*pu32 = pThis->svga.uHeight;
837	else
838	{
839	#ifndef IN_RING3
840	rc = VINF_IOM_R3_IOPORT_READ;
841	#else
842	*pu32 = pThis->pDrv->cy;
843	#endif
844	}
845	break;
846	}
847
848	case SVGA_REG_MAX_WIDTH:
849	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
850	*pu32 = pThis->svga.u32MaxWidth;
851	break;
852
853	case SVGA_REG_MAX_HEIGHT:
854	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
855	*pu32 = pThis->svga.u32MaxHeight;
856	break;
857
858	case SVGA_REG_DEPTH:
859	/* This returns the color depth of the current mode. */
860	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
861	switch (pThis->svga.uBpp)
862	{
863	case 15:
864	case 16:
865	case 24:
866	*pu32 = pThis->svga.uBpp;
867	break;
868
869	default:
870	case 32:
871	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
872	break;
873	}
874	break;
875
876	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
877	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
878	if ( pThis->svga.fEnabled
879	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
880	*pu32 = pThis->svga.uBpp;
881	else
882	{
883	#ifndef IN_RING3
884	rc = VINF_IOM_R3_IOPORT_READ;
885	#else
886	*pu32 = pThis->pDrv->cBits;
887	#endif
888	}
889	break;
890
891	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
892	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
893	if ( pThis->svga.fEnabled
894	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
895	*pu32 = (pThis->svga.uBpp + 7) & ~7;
896	else
897	{
898	#ifndef IN_RING3
899	rc = VINF_IOM_R3_IOPORT_READ;
900	#else
901	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
902	#endif
903	}
904	break;
905
906	case SVGA_REG_PSEUDOCOLOR:
907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
908	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
909	break;
910
911	case SVGA_REG_RED_MASK:
912	case SVGA_REG_GREEN_MASK:
913	case SVGA_REG_BLUE_MASK:
914	{
915	uint32_t uBpp;
916
917	if ( pThis->svga.fEnabled
918	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
919	{
920	uBpp = pThis->svga.uBpp;
921	}
922	else
923	{
924	#ifndef IN_RING3
925	rc = VINF_IOM_R3_IOPORT_READ;
926	break;
927	#else
928	uBpp = pThis->pDrv->cBits;
929	#endif
930	}
931	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
932	switch (uBpp)
933	{
934	case 8:
935	u32RedMask = 0x07;
936	u32GreenMask = 0x38;
937	u32BlueMask = 0xc0;
938	break;
939
940	case 15:
941	u32RedMask = 0x0000001f;
942	u32GreenMask = 0x000003e0;
943	u32BlueMask = 0x00007c00;
944	break;
945
946	case 16:
947	u32RedMask = 0x0000001f;
948	u32GreenMask = 0x000007e0;
949	u32BlueMask = 0x0000f800;
950	break;
951
952	case 24:
953	case 32:
954	default:
955	u32RedMask = 0x00ff0000;
956	u32GreenMask = 0x0000ff00;
957	u32BlueMask = 0x000000ff;
958	break;
959	}
960	switch (idxReg)
961	{
962	case SVGA_REG_RED_MASK:
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
964	*pu32 = u32RedMask;
965	break;
966
967	case SVGA_REG_GREEN_MASK:
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
969	*pu32 = u32GreenMask;
970	break;
971
972	case SVGA_REG_BLUE_MASK:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
974	*pu32 = u32BlueMask;
975	break;
976	}
977	break;
978	}
979
980	case SVGA_REG_BYTES_PER_LINE:
981	{
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
983	if ( pThis->svga.fEnabled
984	&& pThis->svga.cbScanline)
985	*pu32 = pThis->svga.cbScanline;
986	else
987	{
988	#ifndef IN_RING3
989	rc = VINF_IOM_R3_IOPORT_READ;
990	#else
991	*pu32 = pThis->pDrv->cbScanline;
992	#endif
993	}
994	break;
995	}
996
997	case SVGA_REG_VRAM_SIZE: /* VRAM size */
998	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
999	*pu32 = pThis->vram_size;
1000	break;
1001
1002	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1003	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1004	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1005	*pu32 = pThis->GCPhysVRAM;
1006	break;
1007
1008	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1010	/* Always zero in our case. */
1011	*pu32 = 0;
1012	break;
1013
1014	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1015	{
1016	#ifndef IN_RING3
1017	rc = VINF_IOM_R3_IOPORT_READ;
1018	#else
1019	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1020
1021	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1022	if ( pThis->svga.fEnabled
1023	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1024	{
1025	/* Hardware enabled; return real framebuffer size .*/
1026	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1027	}
1028	else
1029	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1030
1031	pu32 = RT_MIN(pThis->vram_size, pu32);
1032	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1033	#endif
1034	break;
1035	}
1036
1037	case SVGA_REG_CAPABILITIES:
1038	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1039	*pu32 = pThis->svga.u32RegCaps;
1040	break;
1041
1042	case SVGA_REG_MEM_START: /* FIFO start */
1043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1044	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1045	*pu32 = pThis->svga.GCPhysFIFO;
1046	break;
1047
1048	case SVGA_REG_MEM_SIZE: /* FIFO size */
1049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1050	*pu32 = pThis->svga.cbFIFO;
1051	break;
1052
1053	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1054	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1055	*pu32 = pThis->svga.fConfigured;
1056	break;
1057
1058	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1060	*pu32 = 0;
1061	break;
1062
1063	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1065	if (pThis->svga.fBusy)
1066	{
1067	#ifndef IN_RING3
1068	/* Go to ring-3 and halt the CPU. */
1069	rc = VINF_IOM_R3_IOPORT_READ;
1070	RT_NOREF(pDevIns);
1071	break;
1072	#else
1073	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1074	/* The guest is basically doing a HLT via the device here, but with
1075	a special wake up condition on FIFO completion. */
1076	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1077	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1078	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1079	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1080	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1081	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1085	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1086	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1087	}
1088	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1089	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1090	# else
1091
1092	/* Delay the EMT a bit so the FIFO and others can get some work done.
1093	This used to be a crude 50 ms sleep. The current code tries to be
1094	more efficient, but the consept is still very crude. */
1095	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1096	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	RTThreadYield();
1098	if (pThis->svga.fBusy)
1099	{
1100	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1101
1102	if (pThis->svga.fBusy && cRefs == 1)
1103	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1104	if (pThis->svga.fBusy)
1105	{
1106	/** @todo If this code is going to stay, we need to call into the halt/wait
1107	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1108	* suffer when the guest is polling on a busy FIFO. */
1109	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1110	if (cNsMaxWait >= RT_NS_100US)
1111	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1112	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1113	RT_MIN(cNsMaxWait, RT_NS_10MS));
1114	}
1115
1116	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1117	}
1118	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1119	# endif
1120	*pu32 = pThis->svga.fBusy != 0;
1121	#endif
1122	}
1123	else
1124	*pu32 = false;
1125	break;
1126
1127	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1129	*pu32 = pThis->svga.u32GuestId;
1130	break;
1131
1132	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1134	*pu32 = pThis->svga.cScratchRegion;
1135	break;
1136
1137	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1139	*pu32 = SVGA_FIFO_NUM_REGS;
1140	break;
1141
1142	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1144	*pu32 = pThis->svga.u32PitchLock;
1145	break;
1146
1147	case SVGA_REG_IRQMASK: /* Interrupt mask */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1149	*pu32 = pThis->svga.u32IrqMask;
1150	break;
1151
1152	/* See "Guest memory regions" below. */
1153	case SVGA_REG_GMR_ID:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1155	*pu32 = pThis->svga.u32CurrentGMRId;
1156	break;
1157
1158	case SVGA_REG_GMR_DESCRIPTOR:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1160	/* Write only */
1161	*pu32 = 0;
1162	break;
1163
1164	case SVGA_REG_GMR_MAX_IDS:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1166	*pu32 = pThis->svga.cGMR;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1171	*pu32 = VMSVGA_MAX_GMR_PAGES;
1172	break;
1173
1174	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1176	*pu32 = pThis->svga.fTraces;
1177	break;
1178
1179	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1181	*pu32 = VMSVGA_MAX_GMR_PAGES;
1182	break;
1183
1184	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1186	*pu32 = VMSVGA_SURFACE_SIZE;
1187	break;
1188
1189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1191	break;
1192
1193	/* Mouse cursor support. */
1194	case SVGA_REG_CURSOR_ID:
1195	case SVGA_REG_CURSOR_X:
1196	case SVGA_REG_CURSOR_Y:
1197	case SVGA_REG_CURSOR_ON:
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1199	break;
1200
1201	/* Legacy multi-monitor support */
1202	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1204	*pu32 = 1;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1209	*pu32 = 0;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1229	*pu32 = pThis->svga.uWidth;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1234	*pu32 = pThis->svga.uHeight;
1235	break;
1236
1237	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1239	/* We must return something sensible here otherwise the Linux driver
1240	will take a legacy code path without 3d support. This number also
1241	limits how many screens Linux guests will allow. */
1242	*pu32 = pThis->cMonitors;
1243	break;
1244
1245	default:
1246	{
1247	uint32_t offReg;
1248	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1249	{
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1253	}
1254	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1255	{
1256	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1258	RT_UNTRUSTED_VALIDATED_FENCE();
1259	uint32_t u32 = pThis->last_palette[offReg / 3];
1260	switch (offReg % 3)
1261	{
1262	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1263	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1264	case 2: pu32 = u32 & 0xff; break; / blue */
1265	}
1266	}
1267	else
1268	{
1269	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1270	rc = VINF_IOM_R3_IOPORT_READ;
1271	#else
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1273
1274	/* Do not assert. The guest might be reading all registers. */
1275	LogFunc(("Unknown reg=%#x\n", idxReg));
1276	#endif
1277	}
1278	break;
1279	}
1280	}
1281	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1282	return rc;
1283	}
1284
1285	#ifdef IN_RING3
1286	/**
1287	* Apply the current resolution settings to change the video mode.
1288	*
1289	* @returns VBox status code.
1290	* @param pThis VMSVGA State
1291	*/
1292	static int vmsvgaR3ChangeMode(PVGASTATE pThis)
1293	{
1294	int rc;
1295
1296	/* Always do changemode on FIFO thread. */
1297	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1298
1299	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1300
1301	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1302
1303	if (pThis->svga.fGFBRegisters)
1304	{
1305	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1306	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1307	* deletes all screens other than screen #0, and redefines screen
1308	* #0 according to the specified mode. Drivers that use
1309	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1310	*/
1311
1312	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1313	pScreen->fDefined = true;
1314	pScreen->fModified = true;
1315	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1316	pScreen->idScreen = 0;
1317	pScreen->xOrigin = 0;
1318	pScreen->yOrigin = 0;
1319	pScreen->offVRAM = 0;
1320	pScreen->cbPitch = pThis->svga.cbScanline;
1321	pScreen->cWidth = pThis->svga.uWidth;
1322	pScreen->cHeight = pThis->svga.uHeight;
1323	pScreen->cBpp = pThis->svga.uBpp;
1324
1325	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	/* Delete screen. */
1328	pScreen = &pSVGAState->aScreens[iScreen];
1329	if (pScreen->fDefined)
1330	{
1331	pScreen->fModified = true;
1332	pScreen->fDefined = false;
1333	}
1334	}
1335	}
1336	else
1337	{
1338	/* "If Screen Objects are supported, they can be used to fully
1339	* replace the functionality provided by the framebuffer registers
1340	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1341	*/
1342	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1343	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1345	}
1346
1347	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1348	{
1349	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1350	if (!pScreen->fModified)
1351	continue;
1352
1353	pScreen->fModified = false;
1354
1355	VBVAINFOVIEW view;
1356	RT_ZERO(view);
1357	view.u32ViewIndex = pScreen->idScreen;
1358	// view.u32ViewOffset = 0;
1359	view.u32ViewSize = pThis->vram_size;
1360	view.u32MaxScreenSize = pThis->vram_size;
1361
1362	VBVAINFOSCREEN screen;
1363	RT_ZERO(screen);
1364	screen.u32ViewIndex = pScreen->idScreen;
1365
1366	if (pScreen->fDefined)
1367	{
1368	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1369	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1371	{
1372	Assert(pThis->svga.fGFBRegisters);
1373	continue;
1374	}
1375
1376	screen.i32OriginX = pScreen->xOrigin;
1377	screen.i32OriginY = pScreen->yOrigin;
1378	screen.u32StartOffset = pScreen->offVRAM;
1379	screen.u32LineSize = pScreen->cbPitch;
1380	screen.u32Width = pScreen->cWidth;
1381	screen.u32Height = pScreen->cHeight;
1382	screen.u16BitsPerPixel = pScreen->cBpp;
1383	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1384	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1385	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1386	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1387	}
1388	else
1389	{
1390	/* Screen is destroyed. */
1391	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1392	}
1393
1394	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1395	AssertRC(rc);
1396	}
1397
1398	/* Last stuff. For the VGA device screenshot. */
1399	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1400	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1401	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1402	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1404
1405	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1406	if ( pThis->svga.viewport.cx == 0
1407	&& pThis->svga.viewport.cy == 0)
1408	{
1409	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1410	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1412	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yLowWC = 0;
1414	}
1415
1416	return VINF_SUCCESS;
1417	}
1418
1419	int vmsvgaR3UpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1420	{
1421	VBVACMDHDR cmd;
1422	cmd.x = (int16_t)(pScreen->xOrigin + x);
1423	cmd.y = (int16_t)(pScreen->yOrigin + y);
1424	cmd.w = (uint16_t)w;
1425	cmd.h = (uint16_t)h;
1426
1427	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1428	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1429	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1430	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1431
1432	return VINF_SUCCESS;
1433	}
1434
1435	#endif /* IN_RING3 */
1436	#if defined(IN_RING0) \|\| defined(IN_RING3)
1437
1438	/**
1439	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1440	*
1441	* @param pThis The VMSVGA state.
1442	* @param fState The busy state.
1443	*/
1444	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1445	{
1446	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1447
1448	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1449	{
1450	/* Race / unfortunately scheduling. Highly unlikly. */
1451	uint32_t cLoops = 64;
1452	do
1453	{
1454	ASMNopPause();
1455	fState = (pThis->svga.fBusy != 0);
1456	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1457	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1458	}
1459	}
1460
1461
1462	/**
1463	* Update the scanline pitch in response to the guest changing mode
1464	* width/bpp.
1465	*
1466	* @param pThis VMSVGA State
1467	*/
1468	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis)
1469	{
1470	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1471	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1472	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1473	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1474
1475	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1476	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1477	* location but it has a different meaning.
1478	*/
1479	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1480	uFifoPitchLock = 0;
1481
1482	/* Sanitize values. */
1483	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1484	uFifoPitchLock = 0;
1485	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1486	uRegPitchLock = 0;
1487
1488	/* Prefer the register value to the FIFO value.*/
1489	if (uRegPitchLock)
1490	pThis->svga.cbScanline = uRegPitchLock;
1491	else if (uFifoPitchLock)
1492	pThis->svga.cbScanline = uFifoPitchLock;
1493	else
1494	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1495
1496	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1497	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1498	}
1499
1500	#endif /* IN_RING0 \|\| IN_RING3 */
1501
1502
1503	/**
1504	* Write port register
1505	*
1506	* @returns Strict VBox status code.
1507	* @param pThis VMSVGA State
1508	* @param u32 Value to write
1509	*/
1510	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32)
1511	{
1512	#ifdef IN_RING3
1513	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1514	#endif
1515	VBOXSTRICTRC rc = VINF_SUCCESS;
1516
1517	/* Rough index register validation. */
1518	uint32_t idxReg = pThis->svga.u32IndexReg;
1519	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1520	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1521	VINF_IOM_R3_IOPORT_WRITE);
1522	#else
1523	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1524	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1525	VINF_SUCCESS);
1526	#endif
1527	RT_UNTRUSTED_VALIDATED_FENCE();
1528
1529	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1530	if ( idxReg >= SVGA_REG_CAPABILITIES
1531	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1532	{
1533	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1534	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1535	}
1536	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1537	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1538	switch (idxReg)
1539	{
1540	case SVGA_REG_WIDTH:
1541	case SVGA_REG_HEIGHT:
1542	case SVGA_REG_PITCHLOCK:
1543	case SVGA_REG_BITS_PER_PIXEL:
1544	pThis->svga.fGFBRegisters = true;
1545	break;
1546	default:
1547	break;
1548	}
1549
1550	switch (idxReg)
1551	{
1552	case SVGA_REG_ID:
1553	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1554	if ( u32 == SVGA_ID_0
1555	\|\| u32 == SVGA_ID_1
1556	\|\| u32 == SVGA_ID_2)
1557	pThis->svga.u32SVGAId = u32;
1558	else
1559	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1560	break;
1561
1562	case SVGA_REG_ENABLE:
1563	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1564	#ifdef IN_RING3
1565	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1566	&& pThis->svga.fEnabled == false)
1567	{
1568	/* Make a backup copy of the first 512kb in order to save font data etc. */
1569	/** @todo should probably swap here, rather than copy + zero */
1570	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1571	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1572	}
1573
1574	pThis->svga.fEnabled = u32;
1575	if (pThis->svga.fEnabled)
1576	{
1577	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1578	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1579	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1580	{
1581	/* Keep the current mode. */
1582	pThis->svga.uWidth = pThis->pDrv->cx;
1583	pThis->svga.uHeight = pThis->pDrv->cy;
1584	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1585	}
1586
1587	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1588	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1589	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1590	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1591	# ifdef LOG_ENABLED
1592	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1593	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1594	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1595	# endif
1596
1597	/* Disable or enable dirty page tracking according to the current fTraces value. */
1598	vmsvgaR3SetTraces(pThis, !!pThis->svga.fTraces);
1599
1600	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1601	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1602	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/);
1603	}
1604	else
1605	{
1606	/* Restore the text mode backup. */
1607	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1608
1609	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1610
1611	/* Enable dirty page tracking again when going into legacy mode. */
1612	vmsvgaR3SetTraces(pThis, true);
1613
1614	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1615	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1616	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1617
1618	/* Clear the pitch lock. */
1619	pThis->svga.u32PitchLock = 0;
1620	}
1621	#else /* !IN_RING3 */
1622	rc = VINF_IOM_R3_IOPORT_WRITE;
1623	#endif /* !IN_RING3 */
1624	break;
1625
1626	case SVGA_REG_WIDTH:
1627	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1628	if (pThis->svga.uWidth != u32)
1629	{
1630	#if defined(IN_RING3) \|\| defined(IN_RING0)
1631	pThis->svga.uWidth = u32;
1632	vmsvgaHCUpdatePitch(pThis);
1633	if (pThis->svga.fEnabled)
1634	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1635	#else
1636	rc = VINF_IOM_R3_IOPORT_WRITE;
1637	#endif
1638	}
1639	/* else: nop */
1640	break;
1641
1642	case SVGA_REG_HEIGHT:
1643	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1644	if (pThis->svga.uHeight != u32)
1645	{
1646	pThis->svga.uHeight = u32;
1647	if (pThis->svga.fEnabled)
1648	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1649	}
1650	/* else: nop */
1651	break;
1652
1653	case SVGA_REG_DEPTH:
1654	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1655	/** @todo read-only?? */
1656	break;
1657
1658	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1659	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1660	if (pThis->svga.uBpp != u32)
1661	{
1662	#if defined(IN_RING3) \|\| defined(IN_RING0)
1663	pThis->svga.uBpp = u32;
1664	vmsvgaHCUpdatePitch(pThis);
1665	if (pThis->svga.fEnabled)
1666	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1667	#else
1668	rc = VINF_IOM_R3_IOPORT_WRITE;
1669	#endif
1670	}
1671	/* else: nop */
1672	break;
1673
1674	case SVGA_REG_PSEUDOCOLOR:
1675	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1676	break;
1677
1678	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1679	#ifdef IN_RING3
1680	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1681	pThis->svga.fConfigured = u32;
1682	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1683	if (!pThis->svga.fConfigured)
1684	pThis->svga.fTraces = true;
1685	vmsvgaR3SetTraces(pThis, !!pThis->svga.fTraces);
1686	#else
1687	rc = VINF_IOM_R3_IOPORT_WRITE;
1688	#endif
1689	break;
1690
1691	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1692	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1693	if ( pThis->svga.fEnabled
1694	&& pThis->svga.fConfigured)
1695	{
1696	#if defined(IN_RING3) \|\| defined(IN_RING0)
1697	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1698	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1699	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1700	vmsvgaHCSafeFifoBusyRegUpdate(pThis, true);
1701
1702	/* Kick the FIFO thread to start processing commands again. */
1703	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1704	#else
1705	rc = VINF_IOM_R3_IOPORT_WRITE;
1706	#endif
1707	}
1708	/* else nothing to do. */
1709	else
1710	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1711
1712	break;
1713
1714	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1715	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1716	break;
1717
1718	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1719	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1720	pThis->svga.u32GuestId = u32;
1721	break;
1722
1723	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1724	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1725	pThis->svga.u32PitchLock = u32;
1726	/* Should this also update the FIFO pitch lock? Unclear. */
1727	break;
1728
1729	case SVGA_REG_IRQMASK: /* Interrupt mask */
1730	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1731	pThis->svga.u32IrqMask = u32;
1732
1733	/* Irq pending after the above change? */
1734	if (pThis->svga.u32IrqStatus & u32)
1735	{
1736	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1737	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1738	}
1739	else
1740	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1741	break;
1742
1743	/* Mouse cursor support */
1744	case SVGA_REG_CURSOR_ID:
1745	case SVGA_REG_CURSOR_X:
1746	case SVGA_REG_CURSOR_Y:
1747	case SVGA_REG_CURSOR_ON:
1748	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1749	break;
1750
1751	/* Legacy multi-monitor support */
1752	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1753	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1754	break;
1755	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1756	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1757	break;
1758	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1759	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1760	break;
1761	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1762	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1763	break;
1764	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1765	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1766	break;
1767	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1769	break;
1770	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1771	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1772	break;
1773	#ifdef VBOX_WITH_VMSVGA3D
1774	/* See "Guest memory regions" below. */
1775	case SVGA_REG_GMR_ID:
1776	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1777	pThis->svga.u32CurrentGMRId = u32;
1778	break;
1779
1780	case SVGA_REG_GMR_DESCRIPTOR:
1781	# ifndef IN_RING3
1782	rc = VINF_IOM_R3_IOPORT_WRITE;
1783	break;
1784	# else /* IN_RING3 */
1785	{
1786	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1787
1788	/* Validate current GMR id. */
1789	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1790	AssertBreak(idGMR < pThis->svga.cGMR);
1791	RT_UNTRUSTED_VALIDATED_FENCE();
1792
1793	/* Free the old GMR if present. */
1794	vmsvgaR3GmrFree(pThis, idGMR);
1795
1796	/* Just undefine the GMR? */
1797	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1798	if (GCPhys == 0)
1799	{
1800	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1801	break;
1802	}
1803
1804
1805	/* Never cross a page boundary automatically. */
1806	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1807	uint32_t cPagesTotal = 0;
1808	uint32_t iDesc = 0;
1809	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1810	uint32_t cLoops = 0;
1811	RTGCPHYS GCPhysBase = GCPhys;
1812	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1813	{
1814	/* Read descriptor. */
1815	SVGAGuestMemDescriptor desc;
1816	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1817	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1818
1819	if (desc.numPages != 0)
1820	{
1821	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1822	cPagesTotal += desc.numPages;
1823	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1824
1825	if ((iDesc & 15) == 0)
1826	{
1827	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1828	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1829	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1830	}
1831
1832	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1833	paDescs[iDesc++].numPages = desc.numPages;
1834
1835	/* Continue with the next descriptor. */
1836	GCPhys += sizeof(desc);
1837	}
1838	else if (desc.ppn == 0)
1839	break; /* terminator */
1840	else /* Pointer to the next physical page of descriptors. */
1841	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1842
1843	cLoops++;
1844	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1845	}
1846
1847	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1848	if (RT_SUCCESS(rc))
1849	{
1850	/* Commit the GMR. */
1851	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1852	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1853	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1854	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1855	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1856	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1857	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1858	}
1859	else
1860	{
1861	RTMemFree(paDescs);
1862	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1863	}
1864	break;
1865	}
1866	# endif /* IN_RING3 */
1867	#endif // VBOX_WITH_VMSVGA3D
1868
1869	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1870	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1871	if (pThis->svga.fTraces == u32)
1872	break; /* nothing to do */
1873
1874	#ifdef IN_RING3
1875	vmsvgaR3SetTraces(pThis, !!u32);
1876	#else
1877	rc = VINF_IOM_R3_IOPORT_WRITE;
1878	#endif
1879	break;
1880
1881	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1882	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1883	break;
1884
1885	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1886	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1887	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1888	break;
1889
1890	case SVGA_REG_FB_START:
1891	case SVGA_REG_MEM_START:
1892	case SVGA_REG_HOST_BITS_PER_PIXEL:
1893	case SVGA_REG_MAX_WIDTH:
1894	case SVGA_REG_MAX_HEIGHT:
1895	case SVGA_REG_VRAM_SIZE:
1896	case SVGA_REG_FB_SIZE:
1897	case SVGA_REG_CAPABILITIES:
1898	case SVGA_REG_MEM_SIZE:
1899	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1900	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1901	case SVGA_REG_BYTES_PER_LINE:
1902	case SVGA_REG_FB_OFFSET:
1903	case SVGA_REG_RED_MASK:
1904	case SVGA_REG_GREEN_MASK:
1905	case SVGA_REG_BLUE_MASK:
1906	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1907	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1908	case SVGA_REG_GMR_MAX_IDS:
1909	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1910	/* Read only - ignore. */
1911	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1912	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1913	break;
1914
1915	default:
1916	{
1917	uint32_t offReg;
1918	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1919	{
1920	RT_UNTRUSTED_VALIDATED_FENCE();
1921	pThis->svga.au32ScratchRegion[offReg] = u32;
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1923	}
1924	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1925	{
1926	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1927	Btw, see rgb_to_pixel32. */
1928	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1929	u32 &= 0xff;
1930	RT_UNTRUSTED_VALIDATED_FENCE();
1931	uint32_t uRgb = pThis->last_palette[offReg / 3];
1932	switch (offReg % 3)
1933	{
1934	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1935	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1936	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1937	}
1938	pThis->last_palette[offReg / 3] = uRgb;
1939	}
1940	else
1941	{
1942	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1943	rc = VINF_IOM_R3_IOPORT_WRITE;
1944	#else
1945	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1946	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1947	#endif
1948	}
1949	break;
1950	}
1951	}
1952	return rc;
1953	}
1954
1955	/**
1956	* @callback_method_impl{FNIOMIOPORTNEWIN}
1957	*/
1958	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1959	{
1960	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1961	RT_NOREF_PV(pvUser);
1962
1963	/* Only dword accesses. */
1964	if (cb == 4)
1965	{
1966	switch (offPort)
1967	{
1968	case SVGA_INDEX_PORT:
1969	*pu32 = pThis->svga.u32IndexReg;
1970	break;
1971
1972	case SVGA_VALUE_PORT:
1973	return vmsvgaReadPort(pDevIns, pThis, pu32);
1974
1975	case SVGA_BIOS_PORT:
1976	Log(("Ignoring BIOS port read\n"));
1977	*pu32 = 0;
1978	break;
1979
1980	case SVGA_IRQSTATUS_PORT:
1981	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1982	*pu32 = pThis->svga.u32IrqStatus;
1983	break;
1984
1985	default:
1986	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1987	*pu32 = UINT32_MAX;
1988	break;
1989	}
1990	}
1991	else
1992	{
1993	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
1994	*pu32 = UINT32_MAX;
1995	}
1996	return VINF_SUCCESS;
1997	}
1998
1999	/**
2000	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2001	*/
2002	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2003	{
2004	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2005	RT_NOREF_PV(pvUser);
2006
2007	/* Only dword accesses. */
2008	if (cb == 4)
2009	switch (offPort)
2010	{
2011	case SVGA_INDEX_PORT:
2012	pThis->svga.u32IndexReg = u32;
2013	break;
2014
2015	case SVGA_VALUE_PORT:
2016	return vmsvgaWritePort(pDevIns, pThis, u32);
2017
2018	case SVGA_BIOS_PORT:
2019	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2020	break;
2021
2022	case SVGA_IRQSTATUS_PORT:
2023	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2024	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2025	/* Clear the irq in case all events have been cleared. */
2026	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2027	{
2028	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2029	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2030	}
2031	break;
2032
2033	default:
2034	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2035	break;
2036	}
2037	else
2038	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2039
2040	return VINF_SUCCESS;
2041	}
2042
2043	#ifdef IN_RING3
2044
2045	# ifdef DEBUG_FIFO_ACCESS
2046	/**
2047	* Handle FIFO memory access.
2048	* @returns VBox status code.
2049	* @param pVM VM handle.
2050	* @param pThis VGA device instance data.
2051	* @param GCPhys The access physical address.
2052	* @param fWriteAccess Read or write access
2053	*/
2054	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2055	{
2056	RT_NOREF(pVM);
2057	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2058	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2059
2060	switch (GCPhysOffset >> 2)
2061	{
2062	case SVGA_FIFO_MIN:
2063	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2064	break;
2065	case SVGA_FIFO_MAX:
2066	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2067	break;
2068	case SVGA_FIFO_NEXT_CMD:
2069	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2070	break;
2071	case SVGA_FIFO_STOP:
2072	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2073	break;
2074	case SVGA_FIFO_CAPABILITIES:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_FLAGS:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_FENCE:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_3D_HWVERSION:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_PITCHLOCK:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_CURSOR_ON:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_CURSOR_X:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_CURSOR_Y:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_CURSOR_COUNT:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_RESERVED:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_CURSOR_SCREEN_ID:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_DEAD:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_3D_HWVERSION_REVISED:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS_LAST:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_GUEST_3D_HWVERSION:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_FENCE_GOAL:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_BUSY:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	default:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	}
2381
2382	return VINF_EM_RAW_EMULATE_INSTR;
2383	}
2384	# endif /* DEBUG_FIFO_ACCESS */
2385
2386	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2387	/**
2388	* HC access handler for the FIFO.
2389	*
2390	* @returns VINF_SUCCESS if the handler have carried out the operation.
2391	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2392	* @param pVM VM Handle.
2393	* @param pVCpu The cross context CPU structure for the calling EMT.
2394	* @param GCPhys The physical address the guest is writing to.
2395	* @param pvPhys The HC mapping of that address.
2396	* @param pvBuf What the guest is reading/writing.
2397	* @param cbBuf How much it's reading/writing.
2398	* @param enmAccessType The access type.
2399	* @param enmOrigin Who is making the access.
2400	* @param pvUser User argument.
2401	*/
2402	static DECLCALLBACK(VBOXSTRICTRC)
2403	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2404	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2405	{
2406	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2407	PVGASTATE pThis = (PVGASTATE)pvUser;
2408	AssertPtr(pThis);
2409
2410	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2411	/*
2412	* Wake up the FIFO thread as it might have work to do now.
2413	*/
2414	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2415	AssertLogRelRC(rc);
2416	# endif
2417
2418	# ifdef DEBUG_FIFO_ACCESS
2419	/*
2420	* When in debug-fifo-access mode, we do not disable the access handler,
2421	* but leave it on as we wish to catch all access.
2422	*/
2423	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2424	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2425	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2426	/*
2427	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2428	*/
2429	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2430	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2431	# endif
2432	if (RT_SUCCESS(rc))
2433	return VINF_PGM_HANDLER_DO_DEFAULT;
2434	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2435	return rc;
2436	}
2437	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2438
2439	#endif /* IN_RING3 */
2440
2441	#ifdef DEBUG_GMR_ACCESS
2442	# ifdef IN_RING3
2443
2444	/**
2445	* HC access handler for the FIFO.
2446	*
2447	* @returns VINF_SUCCESS if the handler have carried out the operation.
2448	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2449	* @param pVM VM Handle.
2450	* @param pVCpu The cross context CPU structure for the calling EMT.
2451	* @param GCPhys The physical address the guest is writing to.
2452	* @param pvPhys The HC mapping of that address.
2453	* @param pvBuf What the guest is reading/writing.
2454	* @param cbBuf How much it's reading/writing.
2455	* @param enmAccessType The access type.
2456	* @param enmOrigin Who is making the access.
2457	* @param pvUser User argument.
2458	*/
2459	static DECLCALLBACK(VBOXSTRICTRC)
2460	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2461	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2462	{
2463	PVGASTATE pThis = (PVGASTATE)pvUser;
2464	Assert(pThis);
2465	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2466	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2467
2468	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2469
2470	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2471	{
2472	PGMR pGMR = &pSVGAState->paGMR[i];
2473
2474	if (pGMR->numDescriptors)
2475	{
2476	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2477	{
2478	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2479	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2480	{
2481	/*
2482	* Turn off the write handler for this particular page and make it R/W.
2483	* Then return telling the caller to restart the guest instruction.
2484	*/
2485	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2486	AssertRC(rc);
2487	return VINF_PGM_HANDLER_DO_DEFAULT;
2488	}
2489	}
2490	}
2491	}
2492
2493	return VINF_PGM_HANDLER_DO_DEFAULT;
2494	}
2495
2496	/** Callback handler for VMR3ReqCallWaitU */
2497	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2498	{
2499	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2500	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2501	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2502	int rc;
2503
2504	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2505	{
2506	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2507	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2508	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2509	AssertRC(rc);
2510	}
2511	return VINF_SUCCESS;
2512	}
2513
2514	/** Callback handler for VMR3ReqCallWaitU */
2515	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2516	{
2517	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2518	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2519	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2520
2521	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2522	{
2523	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2524	AssertRC(rc);
2525	}
2526	return VINF_SUCCESS;
2527	}
2528
2529	/** Callback handler for VMR3ReqCallWaitU */
2530	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2531	{
2532	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2533
2534	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2535	{
2536	PGMR pGMR = &pSVGAState->paGMR[i];
2537
2538	if (pGMR->numDescriptors)
2539	{
2540	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2541	{
2542	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2543	AssertRC(rc);
2544	}
2545	}
2546	}
2547	return VINF_SUCCESS;
2548	}
2549
2550	# endif /* IN_RING3 */
2551	#endif /* DEBUG_GMR_ACCESS */
2552
2553	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2554
2555	#ifdef IN_RING3
2556
2557
2558	/**
2559	* Common worker for changing the pointer shape.
2560	*
2561	* @param pThis The VGA instance data.
2562	* @param pSVGAState The VMSVGA ring-3 instance data.
2563	* @param fAlpha Whether there is alpha or not.
2564	* @param xHot Hotspot x coordinate.
2565	* @param yHot Hotspot y coordinate.
2566	* @param cx Width.
2567	* @param cy Height.
2568	* @param pbData Heap copy of the cursor data. Consumed.
2569	* @param cbData The size of the data.
2570	*/
2571	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2572	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2573	{
2574	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2575	# ifdef LOG_ENABLED
2576	if (LogIs2Enabled())
2577	{
2578	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2579	if (!fAlpha)
2580	{
2581	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2582	for (uint32_t y = 0; y < cy; y++)
2583	{
2584	Log2(("%3u:", y));
2585	uint8_t const pbLine = &pbData[y cbAndLine];
2586	for (uint32_t x = 0; x < cx; x += 8)
2587	{
2588	uint8_t b = pbLine[x / 8];
2589	char szByte[12];
2590	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2591	szByte[1] = b & 0x40 ? '*' : ' ';
2592	szByte[2] = b & 0x20 ? '*' : ' ';
2593	szByte[3] = b & 0x10 ? '*' : ' ';
2594	szByte[4] = b & 0x08 ? '*' : ' ';
2595	szByte[5] = b & 0x04 ? '*' : ' ';
2596	szByte[6] = b & 0x02 ? '*' : ' ';
2597	szByte[7] = b & 0x01 ? '*' : ' ';
2598	szByte[8] = '\0';
2599	Log2(("%s", szByte));
2600	}
2601	Log2(("\n"));
2602	}
2603	}
2604
2605	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2606	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2607	for (uint32_t y = 0; y < cy; y++)
2608	{
2609	Log2(("%3u:", y));
2610	uint32_t const pu32Line = &pu32Xor[y cx];
2611	for (uint32_t x = 0; x < cx; x++)
2612	Log2((" %08x", pu32Line[x]));
2613	Log2(("\n"));
2614	}
2615	}
2616	# endif
2617
2618	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2619	AssertRC(rc);
2620
2621	if (pSVGAState->Cursor.fActive)
2622	RTMemFree(pSVGAState->Cursor.pData);
2623
2624	pSVGAState->Cursor.fActive = true;
2625	pSVGAState->Cursor.xHotspot = xHot;
2626	pSVGAState->Cursor.yHotspot = yHot;
2627	pSVGAState->Cursor.width = cx;
2628	pSVGAState->Cursor.height = cy;
2629	pSVGAState->Cursor.cbData = cbData;
2630	pSVGAState->Cursor.pData = pbData;
2631	}
2632
2633
2634	/**
2635	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2636	*
2637	* @param pThis The VGA instance data.
2638	* @param pSVGAState The VMSVGA ring-3 instance data.
2639	* @param pCursor The cursor.
2640	* @param pbSrcAndMask The AND mask.
2641	* @param cbSrcAndLine The scanline length of the AND mask.
2642	* @param pbSrcXorMask The XOR mask.
2643	* @param cbSrcXorLine The scanline length of the XOR mask.
2644	*/
2645	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2646	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2647	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2648	{
2649	uint32_t const cx = pCursor->width;
2650	uint32_t const cy = pCursor->height;
2651
2652	/*
2653	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2654	* The AND data uses 8-bit aligned scanlines.
2655	* The XOR data must be starting on a 32-bit boundrary.
2656	*/
2657	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2658	uint32_t cbDstAndMask = cbDstAndLine * cy;
2659	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2660	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2661
2662	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2663	AssertReturnVoid(pbCopy);
2664
2665	/* Convert the AND mask. */
2666	uint8_t *pbDst = pbCopy;
2667	uint8_t const *pbSrc = pbSrcAndMask;
2668	switch (pCursor->andMaskDepth)
2669	{
2670	case 1:
2671	if (cbSrcAndLine == cbDstAndLine)
2672	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2673	else
2674	{
2675	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2676	for (uint32_t y = 0; y < cy; y++)
2677	{
2678	memcpy(pbDst, pbSrc, cbDstAndLine);
2679	pbDst += cbDstAndLine;
2680	pbSrc += cbSrcAndLine;
2681	}
2682	}
2683	break;
2684	/* Should take the XOR mask into account for the multi-bit AND mask. */
2685	case 8:
2686	for (uint32_t y = 0; y < cy; y++)
2687	{
2688	for (uint32_t x = 0; x < cx; )
2689	{
2690	uint8_t bDst = 0;
2691	uint8_t fBit = 1;
2692	do
2693	{
2694	uintptr_t const idxPal = pbSrc[x] * 3;
2695	if ((( pThis->last_palette[idxPal]
2696	\| (pThis->last_palette[idxPal] >> 8)
2697	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2698	bDst \|= fBit;
2699	fBit <<= 1;
2700	x++;
2701	} while (x < cx && (x & 7));
2702	pbDst[(x - 1) / 8] = bDst;
2703	}
2704	pbDst += cbDstAndLine;
2705	pbSrc += cbSrcAndLine;
2706	}
2707	break;
2708	case 15:
2709	for (uint32_t y = 0; y < cy; y++)
2710	{
2711	for (uint32_t x = 0; x < cx; )
2712	{
2713	uint8_t bDst = 0;
2714	uint8_t fBit = 1;
2715	do
2716	{
2717	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2718	bDst \|= fBit;
2719	fBit <<= 1;
2720	x++;
2721	} while (x < cx && (x & 7));
2722	pbDst[(x - 1) / 8] = bDst;
2723	}
2724	pbDst += cbDstAndLine;
2725	pbSrc += cbSrcAndLine;
2726	}
2727	break;
2728	case 16:
2729	for (uint32_t y = 0; y < cy; y++)
2730	{
2731	for (uint32_t x = 0; x < cx; )
2732	{
2733	uint8_t bDst = 0;
2734	uint8_t fBit = 1;
2735	do
2736	{
2737	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2738	bDst \|= fBit;
2739	fBit <<= 1;
2740	x++;
2741	} while (x < cx && (x & 7));
2742	pbDst[(x - 1) / 8] = bDst;
2743	}
2744	pbDst += cbDstAndLine;
2745	pbSrc += cbSrcAndLine;
2746	}
2747	break;
2748	case 24:
2749	for (uint32_t y = 0; y < cy; y++)
2750	{
2751	for (uint32_t x = 0; x < cx; )
2752	{
2753	uint8_t bDst = 0;
2754	uint8_t fBit = 1;
2755	do
2756	{
2757	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2758	bDst \|= fBit;
2759	fBit <<= 1;
2760	x++;
2761	} while (x < cx && (x & 7));
2762	pbDst[(x - 1) / 8] = bDst;
2763	}
2764	pbDst += cbDstAndLine;
2765	pbSrc += cbSrcAndLine;
2766	}
2767	break;
2768	case 32:
2769	for (uint32_t y = 0; y < cy; y++)
2770	{
2771	for (uint32_t x = 0; x < cx; )
2772	{
2773	uint8_t bDst = 0;
2774	uint8_t fBit = 1;
2775	do
2776	{
2777	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2778	bDst \|= fBit;
2779	fBit <<= 1;
2780	x++;
2781	} while (x < cx && (x & 7));
2782	pbDst[(x - 1) / 8] = bDst;
2783	}
2784	pbDst += cbDstAndLine;
2785	pbSrc += cbSrcAndLine;
2786	}
2787	break;
2788	default:
2789	RTMemFree(pbCopy);
2790	AssertFailedReturnVoid();
2791	}
2792
2793	/* Convert the XOR mask. */
2794	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2795	pbSrc = pbSrcXorMask;
2796	switch (pCursor->xorMaskDepth)
2797	{
2798	case 1:
2799	for (uint32_t y = 0; y < cy; y++)
2800	{
2801	for (uint32_t x = 0; x < cx; )
2802	{
2803	/* most significant bit is the left most one. */
2804	uint8_t bSrc = pbSrc[x / 8];
2805	do
2806	{
2807	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2808	bSrc <<= 1;
2809	x++;
2810	} while ((x & 7) && x < cx);
2811	}
2812	pbSrc += cbSrcXorLine;
2813	}
2814	break;
2815	case 8:
2816	for (uint32_t y = 0; y < cy; y++)
2817	{
2818	for (uint32_t x = 0; x < cx; x++)
2819	{
2820	uint32_t u = pThis->last_palette[pbSrc[x]];
2821	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2822	}
2823	pbSrc += cbSrcXorLine;
2824	}
2825	break;
2826	case 15: /* Src: RGB-5-5-5 */
2827	for (uint32_t y = 0; y < cy; y++)
2828	{
2829	for (uint32_t x = 0; x < cx; x++)
2830	{
2831	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2832	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2833	((uValue >> 5) & 0x1f) << 3,
2834	((uValue >> 10) & 0x1f) << 3, 0);
2835	}
2836	pbSrc += cbSrcXorLine;
2837	}
2838	break;
2839	case 16: /* Src: RGB-5-6-5 */
2840	for (uint32_t y = 0; y < cy; y++)
2841	{
2842	for (uint32_t x = 0; x < cx; x++)
2843	{
2844	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2845	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2846	((uValue >> 5) & 0x3f) << 2,
2847	((uValue >> 11) & 0x1f) << 3, 0);
2848	}
2849	pbSrc += cbSrcXorLine;
2850	}
2851	break;
2852	case 24:
2853	for (uint32_t y = 0; y < cy; y++)
2854	{
2855	for (uint32_t x = 0; x < cx; x++)
2856	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2857	pbSrc += cbSrcXorLine;
2858	}
2859	break;
2860	case 32:
2861	for (uint32_t y = 0; y < cy; y++)
2862	{
2863	for (uint32_t x = 0; x < cx; x++)
2864	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2865	pbSrc += cbSrcXorLine;
2866	}
2867	break;
2868	default:
2869	RTMemFree(pbCopy);
2870	AssertFailedReturnVoid();
2871	}
2872
2873	/*
2874	* Pass it to the frontend/whatever.
2875	*/
2876	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2877	}
2878
2879
2880	/**
2881	* Worker for vmsvgaR3FifoThread that handles an external command.
2882	*
2883	* @param pThis VGA device instance data.
2884	*/
2885	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2886	{
2887	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2888	switch (pThis->svga.u8FIFOExtCommand)
2889	{
2890	case VMSVGA_FIFO_EXTCMD_RESET:
2891	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2892	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2893	# ifdef VBOX_WITH_VMSVGA3D
2894	if (pThis->svga.f3DEnabled)
2895	{
2896	/* The 3d subsystem must be reset from the fifo thread. */
2897	vmsvga3dReset(pThis);
2898	}
2899	# endif
2900	break;
2901
2902	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2903	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2904	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2905	# ifdef VBOX_WITH_VMSVGA3D
2906	if (pThis->svga.f3DEnabled)
2907	{
2908	/* The 3d subsystem must be shut down from the fifo thread. */
2909	vmsvga3dTerminate(pThis);
2910	}
2911	# endif
2912	break;
2913
2914	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2915	{
2916	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2917	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2918	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2919	vmsvgaR3SaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM);
2920	# ifdef VBOX_WITH_VMSVGA3D
2921	if (pThis->svga.f3DEnabled)
2922	vmsvga3dSaveExec(pThis->pDevInsR3, pThis, pSSM);
2923	# endif
2924	break;
2925	}
2926
2927	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2928	{
2929	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2930	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2931	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2932	vmsvgaR3LoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2933	# ifdef VBOX_WITH_VMSVGA3D
2934	if (pThis->svga.f3DEnabled)
2935	vmsvga3dLoadExec(pThis->pDevInsR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2936	# endif
2937	break;
2938	}
2939
2940	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2941	{
2942	# ifdef VBOX_WITH_VMSVGA3D
2943	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2944	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2945	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2946	# endif
2947	break;
2948	}
2949
2950
2951	default:
2952	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2953	break;
2954	}
2955
2956	/*
2957	* Signal the end of the external command.
2958	*/
2959	pThis->svga.pvFIFOExtCmdParam = NULL;
2960	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2961	ASMMemoryFence(); /* paranoia^2 */
2962	int rc = RTSemEventSignal(pThis->svga.hFIFOExtCmdSem);
2963	AssertLogRelRC(rc);
2964	}
2965
2966	/**
2967	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2968	* doing a job on the FIFO thread (even when it's officially suspended).
2969	*
2970	* @returns VBox status code (fully asserted).
2971	* @param pDevIns The device instance.
2972	* @param pThis VGA device instance data.
2973	* @param uExtCmd The command to execute on the FIFO thread.
2974	* @param pvParam Pointer to command parameters.
2975	* @param cMsWait The time to wait for the command, given in
2976	* milliseconds.
2977	*/
2978	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis,
2979	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2980	{
2981	Assert(cMsWait >= RT_MS_1SEC * 5);
2982	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2983	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2984
2985	int rc;
2986	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2987	PDMTHREADSTATE enmState = pThread->enmState;
2988	if (enmState == PDMTHREADSTATE_SUSPENDED)
2989	{
2990	/*
2991	* The thread is suspended, we have to temporarily wake it up so it can
2992	* perform the task.
2993	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2994	*/
2995	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2996	/* Post the request. */
2997	pThis->svga.fFifoExtCommandWakeup = true;
2998	pThis->svga.pvFIFOExtCmdParam = pvParam;
2999	pThis->svga.u8FIFOExtCommand = uExtCmd;
3000	ASMMemoryFence(); /* paranoia^3 */
3001
3002	/* Resume the thread. */
3003	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3004	AssertLogRelRC(rc);
3005	if (RT_SUCCESS(rc))
3006	{
3007	/* Wait. Take care in case the semaphore was already posted (same as below). */
3008	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3009	if ( rc == VINF_SUCCESS
3010	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3011	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3012	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3013	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3014
3015	/* suspend the thread */
3016	pThis->svga.fFifoExtCommandWakeup = false;
3017	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3018	AssertLogRelRC(rc2);
3019	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3020	rc = rc2;
3021	}
3022	pThis->svga.fFifoExtCommandWakeup = false;
3023	pThis->svga.pvFIFOExtCmdParam = NULL;
3024	}
3025	else if (enmState == PDMTHREADSTATE_RUNNING)
3026	{
3027	/*
3028	* The thread is running, should only happen during reset and vmsvga3dsfc.
3029	* We ASSUME not racing code here, both wrt thread state and ext commands.
3030	*/
3031	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3032	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3033
3034	/* Post the request. */
3035	pThis->svga.pvFIFOExtCmdParam = pvParam;
3036	pThis->svga.u8FIFOExtCommand = uExtCmd;
3037	ASMMemoryFence(); /* paranoia^2 */
3038	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3039	AssertLogRelRC(rc);
3040
3041	/* Wait. Take care in case the semaphore was already posted (same as above). */
3042	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3043	if ( rc == VINF_SUCCESS
3044	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3045	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3046	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3047	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3048
3049	pThis->svga.pvFIFOExtCmdParam = NULL;
3050	}
3051	else
3052	{
3053	/*
3054	* Something is wrong with the thread!
3055	*/
3056	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3057	rc = VERR_INVALID_STATE;
3058	}
3059	return rc;
3060	}
3061
3062
3063	/**
3064	* Marks the FIFO non-busy, notifying any waiting EMTs.
3065	*
3066	* @param pThis The VGA state.
3067	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3068	* @param offFifoMin The start byte offset of the command FIFO.
3069	*/
3070	static void vmsvgaR3FifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3071	{
3072	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3073	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3074	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3075
3076	/* Wake up any waiting EMTs. */
3077	if (pSVGAState->cBusyDelayedEmts > 0)
3078	{
3079	# ifdef VMSVGA_USE_EMT_HALT_CODE
3080	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3081	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3082	if (idCpu != NIL_VMCPUID)
3083	{
3084	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3085	while (idCpu-- > 0)
3086	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3087	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3088	}
3089	# else
3090	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3091	AssertRC(rc2);
3092	# endif
3093	}
3094	}
3095
3096	/**
3097	* Reads (more) payload into the command buffer.
3098	*
3099	* @returns pbBounceBuf on success
3100	* @retval (void *)1 if the thread was requested to stop.
3101	* @retval NULL on FIFO error.
3102	*
3103	* @param cbPayloadReq The number of bytes of payload requested.
3104	* @param pFIFO The FIFO.
3105	* @param offCurrentCmd The FIFO byte offset of the current command.
3106	* @param offFifoMin The start byte offset of the command FIFO.
3107	* @param offFifoMax The end byte offset of the command FIFO.
3108	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3109	* always sufficient size.
3110	* @param pcbAlreadyRead How much payload we've already read into the bounce
3111	* buffer. (We will NEVER re-read anything.)
3112	* @param pThread The calling PDM thread handle.
3113	* @param pThis The VGA state.
3114	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3115	* statistics collection.
3116	*/
3117	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3118	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3119	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3120	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3121	{
3122	Assert(pbBounceBuf);
3123	Assert(pcbAlreadyRead);
3124	Assert(offFifoMin < offFifoMax);
3125	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3126	Assert(offFifoMax <= pThis->svga.cbFIFO);
3127
3128	/*
3129	* Check if the requested payload size has already been satisfied .
3130	* .
3131	* When called to read more, the caller is responsible for making sure the .
3132	* new command size (cbRequsted) never is smaller than what has already .
3133	* been read.
3134	*/
3135	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3136	if (cbPayloadReq <= cbAlreadyRead)
3137	{
3138	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3139	return pbBounceBuf;
3140	}
3141
3142	/*
3143	* Commands bigger than the fifo buffer are invalid.
3144	*/
3145	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3146	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3147	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3148	NULL);
3149
3150	/*
3151	* Move offCurrentCmd past the command dword.
3152	*/
3153	offCurrentCmd += sizeof(uint32_t);
3154	if (offCurrentCmd >= offFifoMax)
3155	offCurrentCmd = offFifoMin;
3156
3157	/*
3158	* Do we have sufficient payload data available already?
3159	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3160	*/
3161	uint32_t cbAfter, cbBefore;
3162	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3163	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3164	if (offNextCmd >= offCurrentCmd)
3165	{
3166	if (RT_LIKELY(offNextCmd < offFifoMax))
3167	cbAfter = offNextCmd - offCurrentCmd;
3168	else
3169	{
3170	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3171	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3172	offNextCmd, offFifoMin, offFifoMax));
3173	cbAfter = offFifoMax - offCurrentCmd;
3174	}
3175	cbBefore = 0;
3176	}
3177	else
3178	{
3179	cbAfter = offFifoMax - offCurrentCmd;
3180	if (offNextCmd >= offFifoMin)
3181	cbBefore = offNextCmd - offFifoMin;
3182	else
3183	{
3184	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3185	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3186	offNextCmd, offFifoMin, offFifoMax));
3187	cbBefore = 0;
3188	}
3189	}
3190	if (cbAfter + cbBefore < cbPayloadReq)
3191	{
3192	/*
3193	* Insufficient, must wait for it to arrive.
3194	*/
3195	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3196	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3197	for (uint32_t i = 0;; i++)
3198	{
3199	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3200	{
3201	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3202	return (void *)(uintptr_t)1;
3203	}
3204	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3205	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3206
3207	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3208
3209	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3210	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3211	if (offNextCmd >= offCurrentCmd)
3212	{
3213	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3214	cbBefore = 0;
3215	}
3216	else
3217	{
3218	cbAfter = offFifoMax - offCurrentCmd;
3219	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3220	}
3221
3222	if (cbAfter + cbBefore >= cbPayloadReq)
3223	break;
3224	}
3225	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3226	}
3227
3228	/*
3229	* Copy out the memory and update what pcbAlreadyRead points to.
3230	*/
3231	if (cbAfter >= cbPayloadReq)
3232	memcpy(pbBounceBuf + cbAlreadyRead,
3233	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3234	cbPayloadReq - cbAlreadyRead);
3235	else
3236	{
3237	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3238	if (cbAlreadyRead < cbAfter)
3239	{
3240	memcpy(pbBounceBuf + cbAlreadyRead,
3241	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3242	cbAfter - cbAlreadyRead);
3243	cbAlreadyRead = cbAfter;
3244	}
3245	memcpy(pbBounceBuf + cbAlreadyRead,
3246	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3247	cbPayloadReq - cbAlreadyRead);
3248	}
3249	*pcbAlreadyRead = cbPayloadReq;
3250	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3251	return pbBounceBuf;
3252	}
3253
3254
3255	/**
3256	* Sends cursor position and visibility information from the FIFO to the front-end.
3257	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3258	*/
3259	static uint32_t
3260	vmsvgaR3FifoUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3261	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3262	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3263	{
3264	/*
3265	* Check if the cursor update counter has changed and try get a stable
3266	* set of values if it has. This is race-prone, especially consindering
3267	* the screen ID, but little we can do about that.
3268	*/
3269	uint32_t x, y, fVisible, idScreen;
3270	for (uint32_t i = 0; ; i++)
3271	{
3272	x = pFIFO[SVGA_FIFO_CURSOR_X];
3273	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3274	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3275	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3276	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3277	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3278	\|\| i > 3)
3279	break;
3280	if (i == 0)
3281	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3282	ASMNopPause();
3283	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3284	}
3285
3286	/*
3287	* Check if anything has changed, as calling into pDrv is not light-weight.
3288	*/
3289	if ( *pxLast == x
3290	&& *pyLast == y
3291	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3292	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3293	else
3294	{
3295	/*
3296	* Detected changes.
3297	*
3298	* We handle global, not per-screen visibility information by sending
3299	* pfnVBVAMousePointerShape without shape data.
3300	*/
3301	*pxLast = x;
3302	*pyLast = y;
3303	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3304	if (idScreen != SVGA_ID_INVALID)
3305	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3306	else if (*pfLastVisible != fVisible)
3307	{
3308	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3309	*pfLastVisible = fVisible;
3310	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3311	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3312	}
3313	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3314	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3315	}
3316
3317	/*
3318	* Update done. Signal this to the guest.
3319	*/
3320	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3321
3322	return uCursorUpdateCount;
3323	}
3324
3325
3326	/**
3327	* Checks if there is work to be done, either cursor updating or FIFO commands.
3328	*
3329	* @returns true if pending work, false if not.
3330	* @param pFIFO The FIFO to examine.
3331	* @param uLastCursorCount The last cursor update counter value.
3332	*/
3333	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3334	{
3335	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3336	return true;
3337
3338	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3339	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3340	return true;
3341
3342	return false;
3343	}
3344
3345
3346	/**
3347	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3348	*
3349	* @param pThis The VGA state.
3350	*/
3351	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis)
3352	{
3353	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3354	to recheck it before doing the signalling. */
3355	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3356	AssertReturnVoid(pFIFO);
3357	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3358	&& pThis->svga.fFIFOThreadSleeping)
3359	{
3360	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3361	AssertRC(rc);
3362	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3363	}
3364	}
3365
3366
3367	/**
3368	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3369	*/
3370	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3371	{
3372	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3373	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3374	int rc;
3375
3376	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3377	return VINF_SUCCESS;
3378
3379	/*
3380	* Special mode where we only execute an external command and the go back
3381	* to being suspended. Currently, all ext cmds ends up here, with the reset
3382	* one also being eligble for runtime execution further down as well.
3383	*/
3384	if (pThis->svga.fFifoExtCommandWakeup)
3385	{
3386	vmsvgaR3FifoHandleExtCmd(pThis);
3387	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3388	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3389	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3390	else
3391	vmsvgaR3FifoHandleExtCmd(pThis);
3392	return VINF_SUCCESS;
3393	}
3394
3395
3396	/*
3397	* Signal the semaphore to make sure we don't wait for 250ms after a
3398	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3399	*/
3400	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3401
3402	/*
3403	* Allocate a bounce buffer for command we get from the FIFO.
3404	* (All code must return via the end of the function to free this buffer.)
3405	*/
3406	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3407	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3408
3409	/*
3410	* Polling/sleep interval config.
3411	*
3412	* We wait for an a short interval if the guest has recently given us work
3413	* to do, but the interval increases the longer we're kept idle. Once we've
3414	* reached the refresh timer interval, we'll switch to extended waits,
3415	* depending on it or the guest to kick us into action when needed.
3416	*
3417	* Should the refresh time go fishing, we'll just continue increasing the
3418	* sleep length till we reaches the 250 ms max after about 16 seconds.
3419	*/
3420	RTMSINTERVAL const cMsMinSleep = 16;
3421	RTMSINTERVAL const cMsIncSleep = 2;
3422	RTMSINTERVAL const cMsMaxSleep = 250;
3423	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3424	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3425
3426	/*
3427	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3428	*
3429	* Initialize with values that will detect an update from the guest.
3430	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3431	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3432	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3433	*/
3434	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3435	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3436	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3437	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3438	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3439
3440	/*
3441	* The FIFO loop.
3442	*/
3443	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3444	bool fBadOrDisabledFifo = false;
3445	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3446	{
3447	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3448	/*
3449	* Should service the run loop every so often.
3450	*/
3451	if (pThis->svga.f3DEnabled)
3452	vmsvga3dCocoaServiceRunLoop();
3453	# endif
3454
3455	/*
3456	* Unless there's already work pending, go to sleep for a short while.
3457	* (See polling/sleep interval config above.)
3458	*/
3459	if ( fBadOrDisabledFifo
3460	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3461	{
3462	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3463	Assert(pThis->cMilliesRefreshInterval > 0);
3464	if (cMsSleep < pThis->cMilliesRefreshInterval)
3465	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3466	else
3467	{
3468	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3469	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3470	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3471	# endif
3472	if ( !fBadOrDisabledFifo
3473	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3474	rc = VINF_SUCCESS;
3475	else
3476	{
3477	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3478	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3479	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3480	}
3481	}
3482	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3483	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3484	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3485	{
3486	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3487	break;
3488	}
3489	}
3490	else
3491	rc = VINF_SUCCESS;
3492	fBadOrDisabledFifo = false;
3493	if (rc == VERR_TIMEOUT)
3494	{
3495	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3496	{
3497	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3498	continue;
3499	}
3500	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3501
3502	Log(("vmsvgaR3FifoLoop: timeout\n"));
3503	}
3504	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3505	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3506	cMsSleep = cMsMinSleep;
3507
3508	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3509	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3510	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3511
3512	/*
3513	* Handle external commands (currently only reset).
3514	*/
3515	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3516	{
3517	vmsvgaR3FifoHandleExtCmd(pThis);
3518	continue;
3519	}
3520
3521	/*
3522	* The device must be enabled and configured.
3523	*/
3524	if ( !pThis->svga.fEnabled
3525	\|\| !pThis->svga.fConfigured)
3526	{
3527	vmsvgaR3FifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3528	fBadOrDisabledFifo = true;
3529	cMsSleep = cMsMaxSleep; /* cheat */
3530	continue;
3531	}
3532
3533	/*
3534	* Get and check the min/max values. We ASSUME that they will remain
3535	* unchanged while we process requests. A further ASSUMPTION is that
3536	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3537	* we don't read it back while in the loop.
3538	*/
3539	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3540	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3541	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3542	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3543	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3544	\|\| offFifoMax <= offFifoMin
3545	\|\| offFifoMax > pThis->svga.cbFIFO
3546	\|\| (offFifoMax & 3) != 0
3547	\|\| (offFifoMin & 3) != 0
3548	\|\| offCurrentCmd < offFifoMin
3549	\|\| offCurrentCmd > offFifoMax))
3550	{
3551	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3552	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3553	vmsvgaR3FifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3554	fBadOrDisabledFifo = true;
3555	continue;
3556	}
3557	RT_UNTRUSTED_VALIDATED_FENCE();
3558	if (RT_UNLIKELY(offCurrentCmd & 3))
3559	{
3560	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3561	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3562	offCurrentCmd &= ~UINT32_C(3);
3563	}
3564
3565	/*
3566	* Update the cursor position before we start on the FIFO commands.
3567	*/
3568	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3569	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3570	{
3571	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3572	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3573	{ /* halfways likely */ }
3574	else
3575	{
3576	uint32_t const uLastCursorCount = vmsvgaR3FifoUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3577	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3578	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3579	}
3580	}
3581
3582	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3583	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3584	*
3585	* Will break out of the switch on failure.
3586	* Will restart and quit the loop if the thread was requested to stop.
3587	*
3588	* @param a_PtrVar Request variable pointer.
3589	* @param a_Type Request typedef (not pointer) for casting.
3590	* @param a_cbPayloadReq How much payload to fetch.
3591	* @remarks Accesses a bunch of variables in the current scope!
3592	*/
3593	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3594	if (1) { \
3595	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3596	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3597	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3598	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3599	} else do {} while (0)
3600	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3601	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3602	* buffer after figuring out the actual command size.
3603	*
3604	* Will break out of the switch on failure.
3605	*
3606	* @param a_PtrVar Request variable pointer.
3607	* @param a_Type Request typedef (not pointer) for casting.
3608	* @param a_cbPayloadReq How much payload to fetch.
3609	* @remarks Accesses a bunch of variables in the current scope!
3610	*/
3611	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3612	if (1) { \
3613	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3614	} else do {} while (0)
3615
3616	/*
3617	* Mark the FIFO as busy.
3618	*/
3619	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3620	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3621	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3622
3623	/*
3624	* Execute all queued FIFO commands.
3625	* Quit if pending external command or changes in the thread state.
3626	*/
3627	bool fDone = false;
3628	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3629	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3630	{
3631	uint32_t cbPayload = 0;
3632	uint32_t u32IrqStatus = 0;
3633
3634	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3635
3636	/* First check any pending actions. */
3637	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3638	{
3639	vmsvgaR3ChangeMode(pThis);
3640	# ifdef VBOX_WITH_VMSVGA3D
3641	if (pThis->svga.p3dState != NULL)
3642	vmsvga3dChangeMode(pThis);
3643	# endif
3644	}
3645
3646	/* Check for pending external commands (reset). */
3647	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3648	break;
3649
3650	/*
3651	* Process the command.
3652	*/
3653	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3654	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3655	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3656	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3657	switch (enmCmdId)
3658	{
3659	case SVGA_CMD_INVALID_CMD:
3660	/* Nothing to do. */
3661	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3662	break;
3663
3664	case SVGA_CMD_FENCE:
3665	{
3666	SVGAFifoCmdFence *pCmdFence;
3667	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3668	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3669	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3670	{
3671	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3672	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3673
3674	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3675	{
3676	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3677	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3678	}
3679	else
3680	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3681	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3682	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3683	{
3684	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3685	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3686	}
3687	}
3688	else
3689	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3690	break;
3691	}
3692	case SVGA_CMD_UPDATE:
3693	case SVGA_CMD_UPDATE_VERBOSE:
3694	{
3695	SVGAFifoCmdUpdate *pUpdate;
3696	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3697	if (enmCmdId == SVGA_CMD_UPDATE)
3698	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3699	else
3700	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3701	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3702	/** @todo Multiple screens? */
3703	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, 0);
3704	AssertBreak(pScreen);
3705	vmsvgaR3UpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3706	break;
3707	}
3708
3709	case SVGA_CMD_DEFINE_CURSOR:
3710	{
3711	/* Followed by bitmap data. */
3712	SVGAFifoCmdDefineCursor *pCursor;
3713	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3714	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3715
3716	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3717	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3718	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3719	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3720	AssertBreak(pCursor->andMaskDepth <= 32);
3721	AssertBreak(pCursor->xorMaskDepth <= 32);
3722	RT_UNTRUSTED_VALIDATED_FENCE();
3723
3724	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3725	uint32_t cbAndMask = cbAndLine * pCursor->height;
3726	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3727	uint32_t cbXorMask = cbXorLine * pCursor->height;
3728	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3729
3730	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3731	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3732	break;
3733	}
3734
3735	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3736	{
3737	/* Followed by bitmap data. */
3738	uint32_t cbCursorShape, cbAndMask;
3739	uint8_t *pCursorCopy;
3740	uint32_t cbCmd;
3741
3742	SVGAFifoCmdDefineAlphaCursor *pCursor;
3743	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3744	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3745
3746	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3747
3748	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3749	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3750	RT_UNTRUSTED_VALIDATED_FENCE();
3751
3752	/* Refetch the bitmap data as well. */
3753	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3754	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3755	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3756
3757	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3758	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3759	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3760	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3761
3762	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3763	AssertBreak(pCursorCopy);
3764
3765	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3766	memset(pCursorCopy, 0xff, cbAndMask);
3767	/* Colour data */
3768	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3769
3770	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3771	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3772	break;
3773	}
3774
3775	case SVGA_CMD_ESCAPE:
3776	{
3777	/* Followed by nsize bytes of data. */
3778	SVGAFifoCmdEscape *pEscape;
3779	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3780	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3781
3782	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3783	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3784	RT_UNTRUSTED_VALIDATED_FENCE();
3785	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3786	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3787
3788	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3789	{
3790	AssertBreak(pEscape->size >= sizeof(uint32_t));
3791	RT_UNTRUSTED_VALIDATED_FENCE();
3792	uint32_t cmd = (uint32_t )(pEscape + 1);
3793	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3794
3795	switch (cmd)
3796	{
3797	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3798	{
3799	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3800	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3801	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3802
3803	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3804	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3805	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3806
3807	RT_NOREF_PV(pVideoCmd);
3808	break;
3809
3810	}
3811
3812	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3813	{
3814	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3815	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3816	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3817	RT_NOREF_PV(pVideoCmd);
3818	break;
3819	}
3820
3821	default:
3822	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3823	break;
3824	}
3825	}
3826	else
3827	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3828
3829	break;
3830	}
3831	# ifdef VBOX_WITH_VMSVGA3D
3832	case SVGA_CMD_DEFINE_GMR2:
3833	{
3834	SVGAFifoCmdDefineGMR2 *pCmd;
3835	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3836	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3837	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3838
3839	/* Validate current GMR id. */
3840	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3841	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3842	RT_UNTRUSTED_VALIDATED_FENCE();
3843
3844	if (!pCmd->numPages)
3845	{
3846	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3847	vmsvgaR3GmrFree(pThis, pCmd->gmrId);
3848	}
3849	else
3850	{
3851	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3852	if (pGMR->cMaxPages)
3853	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3854
3855	/* Not sure if we should always free the descriptor, but for simplicity
3856	we do so if the new size is smaller than the current. */
3857	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3858	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3859	vmsvgaR3GmrFree(pThis, pCmd->gmrId);
3860
3861	pGMR->cMaxPages = pCmd->numPages;
3862	/* The rest is done by the REMAP_GMR2 command. */
3863	}
3864	break;
3865	}
3866
3867	case SVGA_CMD_REMAP_GMR2:
3868	{
3869	/* Followed by page descriptors or guest ptr. */
3870	SVGAFifoCmdRemapGMR2 *pCmd;
3871	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3872	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3873
3874	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3875	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3876	RT_UNTRUSTED_VALIDATED_FENCE();
3877
3878	/* Calculate the size of what comes after next and fetch it. */
3879	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3880	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3881	cbCmd += sizeof(SVGAGuestPtr);
3882	else
3883	{
3884	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3885	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3886	{
3887	cbCmd += cbPageDesc;
3888	pCmd->numPages = 1;
3889	}
3890	else
3891	{
3892	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3893	cbCmd += cbPageDesc * pCmd->numPages;
3894	}
3895	}
3896	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3897
3898	/* Validate current GMR id and size. */
3899	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3900	RT_UNTRUSTED_VALIDATED_FENCE();
3901	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3902	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3903	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3904	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3905
3906	if (pCmd->numPages == 0)
3907	break;
3908
3909	/** @todo Move to a separate function vmsvgaGMRRemap() */
3910
3911	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3912	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3913
3914	/*
3915	* We flatten the existing descriptors into a page array, overwrite the
3916	* pages specified in this command and then recompress the descriptor.
3917	*/
3918	/** @todo Optimize the GMR remap algorithm! */
3919
3920	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3921	uint64_t *paNewPage64 = NULL;
3922	if (pGMR->paDesc)
3923	{
3924	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3925
3926	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3927	AssertBreak(paNewPage64);
3928
3929	uint32_t idxPage = 0;
3930	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3931	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3932	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3933	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3934	RT_UNTRUSTED_VALIDATED_FENCE();
3935	}
3936
3937	/* Free the old GMR if present. */
3938	if (pGMR->paDesc)
3939	RTMemFree(pGMR->paDesc);
3940
3941	/* Allocate the maximum amount possible (everything non-continuous) */
3942	PVMSVGAGMRDESCRIPTOR paDescs;
3943	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3944	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3945
3946	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3947	{
3948	/** @todo */
3949	AssertFailed();
3950	pGMR->numDescriptors = 0;
3951	}
3952	else
3953	{
3954	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3955	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3956	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3957
3958	if (paNewPage64)
3959	{
3960	/* Overwrite the old page array with the new page values. */
3961	if (fGCPhys64)
3962	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3963	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3964	else
3965	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3966	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3967
3968	/* Use the updated page array instead of the command data. */
3969	fGCPhys64 = true;
3970	paPages64 = paNewPage64;
3971	pCmd->numPages = cNewTotalPages;
3972	}
3973
3974	/* The first page. */
3975	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3976	* applied to paNewPage64. */
3977	RTGCPHYS GCPhys;
3978	if (fGCPhys64)
3979	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3980	else
3981	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3982	paDescs[0].GCPhys = GCPhys;
3983	paDescs[0].numPages = 1;
3984
3985	/* Subsequent pages. */
3986	uint32_t iDescriptor = 0;
3987	for (uint32_t i = 1; i < pCmd->numPages; i++)
3988	{
3989	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3990	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3991	else
3992	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3993
3994	/* Continuous physical memory? */
3995	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3996	{
3997	Assert(paDescs[iDescriptor].numPages);
3998	paDescs[iDescriptor].numPages++;
3999	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4000	}
4001	else
4002	{
4003	iDescriptor++;
4004	paDescs[iDescriptor].GCPhys = GCPhys;
4005	paDescs[iDescriptor].numPages = 1;
4006	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4007	}
4008	}
4009
4010	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4011	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4012	pGMR->numDescriptors = iDescriptor + 1;
4013	}
4014
4015	if (paNewPage64)
4016	RTMemFree(paNewPage64);
4017
4018	# ifdef DEBUG_GMR_ACCESS
4019	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pThis->pDevInsR3, pCmd->gmrId);
4020	# endif
4021	break;
4022	}
4023	# endif // VBOX_WITH_VMSVGA3D
4024	case SVGA_CMD_DEFINE_SCREEN:
4025	{
4026	/* The size of this command is specified by the guest and depends on capabilities. */
4027	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4028
4029	SVGAFifoCmdDefineScreen *pCmd;
4030	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4031	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4032	RT_UNTRUSTED_VALIDATED_FENCE();
4033
4034	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4035	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4036	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4037
4038	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4039	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4040	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4041
4042	uint32_t const idScreen = pCmd->screen.id;
4043	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4044
4045	uint32_t const uWidth = pCmd->screen.size.width;
4046	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4047
4048	uint32_t const uHeight = pCmd->screen.size.height;
4049	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4050
4051	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4052	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4053	AssertBreak(cbWidth <= cbPitch);
4054
4055	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4056	AssertBreak(uScreenOffset < pThis->vram_size);
4057
4058	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4059	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4060	AssertBreak( (uHeight == 0 && cbPitch == 0)
4061	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4062	RT_UNTRUSTED_VALIDATED_FENCE();
4063
4064	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4065
4066	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4067
4068	pScreen->fDefined = true;
4069	pScreen->fModified = true;
4070	pScreen->fuScreen = pCmd->screen.flags;
4071	pScreen->idScreen = idScreen;
4072	if (!fBlank)
4073	{
4074	AssertBreak(uWidth > 0 && uHeight > 0);
4075
4076	pScreen->xOrigin = pCmd->screen.root.x;
4077	pScreen->yOrigin = pCmd->screen.root.y;
4078	pScreen->cWidth = uWidth;
4079	pScreen->cHeight = uHeight;
4080	pScreen->offVRAM = uScreenOffset;
4081	pScreen->cbPitch = cbPitch;
4082	pScreen->cBpp = 32;
4083	}
4084	else
4085	{
4086	/* Keep old values. */
4087	}
4088
4089	pThis->svga.fGFBRegisters = false;
4090	vmsvgaR3ChangeMode(pThis);
4091	break;
4092	}
4093
4094	case SVGA_CMD_DESTROY_SCREEN:
4095	{
4096	SVGAFifoCmdDestroyScreen *pCmd;
4097	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4098	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4099
4100	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4101
4102	uint32_t const idScreen = pCmd->screenId;
4103	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4104	RT_UNTRUSTED_VALIDATED_FENCE();
4105
4106	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4107	pScreen->fModified = true;
4108	pScreen->fDefined = false;
4109	pScreen->idScreen = idScreen;
4110
4111	vmsvgaR3ChangeMode(pThis);
4112	break;
4113	}
4114
4115	case SVGA_CMD_DEFINE_GMRFB:
4116	{
4117	SVGAFifoCmdDefineGMRFB *pCmd;
4118	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4119	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4120
4121	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4122	pSVGAState->GMRFB.ptr = pCmd->ptr;
4123	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4124	pSVGAState->GMRFB.format = pCmd->format;
4125	break;
4126	}
4127
4128	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4129	{
4130	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4131	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4132	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4133
4134	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4135	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4136
4137	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4138	RT_UNTRUSTED_VALIDATED_FENCE();
4139
4140	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, pCmd->destScreenId);
4141	AssertBreak(pScreen);
4142
4143	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4144	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4145
4146	/* Clip destRect to the screen dimensions. */
4147	SVGASignedRect screenRect;
4148	screenRect.left = 0;
4149	screenRect.top = 0;
4150	screenRect.right = pScreen->cWidth;
4151	screenRect.bottom = pScreen->cHeight;
4152	SVGASignedRect clipRect = pCmd->destRect;
4153	vmsvgaR3ClipRect(&screenRect, &clipRect);
4154	RT_UNTRUSTED_VALIDATED_FENCE();
4155
4156	uint32_t const width = clipRect.right - clipRect.left;
4157	uint32_t const height = clipRect.bottom - clipRect.top;
4158
4159	if ( width == 0
4160	\|\| height == 0)
4161	break; /* Nothing to do. */
4162
4163	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4164	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4165
4166	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4167	* Prepare parameters for vmsvgaR3GmrTransfer.
4168	*/
4169	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4170
4171	/* Destination: host buffer which describes the screen 0 VRAM.
4172	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4173	*/
4174	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4175	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4176	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4177	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4178	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4179	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4180	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4181	+ cbScanline * clipRect.top;
4182	int32_t const cbHstPitch = cbScanline;
4183
4184	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4185	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4186	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4187	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4188	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4189
4190	rc = vmsvgaR3GmrTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4191	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4192	gstPtr, offGst, cbGstPitch,
4193	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4194	AssertRC(rc);
4195	vmsvgaR3UpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4196	break;
4197	}
4198
4199	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4200	{
4201	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4202	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4203	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4204
4205	/* Note! This can fetch 3d render results as well!! */
4206	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4207	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4208
4209	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4210	RT_UNTRUSTED_VALIDATED_FENCE();
4211
4212	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, pCmd->srcScreenId);
4213	AssertBreak(pScreen);
4214
4215	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4216	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4217
4218	/* Clip destRect to the screen dimensions. */
4219	SVGASignedRect screenRect;
4220	screenRect.left = 0;
4221	screenRect.top = 0;
4222	screenRect.right = pScreen->cWidth;
4223	screenRect.bottom = pScreen->cHeight;
4224	SVGASignedRect clipRect = pCmd->srcRect;
4225	vmsvgaR3ClipRect(&screenRect, &clipRect);
4226	RT_UNTRUSTED_VALIDATED_FENCE();
4227
4228	uint32_t const width = clipRect.right - clipRect.left;
4229	uint32_t const height = clipRect.bottom - clipRect.top;
4230
4231	if ( width == 0
4232	\|\| height == 0)
4233	break; /* Nothing to do. */
4234
4235	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4236	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4237
4238	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4239	* Prepare parameters for vmsvgaR3GmrTransfer.
4240	*/
4241	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4242
4243	/* Source: host buffer which describes the screen 0 VRAM.
4244	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4245	*/
4246	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4247	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4248	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4249	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4250	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4251	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4252	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4253	+ cbScanline * clipRect.top;
4254	int32_t const cbHstPitch = cbScanline;
4255
4256	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4257	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4258	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4259	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4260	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4261
4262	rc = vmsvgaR3GmrTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4263	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4264	gstPtr, offGst, cbGstPitch,
4265	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4266	AssertRC(rc);
4267	break;
4268	}
4269
4270	case SVGA_CMD_ANNOTATION_FILL:
4271	{
4272	SVGAFifoCmdAnnotationFill *pCmd;
4273	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4274	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4275
4276	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4277	pSVGAState->colorAnnotation = pCmd->color;
4278	break;
4279	}
4280
4281	case SVGA_CMD_ANNOTATION_COPY:
4282	{
4283	SVGAFifoCmdAnnotationCopy *pCmd;
4284	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4285	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4286
4287	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4288	AssertFailed();
4289	break;
4290	}
4291
4292	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4293
4294	default:
4295	# ifdef VBOX_WITH_VMSVGA3D
4296	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4297	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4298	{
4299	RT_UNTRUSTED_VALIDATED_FENCE();
4300
4301	/* All 3d commands start with a common header, which defines the size of the command. */
4302	SVGA3dCmdHeader *pHdr;
4303	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4304	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4305	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4306	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4307
4308	if (RT_LIKELY(pThis->svga.f3DEnabled))
4309	{ /* likely */ }
4310	else
4311	{
4312	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4313	break;
4314	}
4315
4316	/**
4317	* Check that the 3D command has at least a_cbMin of payload bytes after the
4318	* header. Will break out of the switch if it doesn't.
4319	*/
4320	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4321	if (1) { \
4322	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4323	RT_UNTRUSTED_VALIDATED_FENCE(); \
4324	} else do {} while (0)
4325	switch ((int)enmCmdId)
4326	{
4327	case SVGA_3D_CMD_SURFACE_DEFINE:
4328	{
4329	uint32_t cMipLevels;
4330	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4331	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4332	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4333
4334	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4335	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4336	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4337	# ifdef DEBUG_GMR_ACCESS
4338	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4339	# endif
4340	break;
4341	}
4342
4343	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4344	{
4345	uint32_t cMipLevels;
4346	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4347	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4348	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4349
4350	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4351	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4352	pCmd->multisampleCount, pCmd->autogenFilter,
4353	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4354	break;
4355	}
4356
4357	case SVGA_3D_CMD_SURFACE_DESTROY:
4358	{
4359	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4360	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4361	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4362	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4363	break;
4364	}
4365
4366	case SVGA_3D_CMD_SURFACE_COPY:
4367	{
4368	uint32_t cCopyBoxes;
4369	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4370	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4371	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4372
4373	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4374	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4375	break;
4376	}
4377
4378	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4379	{
4380	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4381	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4382	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4383
4384	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4385	break;
4386	}
4387
4388	case SVGA_3D_CMD_SURFACE_DMA:
4389	{
4390	uint32_t cCopyBoxes;
4391	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4392	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4393	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4394
4395	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4396	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4397	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4398	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4399	break;
4400	}
4401
4402	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4403	{
4404	uint32_t cRects;
4405	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4406	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4407	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4408
4409	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4410	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4411	break;
4412	}
4413
4414	case SVGA_3D_CMD_CONTEXT_DEFINE:
4415	{
4416	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4417	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4418	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4419
4420	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4421	break;
4422	}
4423
4424	case SVGA_3D_CMD_CONTEXT_DESTROY:
4425	{
4426	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4427	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4428	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4429
4430	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4431	break;
4432	}
4433
4434	case SVGA_3D_CMD_SETTRANSFORM:
4435	{
4436	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4437	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4438	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4439
4440	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4441	break;
4442	}
4443
4444	case SVGA_3D_CMD_SETZRANGE:
4445	{
4446	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4447	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4448	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4449
4450	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4451	break;
4452	}
4453
4454	case SVGA_3D_CMD_SETRENDERSTATE:
4455	{
4456	uint32_t cRenderStates;
4457	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4458	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4459	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4460
4461	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4462	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4463	break;
4464	}
4465
4466	case SVGA_3D_CMD_SETRENDERTARGET:
4467	{
4468	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4469	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4470	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4471
4472	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4473	break;
4474	}
4475
4476	case SVGA_3D_CMD_SETTEXTURESTATE:
4477	{
4478	uint32_t cTextureStates;
4479	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4480	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4481	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4482
4483	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4484	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4485	break;
4486	}
4487
4488	case SVGA_3D_CMD_SETMATERIAL:
4489	{
4490	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4491	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4492	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4493
4494	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4495	break;
4496	}
4497
4498	case SVGA_3D_CMD_SETLIGHTDATA:
4499	{
4500	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4501	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4502	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4503
4504	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4505	break;
4506	}
4507
4508	case SVGA_3D_CMD_SETLIGHTENABLED:
4509	{
4510	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4511	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4512	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4513
4514	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4515	break;
4516	}
4517
4518	case SVGA_3D_CMD_SETVIEWPORT:
4519	{
4520	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4521	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4522	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4523
4524	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4525	break;
4526	}
4527
4528	case SVGA_3D_CMD_SETCLIPPLANE:
4529	{
4530	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4531	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4532	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4533
4534	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4535	break;
4536	}
4537
4538	case SVGA_3D_CMD_CLEAR:
4539	{
4540	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4541	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4542	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4543
4544	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4545	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4546	break;
4547	}
4548
4549	case SVGA_3D_CMD_PRESENT:
4550	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4551	{
4552	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4553	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4554	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4555	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4556	else
4557	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4558
4559	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4560
4561	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4562	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4563	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4564	break;
4565	}
4566
4567	case SVGA_3D_CMD_SHADER_DEFINE:
4568	{
4569	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4570	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4571	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4572
4573	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4574	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4575	break;
4576	}
4577
4578	case SVGA_3D_CMD_SHADER_DESTROY:
4579	{
4580	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4581	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4582	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4583
4584	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4585	break;
4586	}
4587
4588	case SVGA_3D_CMD_SET_SHADER:
4589	{
4590	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4591	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4592	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4593
4594	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4595	break;
4596	}
4597
4598	case SVGA_3D_CMD_SET_SHADER_CONST:
4599	{
4600	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4601	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4602	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4603
4604	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4605	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4606	break;
4607	}
4608
4609	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4610	{
4611	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4612	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4613	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4614
4615	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4616	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4617	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4618	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4619	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4620
4621	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4622	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4623
4624	RT_UNTRUSTED_VALIDATED_FENCE();
4625
4626	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4627	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4628	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4629
4630	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4631	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4632	pNumRange, cVertexDivisor, pVertexDivisor);
4633	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4634	break;
4635	}
4636
4637	case SVGA_3D_CMD_SETSCISSORRECT:
4638	{
4639	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4640	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4641	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4642
4643	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4644	break;
4645	}
4646
4647	case SVGA_3D_CMD_BEGIN_QUERY:
4648	{
4649	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4650	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4651	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4652
4653	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4654	break;
4655	}
4656
4657	case SVGA_3D_CMD_END_QUERY:
4658	{
4659	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4660	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4661	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4662
4663	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4664	break;
4665	}
4666
4667	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4668	{
4669	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4670	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4671	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4672
4673	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4674	break;
4675	}
4676
4677	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4678	{
4679	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4680	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4681	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4682
4683	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4684	break;
4685	}
4686
4687	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4688	/* context id + surface id? */
4689	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4690	break;
4691	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4692	/* context id + surface id? */
4693	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4694	break;
4695
4696	default:
4697	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4698	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4699	break;
4700	}
4701	}
4702	else
4703	# endif // VBOX_WITH_VMSVGA3D
4704	{
4705	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4706	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4707	}
4708	}
4709
4710	/* Go to the next slot */
4711	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4712	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4713	if (offCurrentCmd >= offFifoMax)
4714	{
4715	offCurrentCmd -= offFifoMax - offFifoMin;
4716	Assert(offCurrentCmd >= offFifoMin);
4717	Assert(offCurrentCmd < offFifoMax);
4718	}
4719	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4720	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4721
4722	/*
4723	* Raise IRQ if required. Must enter the critical section here
4724	* before making final decisions here, otherwise cubebench and
4725	* others may end up waiting forever.
4726	*/
4727	if ( u32IrqStatus
4728	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4729	{
4730	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4731	AssertRC(rc2);
4732
4733	/* FIFO progress might trigger an interrupt. */
4734	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4735	{
4736	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4737	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4738	}
4739
4740	/* Unmasked IRQ pending? */
4741	if (pThis->svga.u32IrqMask & u32IrqStatus)
4742	{
4743	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4744	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4745	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4746	}
4747
4748	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4749	}
4750	}
4751
4752	/* If really done, clear the busy flag. */
4753	if (fDone)
4754	{
4755	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4756	vmsvgaR3FifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4757	}
4758	}
4759
4760	/*
4761	* Free the bounce buffer. (There are no returns above!)
4762	*/
4763	RTMemFree(pbBounceBuf);
4764
4765	return VINF_SUCCESS;
4766	}
4767
4768	/**
4769	* Free the specified GMR
4770	*
4771	* @param pThis VGA device instance data.
4772	* @param idGMR GMR id
4773	*/
4774	void vmsvgaR3GmrFree(PVGASTATE pThis, uint32_t idGMR)
4775	{
4776	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4777
4778	/* Free the old descriptor if present. */
4779	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4780	if ( pGMR->numDescriptors
4781	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4782	{
4783	# ifdef DEBUG_GMR_ACCESS
4784	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pThis->pDevInsR3, idGMR);
4785	# endif
4786
4787	Assert(pGMR->paDesc);
4788	RTMemFree(pGMR->paDesc);
4789	pGMR->paDesc = NULL;
4790	pGMR->numDescriptors = 0;
4791	pGMR->cbTotal = 0;
4792	pGMR->cMaxPages = 0;
4793	}
4794	Assert(!pGMR->cMaxPages);
4795	Assert(!pGMR->cbTotal);
4796	}
4797
4798	/**
4799	* Copy between a GMR and a host memory buffer.
4800	*
4801	* @returns VBox status code.
4802	* @param pThis VGA device instance data.
4803	* @param enmTransferType Transfer type (read/write)
4804	* @param pbHstBuf Host buffer pointer (valid)
4805	* @param cbHstBuf Size of host buffer (valid)
4806	* @param offHst Host buffer offset of the first scanline
4807	* @param cbHstPitch Destination buffer pitch
4808	* @param gstPtr GMR description
4809	* @param offGst Guest buffer offset of the first scanline
4810	* @param cbGstPitch Guest buffer pitch
4811	* @param cbWidth Width in bytes to copy
4812	* @param cHeight Number of scanllines to copy
4813	*/
4814	int vmsvgaR3GmrTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4815	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4816	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4817	uint32_t cbWidth, uint32_t cHeight)
4818	{
4819	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4820	int rc;
4821
4822	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4823	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4824	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4825	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4826	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4827
4828	PGMR pGMR;
4829	uint32_t cbGmr; /* The GMR size in bytes. */
4830	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4831	{
4832	pGMR = NULL;
4833	cbGmr = pThis->vram_size;
4834	}
4835	else
4836	{
4837	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4838	RT_UNTRUSTED_VALIDATED_FENCE();
4839	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4840	cbGmr = pGMR->cbTotal;
4841	}
4842
4843	/*
4844	* GMR
4845	*/
4846	/* Calculate GMR offset of the data to be copied. */
4847	AssertMsgReturn(gstPtr.offset < cbGmr,
4848	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4849	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4850	VERR_INVALID_PARAMETER);
4851	RT_UNTRUSTED_VALIDATED_FENCE();
4852	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4853	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4854	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4855	VERR_INVALID_PARAMETER);
4856	RT_UNTRUSTED_VALIDATED_FENCE();
4857	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4858
4859	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4860	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4861	AssertMsgReturn(cbGmrScanline != 0,
4862	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4863	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4864	VERR_INVALID_PARAMETER);
4865	RT_UNTRUSTED_VALIDATED_FENCE();
4866	AssertMsgReturn(cbWidth <= cbGmrScanline,
4867	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4868	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4869	VERR_INVALID_PARAMETER);
4870	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4871	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4872	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4873	VERR_INVALID_PARAMETER);
4874	RT_UNTRUSTED_VALIDATED_FENCE();
4875
4876	/* How many bytes are available for the data in the GMR. */
4877	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4878
4879	/* How many scanlines would fit into the available data. */
4880	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4881	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4882	if (cbWidth <= cbGmrLastScanline)
4883	++cGmrScanlines;
4884
4885	if (cHeight > cGmrScanlines)
4886	cHeight = cGmrScanlines;
4887
4888	AssertMsgReturn(cHeight > 0,
4889	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4890	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4891	VERR_INVALID_PARAMETER);
4892	RT_UNTRUSTED_VALIDATED_FENCE();
4893
4894	/*
4895	* Host buffer.
4896	*/
4897	AssertMsgReturn(offHst < cbHstBuf,
4898	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4899	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4900	VERR_INVALID_PARAMETER);
4901
4902	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4903	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4904	AssertMsgReturn(cbHstScanline != 0,
4905	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4906	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4907	VERR_INVALID_PARAMETER);
4908	AssertMsgReturn(cbWidth <= cbHstScanline,
4909	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4910	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4911	VERR_INVALID_PARAMETER);
4912	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4913	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4914	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4915	VERR_INVALID_PARAMETER);
4916
4917	/* How many bytes are available for the data in the buffer. */
4918	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4919
4920	/* How many scanlines would fit into the available data. */
4921	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4922	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4923	if (cbWidth <= cbHstLastScanline)
4924	++cHstScanlines;
4925
4926	if (cHeight > cHstScanlines)
4927	cHeight = cHstScanlines;
4928
4929	AssertMsgReturn(cHeight > 0,
4930	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4931	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4932	VERR_INVALID_PARAMETER);
4933
4934	uint8_t *pbHst = pbHstBuf + offHst;
4935
4936	/* Shortcut for the framebuffer. */
4937	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4938	{
4939	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4940
4941	uint8_t const *pbSrc;
4942	int32_t cbSrcPitch;
4943	uint8_t *pbDst;
4944	int32_t cbDstPitch;
4945
4946	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4947	{
4948	pbSrc = pbHst;
4949	cbSrcPitch = cbHstPitch;
4950	pbDst = pbGst;
4951	cbDstPitch = cbGstPitch;
4952	}
4953	else
4954	{
4955	pbSrc = pbGst;
4956	cbSrcPitch = cbGstPitch;
4957	pbDst = pbHst;
4958	cbDstPitch = cbHstPitch;
4959	}
4960
4961	if ( cbWidth == (uint32_t)cbGstPitch
4962	&& cbGstPitch == cbHstPitch)
4963	{
4964	/* Entire scanlines, positive pitch. */
4965	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4966	}
4967	else
4968	{
4969	for (uint32_t i = 0; i < cHeight; ++i)
4970	{
4971	memcpy(pbDst, pbSrc, cbWidth);
4972
4973	pbDst += cbDstPitch;
4974	pbSrc += cbSrcPitch;
4975	}
4976	}
4977	return VINF_SUCCESS;
4978	}
4979
4980	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4981	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4982
4983	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4984	uint32_t iDesc = 0; /* Index in the descriptor array. */
4985	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4986	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4987	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4988	for (uint32_t i = 0; i < cHeight; ++i)
4989	{
4990	uint32_t cbCurrentWidth = cbWidth;
4991	uint32_t offGmrCurrent = offGmrScanline;
4992	uint8_t *pbCurrentHost = pbHstScanline;
4993
4994	/* Find the right descriptor */
4995	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4996	{
4997	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4998	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4999	++iDesc;
5000	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5001	}
5002
5003	while (cbCurrentWidth)
5004	{
5005	uint32_t cbToCopy;
5006
5007	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5008	{
5009	cbToCopy = cbCurrentWidth;
5010	}
5011	else
5012	{
5013	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5014	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5015	}
5016
5017	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5018
5019	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5020
5021	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5022	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5023	else
5024	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5025	AssertRCBreak(rc);
5026
5027	cbCurrentWidth -= cbToCopy;
5028	offGmrCurrent += cbToCopy;
5029	pbCurrentHost += cbToCopy;
5030
5031	/* Go to the next descriptor if there's anything left. */
5032	if (cbCurrentWidth)
5033	{
5034	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5035	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5036	++iDesc;
5037	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5038	}
5039	}
5040
5041	offGmrScanline += cbGstPitch;
5042	pbHstScanline += cbHstPitch;
5043	}
5044
5045	return VINF_SUCCESS;
5046	}
5047
5048
5049	/**
5050	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5051	*
5052	* @param pSizeSrc Source surface dimensions.
5053	* @param pSizeDest Destination surface dimensions.
5054	* @param pBox Coordinates to be clipped.
5055	*/
5056	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5057	{
5058	/* Src x, w */
5059	if (pBox->srcx > pSizeSrc->width)
5060	pBox->srcx = pSizeSrc->width;
5061	if (pBox->w > pSizeSrc->width - pBox->srcx)
5062	pBox->w = pSizeSrc->width - pBox->srcx;
5063
5064	/* Src y, h */
5065	if (pBox->srcy > pSizeSrc->height)
5066	pBox->srcy = pSizeSrc->height;
5067	if (pBox->h > pSizeSrc->height - pBox->srcy)
5068	pBox->h = pSizeSrc->height - pBox->srcy;
5069
5070	/* Src z, d */
5071	if (pBox->srcz > pSizeSrc->depth)
5072	pBox->srcz = pSizeSrc->depth;
5073	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5074	pBox->d = pSizeSrc->depth - pBox->srcz;
5075
5076	/* Dest x, w */
5077	if (pBox->x > pSizeDest->width)
5078	pBox->x = pSizeDest->width;
5079	if (pBox->w > pSizeDest->width - pBox->x)
5080	pBox->w = pSizeDest->width - pBox->x;
5081
5082	/* Dest y, h */
5083	if (pBox->y > pSizeDest->height)
5084	pBox->y = pSizeDest->height;
5085	if (pBox->h > pSizeDest->height - pBox->y)
5086	pBox->h = pSizeDest->height - pBox->y;
5087
5088	/* Dest z, d */
5089	if (pBox->z > pSizeDest->depth)
5090	pBox->z = pSizeDest->depth;
5091	if (pBox->d > pSizeDest->depth - pBox->z)
5092	pBox->d = pSizeDest->depth - pBox->z;
5093	}
5094
5095	/**
5096	* Unsigned coordinates in pBox. Clip to [0; pSize).
5097	*
5098	* @param pSize Source surface dimensions.
5099	* @param pBox Coordinates to be clipped.
5100	*/
5101	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5102	{
5103	/* x, w */
5104	if (pBox->x > pSize->width)
5105	pBox->x = pSize->width;
5106	if (pBox->w > pSize->width - pBox->x)
5107	pBox->w = pSize->width - pBox->x;
5108
5109	/* y, h */
5110	if (pBox->y > pSize->height)
5111	pBox->y = pSize->height;
5112	if (pBox->h > pSize->height - pBox->y)
5113	pBox->h = pSize->height - pBox->y;
5114
5115	/* z, d */
5116	if (pBox->z > pSize->depth)
5117	pBox->z = pSize->depth;
5118	if (pBox->d > pSize->depth - pBox->z)
5119	pBox->d = pSize->depth - pBox->z;
5120	}
5121
5122	/**
5123	* Clip.
5124	*
5125	* @param pBound Bounding rectangle.
5126	* @param pRect Rectangle to be clipped.
5127	*/
5128	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5129	{
5130	int32_t left;
5131	int32_t top;
5132	int32_t right;
5133	int32_t bottom;
5134
5135	/* Right order. */
5136	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5137	if (pRect->left < pRect->right)
5138	{
5139	left = pRect->left;
5140	right = pRect->right;
5141	}
5142	else
5143	{
5144	left = pRect->right;
5145	right = pRect->left;
5146	}
5147	if (pRect->top < pRect->bottom)
5148	{
5149	top = pRect->top;
5150	bottom = pRect->bottom;
5151	}
5152	else
5153	{
5154	top = pRect->bottom;
5155	bottom = pRect->top;
5156	}
5157
5158	if (left < pBound->left)
5159	left = pBound->left;
5160	if (right < pBound->left)
5161	right = pBound->left;
5162
5163	if (left > pBound->right)
5164	left = pBound->right;
5165	if (right > pBound->right)
5166	right = pBound->right;
5167
5168	if (top < pBound->top)
5169	top = pBound->top;
5170	if (bottom < pBound->top)
5171	bottom = pBound->top;
5172
5173	if (top > pBound->bottom)
5174	top = pBound->bottom;
5175	if (bottom > pBound->bottom)
5176	bottom = pBound->bottom;
5177
5178	pRect->left = left;
5179	pRect->right = right;
5180	pRect->top = top;
5181	pRect->bottom = bottom;
5182	}
5183
5184	/**
5185	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5186	* Unblock the FIFO I/O thread so it can respond to a state change.}
5187	*/
5188	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5189	{
5190	RT_NOREF(pDevIns);
5191	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5192	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5193	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5194	}
5195
5196	/**
5197	* Enables or disables dirty page tracking for the framebuffer
5198	*
5199	* @param pThis VGA device instance data.
5200	* @param fTraces Enable/disable traces
5201	*/
5202	static void vmsvgaR3SetTraces(PVGASTATE pThis, bool fTraces)
5203	{
5204	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5205	&& !fTraces)
5206	{
5207	//Assert(pThis->svga.fTraces);
5208	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5209	return;
5210	}
5211
5212	pThis->svga.fTraces = fTraces;
5213	if (pThis->svga.fTraces)
5214	{
5215	unsigned cbFrameBuffer = pThis->vram_size;
5216
5217	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5218	/** @todo How does this work with screens? */
5219	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5220	{
5221	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5222	Assert(pThis->svga.cbScanline);
5223	# endif
5224	/* Hardware enabled; return real framebuffer size .*/
5225	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5226	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5227	}
5228
5229	if (!pThis->svga.fVRAMTracking)
5230	{
5231	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5232	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5233	pThis->svga.fVRAMTracking = true;
5234	}
5235	}
5236	else
5237	{
5238	if (pThis->svga.fVRAMTracking)
5239	{
5240	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5241	vgaR3UnregisterVRAMHandler(pThis);
5242	pThis->svga.fVRAMTracking = false;
5243	}
5244	}
5245	}
5246
5247	/**
5248	* @callback_method_impl{FNPCIIOREGIONMAP}
5249	*/
5250	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5251	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5252	{
5253	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5254	int rc;
5255	RT_NOREF(pPciDev);
5256	Assert(pPciDev == pDevIns->apPciDevs[0]);
5257
5258	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5259	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5260	if (GCPhysAddress != NIL_RTGCPHYS)
5261	{
5262	/*
5263	* Mapping the FIFO RAM.
5264	*/
5265	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5266	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5267	AssertRC(rc);
5268
5269	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5270	if (RT_SUCCESS(rc))
5271	{
5272	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5273	# ifdef DEBUG_FIFO_ACCESS
5274	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5275	# else
5276	GCPhysAddress + PAGE_SIZE - 1,
5277	# endif
5278	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5279	"VMSVGA FIFO");
5280	AssertRC(rc);
5281	}
5282	# endif
5283	if (RT_SUCCESS(rc))
5284	{
5285	pThis->svga.GCPhysFIFO = GCPhysAddress;
5286	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5287	}
5288	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5289	}
5290	else
5291	{
5292	Assert(pThis->svga.GCPhysFIFO);
5293	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5294	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5295	AssertRC(rc);
5296	# else
5297	rc = VINF_SUCCESS;
5298	# endif
5299	pThis->svga.GCPhysFIFO = 0;
5300	}
5301	return rc;
5302	}
5303
5304	# ifdef VBOX_WITH_VMSVGA3D
5305
5306	/**
5307	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5308	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5309	*
5310	* @param pDevIns The device instance.
5311	* @param pThis The VGA device instance data.
5312	* @param sid Either UINT32_MAX or the ID of a specific
5313	* surface. If UINT32_MAX is used, all surfaces
5314	* are processed.
5315	*/
5316	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid)
5317	{
5318	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5319	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5320	}
5321
5322
5323	/**
5324	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5325	*/
5326	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5327	{
5328	/* There might be a specific surface ID at the start of the
5329	arguments, if not show all surfaces. */
5330	uint32_t sid = UINT32_MAX;
5331	if (pszArgs)
5332	pszArgs = RTStrStripL(pszArgs);
5333	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5334	sid = RTStrToUInt32(pszArgs);
5335
5336	/* Verbose or terse display, we default to verbose. */
5337	bool fVerbose = true;
5338	if (RTStrIStr(pszArgs, "terse"))
5339	fVerbose = false;
5340
5341	/* The size of the ascii art (x direction, y is 3/4 of x). */
5342	uint32_t cxAscii = 80;
5343	if (RTStrIStr(pszArgs, "gigantic"))
5344	cxAscii = 300;
5345	else if (RTStrIStr(pszArgs, "huge"))
5346	cxAscii = 180;
5347	else if (RTStrIStr(pszArgs, "big"))
5348	cxAscii = 132;
5349	else if (RTStrIStr(pszArgs, "normal"))
5350	cxAscii = 80;
5351	else if (RTStrIStr(pszArgs, "medium"))
5352	cxAscii = 64;
5353	else if (RTStrIStr(pszArgs, "small"))
5354	cxAscii = 48;
5355	else if (RTStrIStr(pszArgs, "tiny"))
5356	cxAscii = 24;
5357
5358	/* Y invert the image when producing the ASCII art. */
5359	bool fInvY = false;
5360	if (RTStrIStr(pszArgs, "invy"))
5361	fInvY = true;
5362
5363	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5364	}
5365
5366
5367	/**
5368	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5369	*/
5370	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5371	{
5372	/* pszArg = "sid[>dir]"
5373	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5374	*/
5375	char *pszBitmapPath = NULL;
5376	uint32_t sid = UINT32_MAX;
5377	if (pszArgs)
5378	pszArgs = RTStrStripL(pszArgs);
5379	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5380	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5381	if ( pszBitmapPath
5382	&& *pszBitmapPath == '>')
5383	++pszBitmapPath;
5384
5385	const bool fVerbose = true;
5386	const uint32_t cxAscii = 0; /* No ASCII */
5387	const bool fInvY = false; /* Do not invert. */
5388	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5389	}
5390
5391
5392	/**
5393	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5394	*/
5395	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5396	{
5397	/* There might be a specific surface ID at the start of the
5398	arguments, if not show all contexts. */
5399	uint32_t sid = UINT32_MAX;
5400	if (pszArgs)
5401	pszArgs = RTStrStripL(pszArgs);
5402	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5403	sid = RTStrToUInt32(pszArgs);
5404
5405	/* Verbose or terse display, we default to verbose. */
5406	bool fVerbose = true;
5407	if (RTStrIStr(pszArgs, "terse"))
5408	fVerbose = false;
5409
5410	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5411	}
5412
5413	# endif /* VBOX_WITH_VMSVGA3D */
5414
5415	/**
5416	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5417	*/
5418	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5419	{
5420	RT_NOREF(pszArgs);
5421	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5422	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5423	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5424
5425	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5426	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5427	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5428	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5429	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5430	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5431	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5432	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5433	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5434	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5435	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5436	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5437	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5438	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5439	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5440	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5441	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5442	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5443	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5444	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5445	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5446	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5447	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5448	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5449	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5450
5451	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5452	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5453	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5454	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5455
5456	# ifdef VBOX_WITH_VMSVGA3D
5457	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5458	# endif
5459	if (pThis->pDrv)
5460	{
5461	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5462	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5463	}
5464	}
5465
5466	/**
5467	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5468	*/
5469	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5470	{
5471	RT_NOREF(uPass);
5472
5473	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5474	int rc;
5475
5476	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5477	{
5478	uint32_t cScreens = 0;
5479	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5480	AssertRCReturn(rc, rc);
5481	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5482	("cScreens=%#x\n", cScreens),
5483	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5484
5485	for (uint32_t i = 0; i < cScreens; ++i)
5486	{
5487	VMSVGASCREENOBJECT screen;
5488	RT_ZERO(screen);
5489
5490	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5491	AssertLogRelRCReturn(rc, rc);
5492
5493	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5494	{
5495	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5496	*pScreen = screen;
5497	pScreen->fModified = true;
5498	}
5499	else
5500	{
5501	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5502	}
5503	}
5504	}
5505	else
5506	{
5507	/* Try to setup at least the first screen. */
5508	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5509	pScreen->fDefined = true;
5510	pScreen->fModified = true;
5511	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5512	pScreen->idScreen = 0;
5513	pScreen->xOrigin = 0;
5514	pScreen->yOrigin = 0;
5515	pScreen->offVRAM = pThis->svga.uScreenOffset;
5516	pScreen->cbPitch = pThis->svga.cbScanline;
5517	pScreen->cWidth = pThis->svga.uWidth;
5518	pScreen->cHeight = pThis->svga.uHeight;
5519	pScreen->cBpp = pThis->svga.uBpp;
5520	}
5521
5522	return VINF_SUCCESS;
5523	}
5524
5525	/**
5526	* @copydoc FNSSMDEVLOADEXEC
5527	*/
5528	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5529	{
5530	RT_NOREF(uPass);
5531	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5532	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5533	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5534	int rc;
5535
5536	/* Load our part of the VGAState */
5537	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5538	AssertRCReturn(rc, rc);
5539
5540	/* Load the VGA framebuffer. */
5541	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5542	uint32_t cbVgaFramebuffer = _32K;
5543	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5544	{
5545	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5546	AssertRCReturn(rc, rc);
5547	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5548	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5549	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5550	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5551	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5552	}
5553	rc = pHlp->pfnSSMGetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5554	AssertRCReturn(rc, rc);
5555	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5556	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5557	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5558	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5559
5560	/* Load the VMSVGA state. */
5561	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5562	AssertRCReturn(rc, rc);
5563
5564	/* Load the active cursor bitmaps. */
5565	if (pSVGAState->Cursor.fActive)
5566	{
5567	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5568	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5569
5570	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5571	AssertRCReturn(rc, rc);
5572	}
5573
5574	/* Load the GMR state. */
5575	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5576	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5577	{
5578	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5579	AssertRCReturn(rc, rc);
5580	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5581	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5582	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5583	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5584	}
5585
5586	if (pThis->svga.cGMR != cGMR)
5587	{
5588	/* Reallocate GMR array. */
5589	Assert(pSVGAState->paGMR != NULL);
5590	RTMemFree(pSVGAState->paGMR);
5591	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5592	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5593	pThis->svga.cGMR = cGMR;
5594	}
5595
5596	for (uint32_t i = 0; i < cGMR; ++i)
5597	{
5598	PGMR pGMR = &pSVGAState->paGMR[i];
5599
5600	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5601	AssertRCReturn(rc, rc);
5602
5603	if (pGMR->numDescriptors)
5604	{
5605	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5606	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5607	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5608
5609	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5610	{
5611	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5612	AssertRCReturn(rc, rc);
5613	}
5614	}
5615	}
5616
5617	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5618	vmsvga3dPowerOn(pThis);
5619	# endif
5620
5621	VMSVGA_STATE_LOAD LoadState;
5622	LoadState.pSSM = pSSM;
5623	LoadState.uVersion = uVersion;
5624	LoadState.uPass = uPass;
5625	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5626	AssertLogRelRCReturn(rc, rc);
5627
5628	return VINF_SUCCESS;
5629	}
5630
5631	/**
5632	* Reinit the video mode after the state has been loaded.
5633	*/
5634	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5635	{
5636	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5637	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5638
5639	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5640
5641	/* Set the active cursor. */
5642	if (pSVGAState->Cursor.fActive)
5643	{
5644	int rc;
5645
5646	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5647	true,
5648	true,
5649	pSVGAState->Cursor.xHotspot,
5650	pSVGAState->Cursor.yHotspot,
5651	pSVGAState->Cursor.width,
5652	pSVGAState->Cursor.height,
5653	pSVGAState->Cursor.pData);
5654	AssertRC(rc);
5655	}
5656	return VINF_SUCCESS;
5657	}
5658
5659	/**
5660	* Portion of SVGA state which must be saved in the FIFO thread.
5661	*/
5662	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5663	{
5664	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5665	int rc;
5666
5667	/* Save the screen objects. */
5668	/* Count defined screen object. */
5669	uint32_t cScreens = 0;
5670	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5671	{
5672	if (pSVGAState->aScreens[i].fDefined)
5673	++cScreens;
5674	}
5675
5676	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5677	AssertLogRelRCReturn(rc, rc);
5678
5679	for (uint32_t i = 0; i < cScreens; ++i)
5680	{
5681	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5682
5683	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5684	AssertLogRelRCReturn(rc, rc);
5685	}
5686	return VINF_SUCCESS;
5687	}
5688
5689	/**
5690	* @copydoc FNSSMDEVSAVEEXEC
5691	*/
5692	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5693	{
5694	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5695	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5696	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5697	int rc;
5698
5699	/* Save our part of the VGAState */
5700	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5701	AssertLogRelRCReturn(rc, rc);
5702
5703	/* Save the framebuffer backup. */
5704	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5705	rc = pHlp->pfnSSMPutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5706	AssertLogRelRCReturn(rc, rc);
5707
5708	/* Save the VMSVGA state. */
5709	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5710	AssertLogRelRCReturn(rc, rc);
5711
5712	/* Save the active cursor bitmaps. */
5713	if (pSVGAState->Cursor.fActive)
5714	{
5715	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5716	AssertLogRelRCReturn(rc, rc);
5717	}
5718
5719	/* Save the GMR state */
5720	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5721	AssertLogRelRCReturn(rc, rc);
5722	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5723	{
5724	PGMR pGMR = &pSVGAState->paGMR[i];
5725
5726	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5727	AssertLogRelRCReturn(rc, rc);
5728
5729	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5730	{
5731	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5732	AssertLogRelRCReturn(rc, rc);
5733	}
5734	}
5735
5736	/*
5737	* Must save some state (3D in particular) in the FIFO thread.
5738	*/
5739	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5740	AssertLogRelRCReturn(rc, rc);
5741
5742	return VINF_SUCCESS;
5743	}
5744
5745	/**
5746	* Destructor for PVMSVGAR3STATE structure.
5747	*
5748	* @param pThis The VGA instance.
5749	* @param pSVGAState Pointer to the structure. It is not deallocated.
5750	*/
5751	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5752	{
5753	# ifndef VMSVGA_USE_EMT_HALT_CODE
5754	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5755	{
5756	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5757	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5758	}
5759	# endif
5760
5761	if (pSVGAState->Cursor.fActive)
5762	{
5763	RTMemFree(pSVGAState->Cursor.pData);
5764	pSVGAState->Cursor.pData = NULL;
5765	pSVGAState->Cursor.fActive = false;
5766	}
5767
5768	if (pSVGAState->paGMR)
5769	{
5770	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5771	if (pSVGAState->paGMR[i].paDesc)
5772	RTMemFree(pSVGAState->paGMR[i].paDesc);
5773
5774	RTMemFree(pSVGAState->paGMR);
5775	pSVGAState->paGMR = NULL;
5776	}
5777	}
5778
5779	/**
5780	* Constructor for PVMSVGAR3STATE structure.
5781	*
5782	* @returns VBox status code.
5783	* @param pThis The VGA instance.
5784	* @param pSVGAState Pointer to the structure. It is already allocated.
5785	*/
5786	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5787	{
5788	int rc = VINF_SUCCESS;
5789	RT_ZERO(*pSVGAState);
5790
5791	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5792	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5793
5794	# ifndef VMSVGA_USE_EMT_HALT_CODE
5795	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5796	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5797	AssertRCReturn(rc, rc);
5798	# endif
5799
5800	return rc;
5801	}
5802
5803	/**
5804	* Initializes the host capabilities: registers and FIFO.
5805	*
5806	* @returns VBox status code.
5807	* @param pThis The VGA instance.
5808	*/
5809	static void vmsvgaR3InitCaps(PVGASTATE pThis)
5810	{
5811	/* Register caps. */
5812	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5813	\| SVGA_CAP_GMR2
5814	\| SVGA_CAP_CURSOR
5815	\| SVGA_CAP_CURSOR_BYPASS_2
5816	\| SVGA_CAP_EXTENDED_FIFO
5817	\| SVGA_CAP_IRQMASK
5818	\| SVGA_CAP_PITCHLOCK
5819	\| SVGA_CAP_TRACES
5820	\| SVGA_CAP_SCREEN_OBJECT_2
5821	\| SVGA_CAP_ALPHA_CURSOR;
5822	# ifdef VBOX_WITH_VMSVGA3D
5823	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5824	# endif
5825
5826	/* Clear the FIFO. */
5827	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5828
5829	/* Setup FIFO capabilities. */
5830	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5831	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5832	\| SVGA_FIFO_CAP_GMR2
5833	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5834	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5835	\| SVGA_FIFO_CAP_RESERVE
5836	\| SVGA_FIFO_CAP_PITCHLOCK;
5837
5838	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5839	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5840	}
5841
5842	# ifdef VBOX_WITH_VMSVGA3D
5843	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5844	static const char * const g_apszVmSvgaDevCapNames[] =
5845	{
5846	"x3D", /* = 0 */
5847	"xMAX_LIGHTS",
5848	"xMAX_TEXTURES",
5849	"xMAX_CLIP_PLANES",
5850	"xVERTEX_SHADER_VERSION",
5851	"xVERTEX_SHADER",
5852	"xFRAGMENT_SHADER_VERSION",
5853	"xFRAGMENT_SHADER",
5854	"xMAX_RENDER_TARGETS",
5855	"xS23E8_TEXTURES",
5856	"xS10E5_TEXTURES",
5857	"xMAX_FIXED_VERTEXBLEND",
5858	"xD16_BUFFER_FORMAT",
5859	"xD24S8_BUFFER_FORMAT",
5860	"xD24X8_BUFFER_FORMAT",
5861	"xQUERY_TYPES",
5862	"xTEXTURE_GRADIENT_SAMPLING",
5863	"rMAX_POINT_SIZE",
5864	"xMAX_SHADER_TEXTURES",
5865	"xMAX_TEXTURE_WIDTH",
5866	"xMAX_TEXTURE_HEIGHT",
5867	"xMAX_VOLUME_EXTENT",
5868	"xMAX_TEXTURE_REPEAT",
5869	"xMAX_TEXTURE_ASPECT_RATIO",
5870	"xMAX_TEXTURE_ANISOTROPY",
5871	"xMAX_PRIMITIVE_COUNT",
5872	"xMAX_VERTEX_INDEX",
5873	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5874	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5875	"xMAX_VERTEX_SHADER_TEMPS",
5876	"xMAX_FRAGMENT_SHADER_TEMPS",
5877	"xTEXTURE_OPS",
5878	"xSURFACEFMT_X8R8G8B8",
5879	"xSURFACEFMT_A8R8G8B8",
5880	"xSURFACEFMT_A2R10G10B10",
5881	"xSURFACEFMT_X1R5G5B5",
5882	"xSURFACEFMT_A1R5G5B5",
5883	"xSURFACEFMT_A4R4G4B4",
5884	"xSURFACEFMT_R5G6B5",
5885	"xSURFACEFMT_LUMINANCE16",
5886	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5887	"xSURFACEFMT_ALPHA8",
5888	"xSURFACEFMT_LUMINANCE8",
5889	"xSURFACEFMT_Z_D16",
5890	"xSURFACEFMT_Z_D24S8",
5891	"xSURFACEFMT_Z_D24X8",
5892	"xSURFACEFMT_DXT1",
5893	"xSURFACEFMT_DXT2",
5894	"xSURFACEFMT_DXT3",
5895	"xSURFACEFMT_DXT4",
5896	"xSURFACEFMT_DXT5",
5897	"xSURFACEFMT_BUMPX8L8V8U8",
5898	"xSURFACEFMT_A2W10V10U10",
5899	"xSURFACEFMT_BUMPU8V8",
5900	"xSURFACEFMT_Q8W8V8U8",
5901	"xSURFACEFMT_CxV8U8",
5902	"xSURFACEFMT_R_S10E5",
5903	"xSURFACEFMT_R_S23E8",
5904	"xSURFACEFMT_RG_S10E5",
5905	"xSURFACEFMT_RG_S23E8",
5906	"xSURFACEFMT_ARGB_S10E5",
5907	"xSURFACEFMT_ARGB_S23E8",
5908	"xMISSING62",
5909	"xMAX_VERTEX_SHADER_TEXTURES",
5910	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5911	"xSURFACEFMT_V16U16",
5912	"xSURFACEFMT_G16R16",
5913	"xSURFACEFMT_A16B16G16R16",
5914	"xSURFACEFMT_UYVY",
5915	"xSURFACEFMT_YUY2",
5916	"xMULTISAMPLE_NONMASKABLESAMPLES",
5917	"xMULTISAMPLE_MASKABLESAMPLES",
5918	"xALPHATOCOVERAGE",
5919	"xSUPERSAMPLE",
5920	"xAUTOGENMIPMAPS",
5921	"xSURFACEFMT_NV12",
5922	"xSURFACEFMT_AYUV",
5923	"xMAX_CONTEXT_IDS",
5924	"xMAX_SURFACE_IDS",
5925	"xSURFACEFMT_Z_DF16",
5926	"xSURFACEFMT_Z_DF24",
5927	"xSURFACEFMT_Z_D24S8_INT",
5928	"xSURFACEFMT_BC4_UNORM",
5929	"xSURFACEFMT_BC5_UNORM", /* 83 */
5930	};
5931
5932	/**
5933	* Initializes the host 3D capabilities in FIFO.
5934	*
5935	* @returns VBox status code.
5936	* @param pThis The VGA instance.
5937	*/
5938	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis)
5939	{
5940	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5941	bool fSavedBuffering = RTLogRelSetBuffering(true);
5942	SVGA3dCapsRecord *pCaps;
5943	SVGA3dCapPair *pData;
5944	uint32_t idxCap = 0;
5945
5946	/* 3d hardware version; latest and greatest */
5947	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5948	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5949
5950	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5951	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5952	pData = (SVGA3dCapPair *)&pCaps->data;
5953
5954	/* Fill out all 3d capabilities. */
5955	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5956	{
5957	uint32_t val = 0;
5958
5959	int rc = vmsvga3dQueryCaps(pThis, i, &val);
5960	if (RT_SUCCESS(rc))
5961	{
5962	pData[idxCap][0] = i;
5963	pData[idxCap][1] = val;
5964	idxCap++;
5965	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5966	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5967	else
5968	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5969	&g_apszVmSvgaDevCapNames[i][1]));
5970	}
5971	else
5972	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5973	}
5974	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5975	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5976
5977	/* Mark end of record array. */
5978	pCaps->header.length = 0;
5979
5980	RTLogRelSetBuffering(fSavedBuffering);
5981	}
5982
5983	# endif
5984
5985	/**
5986	* Resets the SVGA hardware state
5987	*
5988	* @returns VBox status code.
5989	* @param pDevIns The device instance.
5990	*/
5991	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
5992	{
5993	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5994	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5995
5996	/* Reset before init? */
5997	if (!pSVGAState)
5998	return VINF_SUCCESS;
5999
6000	Log(("vmsvgaR3Reset\n"));
6001
6002	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6003	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6004	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6005
6006	/* Reset other stuff. */
6007	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6008	RT_ZERO(pThis->svga.au32ScratchRegion);
6009
6010	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6011	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6012
6013	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6014
6015	/* Initialize FIFO and register capabilities. */
6016	vmsvgaR3InitCaps(pThis);
6017
6018	# ifdef VBOX_WITH_VMSVGA3D
6019	if (pThis->svga.f3DEnabled)
6020	vmsvgaR3InitFifo3DCaps(pThis);
6021	# endif
6022
6023	/* VRAM tracking is enabled by default during bootup. */
6024	pThis->svga.fVRAMTracking = true;
6025	pThis->svga.fEnabled = false;
6026
6027	/* Invalidate current settings. */
6028	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6029	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6030	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6031	pThis->svga.cbScanline = 0;
6032	pThis->svga.u32PitchLock = 0;
6033
6034	return rc;
6035	}
6036
6037	/**
6038	* Cleans up the SVGA hardware state
6039	*
6040	* @returns VBox status code.
6041	* @param pDevIns The device instance.
6042	*/
6043	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6044	{
6045	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6046
6047	/*
6048	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6049	*/
6050	if (pThis->svga.pFIFOIOThread)
6051	{
6052	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6053	AssertLogRelRC(rc);
6054
6055	rc = PDMDevHlpThreadDestroy(pDevIns, pThis->svga.pFIFOIOThread, NULL);
6056	AssertLogRelRC(rc);
6057	pThis->svga.pFIFOIOThread = NULL;
6058	}
6059
6060	/*
6061	* Destroy the special SVGA state.
6062	*/
6063	if (pThis->svga.pSvgaR3State)
6064	{
6065	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6066
6067	RTMemFree(pThis->svga.pSvgaR3State);
6068	pThis->svga.pSvgaR3State = NULL;
6069	}
6070
6071	/*
6072	* Free our resources residing in the VGA state.
6073	*/
6074	if (pThis->svga.pbVgaFrameBufferR3)
6075	{
6076	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6077	pThis->svga.pbVgaFrameBufferR3 = NULL;
6078	}
6079	if (pThis->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6080	{
6081	RTSemEventDestroy(pThis->svga.hFIFOExtCmdSem);
6082	pThis->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6083	}
6084	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6085	{
6086	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6087	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6088	}
6089
6090	return VINF_SUCCESS;
6091	}
6092
6093	/**
6094	* Initialize the SVGA hardware state
6095	*
6096	* @returns VBox status code.
6097	* @param pDevIns The device instance.
6098	*/
6099	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6100	{
6101	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6102	PVMSVGAR3STATE pSVGAState;
6103	int rc;
6104
6105	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6106	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6107
6108	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6109
6110	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6111	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6112	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6113
6114	/* Create event semaphore. */
6115	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6116	AssertRCReturn(rc, rc);
6117
6118	/* Create event semaphore. */
6119	rc = RTSemEventCreate(&pThis->svga.hFIFOExtCmdSem);
6120	AssertRCReturn(rc, rc);
6121
6122	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6123	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6124
6125	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6126	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6127
6128	pSVGAState = pThis->svga.pSvgaR3State;
6129
6130	/* Initialize FIFO and register capabilities. */
6131	vmsvgaR3InitCaps(pThis);
6132
6133	# ifdef VBOX_WITH_VMSVGA3D
6134	if (pThis->svga.f3DEnabled)
6135	{
6136	rc = vmsvga3dInit(pThis);
6137	if (RT_FAILURE(rc))
6138	{
6139	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6140	pThis->svga.f3DEnabled = false;
6141	}
6142	}
6143	# endif
6144	/* VRAM tracking is enabled by default during bootup. */
6145	pThis->svga.fVRAMTracking = true;
6146
6147	/* Invalidate current settings. */
6148	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6149	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6150	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6151	pThis->svga.cbScanline = 0;
6152
6153	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6154	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6155	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6156	{
6157	pThis->svga.u32MaxWidth -= 256;
6158	pThis->svga.u32MaxHeight -= 256;
6159	}
6160	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6161
6162	# ifdef DEBUG_GMR_ACCESS
6163	/* Register the GMR access handler type. */
6164	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6165	vmsvgaR3GmrAccessHandler,
6166	NULL, NULL, NULL,
6167	NULL, NULL, NULL,
6168	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6169	AssertRCReturn(rc, rc);
6170	# endif
6171
6172	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6173	/* Register the FIFO access handler type. In addition to
6174	debugging FIFO access, this is also used to facilitate
6175	extended fifo thread sleeps. */
6176	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6177	# ifdef DEBUG_FIFO_ACCESS
6178	PGMPHYSHANDLERKIND_ALL,
6179	# else
6180	PGMPHYSHANDLERKIND_WRITE,
6181	# endif
6182	vmsvgaR3FifoAccessHandler,
6183	NULL, NULL, NULL,
6184	NULL, NULL, NULL,
6185	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6186	AssertRCReturn(rc, rc);
6187	# endif
6188
6189	/* Create the async IO thread. */
6190	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6191	RTTHREADTYPE_IO, "VMSVGA FIFO");
6192	if (RT_FAILURE(rc))
6193	{
6194	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6195	return rc;
6196	}
6197
6198	/*
6199	* Statistics.
6200	*/
6201	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6202	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6203	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6204	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6205	# ifdef VBOX_WITH_STATISTICS
6206	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6207	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6208	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6209	# endif
6210	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6211	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6212	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6213	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6214	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6215	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6216	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6217	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6218	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6219	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6220	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6221	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6222	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6223	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6224	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6225	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6226	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6227	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6228	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6229	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6230	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6231	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6232	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6233	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6234	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6235	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6236	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6237	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6238	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6239	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6240	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6241	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6242	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6243	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6244	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6245	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6246	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6247	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6248	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6249	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6250	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6251	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6252	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6253	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6254	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6255	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6256	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6257	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6258	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6259	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6260	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6261	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6262	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6263
6264	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6265	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6266	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6267	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6268	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6269	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6270	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6271	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6272	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6273	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6274	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6275	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6276	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6277	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6278	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6279	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6280	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6281	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6282	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6283	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6284	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6285	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6286	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6287	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6288	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6289	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6290	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6291	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6292	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6293	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6294	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6295	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6296
6297	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6298	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6299	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6300	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6301	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6302	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6303	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6304	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6305	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6306	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6307	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6308	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6309	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6310	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6311	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6312	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6313	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6314	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6315	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6316	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6317	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6318	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6319	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6320	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6321	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6322	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6323	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6324	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6325	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6326	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6327	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6328	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6329	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6330	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6331	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6332	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6333	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6334	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6335	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6336	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6337	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6338	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6339	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6340	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6341	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6342	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6343	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6344	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6345	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6346
6347	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6348	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6349	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6350	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6351	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6352	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6353	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6354	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6355	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6356	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6357	# endif
6358	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6359	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6360	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6361	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6362	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6363
6364	# undef REG_CNT
6365	# undef REG_PRF
6366
6367	/*
6368	* Info handlers.
6369	*/
6370	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6371	# ifdef VBOX_WITH_VMSVGA3D
6372	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6373	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6374	"VMSVGA 3d surface details. "
6375	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6376	vmsvgaR3Info3dSurface);
6377	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6378	"VMSVGA 3d surface details and bitmap: "
6379	"sid[>dir]",
6380	vmsvgaR3Info3dSurfaceBmp);
6381	# endif
6382
6383	return VINF_SUCCESS;
6384	}
6385
6386	/**
6387	* Power On notification.
6388	*
6389	* @returns VBox status code.
6390	* @param pDevIns The device instance data.
6391	*
6392	* @remarks Caller enters the device critical section.
6393	*/
6394	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6395	{
6396	# ifdef VBOX_WITH_VMSVGA3D
6397	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6398	if (pThis->svga.f3DEnabled)
6399	{
6400	int rc = vmsvga3dPowerOn(pThis);
6401
6402	if (RT_SUCCESS(rc))
6403	{
6404	/* Initialize FIFO 3D capabilities. */
6405	vmsvgaR3InitFifo3DCaps(pThis);
6406	}
6407	}
6408	# else /* !VBOX_WITH_VMSVGA3D */
6409	RT_NOREF(pDevIns);
6410	# endif /* !VBOX_WITH_VMSVGA3D */
6411	}
6412
6413	#endif /* IN_RING3 */
6414

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82089

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