DevVGA-SVGA.cpp@ 82081

最後變更在這個檔案從82081是 82081,由 vboxsync 提交於 5 年前
DevVGA: style nits. bugref:9218
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1	/* $Id: DevVGA-SVGA.cpp 82081 2019-11-21 15:33:01Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.alldomusa.eu.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pDevIns The device instance.
766	* @param pThis VMSVGA State
767	* @param pu32 Where to store the read value
768	*/
769	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
770	{
771	int rc = VINF_SUCCESS;
772	*pu32 = 0;
773
774	/* Rough index register validation. */
775	uint32_t idxReg = pThis->svga.u32IndexReg;
776	#if !defined(IN_RING3) && defined(VBOX_STRICT)
777	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
778	VINF_IOM_R3_IOPORT_READ);
779	#else
780	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
781	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
782	VINF_SUCCESS);
783	#endif
784	RT_UNTRUSTED_VALIDATED_FENCE();
785
786	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
787	if ( idxReg >= SVGA_REG_CAPABILITIES
788	&& pThis->svga.u32SVGAId == SVGA_ID_0)
789	{
790	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
791	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
792	}
793
794	switch (idxReg)
795	{
796	case SVGA_REG_ID:
797	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
798	*pu32 = pThis->svga.u32SVGAId;
799	break;
800
801	case SVGA_REG_ENABLE:
802	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
803	*pu32 = pThis->svga.fEnabled;
804	break;
805
806	case SVGA_REG_WIDTH:
807	{
808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
809	if ( pThis->svga.fEnabled
810	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
811	{
812	*pu32 = pThis->svga.uWidth;
813	}
814	else
815	{
816	#ifndef IN_RING3
817	rc = VINF_IOM_R3_IOPORT_READ;
818	#else
819	*pu32 = pThis->pDrv->cx;
820	#endif
821	}
822	break;
823	}
824
825	case SVGA_REG_HEIGHT:
826	{
827	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
828	if ( pThis->svga.fEnabled
829	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
830	{
831	*pu32 = pThis->svga.uHeight;
832	}
833	else
834	{
835	#ifndef IN_RING3
836	rc = VINF_IOM_R3_IOPORT_READ;
837	#else
838	*pu32 = pThis->pDrv->cy;
839	#endif
840	}
841	break;
842	}
843
844	case SVGA_REG_MAX_WIDTH:
845	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
846	*pu32 = pThis->svga.u32MaxWidth;
847	break;
848
849	case SVGA_REG_MAX_HEIGHT:
850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
851	*pu32 = pThis->svga.u32MaxHeight;
852	break;
853
854	case SVGA_REG_DEPTH:
855	/* This returns the color depth of the current mode. */
856	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
857	switch (pThis->svga.uBpp)
858	{
859	case 15:
860	case 16:
861	case 24:
862	*pu32 = pThis->svga.uBpp;
863	break;
864
865	default:
866	case 32:
867	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
868	break;
869	}
870	break;
871
872	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
873	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
874	if ( pThis->svga.fEnabled
875	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
876	{
877	*pu32 = pThis->svga.uBpp;
878	}
879	else
880	{
881	#ifndef IN_RING3
882	rc = VINF_IOM_R3_IOPORT_READ;
883	#else
884	*pu32 = pThis->pDrv->cBits;
885	#endif
886	}
887	break;
888
889	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
891	if ( pThis->svga.fEnabled
892	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
893	{
894	*pu32 = (pThis->svga.uBpp + 7) & ~7;
895	}
896	else
897	{
898	#ifndef IN_RING3
899	rc = VINF_IOM_R3_IOPORT_READ;
900	#else
901	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
902	#endif
903	}
904	break;
905
906	case SVGA_REG_PSEUDOCOLOR:
907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
908	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
909	break;
910
911	case SVGA_REG_RED_MASK:
912	case SVGA_REG_GREEN_MASK:
913	case SVGA_REG_BLUE_MASK:
914	{
915	uint32_t uBpp;
916
917	if ( pThis->svga.fEnabled
918	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
919	{
920	uBpp = pThis->svga.uBpp;
921	}
922	else
923	{
924	#ifndef IN_RING3
925	rc = VINF_IOM_R3_IOPORT_READ;
926	break;
927	#else
928	uBpp = pThis->pDrv->cBits;
929	#endif
930	}
931	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
932	switch (uBpp)
933	{
934	case 8:
935	u32RedMask = 0x07;
936	u32GreenMask = 0x38;
937	u32BlueMask = 0xc0;
938	break;
939
940	case 15:
941	u32RedMask = 0x0000001f;
942	u32GreenMask = 0x000003e0;
943	u32BlueMask = 0x00007c00;
944	break;
945
946	case 16:
947	u32RedMask = 0x0000001f;
948	u32GreenMask = 0x000007e0;
949	u32BlueMask = 0x0000f800;
950	break;
951
952	case 24:
953	case 32:
954	default:
955	u32RedMask = 0x00ff0000;
956	u32GreenMask = 0x0000ff00;
957	u32BlueMask = 0x000000ff;
958	break;
959	}
960	switch (idxReg)
961	{
962	case SVGA_REG_RED_MASK:
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
964	*pu32 = u32RedMask;
965	break;
966
967	case SVGA_REG_GREEN_MASK:
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
969	*pu32 = u32GreenMask;
970	break;
971
972	case SVGA_REG_BLUE_MASK:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
974	*pu32 = u32BlueMask;
975	break;
976	}
977	break;
978	}
979
980	case SVGA_REG_BYTES_PER_LINE:
981	{
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
983	if ( pThis->svga.fEnabled
984	&& pThis->svga.cbScanline)
985	{
986	*pu32 = pThis->svga.cbScanline;
987	}
988	else
989	{
990	#ifndef IN_RING3
991	rc = VINF_IOM_R3_IOPORT_READ;
992	#else
993	*pu32 = pThis->pDrv->cbScanline;
994	#endif
995	}
996	break;
997	}
998
999	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1000	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1001	*pu32 = pThis->vram_size;
1002	break;
1003
1004	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1005	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1006	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1007	*pu32 = pThis->GCPhysVRAM;
1008	break;
1009
1010	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1011	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1012	/* Always zero in our case. */
1013	*pu32 = 0;
1014	break;
1015
1016	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1017	{
1018	#ifndef IN_RING3
1019	rc = VINF_IOM_R3_IOPORT_READ;
1020	#else
1021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1022
1023	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1024	if ( pThis->svga.fEnabled
1025	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1026	{
1027	/* Hardware enabled; return real framebuffer size .*/
1028	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1029	}
1030	else
1031	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1032
1033	pu32 = RT_MIN(pThis->vram_size, pu32);
1034	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1035	#endif
1036	break;
1037	}
1038
1039	case SVGA_REG_CAPABILITIES:
1040	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1041	*pu32 = pThis->svga.u32RegCaps;
1042	break;
1043
1044	case SVGA_REG_MEM_START: /* FIFO start */
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1046	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1047	*pu32 = pThis->svga.GCPhysFIFO;
1048	break;
1049
1050	case SVGA_REG_MEM_SIZE: /* FIFO size */
1051	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1052	*pu32 = pThis->svga.cbFIFO;
1053	break;
1054
1055	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1057	*pu32 = pThis->svga.fConfigured;
1058	break;
1059
1060	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1061	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1062	*pu32 = 0;
1063	break;
1064
1065	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1066	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1067	if (pThis->svga.fBusy)
1068	{
1069	#ifndef IN_RING3
1070	/* Go to ring-3 and halt the CPU. */
1071	rc = VINF_IOM_R3_IOPORT_READ;
1072	RT_NOREF(pDevIns);
1073	break;
1074	#else
1075	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1076	/* The guest is basically doing a HLT via the device here, but with
1077	a special wake up condition on FIFO completion. */
1078	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1079	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1080	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1081	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1082	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1083	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1084	if (pThis->svga.fBusy)
1085	{
1086	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1087	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1088	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1089	}
1090	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1091	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1092	# else
1093
1094	/* Delay the EMT a bit so the FIFO and others can get some work done.
1095	This used to be a crude 50 ms sleep. The current code tries to be
1096	more efficient, but the consept is still very crude. */
1097	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1098	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1099	RTThreadYield();
1100	if (pThis->svga.fBusy)
1101	{
1102	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1103
1104	if (pThis->svga.fBusy && cRefs == 1)
1105	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1106	if (pThis->svga.fBusy)
1107	{
1108	/** @todo If this code is going to stay, we need to call into the halt/wait
1109	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1110	* suffer when the guest is polling on a busy FIFO. */
1111	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1112	if (cNsMaxWait >= RT_NS_100US)
1113	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1114	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1115	RT_MIN(cNsMaxWait, RT_NS_10MS));
1116	}
1117
1118	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1119	}
1120	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1121	# endif
1122	*pu32 = pThis->svga.fBusy != 0;
1123	#endif
1124	}
1125	else
1126	*pu32 = false;
1127	break;
1128
1129	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1130	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1131	*pu32 = pThis->svga.u32GuestId;
1132	break;
1133
1134	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1135	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1136	*pu32 = pThis->svga.cScratchRegion;
1137	break;
1138
1139	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1140	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1141	*pu32 = SVGA_FIFO_NUM_REGS;
1142	break;
1143
1144	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1145	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1146	*pu32 = pThis->svga.u32PitchLock;
1147	break;
1148
1149	case SVGA_REG_IRQMASK: /* Interrupt mask */
1150	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1151	*pu32 = pThis->svga.u32IrqMask;
1152	break;
1153
1154	/* See "Guest memory regions" below. */
1155	case SVGA_REG_GMR_ID:
1156	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1157	*pu32 = pThis->svga.u32CurrentGMRId;
1158	break;
1159
1160	case SVGA_REG_GMR_DESCRIPTOR:
1161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1162	/* Write only */
1163	*pu32 = 0;
1164	break;
1165
1166	case SVGA_REG_GMR_MAX_IDS:
1167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1168	*pu32 = pThis->svga.cGMR;
1169	break;
1170
1171	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1172	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1173	*pu32 = VMSVGA_MAX_GMR_PAGES;
1174	break;
1175
1176	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1178	*pu32 = pThis->svga.fTraces;
1179	break;
1180
1181	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1183	*pu32 = VMSVGA_MAX_GMR_PAGES;
1184	break;
1185
1186	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1188	*pu32 = VMSVGA_SURFACE_SIZE;
1189	break;
1190
1191	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1192	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1193	break;
1194
1195	/* Mouse cursor support. */
1196	case SVGA_REG_CURSOR_ID:
1197	case SVGA_REG_CURSOR_X:
1198	case SVGA_REG_CURSOR_Y:
1199	case SVGA_REG_CURSOR_ON:
1200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1201	break;
1202
1203	/* Legacy multi-monitor support */
1204	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1206	*pu32 = 1;
1207	break;
1208
1209	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1210	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1211	*pu32 = 0;
1212	break;
1213
1214	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1215	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1216	*pu32 = 0;
1217	break;
1218
1219	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1220	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1221	*pu32 = 0;
1222	break;
1223
1224	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1225	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1226	*pu32 = 0;
1227	break;
1228
1229	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1231	*pu32 = pThis->svga.uWidth;
1232	break;
1233
1234	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1236	*pu32 = pThis->svga.uHeight;
1237	break;
1238
1239	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1241	/* We must return something sensible here otherwise the Linux driver
1242	will take a legacy code path without 3d support. This number also
1243	limits how many screens Linux guests will allow. */
1244	*pu32 = pThis->cMonitors;
1245	break;
1246
1247	default:
1248	{
1249	uint32_t offReg;
1250	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1251	{
1252	RT_UNTRUSTED_VALIDATED_FENCE();
1253	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1254	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1255	}
1256	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1257	{
1258	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1260	RT_UNTRUSTED_VALIDATED_FENCE();
1261	uint32_t u32 = pThis->last_palette[offReg / 3];
1262	switch (offReg % 3)
1263	{
1264	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1265	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1266	case 2: pu32 = u32 & 0xff; break; / blue */
1267	}
1268	}
1269	else
1270	{
1271	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1272	rc = VINF_IOM_R3_IOPORT_READ;
1273	#else
1274	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1275
1276	/* Do not assert. The guest might be reading all registers. */
1277	LogFunc(("Unknown reg=%#x\n", idxReg));
1278	#endif
1279	}
1280	break;
1281	}
1282	}
1283	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1284	return rc;
1285	}
1286
1287	#ifdef IN_RING3
1288	/**
1289	* Apply the current resolution settings to change the video mode.
1290	*
1291	* @returns VBox status code.
1292	* @param pThis VMSVGA State
1293	*/
1294	static int vmsvgaChangeMode(PVGASTATE pThis)
1295	{
1296	int rc;
1297
1298	/* Always do changemode on FIFO thread. */
1299	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1300
1301	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1302
1303	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1304
1305	if (pThis->svga.fGFBRegisters)
1306	{
1307	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1308	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1309	* deletes all screens other than screen #0, and redefines screen
1310	* #0 according to the specified mode. Drivers that use
1311	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1312	*/
1313
1314	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1315	pScreen->fDefined = true;
1316	pScreen->fModified = true;
1317	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1318	pScreen->idScreen = 0;
1319	pScreen->xOrigin = 0;
1320	pScreen->yOrigin = 0;
1321	pScreen->offVRAM = 0;
1322	pScreen->cbPitch = pThis->svga.cbScanline;
1323	pScreen->cWidth = pThis->svga.uWidth;
1324	pScreen->cHeight = pThis->svga.uHeight;
1325	pScreen->cBpp = pThis->svga.uBpp;
1326
1327	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1328	{
1329	/* Delete screen. */
1330	pScreen = &pSVGAState->aScreens[iScreen];
1331	if (pScreen->fDefined)
1332	{
1333	pScreen->fModified = true;
1334	pScreen->fDefined = false;
1335	}
1336	}
1337	}
1338	else
1339	{
1340	/* "If Screen Objects are supported, they can be used to fully
1341	* replace the functionality provided by the framebuffer registers
1342	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1343	*/
1344	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1345	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1346	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1347	}
1348
1349	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1350	{
1351	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1352	if (!pScreen->fModified)
1353	continue;
1354
1355	pScreen->fModified = false;
1356
1357	VBVAINFOVIEW view;
1358	RT_ZERO(view);
1359	view.u32ViewIndex = pScreen->idScreen;
1360	// view.u32ViewOffset = 0;
1361	view.u32ViewSize = pThis->vram_size;
1362	view.u32MaxScreenSize = pThis->vram_size;
1363
1364	VBVAINFOSCREEN screen;
1365	RT_ZERO(screen);
1366	screen.u32ViewIndex = pScreen->idScreen;
1367
1368	if (pScreen->fDefined)
1369	{
1370	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1371	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1372	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1373	{
1374	Assert(pThis->svga.fGFBRegisters);
1375	continue;
1376	}
1377
1378	screen.i32OriginX = pScreen->xOrigin;
1379	screen.i32OriginY = pScreen->yOrigin;
1380	screen.u32StartOffset = pScreen->offVRAM;
1381	screen.u32LineSize = pScreen->cbPitch;
1382	screen.u32Width = pScreen->cWidth;
1383	screen.u32Height = pScreen->cHeight;
1384	screen.u16BitsPerPixel = pScreen->cBpp;
1385	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1386	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1387	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1388	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1389	}
1390	else
1391	{
1392	/* Screen is destroyed. */
1393	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1394	}
1395
1396	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1397	AssertRC(rc);
1398	}
1399
1400	/* Last stuff. For the VGA device screenshot. */
1401	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1402	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1404	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1405	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1406
1407	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1408	if ( pThis->svga.viewport.cx == 0
1409	&& pThis->svga.viewport.cy == 0)
1410	{
1411	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1412	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1413	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1414	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1415	pThis->svga.viewport.yLowWC = 0;
1416	}
1417
1418	return VINF_SUCCESS;
1419	}
1420
1421	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1422	{
1423	VBVACMDHDR cmd;
1424	cmd.x = (int16_t)(pScreen->xOrigin + x);
1425	cmd.y = (int16_t)(pScreen->yOrigin + y);
1426	cmd.w = (uint16_t)w;
1427	cmd.h = (uint16_t)h;
1428
1429	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1430	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1431	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1432	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1433
1434	return VINF_SUCCESS;
1435	}
1436
1437	#endif /* IN_RING3 */
1438	#if defined(IN_RING0) \|\| defined(IN_RING3)
1439
1440	/**
1441	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1442	*
1443	* @param pThis The VMSVGA state.
1444	* @param fState The busy state.
1445	*/
1446	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1447	{
1448	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1449
1450	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1451	{
1452	/* Race / unfortunately scheduling. Highly unlikly. */
1453	uint32_t cLoops = 64;
1454	do
1455	{
1456	ASMNopPause();
1457	fState = (pThis->svga.fBusy != 0);
1458	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1459	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1460	}
1461	}
1462
1463
1464	/**
1465	* Update the scanline pitch in response to the guest changing mode
1466	* width/bpp.
1467	*
1468	* @param pThis VMSVGA State
1469	*/
1470	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1471	{
1472	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1473	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1474	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1475	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1476
1477	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1478	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1479	* location but it has a different meaning.
1480	*/
1481	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1482	uFifoPitchLock = 0;
1483
1484	/* Sanitize values. */
1485	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1486	uFifoPitchLock = 0;
1487	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1488	uRegPitchLock = 0;
1489
1490	/* Prefer the register value to the FIFO value.*/
1491	if (uRegPitchLock)
1492	pThis->svga.cbScanline = uRegPitchLock;
1493	else if (uFifoPitchLock)
1494	pThis->svga.cbScanline = uFifoPitchLock;
1495	else
1496	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1497
1498	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1499	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1500	}
1501
1502	#endif /* IN_RING0 \|\| IN_RING3 */
1503
1504
1505	/**
1506	* Write port register
1507	*
1508	* @returns Strict VBox status code.
1509	* @param pThis VMSVGA State
1510	* @param u32 Value to write
1511	*/
1512	static VBOXSTRICTRC vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1513	{
1514	#ifdef IN_RING3
1515	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1516	#endif
1517	VBOXSTRICTRC rc = VINF_SUCCESS;
1518
1519	/* Rough index register validation. */
1520	uint32_t idxReg = pThis->svga.u32IndexReg;
1521	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1522	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1523	VINF_IOM_R3_IOPORT_WRITE);
1524	#else
1525	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1526	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1527	VINF_SUCCESS);
1528	#endif
1529	RT_UNTRUSTED_VALIDATED_FENCE();
1530
1531	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1532	if ( idxReg >= SVGA_REG_CAPABILITIES
1533	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1534	{
1535	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1536	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1537	}
1538	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1539	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1540	switch (idxReg)
1541	{
1542	case SVGA_REG_WIDTH:
1543	case SVGA_REG_HEIGHT:
1544	case SVGA_REG_PITCHLOCK:
1545	case SVGA_REG_BITS_PER_PIXEL:
1546	pThis->svga.fGFBRegisters = true;
1547	break;
1548	default:
1549	break;
1550	}
1551
1552	switch (idxReg)
1553	{
1554	case SVGA_REG_ID:
1555	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1556	if ( u32 == SVGA_ID_0
1557	\|\| u32 == SVGA_ID_1
1558	\|\| u32 == SVGA_ID_2)
1559	pThis->svga.u32SVGAId = u32;
1560	else
1561	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1562	break;
1563
1564	case SVGA_REG_ENABLE:
1565	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1566	#ifdef IN_RING3
1567	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1568	&& pThis->svga.fEnabled == false)
1569	{
1570	/* Make a backup copy of the first 512kb in order to save font data etc. */
1571	/** @todo should probably swap here, rather than copy + zero */
1572	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1573	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1574	}
1575
1576	pThis->svga.fEnabled = u32;
1577	if (pThis->svga.fEnabled)
1578	{
1579	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1580	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1581	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1582	{
1583	/* Keep the current mode. */
1584	pThis->svga.uWidth = pThis->pDrv->cx;
1585	pThis->svga.uHeight = pThis->pDrv->cy;
1586	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1587	}
1588
1589	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1590	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1591	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1592	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1593	# ifdef LOG_ENABLED
1594	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1595	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1596	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1597	# endif
1598
1599	/* Disable or enable dirty page tracking according to the current fTraces value. */
1600	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1601
1602	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1603	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1604	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/);
1605	}
1606	else
1607	{
1608	/* Restore the text mode backup. */
1609	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1610
1611	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1612
1613	/* Enable dirty page tracking again when going into legacy mode. */
1614	vmsvgaSetTraces(pThis, true);
1615
1616	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1617	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1618	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1619
1620	/* Clear the pitch lock. */
1621	pThis->svga.u32PitchLock = 0;
1622	}
1623	#else /* !IN_RING3 */
1624	rc = VINF_IOM_R3_IOPORT_WRITE;
1625	#endif /* !IN_RING3 */
1626	break;
1627
1628	case SVGA_REG_WIDTH:
1629	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1630	if (pThis->svga.uWidth != u32)
1631	{
1632	#if defined(IN_RING3) \|\| defined(IN_RING0)
1633	pThis->svga.uWidth = u32;
1634	vmsvgaUpdatePitch(pThis);
1635	if (pThis->svga.fEnabled)
1636	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1637	#else
1638	rc = VINF_IOM_R3_IOPORT_WRITE;
1639	#endif
1640	}
1641	/* else: nop */
1642	break;
1643
1644	case SVGA_REG_HEIGHT:
1645	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1646	if (pThis->svga.uHeight != u32)
1647	{
1648	pThis->svga.uHeight = u32;
1649	if (pThis->svga.fEnabled)
1650	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1651	}
1652	/* else: nop */
1653	break;
1654
1655	case SVGA_REG_DEPTH:
1656	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1657	/** @todo read-only?? */
1658	break;
1659
1660	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1661	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1662	if (pThis->svga.uBpp != u32)
1663	{
1664	#if defined(IN_RING3) \|\| defined(IN_RING0)
1665	pThis->svga.uBpp = u32;
1666	vmsvgaUpdatePitch(pThis);
1667	if (pThis->svga.fEnabled)
1668	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1669	#else
1670	rc = VINF_IOM_R3_IOPORT_WRITE;
1671	#endif
1672	}
1673	/* else: nop */
1674	break;
1675
1676	case SVGA_REG_PSEUDOCOLOR:
1677	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1678	break;
1679
1680	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1681	#ifdef IN_RING3
1682	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1683	pThis->svga.fConfigured = u32;
1684	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1685	if (!pThis->svga.fConfigured)
1686	pThis->svga.fTraces = true;
1687	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1688	#else
1689	rc = VINF_IOM_R3_IOPORT_WRITE;
1690	#endif
1691	break;
1692
1693	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1694	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1695	if ( pThis->svga.fEnabled
1696	&& pThis->svga.fConfigured)
1697	{
1698	#if defined(IN_RING3) \|\| defined(IN_RING0)
1699	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1700	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1701	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1702	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1703
1704	/* Kick the FIFO thread to start processing commands again. */
1705	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1706	#else
1707	rc = VINF_IOM_R3_IOPORT_WRITE;
1708	#endif
1709	}
1710	/* else nothing to do. */
1711	else
1712	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1713
1714	break;
1715
1716	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1717	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1718	break;
1719
1720	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1721	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1722	pThis->svga.u32GuestId = u32;
1723	break;
1724
1725	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1726	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1727	pThis->svga.u32PitchLock = u32;
1728	/* Should this also update the FIFO pitch lock? Unclear. */
1729	break;
1730
1731	case SVGA_REG_IRQMASK: /* Interrupt mask */
1732	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1733	pThis->svga.u32IrqMask = u32;
1734
1735	/* Irq pending after the above change? */
1736	if (pThis->svga.u32IrqStatus & u32)
1737	{
1738	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1739	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1740	}
1741	else
1742	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1743	break;
1744
1745	/* Mouse cursor support */
1746	case SVGA_REG_CURSOR_ID:
1747	case SVGA_REG_CURSOR_X:
1748	case SVGA_REG_CURSOR_Y:
1749	case SVGA_REG_CURSOR_ON:
1750	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1751	break;
1752
1753	/* Legacy multi-monitor support */
1754	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1755	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1756	break;
1757	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1758	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1759	break;
1760	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1761	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1762	break;
1763	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1764	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1765	break;
1766	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1767	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1768	break;
1769	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1770	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1771	break;
1772	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1773	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1774	break;
1775	#ifdef VBOX_WITH_VMSVGA3D
1776	/* See "Guest memory regions" below. */
1777	case SVGA_REG_GMR_ID:
1778	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1779	pThis->svga.u32CurrentGMRId = u32;
1780	break;
1781
1782	case SVGA_REG_GMR_DESCRIPTOR:
1783	# ifndef IN_RING3
1784	rc = VINF_IOM_R3_IOPORT_WRITE;
1785	break;
1786	# else /* IN_RING3 */
1787	{
1788	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1789
1790	/* Validate current GMR id. */
1791	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1792	AssertBreak(idGMR < pThis->svga.cGMR);
1793	RT_UNTRUSTED_VALIDATED_FENCE();
1794
1795	/* Free the old GMR if present. */
1796	vmsvgaGMRFree(pThis, idGMR);
1797
1798	/* Just undefine the GMR? */
1799	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1800	if (GCPhys == 0)
1801	{
1802	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1803	break;
1804	}
1805
1806
1807	/* Never cross a page boundary automatically. */
1808	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1809	uint32_t cPagesTotal = 0;
1810	uint32_t iDesc = 0;
1811	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1812	uint32_t cLoops = 0;
1813	RTGCPHYS GCPhysBase = GCPhys;
1814	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1815	{
1816	/* Read descriptor. */
1817	SVGAGuestMemDescriptor desc;
1818	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1819	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1820
1821	if (desc.numPages != 0)
1822	{
1823	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1824	cPagesTotal += desc.numPages;
1825	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1826
1827	if ((iDesc & 15) == 0)
1828	{
1829	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1830	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1831	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1832	}
1833
1834	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1835	paDescs[iDesc++].numPages = desc.numPages;
1836
1837	/* Continue with the next descriptor. */
1838	GCPhys += sizeof(desc);
1839	}
1840	else if (desc.ppn == 0)
1841	break; /* terminator */
1842	else /* Pointer to the next physical page of descriptors. */
1843	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1844
1845	cLoops++;
1846	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1847	}
1848
1849	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1850	if (RT_SUCCESS(rc))
1851	{
1852	/* Commit the GMR. */
1853	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1854	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1855	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1856	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1857	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1858	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1859	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1860	}
1861	else
1862	{
1863	RTMemFree(paDescs);
1864	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1865	}
1866	break;
1867	}
1868	# endif /* IN_RING3 */
1869	#endif // VBOX_WITH_VMSVGA3D
1870
1871	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1872	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1873	if (pThis->svga.fTraces == u32)
1874	break; /* nothing to do */
1875
1876	#ifdef IN_RING3
1877	vmsvgaSetTraces(pThis, !!u32);
1878	#else
1879	rc = VINF_IOM_R3_IOPORT_WRITE;
1880	#endif
1881	break;
1882
1883	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1884	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1885	break;
1886
1887	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1888	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1889	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1890	break;
1891
1892	case SVGA_REG_FB_START:
1893	case SVGA_REG_MEM_START:
1894	case SVGA_REG_HOST_BITS_PER_PIXEL:
1895	case SVGA_REG_MAX_WIDTH:
1896	case SVGA_REG_MAX_HEIGHT:
1897	case SVGA_REG_VRAM_SIZE:
1898	case SVGA_REG_FB_SIZE:
1899	case SVGA_REG_CAPABILITIES:
1900	case SVGA_REG_MEM_SIZE:
1901	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1902	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1903	case SVGA_REG_BYTES_PER_LINE:
1904	case SVGA_REG_FB_OFFSET:
1905	case SVGA_REG_RED_MASK:
1906	case SVGA_REG_GREEN_MASK:
1907	case SVGA_REG_BLUE_MASK:
1908	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1909	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1910	case SVGA_REG_GMR_MAX_IDS:
1911	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1912	/* Read only - ignore. */
1913	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1914	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1915	break;
1916
1917	default:
1918	{
1919	uint32_t offReg;
1920	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1921	{
1922	RT_UNTRUSTED_VALIDATED_FENCE();
1923	pThis->svga.au32ScratchRegion[offReg] = u32;
1924	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1925	}
1926	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1927	{
1928	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1929	Btw, see rgb_to_pixel32. */
1930	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1931	u32 &= 0xff;
1932	RT_UNTRUSTED_VALIDATED_FENCE();
1933	uint32_t uRgb = pThis->last_palette[offReg / 3];
1934	switch (offReg % 3)
1935	{
1936	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1937	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1938	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1939	}
1940	pThis->last_palette[offReg / 3] = uRgb;
1941	}
1942	else
1943	{
1944	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1945	rc = VINF_IOM_R3_IOPORT_WRITE;
1946	#else
1947	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1948	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1949	#endif
1950	}
1951	break;
1952	}
1953	}
1954	return rc;
1955	}
1956
1957	/**
1958	* @callback_method_impl{FNIOMIOPORTNEWIN}
1959	*/
1960	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1961	{
1962	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1963	RT_NOREF_PV(pvUser);
1964
1965	/* Only dword accesses. */
1966	if (cb == 4)
1967	{
1968	switch (offPort)
1969	{
1970	case SVGA_INDEX_PORT:
1971	*pu32 = pThis->svga.u32IndexReg;
1972	break;
1973
1974	case SVGA_VALUE_PORT:
1975	return vmsvgaReadPort(pDevIns, pThis, pu32);
1976
1977	case SVGA_BIOS_PORT:
1978	Log(("Ignoring BIOS port read\n"));
1979	*pu32 = 0;
1980	break;
1981
1982	case SVGA_IRQSTATUS_PORT:
1983	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1984	*pu32 = pThis->svga.u32IrqStatus;
1985	break;
1986
1987	default:
1988	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1989	*pu32 = UINT32_MAX;
1990	break;
1991	}
1992	}
1993	else
1994	{
1995	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
1996	*pu32 = UINT32_MAX;
1997	}
1998	return VINF_SUCCESS;
1999	}
2000
2001	/**
2002	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2003	*/
2004	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2005	{
2006	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2007	RT_NOREF_PV(pvUser);
2008
2009	/* Only dword accesses. */
2010	if (cb == 4)
2011	switch (offPort)
2012	{
2013	case SVGA_INDEX_PORT:
2014	pThis->svga.u32IndexReg = u32;
2015	break;
2016
2017	case SVGA_VALUE_PORT:
2018	return vmsvgaWritePort(pThis, u32);
2019
2020	case SVGA_BIOS_PORT:
2021	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2022	break;
2023
2024	case SVGA_IRQSTATUS_PORT:
2025	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2026	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2027	/* Clear the irq in case all events have been cleared. */
2028	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2029	{
2030	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2031	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2032	}
2033	break;
2034
2035	default:
2036	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2037	break;
2038	}
2039	else
2040	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2041
2042	return VINF_SUCCESS;
2043	}
2044
2045	#ifdef IN_RING3
2046
2047	# ifdef DEBUG_FIFO_ACCESS
2048	/**
2049	* Handle FIFO memory access.
2050	* @returns VBox status code.
2051	* @param pVM VM handle.
2052	* @param pThis VGA device instance data.
2053	* @param GCPhys The access physical address.
2054	* @param fWriteAccess Read or write access
2055	*/
2056	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2057	{
2058	RT_NOREF(pVM);
2059	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2060	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2061
2062	switch (GCPhysOffset >> 2)
2063	{
2064	case SVGA_FIFO_MIN:
2065	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2066	break;
2067	case SVGA_FIFO_MAX:
2068	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2069	break;
2070	case SVGA_FIFO_NEXT_CMD:
2071	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2072	break;
2073	case SVGA_FIFO_STOP:
2074	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2075	break;
2076	case SVGA_FIFO_CAPABILITIES:
2077	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2078	break;
2079	case SVGA_FIFO_FLAGS:
2080	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2081	break;
2082	case SVGA_FIFO_FENCE:
2083	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2084	break;
2085	case SVGA_FIFO_3D_HWVERSION:
2086	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2087	break;
2088	case SVGA_FIFO_PITCHLOCK:
2089	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2090	break;
2091	case SVGA_FIFO_CURSOR_ON:
2092	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2093	break;
2094	case SVGA_FIFO_CURSOR_X:
2095	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2096	break;
2097	case SVGA_FIFO_CURSOR_Y:
2098	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2099	break;
2100	case SVGA_FIFO_CURSOR_COUNT:
2101	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2102	break;
2103	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2104	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2105	break;
2106	case SVGA_FIFO_RESERVED:
2107	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2108	break;
2109	case SVGA_FIFO_CURSOR_SCREEN_ID:
2110	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2111	break;
2112	case SVGA_FIFO_DEAD:
2113	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2114	break;
2115	case SVGA_FIFO_3D_HWVERSION_REVISED:
2116	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2117	break;
2118	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2119	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2120	break;
2121	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2122	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2123	break;
2124	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2125	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2126	break;
2127	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2128	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2129	break;
2130	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2131	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2132	break;
2133	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2134	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2135	break;
2136	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2137	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2138	break;
2139	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2140	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2141	break;
2142	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2143	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2144	break;
2145	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2146	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2147	break;
2148	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2149	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2150	break;
2151	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2152	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2153	break;
2154	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2155	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2156	break;
2157	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2158	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2159	break;
2160	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2161	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2162	break;
2163	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2164	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2165	break;
2166	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2167	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2168	break;
2169	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2170	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2171	break;
2172	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2173	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2174	break;
2175	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2176	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2177	break;
2178	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2179	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2180	break;
2181	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2182	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2183	break;
2184	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2185	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2186	break;
2187	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2188	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2189	break;
2190	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2191	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2192	break;
2193	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2194	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2195	break;
2196	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2197	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2198	break;
2199	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2200	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2201	break;
2202	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2203	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2204	break;
2205	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2206	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2207	break;
2208	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2209	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2210	break;
2211	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2212	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2213	break;
2214	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2215	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2216	break;
2217	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2218	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2219	break;
2220	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2221	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2222	break;
2223	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2224	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2225	break;
2226	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2227	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2228	break;
2229	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2230	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2231	break;
2232	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2233	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2234	break;
2235	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2236	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2237	break;
2238	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2239	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2240	break;
2241	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2242	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2243	break;
2244	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2245	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2246	break;
2247	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2248	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2249	break;
2250	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2251	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2252	break;
2253	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2254	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2255	break;
2256	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2257	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2258	break;
2259	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2260	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2261	break;
2262	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2263	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2264	break;
2265	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2266	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2267	break;
2268	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2269	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2270	break;
2271	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2272	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2273	break;
2274	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2275	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2276	break;
2277	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2278	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2279	break;
2280	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2281	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2282	break;
2283	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2284	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2285	break;
2286	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2287	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2288	break;
2289	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2290	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2291	break;
2292	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2293	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2294	break;
2295	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2296	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2297	break;
2298	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2299	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2300	break;
2301	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2302	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2303	break;
2304	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2305	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2306	break;
2307	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2308	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2309	break;
2310	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2311	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2312	break;
2313	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2314	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2315	break;
2316	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2317	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2318	break;
2319	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2320	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2321	break;
2322	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2323	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2324	break;
2325	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2326	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2327	break;
2328	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2329	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2330	break;
2331	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2332	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2333	break;
2334	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2335	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2336	break;
2337	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2338	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2339	break;
2340	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2341	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2342	break;
2343	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2344	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2345	break;
2346	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2347	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2348	break;
2349	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2350	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2351	break;
2352	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2353	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2354	break;
2355	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2356	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2357	break;
2358	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2359	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2360	break;
2361	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2362	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2363	break;
2364	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2365	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2366	break;
2367	case SVGA_FIFO_3D_CAPS_LAST:
2368	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2369	break;
2370	case SVGA_FIFO_GUEST_3D_HWVERSION:
2371	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2372	break;
2373	case SVGA_FIFO_FENCE_GOAL:
2374	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2375	break;
2376	case SVGA_FIFO_BUSY:
2377	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2378	break;
2379	default:
2380	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2381	break;
2382	}
2383
2384	return VINF_EM_RAW_EMULATE_INSTR;
2385	}
2386	# endif /* DEBUG_FIFO_ACCESS */
2387
2388	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2389	/**
2390	* HC access handler for the FIFO.
2391	*
2392	* @returns VINF_SUCCESS if the handler have carried out the operation.
2393	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2394	* @param pVM VM Handle.
2395	* @param pVCpu The cross context CPU structure for the calling EMT.
2396	* @param GCPhys The physical address the guest is writing to.
2397	* @param pvPhys The HC mapping of that address.
2398	* @param pvBuf What the guest is reading/writing.
2399	* @param cbBuf How much it's reading/writing.
2400	* @param enmAccessType The access type.
2401	* @param enmOrigin Who is making the access.
2402	* @param pvUser User argument.
2403	*/
2404	static DECLCALLBACK(VBOXSTRICTRC)
2405	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2406	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2407	{
2408	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2409	PVGASTATE pThis = (PVGASTATE)pvUser;
2410	AssertPtr(pThis);
2411
2412	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2413	/*
2414	* Wake up the FIFO thread as it might have work to do now.
2415	*/
2416	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2417	AssertLogRelRC(rc);
2418	# endif
2419
2420	# ifdef DEBUG_FIFO_ACCESS
2421	/*
2422	* When in debug-fifo-access mode, we do not disable the access handler,
2423	* but leave it on as we wish to catch all access.
2424	*/
2425	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2426	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2427	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2428	/*
2429	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2430	*/
2431	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2432	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2433	# endif
2434	if (RT_SUCCESS(rc))
2435	return VINF_PGM_HANDLER_DO_DEFAULT;
2436	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2437	return rc;
2438	}
2439	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2440
2441	#endif /* IN_RING3 */
2442
2443	#ifdef DEBUG_GMR_ACCESS
2444	# ifdef IN_RING3
2445
2446	/**
2447	* HC access handler for the FIFO.
2448	*
2449	* @returns VINF_SUCCESS if the handler have carried out the operation.
2450	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2451	* @param pVM VM Handle.
2452	* @param pVCpu The cross context CPU structure for the calling EMT.
2453	* @param GCPhys The physical address the guest is writing to.
2454	* @param pvPhys The HC mapping of that address.
2455	* @param pvBuf What the guest is reading/writing.
2456	* @param cbBuf How much it's reading/writing.
2457	* @param enmAccessType The access type.
2458	* @param enmOrigin Who is making the access.
2459	* @param pvUser User argument.
2460	*/
2461	static DECLCALLBACK(VBOXSTRICTRC)
2462	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2463	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2464	{
2465	PVGASTATE pThis = (PVGASTATE)pvUser;
2466	Assert(pThis);
2467	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2468	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2469
2470	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2471
2472	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2473	{
2474	PGMR pGMR = &pSVGAState->paGMR[i];
2475
2476	if (pGMR->numDescriptors)
2477	{
2478	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2479	{
2480	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2481	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2482	{
2483	/*
2484	* Turn off the write handler for this particular page and make it R/W.
2485	* Then return telling the caller to restart the guest instruction.
2486	*/
2487	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2488	AssertRC(rc);
2489	goto end;
2490	}
2491	}
2492	}
2493	}
2494	end:
2495	return VINF_PGM_HANDLER_DO_DEFAULT;
2496	}
2497
2498	/* Callback handler for VMR3ReqCallWaitU */
2499	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2500	{
2501	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2502	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2503	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2504	int rc;
2505
2506	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2507	{
2508	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2509	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2510	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2511	AssertRC(rc);
2512	}
2513	return VINF_SUCCESS;
2514	}
2515
2516	/* Callback handler for VMR3ReqCallWaitU */
2517	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2518	{
2519	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2520	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2521	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2522
2523	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2524	{
2525	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2526	AssertRC(rc);
2527	}
2528	return VINF_SUCCESS;
2529	}
2530
2531	/* Callback handler for VMR3ReqCallWaitU */
2532	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2533	{
2534	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2535
2536	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2537	{
2538	PGMR pGMR = &pSVGAState->paGMR[i];
2539
2540	if (pGMR->numDescriptors)
2541	{
2542	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2543	{
2544	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2545	AssertRC(rc);
2546	}
2547	}
2548	}
2549	return VINF_SUCCESS;
2550	}
2551
2552	# endif /* IN_RING3 */
2553	#endif /* DEBUG_GMR_ACCESS */
2554
2555	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2556
2557	#ifdef IN_RING3
2558
2559
2560	/**
2561	* Common worker for changing the pointer shape.
2562	*
2563	* @param pThis The VGA instance data.
2564	* @param pSVGAState The VMSVGA ring-3 instance data.
2565	* @param fAlpha Whether there is alpha or not.
2566	* @param xHot Hotspot x coordinate.
2567	* @param yHot Hotspot y coordinate.
2568	* @param cx Width.
2569	* @param cy Height.
2570	* @param pbData Heap copy of the cursor data. Consumed.
2571	* @param cbData The size of the data.
2572	*/
2573	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2574	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2575	{
2576	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2577	#ifdef LOG_ENABLED
2578	if (LogIs2Enabled())
2579	{
2580	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2581	if (!fAlpha)
2582	{
2583	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2584	for (uint32_t y = 0; y < cy; y++)
2585	{
2586	Log2(("%3u:", y));
2587	uint8_t const pbLine = &pbData[y cbAndLine];
2588	for (uint32_t x = 0; x < cx; x += 8)
2589	{
2590	uint8_t b = pbLine[x / 8];
2591	char szByte[12];
2592	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2593	szByte[1] = b & 0x40 ? '*' : ' ';
2594	szByte[2] = b & 0x20 ? '*' : ' ';
2595	szByte[3] = b & 0x10 ? '*' : ' ';
2596	szByte[4] = b & 0x08 ? '*' : ' ';
2597	szByte[5] = b & 0x04 ? '*' : ' ';
2598	szByte[6] = b & 0x02 ? '*' : ' ';
2599	szByte[7] = b & 0x01 ? '*' : ' ';
2600	szByte[8] = '\0';
2601	Log2(("%s", szByte));
2602	}
2603	Log2(("\n"));
2604	}
2605	}
2606
2607	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2608	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2609	for (uint32_t y = 0; y < cy; y++)
2610	{
2611	Log2(("%3u:", y));
2612	uint32_t const pu32Line = &pu32Xor[y cx];
2613	for (uint32_t x = 0; x < cx; x++)
2614	Log2((" %08x", pu32Line[x]));
2615	Log2(("\n"));
2616	}
2617	}
2618	#endif
2619
2620	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2621	AssertRC(rc);
2622
2623	if (pSVGAState->Cursor.fActive)
2624	RTMemFree(pSVGAState->Cursor.pData);
2625
2626	pSVGAState->Cursor.fActive = true;
2627	pSVGAState->Cursor.xHotspot = xHot;
2628	pSVGAState->Cursor.yHotspot = yHot;
2629	pSVGAState->Cursor.width = cx;
2630	pSVGAState->Cursor.height = cy;
2631	pSVGAState->Cursor.cbData = cbData;
2632	pSVGAState->Cursor.pData = pbData;
2633	}
2634
2635
2636	/**
2637	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2638	*
2639	* @param pThis The VGA instance data.
2640	* @param pSVGAState The VMSVGA ring-3 instance data.
2641	* @param pCursor The cursor.
2642	* @param pbSrcAndMask The AND mask.
2643	* @param cbSrcAndLine The scanline length of the AND mask.
2644	* @param pbSrcXorMask The XOR mask.
2645	* @param cbSrcXorLine The scanline length of the XOR mask.
2646	*/
2647	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2648	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2649	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2650	{
2651	uint32_t const cx = pCursor->width;
2652	uint32_t const cy = pCursor->height;
2653
2654	/*
2655	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2656	* The AND data uses 8-bit aligned scanlines.
2657	* The XOR data must be starting on a 32-bit boundrary.
2658	*/
2659	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2660	uint32_t cbDstAndMask = cbDstAndLine * cy;
2661	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2662	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2663
2664	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2665	AssertReturnVoid(pbCopy);
2666
2667	/* Convert the AND mask. */
2668	uint8_t *pbDst = pbCopy;
2669	uint8_t const *pbSrc = pbSrcAndMask;
2670	switch (pCursor->andMaskDepth)
2671	{
2672	case 1:
2673	if (cbSrcAndLine == cbDstAndLine)
2674	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2675	else
2676	{
2677	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2678	for (uint32_t y = 0; y < cy; y++)
2679	{
2680	memcpy(pbDst, pbSrc, cbDstAndLine);
2681	pbDst += cbDstAndLine;
2682	pbSrc += cbSrcAndLine;
2683	}
2684	}
2685	break;
2686	/* Should take the XOR mask into account for the multi-bit AND mask. */
2687	case 8:
2688	for (uint32_t y = 0; y < cy; y++)
2689	{
2690	for (uint32_t x = 0; x < cx; )
2691	{
2692	uint8_t bDst = 0;
2693	uint8_t fBit = 1;
2694	do
2695	{
2696	uintptr_t const idxPal = pbSrc[x] * 3;
2697	if ((( pThis->last_palette[idxPal]
2698	\| (pThis->last_palette[idxPal] >> 8)
2699	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2700	bDst \|= fBit;
2701	fBit <<= 1;
2702	x++;
2703	} while (x < cx && (x & 7));
2704	pbDst[(x - 1) / 8] = bDst;
2705	}
2706	pbDst += cbDstAndLine;
2707	pbSrc += cbSrcAndLine;
2708	}
2709	break;
2710	case 15:
2711	for (uint32_t y = 0; y < cy; y++)
2712	{
2713	for (uint32_t x = 0; x < cx; )
2714	{
2715	uint8_t bDst = 0;
2716	uint8_t fBit = 1;
2717	do
2718	{
2719	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2720	bDst \|= fBit;
2721	fBit <<= 1;
2722	x++;
2723	} while (x < cx && (x & 7));
2724	pbDst[(x - 1) / 8] = bDst;
2725	}
2726	pbDst += cbDstAndLine;
2727	pbSrc += cbSrcAndLine;
2728	}
2729	break;
2730	case 16:
2731	for (uint32_t y = 0; y < cy; y++)
2732	{
2733	for (uint32_t x = 0; x < cx; )
2734	{
2735	uint8_t bDst = 0;
2736	uint8_t fBit = 1;
2737	do
2738	{
2739	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2740	bDst \|= fBit;
2741	fBit <<= 1;
2742	x++;
2743	} while (x < cx && (x & 7));
2744	pbDst[(x - 1) / 8] = bDst;
2745	}
2746	pbDst += cbDstAndLine;
2747	pbSrc += cbSrcAndLine;
2748	}
2749	break;
2750	case 24:
2751	for (uint32_t y = 0; y < cy; y++)
2752	{
2753	for (uint32_t x = 0; x < cx; )
2754	{
2755	uint8_t bDst = 0;
2756	uint8_t fBit = 1;
2757	do
2758	{
2759	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2760	bDst \|= fBit;
2761	fBit <<= 1;
2762	x++;
2763	} while (x < cx && (x & 7));
2764	pbDst[(x - 1) / 8] = bDst;
2765	}
2766	pbDst += cbDstAndLine;
2767	pbSrc += cbSrcAndLine;
2768	}
2769	break;
2770	case 32:
2771	for (uint32_t y = 0; y < cy; y++)
2772	{
2773	for (uint32_t x = 0; x < cx; )
2774	{
2775	uint8_t bDst = 0;
2776	uint8_t fBit = 1;
2777	do
2778	{
2779	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2780	bDst \|= fBit;
2781	fBit <<= 1;
2782	x++;
2783	} while (x < cx && (x & 7));
2784	pbDst[(x - 1) / 8] = bDst;
2785	}
2786	pbDst += cbDstAndLine;
2787	pbSrc += cbSrcAndLine;
2788	}
2789	break;
2790	default:
2791	RTMemFree(pbCopy);
2792	AssertFailedReturnVoid();
2793	}
2794
2795	/* Convert the XOR mask. */
2796	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2797	pbSrc = pbSrcXorMask;
2798	switch (pCursor->xorMaskDepth)
2799	{
2800	case 1:
2801	for (uint32_t y = 0; y < cy; y++)
2802	{
2803	for (uint32_t x = 0; x < cx; )
2804	{
2805	/* most significant bit is the left most one. */
2806	uint8_t bSrc = pbSrc[x / 8];
2807	do
2808	{
2809	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2810	bSrc <<= 1;
2811	x++;
2812	} while ((x & 7) && x < cx);
2813	}
2814	pbSrc += cbSrcXorLine;
2815	}
2816	break;
2817	case 8:
2818	for (uint32_t y = 0; y < cy; y++)
2819	{
2820	for (uint32_t x = 0; x < cx; x++)
2821	{
2822	uint32_t u = pThis->last_palette[pbSrc[x]];
2823	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2824	}
2825	pbSrc += cbSrcXorLine;
2826	}
2827	break;
2828	case 15: /* Src: RGB-5-5-5 */
2829	for (uint32_t y = 0; y < cy; y++)
2830	{
2831	for (uint32_t x = 0; x < cx; x++)
2832	{
2833	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2834	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2835	((uValue >> 5) & 0x1f) << 3,
2836	((uValue >> 10) & 0x1f) << 3, 0);
2837	}
2838	pbSrc += cbSrcXorLine;
2839	}
2840	break;
2841	case 16: /* Src: RGB-5-6-5 */
2842	for (uint32_t y = 0; y < cy; y++)
2843	{
2844	for (uint32_t x = 0; x < cx; x++)
2845	{
2846	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2847	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2848	((uValue >> 5) & 0x3f) << 2,
2849	((uValue >> 11) & 0x1f) << 3, 0);
2850	}
2851	pbSrc += cbSrcXorLine;
2852	}
2853	break;
2854	case 24:
2855	for (uint32_t y = 0; y < cy; y++)
2856	{
2857	for (uint32_t x = 0; x < cx; x++)
2858	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2859	pbSrc += cbSrcXorLine;
2860	}
2861	break;
2862	case 32:
2863	for (uint32_t y = 0; y < cy; y++)
2864	{
2865	for (uint32_t x = 0; x < cx; x++)
2866	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2867	pbSrc += cbSrcXorLine;
2868	}
2869	break;
2870	default:
2871	RTMemFree(pbCopy);
2872	AssertFailedReturnVoid();
2873	}
2874
2875	/*
2876	* Pass it to the frontend/whatever.
2877	*/
2878	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2879	}
2880
2881
2882	/**
2883	* Worker for vmsvgaR3FifoThread that handles an external command.
2884	*
2885	* @param pThis VGA device instance data.
2886	*/
2887	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2888	{
2889	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2890	switch (pThis->svga.u8FIFOExtCommand)
2891	{
2892	case VMSVGA_FIFO_EXTCMD_RESET:
2893	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2894	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2895	# ifdef VBOX_WITH_VMSVGA3D
2896	if (pThis->svga.f3DEnabled)
2897	{
2898	/* The 3d subsystem must be reset from the fifo thread. */
2899	vmsvga3dReset(pThis);
2900	}
2901	# endif
2902	break;
2903
2904	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2905	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2906	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2907	# ifdef VBOX_WITH_VMSVGA3D
2908	if (pThis->svga.f3DEnabled)
2909	{
2910	/* The 3d subsystem must be shut down from the fifo thread. */
2911	vmsvga3dTerminate(pThis);
2912	}
2913	# endif
2914	break;
2915
2916	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2917	{
2918	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2919	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2920	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2921	vmsvgaSaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM);
2922	# ifdef VBOX_WITH_VMSVGA3D
2923	if (pThis->svga.f3DEnabled)
2924	vmsvga3dSaveExec(pThis->pDevInsR3, pThis, pSSM);
2925	# endif
2926	break;
2927	}
2928
2929	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2930	{
2931	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2932	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2933	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2934	vmsvgaLoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2935	# ifdef VBOX_WITH_VMSVGA3D
2936	if (pThis->svga.f3DEnabled)
2937	vmsvga3dLoadExec(pThis->pDevInsR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2938	# endif
2939	break;
2940	}
2941
2942	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2943	{
2944	# ifdef VBOX_WITH_VMSVGA3D
2945	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2946	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2947	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2948	# endif
2949	break;
2950	}
2951
2952
2953	default:
2954	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2955	break;
2956	}
2957
2958	/*
2959	* Signal the end of the external command.
2960	*/
2961	pThis->svga.pvFIFOExtCmdParam = NULL;
2962	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2963	ASMMemoryFence(); /* paranoia^2 */
2964	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2965	AssertLogRelRC(rc);
2966	}
2967
2968	/**
2969	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2970	* doing a job on the FIFO thread (even when it's officially suspended).
2971	*
2972	* @returns VBox status code (fully asserted).
2973	* @param pDevIns The device instance.
2974	* @param pThis VGA device instance data.
2975	* @param uExtCmd The command to execute on the FIFO thread.
2976	* @param pvParam Pointer to command parameters.
2977	* @param cMsWait The time to wait for the command, given in
2978	* milliseconds.
2979	*/
2980	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2981	{
2982	Assert(cMsWait >= RT_MS_1SEC * 5);
2983	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2984	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2985
2986	int rc;
2987	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2988	PDMTHREADSTATE enmState = pThread->enmState;
2989	if (enmState == PDMTHREADSTATE_SUSPENDED)
2990	{
2991	/*
2992	* The thread is suspended, we have to temporarily wake it up so it can
2993	* perform the task.
2994	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2995	*/
2996	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2997	/* Post the request. */
2998	pThis->svga.fFifoExtCommandWakeup = true;
2999	pThis->svga.pvFIFOExtCmdParam = pvParam;
3000	pThis->svga.u8FIFOExtCommand = uExtCmd;
3001	ASMMemoryFence(); /* paranoia^3 */
3002
3003	/* Resume the thread. */
3004	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3005	AssertLogRelRC(rc);
3006	if (RT_SUCCESS(rc))
3007	{
3008	/* Wait. Take care in case the semaphore was already posted (same as below). */
3009	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3010	if ( rc == VINF_SUCCESS
3011	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3012	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3013	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3014	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3015
3016	/* suspend the thread */
3017	pThis->svga.fFifoExtCommandWakeup = false;
3018	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3019	AssertLogRelRC(rc2);
3020	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3021	rc = rc2;
3022	}
3023	pThis->svga.fFifoExtCommandWakeup = false;
3024	pThis->svga.pvFIFOExtCmdParam = NULL;
3025	}
3026	else if (enmState == PDMTHREADSTATE_RUNNING)
3027	{
3028	/*
3029	* The thread is running, should only happen during reset and vmsvga3dsfc.
3030	* We ASSUME not racing code here, both wrt thread state and ext commands.
3031	*/
3032	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3033	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3034
3035	/* Post the request. */
3036	pThis->svga.pvFIFOExtCmdParam = pvParam;
3037	pThis->svga.u8FIFOExtCommand = uExtCmd;
3038	ASMMemoryFence(); /* paranoia^2 */
3039	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3040	AssertLogRelRC(rc);
3041
3042	/* Wait. Take care in case the semaphore was already posted (same as above). */
3043	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3044	if ( rc == VINF_SUCCESS
3045	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3046	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3047	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3048	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3049
3050	pThis->svga.pvFIFOExtCmdParam = NULL;
3051	}
3052	else
3053	{
3054	/*
3055	* Something is wrong with the thread!
3056	*/
3057	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3058	rc = VERR_INVALID_STATE;
3059	}
3060	return rc;
3061	}
3062
3063
3064	/**
3065	* Marks the FIFO non-busy, notifying any waiting EMTs.
3066	*
3067	* @param pThis The VGA state.
3068	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3069	* @param offFifoMin The start byte offset of the command FIFO.
3070	*/
3071	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3072	{
3073	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3074	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3075	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3076
3077	/* Wake up any waiting EMTs. */
3078	if (pSVGAState->cBusyDelayedEmts > 0)
3079	{
3080	#ifdef VMSVGA_USE_EMT_HALT_CODE
3081	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3082	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3083	if (idCpu != NIL_VMCPUID)
3084	{
3085	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3086	while (idCpu-- > 0)
3087	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3088	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3089	}
3090	#else
3091	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3092	AssertRC(rc2);
3093	#endif
3094	}
3095	}
3096
3097	/**
3098	* Reads (more) payload into the command buffer.
3099	*
3100	* @returns pbBounceBuf on success
3101	* @retval (void *)1 if the thread was requested to stop.
3102	* @retval NULL on FIFO error.
3103	*
3104	* @param cbPayloadReq The number of bytes of payload requested.
3105	* @param pFIFO The FIFO.
3106	* @param offCurrentCmd The FIFO byte offset of the current command.
3107	* @param offFifoMin The start byte offset of the command FIFO.
3108	* @param offFifoMax The end byte offset of the command FIFO.
3109	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3110	* always sufficient size.
3111	* @param pcbAlreadyRead How much payload we've already read into the bounce
3112	* buffer. (We will NEVER re-read anything.)
3113	* @param pThread The calling PDM thread handle.
3114	* @param pThis The VGA state.
3115	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3116	* statistics collection.
3117	*/
3118	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3119	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3120	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3121	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3122	{
3123	Assert(pbBounceBuf);
3124	Assert(pcbAlreadyRead);
3125	Assert(offFifoMin < offFifoMax);
3126	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3127	Assert(offFifoMax <= pThis->svga.cbFIFO);
3128
3129	/*
3130	* Check if the requested payload size has already been satisfied .
3131	* .
3132	* When called to read more, the caller is responsible for making sure the .
3133	* new command size (cbRequsted) never is smaller than what has already .
3134	* been read.
3135	*/
3136	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3137	if (cbPayloadReq <= cbAlreadyRead)
3138	{
3139	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3140	return pbBounceBuf;
3141	}
3142
3143	/*
3144	* Commands bigger than the fifo buffer are invalid.
3145	*/
3146	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3147	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3148	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3149	NULL);
3150
3151	/*
3152	* Move offCurrentCmd past the command dword.
3153	*/
3154	offCurrentCmd += sizeof(uint32_t);
3155	if (offCurrentCmd >= offFifoMax)
3156	offCurrentCmd = offFifoMin;
3157
3158	/*
3159	* Do we have sufficient payload data available already?
3160	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3161	*/
3162	uint32_t cbAfter, cbBefore;
3163	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3164	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3165	if (offNextCmd >= offCurrentCmd)
3166	{
3167	if (RT_LIKELY(offNextCmd < offFifoMax))
3168	cbAfter = offNextCmd - offCurrentCmd;
3169	else
3170	{
3171	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3172	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3173	offNextCmd, offFifoMin, offFifoMax));
3174	cbAfter = offFifoMax - offCurrentCmd;
3175	}
3176	cbBefore = 0;
3177	}
3178	else
3179	{
3180	cbAfter = offFifoMax - offCurrentCmd;
3181	if (offNextCmd >= offFifoMin)
3182	cbBefore = offNextCmd - offFifoMin;
3183	else
3184	{
3185	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3186	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3187	offNextCmd, offFifoMin, offFifoMax));
3188	cbBefore = 0;
3189	}
3190	}
3191	if (cbAfter + cbBefore < cbPayloadReq)
3192	{
3193	/*
3194	* Insufficient, must wait for it to arrive.
3195	*/
3196	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3197	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3198	for (uint32_t i = 0;; i++)
3199	{
3200	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3201	{
3202	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3203	return (void *)(uintptr_t)1;
3204	}
3205	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3206	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3207
3208	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3209
3210	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3211	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3212	if (offNextCmd >= offCurrentCmd)
3213	{
3214	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3215	cbBefore = 0;
3216	}
3217	else
3218	{
3219	cbAfter = offFifoMax - offCurrentCmd;
3220	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3221	}
3222
3223	if (cbAfter + cbBefore >= cbPayloadReq)
3224	break;
3225	}
3226	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3227	}
3228
3229	/*
3230	* Copy out the memory and update what pcbAlreadyRead points to.
3231	*/
3232	if (cbAfter >= cbPayloadReq)
3233	memcpy(pbBounceBuf + cbAlreadyRead,
3234	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3235	cbPayloadReq - cbAlreadyRead);
3236	else
3237	{
3238	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3239	if (cbAlreadyRead < cbAfter)
3240	{
3241	memcpy(pbBounceBuf + cbAlreadyRead,
3242	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3243	cbAfter - cbAlreadyRead);
3244	cbAlreadyRead = cbAfter;
3245	}
3246	memcpy(pbBounceBuf + cbAlreadyRead,
3247	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3248	cbPayloadReq - cbAlreadyRead);
3249	}
3250	*pcbAlreadyRead = cbPayloadReq;
3251	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3252	return pbBounceBuf;
3253	}
3254
3255
3256	/**
3257	* Sends cursor position and visibility information from the FIFO to the front-end.
3258	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3259	*/
3260	static uint32_t
3261	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3262	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3263	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3264	{
3265	/*
3266	* Check if the cursor update counter has changed and try get a stable
3267	* set of values if it has. This is race-prone, especially consindering
3268	* the screen ID, but little we can do about that.
3269	*/
3270	uint32_t x, y, fVisible, idScreen;
3271	for (uint32_t i = 0; ; i++)
3272	{
3273	x = pFIFO[SVGA_FIFO_CURSOR_X];
3274	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3275	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3276	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3277	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3278	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3279	\|\| i > 3)
3280	break;
3281	if (i == 0)
3282	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3283	ASMNopPause();
3284	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3285	}
3286
3287	/*
3288	* Check if anything has changed, as calling into pDrv is not light-weight.
3289	*/
3290	if ( *pxLast == x
3291	&& *pyLast == y
3292	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3293	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3294	else
3295	{
3296	/*
3297	* Detected changes.
3298	*
3299	* We handle global, not per-screen visibility information by sending
3300	* pfnVBVAMousePointerShape without shape data.
3301	*/
3302	*pxLast = x;
3303	*pyLast = y;
3304	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3305	if (idScreen != SVGA_ID_INVALID)
3306	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3307	else if (*pfLastVisible != fVisible)
3308	{
3309	LogRel2(("vmsvgaFIFOUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3310	*pfLastVisible = fVisible;
3311	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3312	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3313	}
3314	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3315	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3316	}
3317
3318	/*
3319	* Update done. Signal this to the guest.
3320	*/
3321	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3322
3323	return uCursorUpdateCount;
3324	}
3325
3326
3327	/**
3328	* Checks if there is work to be done, either cursor updating or FIFO commands.
3329	*
3330	* @returns true if pending work, false if not.
3331	* @param pFIFO The FIFO to examine.
3332	* @param uLastCursorCount The last cursor update counter value.
3333	*/
3334	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3335	{
3336	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3337	return true;
3338
3339	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3340	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3341	return true;
3342
3343	return false;
3344	}
3345
3346
3347	/**
3348	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3349	*
3350	* @param pThis The VGA state.
3351	*/
3352	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3353	{
3354	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3355	to recheck it before doing the signalling. */
3356	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3357	AssertReturnVoid(pFIFO);
3358	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3359	&& pThis->svga.fFIFOThreadSleeping)
3360	{
3361	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3362	AssertRC(rc);
3363	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3364	}
3365	}
3366
3367
3368	/* The async FIFO handling thread. */
3369	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3370	{
3371	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3372	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3373	int rc;
3374
3375	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3376	return VINF_SUCCESS;
3377
3378	/*
3379	* Special mode where we only execute an external command and the go back
3380	* to being suspended. Currently, all ext cmds ends up here, with the reset
3381	* one also being eligble for runtime execution further down as well.
3382	*/
3383	if (pThis->svga.fFifoExtCommandWakeup)
3384	{
3385	vmsvgaR3FifoHandleExtCmd(pThis);
3386	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3387	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3388	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3389	else
3390	vmsvgaR3FifoHandleExtCmd(pThis);
3391	return VINF_SUCCESS;
3392	}
3393
3394
3395	/*
3396	* Signal the semaphore to make sure we don't wait for 250ms after a
3397	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3398	*/
3399	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3400
3401	/*
3402	* Allocate a bounce buffer for command we get from the FIFO.
3403	* (All code must return via the end of the function to free this buffer.)
3404	*/
3405	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3406	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3407
3408	/*
3409	* Polling/sleep interval config.
3410	*
3411	* We wait for an a short interval if the guest has recently given us work
3412	* to do, but the interval increases the longer we're kept idle. Once we've
3413	* reached the refresh timer interval, we'll switch to extended waits,
3414	* depending on it or the guest to kick us into action when needed.
3415	*
3416	* Should the refresh time go fishing, we'll just continue increasing the
3417	* sleep length till we reaches the 250 ms max after about 16 seconds.
3418	*/
3419	RTMSINTERVAL const cMsMinSleep = 16;
3420	RTMSINTERVAL const cMsIncSleep = 2;
3421	RTMSINTERVAL const cMsMaxSleep = 250;
3422	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3423	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3424
3425	/*
3426	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3427	*
3428	* Initialize with values that will detect an update from the guest.
3429	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3430	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3431	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3432	*/
3433	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3434	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3435	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3436	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3437	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3438
3439	/*
3440	* The FIFO loop.
3441	*/
3442	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3443	bool fBadOrDisabledFifo = false;
3444	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3445	{
3446	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3447	/*
3448	* Should service the run loop every so often.
3449	*/
3450	if (pThis->svga.f3DEnabled)
3451	vmsvga3dCocoaServiceRunLoop();
3452	# endif
3453
3454	/*
3455	* Unless there's already work pending, go to sleep for a short while.
3456	* (See polling/sleep interval config above.)
3457	*/
3458	if ( fBadOrDisabledFifo
3459	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3460	{
3461	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3462	Assert(pThis->cMilliesRefreshInterval > 0);
3463	if (cMsSleep < pThis->cMilliesRefreshInterval)
3464	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3465	else
3466	{
3467	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3468	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3469	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3470	# endif
3471	if ( !fBadOrDisabledFifo
3472	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3473	rc = VINF_SUCCESS;
3474	else
3475	{
3476	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3477	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3478	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3479	}
3480	}
3481	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3482	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3483	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3484	{
3485	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3486	break;
3487	}
3488	}
3489	else
3490	rc = VINF_SUCCESS;
3491	fBadOrDisabledFifo = false;
3492	if (rc == VERR_TIMEOUT)
3493	{
3494	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3495	{
3496	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3497	continue;
3498	}
3499	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3500
3501	Log(("vmsvgaFIFOLoop: timeout\n"));
3502	}
3503	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3504	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3505	cMsSleep = cMsMinSleep;
3506
3507	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3508	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3509	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3510
3511	/*
3512	* Handle external commands (currently only reset).
3513	*/
3514	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3515	{
3516	vmsvgaR3FifoHandleExtCmd(pThis);
3517	continue;
3518	}
3519
3520	/*
3521	* The device must be enabled and configured.
3522	*/
3523	if ( !pThis->svga.fEnabled
3524	\|\| !pThis->svga.fConfigured)
3525	{
3526	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3527	fBadOrDisabledFifo = true;
3528	cMsSleep = cMsMaxSleep; /* cheat */
3529	continue;
3530	}
3531
3532	/*
3533	* Get and check the min/max values. We ASSUME that they will remain
3534	* unchanged while we process requests. A further ASSUMPTION is that
3535	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3536	* we don't read it back while in the loop.
3537	*/
3538	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3539	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3540	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3541	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3542	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3543	\|\| offFifoMax <= offFifoMin
3544	\|\| offFifoMax > pThis->svga.cbFIFO
3545	\|\| (offFifoMax & 3) != 0
3546	\|\| (offFifoMin & 3) != 0
3547	\|\| offCurrentCmd < offFifoMin
3548	\|\| offCurrentCmd > offFifoMax))
3549	{
3550	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3551	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3552	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3553	fBadOrDisabledFifo = true;
3554	continue;
3555	}
3556	RT_UNTRUSTED_VALIDATED_FENCE();
3557	if (RT_UNLIKELY(offCurrentCmd & 3))
3558	{
3559	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3560	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3561	offCurrentCmd &= ~UINT32_C(3);
3562	}
3563
3564	/*
3565	* Update the cursor position before we start on the FIFO commands.
3566	*/
3567	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3568	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3569	{
3570	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3571	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3572	{ /* halfways likely */ }
3573	else
3574	{
3575	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3576	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3577	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3578	}
3579	}
3580
3581	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3582	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3583	*
3584	* Will break out of the switch on failure.
3585	* Will restart and quit the loop if the thread was requested to stop.
3586	*
3587	* @param a_PtrVar Request variable pointer.
3588	* @param a_Type Request typedef (not pointer) for casting.
3589	* @param a_cbPayloadReq How much payload to fetch.
3590	* @remarks Accesses a bunch of variables in the current scope!
3591	*/
3592	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3593	if (1) { \
3594	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3595	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3596	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3597	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3598	} else do {} while (0)
3599	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3600	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3601	* buffer after figuring out the actual command size.
3602	*
3603	* Will break out of the switch on failure.
3604	*
3605	* @param a_PtrVar Request variable pointer.
3606	* @param a_Type Request typedef (not pointer) for casting.
3607	* @param a_cbPayloadReq How much payload to fetch.
3608	* @remarks Accesses a bunch of variables in the current scope!
3609	*/
3610	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3611	if (1) { \
3612	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3613	} else do {} while (0)
3614
3615	/*
3616	* Mark the FIFO as busy.
3617	*/
3618	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3619	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3620	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3621
3622	/*
3623	* Execute all queued FIFO commands.
3624	* Quit if pending external command or changes in the thread state.
3625	*/
3626	bool fDone = false;
3627	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3628	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3629	{
3630	uint32_t cbPayload = 0;
3631	uint32_t u32IrqStatus = 0;
3632
3633	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3634
3635	/* First check any pending actions. */
3636	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3637	{
3638	vmsvgaChangeMode(pThis);
3639	# ifdef VBOX_WITH_VMSVGA3D
3640	if (pThis->svga.p3dState != NULL)
3641	vmsvga3dChangeMode(pThis);
3642	# endif
3643	}
3644
3645	/* Check for pending external commands (reset). */
3646	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3647	break;
3648
3649	/*
3650	* Process the command.
3651	*/
3652	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3653	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3654	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3655	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3656	switch (enmCmdId)
3657	{
3658	case SVGA_CMD_INVALID_CMD:
3659	/* Nothing to do. */
3660	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3661	break;
3662
3663	case SVGA_CMD_FENCE:
3664	{
3665	SVGAFifoCmdFence *pCmdFence;
3666	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3667	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3668	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3669	{
3670	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3671	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3672
3673	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3674	{
3675	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3676	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3677	}
3678	else
3679	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3680	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3681	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3682	{
3683	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3684	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3685	}
3686	}
3687	else
3688	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3689	break;
3690	}
3691	case SVGA_CMD_UPDATE:
3692	case SVGA_CMD_UPDATE_VERBOSE:
3693	{
3694	SVGAFifoCmdUpdate *pUpdate;
3695	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3696	if (enmCmdId == SVGA_CMD_UPDATE)
3697	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3698	else
3699	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3700	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3701	/** @todo Multiple screens? */
3702	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3703	AssertBreak(pScreen);
3704	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3705	break;
3706	}
3707
3708	case SVGA_CMD_DEFINE_CURSOR:
3709	{
3710	/* Followed by bitmap data. */
3711	SVGAFifoCmdDefineCursor *pCursor;
3712	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3713	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3714
3715	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3716	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3717	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3718	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3719	AssertBreak(pCursor->andMaskDepth <= 32);
3720	AssertBreak(pCursor->xorMaskDepth <= 32);
3721	RT_UNTRUSTED_VALIDATED_FENCE();
3722
3723	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3724	uint32_t cbAndMask = cbAndLine * pCursor->height;
3725	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3726	uint32_t cbXorMask = cbXorLine * pCursor->height;
3727	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3728
3729	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3730	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3731	break;
3732	}
3733
3734	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3735	{
3736	/* Followed by bitmap data. */
3737	uint32_t cbCursorShape, cbAndMask;
3738	uint8_t *pCursorCopy;
3739	uint32_t cbCmd;
3740
3741	SVGAFifoCmdDefineAlphaCursor *pCursor;
3742	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3743	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3744
3745	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3746
3747	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3748	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3749	RT_UNTRUSTED_VALIDATED_FENCE();
3750
3751	/* Refetch the bitmap data as well. */
3752	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3753	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3754	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3755
3756	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3757	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3758	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3759	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3760
3761	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3762	AssertBreak(pCursorCopy);
3763
3764	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3765	memset(pCursorCopy, 0xff, cbAndMask);
3766	/* Colour data */
3767	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3768
3769	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3770	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3771	break;
3772	}
3773
3774	case SVGA_CMD_ESCAPE:
3775	{
3776	/* Followed by nsize bytes of data. */
3777	SVGAFifoCmdEscape *pEscape;
3778	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3779	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3780
3781	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3782	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3783	RT_UNTRUSTED_VALIDATED_FENCE();
3784	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3785	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3786
3787	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3788	{
3789	AssertBreak(pEscape->size >= sizeof(uint32_t));
3790	RT_UNTRUSTED_VALIDATED_FENCE();
3791	uint32_t cmd = (uint32_t )(pEscape + 1);
3792	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3793
3794	switch (cmd)
3795	{
3796	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3797	{
3798	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3799	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3800	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3801
3802	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3803	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3804	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3805
3806	RT_NOREF_PV(pVideoCmd);
3807	break;
3808
3809	}
3810
3811	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3812	{
3813	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3814	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3815	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3816	RT_NOREF_PV(pVideoCmd);
3817	break;
3818	}
3819
3820	default:
3821	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3822	break;
3823	}
3824	}
3825	else
3826	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3827
3828	break;
3829	}
3830	# ifdef VBOX_WITH_VMSVGA3D
3831	case SVGA_CMD_DEFINE_GMR2:
3832	{
3833	SVGAFifoCmdDefineGMR2 *pCmd;
3834	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3835	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3836	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3837
3838	/* Validate current GMR id. */
3839	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3840	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3841	RT_UNTRUSTED_VALIDATED_FENCE();
3842
3843	if (!pCmd->numPages)
3844	{
3845	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3846	vmsvgaGMRFree(pThis, pCmd->gmrId);
3847	}
3848	else
3849	{
3850	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3851	if (pGMR->cMaxPages)
3852	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3853
3854	/* Not sure if we should always free the descriptor, but for simplicity
3855	we do so if the new size is smaller than the current. */
3856	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3857	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3858	vmsvgaGMRFree(pThis, pCmd->gmrId);
3859
3860	pGMR->cMaxPages = pCmd->numPages;
3861	/* The rest is done by the REMAP_GMR2 command. */
3862	}
3863	break;
3864	}
3865
3866	case SVGA_CMD_REMAP_GMR2:
3867	{
3868	/* Followed by page descriptors or guest ptr. */
3869	SVGAFifoCmdRemapGMR2 *pCmd;
3870	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3871	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3872
3873	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3874	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3875	RT_UNTRUSTED_VALIDATED_FENCE();
3876
3877	/* Calculate the size of what comes after next and fetch it. */
3878	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3879	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3880	cbCmd += sizeof(SVGAGuestPtr);
3881	else
3882	{
3883	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3884	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3885	{
3886	cbCmd += cbPageDesc;
3887	pCmd->numPages = 1;
3888	}
3889	else
3890	{
3891	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3892	cbCmd += cbPageDesc * pCmd->numPages;
3893	}
3894	}
3895	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3896
3897	/* Validate current GMR id and size. */
3898	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3899	RT_UNTRUSTED_VALIDATED_FENCE();
3900	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3901	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3902	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3903	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3904
3905	if (pCmd->numPages == 0)
3906	break;
3907
3908	/** @todo Move to a separate function vmsvgaGMRRemap() */
3909
3910	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3911	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3912
3913	/*
3914	* We flatten the existing descriptors into a page array, overwrite the
3915	* pages specified in this command and then recompress the descriptor.
3916	*/
3917	/** @todo Optimize the GMR remap algorithm! */
3918
3919	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3920	uint64_t *paNewPage64 = NULL;
3921	if (pGMR->paDesc)
3922	{
3923	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3924
3925	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3926	AssertBreak(paNewPage64);
3927
3928	uint32_t idxPage = 0;
3929	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3930	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3931	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3932	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3933	RT_UNTRUSTED_VALIDATED_FENCE();
3934	}
3935
3936	/* Free the old GMR if present. */
3937	if (pGMR->paDesc)
3938	RTMemFree(pGMR->paDesc);
3939
3940	/* Allocate the maximum amount possible (everything non-continuous) */
3941	PVMSVGAGMRDESCRIPTOR paDescs;
3942	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3943	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3944
3945	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3946	{
3947	/** @todo */
3948	AssertFailed();
3949	pGMR->numDescriptors = 0;
3950	}
3951	else
3952	{
3953	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3954	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3955	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3956
3957	if (paNewPage64)
3958	{
3959	/* Overwrite the old page array with the new page values. */
3960	if (fGCPhys64)
3961	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3962	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3963	else
3964	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3965	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3966
3967	/* Use the updated page array instead of the command data. */
3968	fGCPhys64 = true;
3969	paPages64 = paNewPage64;
3970	pCmd->numPages = cNewTotalPages;
3971	}
3972
3973	/* The first page. */
3974	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3975	* applied to paNewPage64. */
3976	RTGCPHYS GCPhys;
3977	if (fGCPhys64)
3978	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3979	else
3980	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3981	paDescs[0].GCPhys = GCPhys;
3982	paDescs[0].numPages = 1;
3983
3984	/* Subsequent pages. */
3985	uint32_t iDescriptor = 0;
3986	for (uint32_t i = 1; i < pCmd->numPages; i++)
3987	{
3988	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3989	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3990	else
3991	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3992
3993	/* Continuous physical memory? */
3994	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3995	{
3996	Assert(paDescs[iDescriptor].numPages);
3997	paDescs[iDescriptor].numPages++;
3998	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3999	}
4000	else
4001	{
4002	iDescriptor++;
4003	paDescs[iDescriptor].GCPhys = GCPhys;
4004	paDescs[iDescriptor].numPages = 1;
4005	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4006	}
4007	}
4008
4009	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4010	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4011	pGMR->numDescriptors = iDescriptor + 1;
4012	}
4013
4014	if (paNewPage64)
4015	RTMemFree(paNewPage64);
4016
4017	# ifdef DEBUG_GMR_ACCESS
4018	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4019	# endif
4020	break;
4021	}
4022	# endif // VBOX_WITH_VMSVGA3D
4023	case SVGA_CMD_DEFINE_SCREEN:
4024	{
4025	/* The size of this command is specified by the guest and depends on capabilities. */
4026	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4027
4028	SVGAFifoCmdDefineScreen *pCmd;
4029	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4030	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4031	RT_UNTRUSTED_VALIDATED_FENCE();
4032
4033	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4034	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4035	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4036
4037	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4038	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4039	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4040
4041	uint32_t const idScreen = pCmd->screen.id;
4042	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4043
4044	uint32_t const uWidth = pCmd->screen.size.width;
4045	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4046
4047	uint32_t const uHeight = pCmd->screen.size.height;
4048	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4049
4050	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4051	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4052	AssertBreak(cbWidth <= cbPitch);
4053
4054	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4055	AssertBreak(uScreenOffset < pThis->vram_size);
4056
4057	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4058	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4059	AssertBreak( (uHeight == 0 && cbPitch == 0)
4060	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4061	RT_UNTRUSTED_VALIDATED_FENCE();
4062
4063	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4064
4065	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4066
4067	pScreen->fDefined = true;
4068	pScreen->fModified = true;
4069	pScreen->fuScreen = pCmd->screen.flags;
4070	pScreen->idScreen = idScreen;
4071	if (!fBlank)
4072	{
4073	AssertBreak(uWidth > 0 && uHeight > 0);
4074
4075	pScreen->xOrigin = pCmd->screen.root.x;
4076	pScreen->yOrigin = pCmd->screen.root.y;
4077	pScreen->cWidth = uWidth;
4078	pScreen->cHeight = uHeight;
4079	pScreen->offVRAM = uScreenOffset;
4080	pScreen->cbPitch = cbPitch;
4081	pScreen->cBpp = 32;
4082	}
4083	else
4084	{
4085	/* Keep old values. */
4086	}
4087
4088	pThis->svga.fGFBRegisters = false;
4089	vmsvgaChangeMode(pThis);
4090	break;
4091	}
4092
4093	case SVGA_CMD_DESTROY_SCREEN:
4094	{
4095	SVGAFifoCmdDestroyScreen *pCmd;
4096	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4097	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4098
4099	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4100
4101	uint32_t const idScreen = pCmd->screenId;
4102	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4103	RT_UNTRUSTED_VALIDATED_FENCE();
4104
4105	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4106	pScreen->fModified = true;
4107	pScreen->fDefined = false;
4108	pScreen->idScreen = idScreen;
4109
4110	vmsvgaChangeMode(pThis);
4111	break;
4112	}
4113
4114	case SVGA_CMD_DEFINE_GMRFB:
4115	{
4116	SVGAFifoCmdDefineGMRFB *pCmd;
4117	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4118	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4119
4120	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4121	pSVGAState->GMRFB.ptr = pCmd->ptr;
4122	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4123	pSVGAState->GMRFB.format = pCmd->format;
4124	break;
4125	}
4126
4127	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4128	{
4129	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4130	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4131	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4132
4133	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4134	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4135
4136	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4137	RT_UNTRUSTED_VALIDATED_FENCE();
4138
4139	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4140	AssertBreak(pScreen);
4141
4142	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4143	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4144
4145	/* Clip destRect to the screen dimensions. */
4146	SVGASignedRect screenRect;
4147	screenRect.left = 0;
4148	screenRect.top = 0;
4149	screenRect.right = pScreen->cWidth;
4150	screenRect.bottom = pScreen->cHeight;
4151	SVGASignedRect clipRect = pCmd->destRect;
4152	vmsvgaClipRect(&screenRect, &clipRect);
4153	RT_UNTRUSTED_VALIDATED_FENCE();
4154
4155	uint32_t const width = clipRect.right - clipRect.left;
4156	uint32_t const height = clipRect.bottom - clipRect.top;
4157
4158	if ( width == 0
4159	\|\| height == 0)
4160	break; /* Nothing to do. */
4161
4162	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4163	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4164
4165	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4166	* Prepare parameters for vmsvgaGMRTransfer.
4167	*/
4168	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4169
4170	/* Destination: host buffer which describes the screen 0 VRAM.
4171	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4172	*/
4173	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4174	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4175	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4176	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4177	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4178	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4179	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4180	+ cbScanline * clipRect.top;
4181	int32_t const cbHstPitch = cbScanline;
4182
4183	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4184	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4185	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4186	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4187	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4188
4189	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4190	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4191	gstPtr, offGst, cbGstPitch,
4192	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4193	AssertRC(rc);
4194	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4195	break;
4196	}
4197
4198	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4199	{
4200	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4201	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4202	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4203
4204	/* Note! This can fetch 3d render results as well!! */
4205	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4206	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4207
4208	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4209	RT_UNTRUSTED_VALIDATED_FENCE();
4210
4211	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4212	AssertBreak(pScreen);
4213
4214	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4215	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4216
4217	/* Clip destRect to the screen dimensions. */
4218	SVGASignedRect screenRect;
4219	screenRect.left = 0;
4220	screenRect.top = 0;
4221	screenRect.right = pScreen->cWidth;
4222	screenRect.bottom = pScreen->cHeight;
4223	SVGASignedRect clipRect = pCmd->srcRect;
4224	vmsvgaClipRect(&screenRect, &clipRect);
4225	RT_UNTRUSTED_VALIDATED_FENCE();
4226
4227	uint32_t const width = clipRect.right - clipRect.left;
4228	uint32_t const height = clipRect.bottom - clipRect.top;
4229
4230	if ( width == 0
4231	\|\| height == 0)
4232	break; /* Nothing to do. */
4233
4234	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4235	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4236
4237	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4238	* Prepare parameters for vmsvgaGMRTransfer.
4239	*/
4240	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4241
4242	/* Source: host buffer which describes the screen 0 VRAM.
4243	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4244	*/
4245	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4246	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4247	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4248	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4249	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4250	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4251	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4252	+ cbScanline * clipRect.top;
4253	int32_t const cbHstPitch = cbScanline;
4254
4255	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4256	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4257	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4258	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4259	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4260
4261	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4262	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4263	gstPtr, offGst, cbGstPitch,
4264	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4265	AssertRC(rc);
4266	break;
4267	}
4268
4269	case SVGA_CMD_ANNOTATION_FILL:
4270	{
4271	SVGAFifoCmdAnnotationFill *pCmd;
4272	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4273	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4274
4275	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4276	pSVGAState->colorAnnotation = pCmd->color;
4277	break;
4278	}
4279
4280	case SVGA_CMD_ANNOTATION_COPY:
4281	{
4282	SVGAFifoCmdAnnotationCopy *pCmd;
4283	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4284	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4285
4286	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4287	AssertFailed();
4288	break;
4289	}
4290
4291	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4292
4293	default:
4294	# ifdef VBOX_WITH_VMSVGA3D
4295	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4296	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4297	{
4298	RT_UNTRUSTED_VALIDATED_FENCE();
4299
4300	/* All 3d commands start with a common header, which defines the size of the command. */
4301	SVGA3dCmdHeader *pHdr;
4302	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4303	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4304	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4305	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4306
4307	if (RT_LIKELY(pThis->svga.f3DEnabled))
4308	{ /* likely */ }
4309	else
4310	{
4311	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4312	break;
4313	}
4314
4315	/**
4316	* Check that the 3D command has at least a_cbMin of payload bytes after the
4317	* header. Will break out of the switch if it doesn't.
4318	*/
4319	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4320	if (1) { \
4321	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4322	RT_UNTRUSTED_VALIDATED_FENCE(); \
4323	} else do {} while (0)
4324	switch ((int)enmCmdId)
4325	{
4326	case SVGA_3D_CMD_SURFACE_DEFINE:
4327	{
4328	uint32_t cMipLevels;
4329	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4330	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4331	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4332
4333	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4334	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4335	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4336	# ifdef DEBUG_GMR_ACCESS
4337	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4338	# endif
4339	break;
4340	}
4341
4342	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4343	{
4344	uint32_t cMipLevels;
4345	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4346	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4347	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4348
4349	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4350	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4351	pCmd->multisampleCount, pCmd->autogenFilter,
4352	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4353	break;
4354	}
4355
4356	case SVGA_3D_CMD_SURFACE_DESTROY:
4357	{
4358	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4359	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4360	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4361	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4362	break;
4363	}
4364
4365	case SVGA_3D_CMD_SURFACE_COPY:
4366	{
4367	uint32_t cCopyBoxes;
4368	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4369	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4370	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4371
4372	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4373	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4374	break;
4375	}
4376
4377	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4378	{
4379	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4380	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4381	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4382
4383	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4384	break;
4385	}
4386
4387	case SVGA_3D_CMD_SURFACE_DMA:
4388	{
4389	uint32_t cCopyBoxes;
4390	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4391	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4392	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4393
4394	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4395	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4396	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4397	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4398	break;
4399	}
4400
4401	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4402	{
4403	uint32_t cRects;
4404	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4405	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4406	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4407
4408	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4409	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4410	break;
4411	}
4412
4413	case SVGA_3D_CMD_CONTEXT_DEFINE:
4414	{
4415	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4416	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4417	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4418
4419	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4420	break;
4421	}
4422
4423	case SVGA_3D_CMD_CONTEXT_DESTROY:
4424	{
4425	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4426	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4427	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4428
4429	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4430	break;
4431	}
4432
4433	case SVGA_3D_CMD_SETTRANSFORM:
4434	{
4435	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4436	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4437	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4438
4439	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4440	break;
4441	}
4442
4443	case SVGA_3D_CMD_SETZRANGE:
4444	{
4445	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4446	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4448
4449	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4450	break;
4451	}
4452
4453	case SVGA_3D_CMD_SETRENDERSTATE:
4454	{
4455	uint32_t cRenderStates;
4456	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4457	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4458	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4459
4460	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4461	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4462	break;
4463	}
4464
4465	case SVGA_3D_CMD_SETRENDERTARGET:
4466	{
4467	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4468	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4469	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4470
4471	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4472	break;
4473	}
4474
4475	case SVGA_3D_CMD_SETTEXTURESTATE:
4476	{
4477	uint32_t cTextureStates;
4478	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4479	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4480	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4481
4482	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4483	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4484	break;
4485	}
4486
4487	case SVGA_3D_CMD_SETMATERIAL:
4488	{
4489	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4490	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4491	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4492
4493	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4494	break;
4495	}
4496
4497	case SVGA_3D_CMD_SETLIGHTDATA:
4498	{
4499	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4500	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4501	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4502
4503	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4504	break;
4505	}
4506
4507	case SVGA_3D_CMD_SETLIGHTENABLED:
4508	{
4509	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4510	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4511	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4512
4513	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4514	break;
4515	}
4516
4517	case SVGA_3D_CMD_SETVIEWPORT:
4518	{
4519	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4520	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4521	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4522
4523	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4524	break;
4525	}
4526
4527	case SVGA_3D_CMD_SETCLIPPLANE:
4528	{
4529	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4530	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4532
4533	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4534	break;
4535	}
4536
4537	case SVGA_3D_CMD_CLEAR:
4538	{
4539	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4540	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4541	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4542
4543	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4544	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4545	break;
4546	}
4547
4548	case SVGA_3D_CMD_PRESENT:
4549	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4550	{
4551	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4552	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4553	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4554	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4555	else
4556	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4557
4558	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4559
4560	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4561	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4562	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4563	break;
4564	}
4565
4566	case SVGA_3D_CMD_SHADER_DEFINE:
4567	{
4568	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4569	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4570	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4571
4572	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4573	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4574	break;
4575	}
4576
4577	case SVGA_3D_CMD_SHADER_DESTROY:
4578	{
4579	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4580	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4581	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4582
4583	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4584	break;
4585	}
4586
4587	case SVGA_3D_CMD_SET_SHADER:
4588	{
4589	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4590	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4591	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4592
4593	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4594	break;
4595	}
4596
4597	case SVGA_3D_CMD_SET_SHADER_CONST:
4598	{
4599	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4600	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4601	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4602
4603	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4604	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4605	break;
4606	}
4607
4608	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4609	{
4610	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4611	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4612	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4613
4614	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4615	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4616	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4617	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4618	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4619
4620	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4621	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4622
4623	RT_UNTRUSTED_VALIDATED_FENCE();
4624
4625	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4626	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4627	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4628
4629	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4630	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4631	pNumRange, cVertexDivisor, pVertexDivisor);
4632	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4633	break;
4634	}
4635
4636	case SVGA_3D_CMD_SETSCISSORRECT:
4637	{
4638	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4639	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4640	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4641
4642	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4643	break;
4644	}
4645
4646	case SVGA_3D_CMD_BEGIN_QUERY:
4647	{
4648	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4649	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4650	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4651
4652	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4653	break;
4654	}
4655
4656	case SVGA_3D_CMD_END_QUERY:
4657	{
4658	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4659	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4660	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4661
4662	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4663	break;
4664	}
4665
4666	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4667	{
4668	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4671
4672	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4673	break;
4674	}
4675
4676	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4677	{
4678	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4679	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4680	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4681
4682	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4683	break;
4684	}
4685
4686	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4687	/* context id + surface id? */
4688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4689	break;
4690	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4691	/* context id + surface id? */
4692	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4693	break;
4694
4695	default:
4696	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4697	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4698	break;
4699	}
4700	}
4701	else
4702	# endif // VBOX_WITH_VMSVGA3D
4703	{
4704	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4705	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4706	}
4707	}
4708
4709	/* Go to the next slot */
4710	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4711	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4712	if (offCurrentCmd >= offFifoMax)
4713	{
4714	offCurrentCmd -= offFifoMax - offFifoMin;
4715	Assert(offCurrentCmd >= offFifoMin);
4716	Assert(offCurrentCmd < offFifoMax);
4717	}
4718	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4719	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4720
4721	/*
4722	* Raise IRQ if required. Must enter the critical section here
4723	* before making final decisions here, otherwise cubebench and
4724	* others may end up waiting forever.
4725	*/
4726	if ( u32IrqStatus
4727	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4728	{
4729	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4730	AssertRC(rc2);
4731
4732	/* FIFO progress might trigger an interrupt. */
4733	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4734	{
4735	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4736	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4737	}
4738
4739	/* Unmasked IRQ pending? */
4740	if (pThis->svga.u32IrqMask & u32IrqStatus)
4741	{
4742	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4743	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4744	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4745	}
4746
4747	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4748	}
4749	}
4750
4751	/* If really done, clear the busy flag. */
4752	if (fDone)
4753	{
4754	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4755	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4756	}
4757	}
4758
4759	/*
4760	* Free the bounce buffer. (There are no returns above!)
4761	*/
4762	RTMemFree(pbBounceBuf);
4763
4764	return VINF_SUCCESS;
4765	}
4766
4767	/**
4768	* Free the specified GMR
4769	*
4770	* @param pThis VGA device instance data.
4771	* @param idGMR GMR id
4772	*/
4773	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4774	{
4775	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4776
4777	/* Free the old descriptor if present. */
4778	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4779	if ( pGMR->numDescriptors
4780	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4781	{
4782	# ifdef DEBUG_GMR_ACCESS
4783	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4784	# endif
4785
4786	Assert(pGMR->paDesc);
4787	RTMemFree(pGMR->paDesc);
4788	pGMR->paDesc = NULL;
4789	pGMR->numDescriptors = 0;
4790	pGMR->cbTotal = 0;
4791	pGMR->cMaxPages = 0;
4792	}
4793	Assert(!pGMR->cMaxPages);
4794	Assert(!pGMR->cbTotal);
4795	}
4796
4797	/**
4798	* Copy between a GMR and a host memory buffer.
4799	*
4800	* @returns VBox status code.
4801	* @param pThis VGA device instance data.
4802	* @param enmTransferType Transfer type (read/write)
4803	* @param pbHstBuf Host buffer pointer (valid)
4804	* @param cbHstBuf Size of host buffer (valid)
4805	* @param offHst Host buffer offset of the first scanline
4806	* @param cbHstPitch Destination buffer pitch
4807	* @param gstPtr GMR description
4808	* @param offGst Guest buffer offset of the first scanline
4809	* @param cbGstPitch Guest buffer pitch
4810	* @param cbWidth Width in bytes to copy
4811	* @param cHeight Number of scanllines to copy
4812	*/
4813	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4814	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4815	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4816	uint32_t cbWidth, uint32_t cHeight)
4817	{
4818	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4819	int rc;
4820
4821	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4822	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4823	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4824	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4825	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4826
4827	PGMR pGMR;
4828	uint32_t cbGmr; /* The GMR size in bytes. */
4829	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4830	{
4831	pGMR = NULL;
4832	cbGmr = pThis->vram_size;
4833	}
4834	else
4835	{
4836	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4837	RT_UNTRUSTED_VALIDATED_FENCE();
4838	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4839	cbGmr = pGMR->cbTotal;
4840	}
4841
4842	/*
4843	* GMR
4844	*/
4845	/* Calculate GMR offset of the data to be copied. */
4846	AssertMsgReturn(gstPtr.offset < cbGmr,
4847	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4848	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4849	VERR_INVALID_PARAMETER);
4850	RT_UNTRUSTED_VALIDATED_FENCE();
4851	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4852	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4853	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4854	VERR_INVALID_PARAMETER);
4855	RT_UNTRUSTED_VALIDATED_FENCE();
4856	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4857
4858	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4859	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4860	AssertMsgReturn(cbGmrScanline != 0,
4861	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4862	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4863	VERR_INVALID_PARAMETER);
4864	RT_UNTRUSTED_VALIDATED_FENCE();
4865	AssertMsgReturn(cbWidth <= cbGmrScanline,
4866	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4867	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4868	VERR_INVALID_PARAMETER);
4869	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4870	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4871	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4872	VERR_INVALID_PARAMETER);
4873	RT_UNTRUSTED_VALIDATED_FENCE();
4874
4875	/* How many bytes are available for the data in the GMR. */
4876	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4877
4878	/* How many scanlines would fit into the available data. */
4879	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4880	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4881	if (cbWidth <= cbGmrLastScanline)
4882	++cGmrScanlines;
4883
4884	if (cHeight > cGmrScanlines)
4885	cHeight = cGmrScanlines;
4886
4887	AssertMsgReturn(cHeight > 0,
4888	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4889	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4890	VERR_INVALID_PARAMETER);
4891	RT_UNTRUSTED_VALIDATED_FENCE();
4892
4893	/*
4894	* Host buffer.
4895	*/
4896	AssertMsgReturn(offHst < cbHstBuf,
4897	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4898	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4899	VERR_INVALID_PARAMETER);
4900
4901	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4902	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4903	AssertMsgReturn(cbHstScanline != 0,
4904	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4905	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4906	VERR_INVALID_PARAMETER);
4907	AssertMsgReturn(cbWidth <= cbHstScanline,
4908	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4909	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4910	VERR_INVALID_PARAMETER);
4911	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4912	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4913	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4914	VERR_INVALID_PARAMETER);
4915
4916	/* How many bytes are available for the data in the buffer. */
4917	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4918
4919	/* How many scanlines would fit into the available data. */
4920	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4921	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4922	if (cbWidth <= cbHstLastScanline)
4923	++cHstScanlines;
4924
4925	if (cHeight > cHstScanlines)
4926	cHeight = cHstScanlines;
4927
4928	AssertMsgReturn(cHeight > 0,
4929	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4930	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4931	VERR_INVALID_PARAMETER);
4932
4933	uint8_t *pbHst = pbHstBuf + offHst;
4934
4935	/* Shortcut for the framebuffer. */
4936	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4937	{
4938	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4939
4940	uint8_t const *pbSrc;
4941	int32_t cbSrcPitch;
4942	uint8_t *pbDst;
4943	int32_t cbDstPitch;
4944
4945	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4946	{
4947	pbSrc = pbHst;
4948	cbSrcPitch = cbHstPitch;
4949	pbDst = pbGst;
4950	cbDstPitch = cbGstPitch;
4951	}
4952	else
4953	{
4954	pbSrc = pbGst;
4955	cbSrcPitch = cbGstPitch;
4956	pbDst = pbHst;
4957	cbDstPitch = cbHstPitch;
4958	}
4959
4960	if ( cbWidth == (uint32_t)cbGstPitch
4961	&& cbGstPitch == cbHstPitch)
4962	{
4963	/* Entire scanlines, positive pitch. */
4964	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4965	}
4966	else
4967	{
4968	for (uint32_t i = 0; i < cHeight; ++i)
4969	{
4970	memcpy(pbDst, pbSrc, cbWidth);
4971
4972	pbDst += cbDstPitch;
4973	pbSrc += cbSrcPitch;
4974	}
4975	}
4976	return VINF_SUCCESS;
4977	}
4978
4979	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4980	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4981
4982	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4983	uint32_t iDesc = 0; /* Index in the descriptor array. */
4984	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4985	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4986	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4987	for (uint32_t i = 0; i < cHeight; ++i)
4988	{
4989	uint32_t cbCurrentWidth = cbWidth;
4990	uint32_t offGmrCurrent = offGmrScanline;
4991	uint8_t *pbCurrentHost = pbHstScanline;
4992
4993	/* Find the right descriptor */
4994	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4995	{
4996	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4997	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4998	++iDesc;
4999	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5000	}
5001
5002	while (cbCurrentWidth)
5003	{
5004	uint32_t cbToCopy;
5005
5006	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5007	{
5008	cbToCopy = cbCurrentWidth;
5009	}
5010	else
5011	{
5012	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5013	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5014	}
5015
5016	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5017
5018	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5019
5020	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5021	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5022	else
5023	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5024	AssertRCBreak(rc);
5025
5026	cbCurrentWidth -= cbToCopy;
5027	offGmrCurrent += cbToCopy;
5028	pbCurrentHost += cbToCopy;
5029
5030	/* Go to the next descriptor if there's anything left. */
5031	if (cbCurrentWidth)
5032	{
5033	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5034	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5035	++iDesc;
5036	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5037	}
5038	}
5039
5040	offGmrScanline += cbGstPitch;
5041	pbHstScanline += cbHstPitch;
5042	}
5043
5044	return VINF_SUCCESS;
5045	}
5046
5047
5048	/**
5049	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5050	*
5051	* @param pSizeSrc Source surface dimensions.
5052	* @param pSizeDest Destination surface dimensions.
5053	* @param pBox Coordinates to be clipped.
5054	*/
5055	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5056	const SVGA3dSize *pSizeDest,
5057	SVGA3dCopyBox *pBox)
5058	{
5059	/* Src x, w */
5060	if (pBox->srcx > pSizeSrc->width)
5061	pBox->srcx = pSizeSrc->width;
5062	if (pBox->w > pSizeSrc->width - pBox->srcx)
5063	pBox->w = pSizeSrc->width - pBox->srcx;
5064
5065	/* Src y, h */
5066	if (pBox->srcy > pSizeSrc->height)
5067	pBox->srcy = pSizeSrc->height;
5068	if (pBox->h > pSizeSrc->height - pBox->srcy)
5069	pBox->h = pSizeSrc->height - pBox->srcy;
5070
5071	/* Src z, d */
5072	if (pBox->srcz > pSizeSrc->depth)
5073	pBox->srcz = pSizeSrc->depth;
5074	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5075	pBox->d = pSizeSrc->depth - pBox->srcz;
5076
5077	/* Dest x, w */
5078	if (pBox->x > pSizeDest->width)
5079	pBox->x = pSizeDest->width;
5080	if (pBox->w > pSizeDest->width - pBox->x)
5081	pBox->w = pSizeDest->width - pBox->x;
5082
5083	/* Dest y, h */
5084	if (pBox->y > pSizeDest->height)
5085	pBox->y = pSizeDest->height;
5086	if (pBox->h > pSizeDest->height - pBox->y)
5087	pBox->h = pSizeDest->height - pBox->y;
5088
5089	/* Dest z, d */
5090	if (pBox->z > pSizeDest->depth)
5091	pBox->z = pSizeDest->depth;
5092	if (pBox->d > pSizeDest->depth - pBox->z)
5093	pBox->d = pSizeDest->depth - pBox->z;
5094	}
5095
5096	/**
5097	* Unsigned coordinates in pBox. Clip to [0; pSize).
5098	*
5099	* @param pSize Source surface dimensions.
5100	* @param pBox Coordinates to be clipped.
5101	*/
5102	void vmsvgaClipBox(const SVGA3dSize *pSize,
5103	SVGA3dBox *pBox)
5104	{
5105	/* x, w */
5106	if (pBox->x > pSize->width)
5107	pBox->x = pSize->width;
5108	if (pBox->w > pSize->width - pBox->x)
5109	pBox->w = pSize->width - pBox->x;
5110
5111	/* y, h */
5112	if (pBox->y > pSize->height)
5113	pBox->y = pSize->height;
5114	if (pBox->h > pSize->height - pBox->y)
5115	pBox->h = pSize->height - pBox->y;
5116
5117	/* z, d */
5118	if (pBox->z > pSize->depth)
5119	pBox->z = pSize->depth;
5120	if (pBox->d > pSize->depth - pBox->z)
5121	pBox->d = pSize->depth - pBox->z;
5122	}
5123
5124	/**
5125	* Clip.
5126	*
5127	* @param pBound Bounding rectangle.
5128	* @param pRect Rectangle to be clipped.
5129	*/
5130	void vmsvgaClipRect(SVGASignedRect const *pBound,
5131	SVGASignedRect *pRect)
5132	{
5133	int32_t left;
5134	int32_t top;
5135	int32_t right;
5136	int32_t bottom;
5137
5138	/* Right order. */
5139	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5140	if (pRect->left < pRect->right)
5141	{
5142	left = pRect->left;
5143	right = pRect->right;
5144	}
5145	else
5146	{
5147	left = pRect->right;
5148	right = pRect->left;
5149	}
5150	if (pRect->top < pRect->bottom)
5151	{
5152	top = pRect->top;
5153	bottom = pRect->bottom;
5154	}
5155	else
5156	{
5157	top = pRect->bottom;
5158	bottom = pRect->top;
5159	}
5160
5161	if (left < pBound->left)
5162	left = pBound->left;
5163	if (right < pBound->left)
5164	right = pBound->left;
5165
5166	if (left > pBound->right)
5167	left = pBound->right;
5168	if (right > pBound->right)
5169	right = pBound->right;
5170
5171	if (top < pBound->top)
5172	top = pBound->top;
5173	if (bottom < pBound->top)
5174	bottom = pBound->top;
5175
5176	if (top > pBound->bottom)
5177	top = pBound->bottom;
5178	if (bottom > pBound->bottom)
5179	bottom = pBound->bottom;
5180
5181	pRect->left = left;
5182	pRect->right = right;
5183	pRect->top = top;
5184	pRect->bottom = bottom;
5185	}
5186
5187	/**
5188	* Unblock the FIFO I/O thread so it can respond to a state change.
5189	*
5190	* @returns VBox status code.
5191	* @param pDevIns The VGA device instance.
5192	* @param pThread The send thread.
5193	*/
5194	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5195	{
5196	RT_NOREF(pDevIns);
5197	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5198	Log(("vmsvgaFIFOLoopWakeUp\n"));
5199	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5200	}
5201
5202	/**
5203	* Enables or disables dirty page tracking for the framebuffer
5204	*
5205	* @param pThis VGA device instance data.
5206	* @param fTraces Enable/disable traces
5207	*/
5208	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5209	{
5210	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5211	&& !fTraces)
5212	{
5213	//Assert(pThis->svga.fTraces);
5214	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5215	return;
5216	}
5217
5218	pThis->svga.fTraces = fTraces;
5219	if (pThis->svga.fTraces)
5220	{
5221	unsigned cbFrameBuffer = pThis->vram_size;
5222
5223	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5224	/** @todo How does this work with screens? */
5225	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5226	{
5227	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5228	Assert(pThis->svga.cbScanline);
5229	#endif
5230	/* Hardware enabled; return real framebuffer size .*/
5231	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5232	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5233	}
5234
5235	if (!pThis->svga.fVRAMTracking)
5236	{
5237	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5238	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5239	pThis->svga.fVRAMTracking = true;
5240	}
5241	}
5242	else
5243	{
5244	if (pThis->svga.fVRAMTracking)
5245	{
5246	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5247	vgaR3UnregisterVRAMHandler(pThis);
5248	pThis->svga.fVRAMTracking = false;
5249	}
5250	}
5251	}
5252
5253	/**
5254	* @callback_method_impl{FNPCIIOREGIONMAP}
5255	*/
5256	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5257	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5258	{
5259	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5260	int rc;
5261	RT_NOREF(pPciDev);
5262	Assert(pPciDev == pDevIns->apPciDevs[0]);
5263
5264	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5265	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5266	if (GCPhysAddress != NIL_RTGCPHYS)
5267	{
5268	/*
5269	* Mapping the FIFO RAM.
5270	*/
5271	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5272	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5273	AssertRC(rc);
5274
5275	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5276	if (RT_SUCCESS(rc))
5277	{
5278	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5279	# ifdef DEBUG_FIFO_ACCESS
5280	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5281	# else
5282	GCPhysAddress + PAGE_SIZE - 1,
5283	# endif
5284	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5285	"VMSVGA FIFO");
5286	AssertRC(rc);
5287	}
5288	# endif
5289	if (RT_SUCCESS(rc))
5290	{
5291	pThis->svga.GCPhysFIFO = GCPhysAddress;
5292	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5293	}
5294	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5295	}
5296	else
5297	{
5298	Assert(pThis->svga.GCPhysFIFO);
5299	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5300	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5301	AssertRC(rc);
5302	# else
5303	rc = VINF_SUCCESS;
5304	# endif
5305	pThis->svga.GCPhysFIFO = 0;
5306	}
5307	return rc;
5308	}
5309
5310	# ifdef VBOX_WITH_VMSVGA3D
5311
5312	/**
5313	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5314	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5315	*
5316	* @param pDevIns The device instance.
5317	* @param pThis The VGA device instance data.
5318	* @param sid Either UINT32_MAX or the ID of a specific
5319	* surface. If UINT32_MAX is used, all surfaces
5320	* are processed.
5321	*/
5322	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid)
5323	{
5324	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5325	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5326	}
5327
5328
5329	/**
5330	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5331	*/
5332	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5333	{
5334	/* There might be a specific surface ID at the start of the
5335	arguments, if not show all surfaces. */
5336	uint32_t sid = UINT32_MAX;
5337	if (pszArgs)
5338	pszArgs = RTStrStripL(pszArgs);
5339	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5340	sid = RTStrToUInt32(pszArgs);
5341
5342	/* Verbose or terse display, we default to verbose. */
5343	bool fVerbose = true;
5344	if (RTStrIStr(pszArgs, "terse"))
5345	fVerbose = false;
5346
5347	/* The size of the ascii art (x direction, y is 3/4 of x). */
5348	uint32_t cxAscii = 80;
5349	if (RTStrIStr(pszArgs, "gigantic"))
5350	cxAscii = 300;
5351	else if (RTStrIStr(pszArgs, "huge"))
5352	cxAscii = 180;
5353	else if (RTStrIStr(pszArgs, "big"))
5354	cxAscii = 132;
5355	else if (RTStrIStr(pszArgs, "normal"))
5356	cxAscii = 80;
5357	else if (RTStrIStr(pszArgs, "medium"))
5358	cxAscii = 64;
5359	else if (RTStrIStr(pszArgs, "small"))
5360	cxAscii = 48;
5361	else if (RTStrIStr(pszArgs, "tiny"))
5362	cxAscii = 24;
5363
5364	/* Y invert the image when producing the ASCII art. */
5365	bool fInvY = false;
5366	if (RTStrIStr(pszArgs, "invy"))
5367	fInvY = true;
5368
5369	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5370	}
5371
5372
5373	/**
5374	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5375	*/
5376	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5377	{
5378	/* pszArg = "sid[>dir]"
5379	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5380	*/
5381	char *pszBitmapPath = NULL;
5382	uint32_t sid = UINT32_MAX;
5383	if (pszArgs)
5384	pszArgs = RTStrStripL(pszArgs);
5385	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5386	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5387	if ( pszBitmapPath
5388	&& *pszBitmapPath == '>')
5389	++pszBitmapPath;
5390
5391	const bool fVerbose = true;
5392	const uint32_t cxAscii = 0; /* No ASCII */
5393	const bool fInvY = false; /* Do not invert. */
5394	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5395	}
5396
5397
5398	/**
5399	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5400	*/
5401	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5402	{
5403	/* There might be a specific surface ID at the start of the
5404	arguments, if not show all contexts. */
5405	uint32_t sid = UINT32_MAX;
5406	if (pszArgs)
5407	pszArgs = RTStrStripL(pszArgs);
5408	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5409	sid = RTStrToUInt32(pszArgs);
5410
5411	/* Verbose or terse display, we default to verbose. */
5412	bool fVerbose = true;
5413	if (RTStrIStr(pszArgs, "terse"))
5414	fVerbose = false;
5415
5416	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5417	}
5418
5419	# endif /* VBOX_WITH_VMSVGA3D */
5420
5421	/**
5422	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5423	*/
5424	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5425	{
5426	RT_NOREF(pszArgs);
5427	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5428	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5429	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5430
5431	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5432	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5433	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5434	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5435	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5436	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5437	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5438	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5439	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5440	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5441	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5442	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5443	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5444	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5445	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5446	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5447	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5448	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5449	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5450	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5451	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5452	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5453	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5454	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5455	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5456
5457	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5458	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5459	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5460	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5461
5462	# ifdef VBOX_WITH_VMSVGA3D
5463	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5464	# endif
5465	if (pThis->pDrv)
5466	{
5467	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5468	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5469	}
5470	}
5471
5472	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5473	*/
5474	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5475	{
5476	RT_NOREF(uPass);
5477
5478	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5479	int rc;
5480
5481	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5482	{
5483	uint32_t cScreens = 0;
5484	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5485	AssertRCReturn(rc, rc);
5486	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5487	("cScreens=%#x\n", cScreens),
5488	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5489
5490	for (uint32_t i = 0; i < cScreens; ++i)
5491	{
5492	VMSVGASCREENOBJECT screen;
5493	RT_ZERO(screen);
5494
5495	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5496	AssertLogRelRCReturn(rc, rc);
5497
5498	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5499	{
5500	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5501	*pScreen = screen;
5502	pScreen->fModified = true;
5503	}
5504	else
5505	{
5506	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5507	}
5508	}
5509	}
5510	else
5511	{
5512	/* Try to setup at least the first screen. */
5513	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5514	pScreen->fDefined = true;
5515	pScreen->fModified = true;
5516	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5517	pScreen->idScreen = 0;
5518	pScreen->xOrigin = 0;
5519	pScreen->yOrigin = 0;
5520	pScreen->offVRAM = pThis->svga.uScreenOffset;
5521	pScreen->cbPitch = pThis->svga.cbScanline;
5522	pScreen->cWidth = pThis->svga.uWidth;
5523	pScreen->cHeight = pThis->svga.uHeight;
5524	pScreen->cBpp = pThis->svga.uBpp;
5525	}
5526
5527	return VINF_SUCCESS;
5528	}
5529
5530	/**
5531	* @copydoc FNSSMDEVLOADEXEC
5532	*/
5533	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5534	{
5535	RT_NOREF(uPass);
5536	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5537	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5538	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5539	int rc;
5540
5541	/* Load our part of the VGAState */
5542	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5543	AssertRCReturn(rc, rc);
5544
5545	/* Load the VGA framebuffer. */
5546	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5547	uint32_t cbVgaFramebuffer = _32K;
5548	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5549	{
5550	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5551	AssertRCReturn(rc, rc);
5552	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5553	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5554	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5555	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5556	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5557	}
5558	rc = pHlp->pfnSSMGetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5559	AssertRCReturn(rc, rc);
5560	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5561	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5562	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5563	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5564
5565	/* Load the VMSVGA state. */
5566	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5567	AssertRCReturn(rc, rc);
5568
5569	/* Load the active cursor bitmaps. */
5570	if (pSVGAState->Cursor.fActive)
5571	{
5572	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5573	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5574
5575	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5576	AssertRCReturn(rc, rc);
5577	}
5578
5579	/* Load the GMR state. */
5580	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5581	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5582	{
5583	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5584	AssertRCReturn(rc, rc);
5585	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5586	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5587	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5588	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5589	}
5590
5591	if (pThis->svga.cGMR != cGMR)
5592	{
5593	/* Reallocate GMR array. */
5594	Assert(pSVGAState->paGMR != NULL);
5595	RTMemFree(pSVGAState->paGMR);
5596	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5597	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5598	pThis->svga.cGMR = cGMR;
5599	}
5600
5601	for (uint32_t i = 0; i < cGMR; ++i)
5602	{
5603	PGMR pGMR = &pSVGAState->paGMR[i];
5604
5605	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5606	AssertRCReturn(rc, rc);
5607
5608	if (pGMR->numDescriptors)
5609	{
5610	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5611	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5612	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5613
5614	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5615	{
5616	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5617	AssertRCReturn(rc, rc);
5618	}
5619	}
5620	}
5621
5622	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5623	vmsvga3dPowerOn(pThis);
5624	# endif
5625
5626	VMSVGA_STATE_LOAD LoadState;
5627	LoadState.pSSM = pSSM;
5628	LoadState.uVersion = uVersion;
5629	LoadState.uPass = uPass;
5630	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5631	AssertLogRelRCReturn(rc, rc);
5632
5633	return VINF_SUCCESS;
5634	}
5635
5636	/**
5637	* Reinit the video mode after the state has been loaded.
5638	*/
5639	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5640	{
5641	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5642	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5643
5644	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5645
5646	/* Set the active cursor. */
5647	if (pSVGAState->Cursor.fActive)
5648	{
5649	int rc;
5650
5651	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5652	true,
5653	true,
5654	pSVGAState->Cursor.xHotspot,
5655	pSVGAState->Cursor.yHotspot,
5656	pSVGAState->Cursor.width,
5657	pSVGAState->Cursor.height,
5658	pSVGAState->Cursor.pData);
5659	AssertRC(rc);
5660	}
5661	return VINF_SUCCESS;
5662	}
5663
5664	/**
5665	* Portion of SVGA state which must be saved in the FIFO thread.
5666	*/
5667	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5668	{
5669	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5670	int rc;
5671
5672	/* Save the screen objects. */
5673	/* Count defined screen object. */
5674	uint32_t cScreens = 0;
5675	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5676	{
5677	if (pSVGAState->aScreens[i].fDefined)
5678	++cScreens;
5679	}
5680
5681	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5682	AssertLogRelRCReturn(rc, rc);
5683
5684	for (uint32_t i = 0; i < cScreens; ++i)
5685	{
5686	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5687
5688	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5689	AssertLogRelRCReturn(rc, rc);
5690	}
5691	return VINF_SUCCESS;
5692	}
5693
5694	/**
5695	* @copydoc FNSSMDEVSAVEEXEC
5696	*/
5697	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5698	{
5699	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5700	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5701	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5702	int rc;
5703
5704	/* Save our part of the VGAState */
5705	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5706	AssertLogRelRCReturn(rc, rc);
5707
5708	/* Save the framebuffer backup. */
5709	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5710	rc = pHlp->pfnSSMPutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5711	AssertLogRelRCReturn(rc, rc);
5712
5713	/* Save the VMSVGA state. */
5714	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5715	AssertLogRelRCReturn(rc, rc);
5716
5717	/* Save the active cursor bitmaps. */
5718	if (pSVGAState->Cursor.fActive)
5719	{
5720	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5721	AssertLogRelRCReturn(rc, rc);
5722	}
5723
5724	/* Save the GMR state */
5725	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5726	AssertLogRelRCReturn(rc, rc);
5727	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5728	{
5729	PGMR pGMR = &pSVGAState->paGMR[i];
5730
5731	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5732	AssertLogRelRCReturn(rc, rc);
5733
5734	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5735	{
5736	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5737	AssertLogRelRCReturn(rc, rc);
5738	}
5739	}
5740
5741	/*
5742	* Must save some state (3D in particular) in the FIFO thread.
5743	*/
5744	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5745	AssertLogRelRCReturn(rc, rc);
5746
5747	return VINF_SUCCESS;
5748	}
5749
5750	/**
5751	* Destructor for PVMSVGAR3STATE structure.
5752	*
5753	* @param pThis The VGA instance.
5754	* @param pSVGAState Pointer to the structure. It is not deallocated.
5755	*/
5756	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5757	{
5758	#ifndef VMSVGA_USE_EMT_HALT_CODE
5759	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5760	{
5761	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5762	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5763	}
5764	#endif
5765
5766	if (pSVGAState->Cursor.fActive)
5767	{
5768	RTMemFree(pSVGAState->Cursor.pData);
5769	pSVGAState->Cursor.pData = NULL;
5770	pSVGAState->Cursor.fActive = false;
5771	}
5772
5773	if (pSVGAState->paGMR)
5774	{
5775	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5776	if (pSVGAState->paGMR[i].paDesc)
5777	RTMemFree(pSVGAState->paGMR[i].paDesc);
5778
5779	RTMemFree(pSVGAState->paGMR);
5780	pSVGAState->paGMR = NULL;
5781	}
5782	}
5783
5784	/**
5785	* Constructor for PVMSVGAR3STATE structure.
5786	*
5787	* @returns VBox status code.
5788	* @param pThis The VGA instance.
5789	* @param pSVGAState Pointer to the structure. It is already allocated.
5790	*/
5791	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5792	{
5793	int rc = VINF_SUCCESS;
5794	RT_ZERO(*pSVGAState);
5795
5796	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5797	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5798
5799	#ifndef VMSVGA_USE_EMT_HALT_CODE
5800	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5801	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5802	AssertRCReturn(rc, rc);
5803	#endif
5804
5805	return rc;
5806	}
5807
5808	/**
5809	* Initializes the host capabilities: registers and FIFO.
5810	*
5811	* @returns VBox status code.
5812	* @param pThis The VGA instance.
5813	*/
5814	static void vmsvgaInitCaps(PVGASTATE pThis)
5815	{
5816	/* Register caps. */
5817	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5818	\| SVGA_CAP_GMR2
5819	\| SVGA_CAP_CURSOR
5820	\| SVGA_CAP_CURSOR_BYPASS_2
5821	\| SVGA_CAP_EXTENDED_FIFO
5822	\| SVGA_CAP_IRQMASK
5823	\| SVGA_CAP_PITCHLOCK
5824	\| SVGA_CAP_TRACES
5825	\| SVGA_CAP_SCREEN_OBJECT_2
5826	\| SVGA_CAP_ALPHA_CURSOR;
5827	# ifdef VBOX_WITH_VMSVGA3D
5828	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5829	# endif
5830
5831	/* Clear the FIFO. */
5832	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5833
5834	/* Setup FIFO capabilities. */
5835	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5836	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5837	\| SVGA_FIFO_CAP_GMR2
5838	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5839	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5840	\| SVGA_FIFO_CAP_RESERVE
5841	\| SVGA_FIFO_CAP_PITCHLOCK;
5842
5843	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5844	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5845	}
5846
5847	# ifdef VBOX_WITH_VMSVGA3D
5848	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5849	static const char * const g_apszVmSvgaDevCapNames[] =
5850	{
5851	"x3D", /* = 0 */
5852	"xMAX_LIGHTS",
5853	"xMAX_TEXTURES",
5854	"xMAX_CLIP_PLANES",
5855	"xVERTEX_SHADER_VERSION",
5856	"xVERTEX_SHADER",
5857	"xFRAGMENT_SHADER_VERSION",
5858	"xFRAGMENT_SHADER",
5859	"xMAX_RENDER_TARGETS",
5860	"xS23E8_TEXTURES",
5861	"xS10E5_TEXTURES",
5862	"xMAX_FIXED_VERTEXBLEND",
5863	"xD16_BUFFER_FORMAT",
5864	"xD24S8_BUFFER_FORMAT",
5865	"xD24X8_BUFFER_FORMAT",
5866	"xQUERY_TYPES",
5867	"xTEXTURE_GRADIENT_SAMPLING",
5868	"rMAX_POINT_SIZE",
5869	"xMAX_SHADER_TEXTURES",
5870	"xMAX_TEXTURE_WIDTH",
5871	"xMAX_TEXTURE_HEIGHT",
5872	"xMAX_VOLUME_EXTENT",
5873	"xMAX_TEXTURE_REPEAT",
5874	"xMAX_TEXTURE_ASPECT_RATIO",
5875	"xMAX_TEXTURE_ANISOTROPY",
5876	"xMAX_PRIMITIVE_COUNT",
5877	"xMAX_VERTEX_INDEX",
5878	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5879	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5880	"xMAX_VERTEX_SHADER_TEMPS",
5881	"xMAX_FRAGMENT_SHADER_TEMPS",
5882	"xTEXTURE_OPS",
5883	"xSURFACEFMT_X8R8G8B8",
5884	"xSURFACEFMT_A8R8G8B8",
5885	"xSURFACEFMT_A2R10G10B10",
5886	"xSURFACEFMT_X1R5G5B5",
5887	"xSURFACEFMT_A1R5G5B5",
5888	"xSURFACEFMT_A4R4G4B4",
5889	"xSURFACEFMT_R5G6B5",
5890	"xSURFACEFMT_LUMINANCE16",
5891	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5892	"xSURFACEFMT_ALPHA8",
5893	"xSURFACEFMT_LUMINANCE8",
5894	"xSURFACEFMT_Z_D16",
5895	"xSURFACEFMT_Z_D24S8",
5896	"xSURFACEFMT_Z_D24X8",
5897	"xSURFACEFMT_DXT1",
5898	"xSURFACEFMT_DXT2",
5899	"xSURFACEFMT_DXT3",
5900	"xSURFACEFMT_DXT4",
5901	"xSURFACEFMT_DXT5",
5902	"xSURFACEFMT_BUMPX8L8V8U8",
5903	"xSURFACEFMT_A2W10V10U10",
5904	"xSURFACEFMT_BUMPU8V8",
5905	"xSURFACEFMT_Q8W8V8U8",
5906	"xSURFACEFMT_CxV8U8",
5907	"xSURFACEFMT_R_S10E5",
5908	"xSURFACEFMT_R_S23E8",
5909	"xSURFACEFMT_RG_S10E5",
5910	"xSURFACEFMT_RG_S23E8",
5911	"xSURFACEFMT_ARGB_S10E5",
5912	"xSURFACEFMT_ARGB_S23E8",
5913	"xMISSING62",
5914	"xMAX_VERTEX_SHADER_TEXTURES",
5915	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5916	"xSURFACEFMT_V16U16",
5917	"xSURFACEFMT_G16R16",
5918	"xSURFACEFMT_A16B16G16R16",
5919	"xSURFACEFMT_UYVY",
5920	"xSURFACEFMT_YUY2",
5921	"xMULTISAMPLE_NONMASKABLESAMPLES",
5922	"xMULTISAMPLE_MASKABLESAMPLES",
5923	"xALPHATOCOVERAGE",
5924	"xSUPERSAMPLE",
5925	"xAUTOGENMIPMAPS",
5926	"xSURFACEFMT_NV12",
5927	"xSURFACEFMT_AYUV",
5928	"xMAX_CONTEXT_IDS",
5929	"xMAX_SURFACE_IDS",
5930	"xSURFACEFMT_Z_DF16",
5931	"xSURFACEFMT_Z_DF24",
5932	"xSURFACEFMT_Z_D24S8_INT",
5933	"xSURFACEFMT_BC4_UNORM",
5934	"xSURFACEFMT_BC5_UNORM", /* 83 */
5935	};
5936
5937	/**
5938	* Initializes the host 3D capabilities in FIFO.
5939	*
5940	* @returns VBox status code.
5941	* @param pThis The VGA instance.
5942	*/
5943	static void vmsvgaInitFifo3DCaps(PVGASTATE pThis)
5944	{
5945	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5946	bool fSavedBuffering = RTLogRelSetBuffering(true);
5947	SVGA3dCapsRecord *pCaps;
5948	SVGA3dCapPair *pData;
5949	uint32_t idxCap = 0;
5950
5951	/* 3d hardware version; latest and greatest */
5952	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5953	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5954
5955	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5956	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5957	pData = (SVGA3dCapPair *)&pCaps->data;
5958
5959	/* Fill out all 3d capabilities. */
5960	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5961	{
5962	uint32_t val = 0;
5963
5964	int rc = vmsvga3dQueryCaps(pThis, i, &val);
5965	if (RT_SUCCESS(rc))
5966	{
5967	pData[idxCap][0] = i;
5968	pData[idxCap][1] = val;
5969	idxCap++;
5970	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5971	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5972	else
5973	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5974	&g_apszVmSvgaDevCapNames[i][1]));
5975	}
5976	else
5977	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5978	}
5979	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5980	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5981
5982	/* Mark end of record array. */
5983	pCaps->header.length = 0;
5984
5985	RTLogRelSetBuffering(fSavedBuffering);
5986	}
5987
5988	# endif
5989
5990	/**
5991	* Resets the SVGA hardware state
5992	*
5993	* @returns VBox status code.
5994	* @param pDevIns The device instance.
5995	*/
5996	int vmsvgaReset(PPDMDEVINS pDevIns)
5997	{
5998	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5999	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
6000
6001	/* Reset before init? */
6002	if (!pSVGAState)
6003	return VINF_SUCCESS;
6004
6005	Log(("vmsvgaReset\n"));
6006
6007	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6008	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6009	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6010
6011	/* Reset other stuff. */
6012	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6013	RT_ZERO(pThis->svga.au32ScratchRegion);
6014
6015	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6016	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6017
6018	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6019
6020	/* Initialize FIFO and register capabilities. */
6021	vmsvgaInitCaps(pThis);
6022
6023	# ifdef VBOX_WITH_VMSVGA3D
6024	if (pThis->svga.f3DEnabled)
6025	vmsvgaInitFifo3DCaps(pThis);
6026	# endif
6027
6028	/* VRAM tracking is enabled by default during bootup. */
6029	pThis->svga.fVRAMTracking = true;
6030	pThis->svga.fEnabled = false;
6031
6032	/* Invalidate current settings. */
6033	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6034	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6035	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6036	pThis->svga.cbScanline = 0;
6037	pThis->svga.u32PitchLock = 0;
6038
6039	return rc;
6040	}
6041
6042	/**
6043	* Cleans up the SVGA hardware state
6044	*
6045	* @returns VBox status code.
6046	* @param pDevIns The device instance.
6047	*/
6048	int vmsvgaDestruct(PPDMDEVINS pDevIns)
6049	{
6050	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6051
6052	/*
6053	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6054	*/
6055	if (pThis->svga.pFIFOIOThread)
6056	{
6057	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6058	AssertLogRelRC(rc);
6059
6060	rc = PDMDevHlpThreadDestroy(pDevIns, pThis->svga.pFIFOIOThread, NULL);
6061	AssertLogRelRC(rc);
6062	pThis->svga.pFIFOIOThread = NULL;
6063	}
6064
6065	/*
6066	* Destroy the special SVGA state.
6067	*/
6068	if (pThis->svga.pSvgaR3State)
6069	{
6070	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6071
6072	RTMemFree(pThis->svga.pSvgaR3State);
6073	pThis->svga.pSvgaR3State = NULL;
6074	}
6075
6076	/*
6077	* Free our resources residing in the VGA state.
6078	*/
6079	if (pThis->svga.pbVgaFrameBufferR3)
6080	{
6081	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6082	pThis->svga.pbVgaFrameBufferR3 = NULL;
6083	}
6084	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
6085	{
6086	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
6087	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
6088	}
6089	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
6090	{
6091	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
6092	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
6093	}
6094
6095	return VINF_SUCCESS;
6096	}
6097
6098	/**
6099	* Initialize the SVGA hardware state
6100	*
6101	* @returns VBox status code.
6102	* @param pDevIns The device instance.
6103	*/
6104	int vmsvgaInit(PPDMDEVINS pDevIns)
6105	{
6106	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6107	PVMSVGAR3STATE pSVGAState;
6108	int rc;
6109
6110	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6111	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6112
6113	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6114
6115	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6116	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6117	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6118
6119	/* Create event semaphore. */
6120	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
6121
6122	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
6123	if (RT_FAILURE(rc))
6124	{
6125	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
6126	return rc;
6127	}
6128
6129	/* Create event semaphore. */
6130	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
6131	if (RT_FAILURE(rc))
6132	{
6133	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
6134	return rc;
6135	}
6136
6137	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6138	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6139
6140	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6141	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6142
6143	pSVGAState = pThis->svga.pSvgaR3State;
6144
6145	/* Initialize FIFO and register capabilities. */
6146	vmsvgaInitCaps(pThis);
6147
6148	# ifdef VBOX_WITH_VMSVGA3D
6149	if (pThis->svga.f3DEnabled)
6150	{
6151	rc = vmsvga3dInit(pThis);
6152	if (RT_FAILURE(rc))
6153	{
6154	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6155	pThis->svga.f3DEnabled = false;
6156	}
6157	}
6158	# endif
6159	/* VRAM tracking is enabled by default during bootup. */
6160	pThis->svga.fVRAMTracking = true;
6161
6162	/* Invalidate current settings. */
6163	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6164	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6165	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6166	pThis->svga.cbScanline = 0;
6167
6168	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6169	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6170	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6171	{
6172	pThis->svga.u32MaxWidth -= 256;
6173	pThis->svga.u32MaxHeight -= 256;
6174	}
6175	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6176
6177	# ifdef DEBUG_GMR_ACCESS
6178	/* Register the GMR access handler type. */
6179	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6180	vmsvgaR3GMRAccessHandler,
6181	NULL, NULL, NULL,
6182	NULL, NULL, NULL,
6183	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6184	AssertRCReturn(rc, rc);
6185	# endif
6186
6187	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6188	/* Register the FIFO access handler type. In addition to
6189	debugging FIFO access, this is also used to facilitate
6190	extended fifo thread sleeps. */
6191	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6192	# ifdef DEBUG_FIFO_ACCESS
6193	PGMPHYSHANDLERKIND_ALL,
6194	# else
6195	PGMPHYSHANDLERKIND_WRITE,
6196	# endif
6197	vmsvgaR3FIFOAccessHandler,
6198	NULL, NULL, NULL,
6199	NULL, NULL, NULL,
6200	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6201	AssertRCReturn(rc, rc);
6202	# endif
6203
6204	/* Create the async IO thread. */
6205	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6206	RTTHREADTYPE_IO, "VMSVGA FIFO");
6207	if (RT_FAILURE(rc))
6208	{
6209	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6210	return rc;
6211	}
6212
6213	/*
6214	* Statistics.
6215	*/
6216	#define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6217	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6218	#define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6219	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6220	#ifdef VBOX_WITH_STATISTICS
6221	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6222	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6223	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6224	#endif
6225	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6226	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6227	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6228	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6229	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6230	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6231	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6232	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6233	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6234	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6235	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6236	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6237	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6238	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6239	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6240	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6241	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6242	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6243	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6244	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6245	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6246	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6247	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6248	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6249	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6250	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6251	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6252	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6253	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6254	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6255	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6256	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6257	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6258	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6259	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6260	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6261	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6262	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6263	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6264	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6265	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6266	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6267	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6268	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6269	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6270	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6271	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6272	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6273	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6274	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6275	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6276	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6277	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6278
6279	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6280	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6281	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6282	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6283	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6284	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6285	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6286	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6287	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6288	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6289	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6290	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6291	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6292	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6293	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6294	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6295	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6296	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6297	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6298	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6299	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6300	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6301	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6302	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6303	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6304	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6305	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6306	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6307	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6308	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6309	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6310	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6311
6312	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6313	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6314	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6315	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6316	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6317	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6318	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6319	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6320	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6321	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6322	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6323	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6324	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6325	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6326	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6327	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6328	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6329	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6330	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6331	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6332	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6333	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6334	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6335	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6336	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6337	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6338	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6339	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6340	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6341	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6342	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6343	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6344	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6345	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6346	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6347	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6348	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6349	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6350	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6351	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6352	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6353	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6354	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6355	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6356	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6357	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6358	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6359	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6360	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6361
6362	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6363	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6364	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6365	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6366	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6367	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6368	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6369	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6370	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6371	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6372	# endif
6373	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6374	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6375	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6376	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6377	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6378
6379	#undef REG_CNT
6380	#undef REG_PRF
6381
6382	/*
6383	* Info handlers.
6384	*/
6385	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6386	# ifdef VBOX_WITH_VMSVGA3D
6387	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6388	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6389	"VMSVGA 3d surface details. "
6390	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6391	vmsvgaR3Info3dSurface);
6392	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6393	"VMSVGA 3d surface details and bitmap: "
6394	"sid[>dir]",
6395	vmsvgaR3Info3dSurfaceBmp);
6396	# endif
6397
6398	return VINF_SUCCESS;
6399	}
6400
6401	/**
6402	* Power On notification.
6403	*
6404	* @returns VBox status code.
6405	* @param pDevIns The device instance data.
6406	*
6407	* @remarks Caller enters the device critical section.
6408	*/
6409	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6410	{
6411	# ifdef VBOX_WITH_VMSVGA3D
6412	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6413	if (pThis->svga.f3DEnabled)
6414	{
6415	int rc = vmsvga3dPowerOn(pThis);
6416
6417	if (RT_SUCCESS(rc))
6418	{
6419	/* Initialize FIFO 3D capabilities. */
6420	vmsvgaInitFifo3DCaps(pThis);
6421	}
6422	}
6423	# else /* !VBOX_WITH_VMSVGA3D */
6424	RT_NOREF(pDevIns);
6425	# endif /* !VBOX_WITH_VMSVGA3D */
6426	}
6427
6428	#endif /* IN_RING3 */
6429

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82081

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