DevVGA-SVGA.cpp@ 77237

最後變更在這個檔案從77237是 77226,由 vboxsync 提交於 6 年前
Devices/DevVGA-SVGA: move an assertion out of the FIFO access handler. bugref:9376: Complete hardware cursor implementation in VMSVGA. I put an assertion into the FIFO access handler that it would not trigger more than once every 500ms. However, disabling it is not reliable, so that can still happen. Instead, I moved the assertion to the code re-enabling the handler. That should really not happen more frequently.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
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1	/* $Id: DevVGA-SVGA.cpp 77226 2019-02-08 17:13:26Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.alldomusa.eu.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	#include "DevVGA-SVGA.h"
159	#include "vmsvga/svga_escape.h"
160	#include "vmsvga/svga_overlay.h"
161	#include "vmsvga/svga3d_caps.h"
162	#ifdef VBOX_WITH_VMSVGA3D
163	# include "DevVGA-SVGA3d.h"
164	# ifdef RT_OS_DARWIN
165	# include "DevVGA-SVGA3d-cocoa.h"
166	# endif
167	#endif
168
169
170	/*********************************************************************************************************************************
171	* Defined Constants And Macros *
172	*********************************************************************************************************************************/
173	/**
174	* Macro for checking if a fixed FIFO register is valid according to the
175	* current FIFO configuration.
176	*
177	* @returns true / false.
178	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
179	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
180	*/
181	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
182
183
184	/*********************************************************************************************************************************
185	* Structures and Typedefs *
186	*********************************************************************************************************************************/
187	/**
188	* 64-bit GMR descriptor.
189	*/
190	typedef struct
191	{
192	RTGCPHYS GCPhys;
193	uint64_t numPages;
194	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
195
196	/**
197	* GMR slot
198	*/
199	typedef struct
200	{
201	uint32_t cMaxPages;
202	uint32_t cbTotal;
203	uint32_t numDescriptors;
204	PVMSVGAGMRDESCRIPTOR paDesc;
205	} GMR, *PGMR;
206
207	#ifdef IN_RING3
208	/**
209	* Internal SVGA ring-3 only state.
210	*/
211	typedef struct VMSVGAR3STATE
212	{
213	GMR *paGMR; // [VMSVGAState::cGMR]
214	struct
215	{
216	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
217	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
218	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
219	} GMRFB;
220	struct
221	{
222	bool fActive;
223	uint32_t xHotspot;
224	uint32_t yHotspot;
225	uint32_t width;
226	uint32_t height;
227	uint32_t cbData;
228	void *pData;
229	} Cursor;
230	SVGAColorBGRX colorAnnotation;
231
232	# ifdef VMSVGA_USE_EMT_HALT_CODE
233	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
234	uint32_t volatile cBusyDelayedEmts;
235	/** Set of EMTs that are */
236	VMCPUSET BusyDelayedEmts;
237	# else
238	/** Number of EMTs waiting on hBusyDelayedEmts. */
239	uint32_t volatile cBusyDelayedEmts;
240	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
241	* busy (ugly). */
242	RTSEMEVENTMULTI hBusyDelayedEmts;
243	# endif
244
245	/** Information obout screens. */
246	VMSVGASCREENOBJECT aScreens[64];
247
248	# ifdef VBOX_STRICT
249	/** The time the access handler for the FIFO last triggered. This should
250	* never happen less than a certain interval from the last access, and we
251	* assert this. */
252	uint64_t TimeLastFIFOIntercept;
253	# endif
254
255	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
256	STAMPROFILE StatBusyDelayEmts;
257
258	STAMPROFILE StatR3Cmd3dPresentProf;
259	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
260	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
261	STAMCOUNTER StatR3CmdDefineGmr2;
262	STAMCOUNTER StatR3CmdDefineGmr2Free;
263	STAMCOUNTER StatR3CmdDefineGmr2Modify;
264	STAMCOUNTER StatR3CmdRemapGmr2;
265	STAMCOUNTER StatR3CmdRemapGmr2Modify;
266	STAMCOUNTER StatR3CmdInvalidCmd;
267	STAMCOUNTER StatR3CmdFence;
268	STAMCOUNTER StatR3CmdUpdate;
269	STAMCOUNTER StatR3CmdUpdateVerbose;
270	STAMCOUNTER StatR3CmdDefineCursor;
271	STAMCOUNTER StatR3CmdDefineAlphaCursor;
272	STAMCOUNTER StatR3CmdEscape;
273	STAMCOUNTER StatR3CmdDefineScreen;
274	STAMCOUNTER StatR3CmdDestroyScreen;
275	STAMCOUNTER StatR3CmdDefineGmrFb;
276	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
277	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
278	STAMCOUNTER StatR3CmdAnnotationFill;
279	STAMCOUNTER StatR3CmdAnnotationCopy;
280	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
281	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
282	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
283	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
284	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
285	STAMCOUNTER StatR3Cmd3dSurfaceDma;
286	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
287	STAMCOUNTER StatR3Cmd3dContextDefine;
288	STAMCOUNTER StatR3Cmd3dContextDestroy;
289	STAMCOUNTER StatR3Cmd3dSetTransform;
290	STAMCOUNTER StatR3Cmd3dSetZRange;
291	STAMCOUNTER StatR3Cmd3dSetRenderState;
292	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
293	STAMCOUNTER StatR3Cmd3dSetTextureState;
294	STAMCOUNTER StatR3Cmd3dSetMaterial;
295	STAMCOUNTER StatR3Cmd3dSetLightData;
296	STAMCOUNTER StatR3Cmd3dSetLightEnable;
297	STAMCOUNTER StatR3Cmd3dSetViewPort;
298	STAMCOUNTER StatR3Cmd3dSetClipPlane;
299	STAMCOUNTER StatR3Cmd3dClear;
300	STAMCOUNTER StatR3Cmd3dPresent;
301	STAMCOUNTER StatR3Cmd3dPresentReadBack;
302	STAMCOUNTER StatR3Cmd3dShaderDefine;
303	STAMCOUNTER StatR3Cmd3dShaderDestroy;
304	STAMCOUNTER StatR3Cmd3dSetShader;
305	STAMCOUNTER StatR3Cmd3dSetShaderConst;
306	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
307	STAMCOUNTER StatR3Cmd3dSetScissorRect;
308	STAMCOUNTER StatR3Cmd3dBeginQuery;
309	STAMCOUNTER StatR3Cmd3dEndQuery;
310	STAMCOUNTER StatR3Cmd3dWaitForQuery;
311	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
312	STAMCOUNTER StatR3Cmd3dActivateSurface;
313	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
314
315	STAMCOUNTER StatR3RegConfigDoneWr;
316	STAMCOUNTER StatR3RegGmrDescriptorWr;
317	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
318	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
319
320	STAMCOUNTER StatFifoCommands;
321	STAMCOUNTER StatFifoErrors;
322	STAMCOUNTER StatFifoUnkCmds;
323	STAMCOUNTER StatFifoTodoTimeout;
324	STAMCOUNTER StatFifoTodoWoken;
325	STAMPROFILE StatFifoStalls;
326	STAMPROFILE StatFifoSleepOnHandler;
327	STAMCOUNTER StatFifoAccessHandler;
328	STAMCOUNTER StatFifoCursorFetchAgain;
329	STAMCOUNTER StatFifoCursorNoChange;
330	STAMCOUNTER StatFifoCursorPosition;
331	STAMCOUNTER StatFifoCursorVisiblity;
332
333	} VMSVGAR3STATE, *PVMSVGAR3STATE;
334	#endif /* IN_RING3 */
335
336
337	/*********************************************************************************************************************************
338	* Internal Functions *
339	*********************************************************************************************************************************/
340	#ifdef IN_RING3
341	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
342	# ifdef DEBUG_GMR_ACCESS
343	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
344	# endif
345	#endif
346
347
348	/*********************************************************************************************************************************
349	* Global Variables *
350	*********************************************************************************************************************************/
351	#ifdef IN_RING3
352
353	/**
354	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
355	*/
356	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
357	{
358	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
359	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
360	SSMFIELD_ENTRY_TERM()
361	};
362
363	/**
364	* SSM descriptor table for the GMR structure.
365	*/
366	static SSMFIELD const g_aGMRFields[] =
367	{
368	SSMFIELD_ENTRY( GMR, cMaxPages),
369	SSMFIELD_ENTRY( GMR, cbTotal),
370	SSMFIELD_ENTRY( GMR, numDescriptors),
371	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
372	SSMFIELD_ENTRY_TERM()
373	};
374
375	/**
376	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
377	*/
378	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
379	{
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
391	SSMFIELD_ENTRY_TERM()
392	};
393
394	/**
395	* SSM descriptor table for the VMSVGAR3STATE structure.
396	*/
397	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
398	{
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
407	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
410	#ifdef VMSVGA_USE_EMT_HALT_CODE
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
412	#else
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
414	#endif
415	#ifdef VBOX_STRICT
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, TimeLastFIFOIntercept),
417	#endif
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
480
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoSleepOnHandler),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
493
494	SSMFIELD_ENTRY_TERM()
495	};
496
497	/**
498	* SSM descriptor table for the VGAState.svga structure.
499	*/
500	static SSMFIELD const g_aVGAStateSVGAFields[] =
501	{
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
505	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
506	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
507	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
508	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
509	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
510	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
511	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
512	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
513	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
514	SSMFIELD_ENTRY( VMSVGAState, fBusy),
515	SSMFIELD_ENTRY( VMSVGAState, fTraces),
516	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
517	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
518	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
519	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
520	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
521	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
522	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
523	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
525	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
528	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
529	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
530	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
531	SSMFIELD_ENTRY( VMSVGAState, uWidth),
532	SSMFIELD_ENTRY( VMSVGAState, uHeight),
533	SSMFIELD_ENTRY( VMSVGAState, uBpp),
534	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
535	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
536	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
537	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
538	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
539	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
540	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
542	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
543	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
544	SSMFIELD_ENTRY_TERM()
545	};
546
547	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
548	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
549	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
550
551	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
552	{
553	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
554	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
555	&& pSVGAState
556	&& pSVGAState->aScreens[idScreen].fDefined)
557	{
558	return &pSVGAState->aScreens[idScreen];
559	}
560	return NULL;
561	}
562
563	#endif /* IN_RING3 */
564
565	#ifdef LOG_ENABLED
566
567	/**
568	* Index register string name lookup
569	*
570	* @returns Index register string or "UNKNOWN"
571	* @param pThis VMSVGA State
572	* @param idxReg The index register.
573	*/
574	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
575	{
576	switch (idxReg)
577	{
578	case SVGA_REG_ID: return "SVGA_REG_ID";
579	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
580	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
581	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
582	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
583	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
584	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
585	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
586	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
587	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
588	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
589	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
590	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
591	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
592	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
593	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
594	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
595	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
596	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
597	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
598	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
599	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
600	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
601	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
602	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
603	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
604	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
605	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
606	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
607	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
608	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
609	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
610	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
611	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
612	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
613	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
614	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
615	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
616	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
617	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
618	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
619	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
620	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
621	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
622	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
623	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
624	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
625	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
626	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
627	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
628
629	default:
630	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
631	return "SVGA_SCRATCH_BASE reg";
632	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
633	return "SVGA_PALETTE_BASE reg";
634	return "UNKNOWN";
635	}
636	}
637
638	#ifdef IN_RING3
639	/**
640	* FIFO command name lookup
641	*
642	* @returns FIFO command string or "UNKNOWN"
643	* @param u32Cmd FIFO command
644	*/
645	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
646	{
647	switch (u32Cmd)
648	{
649	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
650	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
651	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
652	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
653	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
654	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
655	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
656	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
657	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
658	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
659	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
660	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
661	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
662	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
663	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
664	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
665	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
666	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
667	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
668	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
669	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
670	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
671	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
672	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
673	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
674	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
675	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
676	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
677	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
678	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
679	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
680	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
681	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
682	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
683	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
684	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
685	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
686	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
687	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
688	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
689	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
690	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
691	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
692	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
693	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
694	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
695	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
696	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
697	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
698	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
699	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
700	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
701	default: return "UNKNOWN";
702	}
703	}
704	# endif /* IN_RING3 */
705
706	#endif /* LOG_ENABLED */
707
708	#ifdef IN_RING3
709	/**
710	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
711	*/
712	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
713	{
714	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
715
716	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
717	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
718
719	/** @todo Test how it interacts with multiple screen objects. */
720	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
721	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
722	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
723
724	if (x < uWidth)
725	{
726	pThis->svga.viewport.x = x;
727	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
728	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
729	}
730	else
731	{
732	pThis->svga.viewport.x = uWidth;
733	pThis->svga.viewport.cx = 0;
734	pThis->svga.viewport.xRight = uWidth;
735	}
736	if (y < uHeight)
737	{
738	pThis->svga.viewport.y = y;
739	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
740	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
741	pThis->svga.viewport.yHighWC = uHeight - y;
742	}
743	else
744	{
745	pThis->svga.viewport.y = uHeight;
746	pThis->svga.viewport.cy = 0;
747	pThis->svga.viewport.yLowWC = 0;
748	pThis->svga.viewport.yHighWC = 0;
749	}
750
751	# ifdef VBOX_WITH_VMSVGA3D
752	/*
753	* Now inform the 3D backend.
754	*/
755	if (pThis->svga.f3DEnabled)
756	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
757	# else
758	RT_NOREF(OldViewport);
759	# endif
760	}
761	#endif /* IN_RING3 */
762
763	/**
764	* Read port register
765	*
766	* @returns VBox status code.
767	* @param pThis VMSVGA State
768	* @param pu32 Where to store the read value
769	*/
770	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
771	{
772	int rc = VINF_SUCCESS;
773	*pu32 = 0;
774
775	/* Rough index register validation. */
776	uint32_t idxReg = pThis->svga.u32IndexReg;
777	#if !defined(IN_RING3) && defined(VBOX_STRICT)
778	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
779	VINF_IOM_R3_IOPORT_READ);
780	#else
781	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
782	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
783	VINF_SUCCESS);
784	#endif
785	RT_UNTRUSTED_VALIDATED_FENCE();
786
787	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
788	if ( idxReg >= SVGA_REG_CAPABILITIES
789	&& pThis->svga.u32SVGAId == SVGA_ID_0)
790	{
791	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
792	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
793	}
794
795	switch (idxReg)
796	{
797	case SVGA_REG_ID:
798	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
799	*pu32 = pThis->svga.u32SVGAId;
800	break;
801
802	case SVGA_REG_ENABLE:
803	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
804	*pu32 = pThis->svga.fEnabled;
805	break;
806
807	case SVGA_REG_WIDTH:
808	{
809	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
810	if ( pThis->svga.fEnabled
811	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
812	{
813	*pu32 = pThis->svga.uWidth;
814	}
815	else
816	{
817	#ifndef IN_RING3
818	rc = VINF_IOM_R3_IOPORT_READ;
819	#else
820	*pu32 = pThis->pDrv->cx;
821	#endif
822	}
823	break;
824	}
825
826	case SVGA_REG_HEIGHT:
827	{
828	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
829	if ( pThis->svga.fEnabled
830	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
831	{
832	*pu32 = pThis->svga.uHeight;
833	}
834	else
835	{
836	#ifndef IN_RING3
837	rc = VINF_IOM_R3_IOPORT_READ;
838	#else
839	*pu32 = pThis->pDrv->cy;
840	#endif
841	}
842	break;
843	}
844
845	case SVGA_REG_MAX_WIDTH:
846	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
847	*pu32 = pThis->svga.u32MaxWidth;
848	break;
849
850	case SVGA_REG_MAX_HEIGHT:
851	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
852	*pu32 = pThis->svga.u32MaxHeight;
853	break;
854
855	case SVGA_REG_DEPTH:
856	/* This returns the color depth of the current mode. */
857	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
858	switch (pThis->svga.uBpp)
859	{
860	case 15:
861	case 16:
862	case 24:
863	*pu32 = pThis->svga.uBpp;
864	break;
865
866	default:
867	case 32:
868	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
869	break;
870	}
871	break;
872
873	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
874	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
875	if ( pThis->svga.fEnabled
876	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
877	{
878	*pu32 = pThis->svga.uBpp;
879	}
880	else
881	{
882	#ifndef IN_RING3
883	rc = VINF_IOM_R3_IOPORT_READ;
884	#else
885	*pu32 = pThis->pDrv->cBits;
886	#endif
887	}
888	break;
889
890	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
891	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
892	if ( pThis->svga.fEnabled
893	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
894	{
895	*pu32 = (pThis->svga.uBpp + 7) & ~7;
896	}
897	else
898	{
899	#ifndef IN_RING3
900	rc = VINF_IOM_R3_IOPORT_READ;
901	#else
902	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
903	#endif
904	}
905	break;
906
907	case SVGA_REG_PSEUDOCOLOR:
908	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
909	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
910	break;
911
912	case SVGA_REG_RED_MASK:
913	case SVGA_REG_GREEN_MASK:
914	case SVGA_REG_BLUE_MASK:
915	{
916	uint32_t uBpp;
917
918	if ( pThis->svga.fEnabled
919	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
920	{
921	uBpp = pThis->svga.uBpp;
922	}
923	else
924	{
925	#ifndef IN_RING3
926	rc = VINF_IOM_R3_IOPORT_READ;
927	break;
928	#else
929	uBpp = pThis->pDrv->cBits;
930	#endif
931	}
932	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
933	switch (uBpp)
934	{
935	case 8:
936	u32RedMask = 0x07;
937	u32GreenMask = 0x38;
938	u32BlueMask = 0xc0;
939	break;
940
941	case 15:
942	u32RedMask = 0x0000001f;
943	u32GreenMask = 0x000003e0;
944	u32BlueMask = 0x00007c00;
945	break;
946
947	case 16:
948	u32RedMask = 0x0000001f;
949	u32GreenMask = 0x000007e0;
950	u32BlueMask = 0x0000f800;
951	break;
952
953	case 24:
954	case 32:
955	default:
956	u32RedMask = 0x00ff0000;
957	u32GreenMask = 0x0000ff00;
958	u32BlueMask = 0x000000ff;
959	break;
960	}
961	switch (idxReg)
962	{
963	case SVGA_REG_RED_MASK:
964	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
965	*pu32 = u32RedMask;
966	break;
967
968	case SVGA_REG_GREEN_MASK:
969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
970	*pu32 = u32GreenMask;
971	break;
972
973	case SVGA_REG_BLUE_MASK:
974	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
975	*pu32 = u32BlueMask;
976	break;
977	}
978	break;
979	}
980
981	case SVGA_REG_BYTES_PER_LINE:
982	{
983	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
984	if ( pThis->svga.fEnabled
985	&& pThis->svga.cbScanline)
986	{
987	*pu32 = pThis->svga.cbScanline;
988	}
989	else
990	{
991	#ifndef IN_RING3
992	rc = VINF_IOM_R3_IOPORT_READ;
993	#else
994	*pu32 = pThis->pDrv->cbScanline;
995	#endif
996	}
997	break;
998	}
999
1000	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1002	*pu32 = pThis->vram_size;
1003	break;
1004
1005	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1006	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1007	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1008	*pu32 = pThis->GCPhysVRAM;
1009	break;
1010
1011	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1012	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1013	/* Always zero in our case. */
1014	*pu32 = 0;
1015	break;
1016
1017	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1018	{
1019	#ifndef IN_RING3
1020	rc = VINF_IOM_R3_IOPORT_READ;
1021	#else
1022	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1023
1024	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1025	if ( pThis->svga.fEnabled
1026	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1027	{
1028	/* Hardware enabled; return real framebuffer size .*/
1029	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1030	}
1031	else
1032	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1033
1034	pu32 = RT_MIN(pThis->vram_size, pu32);
1035	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1036	#endif
1037	break;
1038	}
1039
1040	case SVGA_REG_CAPABILITIES:
1041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1042	*pu32 = pThis->svga.u32RegCaps;
1043	break;
1044
1045	case SVGA_REG_MEM_START: /* FIFO start */
1046	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1047	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1048	*pu32 = pThis->svga.GCPhysFIFO;
1049	break;
1050
1051	case SVGA_REG_MEM_SIZE: /* FIFO size */
1052	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1053	*pu32 = pThis->svga.cbFIFO;
1054	break;
1055
1056	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1057	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1058	*pu32 = pThis->svga.fConfigured;
1059	break;
1060
1061	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1063	*pu32 = 0;
1064	break;
1065
1066	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1067	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1068	if (pThis->svga.fBusy)
1069	{
1070	#ifndef IN_RING3
1071	/* Go to ring-3 and halt the CPU. */
1072	rc = VINF_IOM_R3_IOPORT_READ;
1073	break;
1074	#else
1075	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1076	/* The guest is basically doing a HLT via the device here, but with
1077	a special wake up condition on FIFO completion. */
1078	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1079	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1080	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1081	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1082	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1083	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1084	if (pThis->svga.fBusy)
1085	{
1086	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1087	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1088	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1089	}
1090	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1091	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1092	# else
1093
1094	/* Delay the EMT a bit so the FIFO and others can get some work done.
1095	This used to be a crude 50 ms sleep. The current code tries to be
1096	more efficient, but the consept is still very crude. */
1097	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1098	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1099	RTThreadYield();
1100	if (pThis->svga.fBusy)
1101	{
1102	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1103
1104	if (pThis->svga.fBusy && cRefs == 1)
1105	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1106	if (pThis->svga.fBusy)
1107	{
1108	/** @todo If this code is going to stay, we need to call into the halt/wait
1109	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1110	* suffer when the guest is polling on a busy FIFO. */
1111	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1112	if (cNsMaxWait >= RT_NS_100US)
1113	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1114	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1115	RT_MIN(cNsMaxWait, RT_NS_10MS));
1116	}
1117
1118	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1119	}
1120	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1121	# endif
1122	*pu32 = pThis->svga.fBusy != 0;
1123	#endif
1124	}
1125	else
1126	*pu32 = false;
1127	break;
1128
1129	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1130	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1131	*pu32 = pThis->svga.u32GuestId;
1132	break;
1133
1134	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1135	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1136	*pu32 = pThis->svga.cScratchRegion;
1137	break;
1138
1139	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1140	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1141	*pu32 = SVGA_FIFO_NUM_REGS;
1142	break;
1143
1144	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1145	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1146	*pu32 = pThis->svga.u32PitchLock;
1147	break;
1148
1149	case SVGA_REG_IRQMASK: /* Interrupt mask */
1150	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1151	*pu32 = pThis->svga.u32IrqMask;
1152	break;
1153
1154	/* See "Guest memory regions" below. */
1155	case SVGA_REG_GMR_ID:
1156	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1157	*pu32 = pThis->svga.u32CurrentGMRId;
1158	break;
1159
1160	case SVGA_REG_GMR_DESCRIPTOR:
1161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1162	/* Write only */
1163	*pu32 = 0;
1164	break;
1165
1166	case SVGA_REG_GMR_MAX_IDS:
1167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1168	*pu32 = pThis->svga.cGMR;
1169	break;
1170
1171	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1172	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1173	*pu32 = VMSVGA_MAX_GMR_PAGES;
1174	break;
1175
1176	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1178	*pu32 = pThis->svga.fTraces;
1179	break;
1180
1181	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1183	*pu32 = VMSVGA_MAX_GMR_PAGES;
1184	break;
1185
1186	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1188	*pu32 = VMSVGA_SURFACE_SIZE;
1189	break;
1190
1191	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1192	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1193	break;
1194
1195	/* Mouse cursor support. */
1196	case SVGA_REG_CURSOR_ID:
1197	case SVGA_REG_CURSOR_X:
1198	case SVGA_REG_CURSOR_Y:
1199	case SVGA_REG_CURSOR_ON:
1200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1201	break;
1202
1203	/* Legacy multi-monitor support */
1204	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1206	*pu32 = 1;
1207	break;
1208
1209	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1210	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1211	*pu32 = 0;
1212	break;
1213
1214	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1215	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1216	*pu32 = 0;
1217	break;
1218
1219	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1220	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1221	*pu32 = 0;
1222	break;
1223
1224	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1225	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1226	*pu32 = 0;
1227	break;
1228
1229	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1231	*pu32 = pThis->svga.uWidth;
1232	break;
1233
1234	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1236	*pu32 = pThis->svga.uHeight;
1237	break;
1238
1239	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1241	/* We must return something sensible here otherwise the Linux driver
1242	will take a legacy code path without 3d support. This number also
1243	limits how many screens Linux guests will allow. */
1244	*pu32 = pThis->cMonitors;
1245	break;
1246
1247	default:
1248	{
1249	uint32_t offReg;
1250	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1251	{
1252	RT_UNTRUSTED_VALIDATED_FENCE();
1253	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1254	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1255	}
1256	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1257	{
1258	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1260	RT_UNTRUSTED_VALIDATED_FENCE();
1261	uint32_t u32 = pThis->last_palette[offReg / 3];
1262	switch (offReg % 3)
1263	{
1264	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1265	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1266	case 2: pu32 = u32 & 0xff; break; / blue */
1267	}
1268	}
1269	else
1270	{
1271	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1272	rc = VINF_IOM_R3_IOPORT_READ;
1273	#else
1274	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1275
1276	/* Do not assert. The guest might be reading all registers. */
1277	LogFunc(("Unknown reg=%#x\n", idxReg));
1278	#endif
1279	}
1280	break;
1281	}
1282	}
1283	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1284	return rc;
1285	}
1286
1287	#ifdef IN_RING3
1288	/**
1289	* Apply the current resolution settings to change the video mode.
1290	*
1291	* @returns VBox status code.
1292	* @param pThis VMSVGA State
1293	*/
1294	static int vmsvgaChangeMode(PVGASTATE pThis)
1295	{
1296	int rc;
1297
1298	/* Always do changemode on FIFO thread. */
1299	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1300
1301	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1302
1303	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1304
1305	if (pThis->svga.fGFBRegisters)
1306	{
1307	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1308	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1309	* deletes all screens other than screen #0, and redefines screen
1310	* #0 according to the specified mode. Drivers that use
1311	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1312	*/
1313
1314	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1315	pScreen->fDefined = true;
1316	pScreen->fModified = true;
1317	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1318	pScreen->idScreen = 0;
1319	pScreen->xOrigin = 0;
1320	pScreen->yOrigin = 0;
1321	pScreen->offVRAM = 0;
1322	pScreen->cbPitch = pThis->svga.cbScanline;
1323	pScreen->cWidth = pThis->svga.uWidth;
1324	pScreen->cHeight = pThis->svga.uHeight;
1325	pScreen->cBpp = pThis->svga.uBpp;
1326
1327	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1328	{
1329	/* Delete screen. */
1330	pScreen = &pSVGAState->aScreens[iScreen];
1331	if (pScreen->fDefined)
1332	{
1333	pScreen->fModified = true;
1334	pScreen->fDefined = false;
1335	}
1336	}
1337	}
1338	else
1339	{
1340	/* "If Screen Objects are supported, they can be used to fully
1341	* replace the functionality provided by the framebuffer registers
1342	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1343	*/
1344	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1345	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1346	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1347	}
1348
1349	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1350	{
1351	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1352	if (!pScreen->fModified)
1353	continue;
1354
1355	pScreen->fModified = false;
1356
1357	VBVAINFOVIEW view;
1358	RT_ZERO(view);
1359	view.u32ViewIndex = pScreen->idScreen;
1360	// view.u32ViewOffset = 0;
1361	view.u32ViewSize = pThis->vram_size;
1362	view.u32MaxScreenSize = pThis->vram_size;
1363
1364	VBVAINFOSCREEN screen;
1365	RT_ZERO(screen);
1366	screen.u32ViewIndex = pScreen->idScreen;
1367
1368	if (pScreen->fDefined)
1369	{
1370	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1371	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1372	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1373	{
1374	Assert(pThis->svga.fGFBRegisters);
1375	continue;
1376	}
1377
1378	screen.i32OriginX = pScreen->xOrigin;
1379	screen.i32OriginY = pScreen->yOrigin;
1380	screen.u32StartOffset = pScreen->offVRAM;
1381	screen.u32LineSize = pScreen->cbPitch;
1382	screen.u32Width = pScreen->cWidth;
1383	screen.u32Height = pScreen->cHeight;
1384	screen.u16BitsPerPixel = pScreen->cBpp;
1385	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1386	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1387	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1388	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1389	}
1390	else
1391	{
1392	/* Screen is destroyed. */
1393	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1394	}
1395
1396	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1397	AssertRC(rc);
1398	}
1399
1400	/* Last stuff. For the VGA device screenshot. */
1401	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1402	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1404	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1405	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1406
1407	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1408	if ( pThis->svga.viewport.cx == 0
1409	&& pThis->svga.viewport.cy == 0)
1410	{
1411	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1412	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1413	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1414	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1415	pThis->svga.viewport.yLowWC = 0;
1416	}
1417
1418	return VINF_SUCCESS;
1419	}
1420
1421	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1422	{
1423	if (pThis->svga.fGFBRegisters)
1424	{
1425	vgaR3UpdateDisplay(pThis, x, y, w, h);
1426	}
1427	else
1428	{
1429	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1430	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1431	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1432	}
1433
1434	return VINF_SUCCESS;
1435	}
1436
1437	#endif /* IN_RING3 */
1438
1439	#if defined(IN_RING0) \|\| defined(IN_RING3)
1440	/**
1441	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1442	*
1443	* @param pThis The VMSVGA state.
1444	* @param fState The busy state.
1445	*/
1446	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1447	{
1448	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1449
1450	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1451	{
1452	/* Race / unfortunately scheduling. Highly unlikly. */
1453	uint32_t cLoops = 64;
1454	do
1455	{
1456	ASMNopPause();
1457	fState = (pThis->svga.fBusy != 0);
1458	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1459	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1460	}
1461	}
1462	#endif
1463
1464	/**
1465	* Write port register
1466	*
1467	* @returns VBox status code.
1468	* @param pThis VMSVGA State
1469	* @param u32 Value to write
1470	*/
1471	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1472	{
1473	#ifdef IN_RING3
1474	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1475	#endif
1476	int rc = VINF_SUCCESS;
1477
1478	/* Rough index register validation. */
1479	uint32_t idxReg = pThis->svga.u32IndexReg;
1480	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1481	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1482	VINF_IOM_R3_IOPORT_WRITE);
1483	#else
1484	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1485	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1486	VINF_SUCCESS);
1487	#endif
1488	RT_UNTRUSTED_VALIDATED_FENCE();
1489
1490	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1491	if ( idxReg >= SVGA_REG_CAPABILITIES
1492	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1493	{
1494	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1495	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1496	}
1497	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1498	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1499	switch (idxReg)
1500	{
1501	case SVGA_REG_WIDTH:
1502	case SVGA_REG_HEIGHT:
1503	case SVGA_REG_PITCHLOCK:
1504	case SVGA_REG_BITS_PER_PIXEL:
1505	pThis->svga.fGFBRegisters = true;
1506	break;
1507	default:
1508	break;
1509	}
1510
1511	switch (idxReg)
1512	{
1513	case SVGA_REG_ID:
1514	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1515	if ( u32 == SVGA_ID_0
1516	\|\| u32 == SVGA_ID_1
1517	\|\| u32 == SVGA_ID_2)
1518	pThis->svga.u32SVGAId = u32;
1519	else
1520	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1521	break;
1522
1523	case SVGA_REG_ENABLE:
1524	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1525	#ifdef IN_RING3
1526	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1527	&& pThis->svga.fEnabled == false)
1528	{
1529	/* Make a backup copy of the first 512kb in order to save font data etc. */
1530	/** @todo should probably swap here, rather than copy + zero */
1531	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1532	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1533	}
1534
1535	pThis->svga.fEnabled = u32;
1536	if (pThis->svga.fEnabled)
1537	{
1538	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1539	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1540	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1541	{
1542	/* Keep the current mode. */
1543	pThis->svga.uWidth = pThis->pDrv->cx;
1544	pThis->svga.uHeight = pThis->pDrv->cy;
1545	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1546	}
1547
1548	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1549	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1550	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1551	{
1552	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1553	}
1554	# ifdef LOG_ENABLED
1555	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1556	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1557	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1558	# endif
1559
1560	/* Disable or enable dirty page tracking according to the current fTraces value. */
1561	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1562
1563	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1564	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1565	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/, false /fRenderThreadMode/);
1566	}
1567	else
1568	{
1569	/* Restore the text mode backup. */
1570	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1571
1572	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1573
1574	/* Enable dirty page tracking again when going into legacy mode. */
1575	vmsvgaSetTraces(pThis, true);
1576
1577	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1578	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1579	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1580	}
1581	#else /* !IN_RING3 */
1582	rc = VINF_IOM_R3_IOPORT_WRITE;
1583	#endif /* !IN_RING3 */
1584	break;
1585
1586	case SVGA_REG_WIDTH:
1587	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1588	if (pThis->svga.uWidth != u32)
1589	{
1590	pThis->svga.uWidth = u32;
1591	if (pThis->svga.fEnabled)
1592	{
1593	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1594	}
1595	}
1596	/* else: nop */
1597	break;
1598
1599	case SVGA_REG_HEIGHT:
1600	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1601	if (pThis->svga.uHeight != u32)
1602	{
1603	pThis->svga.uHeight = u32;
1604	if (pThis->svga.fEnabled)
1605	{
1606	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1607	}
1608	}
1609	/* else: nop */
1610	break;
1611
1612	case SVGA_REG_DEPTH:
1613	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1614	/** @todo read-only?? */
1615	break;
1616
1617	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1618	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1619	if (pThis->svga.uBpp != u32)
1620	{
1621	pThis->svga.uBpp = u32;
1622	if (pThis->svga.fEnabled)
1623	{
1624	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1625	}
1626	}
1627	/* else: nop */
1628	break;
1629
1630	case SVGA_REG_PSEUDOCOLOR:
1631	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1632	break;
1633
1634	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1635	#ifdef IN_RING3
1636	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1637	pThis->svga.fConfigured = u32;
1638	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1639	if (!pThis->svga.fConfigured)
1640	{
1641	pThis->svga.fTraces = true;
1642	}
1643	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1644	#else
1645	rc = VINF_IOM_R3_IOPORT_WRITE;
1646	#endif
1647	break;
1648
1649	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1650	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1651	if ( pThis->svga.fEnabled
1652	&& pThis->svga.fConfigured)
1653	{
1654	#if defined(IN_RING3) \|\| defined(IN_RING0)
1655	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1656	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1657	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1658	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1659
1660	/* Kick the FIFO thread to start processing commands again. */
1661	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1662	#else
1663	rc = VINF_IOM_R3_IOPORT_WRITE;
1664	#endif
1665	}
1666	/* else nothing to do. */
1667	else
1668	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1669
1670	break;
1671
1672	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1673	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1674	break;
1675
1676	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1677	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1678	pThis->svga.u32GuestId = u32;
1679	break;
1680
1681	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1682	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1683	pThis->svga.u32PitchLock = u32;
1684	break;
1685
1686	case SVGA_REG_IRQMASK: /* Interrupt mask */
1687	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1688	pThis->svga.u32IrqMask = u32;
1689
1690	/* Irq pending after the above change? */
1691	if (pThis->svga.u32IrqStatus & u32)
1692	{
1693	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1694	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1695	}
1696	else
1697	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1698	break;
1699
1700	/* Mouse cursor support */
1701	case SVGA_REG_CURSOR_ID:
1702	case SVGA_REG_CURSOR_X:
1703	case SVGA_REG_CURSOR_Y:
1704	case SVGA_REG_CURSOR_ON:
1705	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1706	break;
1707
1708	/* Legacy multi-monitor support */
1709	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1710	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1711	break;
1712	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1713	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1714	break;
1715	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1716	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1717	break;
1718	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1719	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1720	break;
1721	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1722	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1723	break;
1724	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1725	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1726	break;
1727	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1728	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1729	break;
1730	#ifdef VBOX_WITH_VMSVGA3D
1731	/* See "Guest memory regions" below. */
1732	case SVGA_REG_GMR_ID:
1733	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1734	pThis->svga.u32CurrentGMRId = u32;
1735	break;
1736
1737	case SVGA_REG_GMR_DESCRIPTOR:
1738	# ifndef IN_RING3
1739	rc = VINF_IOM_R3_IOPORT_WRITE;
1740	break;
1741	# else /* IN_RING3 */
1742	{
1743	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1744
1745	/* Validate current GMR id. */
1746	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1747	AssertBreak(idGMR < pThis->svga.cGMR);
1748	RT_UNTRUSTED_VALIDATED_FENCE();
1749
1750	/* Free the old GMR if present. */
1751	vmsvgaGMRFree(pThis, idGMR);
1752
1753	/* Just undefine the GMR? */
1754	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1755	if (GCPhys == 0)
1756	{
1757	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1758	break;
1759	}
1760
1761
1762	/* Never cross a page boundary automatically. */
1763	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1764	uint32_t cPagesTotal = 0;
1765	uint32_t iDesc = 0;
1766	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1767	uint32_t cLoops = 0;
1768	RTGCPHYS GCPhysBase = GCPhys;
1769	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1770	{
1771	/* Read descriptor. */
1772	SVGAGuestMemDescriptor desc;
1773	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1774	AssertRCBreak(rc);
1775
1776	if (desc.numPages != 0)
1777	{
1778	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1779	cPagesTotal += desc.numPages;
1780	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1781
1782	if ((iDesc & 15) == 0)
1783	{
1784	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1785	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1786	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1787	}
1788
1789	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1790	paDescs[iDesc++].numPages = desc.numPages;
1791
1792	/* Continue with the next descriptor. */
1793	GCPhys += sizeof(desc);
1794	}
1795	else if (desc.ppn == 0)
1796	break; /* terminator */
1797	else /* Pointer to the next physical page of descriptors. */
1798	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1799
1800	cLoops++;
1801	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1802	}
1803
1804	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1805	if (RT_SUCCESS(rc))
1806	{
1807	/* Commit the GMR. */
1808	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1809	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1810	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1811	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1812	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1813	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1814	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1815	}
1816	else
1817	{
1818	RTMemFree(paDescs);
1819	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1820	}
1821	break;
1822	}
1823	# endif /* IN_RING3 */
1824	#endif // VBOX_WITH_VMSVGA3D
1825
1826	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1827	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1828	if (pThis->svga.fTraces == u32)
1829	break; /* nothing to do */
1830
1831	#ifdef IN_RING3
1832	vmsvgaSetTraces(pThis, !!u32);
1833	#else
1834	rc = VINF_IOM_R3_IOPORT_WRITE;
1835	#endif
1836	break;
1837
1838	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1839	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1840	break;
1841
1842	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1843	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1844	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1845	break;
1846
1847	case SVGA_REG_FB_START:
1848	case SVGA_REG_MEM_START:
1849	case SVGA_REG_HOST_BITS_PER_PIXEL:
1850	case SVGA_REG_MAX_WIDTH:
1851	case SVGA_REG_MAX_HEIGHT:
1852	case SVGA_REG_VRAM_SIZE:
1853	case SVGA_REG_FB_SIZE:
1854	case SVGA_REG_CAPABILITIES:
1855	case SVGA_REG_MEM_SIZE:
1856	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1857	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1858	case SVGA_REG_BYTES_PER_LINE:
1859	case SVGA_REG_FB_OFFSET:
1860	case SVGA_REG_RED_MASK:
1861	case SVGA_REG_GREEN_MASK:
1862	case SVGA_REG_BLUE_MASK:
1863	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1864	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1865	case SVGA_REG_GMR_MAX_IDS:
1866	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1867	/* Read only - ignore. */
1868	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1869	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1870	break;
1871
1872	default:
1873	{
1874	uint32_t offReg;
1875	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1876	{
1877	RT_UNTRUSTED_VALIDATED_FENCE();
1878	pThis->svga.au32ScratchRegion[offReg] = u32;
1879	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1880	}
1881	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1882	{
1883	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1884	Btw, see rgb_to_pixel32. */
1885	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1886	u32 &= 0xff;
1887	RT_UNTRUSTED_VALIDATED_FENCE();
1888	uint32_t uRgb = pThis->last_palette[offReg / 3];
1889	switch (offReg % 3)
1890	{
1891	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1892	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1893	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1894	}
1895	pThis->last_palette[offReg / 3] = uRgb;
1896	}
1897	else
1898	{
1899	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1900	rc = VINF_IOM_R3_IOPORT_WRITE;
1901	#else
1902	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1903	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1904	#endif
1905	}
1906	break;
1907	}
1908	}
1909	return rc;
1910	}
1911
1912	/**
1913	* Port I/O Handler for IN operations.
1914	*
1915	* @returns VINF_SUCCESS or VINF_EM_*.
1916	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1917	*
1918	* @param pDevIns The device instance.
1919	* @param pvUser User argument.
1920	* @param uPort Port number used for the IN operation.
1921	* @param pu32 Where to store the result. This is always a 32-bit
1922	* variable regardless of what @a cb might say.
1923	* @param cb Number of bytes read.
1924	*/
1925	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1926	{
1927	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1928	RT_NOREF_PV(pvUser);
1929
1930	/* Ignore non-dword accesses. */
1931	if (cb != 4)
1932	{
1933	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1934	*pu32 = UINT32_MAX;
1935	return VINF_SUCCESS;
1936	}
1937
1938	switch (uPort - pThis->svga.BasePort)
1939	{
1940	case SVGA_INDEX_PORT:
1941	*pu32 = pThis->svga.u32IndexReg;
1942	break;
1943
1944	case SVGA_VALUE_PORT:
1945	return vmsvgaReadPort(pThis, pu32);
1946
1947	case SVGA_BIOS_PORT:
1948	Log(("Ignoring BIOS port read\n"));
1949	*pu32 = 0;
1950	break;
1951
1952	case SVGA_IRQSTATUS_PORT:
1953	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1954	*pu32 = pThis->svga.u32IrqStatus;
1955	break;
1956
1957	default:
1958	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
1959	*pu32 = UINT32_MAX;
1960	break;
1961	}
1962
1963	return VINF_SUCCESS;
1964	}
1965
1966	/**
1967	* Port I/O Handler for OUT operations.
1968	*
1969	* @returns VINF_SUCCESS or VINF_EM_*.
1970	*
1971	* @param pDevIns The device instance.
1972	* @param pvUser User argument.
1973	* @param uPort Port number used for the OUT operation.
1974	* @param u32 The value to output.
1975	* @param cb The value size in bytes.
1976	*/
1977	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1978	{
1979	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1980	RT_NOREF_PV(pvUser);
1981
1982	/* Ignore non-dword accesses. */
1983	if (cb != 4)
1984	{
1985	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1986	return VINF_SUCCESS;
1987	}
1988
1989	switch (uPort - pThis->svga.BasePort)
1990	{
1991	case SVGA_INDEX_PORT:
1992	pThis->svga.u32IndexReg = u32;
1993	break;
1994
1995	case SVGA_VALUE_PORT:
1996	return vmsvgaWritePort(pThis, u32);
1997
1998	case SVGA_BIOS_PORT:
1999	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2000	break;
2001
2002	case SVGA_IRQSTATUS_PORT:
2003	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2004	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2005	/* Clear the irq in case all events have been cleared. */
2006	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2007	{
2008	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2009	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2010	}
2011	break;
2012
2013	default:
2014	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2015	uPort - pThis->svga.BasePort, uPort, u32, cb));
2016	break;
2017	}
2018	return VINF_SUCCESS;
2019	}
2020
2021	#ifdef IN_RING3
2022
2023	# ifdef DEBUG_FIFO_ACCESS
2024	/**
2025	* Handle FIFO memory access.
2026	* @returns VBox status code.
2027	* @param pVM VM handle.
2028	* @param pThis VGA device instance data.
2029	* @param GCPhys The access physical address.
2030	* @param fWriteAccess Read or write access
2031	*/
2032	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2033	{
2034	RT_NOREF(pVM);
2035	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2036	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2037
2038	switch (GCPhysOffset >> 2)
2039	{
2040	case SVGA_FIFO_MIN:
2041	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2042	break;
2043	case SVGA_FIFO_MAX:
2044	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2045	break;
2046	case SVGA_FIFO_NEXT_CMD:
2047	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2048	break;
2049	case SVGA_FIFO_STOP:
2050	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2051	break;
2052	case SVGA_FIFO_CAPABILITIES:
2053	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2054	break;
2055	case SVGA_FIFO_FLAGS:
2056	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2057	break;
2058	case SVGA_FIFO_FENCE:
2059	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2060	break;
2061	case SVGA_FIFO_3D_HWVERSION:
2062	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2063	break;
2064	case SVGA_FIFO_PITCHLOCK:
2065	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2066	break;
2067	case SVGA_FIFO_CURSOR_ON:
2068	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2069	break;
2070	case SVGA_FIFO_CURSOR_X:
2071	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2072	break;
2073	case SVGA_FIFO_CURSOR_Y:
2074	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2075	break;
2076	case SVGA_FIFO_CURSOR_COUNT:
2077	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2078	break;
2079	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2080	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2081	break;
2082	case SVGA_FIFO_RESERVED:
2083	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2084	break;
2085	case SVGA_FIFO_CURSOR_SCREEN_ID:
2086	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2087	break;
2088	case SVGA_FIFO_DEAD:
2089	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2090	break;
2091	case SVGA_FIFO_3D_HWVERSION_REVISED:
2092	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2093	break;
2094	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2095	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2096	break;
2097	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2098	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2099	break;
2100	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2101	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2102	break;
2103	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2104	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2105	break;
2106	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2107	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2108	break;
2109	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2110	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2111	break;
2112	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2113	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2114	break;
2115	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2116	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2117	break;
2118	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2119	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2120	break;
2121	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2122	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2123	break;
2124	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2125	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2126	break;
2127	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2128	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2129	break;
2130	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2131	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2132	break;
2133	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2134	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2135	break;
2136	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2137	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2138	break;
2139	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2140	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2141	break;
2142	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2143	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2144	break;
2145	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2146	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2147	break;
2148	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2149	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2150	break;
2151	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2152	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2153	break;
2154	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2155	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2156	break;
2157	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2158	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2159	break;
2160	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2161	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2162	break;
2163	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2164	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2165	break;
2166	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2167	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2168	break;
2169	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2170	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2171	break;
2172	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2173	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2174	break;
2175	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2176	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2177	break;
2178	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2179	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2180	break;
2181	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2182	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2183	break;
2184	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2185	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2186	break;
2187	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2188	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2189	break;
2190	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2191	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2192	break;
2193	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2194	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2195	break;
2196	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2197	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2198	break;
2199	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2200	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2201	break;
2202	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2203	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2204	break;
2205	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2206	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2207	break;
2208	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2209	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2210	break;
2211	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2212	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2213	break;
2214	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2215	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2216	break;
2217	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2218	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2219	break;
2220	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2221	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2222	break;
2223	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2224	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2225	break;
2226	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2227	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2228	break;
2229	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2230	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2231	break;
2232	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2233	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2234	break;
2235	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2236	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2237	break;
2238	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2239	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2240	break;
2241	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2242	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2243	break;
2244	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2245	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2246	break;
2247	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2248	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2249	break;
2250	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2251	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2252	break;
2253	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2254	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2255	break;
2256	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2257	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2258	break;
2259	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2260	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2261	break;
2262	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2263	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2264	break;
2265	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2266	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2267	break;
2268	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2269	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2270	break;
2271	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2272	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2273	break;
2274	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2275	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2276	break;
2277	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2278	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2279	break;
2280	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2281	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2282	break;
2283	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2284	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2285	break;
2286	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2287	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2288	break;
2289	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2290	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2291	break;
2292	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2293	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2294	break;
2295	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2296	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2297	break;
2298	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2299	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2300	break;
2301	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2302	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2303	break;
2304	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2305	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2306	break;
2307	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2308	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2309	break;
2310	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2311	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2312	break;
2313	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2314	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2315	break;
2316	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2317	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2318	break;
2319	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2320	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2321	break;
2322	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2323	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2324	break;
2325	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2326	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2327	break;
2328	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2329	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2330	break;
2331	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2332	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2333	break;
2334	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2335	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2336	break;
2337	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2338	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2339	break;
2340	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2341	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2342	break;
2343	case SVGA_FIFO_3D_CAPS_LAST:
2344	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2345	break;
2346	case SVGA_FIFO_GUEST_3D_HWVERSION:
2347	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2348	break;
2349	case SVGA_FIFO_FENCE_GOAL:
2350	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2351	break;
2352	case SVGA_FIFO_BUSY:
2353	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2354	break;
2355	default:
2356	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2357	break;
2358	}
2359
2360	return VINF_EM_RAW_EMULATE_INSTR;
2361	}
2362	# endif /* DEBUG_FIFO_ACCESS */
2363
2364	/**
2365	* HC access handler for the FIFO.
2366	*
2367	* @returns VINF_SUCCESS if the handler have carried out the operation.
2368	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2369	* @param pVM VM Handle.
2370	* @param pVCpu The cross context CPU structure for the calling EMT.
2371	* @param GCPhys The physical address the guest is writing to.
2372	* @param pvPhys The HC mapping of that address.
2373	* @param pvBuf What the guest is reading/writing.
2374	* @param cbBuf How much it's reading/writing.
2375	* @param enmAccessType The access type.
2376	* @param enmOrigin Who is making the access.
2377	* @param pvUser User argument.
2378	*/
2379	static DECLCALLBACK(VBOXSTRICTRC)
2380	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2381	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2382	{
2383	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2384	PVGASTATE pThis = (PVGASTATE)pvUser;
2385	AssertPtr(pThis);
2386
2387	/*
2388	* Wake up the FIFO thread as it might have work to do now.
2389	*/
2390	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2391	AssertLogRelRC(rc);
2392
2393	# ifdef DEBUG_FIFO_ACCESS
2394	/*
2395	* When in debug-fifo-access mode, we do not disable the access handler,
2396	* but leave it on as we wish to catch all access.
2397	*/
2398	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2399	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2400	# else
2401	/*
2402	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2403	*/
2404
2405	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2406	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2407	# endif
2408	if (RT_SUCCESS(rc))
2409	return VINF_PGM_HANDLER_DO_DEFAULT;
2410	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2411	return rc;
2412	}
2413
2414	#endif /* IN_RING3 */
2415
2416	#ifdef DEBUG_GMR_ACCESS
2417	# ifdef IN_RING3
2418
2419	/**
2420	* HC access handler for the FIFO.
2421	*
2422	* @returns VINF_SUCCESS if the handler have carried out the operation.
2423	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2424	* @param pVM VM Handle.
2425	* @param pVCpu The cross context CPU structure for the calling EMT.
2426	* @param GCPhys The physical address the guest is writing to.
2427	* @param pvPhys The HC mapping of that address.
2428	* @param pvBuf What the guest is reading/writing.
2429	* @param cbBuf How much it's reading/writing.
2430	* @param enmAccessType The access type.
2431	* @param enmOrigin Who is making the access.
2432	* @param pvUser User argument.
2433	*/
2434	static DECLCALLBACK(VBOXSTRICTRC)
2435	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2436	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2437	{
2438	PVGASTATE pThis = (PVGASTATE)pvUser;
2439	Assert(pThis);
2440	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2441	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2442
2443	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2444
2445	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2446	{
2447	PGMR pGMR = &pSVGAState->paGMR[i];
2448
2449	if (pGMR->numDescriptors)
2450	{
2451	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2452	{
2453	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2454	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2455	{
2456	/*
2457	* Turn off the write handler for this particular page and make it R/W.
2458	* Then return telling the caller to restart the guest instruction.
2459	*/
2460	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2461	AssertRC(rc);
2462	goto end;
2463	}
2464	}
2465	}
2466	}
2467	end:
2468	return VINF_PGM_HANDLER_DO_DEFAULT;
2469	}
2470
2471	/* Callback handler for VMR3ReqCallWaitU */
2472	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2473	{
2474	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2475	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2476	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2477	int rc;
2478
2479	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2480	{
2481	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2482	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2483	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2484	AssertRC(rc);
2485	}
2486	return VINF_SUCCESS;
2487	}
2488
2489	/* Callback handler for VMR3ReqCallWaitU */
2490	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2491	{
2492	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2493	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2494	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2495
2496	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2497	{
2498	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2499	AssertRC(rc);
2500	}
2501	return VINF_SUCCESS;
2502	}
2503
2504	/* Callback handler for VMR3ReqCallWaitU */
2505	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2506	{
2507	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2508
2509	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2510	{
2511	PGMR pGMR = &pSVGAState->paGMR[i];
2512
2513	if (pGMR->numDescriptors)
2514	{
2515	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2516	{
2517	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2518	AssertRC(rc);
2519	}
2520	}
2521	}
2522	return VINF_SUCCESS;
2523	}
2524
2525	# endif /* IN_RING3 */
2526	#endif /* DEBUG_GMR_ACCESS */
2527
2528	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2529
2530	#ifdef IN_RING3
2531
2532
2533	/**
2534	* Common worker for changing the pointer shape.
2535	*
2536	* @param pThis The VGA instance data.
2537	* @param pSVGAState The VMSVGA ring-3 instance data.
2538	* @param fAlpha Whether there is alpha or not.
2539	* @param xHot Hotspot x coordinate.
2540	* @param yHot Hotspot y coordinate.
2541	* @param cx Width.
2542	* @param cy Height.
2543	* @param pbData Heap copy of the cursor data. Consumed.
2544	* @param cbData The size of the data.
2545	*/
2546	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2547	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2548	{
2549	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2550	#ifdef LOG_ENABLED
2551	if (LogIs2Enabled())
2552	{
2553	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2554	if (!fAlpha)
2555	{
2556	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2557	for (uint32_t y = 0; y < cy; y++)
2558	{
2559	Log2(("%3u:", y));
2560	uint8_t const pbLine = &pbData[y cbAndLine];
2561	for (uint32_t x = 0; x < cx; x += 8)
2562	{
2563	uint8_t b = pbLine[x / 8];
2564	char szByte[12];
2565	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2566	szByte[1] = b & 0x40 ? '*' : ' ';
2567	szByte[2] = b & 0x20 ? '*' : ' ';
2568	szByte[3] = b & 0x10 ? '*' : ' ';
2569	szByte[4] = b & 0x08 ? '*' : ' ';
2570	szByte[5] = b & 0x04 ? '*' : ' ';
2571	szByte[6] = b & 0x02 ? '*' : ' ';
2572	szByte[7] = b & 0x01 ? '*' : ' ';
2573	szByte[8] = '\0';
2574	Log2(("%s", szByte));
2575	}
2576	Log2(("\n"));
2577	}
2578	}
2579
2580	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2581	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2582	for (uint32_t y = 0; y < cy; y++)
2583	{
2584	Log2(("%3u:", y));
2585	uint32_t const pu32Line = &pu32Xor[y cx];
2586	for (uint32_t x = 0; x < cx; x++)
2587	Log2((" %08x", pu32Line[x]));
2588	Log2(("\n"));
2589	}
2590	}
2591	#endif
2592
2593	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2594	AssertRC(rc);
2595
2596	if (pSVGAState->Cursor.fActive)
2597	RTMemFree(pSVGAState->Cursor.pData);
2598
2599	pSVGAState->Cursor.fActive = true;
2600	pSVGAState->Cursor.xHotspot = xHot;
2601	pSVGAState->Cursor.yHotspot = yHot;
2602	pSVGAState->Cursor.width = cx;
2603	pSVGAState->Cursor.height = cy;
2604	pSVGAState->Cursor.cbData = cbData;
2605	pSVGAState->Cursor.pData = pbData;
2606	}
2607
2608
2609	/**
2610	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2611	*
2612	* @param pThis The VGA instance data.
2613	* @param pSVGAState The VMSVGA ring-3 instance data.
2614	* @param pCursor The cursor.
2615	* @param pbSrcAndMask The AND mask.
2616	* @param cbSrcAndLine The scanline length of the AND mask.
2617	* @param pbSrcXorMask The XOR mask.
2618	* @param cbSrcXorLine The scanline length of the XOR mask.
2619	*/
2620	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2621	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2622	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2623	{
2624	uint32_t const cx = pCursor->width;
2625	uint32_t const cy = pCursor->height;
2626
2627	/*
2628	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2629	* The AND data uses 8-bit aligned scanlines.
2630	* The XOR data must be starting on a 32-bit boundrary.
2631	*/
2632	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2633	uint32_t cbDstAndMask = cbDstAndLine * cy;
2634	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2635	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2636
2637	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2638	AssertReturnVoid(pbCopy);
2639
2640	/* Convert the AND mask. */
2641	uint8_t *pbDst = pbCopy;
2642	uint8_t const *pbSrc = pbSrcAndMask;
2643	switch (pCursor->andMaskDepth)
2644	{
2645	case 1:
2646	if (cbSrcAndLine == cbDstAndLine)
2647	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2648	else
2649	{
2650	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2651	for (uint32_t y = 0; y < cy; y++)
2652	{
2653	memcpy(pbDst, pbSrc, cbDstAndLine);
2654	pbDst += cbDstAndLine;
2655	pbSrc += cbSrcAndLine;
2656	}
2657	}
2658	break;
2659	/* Should take the XOR mask into account for the multi-bit AND mask. */
2660	case 8:
2661	for (uint32_t y = 0; y < cy; y++)
2662	{
2663	for (uint32_t x = 0; x < cx; )
2664	{
2665	uint8_t bDst = 0;
2666	uint8_t fBit = 1;
2667	do
2668	{
2669	uintptr_t const idxPal = pbSrc[x] * 3;
2670	if ((( pThis->last_palette[idxPal]
2671	\| (pThis->last_palette[idxPal] >> 8)
2672	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2673	bDst \|= fBit;
2674	fBit <<= 1;
2675	x++;
2676	} while (x < cx && (x & 7));
2677	pbDst[(x - 1) / 8] = bDst;
2678	}
2679	pbDst += cbDstAndLine;
2680	pbSrc += cbSrcAndLine;
2681	}
2682	break;
2683	case 15:
2684	for (uint32_t y = 0; y < cy; y++)
2685	{
2686	for (uint32_t x = 0; x < cx; )
2687	{
2688	uint8_t bDst = 0;
2689	uint8_t fBit = 1;
2690	do
2691	{
2692	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2693	bDst \|= fBit;
2694	fBit <<= 1;
2695	x++;
2696	} while (x < cx && (x & 7));
2697	pbDst[(x - 1) / 8] = bDst;
2698	}
2699	pbDst += cbDstAndLine;
2700	pbSrc += cbSrcAndLine;
2701	}
2702	break;
2703	case 16:
2704	for (uint32_t y = 0; y < cy; y++)
2705	{
2706	for (uint32_t x = 0; x < cx; )
2707	{
2708	uint8_t bDst = 0;
2709	uint8_t fBit = 1;
2710	do
2711	{
2712	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2713	bDst \|= fBit;
2714	fBit <<= 1;
2715	x++;
2716	} while (x < cx && (x & 7));
2717	pbDst[(x - 1) / 8] = bDst;
2718	}
2719	pbDst += cbDstAndLine;
2720	pbSrc += cbSrcAndLine;
2721	}
2722	break;
2723	case 24:
2724	for (uint32_t y = 0; y < cy; y++)
2725	{
2726	for (uint32_t x = 0; x < cx; )
2727	{
2728	uint8_t bDst = 0;
2729	uint8_t fBit = 1;
2730	do
2731	{
2732	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2733	bDst \|= fBit;
2734	fBit <<= 1;
2735	x++;
2736	} while (x < cx && (x & 7));
2737	pbDst[(x - 1) / 8] = bDst;
2738	}
2739	pbDst += cbDstAndLine;
2740	pbSrc += cbSrcAndLine;
2741	}
2742	break;
2743	case 32:
2744	for (uint32_t y = 0; y < cy; y++)
2745	{
2746	for (uint32_t x = 0; x < cx; )
2747	{
2748	uint8_t bDst = 0;
2749	uint8_t fBit = 1;
2750	do
2751	{
2752	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2753	bDst \|= fBit;
2754	fBit <<= 1;
2755	x++;
2756	} while (x < cx && (x & 7));
2757	pbDst[(x - 1) / 8] = bDst;
2758	}
2759	pbDst += cbDstAndLine;
2760	pbSrc += cbSrcAndLine;
2761	}
2762	break;
2763	default:
2764	RTMemFree(pbCopy);
2765	AssertFailedReturnVoid();
2766	}
2767
2768	/* Convert the XOR mask. */
2769	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2770	pbSrc = pbSrcXorMask;
2771	switch (pCursor->xorMaskDepth)
2772	{
2773	case 1:
2774	for (uint32_t y = 0; y < cy; y++)
2775	{
2776	for (uint32_t x = 0; x < cx; )
2777	{
2778	/* most significant bit is the left most one. */
2779	uint8_t bSrc = pbSrc[x / 8];
2780	do
2781	{
2782	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2783	bSrc <<= 1;
2784	x++;
2785	} while ((x & 7) && x < cx);
2786	}
2787	pbSrc += cbSrcXorLine;
2788	}
2789	break;
2790	case 8:
2791	for (uint32_t y = 0; y < cy; y++)
2792	{
2793	for (uint32_t x = 0; x < cx; x++)
2794	{
2795	uint32_t u = pThis->last_palette[pbSrc[x]];
2796	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2797	}
2798	pbSrc += cbSrcXorLine;
2799	}
2800	break;
2801	case 15: /* Src: RGB-5-5-5 */
2802	for (uint32_t y = 0; y < cy; y++)
2803	{
2804	for (uint32_t x = 0; x < cx; x++)
2805	{
2806	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2807	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2808	((uValue >> 5) & 0x1f) << 3,
2809	((uValue >> 10) & 0x1f) << 3, 0);
2810	}
2811	pbSrc += cbSrcXorLine;
2812	}
2813	break;
2814	case 16: /* Src: RGB-5-6-5 */
2815	for (uint32_t y = 0; y < cy; y++)
2816	{
2817	for (uint32_t x = 0; x < cx; x++)
2818	{
2819	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2820	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2821	((uValue >> 5) & 0x3f) << 2,
2822	((uValue >> 11) & 0x1f) << 3, 0);
2823	}
2824	pbSrc += cbSrcXorLine;
2825	}
2826	break;
2827	case 24:
2828	for (uint32_t y = 0; y < cy; y++)
2829	{
2830	for (uint32_t x = 0; x < cx; x++)
2831	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2832	pbSrc += cbSrcXorLine;
2833	}
2834	break;
2835	case 32:
2836	for (uint32_t y = 0; y < cy; y++)
2837	{
2838	for (uint32_t x = 0; x < cx; x++)
2839	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2840	pbSrc += cbSrcXorLine;
2841	}
2842	break;
2843	default:
2844	RTMemFree(pbCopy);
2845	AssertFailedReturnVoid();
2846	}
2847
2848	/*
2849	* Pass it to the frontend/whatever.
2850	*/
2851	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2852	}
2853
2854
2855	/**
2856	* Worker for vmsvgaR3FifoThread that handles an external command.
2857	*
2858	* @param pThis VGA device instance data.
2859	*/
2860	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2861	{
2862	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2863	switch (pThis->svga.u8FIFOExtCommand)
2864	{
2865	case VMSVGA_FIFO_EXTCMD_RESET:
2866	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2867	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2868	# ifdef VBOX_WITH_VMSVGA3D
2869	if (pThis->svga.f3DEnabled)
2870	{
2871	/* The 3d subsystem must be reset from the fifo thread. */
2872	vmsvga3dReset(pThis);
2873	}
2874	# endif
2875	break;
2876
2877	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2878	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2879	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2880	# ifdef VBOX_WITH_VMSVGA3D
2881	if (pThis->svga.f3DEnabled)
2882	{
2883	/* The 3d subsystem must be shut down from the fifo thread. */
2884	vmsvga3dTerminate(pThis);
2885	}
2886	# endif
2887	break;
2888
2889	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2890	{
2891	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2892	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2893	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2894	vmsvgaSaveExecFifo(pThis, pSSM);
2895	# ifdef VBOX_WITH_VMSVGA3D
2896	if (pThis->svga.f3DEnabled)
2897	vmsvga3dSaveExec(pThis, pSSM);
2898	# endif
2899	break;
2900	}
2901
2902	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2903	{
2904	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2905	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2906	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2907	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2908	# ifdef VBOX_WITH_VMSVGA3D
2909	if (pThis->svga.f3DEnabled)
2910	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2911	# endif
2912	break;
2913	}
2914
2915	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2916	{
2917	# ifdef VBOX_WITH_VMSVGA3D
2918	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2919	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2920	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2921	# endif
2922	break;
2923	}
2924
2925
2926	default:
2927	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2928	break;
2929	}
2930
2931	/*
2932	* Signal the end of the external command.
2933	*/
2934	pThis->svga.pvFIFOExtCmdParam = NULL;
2935	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2936	ASMMemoryFence(); /* paranoia^2 */
2937	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2938	AssertLogRelRC(rc);
2939	}
2940
2941	/**
2942	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2943	* doing a job on the FIFO thread (even when it's officially suspended).
2944	*
2945	* @returns VBox status code (fully asserted).
2946	* @param pThis VGA device instance data.
2947	* @param uExtCmd The command to execute on the FIFO thread.
2948	* @param pvParam Pointer to command parameters.
2949	* @param cMsWait The time to wait for the command, given in
2950	* milliseconds.
2951	*/
2952	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2953	{
2954	Assert(cMsWait >= RT_MS_1SEC * 5);
2955	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2956	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2957
2958	int rc;
2959	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2960	PDMTHREADSTATE enmState = pThread->enmState;
2961	if (enmState == PDMTHREADSTATE_SUSPENDED)
2962	{
2963	/*
2964	* The thread is suspended, we have to temporarily wake it up so it can
2965	* perform the task.
2966	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2967	*/
2968	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2969	/* Post the request. */
2970	pThis->svga.fFifoExtCommandWakeup = true;
2971	pThis->svga.pvFIFOExtCmdParam = pvParam;
2972	pThis->svga.u8FIFOExtCommand = uExtCmd;
2973	ASMMemoryFence(); /* paranoia^3 */
2974
2975	/* Resume the thread. */
2976	rc = PDMR3ThreadResume(pThread);
2977	AssertLogRelRC(rc);
2978	if (RT_SUCCESS(rc))
2979	{
2980	/* Wait. Take care in case the semaphore was already posted (same as below). */
2981	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2982	if ( rc == VINF_SUCCESS
2983	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2984	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2985	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2986	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2987
2988	/* suspend the thread */
2989	pThis->svga.fFifoExtCommandWakeup = false;
2990	int rc2 = PDMR3ThreadSuspend(pThread);
2991	AssertLogRelRC(rc2);
2992	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2993	rc = rc2;
2994	}
2995	pThis->svga.fFifoExtCommandWakeup = false;
2996	pThis->svga.pvFIFOExtCmdParam = NULL;
2997	}
2998	else if (enmState == PDMTHREADSTATE_RUNNING)
2999	{
3000	/*
3001	* The thread is running, should only happen during reset and vmsvga3dsfc.
3002	* We ASSUME not racing code here, both wrt thread state and ext commands.
3003	*/
3004	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3005	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3006
3007	/* Post the request. */
3008	pThis->svga.pvFIFOExtCmdParam = pvParam;
3009	pThis->svga.u8FIFOExtCommand = uExtCmd;
3010	ASMMemoryFence(); /* paranoia^2 */
3011	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3012	AssertLogRelRC(rc);
3013
3014	/* Wait. Take care in case the semaphore was already posted (same as above). */
3015	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3016	if ( rc == VINF_SUCCESS
3017	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3018	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3019	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3020	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3021
3022	pThis->svga.pvFIFOExtCmdParam = NULL;
3023	}
3024	else
3025	{
3026	/*
3027	* Something is wrong with the thread!
3028	*/
3029	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3030	rc = VERR_INVALID_STATE;
3031	}
3032	return rc;
3033	}
3034
3035
3036	/**
3037	* Marks the FIFO non-busy, notifying any waiting EMTs.
3038	*
3039	* @param pThis The VGA state.
3040	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3041	* @param offFifoMin The start byte offset of the command FIFO.
3042	*/
3043	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3044	{
3045	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3046	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3047	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3048
3049	/* Wake up any waiting EMTs. */
3050	if (pSVGAState->cBusyDelayedEmts > 0)
3051	{
3052	#ifdef VMSVGA_USE_EMT_HALT_CODE
3053	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3054	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3055	if (idCpu != NIL_VMCPUID)
3056	{
3057	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3058	while (idCpu-- > 0)
3059	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3060	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3061	}
3062	#else
3063	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3064	AssertRC(rc2);
3065	#endif
3066	}
3067	}
3068
3069	/**
3070	* Reads (more) payload into the command buffer.
3071	*
3072	* @returns pbBounceBuf on success
3073	* @retval (void *)1 if the thread was requested to stop.
3074	* @retval NULL on FIFO error.
3075	*
3076	* @param cbPayloadReq The number of bytes of payload requested.
3077	* @param pFIFO The FIFO.
3078	* @param offCurrentCmd The FIFO byte offset of the current command.
3079	* @param offFifoMin The start byte offset of the command FIFO.
3080	* @param offFifoMax The end byte offset of the command FIFO.
3081	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3082	* always sufficient size.
3083	* @param pcbAlreadyRead How much payload we've already read into the bounce
3084	* buffer. (We will NEVER re-read anything.)
3085	* @param pThread The calling PDM thread handle.
3086	* @param pThis The VGA state.
3087	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3088	* statistics collection.
3089	*/
3090	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3091	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3092	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3093	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3094	{
3095	Assert(pbBounceBuf);
3096	Assert(pcbAlreadyRead);
3097	Assert(offFifoMin < offFifoMax);
3098	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3099	Assert(offFifoMax <= pThis->svga.cbFIFO);
3100
3101	/*
3102	* Check if the requested payload size has already been satisfied .
3103	* .
3104	* When called to read more, the caller is responsible for making sure the .
3105	* new command size (cbRequsted) never is smaller than what has already .
3106	* been read.
3107	*/
3108	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3109	if (cbPayloadReq <= cbAlreadyRead)
3110	{
3111	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3112	return pbBounceBuf;
3113	}
3114
3115	/*
3116	* Commands bigger than the fifo buffer are invalid.
3117	*/
3118	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3119	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3120	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3121	NULL);
3122
3123	/*
3124	* Move offCurrentCmd past the command dword.
3125	*/
3126	offCurrentCmd += sizeof(uint32_t);
3127	if (offCurrentCmd >= offFifoMax)
3128	offCurrentCmd = offFifoMin;
3129
3130	/*
3131	* Do we have sufficient payload data available already?
3132	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3133	*/
3134	uint32_t cbAfter, cbBefore;
3135	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3136	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3137	if (offNextCmd >= offCurrentCmd)
3138	{
3139	if (RT_LIKELY(offNextCmd < offFifoMax))
3140	cbAfter = offNextCmd - offCurrentCmd;
3141	else
3142	{
3143	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3144	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3145	offNextCmd, offFifoMin, offFifoMax));
3146	cbAfter = offFifoMax - offCurrentCmd;
3147	}
3148	cbBefore = 0;
3149	}
3150	else
3151	{
3152	cbAfter = offFifoMax - offCurrentCmd;
3153	if (offNextCmd >= offFifoMin)
3154	cbBefore = offNextCmd - offFifoMin;
3155	else
3156	{
3157	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3158	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3159	offNextCmd, offFifoMin, offFifoMax));
3160	cbBefore = 0;
3161	}
3162	}
3163	if (cbAfter + cbBefore < cbPayloadReq)
3164	{
3165	/*
3166	* Insufficient, must wait for it to arrive.
3167	*/
3168	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3169	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3170	for (uint32_t i = 0;; i++)
3171	{
3172	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3173	{
3174	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3175	return (void *)(uintptr_t)1;
3176	}
3177	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3178	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3179
3180	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3181
3182	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3183	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3184	if (offNextCmd >= offCurrentCmd)
3185	{
3186	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3187	cbBefore = 0;
3188	}
3189	else
3190	{
3191	cbAfter = offFifoMax - offCurrentCmd;
3192	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3193	}
3194
3195	if (cbAfter + cbBefore >= cbPayloadReq)
3196	break;
3197	}
3198	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3199	}
3200
3201	/*
3202	* Copy out the memory and update what pcbAlreadyRead points to.
3203	*/
3204	if (cbAfter >= cbPayloadReq)
3205	memcpy(pbBounceBuf + cbAlreadyRead,
3206	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3207	cbPayloadReq - cbAlreadyRead);
3208	else
3209	{
3210	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3211	if (cbAlreadyRead < cbAfter)
3212	{
3213	memcpy(pbBounceBuf + cbAlreadyRead,
3214	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3215	cbAfter - cbAlreadyRead);
3216	cbAlreadyRead = cbAfter;
3217	}
3218	memcpy(pbBounceBuf + cbAlreadyRead,
3219	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3220	cbPayloadReq - cbAlreadyRead);
3221	}
3222	*pcbAlreadyRead = cbPayloadReq;
3223	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3224	return pbBounceBuf;
3225	}
3226
3227
3228	/**
3229	* Sends cursor position and visibility information from the FIFO to the front-end.
3230	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3231	*/
3232	static uint32_t
3233	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3234	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3235	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3236	{
3237	/*
3238	* Check if the cursor update counter has changed and try get a stable
3239	* set of values if it has. This is race-prone, especially consindering
3240	* the screen ID, but little we can do about that.
3241	*/
3242	uint32_t x, y, fVisible, idScreen;
3243	for (uint32_t i = 0; ; i++)
3244	{
3245	x = pFIFO[SVGA_FIFO_CURSOR_X];
3246	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3247	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3248	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3249	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3250	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3251	\|\| i > 3)
3252	break;
3253	if (i == 0)
3254	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3255	ASMNopPause();
3256	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3257	}
3258
3259	/*
3260	* Check if anything has changed, as calling into pDrv is not light-weight.
3261	*/
3262	if ( *pxLast == x
3263	&& *pyLast == y
3264	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3265	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3266	else
3267	{
3268	/*
3269	* Detected changes.
3270	*
3271	* We handle global, not per-screen visibility information by sending
3272	* pfnVBVAMousePointerShape without shape data.
3273	*/
3274	*pxLast = x;
3275	*pyLast = y;
3276	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3277	if (idScreen != SVGA_ID_INVALID)
3278	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3279	else if (*pfLastVisible != fVisible)
3280	{
3281	*pfLastVisible = fVisible;
3282	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3283	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3284	}
3285	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3286	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3287	}
3288
3289	/*
3290	* Update done. Signal this to the guest.
3291	*/
3292	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3293
3294	return uCursorUpdateCount;
3295	}
3296
3297
3298	/**
3299	* Checks if there is work to be done, either cursor updating or FIFO commands.
3300	*
3301	* @returns true if pending work, false if not.
3302	* @param pFIFO The FIFO to examine.
3303	* @param uLastCursorCount The last cursor update counter value.
3304	*/
3305	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3306	{
3307	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3308	return true;
3309
3310	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3311	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3312	return true;
3313
3314	return false;
3315	}
3316
3317
3318	/* The async FIFO handling thread. */
3319	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3320	{
3321	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3322	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3323	int rc;
3324
3325	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3326	return VINF_SUCCESS;
3327
3328	/*
3329	* Special mode where we only execute an external command and the go back
3330	* to being suspended. Currently, all ext cmds ends up here, with the reset
3331	* one also being eligble for runtime execution further down as well.
3332	*/
3333	if (pThis->svga.fFifoExtCommandWakeup)
3334	{
3335	vmsvgaR3FifoHandleExtCmd(pThis);
3336	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3337	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3338	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3339	else
3340	vmsvgaR3FifoHandleExtCmd(pThis);
3341	return VINF_SUCCESS;
3342	}
3343
3344
3345	/*
3346	* Signal the semaphore to make sure we don't wait for 250ms after a
3347	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3348	*/
3349	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3350
3351	/*
3352	* Allocate a bounce buffer for command we get from the FIFO.
3353	* (All code must return via the end of the function to free this buffer.)
3354	*/
3355	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3356	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3357
3358	/*
3359	* Polling/sleep interval config.
3360	*
3361	* We wait for an a short interval if the guest has recently given us work
3362	* to do, but the interval increases the longer we're kept idle. After
3363	* about a second we'll switch to long sleeps and using an access handler
3364	* monitoring writes to the first FIFO page to wake us up. Should the FIFO
3365	* not be mapped, we will continue increasing the wait interval till it
3366	* reaches the 250ms max after about 16 seconds.
3367	*/
3368	RTMSINTERVAL const cMsMinSleep = 16;
3369	RTMSINTERVAL const cMsIncSleep = 2;
3370	RTMSINTERVAL const cMsMaxSleep = 250;
3371	RTMSINTERVAL const cMsAccessHandlerThres = 66;
3372	RTMSINTERVAL const cMsAccessHandlerSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3373	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3374
3375	/*
3376	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3377	* Initialize with values that will trigger an update as soon as maybe.
3378	*/
3379	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3380	uint32_t uLastCursorCount = ~pFIFO[SVGA_FIFO_CURSOR_COUNT];
3381	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3382	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3383	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3384
3385	/*
3386	* The FIFO loop.
3387	*/
3388	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3389	bool fBadOrDisabledFifo = false;
3390	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3391	{
3392	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3393	/*
3394	* Should service the run loop every so often.
3395	*/
3396	if (pThis->svga.f3DEnabled)
3397	vmsvga3dCocoaServiceRunLoop();
3398	# endif
3399
3400	/*
3401	* Unless there's already work pending, go to sleep for a short while.
3402	* (See polling/sleep interval config above.)
3403	*/
3404	if ( fBadOrDisabledFifo
3405	\|\| !vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3406	{
3407	if ( cMsSleep < cMsAccessHandlerThres
3408	\|\| !pThis->svga.GCPhysFIFO /* yeah, really zero rather than NIL when unmapped. */)
3409	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3410	else
3411	{
3412	# ifdef VBOX_STRICT
3413	/* Invariant: The access handler should never be reset twice within
3414	a certain time span; calling it 500ms here for simplicity. */
3415	uint64_t TimeNow = RTTimeMilliTS();
3416	Assert(TimeNow - pSVGAState->TimeLastFIFOIntercept > 500);
3417	pSVGAState->TimeLastFIFOIntercept = TimeNow;
3418	# endif
3419	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3420	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3421
3422	if ( fBadOrDisabledFifo
3423	\|\| !vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3424	{
3425	STAM_REL_PROFILE_START(&pSVGAState->StatFifoSleepOnHandler, Acc);
3426	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsAccessHandlerSleep);
3427	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoSleepOnHandler, Acc);
3428	}
3429	else
3430	rc = VINF_SUCCESS;
3431	}
3432	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3433	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3434	{
3435	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3436	break;
3437	}
3438	}
3439	else
3440	rc = VINF_SUCCESS;
3441	fBadOrDisabledFifo = false;
3442	if (rc == VERR_TIMEOUT)
3443	{
3444	if (!vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3445	{
3446	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3447	continue;
3448	}
3449	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3450
3451	Log(("vmsvgaFIFOLoop: timeout\n"));
3452	}
3453	else if (vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3454	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3455	cMsSleep = cMsMinSleep;
3456
3457	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3458	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3459	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3460
3461	/*
3462	* Handle external commands (currently only reset).
3463	*/
3464	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3465	{
3466	vmsvgaR3FifoHandleExtCmd(pThis);
3467	continue;
3468	}
3469
3470	/*
3471	* The device must be enabled and configured.
3472	*/
3473	if ( !pThis->svga.fEnabled
3474	\|\| !pThis->svga.fConfigured)
3475	{
3476	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3477	fBadOrDisabledFifo = true;
3478	cMsSleep = cMsMaxSleep; /* cheat */
3479	continue;
3480	}
3481
3482	/*
3483	* Get and check the min/max values. We ASSUME that they will remain
3484	* unchanged while we process requests. A further ASSUMPTION is that
3485	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3486	* we don't read it back while in the loop.
3487	*/
3488	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3489	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3490	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3491	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3492	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3493	\|\| offFifoMax <= offFifoMin
3494	\|\| offFifoMax > pThis->svga.cbFIFO
3495	\|\| (offFifoMax & 3) != 0
3496	\|\| (offFifoMin & 3) != 0
3497	\|\| offCurrentCmd < offFifoMin
3498	\|\| offCurrentCmd > offFifoMax))
3499	{
3500	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3501	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3502	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3503	fBadOrDisabledFifo = true;
3504	continue;
3505	}
3506	RT_UNTRUSTED_VALIDATED_FENCE();
3507	if (RT_UNLIKELY(offCurrentCmd & 3))
3508	{
3509	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3510	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3511	offCurrentCmd = ~UINT32_C(3);
3512	}
3513
3514	/*
3515	* Update the cursor position before we start on the FIFO commands.
3516	*/
3517	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3518	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3519	{
3520	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3521	if (uCursorUpdateCount == uLastCursorCount)
3522	{ /* halfways likely */ }
3523	else
3524	uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3525	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3526	}
3527
3528	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3529	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3530	*
3531	* Will break out of the switch on failure.
3532	* Will restart and quit the loop if the thread was requested to stop.
3533	*
3534	* @param a_PtrVar Request variable pointer.
3535	* @param a_Type Request typedef (not pointer) for casting.
3536	* @param a_cbPayloadReq How much payload to fetch.
3537	* @remarks Accesses a bunch of variables in the current scope!
3538	*/
3539	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3540	if (1) { \
3541	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3542	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3543	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3544	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3545	} else do {} while (0)
3546	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3547	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3548	* buffer after figuring out the actual command size.
3549	*
3550	* Will break out of the switch on failure.
3551	*
3552	* @param a_PtrVar Request variable pointer.
3553	* @param a_Type Request typedef (not pointer) for casting.
3554	* @param a_cbPayloadReq How much payload to fetch.
3555	* @remarks Accesses a bunch of variables in the current scope!
3556	*/
3557	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3558	if (1) { \
3559	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3560	} else do {} while (0)
3561
3562	/*
3563	* Mark the FIFO as busy.
3564	*/
3565	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3566	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3567	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3568
3569	/*
3570	* Execute all queued FIFO commands.
3571	* Quit if pending external command or changes in the thread state.
3572	*/
3573	bool fDone = false;
3574	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3575	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3576	{
3577	uint32_t cbPayload = 0;
3578	uint32_t u32IrqStatus = 0;
3579
3580	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3581
3582	/* First check any pending actions. */
3583	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3584	{
3585	vmsvgaChangeMode(pThis);
3586	# ifdef VBOX_WITH_VMSVGA3D
3587	if (pThis->svga.p3dState != NULL)
3588	vmsvga3dChangeMode(pThis);
3589	# endif
3590	}
3591
3592	/* Check for pending external commands (reset). */
3593	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3594	break;
3595
3596	/*
3597	* Process the command.
3598	*/
3599	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3600	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3601	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3602	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3603	switch (enmCmdId)
3604	{
3605	case SVGA_CMD_INVALID_CMD:
3606	/* Nothing to do. */
3607	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3608	break;
3609
3610	case SVGA_CMD_FENCE:
3611	{
3612	SVGAFifoCmdFence *pCmdFence;
3613	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3614	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3615	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3616	{
3617	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3618	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3619
3620	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3621	{
3622	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3623	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3624	}
3625	else
3626	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3627	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3628	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3629	{
3630	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3631	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3632	}
3633	}
3634	else
3635	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3636	break;
3637	}
3638	case SVGA_CMD_UPDATE:
3639	case SVGA_CMD_UPDATE_VERBOSE:
3640	{
3641	SVGAFifoCmdUpdate *pUpdate;
3642	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3643	if (enmCmdId == SVGA_CMD_UPDATE)
3644	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3645	else
3646	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3647	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3648	/** @todo Multiple screens? */
3649	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3650	AssertBreak(pScreen);
3651	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3652	break;
3653	}
3654
3655	case SVGA_CMD_DEFINE_CURSOR:
3656	{
3657	/* Followed by bitmap data. */
3658	SVGAFifoCmdDefineCursor *pCursor;
3659	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3660	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3661
3662	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3663	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3664	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3665	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3666	AssertBreak(pCursor->andMaskDepth <= 32);
3667	AssertBreak(pCursor->xorMaskDepth <= 32);
3668	RT_UNTRUSTED_VALIDATED_FENCE();
3669
3670	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3671	uint32_t cbAndMask = cbAndLine * pCursor->height;
3672	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3673	uint32_t cbXorMask = cbXorLine * pCursor->height;
3674	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3675
3676	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3677	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3678	break;
3679	}
3680
3681	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3682	{
3683	/* Followed by bitmap data. */
3684	uint32_t cbCursorShape, cbAndMask;
3685	uint8_t *pCursorCopy;
3686	uint32_t cbCmd;
3687
3688	SVGAFifoCmdDefineAlphaCursor *pCursor;
3689	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3691
3692	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3693
3694	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3695	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3696	RT_UNTRUSTED_VALIDATED_FENCE();
3697
3698	/* Refetch the bitmap data as well. */
3699	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3700	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3701	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3702
3703	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3704	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3705	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3706	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3707
3708	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3709	AssertBreak(pCursorCopy);
3710
3711	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3712	memset(pCursorCopy, 0xff, cbAndMask);
3713	/* Colour data */
3714	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3715
3716	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3717	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3718	break;
3719	}
3720
3721	case SVGA_CMD_ESCAPE:
3722	{
3723	/* Followed by nsize bytes of data. */
3724	SVGAFifoCmdEscape *pEscape;
3725	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3726	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3727
3728	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3729	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3730	RT_UNTRUSTED_VALIDATED_FENCE();
3731	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3732	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3733
3734	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3735	{
3736	AssertBreak(pEscape->size >= sizeof(uint32_t));
3737	RT_UNTRUSTED_VALIDATED_FENCE();
3738	uint32_t cmd = (uint32_t )(pEscape + 1);
3739	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3740
3741	switch (cmd)
3742	{
3743	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3744	{
3745	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3746	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3747	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3748
3749	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3750	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3751	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3752
3753	RT_NOREF_PV(pVideoCmd);
3754	break;
3755
3756	}
3757
3758	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3759	{
3760	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3761	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3762	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3763	RT_NOREF_PV(pVideoCmd);
3764	break;
3765	}
3766
3767	default:
3768	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3769	break;
3770	}
3771	}
3772	else
3773	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3774
3775	break;
3776	}
3777	# ifdef VBOX_WITH_VMSVGA3D
3778	case SVGA_CMD_DEFINE_GMR2:
3779	{
3780	SVGAFifoCmdDefineGMR2 *pCmd;
3781	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3782	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3783	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3784
3785	/* Validate current GMR id. */
3786	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3787	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3788	RT_UNTRUSTED_VALIDATED_FENCE();
3789
3790	if (!pCmd->numPages)
3791	{
3792	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3793	vmsvgaGMRFree(pThis, pCmd->gmrId);
3794	}
3795	else
3796	{
3797	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3798	if (pGMR->cMaxPages)
3799	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3800
3801	/* Not sure if we should always free the descriptor, but for simplicity
3802	we do so if the new size is smaller than the current. */
3803	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3804	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3805	vmsvgaGMRFree(pThis, pCmd->gmrId);
3806
3807	pGMR->cMaxPages = pCmd->numPages;
3808	/* The rest is done by the REMAP_GMR2 command. */
3809	}
3810	break;
3811	}
3812
3813	case SVGA_CMD_REMAP_GMR2:
3814	{
3815	/* Followed by page descriptors or guest ptr. */
3816	SVGAFifoCmdRemapGMR2 *pCmd;
3817	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3818	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3819
3820	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3821	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3822	RT_UNTRUSTED_VALIDATED_FENCE();
3823
3824	/* Calculate the size of what comes after next and fetch it. */
3825	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3826	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3827	cbCmd += sizeof(SVGAGuestPtr);
3828	else
3829	{
3830	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3831	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3832	{
3833	cbCmd += cbPageDesc;
3834	pCmd->numPages = 1;
3835	}
3836	else
3837	{
3838	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3839	cbCmd += cbPageDesc * pCmd->numPages;
3840	}
3841	}
3842	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3843
3844	/* Validate current GMR id and size. */
3845	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3846	RT_UNTRUSTED_VALIDATED_FENCE();
3847	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3848	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3849	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3850	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3851
3852	if (pCmd->numPages == 0)
3853	break;
3854
3855	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3856	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3857
3858	/*
3859	* We flatten the existing descriptors into a page array, overwrite the
3860	* pages specified in this command and then recompress the descriptor.
3861	*/
3862	/** @todo Optimize the GMR remap algorithm! */
3863
3864	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3865	uint64_t *paNewPage64 = NULL;
3866	if (pGMR->paDesc)
3867	{
3868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3869
3870	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3871	AssertBreak(paNewPage64);
3872
3873	uint32_t idxPage = 0;
3874	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3875	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3876	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3877	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3878	RT_UNTRUSTED_VALIDATED_FENCE();
3879	}
3880
3881	/* Free the old GMR if present. */
3882	if (pGMR->paDesc)
3883	RTMemFree(pGMR->paDesc);
3884
3885	/* Allocate the maximum amount possible (everything non-continuous) */
3886	PVMSVGAGMRDESCRIPTOR paDescs;
3887	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3888	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3889
3890	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3891	{
3892	/** @todo */
3893	AssertFailed();
3894	pGMR->numDescriptors = 0;
3895	}
3896	else
3897	{
3898	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3899	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3900	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3901
3902	if (paNewPage64)
3903	{
3904	/* Overwrite the old page array with the new page values. */
3905	if (fGCPhys64)
3906	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3907	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3908	else
3909	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3910	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3911
3912	/* Use the updated page array instead of the command data. */
3913	fGCPhys64 = true;
3914	paPages64 = paNewPage64;
3915	pCmd->numPages = cNewTotalPages;
3916	}
3917
3918	/* The first page. */
3919	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3920	* applied to paNewPage64. */
3921	RTGCPHYS GCPhys;
3922	if (fGCPhys64)
3923	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3924	else
3925	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3926	paDescs[0].GCPhys = GCPhys;
3927	paDescs[0].numPages = 1;
3928
3929	/* Subsequent pages. */
3930	uint32_t iDescriptor = 0;
3931	for (uint32_t i = 1; i < pCmd->numPages; i++)
3932	{
3933	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3934	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3935	else
3936	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3937
3938	/* Continuous physical memory? */
3939	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3940	{
3941	Assert(paDescs[iDescriptor].numPages);
3942	paDescs[iDescriptor].numPages++;
3943	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3944	}
3945	else
3946	{
3947	iDescriptor++;
3948	paDescs[iDescriptor].GCPhys = GCPhys;
3949	paDescs[iDescriptor].numPages = 1;
3950	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3951	}
3952	}
3953
3954	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3955	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3956	pGMR->numDescriptors = iDescriptor + 1;
3957	}
3958
3959	if (paNewPage64)
3960	RTMemFree(paNewPage64);
3961
3962	# ifdef DEBUG_GMR_ACCESS
3963	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3964	# endif
3965	break;
3966	}
3967	# endif // VBOX_WITH_VMSVGA3D
3968	case SVGA_CMD_DEFINE_SCREEN:
3969	{
3970	/* The size of this command is specified by the guest and depends on capabilities. */
3971	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
3972
3973	SVGAFifoCmdDefineScreen *pCmd;
3974	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3975	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
3976	RT_UNTRUSTED_VALIDATED_FENCE();
3977
3978	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
3979	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3980	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3981
3982	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
3983	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
3984	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
3985
3986	uint32_t const idScreen = pCmd->screen.id;
3987	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3988
3989	uint32_t const uWidth = pCmd->screen.size.width;
3990	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
3991
3992	uint32_t const uHeight = pCmd->screen.size.height;
3993	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
3994
3995	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
3996	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
3997	AssertBreak(cbWidth <= cbPitch);
3998
3999	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4000	AssertBreak(uScreenOffset < pThis->vram_size);
4001
4002	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4003	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4004	AssertBreak( (uHeight == 0 && cbPitch == 0)
4005	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4006	RT_UNTRUSTED_VALIDATED_FENCE();
4007
4008	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4009
4010	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4011
4012	pScreen->fDefined = true;
4013	pScreen->fModified = true;
4014	pScreen->fuScreen = pCmd->screen.flags;
4015	pScreen->idScreen = idScreen;
4016	if (!fBlank)
4017	{
4018	AssertBreak(uWidth > 0 && uHeight > 0);
4019
4020	pScreen->xOrigin = pCmd->screen.root.x;
4021	pScreen->yOrigin = pCmd->screen.root.y;
4022	pScreen->cWidth = uWidth;
4023	pScreen->cHeight = uHeight;
4024	pScreen->offVRAM = uScreenOffset;
4025	pScreen->cbPitch = cbPitch;
4026	pScreen->cBpp = 32;
4027	}
4028	else
4029	{
4030	/* Keep old values. */
4031	}
4032
4033	pThis->svga.fGFBRegisters = false;
4034	vmsvgaChangeMode(pThis);
4035	break;
4036	}
4037
4038	case SVGA_CMD_DESTROY_SCREEN:
4039	{
4040	SVGAFifoCmdDestroyScreen *pCmd;
4041	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4042	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4043
4044	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4045
4046	uint32_t const idScreen = pCmd->screenId;
4047	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4048	RT_UNTRUSTED_VALIDATED_FENCE();
4049
4050	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4051	pScreen->fModified = true;
4052	pScreen->fDefined = false;
4053	pScreen->idScreen = idScreen;
4054
4055	vmsvgaChangeMode(pThis);
4056	break;
4057	}
4058
4059	case SVGA_CMD_DEFINE_GMRFB:
4060	{
4061	SVGAFifoCmdDefineGMRFB *pCmd;
4062	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4063	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4064
4065	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4066	pSVGAState->GMRFB.ptr = pCmd->ptr;
4067	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4068	pSVGAState->GMRFB.format = pCmd->format;
4069	break;
4070	}
4071
4072	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4073	{
4074	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4075	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4076	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4077
4078	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4079	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4080
4081	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4082	RT_UNTRUSTED_VALIDATED_FENCE();
4083
4084	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4085	AssertBreak(pScreen);
4086
4087	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4088	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4089
4090	/* Clip destRect to the screen dimensions. */
4091	SVGASignedRect screenRect;
4092	screenRect.left = 0;
4093	screenRect.top = 0;
4094	screenRect.right = pScreen->cWidth;
4095	screenRect.bottom = pScreen->cHeight;
4096	SVGASignedRect clipRect = pCmd->destRect;
4097	vmsvgaClipRect(&screenRect, &clipRect);
4098	RT_UNTRUSTED_VALIDATED_FENCE();
4099
4100	uint32_t const width = clipRect.right - clipRect.left;
4101	uint32_t const height = clipRect.bottom - clipRect.top;
4102
4103	if ( width == 0
4104	\|\| height == 0)
4105	break; /* Nothing to do. */
4106
4107	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4108	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4109
4110	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4111	* Prepare parameters for vmsvgaGMRTransfer.
4112	*/
4113	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4114
4115	/* Destination: host buffer which describes the screen 0 VRAM.
4116	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4117	*/
4118	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4119	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4120	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4121	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4122	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4123	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4124	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4125	+ cbScanline * clipRect.top;
4126	int32_t const cbHstPitch = cbScanline;
4127
4128	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4129	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4130	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4131	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4132	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4133
4134	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4135	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4136	gstPtr, offGst, cbGstPitch,
4137	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4138	AssertRC(rc);
4139	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4140	break;
4141	}
4142
4143	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4144	{
4145	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4146	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4147	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4148
4149	/* Note! This can fetch 3d render results as well!! */
4150	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4151	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4152
4153	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4154	RT_UNTRUSTED_VALIDATED_FENCE();
4155
4156	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4157	AssertBreak(pScreen);
4158
4159	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4160	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4161
4162	/* Clip destRect to the screen dimensions. */
4163	SVGASignedRect screenRect;
4164	screenRect.left = 0;
4165	screenRect.top = 0;
4166	screenRect.right = pScreen->cWidth;
4167	screenRect.bottom = pScreen->cHeight;
4168	SVGASignedRect clipRect = pCmd->srcRect;
4169	vmsvgaClipRect(&screenRect, &clipRect);
4170	RT_UNTRUSTED_VALIDATED_FENCE();
4171
4172	uint32_t const width = clipRect.right - clipRect.left;
4173	uint32_t const height = clipRect.bottom - clipRect.top;
4174
4175	if ( width == 0
4176	\|\| height == 0)
4177	break; /* Nothing to do. */
4178
4179	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4180	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4181
4182	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4183	* Prepare parameters for vmsvgaGMRTransfer.
4184	*/
4185	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4186
4187	/* Source: host buffer which describes the screen 0 VRAM.
4188	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4189	*/
4190	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4191	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4192	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4193	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4194	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4195	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4196	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4197	+ cbScanline * clipRect.top;
4198	int32_t const cbHstPitch = cbScanline;
4199
4200	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4201	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4202	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4203	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4204	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4205
4206	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4207	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4208	gstPtr, offGst, cbGstPitch,
4209	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4210	AssertRC(rc);
4211	break;
4212	}
4213
4214	case SVGA_CMD_ANNOTATION_FILL:
4215	{
4216	SVGAFifoCmdAnnotationFill *pCmd;
4217	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4218	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4219
4220	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4221	pSVGAState->colorAnnotation = pCmd->color;
4222	break;
4223	}
4224
4225	case SVGA_CMD_ANNOTATION_COPY:
4226	{
4227	SVGAFifoCmdAnnotationCopy *pCmd;
4228	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4229	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4230
4231	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4232	AssertFailed();
4233	break;
4234	}
4235
4236	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4237
4238	default:
4239	# ifdef VBOX_WITH_VMSVGA3D
4240	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4241	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4242	{
4243	RT_UNTRUSTED_VALIDATED_FENCE();
4244
4245	/* All 3d commands start with a common header, which defines the size of the command. */
4246	SVGA3dCmdHeader *pHdr;
4247	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4248	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4249	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4250	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4251
4252	if (RT_LIKELY(pThis->svga.f3DEnabled))
4253	{ /* likely */ }
4254	else
4255	{
4256	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4257	break;
4258	}
4259
4260	/**
4261	* Check that the 3D command has at least a_cbMin of payload bytes after the
4262	* header. Will break out of the switch if it doesn't.
4263	*/
4264	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4265	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4266	RT_UNTRUSTED_VALIDATED_FENCE(); \
4267	} while (0)
4268	switch ((int)enmCmdId)
4269	{
4270	case SVGA_3D_CMD_SURFACE_DEFINE:
4271	{
4272	uint32_t cMipLevels;
4273	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4274	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4275	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4276
4277	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4278	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4279	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4280	# ifdef DEBUG_GMR_ACCESS
4281	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4282	# endif
4283	break;
4284	}
4285
4286	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4287	{
4288	uint32_t cMipLevels;
4289	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4290	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4291	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4292
4293	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4294	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4295	pCmd->multisampleCount, pCmd->autogenFilter,
4296	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4297	break;
4298	}
4299
4300	case SVGA_3D_CMD_SURFACE_DESTROY:
4301	{
4302	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4303	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4304	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4305	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4306	break;
4307	}
4308
4309	case SVGA_3D_CMD_SURFACE_COPY:
4310	{
4311	uint32_t cCopyBoxes;
4312	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4313	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4314	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4315
4316	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4317	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4318	break;
4319	}
4320
4321	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4322	{
4323	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4324	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4326
4327	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4328	break;
4329	}
4330
4331	case SVGA_3D_CMD_SURFACE_DMA:
4332	{
4333	uint32_t cCopyBoxes;
4334	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4335	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4336	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4337
4338	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4339	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4340	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4341	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4342	break;
4343	}
4344
4345	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4346	{
4347	uint32_t cRects;
4348	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4349	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4350	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4351
4352	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4353	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4354	break;
4355	}
4356
4357	case SVGA_3D_CMD_CONTEXT_DEFINE:
4358	{
4359	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4360	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4361	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4362
4363	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4364	break;
4365	}
4366
4367	case SVGA_3D_CMD_CONTEXT_DESTROY:
4368	{
4369	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4370	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4371	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4372
4373	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4374	break;
4375	}
4376
4377	case SVGA_3D_CMD_SETTRANSFORM:
4378	{
4379	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4380	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4381	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4382
4383	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4384	break;
4385	}
4386
4387	case SVGA_3D_CMD_SETZRANGE:
4388	{
4389	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4390	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4391	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4392
4393	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4394	break;
4395	}
4396
4397	case SVGA_3D_CMD_SETRENDERSTATE:
4398	{
4399	uint32_t cRenderStates;
4400	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4401	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4402	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4403
4404	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4405	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4406	break;
4407	}
4408
4409	case SVGA_3D_CMD_SETRENDERTARGET:
4410	{
4411	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4412	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4413	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4414
4415	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4416	break;
4417	}
4418
4419	case SVGA_3D_CMD_SETTEXTURESTATE:
4420	{
4421	uint32_t cTextureStates;
4422	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4423	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4424	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4425
4426	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4427	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4428	break;
4429	}
4430
4431	case SVGA_3D_CMD_SETMATERIAL:
4432	{
4433	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4434	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4435	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4436
4437	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4438	break;
4439	}
4440
4441	case SVGA_3D_CMD_SETLIGHTDATA:
4442	{
4443	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4444	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4446
4447	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4448	break;
4449	}
4450
4451	case SVGA_3D_CMD_SETLIGHTENABLED:
4452	{
4453	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4454	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4455	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4456
4457	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4458	break;
4459	}
4460
4461	case SVGA_3D_CMD_SETVIEWPORT:
4462	{
4463	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4464	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4465	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4466
4467	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4468	break;
4469	}
4470
4471	case SVGA_3D_CMD_SETCLIPPLANE:
4472	{
4473	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4474	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4475	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4476
4477	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4478	break;
4479	}
4480
4481	case SVGA_3D_CMD_CLEAR:
4482	{
4483	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4484	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4485	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4486
4487	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4488	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4489	break;
4490	}
4491
4492	case SVGA_3D_CMD_PRESENT:
4493	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4494	{
4495	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4496	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4497	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4498	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4499	else
4500	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4501
4502	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4503
4504	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4505	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4506	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4507	break;
4508	}
4509
4510	case SVGA_3D_CMD_SHADER_DEFINE:
4511	{
4512	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4513	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4514	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4515
4516	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4517	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4518	break;
4519	}
4520
4521	case SVGA_3D_CMD_SHADER_DESTROY:
4522	{
4523	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4524	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4525	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4526
4527	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4528	break;
4529	}
4530
4531	case SVGA_3D_CMD_SET_SHADER:
4532	{
4533	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4534	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4535	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4536
4537	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4538	break;
4539	}
4540
4541	case SVGA_3D_CMD_SET_SHADER_CONST:
4542	{
4543	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4544	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4545	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4546
4547	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4548	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4549	break;
4550	}
4551
4552	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4553	{
4554	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4555	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4556	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4557
4558	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4559	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4560	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4561	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4562	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4563
4564	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4565	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4566
4567	RT_UNTRUSTED_VALIDATED_FENCE();
4568
4569	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4570	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4571	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4572
4573	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4574	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4575	pNumRange, cVertexDivisor, pVertexDivisor);
4576	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4577	break;
4578	}
4579
4580	case SVGA_3D_CMD_SETSCISSORRECT:
4581	{
4582	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4583	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4584	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4585
4586	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4587	break;
4588	}
4589
4590	case SVGA_3D_CMD_BEGIN_QUERY:
4591	{
4592	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4593	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4594	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4595
4596	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4597	break;
4598	}
4599
4600	case SVGA_3D_CMD_END_QUERY:
4601	{
4602	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4603	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4604	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4605
4606	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4607	break;
4608	}
4609
4610	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4611	{
4612	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4613	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4614	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4615
4616	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4617	break;
4618	}
4619
4620	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4621	{
4622	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4623	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4624	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4625
4626	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4627	break;
4628	}
4629
4630	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4631	/* context id + surface id? */
4632	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4633	break;
4634	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4635	/* context id + surface id? */
4636	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4637	break;
4638
4639	default:
4640	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4641	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4642	break;
4643	}
4644	}
4645	else
4646	# endif // VBOX_WITH_VMSVGA3D
4647	{
4648	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4649	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4650	}
4651	}
4652
4653	/* Go to the next slot */
4654	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4655	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4656	if (offCurrentCmd >= offFifoMax)
4657	{
4658	offCurrentCmd -= offFifoMax - offFifoMin;
4659	Assert(offCurrentCmd >= offFifoMin);
4660	Assert(offCurrentCmd < offFifoMax);
4661	}
4662	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4663	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4664
4665	/*
4666	* Raise IRQ if required. Must enter the critical section here
4667	* before making final decisions here, otherwise cubebench and
4668	* others may end up waiting forever.
4669	*/
4670	if ( u32IrqStatus
4671	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4672	{
4673	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4674	AssertRC(rc2);
4675
4676	/* FIFO progress might trigger an interrupt. */
4677	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4678	{
4679	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4680	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4681	}
4682
4683	/* Unmasked IRQ pending? */
4684	if (pThis->svga.u32IrqMask & u32IrqStatus)
4685	{
4686	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4687	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4688	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4689	}
4690
4691	PDMCritSectLeave(&pThis->CritSect);
4692	}
4693	}
4694
4695	/* If really done, clear the busy flag. */
4696	if (fDone)
4697	{
4698	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4699	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4700	}
4701	}
4702
4703	/*
4704	* Free the bounce buffer. (There are no returns above!)
4705	*/
4706	RTMemFree(pbBounceBuf);
4707
4708	return VINF_SUCCESS;
4709	}
4710
4711	/**
4712	* Free the specified GMR
4713	*
4714	* @param pThis VGA device instance data.
4715	* @param idGMR GMR id
4716	*/
4717	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4718	{
4719	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4720
4721	/* Free the old descriptor if present. */
4722	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4723	if ( pGMR->numDescriptors
4724	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4725	{
4726	# ifdef DEBUG_GMR_ACCESS
4727	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4728	# endif
4729
4730	Assert(pGMR->paDesc);
4731	RTMemFree(pGMR->paDesc);
4732	pGMR->paDesc = NULL;
4733	pGMR->numDescriptors = 0;
4734	pGMR->cbTotal = 0;
4735	pGMR->cMaxPages = 0;
4736	}
4737	Assert(!pGMR->cMaxPages);
4738	Assert(!pGMR->cbTotal);
4739	}
4740
4741	/**
4742	* Copy between a GMR and a host memory buffer.
4743	*
4744	* @returns VBox status code.
4745	* @param pThis VGA device instance data.
4746	* @param enmTransferType Transfer type (read/write)
4747	* @param pbHstBuf Host buffer pointer (valid)
4748	* @param cbHstBuf Size of host buffer (valid)
4749	* @param offHst Host buffer offset of the first scanline
4750	* @param cbHstPitch Destination buffer pitch
4751	* @param gstPtr GMR description
4752	* @param offGst Guest buffer offset of the first scanline
4753	* @param cbGstPitch Guest buffer pitch
4754	* @param cbWidth Width in bytes to copy
4755	* @param cHeight Number of scanllines to copy
4756	*/
4757	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4758	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4759	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4760	uint32_t cbWidth, uint32_t cHeight)
4761	{
4762	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4763	int rc;
4764
4765	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4766	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4767	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4768	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4769	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4770
4771	PGMR pGMR;
4772	uint32_t cbGmr; /* The GMR size in bytes. */
4773	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4774	{
4775	pGMR = NULL;
4776	cbGmr = pThis->vram_size;
4777	}
4778	else
4779	{
4780	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4781	RT_UNTRUSTED_VALIDATED_FENCE();
4782	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4783	cbGmr = pGMR->cbTotal;
4784	}
4785
4786	/*
4787	* GMR
4788	*/
4789	/* Calculate GMR offset of the data to be copied. */
4790	AssertMsgReturn(gstPtr.offset < cbGmr,
4791	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4792	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4793	VERR_INVALID_PARAMETER);
4794	RT_UNTRUSTED_VALIDATED_FENCE();
4795	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4796	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4797	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4798	VERR_INVALID_PARAMETER);
4799	RT_UNTRUSTED_VALIDATED_FENCE();
4800	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4801
4802	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4803	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4804	AssertMsgReturn(cbGmrScanline != 0,
4805	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4806	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4807	VERR_INVALID_PARAMETER);
4808	RT_UNTRUSTED_VALIDATED_FENCE();
4809	AssertMsgReturn(cbWidth <= cbGmrScanline,
4810	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4811	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4812	VERR_INVALID_PARAMETER);
4813	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4814	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4815	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4816	VERR_INVALID_PARAMETER);
4817	RT_UNTRUSTED_VALIDATED_FENCE();
4818
4819	/* How many bytes are available for the data in the GMR. */
4820	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4821
4822	/* How many scanlines would fit into the available data. */
4823	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4824	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4825	if (cbWidth <= cbGmrLastScanline)
4826	++cGmrScanlines;
4827
4828	if (cHeight > cGmrScanlines)
4829	cHeight = cGmrScanlines;
4830
4831	AssertMsgReturn(cHeight > 0,
4832	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4833	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4834	VERR_INVALID_PARAMETER);
4835	RT_UNTRUSTED_VALIDATED_FENCE();
4836
4837	/*
4838	* Host buffer.
4839	*/
4840	AssertMsgReturn(offHst < cbHstBuf,
4841	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4842	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4843	VERR_INVALID_PARAMETER);
4844
4845	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4846	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4847	AssertMsgReturn(cbHstScanline != 0,
4848	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4849	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4850	VERR_INVALID_PARAMETER);
4851	AssertMsgReturn(cbWidth <= cbHstScanline,
4852	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4853	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4854	VERR_INVALID_PARAMETER);
4855	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4856	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4857	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4858	VERR_INVALID_PARAMETER);
4859
4860	/* How many bytes are available for the data in the buffer. */
4861	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4862
4863	/* How many scanlines would fit into the available data. */
4864	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4865	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4866	if (cbWidth <= cbHstLastScanline)
4867	++cHstScanlines;
4868
4869	if (cHeight > cHstScanlines)
4870	cHeight = cHstScanlines;
4871
4872	AssertMsgReturn(cHeight > 0,
4873	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4874	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4875	VERR_INVALID_PARAMETER);
4876
4877	uint8_t *pbHst = pbHstBuf + offHst;
4878
4879	/* Shortcut for the framebuffer. */
4880	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4881	{
4882	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4883
4884	uint8_t const *pbSrc;
4885	int32_t cbSrcPitch;
4886	uint8_t *pbDst;
4887	int32_t cbDstPitch;
4888
4889	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4890	{
4891	pbSrc = pbHst;
4892	cbSrcPitch = cbHstPitch;
4893	pbDst = pbGst;
4894	cbDstPitch = cbGstPitch;
4895	}
4896	else
4897	{
4898	pbSrc = pbGst;
4899	cbSrcPitch = cbGstPitch;
4900	pbDst = pbHst;
4901	cbDstPitch = cbHstPitch;
4902	}
4903
4904	if ( cbWidth == (uint32_t)cbGstPitch
4905	&& cbGstPitch == cbHstPitch)
4906	{
4907	/* Entire scanlines, positive pitch. */
4908	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4909	}
4910	else
4911	{
4912	for (uint32_t i = 0; i < cHeight; ++i)
4913	{
4914	memcpy(pbDst, pbSrc, cbWidth);
4915
4916	pbDst += cbDstPitch;
4917	pbSrc += cbSrcPitch;
4918	}
4919	}
4920	return VINF_SUCCESS;
4921	}
4922
4923	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4924	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4925
4926	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4927	uint32_t iDesc = 0; /* Index in the descriptor array. */
4928	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4929	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4930	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4931	for (uint32_t i = 0; i < cHeight; ++i)
4932	{
4933	uint32_t cbCurrentWidth = cbWidth;
4934	uint32_t offGmrCurrent = offGmrScanline;
4935	uint8_t *pbCurrentHost = pbHstScanline;
4936
4937	/* Find the right descriptor */
4938	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4939	{
4940	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4941	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4942	++iDesc;
4943	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4944	}
4945
4946	while (cbCurrentWidth)
4947	{
4948	uint32_t cbToCopy;
4949
4950	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4951	{
4952	cbToCopy = cbCurrentWidth;
4953	}
4954	else
4955	{
4956	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
4957	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4958	}
4959
4960	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
4961
4962	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
4963
4964	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4965	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4966	else
4967	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4968	AssertRCBreak(rc);
4969
4970	cbCurrentWidth -= cbToCopy;
4971	offGmrCurrent += cbToCopy;
4972	pbCurrentHost += cbToCopy;
4973
4974	/* Go to the next descriptor if there's anything left. */
4975	if (cbCurrentWidth)
4976	{
4977	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4978	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
4979	++iDesc;
4980	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4981	}
4982	}
4983
4984	offGmrScanline += cbGstPitch;
4985	pbHstScanline += cbHstPitch;
4986	}
4987
4988	return VINF_SUCCESS;
4989	}
4990
4991
4992	/**
4993	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
4994	*
4995	* @param pSizeSrc Source surface dimensions.
4996	* @param pSizeDest Destination surface dimensions.
4997	* @param pBox Coordinates to be clipped.
4998	*/
4999	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5000	const SVGA3dSize *pSizeDest,
5001	SVGA3dCopyBox *pBox)
5002	{
5003	/* Src x, w */
5004	if (pBox->srcx > pSizeSrc->width)
5005	pBox->srcx = pSizeSrc->width;
5006	if (pBox->w > pSizeSrc->width - pBox->srcx)
5007	pBox->w = pSizeSrc->width - pBox->srcx;
5008
5009	/* Src y, h */
5010	if (pBox->srcy > pSizeSrc->height)
5011	pBox->srcy = pSizeSrc->height;
5012	if (pBox->h > pSizeSrc->height - pBox->srcy)
5013	pBox->h = pSizeSrc->height - pBox->srcy;
5014
5015	/* Src z, d */
5016	if (pBox->srcz > pSizeSrc->depth)
5017	pBox->srcz = pSizeSrc->depth;
5018	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5019	pBox->d = pSizeSrc->depth - pBox->srcz;
5020
5021	/* Dest x, w */
5022	if (pBox->x > pSizeDest->width)
5023	pBox->x = pSizeDest->width;
5024	if (pBox->w > pSizeDest->width - pBox->x)
5025	pBox->w = pSizeDest->width - pBox->x;
5026
5027	/* Dest y, h */
5028	if (pBox->y > pSizeDest->height)
5029	pBox->y = pSizeDest->height;
5030	if (pBox->h > pSizeDest->height - pBox->y)
5031	pBox->h = pSizeDest->height - pBox->y;
5032
5033	/* Dest z, d */
5034	if (pBox->z > pSizeDest->depth)
5035	pBox->z = pSizeDest->depth;
5036	if (pBox->d > pSizeDest->depth - pBox->z)
5037	pBox->d = pSizeDest->depth - pBox->z;
5038	}
5039
5040	/**
5041	* Unsigned coordinates in pBox. Clip to [0; pSize).
5042	*
5043	* @param pSize Source surface dimensions.
5044	* @param pBox Coordinates to be clipped.
5045	*/
5046	void vmsvgaClipBox(const SVGA3dSize *pSize,
5047	SVGA3dBox *pBox)
5048	{
5049	/* x, w */
5050	if (pBox->x > pSize->width)
5051	pBox->x = pSize->width;
5052	if (pBox->w > pSize->width - pBox->x)
5053	pBox->w = pSize->width - pBox->x;
5054
5055	/* y, h */
5056	if (pBox->y > pSize->height)
5057	pBox->y = pSize->height;
5058	if (pBox->h > pSize->height - pBox->y)
5059	pBox->h = pSize->height - pBox->y;
5060
5061	/* z, d */
5062	if (pBox->z > pSize->depth)
5063	pBox->z = pSize->depth;
5064	if (pBox->d > pSize->depth - pBox->z)
5065	pBox->d = pSize->depth - pBox->z;
5066	}
5067
5068	/**
5069	* Clip.
5070	*
5071	* @param pBound Bounding rectangle.
5072	* @param pRect Rectangle to be clipped.
5073	*/
5074	void vmsvgaClipRect(SVGASignedRect const *pBound,
5075	SVGASignedRect *pRect)
5076	{
5077	int32_t left;
5078	int32_t top;
5079	int32_t right;
5080	int32_t bottom;
5081
5082	/* Right order. */
5083	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5084	if (pRect->left < pRect->right)
5085	{
5086	left = pRect->left;
5087	right = pRect->right;
5088	}
5089	else
5090	{
5091	left = pRect->right;
5092	right = pRect->left;
5093	}
5094	if (pRect->top < pRect->bottom)
5095	{
5096	top = pRect->top;
5097	bottom = pRect->bottom;
5098	}
5099	else
5100	{
5101	top = pRect->bottom;
5102	bottom = pRect->top;
5103	}
5104
5105	if (left < pBound->left)
5106	left = pBound->left;
5107	if (right < pBound->left)
5108	right = pBound->left;
5109
5110	if (left > pBound->right)
5111	left = pBound->right;
5112	if (right > pBound->right)
5113	right = pBound->right;
5114
5115	if (top < pBound->top)
5116	top = pBound->top;
5117	if (bottom < pBound->top)
5118	bottom = pBound->top;
5119
5120	if (top > pBound->bottom)
5121	top = pBound->bottom;
5122	if (bottom > pBound->bottom)
5123	bottom = pBound->bottom;
5124
5125	pRect->left = left;
5126	pRect->right = right;
5127	pRect->top = top;
5128	pRect->bottom = bottom;
5129	}
5130
5131	/**
5132	* Unblock the FIFO I/O thread so it can respond to a state change.
5133	*
5134	* @returns VBox status code.
5135	* @param pDevIns The VGA device instance.
5136	* @param pThread The send thread.
5137	*/
5138	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5139	{
5140	RT_NOREF(pDevIns);
5141	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5142	Log(("vmsvgaFIFOLoopWakeUp\n"));
5143	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5144	}
5145
5146	/**
5147	* Enables or disables dirty page tracking for the framebuffer
5148	*
5149	* @param pThis VGA device instance data.
5150	* @param fTraces Enable/disable traces
5151	*/
5152	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5153	{
5154	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5155	&& !fTraces)
5156	{
5157	//Assert(pThis->svga.fTraces);
5158	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5159	return;
5160	}
5161
5162	pThis->svga.fTraces = fTraces;
5163	if (pThis->svga.fTraces)
5164	{
5165	unsigned cbFrameBuffer = pThis->vram_size;
5166
5167	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5168	/** @todo How does this work with screens? */
5169	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5170	{
5171	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5172	Assert(pThis->svga.cbScanline);
5173	#endif
5174	/* Hardware enabled; return real framebuffer size .*/
5175	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5176	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5177	}
5178
5179	if (!pThis->svga.fVRAMTracking)
5180	{
5181	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5182	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5183	pThis->svga.fVRAMTracking = true;
5184	}
5185	}
5186	else
5187	{
5188	if (pThis->svga.fVRAMTracking)
5189	{
5190	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5191	vgaR3UnregisterVRAMHandler(pThis);
5192	pThis->svga.fVRAMTracking = false;
5193	}
5194	}
5195	}
5196
5197	/**
5198	* @callback_method_impl{FNPCIIOREGIONMAP}
5199	*/
5200	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5201	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5202	{
5203	int rc;
5204	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5205
5206	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5207	if (enmType == PCI_ADDRESS_SPACE_IO)
5208	{
5209	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5210	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5211	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5212	if (RT_FAILURE(rc))
5213	return rc;
5214	if (pThis->fR0Enabled)
5215	{
5216	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5217	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5218	if (RT_FAILURE(rc))
5219	return rc;
5220	}
5221	if (pThis->fGCEnabled)
5222	{
5223	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5224	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5225	if (RT_FAILURE(rc))
5226	return rc;
5227	}
5228
5229	pThis->svga.BasePort = GCPhysAddress;
5230	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5231	}
5232	else
5233	{
5234	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5235	if (GCPhysAddress != NIL_RTGCPHYS)
5236	{
5237	/*
5238	* Mapping the FIFO RAM.
5239	*/
5240	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5241	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5242	AssertRC(rc);
5243
5244	if (RT_SUCCESS(rc))
5245	{
5246	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5247	# ifdef DEBUG_FIFO_ACCESS
5248	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5249	# else
5250	GCPhysAddress + PAGE_SIZE - 1,
5251	# endif
5252	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5253	"VMSVGA FIFO");
5254	AssertRC(rc);
5255	}
5256	if (RT_SUCCESS(rc))
5257	{
5258	pThis->svga.GCPhysFIFO = GCPhysAddress;
5259	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5260	}
5261	}
5262	else
5263	{
5264	Assert(pThis->svga.GCPhysFIFO);
5265	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5266	AssertRC(rc);
5267	pThis->svga.GCPhysFIFO = 0;
5268	}
5269	}
5270	return VINF_SUCCESS;
5271	}
5272
5273	# ifdef VBOX_WITH_VMSVGA3D
5274
5275	/**
5276	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5277	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5278	*
5279	* @param pThis The VGA device instance data.
5280	* @param sid Either UINT32_MAX or the ID of a specific
5281	* surface. If UINT32_MAX is used, all surfaces
5282	* are processed.
5283	*/
5284	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5285	{
5286	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5287	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5288	}
5289
5290
5291	/**
5292	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5293	*/
5294	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5295	{
5296	/* There might be a specific surface ID at the start of the
5297	arguments, if not show all surfaces. */
5298	uint32_t sid = UINT32_MAX;
5299	if (pszArgs)
5300	pszArgs = RTStrStripL(pszArgs);
5301	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5302	sid = RTStrToUInt32(pszArgs);
5303
5304	/* Verbose or terse display, we default to verbose. */
5305	bool fVerbose = true;
5306	if (RTStrIStr(pszArgs, "terse"))
5307	fVerbose = false;
5308
5309	/* The size of the ascii art (x direction, y is 3/4 of x). */
5310	uint32_t cxAscii = 80;
5311	if (RTStrIStr(pszArgs, "gigantic"))
5312	cxAscii = 300;
5313	else if (RTStrIStr(pszArgs, "huge"))
5314	cxAscii = 180;
5315	else if (RTStrIStr(pszArgs, "big"))
5316	cxAscii = 132;
5317	else if (RTStrIStr(pszArgs, "normal"))
5318	cxAscii = 80;
5319	else if (RTStrIStr(pszArgs, "medium"))
5320	cxAscii = 64;
5321	else if (RTStrIStr(pszArgs, "small"))
5322	cxAscii = 48;
5323	else if (RTStrIStr(pszArgs, "tiny"))
5324	cxAscii = 24;
5325
5326	/* Y invert the image when producing the ASCII art. */
5327	bool fInvY = false;
5328	if (RTStrIStr(pszArgs, "invy"))
5329	fInvY = true;
5330
5331	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5332	}
5333
5334
5335	/**
5336	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5337	*/
5338	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5339	{
5340	/* pszArg = "sid[>dir]"
5341	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5342	*/
5343	char *pszBitmapPath = NULL;
5344	uint32_t sid = UINT32_MAX;
5345	if (pszArgs)
5346	pszArgs = RTStrStripL(pszArgs);
5347	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5348	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5349	if ( pszBitmapPath
5350	&& *pszBitmapPath == '>')
5351	++pszBitmapPath;
5352
5353	const bool fVerbose = true;
5354	const uint32_t cxAscii = 0; /* No ASCII */
5355	const bool fInvY = false; /* Do not invert. */
5356	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5357	}
5358
5359
5360	/**
5361	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5362	*/
5363	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5364	{
5365	/* There might be a specific surface ID at the start of the
5366	arguments, if not show all contexts. */
5367	uint32_t sid = UINT32_MAX;
5368	if (pszArgs)
5369	pszArgs = RTStrStripL(pszArgs);
5370	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5371	sid = RTStrToUInt32(pszArgs);
5372
5373	/* Verbose or terse display, we default to verbose. */
5374	bool fVerbose = true;
5375	if (RTStrIStr(pszArgs, "terse"))
5376	fVerbose = false;
5377
5378	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5379	}
5380
5381	# endif /* VBOX_WITH_VMSVGA3D */
5382
5383	/**
5384	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5385	*/
5386	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5387	{
5388	RT_NOREF(pszArgs);
5389	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5390	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5391
5392	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5393	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5394	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5395	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5396	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5397	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5398	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5399	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5400	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5401	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5402	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5403	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5404	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
5405	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5406	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5407	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5408	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5409	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5410	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5411	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5412	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5413	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5414
5415	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5416	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5417	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5418	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5419
5420	# ifdef VBOX_WITH_VMSVGA3D
5421	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5422	# endif
5423	}
5424
5425	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5426	*/
5427	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5428	{
5429	RT_NOREF(uPass);
5430
5431	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5432	int rc;
5433
5434	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5435	{
5436	uint32_t cScreens = 0;
5437	rc = SSMR3GetU32(pSSM, &cScreens);
5438	AssertRCReturn(rc, rc);
5439	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5440	("cScreens=%#x\n", cScreens),
5441	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5442
5443	for (uint32_t i = 0; i < cScreens; ++i)
5444	{
5445	VMSVGASCREENOBJECT screen;
5446	RT_ZERO(screen);
5447
5448	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5449	AssertLogRelRCReturn(rc, rc);
5450
5451	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5452	{
5453	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5454	*pScreen = screen;
5455	pScreen->fModified = true;
5456	}
5457	else
5458	{
5459	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5460	}
5461	}
5462	}
5463	else
5464	{
5465	/* Try to setup at least the first screen. */
5466	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5467	pScreen->fDefined = true;
5468	pScreen->fModified = true;
5469	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5470	pScreen->idScreen = 0;
5471	pScreen->xOrigin = 0;
5472	pScreen->yOrigin = 0;
5473	pScreen->offVRAM = pThis->svga.uScreenOffset;
5474	pScreen->cbPitch = pThis->svga.cbScanline;
5475	pScreen->cWidth = pThis->svga.uWidth;
5476	pScreen->cHeight = pThis->svga.uHeight;
5477	pScreen->cBpp = pThis->svga.uBpp;
5478	}
5479
5480	return VINF_SUCCESS;
5481	}
5482
5483	/**
5484	* @copydoc FNSSMDEVLOADEXEC
5485	*/
5486	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5487	{
5488	RT_NOREF(uPass);
5489	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5490	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5491	int rc;
5492
5493	/* Load our part of the VGAState */
5494	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5495	AssertRCReturn(rc, rc);
5496
5497	/* Load the VGA framebuffer. */
5498	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5499	uint32_t cbVgaFramebuffer = _32K;
5500	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5501	{
5502	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5503	AssertRCReturn(rc, rc);
5504	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5505	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5506	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5507	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5508	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5509	}
5510	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5511	AssertRCReturn(rc, rc);
5512	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5513	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5514	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5515	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5516
5517	/* Load the VMSVGA state. */
5518	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5519	AssertRCReturn(rc, rc);
5520
5521	/* Load the active cursor bitmaps. */
5522	if (pSVGAState->Cursor.fActive)
5523	{
5524	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5525	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5526
5527	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5528	AssertRCReturn(rc, rc);
5529	}
5530
5531	/* Load the GMR state. */
5532	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5533	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5534	{
5535	rc = SSMR3GetU32(pSSM, &cGMR);
5536	AssertRCReturn(rc, rc);
5537	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5538	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5539	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5540	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5541	}
5542
5543	if (pThis->svga.cGMR != cGMR)
5544	{
5545	/* Reallocate GMR array. */
5546	Assert(pSVGAState->paGMR != NULL);
5547	RTMemFree(pSVGAState->paGMR);
5548	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5549	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5550	pThis->svga.cGMR = cGMR;
5551	}
5552
5553	for (uint32_t i = 0; i < cGMR; ++i)
5554	{
5555	PGMR pGMR = &pSVGAState->paGMR[i];
5556
5557	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5558	AssertRCReturn(rc, rc);
5559
5560	if (pGMR->numDescriptors)
5561	{
5562	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5563	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5564	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5565
5566	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5567	{
5568	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5569	AssertRCReturn(rc, rc);
5570	}
5571	}
5572	}
5573
5574	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5575	vmsvga3dPowerOn(pThis);
5576	# endif
5577
5578	VMSVGA_STATE_LOAD LoadState;
5579	LoadState.pSSM = pSSM;
5580	LoadState.uVersion = uVersion;
5581	LoadState.uPass = uPass;
5582	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5583	AssertLogRelRCReturn(rc, rc);
5584
5585	return VINF_SUCCESS;
5586	}
5587
5588	/**
5589	* Reinit the video mode after the state has been loaded.
5590	*/
5591	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5592	{
5593	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5594	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5595
5596	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5597
5598	/* Set the active cursor. */
5599	if (pSVGAState->Cursor.fActive)
5600	{
5601	int rc;
5602
5603	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5604	true,
5605	true,
5606	pSVGAState->Cursor.xHotspot,
5607	pSVGAState->Cursor.yHotspot,
5608	pSVGAState->Cursor.width,
5609	pSVGAState->Cursor.height,
5610	pSVGAState->Cursor.pData);
5611	AssertRC(rc);
5612	}
5613	return VINF_SUCCESS;
5614	}
5615
5616	/**
5617	* Portion of SVGA state which must be saved in the FIFO thread.
5618	*/
5619	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5620	{
5621	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5622	int rc;
5623
5624	/* Save the screen objects. */
5625	/* Count defined screen object. */
5626	uint32_t cScreens = 0;
5627	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5628	{
5629	if (pSVGAState->aScreens[i].fDefined)
5630	++cScreens;
5631	}
5632
5633	rc = SSMR3PutU32(pSSM, cScreens);
5634	AssertLogRelRCReturn(rc, rc);
5635
5636	for (uint32_t i = 0; i < cScreens; ++i)
5637	{
5638	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5639
5640	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5641	AssertLogRelRCReturn(rc, rc);
5642	}
5643	return VINF_SUCCESS;
5644	}
5645
5646	/**
5647	* @copydoc FNSSMDEVSAVEEXEC
5648	*/
5649	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5650	{
5651	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5652	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5653	int rc;
5654
5655	/* Save our part of the VGAState */
5656	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5657	AssertLogRelRCReturn(rc, rc);
5658
5659	/* Save the framebuffer backup. */
5660	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5661	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5662	AssertLogRelRCReturn(rc, rc);
5663
5664	/* Save the VMSVGA state. */
5665	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5666	AssertLogRelRCReturn(rc, rc);
5667
5668	/* Save the active cursor bitmaps. */
5669	if (pSVGAState->Cursor.fActive)
5670	{
5671	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5672	AssertLogRelRCReturn(rc, rc);
5673	}
5674
5675	/* Save the GMR state */
5676	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5677	AssertLogRelRCReturn(rc, rc);
5678	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5679	{
5680	PGMR pGMR = &pSVGAState->paGMR[i];
5681
5682	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5683	AssertLogRelRCReturn(rc, rc);
5684
5685	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5686	{
5687	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5688	AssertLogRelRCReturn(rc, rc);
5689	}
5690	}
5691
5692	/*
5693	* Must save some state (3D in particular) in the FIFO thread.
5694	*/
5695	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5696	AssertLogRelRCReturn(rc, rc);
5697
5698	return VINF_SUCCESS;
5699	}
5700
5701	/**
5702	* Destructor for PVMSVGAR3STATE structure.
5703	*
5704	* @param pThis The VGA instance.
5705	* @param pSVGAState Pointer to the structure. It is not deallocated.
5706	*/
5707	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5708	{
5709	#ifndef VMSVGA_USE_EMT_HALT_CODE
5710	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5711	{
5712	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5713	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5714	}
5715	#endif
5716
5717	if (pSVGAState->Cursor.fActive)
5718	{
5719	RTMemFree(pSVGAState->Cursor.pData);
5720	pSVGAState->Cursor.pData = NULL;
5721	pSVGAState->Cursor.fActive = false;
5722	}
5723
5724	if (pSVGAState->paGMR)
5725	{
5726	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5727	if (pSVGAState->paGMR[i].paDesc)
5728	RTMemFree(pSVGAState->paGMR[i].paDesc);
5729
5730	RTMemFree(pSVGAState->paGMR);
5731	pSVGAState->paGMR = NULL;
5732	}
5733	}
5734
5735	/**
5736	* Constructor for PVMSVGAR3STATE structure.
5737	*
5738	* @returns VBox status code.
5739	* @param pThis The VGA instance.
5740	* @param pSVGAState Pointer to the structure. It is already allocated.
5741	*/
5742	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5743	{
5744	int rc = VINF_SUCCESS;
5745	RT_ZERO(*pSVGAState);
5746
5747	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5748	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5749
5750	#ifndef VMSVGA_USE_EMT_HALT_CODE
5751	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5752	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5753	AssertRCReturn(rc, rc);
5754	#endif
5755
5756	return rc;
5757	}
5758
5759	/**
5760	* Resets the SVGA hardware state
5761	*
5762	* @returns VBox status code.
5763	* @param pDevIns The device instance.
5764	*/
5765	int vmsvgaReset(PPDMDEVINS pDevIns)
5766	{
5767	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5768	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5769
5770	/* Reset before init? */
5771	if (!pSVGAState)
5772	return VINF_SUCCESS;
5773
5774	Log(("vmsvgaReset\n"));
5775
5776	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5777	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5778	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5779
5780	/* Reset other stuff. */
5781	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5782	RT_ZERO(pThis->svga.au32ScratchRegion);
5783
5784	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5785	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5786
5787	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5788
5789	/* Register caps. */
5790	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5791	# ifdef VBOX_WITH_VMSVGA3D
5792	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5793	# endif
5794
5795	/* Setup FIFO capabilities. */
5796	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5797
5798	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5799	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5800
5801	/* VRAM tracking is enabled by default during bootup. */
5802	pThis->svga.fVRAMTracking = true;
5803	pThis->svga.fEnabled = false;
5804
5805	/* Invalidate current settings. */
5806	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5807	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5808	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5809	pThis->svga.cbScanline = 0;
5810
5811	return rc;
5812	}
5813
5814	/**
5815	* Cleans up the SVGA hardware state
5816	*
5817	* @returns VBox status code.
5818	* @param pDevIns The device instance.
5819	*/
5820	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5821	{
5822	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5823
5824	/*
5825	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5826	*/
5827	if (pThis->svga.pFIFOIOThread)
5828	{
5829	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5830	AssertLogRelRC(rc);
5831
5832	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5833	AssertLogRelRC(rc);
5834	pThis->svga.pFIFOIOThread = NULL;
5835	}
5836
5837	/*
5838	* Destroy the special SVGA state.
5839	*/
5840	if (pThis->svga.pSvgaR3State)
5841	{
5842	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5843
5844	RTMemFree(pThis->svga.pSvgaR3State);
5845	pThis->svga.pSvgaR3State = NULL;
5846	}
5847
5848	/*
5849	* Free our resources residing in the VGA state.
5850	*/
5851	if (pThis->svga.pbVgaFrameBufferR3)
5852	{
5853	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5854	pThis->svga.pbVgaFrameBufferR3 = NULL;
5855	}
5856	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5857	{
5858	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5859	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5860	}
5861	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5862	{
5863	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5864	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5865	}
5866
5867	return VINF_SUCCESS;
5868	}
5869
5870	/**
5871	* Initialize the SVGA hardware state
5872	*
5873	* @returns VBox status code.
5874	* @param pDevIns The device instance.
5875	*/
5876	int vmsvgaInit(PPDMDEVINS pDevIns)
5877	{
5878	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5879	PVMSVGAR3STATE pSVGAState;
5880	PVM pVM = PDMDevHlpGetVM(pDevIns);
5881	int rc;
5882
5883	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5884	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5885
5886	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5887
5888	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5889	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5890	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5891
5892	/* Create event semaphore. */
5893	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5894
5895	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5896	if (RT_FAILURE(rc))
5897	{
5898	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5899	return rc;
5900	}
5901
5902	/* Create event semaphore. */
5903	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5904	if (RT_FAILURE(rc))
5905	{
5906	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5907	return rc;
5908	}
5909
5910	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5911	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5912
5913	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5914	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5915
5916	pSVGAState = pThis->svga.pSvgaR3State;
5917
5918	/* Register caps. */
5919	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5920	# ifdef VBOX_WITH_VMSVGA3D
5921	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5922	# endif
5923
5924	/* Setup FIFO capabilities. */
5925	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5926
5927	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5928	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5929
5930	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5931	# ifdef VBOX_WITH_VMSVGA3D
5932	if (pThis->svga.f3DEnabled)
5933	{
5934	rc = vmsvga3dInit(pThis);
5935	if (RT_FAILURE(rc))
5936	{
5937	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5938	pThis->svga.f3DEnabled = false;
5939	}
5940	}
5941	# endif
5942	/* VRAM tracking is enabled by default during bootup. */
5943	pThis->svga.fVRAMTracking = true;
5944
5945	/* Invalidate current settings. */
5946	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5947	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5948	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5949	pThis->svga.cbScanline = 0;
5950
5951	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5952	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5953	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5954	{
5955	pThis->svga.u32MaxWidth -= 256;
5956	pThis->svga.u32MaxHeight -= 256;
5957	}
5958	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5959
5960	# ifdef DEBUG_GMR_ACCESS
5961	/* Register the GMR access handler type. */
5962	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5963	vmsvgaR3GMRAccessHandler,
5964	NULL, NULL, NULL,
5965	NULL, NULL, NULL,
5966	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5967	AssertRCReturn(rc, rc);
5968	# endif
5969
5970	/* Register the FIFO access handler type. In addition to
5971	debugging FIFO access, this is also used to facilitate
5972	extended fifo thread sleeps. */
5973	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
5974	# ifdef DEBUG_FIFO_ACCESS
5975	PGMPHYSHANDLERKIND_ALL,
5976	# else
5977	PGMPHYSHANDLERKIND_WRITE,
5978	# endif
5979	vmsvgaR3FIFOAccessHandler,
5980	NULL, NULL, NULL,
5981	NULL, NULL, NULL,
5982	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5983	AssertRCReturn(rc, rc);
5984
5985	/* Create the async IO thread. */
5986	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5987	RTTHREADTYPE_IO, "VMSVGA FIFO");
5988	if (RT_FAILURE(rc))
5989	{
5990	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5991	return rc;
5992	}
5993
5994	/*
5995	* Statistics.
5996	*/
5997	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5998	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5999	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6000	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6001	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6002	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6003	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6004	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6005	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6006	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6007	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6008	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6009	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6010	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6011	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6012	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6013	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6014	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6015	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6016	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6017	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6018	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6019	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6020	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6021	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6022	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6023	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6024	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6025	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6026	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6027	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6028	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6029	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6030	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6031	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6032	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6033	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6034	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6035	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6036	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6037	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6038	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6039	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6040	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6041	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6042	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6043	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6044	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6045	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6046	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6047	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6048	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6049	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6050	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6051	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6052	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6053
6054	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6055	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6056	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6057	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6058	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6059	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6060	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6061	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6062	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6063	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6064	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6065	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6066	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6067	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6068	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6069	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6070	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6071	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6072	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6073	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6074	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6075	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6076	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6077	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6078	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6079	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6080	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6081	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6082	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6083	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6084	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6085	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6086
6087	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6088	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6089	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6090	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6091	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6092	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6093	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6094	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6095	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6096	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6097	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6098	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6099	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6100	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6101	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6102	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6103	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6104	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6105	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6106	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6107	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6108	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6109	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6110	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6111	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6112	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6113	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6114	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6115	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6116	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6117	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6118	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6119	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6120	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6121	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6122	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6123	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6124	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6125	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6126	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6127	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6128	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6129	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6130	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6131	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6132	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6133	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6134	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6135	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6136
6137	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6138	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6139	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6140	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6141	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6142	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6143	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6144	STAM_REL_REG(pVM, &pSVGAState->StatFifoSleepOnHandler, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoSleepOnHandler", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the access handler.");
6145	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6146	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6147	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6148	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6149	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6150
6151	/*
6152	* Info handlers.
6153	*/
6154	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6155	# ifdef VBOX_WITH_VMSVGA3D
6156	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6157	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6158	"VMSVGA 3d surface details. "
6159	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6160	vmsvgaR3Info3dSurface);
6161	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6162	"VMSVGA 3d surface details and bitmap: "
6163	"sid[>dir]",
6164	vmsvgaR3Info3dSurfaceBmp);
6165	# endif
6166
6167	return VINF_SUCCESS;
6168	}
6169
6170	# ifdef VBOX_WITH_VMSVGA3D
6171	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6172	static const char * const g_apszVmSvgaDevCapNames[] =
6173	{
6174	"x3D", /* = 0 */
6175	"xMAX_LIGHTS",
6176	"xMAX_TEXTURES",
6177	"xMAX_CLIP_PLANES",
6178	"xVERTEX_SHADER_VERSION",
6179	"xVERTEX_SHADER",
6180	"xFRAGMENT_SHADER_VERSION",
6181	"xFRAGMENT_SHADER",
6182	"xMAX_RENDER_TARGETS",
6183	"xS23E8_TEXTURES",
6184	"xS10E5_TEXTURES",
6185	"xMAX_FIXED_VERTEXBLEND",
6186	"xD16_BUFFER_FORMAT",
6187	"xD24S8_BUFFER_FORMAT",
6188	"xD24X8_BUFFER_FORMAT",
6189	"xQUERY_TYPES",
6190	"xTEXTURE_GRADIENT_SAMPLING",
6191	"rMAX_POINT_SIZE",
6192	"xMAX_SHADER_TEXTURES",
6193	"xMAX_TEXTURE_WIDTH",
6194	"xMAX_TEXTURE_HEIGHT",
6195	"xMAX_VOLUME_EXTENT",
6196	"xMAX_TEXTURE_REPEAT",
6197	"xMAX_TEXTURE_ASPECT_RATIO",
6198	"xMAX_TEXTURE_ANISOTROPY",
6199	"xMAX_PRIMITIVE_COUNT",
6200	"xMAX_VERTEX_INDEX",
6201	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6202	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6203	"xMAX_VERTEX_SHADER_TEMPS",
6204	"xMAX_FRAGMENT_SHADER_TEMPS",
6205	"xTEXTURE_OPS",
6206	"xSURFACEFMT_X8R8G8B8",
6207	"xSURFACEFMT_A8R8G8B8",
6208	"xSURFACEFMT_A2R10G10B10",
6209	"xSURFACEFMT_X1R5G5B5",
6210	"xSURFACEFMT_A1R5G5B5",
6211	"xSURFACEFMT_A4R4G4B4",
6212	"xSURFACEFMT_R5G6B5",
6213	"xSURFACEFMT_LUMINANCE16",
6214	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6215	"xSURFACEFMT_ALPHA8",
6216	"xSURFACEFMT_LUMINANCE8",
6217	"xSURFACEFMT_Z_D16",
6218	"xSURFACEFMT_Z_D24S8",
6219	"xSURFACEFMT_Z_D24X8",
6220	"xSURFACEFMT_DXT1",
6221	"xSURFACEFMT_DXT2",
6222	"xSURFACEFMT_DXT3",
6223	"xSURFACEFMT_DXT4",
6224	"xSURFACEFMT_DXT5",
6225	"xSURFACEFMT_BUMPX8L8V8U8",
6226	"xSURFACEFMT_A2W10V10U10",
6227	"xSURFACEFMT_BUMPU8V8",
6228	"xSURFACEFMT_Q8W8V8U8",
6229	"xSURFACEFMT_CxV8U8",
6230	"xSURFACEFMT_R_S10E5",
6231	"xSURFACEFMT_R_S23E8",
6232	"xSURFACEFMT_RG_S10E5",
6233	"xSURFACEFMT_RG_S23E8",
6234	"xSURFACEFMT_ARGB_S10E5",
6235	"xSURFACEFMT_ARGB_S23E8",
6236	"xMISSING62",
6237	"xMAX_VERTEX_SHADER_TEXTURES",
6238	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6239	"xSURFACEFMT_V16U16",
6240	"xSURFACEFMT_G16R16",
6241	"xSURFACEFMT_A16B16G16R16",
6242	"xSURFACEFMT_UYVY",
6243	"xSURFACEFMT_YUY2",
6244	"xMULTISAMPLE_NONMASKABLESAMPLES",
6245	"xMULTISAMPLE_MASKABLESAMPLES",
6246	"xALPHATOCOVERAGE",
6247	"xSUPERSAMPLE",
6248	"xAUTOGENMIPMAPS",
6249	"xSURFACEFMT_NV12",
6250	"xSURFACEFMT_AYUV",
6251	"xMAX_CONTEXT_IDS",
6252	"xMAX_SURFACE_IDS",
6253	"xSURFACEFMT_Z_DF16",
6254	"xSURFACEFMT_Z_DF24",
6255	"xSURFACEFMT_Z_D24S8_INT",
6256	"xSURFACEFMT_BC4_UNORM",
6257	"xSURFACEFMT_BC5_UNORM", /* 83 */
6258	};
6259	# endif
6260
6261
6262	/**
6263	* Power On notification.
6264	*
6265	* @returns VBox status code.
6266	* @param pDevIns The device instance data.
6267	*
6268	* @remarks Caller enters the device critical section.
6269	*/
6270	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6271	{
6272	# ifdef VBOX_WITH_VMSVGA3D
6273	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6274	if (pThis->svga.f3DEnabled)
6275	{
6276	int rc = vmsvga3dPowerOn(pThis);
6277
6278	if (RT_SUCCESS(rc))
6279	{
6280	bool fSavedBuffering = RTLogRelSetBuffering(true);
6281	SVGA3dCapsRecord *pCaps;
6282	SVGA3dCapPair *pData;
6283	uint32_t idxCap = 0;
6284
6285	/* 3d hardware version; latest and greatest */
6286	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6287	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6288
6289	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6290	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6291	pData = (SVGA3dCapPair *)&pCaps->data;
6292
6293	/* Fill out all 3d capabilities. */
6294	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6295	{
6296	uint32_t val = 0;
6297
6298	rc = vmsvga3dQueryCaps(pThis, i, &val);
6299	if (RT_SUCCESS(rc))
6300	{
6301	pData[idxCap][0] = i;
6302	pData[idxCap][1] = val;
6303	idxCap++;
6304	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6305	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6306	else
6307	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6308	&g_apszVmSvgaDevCapNames[i][1]));
6309	}
6310	else
6311	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6312	}
6313	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6314	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6315
6316	/* Mark end of record array. */
6317	pCaps->header.length = 0;
6318
6319	RTLogRelSetBuffering(fSavedBuffering);
6320	}
6321	}
6322	# else /* !VBOX_WITH_VMSVGA3D */
6323	RT_NOREF(pDevIns);
6324	# endif /* !VBOX_WITH_VMSVGA3D */
6325	}
6326
6327	#endif /* IN_RING3 */
6328

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 77237

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