VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 57358

最後變更 在這個檔案從57358是 57358,由 vboxsync 提交於 10 年 前

*: scm cleanup run.
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1/* $Id: DevVGA-SVGA.cpp 57358 2015-08-14 15:16:38Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2015 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.alldomusa.eu.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/ctype.h>
47# include <iprt/mem.h>
48#endif
49
50#include <VBox/VMMDev.h>
51#include <VBox/VBoxVideo.h>
52#include <VBox/bioslogo.h>
53
54/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
55#include "DevVGA.h"
56
57#ifdef DEBUG
58/* Enable to log FIFO register accesses. */
59//# define DEBUG_FIFO_ACCESS
60/* Enable to log GMR page accesses. */
61//# define DEBUG_GMR_ACCESS
62#endif
63
64#include "DevVGA-SVGA.h"
65#include "vmsvga/svga_reg.h"
66#include "vmsvga/svga_escape.h"
67#include "vmsvga/svga_overlay.h"
68#include "vmsvga/svga3d_reg.h"
69#include "vmsvga/svga3d_caps.h"
70#ifdef VBOX_WITH_VMSVGA3D
71# include "DevVGA-SVGA3d.h"
72# ifdef RT_OS_DARWIN
73# include "DevVGA-SVGA3d-cocoa.h"
74# endif
75#endif
76
77
78/*********************************************************************************************************************************
79* Defined Constants And Macros *
80*********************************************************************************************************************************/
81/**
82 * Macro for checking if a fixed FIFO register is valid according to the
83 * current FIFO configuration.
84 *
85 * @returns true / false.
86 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
87 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
88 */
89#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
90
91
92/*********************************************************************************************************************************
93* Structures and Typedefs *
94*********************************************************************************************************************************/
95/**
96 * 64-bit GMR descriptor.
97 */
98typedef struct
99{
100 RTGCPHYS GCPhys;
101 uint64_t numPages;
102} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
103
104/**
105 * GMR slot
106 */
107typedef struct
108{
109 uint32_t cMaxPages;
110 uint32_t cbTotal;
111 uint32_t numDescriptors;
112 PVMSVGAGMRDESCRIPTOR paDesc;
113} GMR, *PGMR;
114
115#ifdef IN_RING3
116/**
117 * Internal SVGA ring-3 only state.
118 */
119typedef struct VMSVGAR3STATE
120{
121 GMR aGMR[VMSVGA_MAX_GMR_IDS];
122 struct
123 {
124 SVGAGuestPtr ptr;
125 uint32_t bytesPerLine;
126 SVGAGMRImageFormat format;
127 } GMRFB;
128 struct
129 {
130 bool fActive;
131 uint32_t xHotspot;
132 uint32_t yHotspot;
133 uint32_t width;
134 uint32_t height;
135 uint32_t cbData;
136 void *pData;
137 } Cursor;
138 SVGAColorBGRX colorAnnotation;
139
140# ifdef VMSVGA_USE_EMT_HALT_CODE
141 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
142 uint32_t volatile cBusyDelayedEmts;
143 /** Set of EMTs that are */
144 VMCPUSET BusyDelayedEmts;
145# else
146 /** Number of EMTs waiting on hBusyDelayedEmts. */
147 uint32_t volatile cBusyDelayedEmts;
148 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
149 * busy (ugly). */
150 RTSEMEVENTMULTI hBusyDelayedEmts;
151# endif
152 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
153 STAMPROFILE StatBusyDelayEmts;
154
155 STAMPROFILE StatR3CmdPresent;
156 STAMPROFILE StatR3CmdDrawPrimitive;
157 STAMPROFILE StatR3CmdSurfaceDMA;
158
159 STAMCOUNTER StatFifoCommands;
160 STAMCOUNTER StatFifoErrors;
161 STAMCOUNTER StatFifoUnkCmds;
162 STAMCOUNTER StatFifoTodoTimeout;
163 STAMCOUNTER StatFifoTodoWoken;
164 STAMPROFILE StatFifoStalls;
165
166} VMSVGAR3STATE, *PVMSVGAR3STATE;
167#endif /* IN_RING3 */
168
169
170/*********************************************************************************************************************************
171* Internal Functions *
172*********************************************************************************************************************************/
173#ifdef IN_RING3
174# ifdef DEBUG_FIFO_ACCESS
175static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
176# endif
177# ifdef DEBUG_GMR_ACCESS
178static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
179# endif
180#endif
181
182
183/*********************************************************************************************************************************
184* Global Variables *
185*********************************************************************************************************************************/
186#ifdef IN_RING3
187
188/**
189 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
190 */
191static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
192{
193 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
194 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
195 SSMFIELD_ENTRY_TERM()
196};
197
198/**
199 * SSM descriptor table for the GMR structure.
200 */
201static SSMFIELD const g_aGMRFields[] =
202{
203 SSMFIELD_ENTRY( GMR, cMaxPages),
204 SSMFIELD_ENTRY( GMR, cbTotal),
205 SSMFIELD_ENTRY( GMR, numDescriptors),
206 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
207 SSMFIELD_ENTRY_TERM()
208};
209
210/**
211 * SSM descriptor table for the VMSVGAR3STATE structure.
212 */
213static SSMFIELD const g_aVMSVGAR3STATEFields[] =
214{
215 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
216 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
217 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
218 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
219 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
220 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
221 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
222 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
223 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
224 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
225 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
226#ifdef VMSVGA_USE_EMT_HALT_CODE
227 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
228#else
229 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
230#endif
231 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
232 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent),
233 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive),
234 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA),
235 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
236 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
237 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
238 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
239 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
240 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
241 SSMFIELD_ENTRY_TERM()
242};
243
244/**
245 * SSM descriptor table for the VGAState.svga structure.
246 */
247static SSMFIELD const g_aVGAStateSVGAFields[] =
248{
249 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
250 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
251 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
252 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
253 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
254 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
255 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
256 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
257 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
258 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
259 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
260 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
261 SSMFIELD_ENTRY( VMSVGAState, fBusy),
262 SSMFIELD_ENTRY( VMSVGAState, fTraces),
263 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
264 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
265 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
266 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
267 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
268 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
269 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
270 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
271 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
272 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
273 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
274 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
275 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
276 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
277 SSMFIELD_ENTRY( VMSVGAState, uWidth),
278 SSMFIELD_ENTRY( VMSVGAState, uHeight),
279 SSMFIELD_ENTRY( VMSVGAState, uBpp),
280 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
281 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
282 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
283 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
284 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
285 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
286 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
287 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
288 SSMFIELD_ENTRY_TERM()
289};
290
291static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
292
293#endif /* IN_RING3 */
294
295
296#ifdef LOG_ENABLED
297/**
298 * Index register string name lookup
299 *
300 * @returns Index register string or "UNKNOWN"
301 * @param pThis VMSVGA State
302 */
303static const char *vmsvgaIndexToString(PVGASTATE pThis)
304{
305 switch (pThis->svga.u32IndexReg)
306 {
307 case SVGA_REG_ID:
308 return "SVGA_REG_ID";
309 case SVGA_REG_ENABLE:
310 return "SVGA_REG_ENABLE";
311 case SVGA_REG_WIDTH:
312 return "SVGA_REG_WIDTH";
313 case SVGA_REG_HEIGHT:
314 return "SVGA_REG_HEIGHT";
315 case SVGA_REG_MAX_WIDTH:
316 return "SVGA_REG_MAX_WIDTH";
317 case SVGA_REG_MAX_HEIGHT:
318 return "SVGA_REG_MAX_HEIGHT";
319 case SVGA_REG_DEPTH:
320 return "SVGA_REG_DEPTH";
321 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
322 return "SVGA_REG_BITS_PER_PIXEL";
323 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
324 return "SVGA_REG_HOST_BITS_PER_PIXEL";
325 case SVGA_REG_PSEUDOCOLOR:
326 return "SVGA_REG_PSEUDOCOLOR";
327 case SVGA_REG_RED_MASK:
328 return "SVGA_REG_RED_MASK";
329 case SVGA_REG_GREEN_MASK:
330 return "SVGA_REG_GREEN_MASK";
331 case SVGA_REG_BLUE_MASK:
332 return "SVGA_REG_BLUE_MASK";
333 case SVGA_REG_BYTES_PER_LINE:
334 return "SVGA_REG_BYTES_PER_LINE";
335 case SVGA_REG_VRAM_SIZE: /* VRAM size */
336 return "SVGA_REG_VRAM_SIZE";
337 case SVGA_REG_FB_START: /* Frame buffer physical address. */
338 return "SVGA_REG_FB_START";
339 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
340 return "SVGA_REG_FB_OFFSET";
341 case SVGA_REG_FB_SIZE: /* Frame buffer size */
342 return "SVGA_REG_FB_SIZE";
343 case SVGA_REG_CAPABILITIES:
344 return "SVGA_REG_CAPABILITIES";
345 case SVGA_REG_MEM_START: /* FIFO start */
346 return "SVGA_REG_MEM_START";
347 case SVGA_REG_MEM_SIZE: /* FIFO size */
348 return "SVGA_REG_MEM_SIZE";
349 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
350 return "SVGA_REG_CONFIG_DONE";
351 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
352 return "SVGA_REG_SYNC";
353 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
354 return "SVGA_REG_BUSY";
355 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
356 return "SVGA_REG_GUEST_ID";
357 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
358 return "SVGA_REG_SCRATCH_SIZE";
359 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
360 return "SVGA_REG_MEM_REGS";
361 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
362 return "SVGA_REG_PITCHLOCK";
363 case SVGA_REG_IRQMASK: /* Interrupt mask */
364 return "SVGA_REG_IRQMASK";
365 case SVGA_REG_GMR_ID:
366 return "SVGA_REG_GMR_ID";
367 case SVGA_REG_GMR_DESCRIPTOR:
368 return "SVGA_REG_GMR_DESCRIPTOR";
369 case SVGA_REG_GMR_MAX_IDS:
370 return "SVGA_REG_GMR_MAX_IDS";
371 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
372 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
373 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
374 return "SVGA_REG_TRACES";
375 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
376 return "SVGA_REG_GMRS_MAX_PAGES";
377 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
378 return "SVGA_REG_MEMORY_SIZE";
379 case SVGA_REG_TOP: /* Must be 1 more than the last register */
380 return "SVGA_REG_TOP";
381 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
382 return "SVGA_PALETTE_BASE";
383 case SVGA_REG_CURSOR_ID:
384 return "SVGA_REG_CURSOR_ID";
385 case SVGA_REG_CURSOR_X:
386 return "SVGA_REG_CURSOR_X";
387 case SVGA_REG_CURSOR_Y:
388 return "SVGA_REG_CURSOR_Y";
389 case SVGA_REG_CURSOR_ON:
390 return "SVGA_REG_CURSOR_ON";
391 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
392 return "SVGA_REG_NUM_GUEST_DISPLAYS";
393 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
394 return "SVGA_REG_DISPLAY_ID";
395 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
396 return "SVGA_REG_DISPLAY_IS_PRIMARY";
397 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
398 return "SVGA_REG_DISPLAY_POSITION_X";
399 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
400 return "SVGA_REG_DISPLAY_POSITION_Y";
401 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
402 return "SVGA_REG_DISPLAY_WIDTH";
403 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
404 return "SVGA_REG_DISPLAY_HEIGHT";
405 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
406 return "SVGA_REG_NUM_DISPLAYS";
407
408 default:
409 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
410 return "SVGA_SCRATCH_BASE reg";
411 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
412 return "SVGA_PALETTE_BASE reg";
413 return "UNKNOWN";
414 }
415}
416
417/**
418 * FIFO command name lookup
419 *
420 * @returns FIFO command string or "UNKNOWN"
421 * @param u32Cmd FIFO command
422 */
423static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
424{
425 switch (u32Cmd)
426 {
427 case SVGA_CMD_INVALID_CMD:
428 return "SVGA_CMD_INVALID_CMD";
429 case SVGA_CMD_UPDATE:
430 return "SVGA_CMD_UPDATE";
431 case SVGA_CMD_RECT_COPY:
432 return "SVGA_CMD_RECT_COPY";
433 case SVGA_CMD_DEFINE_CURSOR:
434 return "SVGA_CMD_DEFINE_CURSOR";
435 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
436 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
437 case SVGA_CMD_UPDATE_VERBOSE:
438 return "SVGA_CMD_UPDATE_VERBOSE";
439 case SVGA_CMD_FRONT_ROP_FILL:
440 return "SVGA_CMD_FRONT_ROP_FILL";
441 case SVGA_CMD_FENCE:
442 return "SVGA_CMD_FENCE";
443 case SVGA_CMD_ESCAPE:
444 return "SVGA_CMD_ESCAPE";
445 case SVGA_CMD_DEFINE_SCREEN:
446 return "SVGA_CMD_DEFINE_SCREEN";
447 case SVGA_CMD_DESTROY_SCREEN:
448 return "SVGA_CMD_DESTROY_SCREEN";
449 case SVGA_CMD_DEFINE_GMRFB:
450 return "SVGA_CMD_DEFINE_GMRFB";
451 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
452 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
453 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
454 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
455 case SVGA_CMD_ANNOTATION_FILL:
456 return "SVGA_CMD_ANNOTATION_FILL";
457 case SVGA_CMD_ANNOTATION_COPY:
458 return "SVGA_CMD_ANNOTATION_COPY";
459 case SVGA_CMD_DEFINE_GMR2:
460 return "SVGA_CMD_DEFINE_GMR2";
461 case SVGA_CMD_REMAP_GMR2:
462 return "SVGA_CMD_REMAP_GMR2";
463 case SVGA_3D_CMD_SURFACE_DEFINE:
464 return "SVGA_3D_CMD_SURFACE_DEFINE";
465 case SVGA_3D_CMD_SURFACE_DESTROY:
466 return "SVGA_3D_CMD_SURFACE_DESTROY";
467 case SVGA_3D_CMD_SURFACE_COPY:
468 return "SVGA_3D_CMD_SURFACE_COPY";
469 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
470 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
471 case SVGA_3D_CMD_SURFACE_DMA:
472 return "SVGA_3D_CMD_SURFACE_DMA";
473 case SVGA_3D_CMD_CONTEXT_DEFINE:
474 return "SVGA_3D_CMD_CONTEXT_DEFINE";
475 case SVGA_3D_CMD_CONTEXT_DESTROY:
476 return "SVGA_3D_CMD_CONTEXT_DESTROY";
477 case SVGA_3D_CMD_SETTRANSFORM:
478 return "SVGA_3D_CMD_SETTRANSFORM";
479 case SVGA_3D_CMD_SETZRANGE:
480 return "SVGA_3D_CMD_SETZRANGE";
481 case SVGA_3D_CMD_SETRENDERSTATE:
482 return "SVGA_3D_CMD_SETRENDERSTATE";
483 case SVGA_3D_CMD_SETRENDERTARGET:
484 return "SVGA_3D_CMD_SETRENDERTARGET";
485 case SVGA_3D_CMD_SETTEXTURESTATE:
486 return "SVGA_3D_CMD_SETTEXTURESTATE";
487 case SVGA_3D_CMD_SETMATERIAL:
488 return "SVGA_3D_CMD_SETMATERIAL";
489 case SVGA_3D_CMD_SETLIGHTDATA:
490 return "SVGA_3D_CMD_SETLIGHTDATA";
491 case SVGA_3D_CMD_SETLIGHTENABLED:
492 return "SVGA_3D_CMD_SETLIGHTENABLED";
493 case SVGA_3D_CMD_SETVIEWPORT:
494 return "SVGA_3D_CMD_SETVIEWPORT";
495 case SVGA_3D_CMD_SETCLIPPLANE:
496 return "SVGA_3D_CMD_SETCLIPPLANE";
497 case SVGA_3D_CMD_CLEAR:
498 return "SVGA_3D_CMD_CLEAR";
499 case SVGA_3D_CMD_PRESENT:
500 return "SVGA_3D_CMD_PRESENT";
501 case SVGA_3D_CMD_SHADER_DEFINE:
502 return "SVGA_3D_CMD_SHADER_DEFINE";
503 case SVGA_3D_CMD_SHADER_DESTROY:
504 return "SVGA_3D_CMD_SHADER_DESTROY";
505 case SVGA_3D_CMD_SET_SHADER:
506 return "SVGA_3D_CMD_SET_SHADER";
507 case SVGA_3D_CMD_SET_SHADER_CONST:
508 return "SVGA_3D_CMD_SET_SHADER_CONST";
509 case SVGA_3D_CMD_DRAW_PRIMITIVES:
510 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
511 case SVGA_3D_CMD_SETSCISSORRECT:
512 return "SVGA_3D_CMD_SETSCISSORRECT";
513 case SVGA_3D_CMD_BEGIN_QUERY:
514 return "SVGA_3D_CMD_BEGIN_QUERY";
515 case SVGA_3D_CMD_END_QUERY:
516 return "SVGA_3D_CMD_END_QUERY";
517 case SVGA_3D_CMD_WAIT_FOR_QUERY:
518 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
519 case SVGA_3D_CMD_PRESENT_READBACK:
520 return "SVGA_3D_CMD_PRESENT_READBACK";
521 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
522 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
523 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
524 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
525 case SVGA_3D_CMD_GENERATE_MIPMAPS:
526 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
527 case SVGA_3D_CMD_ACTIVATE_SURFACE:
528 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
529 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
530 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
531 default:
532 return "UNKNOWN";
533 }
534}
535#endif
536
537/**
538 * @interface_method_impl{PDMIDISPLAYPORT::pfnSetViewport}
539 */
540DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
541{
542 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
543
544 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
545
546 pThis->svga.viewport.x = x;
547 pThis->svga.viewport.y = y;
548 pThis->svga.viewport.cx = RT_MIN(cx, (uint32_t)pThis->svga.uWidth);
549 pThis->svga.viewport.cy = RT_MIN(cy, (uint32_t)pThis->svga.uHeight);
550 return;
551}
552
553/**
554 * Read port register
555 *
556 * @returns VBox status code.
557 * @param pThis VMSVGA State
558 * @param pu32 Where to store the read value
559 */
560PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
561{
562 int rc = VINF_SUCCESS;
563
564 *pu32 = 0;
565 switch (pThis->svga.u32IndexReg)
566 {
567 case SVGA_REG_ID:
568 *pu32 = pThis->svga.u32SVGAId;
569 break;
570
571 case SVGA_REG_ENABLE:
572 *pu32 = pThis->svga.fEnabled;
573 break;
574
575 case SVGA_REG_WIDTH:
576 {
577 if ( pThis->svga.fEnabled
578 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
579 {
580 *pu32 = pThis->svga.uWidth;
581 }
582 else
583 {
584#ifndef IN_RING3
585 rc = VINF_IOM_R3_IOPORT_READ;
586#else
587 *pu32 = pThis->pDrv->cx;
588#endif
589 }
590 break;
591 }
592
593 case SVGA_REG_HEIGHT:
594 {
595 if ( pThis->svga.fEnabled
596 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
597 {
598 *pu32 = pThis->svga.uHeight;
599 }
600 else
601 {
602#ifndef IN_RING3
603 rc = VINF_IOM_R3_IOPORT_READ;
604#else
605 *pu32 = pThis->pDrv->cy;
606#endif
607 }
608 break;
609 }
610
611 case SVGA_REG_MAX_WIDTH:
612 *pu32 = pThis->svga.u32MaxWidth;
613 break;
614
615 case SVGA_REG_MAX_HEIGHT:
616 *pu32 = pThis->svga.u32MaxHeight;
617 break;
618
619 case SVGA_REG_DEPTH:
620 /* This returns the color depth of the current mode. */
621 switch (pThis->svga.uBpp)
622 {
623 case 15:
624 case 16:
625 case 24:
626 *pu32 = pThis->svga.uBpp;
627 break;
628
629 default:
630 case 32:
631 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
632 break;
633 }
634 break;
635
636 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
637 if ( pThis->svga.fEnabled
638 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
639 {
640 *pu32 = pThis->svga.uBpp;
641 }
642 else
643 {
644#ifndef IN_RING3
645 rc = VINF_IOM_R3_IOPORT_READ;
646#else
647 *pu32 = pThis->pDrv->cBits;
648#endif
649 }
650 break;
651
652 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
653 if ( pThis->svga.fEnabled
654 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
655 {
656 *pu32 = (pThis->svga.uBpp + 7) & ~7;
657 }
658 else
659 {
660#ifndef IN_RING3
661 rc = VINF_IOM_R3_IOPORT_READ;
662#else
663 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
664#endif
665 }
666 break;
667
668 case SVGA_REG_PSEUDOCOLOR:
669 *pu32 = 0;
670 break;
671
672 case SVGA_REG_RED_MASK:
673 case SVGA_REG_GREEN_MASK:
674 case SVGA_REG_BLUE_MASK:
675 {
676 uint32_t uBpp;
677
678 if ( pThis->svga.fEnabled
679 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
680 {
681 uBpp = pThis->svga.uBpp;
682 }
683 else
684 {
685#ifndef IN_RING3
686 rc = VINF_IOM_R3_IOPORT_READ;
687 break;
688#else
689 uBpp = pThis->pDrv->cBits;
690#endif
691 }
692 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
693 switch (uBpp)
694 {
695 case 8:
696 u32RedMask = 0x07;
697 u32GreenMask = 0x38;
698 u32BlueMask = 0xc0;
699 break;
700
701 case 15:
702 u32RedMask = 0x0000001f;
703 u32GreenMask = 0x000003e0;
704 u32BlueMask = 0x00007c00;
705 break;
706
707 case 16:
708 u32RedMask = 0x0000001f;
709 u32GreenMask = 0x000007e0;
710 u32BlueMask = 0x0000f800;
711 break;
712
713 case 24:
714 case 32:
715 default:
716 u32RedMask = 0x00ff0000;
717 u32GreenMask = 0x0000ff00;
718 u32BlueMask = 0x000000ff;
719 break;
720 }
721 switch (pThis->svga.u32IndexReg)
722 {
723 case SVGA_REG_RED_MASK:
724 *pu32 = u32RedMask;
725 break;
726
727 case SVGA_REG_GREEN_MASK:
728 *pu32 = u32GreenMask;
729 break;
730
731 case SVGA_REG_BLUE_MASK:
732 *pu32 = u32BlueMask;
733 break;
734 }
735 break;
736 }
737
738 case SVGA_REG_BYTES_PER_LINE:
739 {
740 if ( pThis->svga.fEnabled
741 && pThis->svga.cbScanline)
742 {
743 *pu32 = pThis->svga.cbScanline;
744 }
745 else
746 {
747#ifndef IN_RING3
748 rc = VINF_IOM_R3_IOPORT_READ;
749#else
750 *pu32 = pThis->pDrv->cbScanline;
751#endif
752 }
753 break;
754 }
755
756 case SVGA_REG_VRAM_SIZE: /* VRAM size */
757 *pu32 = pThis->vram_size;
758 break;
759
760 case SVGA_REG_FB_START: /* Frame buffer physical address. */
761 Assert(pThis->GCPhysVRAM <= 0xffffffff);
762 *pu32 = pThis->GCPhysVRAM;
763 break;
764
765 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
766 /* Always zero in our case. */
767 *pu32 = 0;
768 break;
769
770 case SVGA_REG_FB_SIZE: /* Frame buffer size */
771 {
772#ifndef IN_RING3
773 rc = VINF_IOM_R3_IOPORT_READ;
774#else
775 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
776 if ( pThis->svga.fEnabled
777 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
778 {
779 /* Hardware enabled; return real framebuffer size .*/
780 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
781 }
782 else
783 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
784
785 *pu32 = RT_MIN(pThis->vram_size, *pu32);
786 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
787#endif
788 break;
789 }
790
791 case SVGA_REG_CAPABILITIES:
792 *pu32 = pThis->svga.u32RegCaps;
793 break;
794
795 case SVGA_REG_MEM_START: /* FIFO start */
796 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
797 *pu32 = pThis->svga.GCPhysFIFO;
798 break;
799
800 case SVGA_REG_MEM_SIZE: /* FIFO size */
801 *pu32 = pThis->svga.cbFIFO;
802 break;
803
804 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
805 *pu32 = pThis->svga.fConfigured;
806 break;
807
808 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
809 *pu32 = 0;
810 break;
811
812 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
813 if (pThis->svga.fBusy)
814 {
815#ifndef IN_RING3
816 /* Go to ring-3 and halt the CPU. */
817 rc = VINF_IOM_R3_IOPORT_READ;
818 break;
819#elif defined(VMSVGA_USE_EMT_HALT_CODE)
820 /* The guest is basically doing a HLT via the device here, but with
821 a special wake up condition on FIFO completion. */
822 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
823 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
824 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
825 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
826 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
827 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
828 if (pThis->svga.fBusy)
829 rc = VMR3WaitForDeviceReady(pVM, idCpu);
830 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
831 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
832#else
833
834 /* Delay the EMT a bit so the FIFO and others can get some work done.
835 This used to be a crude 50 ms sleep. The current code tries to be
836 more efficient, but the consept is still very crude. */
837 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
838 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
839 RTThreadYield();
840 if (pThis->svga.fBusy)
841 {
842 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
843
844 if (pThis->svga.fBusy && cRefs == 1)
845 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
846 if (pThis->svga.fBusy)
847 {
848 /** @todo If this code is going to stay, we need to call into the halt/wait
849 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
850 * suffer when the guest is polling on a busy FIFO. */
851 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
852 if (cNsMaxWait >= RT_NS_100US)
853 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
854 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
855 RT_MIN(cNsMaxWait, RT_NS_10MS));
856 }
857
858 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
859 }
860 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
861#endif
862 *pu32 = pThis->svga.fBusy != 0;
863 }
864 else
865 *pu32 = false;
866 break;
867
868 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
869 *pu32 = pThis->svga.u32GuestId;
870 break;
871
872 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
873 *pu32 = pThis->svga.cScratchRegion;
874 break;
875
876 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
877 *pu32 = SVGA_FIFO_NUM_REGS;
878 break;
879
880 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
881 *pu32 = pThis->svga.u32PitchLock;
882 break;
883
884 case SVGA_REG_IRQMASK: /* Interrupt mask */
885 *pu32 = pThis->svga.u32IrqMask;
886 break;
887
888 /* See "Guest memory regions" below. */
889 case SVGA_REG_GMR_ID:
890 *pu32 = pThis->svga.u32CurrentGMRId;
891 break;
892
893 case SVGA_REG_GMR_DESCRIPTOR:
894 /* Write only */
895 *pu32 = 0;
896 break;
897
898 case SVGA_REG_GMR_MAX_IDS:
899 *pu32 = VMSVGA_MAX_GMR_IDS;
900 break;
901
902 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
903 *pu32 = VMSVGA_MAX_GMR_PAGES;
904 break;
905
906 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
907 *pu32 = pThis->svga.fTraces;
908 break;
909
910 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
911 *pu32 = VMSVGA_MAX_GMR_PAGES;
912 break;
913
914 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
915 *pu32 = VMSVGA_SURFACE_SIZE;
916 break;
917
918 case SVGA_REG_TOP: /* Must be 1 more than the last register */
919 break;
920
921 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
922 break;
923 /* Next 768 (== 256*3) registers exist for colormap */
924
925 /* Mouse cursor support. */
926 case SVGA_REG_CURSOR_ID:
927 case SVGA_REG_CURSOR_X:
928 case SVGA_REG_CURSOR_Y:
929 case SVGA_REG_CURSOR_ON:
930 break;
931
932 /* Legacy multi-monitor support */
933 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
934 *pu32 = 1;
935 break;
936
937 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
938 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
939 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
940 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
941 *pu32 = 0;
942 break;
943
944 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
945 *pu32 = pThis->svga.uWidth;
946 break;
947
948 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
949 *pu32 = pThis->svga.uHeight;
950 break;
951
952 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
953 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
954 break;
955
956 default:
957 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
958 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
959 {
960 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
961 }
962 break;
963 }
964 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
965 return rc;
966}
967
968#ifdef IN_RING3
969/**
970 * Apply the current resolution settings to change the video mode.
971 *
972 * @returns VBox status code.
973 * @param pThis VMSVGA State
974 */
975int vmsvgaChangeMode(PVGASTATE pThis)
976{
977 int rc;
978
979 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
980 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
981 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
982 {
983 /* Mode change in progress; wait for all values to be set. */
984 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
985 return VINF_SUCCESS;
986 }
987
988 if ( pThis->svga.uWidth == 0
989 || pThis->svga.uHeight == 0
990 || pThis->svga.uBpp == 0)
991 {
992 /* Invalid mode change - BB does this early in the boot up. */
993 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
994 return VINF_SUCCESS;
995 }
996
997 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
998 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
999 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1000 && pThis->last_width == (unsigned)pThis->svga.uWidth
1001 && pThis->last_height == (unsigned)pThis->svga.uHeight
1002 )
1003 {
1004 /* Nothing to do. */
1005 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1006 return VINF_SUCCESS;
1007 }
1008
1009 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1010 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1011
1012 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1013 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1014 AssertRC(rc);
1015 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1016
1017 /* last stuff */
1018 pThis->last_bpp = pThis->svga.uBpp;
1019 pThis->last_scr_width = pThis->svga.uWidth;
1020 pThis->last_scr_height = pThis->svga.uHeight;
1021 pThis->last_width = pThis->svga.uWidth;
1022 pThis->last_height = pThis->svga.uHeight;
1023
1024 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1025
1026 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1027 if ( pThis->svga.viewport.cx == 0
1028 && pThis->svga.viewport.cy == 0)
1029 {
1030 pThis->svga.viewport.cx = pThis->svga.uWidth;
1031 pThis->svga.viewport.cy = pThis->svga.uHeight;
1032 }
1033 return VINF_SUCCESS;
1034}
1035#endif /* IN_RING3 */
1036
1037#if defined(IN_RING0) || defined(IN_RING3)
1038/**
1039 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1040 *
1041 * @param pThis The VMSVGA state.
1042 * @param fState The busy state.
1043 */
1044DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1045{
1046 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1047
1048 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1049 {
1050 /* Race / unfortunately scheduling. Highly unlikly. */
1051 uint32_t cLoops = 64;
1052 do
1053 {
1054 ASMNopPause();
1055 fState = (pThis->svga.fBusy != 0);
1056 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1057 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1058 }
1059}
1060#endif
1061
1062/**
1063 * Write port register
1064 *
1065 * @returns VBox status code.
1066 * @param pThis VMSVGA State
1067 * @param u32 Value to write
1068 */
1069PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1070{
1071#ifdef IN_RING3
1072 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1073#endif
1074 int rc = VINF_SUCCESS;
1075
1076 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1077 switch (pThis->svga.u32IndexReg)
1078 {
1079 case SVGA_REG_ID:
1080 if ( u32 == SVGA_ID_0
1081 || u32 == SVGA_ID_1
1082 || u32 == SVGA_ID_2)
1083 pThis->svga.u32SVGAId = u32;
1084 break;
1085
1086 case SVGA_REG_ENABLE:
1087 if ( pThis->svga.fEnabled == u32
1088 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1089 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1090 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1091 && pThis->last_width == (unsigned)pThis->svga.uWidth
1092 && pThis->last_height == (unsigned)pThis->svga.uHeight
1093 )
1094 /* Nothing to do. */
1095 break;
1096
1097#ifdef IN_RING3
1098 if ( u32 == 1
1099 && pThis->svga.fEnabled == false)
1100 {
1101 /* Make a backup copy of the first 32k in order to save font data etc. */
1102 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1103 }
1104
1105 pThis->svga.fEnabled = u32;
1106 if (pThis->svga.fEnabled)
1107 {
1108 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1109 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1110 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1111 {
1112 /* Keep the current mode. */
1113 pThis->svga.uWidth = pThis->pDrv->cx;
1114 pThis->svga.uHeight = pThis->pDrv->cy;
1115 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1116 }
1117
1118 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1119 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1120 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1121 {
1122 rc = vmsvgaChangeMode(pThis);
1123 AssertRCReturn(rc, rc);
1124 }
1125 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1126 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1127 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1128
1129 /* Disable or enable dirty page tracking according to the current fTraces value. */
1130 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1131 }
1132 else
1133 {
1134 /* Restore the text mode backup. */
1135 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1136
1137/* pThis->svga.uHeight = -1;
1138 pThis->svga.uWidth = -1;
1139 pThis->svga.uBpp = -1;
1140 pThis->svga.cbScanline = 0; */
1141 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1142
1143 /* Enable dirty page tracking again when going into legacy mode. */
1144 vmsvgaSetTraces(pThis, true);
1145 }
1146#else
1147 rc = VINF_IOM_R3_IOPORT_WRITE;
1148#endif
1149 break;
1150
1151 case SVGA_REG_WIDTH:
1152 if (pThis->svga.uWidth != u32)
1153 {
1154 if (pThis->svga.fEnabled)
1155 {
1156#ifdef IN_RING3
1157 pThis->svga.uWidth = u32;
1158 rc = vmsvgaChangeMode(pThis);
1159 AssertRCReturn(rc, rc);
1160#else
1161 rc = VINF_IOM_R3_IOPORT_WRITE;
1162#endif
1163 }
1164 else
1165 pThis->svga.uWidth = u32;
1166 }
1167 /* else: nop */
1168 break;
1169
1170 case SVGA_REG_HEIGHT:
1171 if (pThis->svga.uHeight != u32)
1172 {
1173 if (pThis->svga.fEnabled)
1174 {
1175#ifdef IN_RING3
1176 pThis->svga.uHeight = u32;
1177 rc = vmsvgaChangeMode(pThis);
1178 AssertRCReturn(rc, rc);
1179#else
1180 rc = VINF_IOM_R3_IOPORT_WRITE;
1181#endif
1182 }
1183 else
1184 pThis->svga.uHeight = u32;
1185 }
1186 /* else: nop */
1187 break;
1188
1189 case SVGA_REG_DEPTH:
1190 /** @todo read-only?? */
1191 break;
1192
1193 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1194 if (pThis->svga.uBpp != u32)
1195 {
1196 if (pThis->svga.fEnabled)
1197 {
1198#ifdef IN_RING3
1199 pThis->svga.uBpp = u32;
1200 rc = vmsvgaChangeMode(pThis);
1201 AssertRCReturn(rc, rc);
1202#else
1203 rc = VINF_IOM_R3_IOPORT_WRITE;
1204#endif
1205 }
1206 else
1207 pThis->svga.uBpp = u32;
1208 }
1209 /* else: nop */
1210 break;
1211
1212 case SVGA_REG_PSEUDOCOLOR:
1213 break;
1214
1215 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1216#ifdef IN_RING3
1217 pThis->svga.fConfigured = u32;
1218 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1219 if (!pThis->svga.fConfigured)
1220 {
1221 pThis->svga.fTraces = true;
1222 }
1223 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1224#else
1225 rc = VINF_IOM_R3_IOPORT_WRITE;
1226#endif
1227 break;
1228
1229 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1230 if ( pThis->svga.fEnabled
1231 && pThis->svga.fConfigured)
1232 {
1233#if defined(IN_RING3) || defined(IN_RING0)
1234 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1235 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1236 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1237 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1238
1239 /* Kick the FIFO thread to start processing commands again. */
1240 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1241#else
1242 rc = VINF_IOM_R3_IOPORT_WRITE;
1243#endif
1244 }
1245 /* else nothing to do. */
1246 else
1247 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1248
1249 break;
1250
1251 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1252 break;
1253
1254 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1255 pThis->svga.u32GuestId = u32;
1256 break;
1257
1258 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1259 pThis->svga.u32PitchLock = u32;
1260 break;
1261
1262 case SVGA_REG_IRQMASK: /* Interrupt mask */
1263 pThis->svga.u32IrqMask = u32;
1264
1265 /* Irq pending after the above change? */
1266 if (pThis->svga.u32IrqStatus & u32)
1267 {
1268 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1269 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1270 }
1271 else
1272 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1273 break;
1274
1275 /* Mouse cursor support */
1276 case SVGA_REG_CURSOR_ID:
1277 case SVGA_REG_CURSOR_X:
1278 case SVGA_REG_CURSOR_Y:
1279 case SVGA_REG_CURSOR_ON:
1280 break;
1281
1282 /* Legacy multi-monitor support */
1283 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1284 break;
1285 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1286 break;
1287 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1288 break;
1289 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1290 break;
1291 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1292 break;
1293 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1294 break;
1295 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1296 break;
1297#ifdef VBOX_WITH_VMSVGA3D
1298 /* See "Guest memory regions" below. */
1299 case SVGA_REG_GMR_ID:
1300 pThis->svga.u32CurrentGMRId = u32;
1301 break;
1302
1303 case SVGA_REG_GMR_DESCRIPTOR:
1304# ifndef IN_RING3
1305 rc = VINF_IOM_R3_IOPORT_WRITE;
1306 break;
1307# else /* IN_RING3 */
1308 {
1309 SVGAGuestMemDescriptor desc;
1310 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1311 RTGCPHYS GCPhysBase = GCPhys;
1312 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1313 uint32_t cDescriptorsAllocated = 16;
1314 uint32_t iDescriptor = 0;
1315
1316 /* Validate current GMR id. */
1317 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1318
1319 /* Free the old GMR if present. */
1320 vmsvgaGMRFree(pThis, idGMR);
1321
1322 /* Just undefine the GMR? */
1323 if (GCPhys == 0)
1324 break;
1325
1326 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1327 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1328
1329 /* Never cross a page boundary automatically. */
1330 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1331 {
1332 /* Read descriptor. */
1333 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1334 AssertRCBreak(rc);
1335
1336 if ( desc.ppn == 0
1337 && desc.numPages == 0)
1338 break; /* terminator */
1339
1340 if ( desc.ppn != 0
1341 && desc.numPages == 0)
1342 {
1343 /* Pointer to the next physical page of descriptors. */
1344 GCPhys = GCPhysBase = desc.ppn << PAGE_SHIFT;
1345 }
1346 else
1347 {
1348 if (iDescriptor == cDescriptorsAllocated)
1349 {
1350 cDescriptorsAllocated += 16;
1351 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1352 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1353 }
1354
1355 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
1356 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1357 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1358
1359 /* Continue with the next descriptor. */
1360 GCPhys += sizeof(desc);
1361 }
1362 }
1363 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1364 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1365
1366 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1367 {
1368 AssertFailed();
1369 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1370 pSVGAState->aGMR[idGMR].paDesc = NULL;
1371 }
1372 AssertRC(rc);
1373 break;
1374 }
1375# endif /* IN_RING3 */
1376#endif // VBOX_WITH_VMSVGA3D
1377
1378 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1379 if (pThis->svga.fTraces == u32)
1380 break; /* nothing to do */
1381
1382#ifdef IN_RING3
1383 vmsvgaSetTraces(pThis, !!u32);
1384#else
1385 rc = VINF_IOM_R3_IOPORT_WRITE;
1386#endif
1387 break;
1388
1389 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1390 break;
1391
1392 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1393 break;
1394 /* Next 768 (== 256*3) registers exist for colormap */
1395
1396 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1397 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1398 break;
1399
1400 case SVGA_REG_FB_START:
1401 case SVGA_REG_MEM_START:
1402 case SVGA_REG_HOST_BITS_PER_PIXEL:
1403 case SVGA_REG_MAX_WIDTH:
1404 case SVGA_REG_MAX_HEIGHT:
1405 case SVGA_REG_VRAM_SIZE:
1406 case SVGA_REG_FB_SIZE:
1407 case SVGA_REG_CAPABILITIES:
1408 case SVGA_REG_MEM_SIZE:
1409 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1410 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1411 case SVGA_REG_BYTES_PER_LINE:
1412 case SVGA_REG_FB_OFFSET:
1413 case SVGA_REG_RED_MASK:
1414 case SVGA_REG_GREEN_MASK:
1415 case SVGA_REG_BLUE_MASK:
1416 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1417 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1418 case SVGA_REG_GMR_MAX_IDS:
1419 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1420 /* Read only - ignore. */
1421 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1422 break;
1423
1424 default:
1425 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1426 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1427 {
1428 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1429 }
1430 break;
1431 }
1432 return rc;
1433}
1434
1435/**
1436 * Port I/O Handler for IN operations.
1437 *
1438 * @returns VINF_SUCCESS or VINF_EM_*.
1439 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1440 *
1441 * @param pDevIns The device instance.
1442 * @param pvUser User argument.
1443 * @param uPort Port number used for the IN operation.
1444 * @param pu32 Where to store the result. This is always a 32-bit
1445 * variable regardless of what @a cb might say.
1446 * @param cb Number of bytes read.
1447 */
1448PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1449{
1450 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1451 int rc = VINF_SUCCESS;
1452
1453 /* Ignore non-dword accesses. */
1454 if (cb != 4)
1455 {
1456 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1457 *pu32 = ~0;
1458 return VINF_SUCCESS;
1459 }
1460
1461 switch (Port - pThis->svga.BasePort)
1462 {
1463 case SVGA_INDEX_PORT:
1464 *pu32 = pThis->svga.u32IndexReg;
1465 break;
1466
1467 case SVGA_VALUE_PORT:
1468 return vmsvgaReadPort(pThis, pu32);
1469
1470 case SVGA_BIOS_PORT:
1471 Log(("Ignoring BIOS port read\n"));
1472 *pu32 = 0;
1473 break;
1474
1475 case SVGA_IRQSTATUS_PORT:
1476 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1477 *pu32 = pThis->svga.u32IrqStatus;
1478 break;
1479 }
1480 return rc;
1481}
1482
1483/**
1484 * Port I/O Handler for OUT operations.
1485 *
1486 * @returns VINF_SUCCESS or VINF_EM_*.
1487 *
1488 * @param pDevIns The device instance.
1489 * @param pvUser User argument.
1490 * @param uPort Port number used for the OUT operation.
1491 * @param u32 The value to output.
1492 * @param cb The value size in bytes.
1493 */
1494PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1495{
1496 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1497 int rc = VINF_SUCCESS;
1498
1499 /* Ignore non-dword accesses. */
1500 if (cb != 4)
1501 {
1502 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1503 return VINF_SUCCESS;
1504 }
1505
1506 switch (Port - pThis->svga.BasePort)
1507 {
1508 case SVGA_INDEX_PORT:
1509 pThis->svga.u32IndexReg = u32;
1510 break;
1511
1512 case SVGA_VALUE_PORT:
1513 return vmsvgaWritePort(pThis, u32);
1514
1515 case SVGA_BIOS_PORT:
1516 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1517 break;
1518
1519 case SVGA_IRQSTATUS_PORT:
1520 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1521 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1522 /* Clear the irq in case all events have been cleared. */
1523 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1524 {
1525 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1526 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1527 }
1528 break;
1529 }
1530 return rc;
1531}
1532
1533#ifdef DEBUG_FIFO_ACCESS
1534
1535# ifdef IN_RING3
1536/**
1537 * Handle LFB access.
1538 * @returns VBox status code.
1539 * @param pVM VM handle.
1540 * @param pThis VGA device instance data.
1541 * @param GCPhys The access physical address.
1542 * @param fWriteAccess Read or write access
1543 */
1544static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1545{
1546 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1547 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1548
1549 switch (GCPhysOffset >> 2)
1550 {
1551 case SVGA_FIFO_MIN:
1552 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1553 break;
1554 case SVGA_FIFO_MAX:
1555 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1556 break;
1557 case SVGA_FIFO_NEXT_CMD:
1558 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1559 break;
1560 case SVGA_FIFO_STOP:
1561 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1562 break;
1563 case SVGA_FIFO_CAPABILITIES:
1564 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1565 break;
1566 case SVGA_FIFO_FLAGS:
1567 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1568 break;
1569 case SVGA_FIFO_FENCE:
1570 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1571 break;
1572 case SVGA_FIFO_3D_HWVERSION:
1573 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1574 break;
1575 case SVGA_FIFO_PITCHLOCK:
1576 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1577 break;
1578 case SVGA_FIFO_CURSOR_ON:
1579 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1580 break;
1581 case SVGA_FIFO_CURSOR_X:
1582 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1583 break;
1584 case SVGA_FIFO_CURSOR_Y:
1585 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1586 break;
1587 case SVGA_FIFO_CURSOR_COUNT:
1588 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1589 break;
1590 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1591 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1592 break;
1593 case SVGA_FIFO_RESERVED:
1594 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1595 break;
1596 case SVGA_FIFO_CURSOR_SCREEN_ID:
1597 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1598 break;
1599 case SVGA_FIFO_DEAD:
1600 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1601 break;
1602 case SVGA_FIFO_3D_HWVERSION_REVISED:
1603 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1604 break;
1605 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1606 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1607 break;
1608 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1609 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1610 break;
1611 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1612 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1613 break;
1614 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1615 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1616 break;
1617 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1618 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1619 break;
1620 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1621 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1622 break;
1623 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1624 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1625 break;
1626 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1627 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1628 break;
1629 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1630 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1631 break;
1632 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1633 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1634 break;
1635 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1636 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1637 break;
1638 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1639 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1640 break;
1641 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1642 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1643 break;
1644 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1645 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1646 break;
1647 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1648 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1649 break;
1650 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1651 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1652 break;
1653 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1654 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1655 break;
1656 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1657 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1658 break;
1659 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1660 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1661 break;
1662 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1663 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1664 break;
1665 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1666 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1667 break;
1668 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1669 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1670 break;
1671 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1672 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1673 break;
1674 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1675 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1676 break;
1677 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1678 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1679 break;
1680 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1681 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1682 break;
1683 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1684 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1685 break;
1686 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1687 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1688 break;
1689 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1690 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1691 break;
1692 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1693 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1694 break;
1695 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1696 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1697 break;
1698 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1699 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1700 break;
1701 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1702 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1703 break;
1704 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1705 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1706 break;
1707 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1708 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1709 break;
1710 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1711 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1712 break;
1713 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1714 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1715 break;
1716 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1717 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1718 break;
1719 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1720 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1721 break;
1722 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1723 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1724 break;
1725 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1726 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1727 break;
1728 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1729 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1730 break;
1731 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1732 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1733 break;
1734 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1735 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1736 break;
1737 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1738 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1739 break;
1740 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1741 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1742 break;
1743 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1744 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1745 break;
1746 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1747 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1748 break;
1749 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1750 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1751 break;
1752 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1753 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1754 break;
1755 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1756 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1757 break;
1758 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1759 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1760 break;
1761 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1762 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1763 break;
1764 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1765 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1766 break;
1767 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1768 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1769 break;
1770 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1771 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1772 break;
1773 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1774 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1775 break;
1776 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1777 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1778 break;
1779 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1780 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1781 break;
1782 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1783 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1784 break;
1785 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1786 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1787 break;
1788 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1789 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1790 break;
1791 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1792 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1793 break;
1794 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1795 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1796 break;
1797 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1798 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1799 break;
1800 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1801 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1802 break;
1803 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1804 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1805 break;
1806 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1807 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1808 break;
1809 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1810 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1811 break;
1812 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1813 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1814 break;
1815 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1816 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1817 break;
1818 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1819 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1820 break;
1821 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1822 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1823 break;
1824 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1825 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1826 break;
1827 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1828 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1829 break;
1830 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1831 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1832 break;
1833 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1834 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1835 break;
1836 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1837 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1838 break;
1839 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1840 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1841 break;
1842 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1843 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1844 break;
1845 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1846 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1847 break;
1848 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1849 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1850 break;
1851 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1852 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1853 break;
1854 case SVGA_FIFO_3D_CAPS_LAST:
1855 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1856 break;
1857 case SVGA_FIFO_GUEST_3D_HWVERSION:
1858 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1859 break;
1860 case SVGA_FIFO_FENCE_GOAL:
1861 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1862 break;
1863 case SVGA_FIFO_BUSY:
1864 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1865 break;
1866 default:
1867 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1868 break;
1869 }
1870
1871 return VINF_EM_RAW_EMULATE_INSTR;
1872}
1873
1874/**
1875 * HC access handler for the FIFO.
1876 *
1877 * @returns VINF_SUCCESS if the handler have carried out the operation.
1878 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1879 * @param pVM VM Handle.
1880 * @param pVCpu The cross context CPU structure for the calling EMT.
1881 * @param GCPhys The physical address the guest is writing to.
1882 * @param pvPhys The HC mapping of that address.
1883 * @param pvBuf What the guest is reading/writing.
1884 * @param cbBuf How much it's reading/writing.
1885 * @param enmAccessType The access type.
1886 * @param enmOrigin Who is making the access.
1887 * @param pvUser User argument.
1888 */
1889static DECLCALLBACK(VBOXSTRICTRC)
1890vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1891 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1892{
1893 PVGASTATE pThis = (PVGASTATE)pvUser;
1894 int rc;
1895 Assert(pThis);
1896 Assert(GCPhys >= pThis->GCPhysVRAM);
1897 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1898
1899 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1900 if (RT_SUCCESS(rc))
1901 return VINF_PGM_HANDLER_DO_DEFAULT;
1902 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1903 return rc;
1904}
1905
1906# endif /* IN_RING3 */
1907#endif /* DEBUG_FIFO_ACCESS */
1908
1909#ifdef DEBUG_GMR_ACCESS
1910/**
1911 * HC access handler for the FIFO.
1912 *
1913 * @returns VINF_SUCCESS if the handler have carried out the operation.
1914 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1915 * @param pVM VM Handle.
1916 * @param pVCpu The cross context CPU structure for the calling EMT.
1917 * @param GCPhys The physical address the guest is writing to.
1918 * @param pvPhys The HC mapping of that address.
1919 * @param pvBuf What the guest is reading/writing.
1920 * @param cbBuf How much it's reading/writing.
1921 * @param enmAccessType The access type.
1922 * @param enmOrigin Who is making the access.
1923 * @param pvUser User argument.
1924 */
1925static DECLCALLBACK(VBOXSTRICTRC)
1926vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1927 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1928{
1929 PVGASTATE pThis = (PVGASTATE)pvUser;
1930 Assert(pThis);
1931 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1932 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1933
1934 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1935
1936 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1937 {
1938 PGMR pGMR = &pSVGAState->aGMR[i];
1939
1940 if (pGMR->numDescriptors)
1941 {
1942 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1943 {
1944 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1945 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1946 {
1947 /*
1948 * Turn off the write handler for this particular page and make it R/W.
1949 * Then return telling the caller to restart the guest instruction.
1950 */
1951 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1952 goto end;
1953 }
1954 }
1955 }
1956 }
1957end:
1958 return VINF_PGM_HANDLER_DO_DEFAULT;
1959}
1960
1961# ifdef IN_RING3
1962
1963/* Callback handler for VMR3ReqCallWait */
1964static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1965{
1966 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1967 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1968 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1969 int rc;
1970
1971 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1972 {
1973 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
1974 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
1975 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
1976 AssertRC(rc);
1977 }
1978 return VINF_SUCCESS;
1979}
1980
1981/* Callback handler for VMR3ReqCallWait */
1982static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1983{
1984 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1985 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1986 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1987
1988 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1989 {
1990 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
1991 AssertRC(rc);
1992 }
1993 return VINF_SUCCESS;
1994}
1995
1996/* Callback handler for VMR3ReqCallWait */
1997static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
1998{
1999 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2000
2001 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2002 {
2003 PGMR pGMR = &pSVGAState->aGMR[i];
2004
2005 if (pGMR->numDescriptors)
2006 {
2007 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2008 {
2009 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2010 AssertRC(rc);
2011 }
2012 }
2013 }
2014 return VINF_SUCCESS;
2015}
2016
2017# endif /* IN_RING3 */
2018#endif /* DEBUG_GMR_ACCESS */
2019
2020/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2021
2022#ifdef IN_RING3
2023
2024/**
2025 * Worker for vmsvgaR3FifoThread that handles an external command.
2026 *
2027 * @param pThis VGA device instance data.
2028 */
2029static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2030{
2031 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2032 switch (pThis->svga.u8FIFOExtCommand)
2033 {
2034 case VMSVGA_FIFO_EXTCMD_RESET:
2035 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2036 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2037# ifdef VBOX_WITH_VMSVGA3D
2038 if (pThis->svga.f3DEnabled)
2039 {
2040 /* The 3d subsystem must be reset from the fifo thread. */
2041 vmsvga3dReset(pThis);
2042 }
2043# endif
2044 break;
2045
2046 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2047 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2048 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2049# ifdef VBOX_WITH_VMSVGA3D
2050 if (pThis->svga.f3DEnabled)
2051 {
2052 /* The 3d subsystem must be shut down from the fifo thread. */
2053 vmsvga3dTerminate(pThis);
2054 }
2055# endif
2056 break;
2057
2058 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2059 {
2060 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2061# ifdef VBOX_WITH_VMSVGA3D
2062 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2063 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2064 vmsvga3dSaveExec(pThis, pSSM);
2065# endif
2066 break;
2067 }
2068
2069 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2070 {
2071 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2072# ifdef VBOX_WITH_VMSVGA3D
2073 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2074 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2075 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2076# endif
2077 break;
2078 }
2079
2080 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2081 {
2082# ifdef VBOX_WITH_VMSVGA3D
2083 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2084 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2085 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2086# endif
2087 break;
2088 }
2089
2090
2091 default:
2092 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2093 break;
2094 }
2095
2096 /*
2097 * Signal the end of the external command.
2098 */
2099 pThis->svga.pvFIFOExtCmdParam = NULL;
2100 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2101 ASMMemoryFence(); /* paranoia^2 */
2102 int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2103 AssertLogRelRC(rc);
2104}
2105
2106/**
2107 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2108 * doing a job on the FIFO thread (even when it's officially suspended).
2109 *
2110 * @returns VBox status code (fully asserted).
2111 * @param pThis VGA device instance data.
2112 * @param uExtCmd The command to execute on the FIFO thread.
2113 * @param pvParam Pointer to command parameters.
2114 * @param cMsWait The time to wait for the command, given in
2115 * milliseconds.
2116 */
2117static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2118{
2119 Assert(cMsWait >= RT_MS_1SEC * 5);
2120 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2121 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2122
2123 int rc;
2124 PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2125 PDMTHREADSTATE enmState = pThread->enmState;
2126 if (enmState == PDMTHREADSTATE_SUSPENDED)
2127 {
2128 /*
2129 * The thread is suspended, we have to temporarily wake it up so it can
2130 * perform the task.
2131 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
2132 */
2133 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2134 /* Post the request. */
2135 pThis->svga.fFifoExtCommandWakeup = true;
2136 pThis->svga.pvFIFOExtCmdParam = pvParam;
2137 pThis->svga.u8FIFOExtCommand = uExtCmd;
2138 ASMMemoryFence(); /* paranoia^3 */
2139
2140 /* Resume the thread. */
2141 rc = PDMR3ThreadResume(pThread);
2142 AssertLogRelRC(rc);
2143 if (RT_SUCCESS(rc))
2144 {
2145 /* Wait. Take care in case the semaphore was already posted (same as below). */
2146 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2147 if ( rc == VINF_SUCCESS
2148 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2149 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2150 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2151 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2152
2153 /* suspend the thread */
2154 pThis->svga.fFifoExtCommandWakeup = false;
2155 int rc2 = PDMR3ThreadSuspend(pThread);
2156 AssertLogRelRC(rc2);
2157 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2158 rc = rc2;
2159 }
2160 pThis->svga.fFifoExtCommandWakeup = false;
2161 pThis->svga.pvFIFOExtCmdParam = NULL;
2162 }
2163 else if (enmState == PDMTHREADSTATE_RUNNING)
2164 {
2165 /*
2166 * The thread is running, should only happen during reset and vmsvga3dsfc.
2167 * We ASSUME not racing code here, both wrt thread state and ext commands.
2168 */
2169 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2170 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2171
2172 /* Post the request. */
2173 pThis->svga.pvFIFOExtCmdParam = pvParam;
2174 pThis->svga.u8FIFOExtCommand = uExtCmd;
2175 ASMMemoryFence(); /* paranoia^2 */
2176 rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2177 AssertLogRelRC(rc);
2178
2179 /* Wait. Take care in case the semaphore was already posted (same as above). */
2180 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2181 if ( rc == VINF_SUCCESS
2182 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2183 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2184 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2185 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2186
2187 pThis->svga.pvFIFOExtCmdParam = NULL;
2188 }
2189 else
2190 {
2191 /*
2192 * Something is wrong with the thread!
2193 */
2194 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2195 rc = VERR_INVALID_STATE;
2196 }
2197 return rc;
2198}
2199
2200
2201/**
2202 * Marks the FIFO non-busy, notifying any waiting EMTs.
2203 *
2204 * @param pThis The VGA state.
2205 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2206 * @param offFifoMin The start byte offset of the command FIFO.
2207 */
2208static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2209{
2210 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2211 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2212 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2213
2214 /* Wake up any waiting EMTs. */
2215 if (pSVGAState->cBusyDelayedEmts > 0)
2216 {
2217#ifdef VMSVGA_USE_EMT_HALT_CODE
2218 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2219 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2220 if (idCpu != NIL_VMCPUID)
2221 {
2222 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2223 while (idCpu-- > 0)
2224 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2225 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2226 }
2227#else
2228 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2229 AssertRC(rc2);
2230#endif
2231 }
2232}
2233
2234/**
2235 * Reads (more) payload into the command buffer.
2236 *
2237 * @returns pbBounceBuf on success
2238 * @retval (void *)1 if the thread was requested to stop.
2239 * @retval NULL on FIFO error.
2240 *
2241 * @param cbPayloadReq The number of bytes of payload requested.
2242 * @param pFIFO The FIFO.
2243 * @param offCurrentCmd The FIFO byte offset of the current command.
2244 * @param offFifoMin The start byte offset of the command FIFO.
2245 * @param offFifoMax The end byte offset of the command FIFO.
2246 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2247 * always sufficient size.
2248 * @param pcbAlreadyRead How much payload we've already read into the bounce
2249 * buffer. (We will NEVER re-read anything.)
2250 * @param pThread The calling PDM thread handle.
2251 * @param pThis The VGA state.
2252 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2253 * statistics collection.
2254 */
2255static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2256 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2257 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2258 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2259{
2260 Assert(pbBounceBuf);
2261 Assert(pcbAlreadyRead);
2262 Assert(offFifoMin < offFifoMax);
2263 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2264 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2265
2266 /*
2267 * Check if the requested payload size has already been satisfied .
2268 * .
2269 * When called to read more, the caller is responsible for making sure the .
2270 * new command size (cbRequsted) never is smaller than what has already .
2271 * been read.
2272 */
2273 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2274 if (cbPayloadReq <= cbAlreadyRead)
2275 {
2276 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2277 return pbBounceBuf;
2278 }
2279
2280 /*
2281 * Commands bigger than the fifo buffer are invalid.
2282 */
2283 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2284 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2285 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2286 NULL);
2287
2288 /*
2289 * Move offCurrentCmd past the command dword.
2290 */
2291 offCurrentCmd += sizeof(uint32_t);
2292 if (offCurrentCmd >= offFifoMax)
2293 offCurrentCmd = offFifoMin;
2294
2295 /*
2296 * Do we have sufficient payload data available already?
2297 */
2298 uint32_t cbAfter, cbBefore;
2299 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2300 if (offNextCmd > offCurrentCmd)
2301 {
2302 if (RT_LIKELY(offNextCmd < offFifoMax))
2303 cbAfter = offNextCmd - offCurrentCmd;
2304 else
2305 {
2306 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2307 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2308 offNextCmd, offFifoMin, offFifoMax));
2309 cbAfter = offFifoMax - offCurrentCmd;
2310 }
2311 cbBefore = 0;
2312 }
2313 else
2314 {
2315 cbAfter = offFifoMax - offCurrentCmd;
2316 if (offNextCmd >= offFifoMin)
2317 cbBefore = offNextCmd - offFifoMin;
2318 else
2319 {
2320 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2321 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2322 offNextCmd, offFifoMin, offFifoMax));
2323 cbBefore = 0;
2324 }
2325 }
2326 if (cbAfter + cbBefore < cbPayloadReq)
2327 {
2328 /*
2329 * Insufficient, must wait for it to arrive.
2330 */
2331 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2332 for (uint32_t i = 0;; i++)
2333 {
2334 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2335 {
2336 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2337 return (void *)(uintptr_t)1;
2338 }
2339 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2340 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2341
2342 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2343
2344 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2345 if (offNextCmd > offCurrentCmd)
2346 {
2347 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2348 cbBefore = 0;
2349 }
2350 else
2351 {
2352 cbAfter = offFifoMax - offCurrentCmd;
2353 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2354 }
2355
2356 if (cbAfter + cbBefore >= cbPayloadReq)
2357 break;
2358 }
2359 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2360 }
2361
2362 /*
2363 * Copy out the memory and update what pcbAlreadyRead points to.
2364 */
2365 if (cbAfter >= cbPayloadReq)
2366 memcpy(pbBounceBuf + cbAlreadyRead,
2367 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2368 cbPayloadReq - cbAlreadyRead);
2369 else
2370 {
2371 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2372 if (cbAlreadyRead < cbAfter)
2373 {
2374 memcpy(pbBounceBuf + cbAlreadyRead,
2375 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2376 cbAfter - cbAlreadyRead);
2377 cbAlreadyRead = cbAfter;
2378 }
2379 memcpy(pbBounceBuf + cbAlreadyRead,
2380 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2381 cbPayloadReq - cbAlreadyRead);
2382 }
2383 *pcbAlreadyRead = cbPayloadReq;
2384 return pbBounceBuf;
2385}
2386
2387/* The async FIFO handling thread. */
2388static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2389{
2390 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2391 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2392 int rc;
2393
2394 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2395 return VINF_SUCCESS;
2396
2397 /*
2398 * Special mode where we only execute an external command and the go back
2399 * to being suspended. Currently, all ext cmds ends up here, with the reset
2400 * one also being eligble for runtime execution further down as well.
2401 */
2402 if (pThis->svga.fFifoExtCommandWakeup)
2403 {
2404 vmsvgaR3FifoHandleExtCmd(pThis);
2405 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2406 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
2407 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
2408 else
2409 vmsvgaR3FifoHandleExtCmd(pThis);
2410 return VINF_SUCCESS;
2411 }
2412
2413
2414 /*
2415 * Signal the semaphore to make sure we don't wait for 250 after a
2416 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2417 */
2418 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2419
2420 /*
2421 * Allocate a bounce buffer for command we get from the FIFO.
2422 * (All code must return via the end of the function to free this buffer.)
2423 */
2424 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2425 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2426
2427 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2428 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2429 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2430 {
2431# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2432 /*
2433 * Should service the run loop every so often.
2434 */
2435 if (pThis->svga.f3DEnabled)
2436 vmsvga3dCocoaServiceRunLoop();
2437# endif
2438
2439 /*
2440 * Wait for at most 250 ms to start polling.
2441 */
2442 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, 250);
2443 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2444 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2445 {
2446 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2447 break;
2448 }
2449 if (rc == VERR_TIMEOUT)
2450 {
2451 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2452 continue;
2453 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2454
2455 Log(("vmsvgaFIFOLoop: timeout\n"));
2456 }
2457 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2458 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2459
2460 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2461 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2462 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2463
2464 /*
2465 * Handle external commands (currently only reset).
2466 */
2467 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2468 {
2469 vmsvgaR3FifoHandleExtCmd(pThis);
2470 continue;
2471 }
2472
2473 /*
2474 * The device must be enabled and configured.
2475 */
2476 if ( !pThis->svga.fEnabled
2477 || !pThis->svga.fConfigured)
2478 {
2479 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2480 continue;
2481 }
2482
2483 /*
2484 * Get and check the min/max values. We ASSUME that they will remain
2485 * unchanged while we process requests. A further ASSUMPTION is that
2486 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2487 * we don't read it back while in the loop.
2488 */
2489 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2490 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2491 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2492 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2493 || offFifoMax <= offFifoMin
2494 || offFifoMax > VMSVGA_FIFO_SIZE
2495 || (offFifoMax & 3) != 0
2496 || (offFifoMin & 3) != 0
2497 || offCurrentCmd < offFifoMin
2498 || offCurrentCmd > offFifoMax))
2499 {
2500 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2501 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2502 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2503 continue;
2504 }
2505 if (RT_UNLIKELY(offCurrentCmd & 3))
2506 {
2507 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2508 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2509 offCurrentCmd = ~UINT32_C(3);
2510 }
2511
2512/**
2513 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2514 *
2515 * Will break out of the switch on failure.
2516 * Will restart and quit the loop if the thread was requested to stop.
2517 *
2518 * @param a_cbPayloadReq How much payload to fetch.
2519 * @remarks Access a bunch of variables in the current scope!
2520 */
2521# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2522 if (1) { \
2523 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2524 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2525 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2526 } else do {} while (0)
2527/**
2528 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2529 * buffer after figuring out the actual command size.
2530 * Will break out of the switch on failure.
2531 * @param a_cbPayloadReq How much payload to fetch.
2532 * @remarks Access a bunch of variables in the current scope!
2533 */
2534# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2535 if (1) { \
2536 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2537 } else do {} while (0)
2538
2539 /*
2540 * Mark the FIFO as busy.
2541 */
2542 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2543 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2544 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2545
2546 /*
2547 * Execute all queued FIFO commands.
2548 * Quit if pending external command or changes in the thread state.
2549 */
2550 bool fDone = false;
2551 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
2552 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2553 {
2554 uint32_t cbPayload = 0;
2555 uint32_t u32IrqStatus = 0;
2556 bool fTriggerIrq = false;
2557
2558 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2559
2560 /* First check any pending actions. */
2561 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2562# ifdef VBOX_WITH_VMSVGA3D
2563 vmsvga3dChangeMode(pThis);
2564# else
2565 {/*nothing*/}
2566# endif
2567 /* Check for pending external commands (reset). */
2568 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2569 break;
2570
2571 /*
2572 * Process the command.
2573 */
2574 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2575 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2576 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2577 switch (enmCmdId)
2578 {
2579 case SVGA_CMD_INVALID_CMD:
2580 /* Nothing to do. */
2581 break;
2582
2583 case SVGA_CMD_FENCE:
2584 {
2585 SVGAFifoCmdFence *pCmdFence;
2586 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2587 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2588 {
2589 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2590 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2591
2592 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2593 {
2594 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2595 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2596 }
2597 else
2598 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2599 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2600 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2601 {
2602 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2603 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2604 }
2605 }
2606 else
2607 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2608 break;
2609 }
2610 case SVGA_CMD_UPDATE:
2611 case SVGA_CMD_UPDATE_VERBOSE:
2612 {
2613 SVGAFifoCmdUpdate *pUpdate;
2614 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2615 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2616 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2617 break;
2618 }
2619
2620 case SVGA_CMD_DEFINE_CURSOR:
2621 {
2622 /* Followed by bitmap data. */
2623 SVGAFifoCmdDefineCursor *pCursor;
2624 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2625 AssertFailed(); /** @todo implement when necessary. */
2626 break;
2627 }
2628
2629 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2630 {
2631 /* Followed by bitmap data. */
2632 uint32_t cbCursorShape, cbAndMask;
2633 uint8_t *pCursorCopy;
2634 uint32_t cbCmd;
2635
2636 SVGAFifoCmdDefineAlphaCursor *pCursor;
2637 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2638
2639 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2640
2641 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2642 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2643
2644 /* Refetch the bitmap data as well. */
2645 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2646 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2647 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2648
2649 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2650 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2651 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2652 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2653
2654 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2655 AssertBreak(pCursorCopy);
2656
2657 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2658
2659 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2660 memset(pCursorCopy, 0xff, cbAndMask);
2661 /* Colour data */
2662 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2663
2664 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2665 true,
2666 true,
2667 pCursor->hotspotX,
2668 pCursor->hotspotY,
2669 pCursor->width,
2670 pCursor->height,
2671 pCursorCopy);
2672 AssertRC(rc);
2673
2674 if (pSVGAState->Cursor.fActive)
2675 RTMemFree(pSVGAState->Cursor.pData);
2676
2677 pSVGAState->Cursor.fActive = true;
2678 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2679 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2680 pSVGAState->Cursor.width = pCursor->width;
2681 pSVGAState->Cursor.height = pCursor->height;
2682 pSVGAState->Cursor.cbData = cbCursorShape;
2683 pSVGAState->Cursor.pData = pCursorCopy;
2684 break;
2685 }
2686
2687 case SVGA_CMD_ESCAPE:
2688 {
2689 /* Followed by nsize bytes of data. */
2690 SVGAFifoCmdEscape *pEscape;
2691 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2692
2693 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2694 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2695 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2696 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2697
2698 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2699 {
2700 AssertBreak(pEscape->size >= sizeof(uint32_t));
2701 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2702 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2703
2704 switch (cmd)
2705 {
2706 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2707 {
2708 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2709 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2710 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2711
2712 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2713 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2714 {
2715 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2716 }
2717 break;
2718 }
2719
2720 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2721 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2722 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2723 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2724 break;
2725 }
2726 }
2727 else
2728 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2729
2730 break;
2731 }
2732# ifdef VBOX_WITH_VMSVGA3D
2733 case SVGA_CMD_DEFINE_GMR2:
2734 {
2735 SVGAFifoCmdDefineGMR2 *pCmd;
2736 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2737 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2738
2739 /* Validate current GMR id. */
2740 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2741 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2742
2743 if (!pCmd->numPages)
2744 {
2745 vmsvgaGMRFree(pThis, pCmd->gmrId);
2746 }
2747 else
2748 {
2749 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2750 pGMR->cMaxPages = pCmd->numPages;
2751 }
2752 /* everything done in remap */
2753 break;
2754 }
2755
2756 case SVGA_CMD_REMAP_GMR2:
2757 {
2758 /* Followed by page descriptors or guest ptr. */
2759 SVGAFifoCmdRemapGMR2 *pCmd;
2760 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2761 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2762 uint32_t cbCmd;
2763 uint64_t *paNewPage64 = NULL;
2764
2765 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2766 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2767
2768 /* Calculate the size of what comes after next and fetch it. */
2769 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2770 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2771 cbCmd += sizeof(SVGAGuestPtr);
2772 else
2773 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2774 {
2775 cbCmd += cbPageDesc;
2776 pCmd->numPages = 1;
2777 }
2778 else
2779 {
2780 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2781 cbCmd += cbPageDesc * pCmd->numPages;
2782 }
2783 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2784
2785 /* Validate current GMR id. */
2786 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2787 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2788 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2789 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2790
2791 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2792 if (pGMR->paDesc)
2793 {
2794 uint32_t idxPage = 0;
2795 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2796 AssertBreak(paNewPage64);
2797
2798 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2799 {
2800 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2801 {
2802 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2803 }
2804 }
2805 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2806 }
2807
2808 /* Free the old GMR if present. */
2809 if (pGMR->paDesc)
2810 RTMemFree(pGMR->paDesc);
2811
2812 /* Allocate the maximum amount possible (everything non-continuous) */
2813 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2814 AssertBreak(pGMR->paDesc);
2815
2816 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2817 {
2818 /** @todo */
2819 AssertFailed();
2820 }
2821 else
2822 {
2823 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2824 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2825 uint32_t iDescriptor = 0;
2826 RTGCPHYS GCPhys;
2827 PVMSVGAGMRDESCRIPTOR paDescOld = NULL;
2828 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2829
2830 if (paNewPage64)
2831 {
2832 /* Overwrite the old page array with the new page values. */
2833 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2834 {
2835 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2836 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2837 else
2838 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2839 }
2840 /* Use the updated page array instead of the command data. */
2841 fGCPhys64 = true;
2842 pPage64 = paNewPage64;
2843 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2844 }
2845
2846 if (fGCPhys64)
2847 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2848 else
2849 GCPhys = pPage32[0] << PAGE_SHIFT;
2850
2851 pGMR->paDesc[0].GCPhys = GCPhys;
2852 pGMR->paDesc[0].numPages = 1;
2853 pGMR->cbTotal = PAGE_SIZE;
2854
2855 for (uint32_t i = 1; i < pCmd->numPages; i++)
2856 {
2857 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2858 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2859 else
2860 GCPhys = pPage32[i] << PAGE_SHIFT;
2861
2862 /* Continuous physical memory? */
2863 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2864 {
2865 Assert(pGMR->paDesc[iDescriptor].numPages);
2866 pGMR->paDesc[iDescriptor].numPages++;
2867 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2868 }
2869 else
2870 {
2871 iDescriptor++;
2872 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2873 pGMR->paDesc[iDescriptor].numPages = 1;
2874 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2875 }
2876
2877 pGMR->cbTotal += PAGE_SIZE;
2878 }
2879 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2880 pGMR->numDescriptors = iDescriptor + 1;
2881 }
2882
2883 if (paNewPage64)
2884 RTMemFree(paNewPage64);
2885
2886# ifdef DEBUG_GMR_ACCESS
2887 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2888# endif
2889 break;
2890 }
2891# endif // VBOX_WITH_VMSVGA3D
2892 case SVGA_CMD_DEFINE_SCREEN:
2893 {
2894 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2895 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2896 SVGAFifoCmdDefineScreen *pCmd;
2897 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2898 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2899 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2900
2901 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2902 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2903 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2904 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2905 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2906 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2907 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2908 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2909 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2910 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2911 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2912
2913 /** @todo multi monitor support and screen object capabilities. */
2914 pThis->svga.uWidth = pCmd->screen.size.width;
2915 pThis->svga.uHeight = pCmd->screen.size.height;
2916 vmsvgaChangeMode(pThis);
2917 break;
2918 }
2919
2920 case SVGA_CMD_DESTROY_SCREEN:
2921 {
2922 SVGAFifoCmdDestroyScreen *pCmd;
2923 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
2924
2925 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
2926 break;
2927 }
2928# ifdef VBOX_WITH_VMSVGA3D
2929 case SVGA_CMD_DEFINE_GMRFB:
2930 {
2931 SVGAFifoCmdDefineGMRFB *pCmd;
2932 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
2933
2934 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
2935 pSVGAState->GMRFB.ptr = pCmd->ptr;
2936 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
2937 pSVGAState->GMRFB.format = pCmd->format;
2938 break;
2939 }
2940
2941 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
2942 {
2943 uint32_t width, height;
2944 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
2945 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
2946
2947 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
2948
2949 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
2950 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
2951 AssertBreak(pCmd->destScreenId == 0);
2952
2953 if (pCmd->destRect.left < 0)
2954 pCmd->destRect.left = 0;
2955 if (pCmd->destRect.top < 0)
2956 pCmd->destRect.top = 0;
2957 if (pCmd->destRect.right < 0)
2958 pCmd->destRect.right = 0;
2959 if (pCmd->destRect.bottom < 0)
2960 pCmd->destRect.bottom = 0;
2961
2962 width = pCmd->destRect.right - pCmd->destRect.left;
2963 height = pCmd->destRect.bottom - pCmd->destRect.top;
2964
2965 if ( width == 0
2966 || height == 0)
2967 break; /* Nothing to do. */
2968
2969 /* Clip to screen dimensions. */
2970 if (width > pThis->svga.uWidth)
2971 width = pThis->svga.uWidth;
2972 if (height > pThis->svga.uHeight)
2973 height = pThis->svga.uHeight;
2974
2975 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
2976 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
2977 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
2978
2979 AssertBreak(offsetDest < pThis->vram_size);
2980
2981 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
2982 AssertRC(rc);
2983 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
2984 break;
2985 }
2986
2987 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
2988 {
2989 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
2990 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
2991
2992 /* Note! This can fetch 3d render results as well!! */
2993 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
2994 AssertFailed();
2995 break;
2996 }
2997# endif // VBOX_WITH_VMSVGA3D
2998 case SVGA_CMD_ANNOTATION_FILL:
2999 {
3000 SVGAFifoCmdAnnotationFill *pCmd;
3001 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3002
3003 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3004 pSVGAState->colorAnnotation = pCmd->color;
3005 break;
3006 }
3007
3008 case SVGA_CMD_ANNOTATION_COPY:
3009 {
3010 SVGAFifoCmdAnnotationCopy *pCmd;
3011 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3012
3013 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3014 AssertFailed();
3015 break;
3016 }
3017
3018 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3019
3020 default:
3021# ifdef VBOX_WITH_VMSVGA3D
3022 if ( enmCmdId >= SVGA_3D_CMD_BASE
3023 && enmCmdId < SVGA_3D_CMD_MAX)
3024 {
3025 /* All 3d commands start with a common header, which defines the size of the command. */
3026 SVGA3dCmdHeader *pHdr;
3027 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3028 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
3029 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3030 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3031
3032/**
3033 * Check that the 3D command has at least a_cbMin of payload bytes after the
3034 * header. Will break out of the switch if it doesn't.
3035 */
3036# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3037 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3038 switch ((int)enmCmdId)
3039 {
3040 case SVGA_3D_CMD_SURFACE_DEFINE:
3041 {
3042 uint32_t cMipLevels;
3043 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
3044 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3045
3046 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3047 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3048 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3049# ifdef DEBUG_GMR_ACCESS
3050 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3051# endif
3052 break;
3053 }
3054
3055 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3056 {
3057 uint32_t cMipLevels;
3058 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
3059 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3060
3061 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3062 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3063 pCmd->multisampleCount, pCmd->autogenFilter,
3064 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3065 break;
3066 }
3067
3068 case SVGA_3D_CMD_SURFACE_DESTROY:
3069 {
3070 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
3071 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3072 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3073 break;
3074 }
3075
3076 case SVGA_3D_CMD_SURFACE_COPY:
3077 {
3078 uint32_t cCopyBoxes;
3079 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
3080 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3081
3082 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3083 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3084 break;
3085 }
3086
3087 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3088 {
3089 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
3090 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3091
3092 rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3093 break;
3094 }
3095
3096 case SVGA_3D_CMD_SURFACE_DMA:
3097 {
3098 uint32_t cCopyBoxes;
3099 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
3100 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3101
3102 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3103 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
3104 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3105 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3106 break;
3107 }
3108
3109 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3110 {
3111 uint32_t cRects;
3112 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
3113 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3114
3115 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3116 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3117 break;
3118 }
3119
3120 case SVGA_3D_CMD_CONTEXT_DEFINE:
3121 {
3122 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
3123 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3124
3125 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3126 break;
3127 }
3128
3129 case SVGA_3D_CMD_CONTEXT_DESTROY:
3130 {
3131 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
3132 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3133
3134 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3135 break;
3136 }
3137
3138 case SVGA_3D_CMD_SETTRANSFORM:
3139 {
3140 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
3141 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3142
3143 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3144 break;
3145 }
3146
3147 case SVGA_3D_CMD_SETZRANGE:
3148 {
3149 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
3150 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3151
3152 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3153 break;
3154 }
3155
3156 case SVGA_3D_CMD_SETRENDERSTATE:
3157 {
3158 uint32_t cRenderStates;
3159 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3160 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3161
3162 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3163 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3164 break;
3165 }
3166
3167 case SVGA_3D_CMD_SETRENDERTARGET:
3168 {
3169 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3170 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3171
3172 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3173 break;
3174 }
3175
3176 case SVGA_3D_CMD_SETTEXTURESTATE:
3177 {
3178 uint32_t cTextureStates;
3179 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3180 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3181
3182 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3183 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3184 break;
3185 }
3186
3187 case SVGA_3D_CMD_SETMATERIAL:
3188 {
3189 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3191
3192 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3193 break;
3194 }
3195
3196 case SVGA_3D_CMD_SETLIGHTDATA:
3197 {
3198 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3199 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3200
3201 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3202 break;
3203 }
3204
3205 case SVGA_3D_CMD_SETLIGHTENABLED:
3206 {
3207 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3208 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3209
3210 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3211 break;
3212 }
3213
3214 case SVGA_3D_CMD_SETVIEWPORT:
3215 {
3216 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3217 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3218
3219 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3220 break;
3221 }
3222
3223 case SVGA_3D_CMD_SETCLIPPLANE:
3224 {
3225 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3226 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3227
3228 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3229 break;
3230 }
3231
3232 case SVGA_3D_CMD_CLEAR:
3233 {
3234 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3235 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3236 uint32_t cRects;
3237
3238 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3239 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3240 break;
3241 }
3242
3243 case SVGA_3D_CMD_PRESENT:
3244 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3245 {
3246 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3247 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3248 uint32_t cRects;
3249
3250 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3251
3252 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3253 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3254 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3255 break;
3256 }
3257
3258 case SVGA_3D_CMD_SHADER_DEFINE:
3259 {
3260 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3261 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3262 uint32_t cbData;
3263
3264 cbData = (pHdr->size - sizeof(*pCmd));
3265 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3266 break;
3267 }
3268
3269 case SVGA_3D_CMD_SHADER_DESTROY:
3270 {
3271 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3272 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3273
3274 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3275 break;
3276 }
3277
3278 case SVGA_3D_CMD_SET_SHADER:
3279 {
3280 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3281 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3282
3283 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3284 break;
3285 }
3286
3287 case SVGA_3D_CMD_SET_SHADER_CONST:
3288 {
3289 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3290 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3291
3292 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3293 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3294 break;
3295 }
3296
3297 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3298 {
3299 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3300 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3301 uint32_t cVertexDivisor;
3302
3303 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3304 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3305 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3306 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3307
3308 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3309 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3310 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3311
3312 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3313 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3314 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3315 break;
3316 }
3317
3318 case SVGA_3D_CMD_SETSCISSORRECT:
3319 {
3320 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3321 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3322
3323 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3324 break;
3325 }
3326
3327 case SVGA_3D_CMD_BEGIN_QUERY:
3328 {
3329 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3330 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3331
3332 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3333 break;
3334 }
3335
3336 case SVGA_3D_CMD_END_QUERY:
3337 {
3338 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3339 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3340
3341 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3342 break;
3343 }
3344
3345 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3346 {
3347 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3348 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3349
3350 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3351 break;
3352 }
3353
3354 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3355 {
3356 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3357 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3358
3359 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3360 break;
3361 }
3362
3363 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3364 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3365 /* context id + surface id? */
3366 break;
3367
3368 default:
3369 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3370 AssertFailed();
3371 break;
3372 }
3373 }
3374 else
3375# endif // VBOX_WITH_VMSVGA3D
3376 {
3377 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3378 AssertFailed();
3379 }
3380 }
3381
3382 /* Go to the next slot */
3383 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3384 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3385 if (offCurrentCmd >= offFifoMax)
3386 {
3387 offCurrentCmd -= offFifoMax - offFifoMin;
3388 Assert(offCurrentCmd >= offFifoMin);
3389 Assert(offCurrentCmd < offFifoMax);
3390 }
3391 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3392 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3393
3394 /*
3395 * Raise IRQ if required. Must enter the critical section here
3396 * before making final decisions here, otherwise cubebench and
3397 * others may end up waiting forever.
3398 */
3399 if ( u32IrqStatus
3400 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3401 {
3402 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3403
3404 /* FIFO progress might trigger an interrupt. */
3405 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3406 {
3407 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3408 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3409 }
3410
3411 /* Unmasked IRQ pending? */
3412 if (pThis->svga.u32IrqMask & u32IrqStatus)
3413 {
3414 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3415 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3416 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3417 }
3418
3419 PDMCritSectLeave(&pThis->CritSect);
3420 }
3421 }
3422
3423 /* If really done, clear the busy flag. */
3424 if (fDone)
3425 {
3426 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3427 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3428 }
3429 }
3430
3431 /*
3432 * Free the bounce buffer. (There are no returns above!)
3433 */
3434 RTMemFree(pbBounceBuf);
3435
3436 return VINF_SUCCESS;
3437}
3438
3439/**
3440 * Free the specified GMR
3441 *
3442 * @param pThis VGA device instance data.
3443 * @param idGMR GMR id
3444 */
3445void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3446{
3447 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3448
3449 /* Free the old descriptor if present. */
3450 if (pSVGAState->aGMR[idGMR].numDescriptors)
3451 {
3452 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3453# ifdef DEBUG_GMR_ACCESS
3454 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3455# endif
3456
3457 Assert(pGMR->paDesc);
3458 RTMemFree(pGMR->paDesc);
3459 pGMR->paDesc = NULL;
3460 pGMR->numDescriptors = 0;
3461 pGMR->cbTotal = 0;
3462 pGMR->cMaxPages = 0;
3463 }
3464 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3465}
3466
3467/**
3468 * Copy from a GMR to host memory or vice versa
3469 *
3470 * @returns VBox status code.
3471 * @param pThis VGA device instance data.
3472 * @param enmTransferType Transfer type (read/write)
3473 * @param pbDst Host destination pointer
3474 * @param cbDestPitch Destination buffer pitch
3475 * @param src GMR description
3476 * @param offSrc Source buffer offset
3477 * @param cbSrcPitch Source buffer pitch
3478 * @param cbWidth Source width in bytes
3479 * @param cHeight Source height
3480 */
3481int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3482 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3483{
3484 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3485 PGMR pGMR;
3486 int rc;
3487 PVMSVGAGMRDESCRIPTOR pDesc;
3488 unsigned offDesc = 0;
3489
3490 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3491 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3492 Assert(cbWidth && cHeight);
3493
3494 /* Shortcut for the framebuffer. */
3495 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3496 {
3497 offSrc += src.offset;
3498 AssertMsgReturn(src.offset < pThis->vram_size,
3499 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3500 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3501 VERR_INVALID_PARAMETER);
3502 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3503 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3504 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3505 VERR_INVALID_PARAMETER);
3506
3507 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3508
3509 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3510 {
3511 /* switch src & dest */
3512 uint8_t *pTemp = pbDst;
3513 int32_t cbTempPitch = cbDestPitch;
3514
3515 pbDst = pSrc;
3516 pSrc = pTemp;
3517
3518 cbDestPitch = cbSrcPitch;
3519 cbSrcPitch = cbTempPitch;
3520 }
3521
3522 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3523 && cbWidth == (uint32_t)cbDestPitch
3524 && cbSrcPitch == cbDestPitch)
3525 {
3526 memcpy(pbDst, pSrc, cbWidth * cHeight);
3527 }
3528 else
3529 {
3530 for(uint32_t i = 0; i < cHeight; i++)
3531 {
3532 memcpy(pbDst, pSrc, cbWidth);
3533
3534 pbDst += cbDestPitch;
3535 pSrc += cbSrcPitch;
3536 }
3537 }
3538 return VINF_SUCCESS;
3539 }
3540
3541 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3542 pGMR = &pSVGAState->aGMR[src.gmrId];
3543 pDesc = pGMR->paDesc;
3544
3545 offSrc += src.offset;
3546 AssertMsgReturn(src.offset < pGMR->cbTotal,
3547 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3548 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3549 VERR_INVALID_PARAMETER);
3550 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3551 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3552 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3553 VERR_INVALID_PARAMETER);
3554
3555 for (uint32_t i = 0; i < cHeight; i++)
3556 {
3557 uint32_t cbCurrentWidth = cbWidth;
3558 uint32_t offCurrent = offSrc;
3559 uint8_t *pCurrentDest = pbDst;
3560
3561 /* Find the right descriptor */
3562 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3563 {
3564 offDesc += pDesc->numPages * PAGE_SIZE;
3565 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3566 pDesc++;
3567 }
3568
3569 while (cbCurrentWidth)
3570 {
3571 uint32_t cbToCopy;
3572
3573 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3574 {
3575 cbToCopy = cbCurrentWidth;
3576 }
3577 else
3578 {
3579 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3580 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3581 }
3582
3583 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3584
3585 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3586 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3587 else
3588 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3589 AssertRCBreak(rc);
3590
3591 cbCurrentWidth -= cbToCopy;
3592 offCurrent += cbToCopy;
3593 pCurrentDest += cbToCopy;
3594
3595 /* Go to the next descriptor if there's anything left. */
3596 if (cbCurrentWidth)
3597 {
3598 offDesc += pDesc->numPages * PAGE_SIZE;
3599 pDesc++;
3600 }
3601 }
3602
3603 offSrc += cbSrcPitch;
3604 pbDst += cbDestPitch;
3605 }
3606
3607 return VINF_SUCCESS;
3608}
3609
3610/**
3611 * Unblock the FIFO I/O thread so it can respond to a state change.
3612 *
3613 * @returns VBox status code.
3614 * @param pDevIns The VGA device instance.
3615 * @param pThread The send thread.
3616 */
3617static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3618{
3619 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3620 Log(("vmsvgaFIFOLoopWakeUp\n"));
3621 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3622}
3623
3624/**
3625 * Enables or disables dirty page tracking for the framebuffer
3626 *
3627 * @param pThis VGA device instance data.
3628 * @param fTraces Enable/disable traces
3629 */
3630static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3631{
3632 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3633 && !fTraces)
3634 {
3635 //Assert(pThis->svga.fTraces);
3636 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3637 return;
3638 }
3639
3640 pThis->svga.fTraces = fTraces;
3641 if (pThis->svga.fTraces)
3642 {
3643 unsigned cbFrameBuffer = pThis->vram_size;
3644
3645 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3646 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3647 {
3648#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
3649 Assert(pThis->svga.cbScanline);
3650#endif
3651 /* Hardware enabled; return real framebuffer size .*/
3652 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3653 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3654 }
3655
3656 if (!pThis->svga.fVRAMTracking)
3657 {
3658 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3659 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3660 pThis->svga.fVRAMTracking = true;
3661 }
3662 }
3663 else
3664 {
3665 if (pThis->svga.fVRAMTracking)
3666 {
3667 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3668 vgaR3UnregisterVRAMHandler(pThis);
3669 pThis->svga.fVRAMTracking = false;
3670 }
3671 }
3672}
3673
3674/**
3675 * Callback function for mapping a PCI I/O region.
3676 *
3677 * @return VBox status code.
3678 * @param pPciDev Pointer to PCI device.
3679 * Use pPciDev->pDevIns to get the device instance.
3680 * @param iRegion The region number.
3681 * @param GCPhysAddress Physical address of the region.
3682 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3683 * I/O port, else it's a physical address.
3684 * This address is *NOT* relative
3685 * to pci_mem_base like earlier!
3686 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3687 */
3688DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3689{
3690 int rc;
3691 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3692 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3693
3694 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3695 if (enmType == PCI_ADDRESS_SPACE_IO)
3696 {
3697 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3698 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3699 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3700 if (RT_FAILURE(rc))
3701 return rc;
3702 if (pThis->fR0Enabled)
3703 {
3704 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3705 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3706 if (RT_FAILURE(rc))
3707 return rc;
3708 }
3709 if (pThis->fGCEnabled)
3710 {
3711 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3712 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3713 if (RT_FAILURE(rc))
3714 return rc;
3715 }
3716
3717 pThis->svga.BasePort = GCPhysAddress;
3718 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3719 }
3720 else
3721 {
3722 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3723 if (GCPhysAddress != NIL_RTGCPHYS)
3724 {
3725 /*
3726 * Mapping the FIFO RAM.
3727 */
3728 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3729 AssertRC(rc);
3730
3731# ifdef DEBUG_FIFO_ACCESS
3732 if (RT_SUCCESS(rc))
3733 {
3734 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3735 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3736 "VMSVGA FIFO");
3737 AssertRC(rc);
3738 }
3739# endif
3740 if (RT_SUCCESS(rc))
3741 {
3742 pThis->svga.GCPhysFIFO = GCPhysAddress;
3743 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3744 }
3745 }
3746 else
3747 {
3748 Assert(pThis->svga.GCPhysFIFO);
3749# ifdef DEBUG_FIFO_ACCESS
3750 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3751 AssertRC(rc);
3752# endif
3753 pThis->svga.GCPhysFIFO = 0;
3754 }
3755
3756 }
3757 return VINF_SUCCESS;
3758}
3759
3760# ifdef VBOX_WITH_VMSVGA3D
3761
3762/**
3763 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
3764 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
3765 *
3766 * @param pThis The VGA device instance data.
3767 * @param sid Either UINT32_MAX or the ID of a specific
3768 * surface. If UINT32_MAX is used, all surfaces
3769 * are processed.
3770 */
3771void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
3772{
3773 vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
3774 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
3775}
3776
3777
3778/**
3779 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
3780 */
3781DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3782{
3783 /* There might be a specific context ID at the start of the
3784 arguments, if not show all contexts. */
3785 uint32_t cid = UINT32_MAX;
3786 if (pszArgs)
3787 pszArgs = RTStrStripL(pszArgs);
3788 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3789 cid = RTStrToUInt32(pszArgs);
3790
3791 /* Verbose or terse display, we default to verbose. */
3792 bool fVerbose = true;
3793 if (RTStrIStr(pszArgs, "terse"))
3794 fVerbose = false;
3795
3796 /* The size of the ascii art (x direction, y is 3/4 of x). */
3797 uint32_t cxAscii = 80;
3798 if (RTStrIStr(pszArgs, "gigantic"))
3799 cxAscii = 300;
3800 else if (RTStrIStr(pszArgs, "huge"))
3801 cxAscii = 180;
3802 else if (RTStrIStr(pszArgs, "big"))
3803 cxAscii = 132;
3804 else if (RTStrIStr(pszArgs, "normal"))
3805 cxAscii = 80;
3806 else if (RTStrIStr(pszArgs, "medium"))
3807 cxAscii = 64;
3808 else if (RTStrIStr(pszArgs, "small"))
3809 cxAscii = 48;
3810 else if (RTStrIStr(pszArgs, "tiny"))
3811 cxAscii = 24;
3812
3813 /* Y invert the image when producing the ASCII art. */
3814 bool fInvY = false;
3815 if (RTStrIStr(pszArgs, "invy"))
3816 fInvY = true;
3817
3818 vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
3819}
3820
3821
3822/**
3823 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
3824 */
3825DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3826{
3827 /* There might be a specific surface ID at the start of the
3828 arguments, if not show all contexts. */
3829 uint32_t sid = UINT32_MAX;
3830 if (pszArgs)
3831 pszArgs = RTStrStripL(pszArgs);
3832 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3833 sid = RTStrToUInt32(pszArgs);
3834
3835 /* Verbose or terse display, we default to verbose. */
3836 bool fVerbose = true;
3837 if (RTStrIStr(pszArgs, "terse"))
3838 fVerbose = false;
3839
3840 vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
3841}
3842
3843# endif /* VBOX_WITH_VMSVGA3D */
3844
3845/**
3846 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
3847 */
3848static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3849{
3850 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3851 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3852
3853 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
3854 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
3855 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
3856 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
3857 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
3858 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
3859 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
3860 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
3861 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
3862 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
3863 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
3864 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
3865 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
3866 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
3867 pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
3868 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
3869 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
3870 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
3871 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
3872 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
3873 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
3874 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
3875
3876 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
3877 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
3878 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
3879 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
3880
3881# ifdef VBOX_WITH_VMSVGA3D
3882 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
3883 pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
3884 if (pThis->svga.u64HostWindowId != 0)
3885 vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
3886# endif
3887}
3888
3889
3890/**
3891 * @copydoc FNSSMDEVLOADEXEC
3892 */
3893int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3894{
3895 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3896 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3897 int rc;
3898
3899 /* Load our part of the VGAState */
3900 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3901 AssertRCReturn(rc, rc);
3902
3903 /* Load the framebuffer backup. */
3904 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3905 AssertRCReturn(rc, rc);
3906
3907 /* Load the VMSVGA state. */
3908 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
3909 AssertRCReturn(rc, rc);
3910
3911 /* Load the active cursor bitmaps. */
3912 if (pSVGAState->Cursor.fActive)
3913 {
3914 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3915 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3916
3917 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3918 AssertRCReturn(rc, rc);
3919 }
3920
3921 /* Load the GMR state */
3922 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3923 {
3924 PGMR pGMR = &pSVGAState->aGMR[i];
3925
3926 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
3927 AssertRCReturn(rc, rc);
3928
3929 if (pGMR->numDescriptors)
3930 {
3931 /* Allocate the maximum amount possible (everything non-continuous) */
3932 Assert(pGMR->cMaxPages || pGMR->cbTotal);
3933 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
3934 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
3935
3936 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3937 {
3938 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3939 AssertRCReturn(rc, rc);
3940 }
3941 }
3942 }
3943
3944# ifdef VBOX_WITH_VMSVGA3D
3945 if (pThis->svga.f3DEnabled)
3946 {
3947# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
3948 vmsvga3dPowerOn(pThis);
3949# endif
3950
3951 VMSVGA_STATE_LOAD LoadState;
3952 LoadState.pSSM = pSSM;
3953 LoadState.uVersion = uVersion;
3954 LoadState.uPass = uPass;
3955 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
3956 AssertLogRelRCReturn(rc, rc);
3957 }
3958# endif
3959
3960 return VINF_SUCCESS;
3961}
3962
3963/**
3964 * Reinit the video mode after the state has been loaded.
3965 */
3966int vmsvgaLoadDone(PPDMDEVINS pDevIns)
3967{
3968 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3969 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3970
3971 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
3972 vmsvgaChangeMode(pThis);
3973
3974 /* Set the active cursor. */
3975 if (pSVGAState->Cursor.fActive)
3976 {
3977 int rc;
3978
3979 rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
3980 true,
3981 true,
3982 pSVGAState->Cursor.xHotspot,
3983 pSVGAState->Cursor.yHotspot,
3984 pSVGAState->Cursor.width,
3985 pSVGAState->Cursor.height,
3986 pSVGAState->Cursor.pData);
3987 AssertRC(rc);
3988 }
3989 return VINF_SUCCESS;
3990}
3991
3992/**
3993 * @copydoc FNSSMDEVSAVEEXEC
3994 */
3995int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3996{
3997 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3998 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3999 int rc;
4000
4001 /* Save our part of the VGAState */
4002 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4003 AssertLogRelRCReturn(rc, rc);
4004
4005 /* Save the framebuffer backup. */
4006 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4007 AssertLogRelRCReturn(rc, rc);
4008
4009 /* Save the VMSVGA state. */
4010 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4011 AssertLogRelRCReturn(rc, rc);
4012
4013 /* Save the active cursor bitmaps. */
4014 if (pSVGAState->Cursor.fActive)
4015 {
4016 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4017 AssertLogRelRCReturn(rc, rc);
4018 }
4019
4020 /* Save the GMR state */
4021 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4022 {
4023 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4024 AssertLogRelRCReturn(rc, rc);
4025
4026 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4027 {
4028 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4029 AssertLogRelRCReturn(rc, rc);
4030 }
4031 }
4032
4033# ifdef VBOX_WITH_VMSVGA3D
4034 /*
4035 * Must save the 3d state in the FIFO thread.
4036 */
4037 if (pThis->svga.f3DEnabled)
4038 {
4039 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4040 AssertLogRelRCReturn(rc, rc);
4041 }
4042# endif
4043 return VINF_SUCCESS;
4044}
4045
4046/**
4047 * Resets the SVGA hardware state
4048 *
4049 * @returns VBox status code.
4050 * @param pDevIns The device instance.
4051 */
4052int vmsvgaReset(PPDMDEVINS pDevIns)
4053{
4054 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4055 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4056
4057 /* Reset before init? */
4058 if (!pSVGAState)
4059 return VINF_SUCCESS;
4060
4061 Log(("vmsvgaReset\n"));
4062
4063
4064 /* Reset the FIFO processing as well as the 3d state (if we have one). */
4065 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4066 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
4067
4068 /* Reset other stuff. */
4069 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4070 RT_ZERO(pThis->svga.au32ScratchRegion);
4071 RT_ZERO(*pThis->svga.pSvgaR3State);
4072 RT_BZERO(pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4073
4074 /* Register caps. */
4075 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4076# ifdef VBOX_WITH_VMSVGA3D
4077 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4078# endif
4079
4080 /* Setup FIFO capabilities. */
4081 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4082
4083 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4084 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4085
4086 /* VRAM tracking is enabled by default during bootup. */
4087 pThis->svga.fVRAMTracking = true;
4088 pThis->svga.fEnabled = false;
4089
4090 /* Invalidate current settings. */
4091 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4092 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4093 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4094 pThis->svga.cbScanline = 0;
4095
4096 return rc;
4097}
4098
4099/**
4100 * Cleans up the SVGA hardware state
4101 *
4102 * @returns VBox status code.
4103 * @param pDevIns The device instance.
4104 */
4105int vmsvgaDestruct(PPDMDEVINS pDevIns)
4106{
4107 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4108
4109 /*
4110 * Ask the FIFO thread to terminate the 3d state and then terminate it.
4111 */
4112 if (pThis->svga.pFIFOIOThread)
4113 {
4114 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /*pvParam*/, 30000 /*ms*/);
4115 AssertLogRelRC(rc);
4116
4117 rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4118 AssertLogRelRC(rc);
4119 pThis->svga.pFIFOIOThread = NULL;
4120 }
4121
4122 /*
4123 * Destroy the special SVGA state.
4124 */
4125 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4126 if (pSVGAState)
4127 {
4128# ifndef VMSVGA_USE_EMT_HALT_CODE
4129 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4130 {
4131 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4132 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4133 }
4134# endif
4135 if (pSVGAState->Cursor.fActive)
4136 RTMemFree(pSVGAState->Cursor.pData);
4137
4138 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4139 if (pSVGAState->aGMR[i].paDesc)
4140 RTMemFree(pSVGAState->aGMR[i].paDesc);
4141
4142 RTMemFree(pSVGAState);
4143 pThis->svga.pSvgaR3State = NULL;
4144 }
4145
4146 /*
4147 * Free our resources residing in the VGA state.
4148 */
4149 if (pThis->svga.pFrameBufferBackup)
4150 RTMemFree(pThis->svga.pFrameBufferBackup);
4151 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4152 {
4153 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4154 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4155 }
4156 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4157 {
4158 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4159 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4160 }
4161
4162 return VINF_SUCCESS;
4163}
4164
4165/**
4166 * Initialize the SVGA hardware state
4167 *
4168 * @returns VBox status code.
4169 * @param pDevIns The device instance.
4170 */
4171int vmsvgaInit(PPDMDEVINS pDevIns)
4172{
4173 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4174 PVMSVGAR3STATE pSVGAState;
4175 PVM pVM = PDMDevHlpGetVM(pDevIns);
4176 int rc;
4177
4178 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4179 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4180
4181 pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4182 AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4183 pSVGAState = pThis->svga.pSvgaR3State;
4184
4185 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4186 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4187 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
4188
4189 /* Create event semaphore. */
4190 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4191
4192 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4193 if (RT_FAILURE(rc))
4194 {
4195 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4196 return rc;
4197 }
4198
4199 /* Create event semaphore. */
4200 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4201 if (RT_FAILURE(rc))
4202 {
4203 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4204 return rc;
4205 }
4206
4207# ifndef VMSVGA_USE_EMT_HALT_CODE
4208 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4209 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4210 AssertRCReturn(rc, rc);
4211# endif
4212
4213 /* Register caps. */
4214 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4215# ifdef VBOX_WITH_VMSVGA3D
4216 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4217# endif
4218
4219 /* Setup FIFO capabilities. */
4220 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4221
4222 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4223 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4224
4225 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4226# ifdef VBOX_WITH_VMSVGA3D
4227 if (pThis->svga.f3DEnabled)
4228 {
4229 rc = vmsvga3dInit(pThis);
4230 if (RT_FAILURE(rc))
4231 {
4232 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4233 pThis->svga.f3DEnabled = false;
4234 }
4235 }
4236# endif
4237 /* VRAM tracking is enabled by default during bootup. */
4238 pThis->svga.fVRAMTracking = true;
4239
4240 /* Invalidate current settings. */
4241 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4242 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4243 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4244 pThis->svga.cbScanline = 0;
4245
4246 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
4247 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
4248 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
4249 {
4250 pThis->svga.u32MaxWidth -= 256;
4251 pThis->svga.u32MaxHeight -= 256;
4252 }
4253 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
4254
4255# ifdef DEBUG_GMR_ACCESS
4256 /* Register the GMR access handler type. */
4257 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
4258 vmsvgaR3GMRAccessHandler,
4259 NULL, NULL, NULL,
4260 NULL, NULL, NULL,
4261 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
4262 AssertRCReturn(rc, rc);
4263# endif
4264# ifdef DEBUG_FIFO_ACCESS
4265 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
4266 vmsvgaR3FIFOAccessHandler,
4267 NULL, NULL, NULL,
4268 NULL, NULL, NULL,
4269 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
4270 AssertRCReturn(rc, rc);
4271#endif
4272
4273 /* Create the async IO thread. */
4274 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
4275 RTTHREADTYPE_IO, "VMSVGA FIFO");
4276 if (RT_FAILURE(rc))
4277 {
4278 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
4279 return rc;
4280 }
4281
4282 /*
4283 * Statistics.
4284 */
4285 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4286 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4287 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4288 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4289 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4290 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4291 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4292 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4293 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4294 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4295
4296 /*
4297 * Info handlers.
4298 */
4299 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
4300# ifdef VBOX_WITH_VMSVGA3D
4301 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
4302 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
4303 "VMSVGA 3d surface details. "
4304 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
4305 vmsvgaR3Info3dSurface);
4306# endif
4307
4308 return VINF_SUCCESS;
4309}
4310
4311# ifdef VBOX_WITH_VMSVGA3D
4312/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4313static const char * const g_apszVmSvgaDevCapNames[] =
4314{
4315 "x3D", /* = 0 */
4316 "xMAX_LIGHTS",
4317 "xMAX_TEXTURES",
4318 "xMAX_CLIP_PLANES",
4319 "xVERTEX_SHADER_VERSION",
4320 "xVERTEX_SHADER",
4321 "xFRAGMENT_SHADER_VERSION",
4322 "xFRAGMENT_SHADER",
4323 "xMAX_RENDER_TARGETS",
4324 "xS23E8_TEXTURES",
4325 "xS10E5_TEXTURES",
4326 "xMAX_FIXED_VERTEXBLEND",
4327 "xD16_BUFFER_FORMAT",
4328 "xD24S8_BUFFER_FORMAT",
4329 "xD24X8_BUFFER_FORMAT",
4330 "xQUERY_TYPES",
4331 "xTEXTURE_GRADIENT_SAMPLING",
4332 "rMAX_POINT_SIZE",
4333 "xMAX_SHADER_TEXTURES",
4334 "xMAX_TEXTURE_WIDTH",
4335 "xMAX_TEXTURE_HEIGHT",
4336 "xMAX_VOLUME_EXTENT",
4337 "xMAX_TEXTURE_REPEAT",
4338 "xMAX_TEXTURE_ASPECT_RATIO",
4339 "xMAX_TEXTURE_ANISOTROPY",
4340 "xMAX_PRIMITIVE_COUNT",
4341 "xMAX_VERTEX_INDEX",
4342 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4343 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4344 "xMAX_VERTEX_SHADER_TEMPS",
4345 "xMAX_FRAGMENT_SHADER_TEMPS",
4346 "xTEXTURE_OPS",
4347 "xSURFACEFMT_X8R8G8B8",
4348 "xSURFACEFMT_A8R8G8B8",
4349 "xSURFACEFMT_A2R10G10B10",
4350 "xSURFACEFMT_X1R5G5B5",
4351 "xSURFACEFMT_A1R5G5B5",
4352 "xSURFACEFMT_A4R4G4B4",
4353 "xSURFACEFMT_R5G6B5",
4354 "xSURFACEFMT_LUMINANCE16",
4355 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4356 "xSURFACEFMT_ALPHA8",
4357 "xSURFACEFMT_LUMINANCE8",
4358 "xSURFACEFMT_Z_D16",
4359 "xSURFACEFMT_Z_D24S8",
4360 "xSURFACEFMT_Z_D24X8",
4361 "xSURFACEFMT_DXT1",
4362 "xSURFACEFMT_DXT2",
4363 "xSURFACEFMT_DXT3",
4364 "xSURFACEFMT_DXT4",
4365 "xSURFACEFMT_DXT5",
4366 "xSURFACEFMT_BUMPX8L8V8U8",
4367 "xSURFACEFMT_A2W10V10U10",
4368 "xSURFACEFMT_BUMPU8V8",
4369 "xSURFACEFMT_Q8W8V8U8",
4370 "xSURFACEFMT_CxV8U8",
4371 "xSURFACEFMT_R_S10E5",
4372 "xSURFACEFMT_R_S23E8",
4373 "xSURFACEFMT_RG_S10E5",
4374 "xSURFACEFMT_RG_S23E8",
4375 "xSURFACEFMT_ARGB_S10E5",
4376 "xSURFACEFMT_ARGB_S23E8",
4377 "xMISSING62",
4378 "xMAX_VERTEX_SHADER_TEXTURES",
4379 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4380 "xSURFACEFMT_V16U16",
4381 "xSURFACEFMT_G16R16",
4382 "xSURFACEFMT_A16B16G16R16",
4383 "xSURFACEFMT_UYVY",
4384 "xSURFACEFMT_YUY2",
4385 "xMULTISAMPLE_NONMASKABLESAMPLES",
4386 "xMULTISAMPLE_MASKABLESAMPLES",
4387 "xALPHATOCOVERAGE",
4388 "xSUPERSAMPLE",
4389 "xAUTOGENMIPMAPS",
4390 "xSURFACEFMT_NV12",
4391 "xSURFACEFMT_AYUV",
4392 "xMAX_CONTEXT_IDS",
4393 "xMAX_SURFACE_IDS",
4394 "xSURFACEFMT_Z_DF16",
4395 "xSURFACEFMT_Z_DF24",
4396 "xSURFACEFMT_Z_D24S8_INT",
4397 "xSURFACEFMT_BC4_UNORM",
4398 "xSURFACEFMT_BC5_UNORM", /* 83 */
4399};
4400# endif
4401
4402
4403/**
4404 * Power On notification.
4405 *
4406 * @returns VBox status.
4407 * @param pDevIns The device instance data.
4408 *
4409 * @remarks Caller enters the device critical section.
4410 */
4411DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4412{
4413 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4414 int rc;
4415
4416# ifdef VBOX_WITH_VMSVGA3D
4417 if (pThis->svga.f3DEnabled)
4418 {
4419 rc = vmsvga3dPowerOn(pThis);
4420
4421 if (RT_SUCCESS(rc))
4422 {
4423 bool fSavedBuffering = RTLogRelSetBuffering(true);
4424 SVGA3dCapsRecord *pCaps;
4425 SVGA3dCapPair *pData;
4426 uint32_t idxCap = 0;
4427
4428 /* 3d hardware version; latest and greatest */
4429 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4430 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4431
4432 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4433 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4434 pData = (SVGA3dCapPair *)&pCaps->data;
4435
4436 /* Fill out all 3d capabilities. */
4437 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4438 {
4439 uint32_t val = 0;
4440
4441 rc = vmsvga3dQueryCaps(pThis, i, &val);
4442 if (RT_SUCCESS(rc))
4443 {
4444 pData[idxCap][0] = i;
4445 pData[idxCap][1] = val;
4446 idxCap++;
4447 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4448 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4449 else
4450 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4451 &g_apszVmSvgaDevCapNames[i][1]));
4452 }
4453 else
4454 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4455 }
4456 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4457 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4458
4459 /* Mark end of record array. */
4460 pCaps->header.length = 0;
4461
4462 RTLogRelSetBuffering(fSavedBuffering);
4463 }
4464 }
4465# endif // VBOX_WITH_VMSVGA3D
4466}
4467
4468#endif /* IN_RING3 */
4469
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