VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 95055

最後變更 在這個檔案從95055是 95055,由 vboxsync 提交於 3 年 前

Devices/Graphics: stream output; ClearView; typeless formats: bugref:9830
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 274.7 KB
行 
1/* $Id: DevVGA-SVGA-cmd.cpp 95055 2022-05-21 10:32:50Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#include <iprt/formats/bmp.h>
40#include <stdio.h>
41
42#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
43# define SVGA_CASE_ID2STR(idx) case idx: return #idx
44
45static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
46{
47 switch (enmCmdId)
48 {
49 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
50 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION); /* SVGA_3D_CMD_DEAD1 */
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
290 }
291 return "UNKNOWN_3D";
292}
293
294/**
295 * FIFO command name lookup
296 *
297 * @returns FIFO command string or "UNKNOWN"
298 * @param u32Cmd FIFO command
299 */
300const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
301{
302 switch (u32Cmd)
303 {
304 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
305 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
306 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
307 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
309 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
310 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
311 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
314 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
315 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
316 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
317 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
318 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
320 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
323 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
324 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
325 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
327 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
328 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
329 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
330 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
331 default:
332 if ( u32Cmd >= SVGA_3D_CMD_BASE
333 && u32Cmd < SVGA_3D_CMD_MAX)
334 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
335 }
336 return "UNKNOWN";
337}
338# undef SVGA_CASE_ID2STR
339#endif /* LOG_ENABLED || VBOX_STRICT */
340
341
342/*
343 *
344 * Guest-Backed Objects (GBO).
345 *
346 */
347
348/**
349 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
350 *
351 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
352 * @param pVM VM Handle.
353 * @param pVCpu The cross context CPU structure for the calling EMT.
354 * @param GCPhys The physical address the guest is writing to.
355 * @param pvPhys The HC mapping of that address.
356 * @param pvBuf What the guest is reading/writing.
357 * @param cbBuf How much it's reading/writing.
358 * @param enmAccessType The access type.
359 * @param enmOrigin Who is making the access.
360 * @param uUser The VMM automatically sets this to the address of
361 * the device instance.
362 */
363DECLCALLBACK(VBOXSTRICTRC)
364vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
365 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, uint64_t uUser)
366{
367 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
368
369 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
370 return VINF_PGM_HANDLER_DO_DEFAULT;
371
372 PPDMDEVINS pDevIns = (PPDMDEVINS)uUser;
373 AssertPtrReturn(pDevIns, VERR_INTERNAL_ERROR_4);
374 AssertReturn(pDevIns->u32Version == PDM_DEVINSR3_VERSION, VERR_INTERNAL_ERROR_5);
375 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
376 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
377 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
378
379 /*
380 * The guest is not allowed to access the memory.
381 * Set the error condition.
382 */
383 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
384
385 /* Try to find the GBO which the guest is accessing. */
386 char const *pszTarget = NULL;
387 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
388 {
389 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
390 if (pGbo->cDescriptors)
391 {
392 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
393 {
394 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
395 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * GUEST_PAGE_SIZE)
396 {
397 switch (i)
398 {
399 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
400 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
401 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
402 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
403 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
404 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
405 default: pszTarget = "Unknown OTABLE"; break;
406 }
407 break;
408 }
409 }
410 }
411 }
412
413 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
414 "%.*Rhxd\n",
415 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
416
417 return VINF_PGM_HANDLER_DO_DEFAULT;
418}
419
420#ifdef VBOX_WITH_VMSVGA3D
421
422static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
423{
424 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
425
426 /*
427 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
428 * Content of the root page depends on the ptDepth value:
429 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
430 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
431 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
432 * The code below extracts the page addresses of the GBO.
433 */
434
435 /* Verify and normalize the ptDepth value. */
436 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
437 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
438 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
439 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
440 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
441 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
442 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
443 {
444 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
445 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
446 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
447 }
448 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
449 { }
450 else
451 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
452
453 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
454
455 pGbo->cbTotal = sizeInBytes;
456 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
457
458 /* Allocate the maximum amount possible (everything non-continuous) */
459 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
460 AssertReturn(paDescriptors, VERR_NO_MEMORY);
461
462 int rc = VINF_SUCCESS;
463 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
464 {
465 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
466 RTMemFree(paDescriptors),
467 VERR_INVALID_PARAMETER);
468
469 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
470 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471 paDescriptors[0].GCPhys = GCPhys;
472 paDescriptors[0].cPages = 1;
473 }
474 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
475 {
476 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
477 RTMemFree(paDescriptors),
478 VERR_INVALID_PARAMETER);
479
480 /* Read the root page. */
481 uint8_t au8RootPage[X86_PAGE_SIZE];
482 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
483 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
484 if (RT_SUCCESS(rc))
485 {
486 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
487 PPN *paPPN32 = (PPN *)&au8RootPage[0];
488 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
489 {
490 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
491 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
492 paDescriptors[iPPN].GCPhys = GCPhys;
493 paDescriptors[iPPN].cPages = 1;
494 }
495 }
496 }
497 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
498 {
499 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
500 RTMemFree(paDescriptors),
501 VERR_INVALID_PARAMETER);
502
503 /* Read the Level2 root page. */
504 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
505 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
506 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
507 if (RT_SUCCESS(rc))
508 {
509 uint32_t cPagesLeft = pGbo->cTotalPages;
510
511 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
512 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
513
514 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
515 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
516 {
517 /* Read the Level1 root page. */
518 uint8_t au8RootPage[X86_PAGE_SIZE];
519 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
520 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
521 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
522 if (RT_SUCCESS(rc))
523 {
524 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
525 PPN *paPPN32 = (PPN *)&au8RootPage[0];
526
527 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
528 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
529 {
530 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
531 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
532 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
533 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
534 }
535 cPagesLeft -= cPPNs;
536 }
537 }
538 }
539 }
540 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
541 {
542 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[0].GCPhys = GCPhys;
545 paDescriptors[0].cPages = pGbo->cTotalPages;
546 }
547 else
548 {
549 AssertFailed();
550 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
551 }
552
553 /* Compress the descriptors. */
554 if (ptDepth != SVGA3D_MOBFMT_RANGE)
555 {
556 uint32_t iDescriptor = 0;
557 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
558 {
559 /* Continuous physical memory? */
560 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
561 {
562 Assert(paDescriptors[iDescriptor].cPages);
563 paDescriptors[iDescriptor].cPages++;
564 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
565 }
566 else
567 {
568 iDescriptor++;
569 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
570 paDescriptors[iDescriptor].cPages = 1;
571 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
572 }
573 }
574
575 pGbo->cDescriptors = iDescriptor + 1;
576 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
577 }
578 else
579 pGbo->cDescriptors = 1;
580
581 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
582 {
583 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
584 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
585 }
586 else
587 pGbo->paDescriptors = paDescriptors;
588
589#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
590fWriteProtected = false;
591#endif
592 if (fWriteProtected)
593 {
594 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
595 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
596 {
597 rc = PDMDevHlpPGMHandlerPhysicalRegister(pSvgaR3State->pDevIns,
598 pGbo->paDescriptors[i].GCPhys,
599 pGbo->paDescriptors[i].GCPhys
600 + pGbo->paDescriptors[i].cPages * GUEST_PAGE_SIZE - 1,
601 pSvgaR3State->hGboAccessHandlerType, "VMSVGA GBO");
602 AssertRC(rc);
603 }
604 }
605
606 return VINF_SUCCESS;
607}
608
609
610static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
611{
612 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
613 {
614 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
615 {
616 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
617 {
618 int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pSvgaR3State->pDevIns, pGbo->paDescriptors[i].GCPhys);
619 AssertRC(rc);
620 }
621 }
622 RTMemFree(pGbo->paDescriptors);
623 RT_ZERO(pGbo);
624 }
625}
626
627/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
628
629typedef enum VMSVGAGboTransferDirection
630{
631 VMSVGAGboTransferDirection_Read,
632 VMSVGAGboTransferDirection_Write,
633} VMSVGAGboTransferDirection;
634
635static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
636 uint32_t off, void *pvData, uint32_t cbData,
637 VMSVGAGboTransferDirection enmDirection)
638{
639 //DEBUG_BREAKPOINT_TEST();
640 int rc = VINF_SUCCESS;
641 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
642
643 /* Find the right descriptor */
644 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
645 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
646 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
647 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
648 {
649 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
650 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
651 ++iDescriptor;
652 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
653 }
654
655 while (cbData)
656 {
657 uint32_t cbToCopy;
658 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
659 cbToCopy = cbData;
660 else
661 {
662 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
663 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
664 }
665
666 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
667 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
668
669 /*
670 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
671 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
672 * see @bugref{9654#c75}.
673 */
674 if (enmDirection == VMSVGAGboTransferDirection_Read)
675 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
676 else
677 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
678 AssertRCBreak(rc);
679
680 cbData -= cbToCopy;
681 off += cbToCopy;
682 pu8CurrentHost += cbToCopy;
683
684 /* Go to the next descriptor if there's anything left. */
685 if (cbData)
686 {
687 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
688 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
689 ++iDescriptor;
690 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
691 }
692 }
693 return rc;
694}
695
696
697static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
698 uint32_t off, void const *pvData, uint32_t cbData)
699{
700 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
701 off, (void *)pvData, cbData,
702 VMSVGAGboTransferDirection_Write);
703}
704
705
706static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
707 uint32_t off, void *pvData, uint32_t cbData)
708{
709 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
710 off, pvData, cbData,
711 VMSVGAGboTransferDirection_Read);
712}
713
714
715static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
716{
717 int rc;
718
719 /* Just reread the data if pvHost has been allocated already. */
720 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
721 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
722
723 if (pGbo->pvHost)
724 {
725 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
726 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
727 }
728 else
729 rc = VERR_NO_MEMORY;
730
731 if (RT_SUCCESS(rc))
732 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
733 else
734 {
735 RTMemFree(pGbo->pvHost);
736 pGbo->pvHost = NULL;
737 }
738 return rc;
739}
740
741
742static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
743{
744 RT_NOREF(pSvgaR3State);
745 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
746 RTMemFree(pGbo->pvHost);
747 pGbo->pvHost = NULL;
748 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
749}
750
751
752static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
753{
754 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
755 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
756}
757
758
759static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
760{
761 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
762 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
763}
764
765
766
767/*
768 *
769 * Object Tables.
770 *
771 */
772
773static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
774 uint32_t idx, uint32_t cbEntry)
775{
776 RT_NOREF(pSvgaR3State);
777
778 /* The table must exist and the index must be within the table. */
779 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
780 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
781 RT_UNTRUSTED_VALIDATED_FENCE();
782 return VINF_SUCCESS;
783}
784
785
786static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
787 uint32_t idx, uint32_t cbEntry,
788 void *pvData, uint32_t cbData)
789{
790 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
791
792 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
793 if (RT_SUCCESS(rc))
794 {
795 uint32_t const off = idx * cbEntry;
796 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
797 }
798 return rc;
799}
800
801static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
802 uint32_t idx, uint32_t cbEntry,
803 void const *pvData, uint32_t cbData)
804{
805 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
806
807 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
808 if (RT_SUCCESS(rc))
809 {
810 uint32_t const off = idx * cbEntry;
811 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
812 }
813 return rc;
814}
815
816
817int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
818{
819 return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
820 sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
821}
822
823
824/*
825 *
826 * The guest's Memory OBjects (MOB).
827 *
828 */
829
830static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
831 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
832 bool fGCPhys64, PVMSVGAMOB pMob)
833{
834 RT_ZERO(*pMob);
835
836 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
837 SVGAOTableMobEntry entry;
838 entry.ptDepth = ptDepth;
839 entry.sizeInBytes = sizeInBytes;
840 entry.base = baseAddress;
841 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
842 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
843 if (RT_SUCCESS(rc))
844 {
845 /* Create the corresponding GBO. */
846 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
847 if (RT_SUCCESS(rc))
848 {
849 /* Add to the tree of known GBOs and the LRU list. */
850 pMob->Core.Key = mobid;
851 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
852 {
853 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
854 return VINF_SUCCESS;
855 }
856
857 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
858 }
859 }
860
861 return rc;
862}
863
864
865static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
866{
867 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
868 SVGAOTableMobEntry entry;
869 RT_ZERO(entry);
870 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
871 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
872
873 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
874 if (pMob)
875 {
876 RTListNodeRemove(&pMob->nodeLRU);
877 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
878 RTMemFree(pMob);
879 return VINF_SUCCESS;
880 }
881
882 return VERR_INVALID_PARAMETER;
883}
884
885
886PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
887{
888 if (mobid == SVGA_ID_INVALID)
889 return NULL;
890
891 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
892 if (pMob)
893 {
894 /* Move to the head of the LRU list. */
895 RTListNodeRemove(&pMob->nodeLRU);
896 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
897 }
898 else
899 ASSERT_GUEST_FAILED();
900
901 return pMob;
902}
903
904
905int vmsvgaR3MobWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
906 uint32_t off, void const *pvData, uint32_t cbData)
907{
908 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
909}
910
911
912int vmsvgaR3MobRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
913 uint32_t off, void *pvData, uint32_t cbData)
914{
915 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
916}
917
918
919/** Create a host ring-3 pointer to the MOB data.
920 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
921 * @param pSvgaR3State R3 device state.
922 * @param pMob The MOB.
923 * @param cbValid How many bytes of the guest backing memory contain valid data.
924 * @return VBox status.
925 */
926/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
927int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
928{
929 AssertReturn(pMob, VERR_INVALID_PARAMETER);
930 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
931}
932
933
934void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
935{
936 if (pMob)
937 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
938}
939
940
941int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
942{
943 if (pMob)
944 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
945 return VERR_INVALID_PARAMETER;
946}
947
948
949int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
950{
951 if (pMob)
952 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
953 return VERR_INVALID_PARAMETER;
954}
955
956
957void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
958{
959 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
960 {
961 if (off <= pMob->Gbo.cbTotal)
962 return (uint8_t *)pMob->Gbo.pvHost + off;
963 }
964 return NULL;
965}
966
967#endif /* VBOX_WITH_VMSVGA3D */
968
969/*
970 * Screen objects.
971 */
972VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
973{
974 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
975 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
976 && pSVGAState
977 && pSVGAState->aScreens[idScreen].fDefined)
978 {
979 return &pSVGAState->aScreens[idScreen];
980 }
981 return NULL;
982}
983
984void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
985{
986#ifdef VBOX_WITH_VMSVGA3D
987 if (pThis->svga.f3DEnabled)
988 {
989 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
990 {
991 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
992 if (pScreen)
993 vmsvga3dDestroyScreen(pThisCC, pScreen);
994 }
995 }
996#else
997 RT_NOREF(pThis, pThisCC);
998#endif
999}
1000
1001
1002/**
1003 * Copy a rectangle of pixels within guest VRAM.
1004 */
1005static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1006 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1007{
1008 if (!width || !height)
1009 return; /* Nothing to do, don't even bother. */
1010
1011 /*
1012 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1013 * corresponding to the current display mode.
1014 */
1015 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1016 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1017 uint8_t const *pSrc;
1018 uint8_t *pDst;
1019 unsigned const cbRectWidth = width * cbPixel;
1020 unsigned uMaxOffset;
1021
1022 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1023 if (uMaxOffset >= cbFrameBuffer)
1024 {
1025 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1026 return; /* Just don't listen to a bad guest. */
1027 }
1028
1029 pSrc = pDst = pThisCC->pbVRam;
1030 pSrc += srcY * cbScanline + srcX * cbPixel;
1031 pDst += dstY * cbScanline + dstX * cbPixel;
1032
1033 if (srcY >= dstY)
1034 {
1035 /* Source below destination, copy top to bottom. */
1036 for (; height > 0; height--)
1037 {
1038 memmove(pDst, pSrc, cbRectWidth);
1039 pSrc += cbScanline;
1040 pDst += cbScanline;
1041 }
1042 }
1043 else
1044 {
1045 /* Source above destination, copy bottom to top. */
1046 pSrc += cbScanline * (height - 1);
1047 pDst += cbScanline * (height - 1);
1048 for (; height > 0; height--)
1049 {
1050 memmove(pDst, pSrc, cbRectWidth);
1051 pSrc -= cbScanline;
1052 pDst -= cbScanline;
1053 }
1054 }
1055}
1056
1057
1058/**
1059 * Common worker for changing the pointer shape.
1060 *
1061 * @param pThisCC The VGA/VMSVGA state for ring-3.
1062 * @param pSVGAState The VMSVGA ring-3 instance data.
1063 * @param fAlpha Whether there is alpha or not.
1064 * @param xHot Hotspot x coordinate.
1065 * @param yHot Hotspot y coordinate.
1066 * @param cx Width.
1067 * @param cy Height.
1068 * @param pbData Heap copy of the cursor data. Consumed.
1069 * @param cbData The size of the data.
1070 */
1071static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1072 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1073{
1074 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1075#ifdef LOG_ENABLED
1076 if (LogIs2Enabled())
1077 {
1078 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1079 if (!fAlpha)
1080 {
1081 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1082 for (uint32_t y = 0; y < cy; y++)
1083 {
1084 Log2(("%3u:", y));
1085 uint8_t const *pbLine = &pbData[y * cbAndLine];
1086 for (uint32_t x = 0; x < cx; x += 8)
1087 {
1088 uint8_t b = pbLine[x / 8];
1089 char szByte[12];
1090 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1091 szByte[1] = b & 0x40 ? '*' : ' ';
1092 szByte[2] = b & 0x20 ? '*' : ' ';
1093 szByte[3] = b & 0x10 ? '*' : ' ';
1094 szByte[4] = b & 0x08 ? '*' : ' ';
1095 szByte[5] = b & 0x04 ? '*' : ' ';
1096 szByte[6] = b & 0x02 ? '*' : ' ';
1097 szByte[7] = b & 0x01 ? '*' : ' ';
1098 szByte[8] = '\0';
1099 Log2(("%s", szByte));
1100 }
1101 Log2(("\n"));
1102 }
1103 }
1104
1105 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1106 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1107 for (uint32_t y = 0; y < cy; y++)
1108 {
1109 Log2(("%3u:", y));
1110 uint32_t const *pu32Line = &pu32Xor[y * cx];
1111 for (uint32_t x = 0; x < cx; x++)
1112 Log2((" %08x", pu32Line[x]));
1113 Log2(("\n"));
1114 }
1115 }
1116#endif
1117
1118 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1119 AssertRC(rc);
1120
1121 if (pSVGAState->Cursor.fActive)
1122 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1123
1124 pSVGAState->Cursor.fActive = true;
1125 pSVGAState->Cursor.xHotspot = xHot;
1126 pSVGAState->Cursor.yHotspot = yHot;
1127 pSVGAState->Cursor.width = cx;
1128 pSVGAState->Cursor.height = cy;
1129 pSVGAState->Cursor.cbData = cbData;
1130 pSVGAState->Cursor.pData = pbData;
1131}
1132
1133
1134#ifdef VBOX_WITH_VMSVGA3D
1135
1136/*
1137 * SVGA_3D_CMD_* handlers.
1138 */
1139
1140
1141/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1142 *
1143 * @param pThisCC The VGA/VMSVGA state for the current context.
1144 * @param pCmd The VMSVGA command.
1145 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1146 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1147 */
1148static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1149 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1150{
1151 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1152 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1153 RT_UNTRUSTED_VALIDATED_FENCE();
1154
1155 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1156 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1157 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1158 */
1159 uint32_t cRemainingMipLevels = cMipLevelSizes;
1160 uint32_t cFaces = 0;
1161 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1162 {
1163 if (pCmd->face[i].numMipLevels == 0)
1164 break;
1165
1166 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1167 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1168
1169 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1170 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1171 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1172
1173 ++cFaces;
1174 }
1175 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1176 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1177
1178 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1179 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1180
1181 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1182 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1183 RT_UNTRUSTED_VALIDATED_FENCE();
1184
1185 /* Verify paMipLevelSizes */
1186 uint32_t cWidth = paMipLevelSizes[0].width;
1187 uint32_t cHeight = paMipLevelSizes[0].height;
1188 uint32_t cDepth = paMipLevelSizes[0].depth;
1189 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1190 {
1191 cWidth >>= 1;
1192 if (cWidth == 0) cWidth = 1;
1193 cHeight >>= 1;
1194 if (cHeight == 0) cHeight = 1;
1195 cDepth >>= 1;
1196 if (cDepth == 0) cDepth = 1;
1197 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1198 {
1199 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1200 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1201 && cHeight == paMipLevelSizes[iMipLevelSize].height
1202 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1203 }
1204 }
1205 RT_UNTRUSTED_VALIDATED_FENCE();
1206
1207 /* Create the surface. */
1208 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1209 pCmd->multisampleCount, pCmd->autogenFilter,
1210 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* arraySize = */ 0, /* fAllocMipLevels = */ true);
1211}
1212
1213
1214/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1215static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1216{
1217 DEBUG_BREAKPOINT_TEST();
1218 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1219
1220 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1221
1222 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1223 /* Allocate a structure for the MOB. */
1224 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1225 AssertPtrReturnVoid(pMob);
1226
1227 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1228 if (RT_SUCCESS(rc))
1229 {
1230 return;
1231 }
1232
1233 AssertFailed();
1234
1235 RTMemFree(pMob);
1236}
1237
1238
1239/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1240static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1241{
1242 //DEBUG_BREAKPOINT_TEST();
1243 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1244
1245 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1246
1247 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1248 if (RT_SUCCESS(rc))
1249 {
1250 return;
1251 }
1252
1253 AssertFailed();
1254}
1255
1256
1257/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1258static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1259{
1260 //DEBUG_BREAKPOINT_TEST();
1261 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1262
1263 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1264 SVGAOTableSurfaceEntry entry;
1265 RT_ZERO(entry);
1266 entry.format = pCmd->format;
1267 entry.surface1Flags = pCmd->surfaceFlags;
1268 entry.numMipLevels = pCmd->numMipLevels;
1269 entry.multisampleCount = pCmd->multisampleCount;
1270 entry.autogenFilter = pCmd->autogenFilter;
1271 entry.size = pCmd->size;
1272 entry.mobid = SVGA_ID_INVALID;
1273 // entry.arraySize = 0;
1274 // entry.mobPitch = 0;
1275 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1276 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1277 if (RT_SUCCESS(rc))
1278 {
1279 /* Create the host surface. */
1280 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1281 pCmd->multisampleCount, pCmd->autogenFilter,
1282 pCmd->numMipLevels, &pCmd->size, /* arraySize = */ 0, /* fAllocMipLevels = */ false);
1283 }
1284}
1285
1286
1287/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1288static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1289{
1290 //DEBUG_BREAKPOINT_TEST();
1291 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1292
1293 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1294 SVGAOTableSurfaceEntry entry;
1295 RT_ZERO(entry);
1296 entry.mobid = SVGA_ID_INVALID;
1297 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1298 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1299
1300 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1301}
1302
1303
1304/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1305static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1306{
1307 //DEBUG_BREAKPOINT_TEST();
1308 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1309
1310 /* Assign the mobid to the surface. */
1311 int rc = VINF_SUCCESS;
1312 if (pCmd->mobid != SVGA_ID_INVALID)
1313 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1314 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1315 if (RT_SUCCESS(rc))
1316 {
1317 SVGAOTableSurfaceEntry entry;
1318 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1319 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1320 if (RT_SUCCESS(rc))
1321 {
1322 entry.mobid = pCmd->mobid;
1323 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1324 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1325 if (RT_SUCCESS(rc))
1326 {
1327 /* */
1328 }
1329 }
1330 }
1331}
1332
1333
1334typedef union
1335{
1336 float f;
1337 uint32_t u;
1338} Unsigned2Float;
1339
1340float float16ToFloat(uint16_t f16)
1341{
1342 /* Format specs from Wiki: [15] = sign, [14:10] = exponent, [9:0] = fraction */
1343 uint16_t const f = f16 & 0x3FF;
1344 uint16_t const e = (f16 >> 10) & 0x1F;
1345 uint16_t const s = (f16 >> 15) & 0x1;
1346 Unsigned2Float u2f;
1347
1348 if (e == 0)
1349 {
1350 if (f == 0)
1351 {
1352 /* zero, -0 */
1353 u2f.u = (s << 31) | (0 << 23) | 0;
1354 return u2f.f;
1355 }
1356
1357 /* subnormal numbers: (-1)^signbit * 2^-14 * 0.significantbits */
1358 float const k = 1.0f / 16384.0f; /* 2^-14 */
1359 return (s ? -1.0f : 1.0f) * k * (float)f / 1024.0f;
1360 }
1361
1362 if (e == 31)
1363 {
1364 if (f == 0)
1365 {
1366 /* +-infinity */
1367 u2f.u = (s << 31) | (0xFF << 23) | 0;
1368 return u2f.f;
1369 }
1370
1371 /* NaN */
1372 u2f.u = (s << 31) | (0xFF << 23) | 1;
1373 return u2f.f;
1374 }
1375
1376 /* normalized value: (-1)^signbit * 2^(exponent - 15) * 1.significantbits */
1377 /* Build the float, adjusting for exponent bias (float32 bias is 127, float16 is 15)
1378 * and number of bits in the fraction (float32 has 23, float16 has 10). */
1379 u2f.u = (s << 31) | ((e + 127 - 15) << 23) | (f << (23 - 10));
1380 return u2f.f;
1381}
1382
1383
1384static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1385{
1386 if (pMap->cbBlock != 4 && pMap->cbBlock != 1 && pMap->format != SVGA3D_R16G16B16A16_FLOAT)
1387 return VERR_NOT_SUPPORTED;
1388
1389 int const w = pMap->cbRow / pMap->cbBlock;
1390 int const h = pMap->cRows;
1391
1392 const int cbBitmap = pMap->cbRow * pMap->cRows * 4;
1393
1394 FILE *f = fopen(pszFilename, "wb");
1395 if (!f)
1396 return VERR_FILE_NOT_FOUND;
1397
1398 {
1399 BMPFILEHDR fileHdr;
1400 RT_ZERO(fileHdr);
1401 fileHdr.uType = BMP_HDR_MAGIC;
1402 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1403 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1404
1405 BMPWIN3XINFOHDR coreHdr;
1406 RT_ZERO(coreHdr);
1407 coreHdr.cbSize = sizeof(coreHdr);
1408 coreHdr.uWidth = w;
1409 coreHdr.uHeight = -h;
1410 coreHdr.cPlanes = 1;
1411 coreHdr.cBits = 32;
1412 coreHdr.cbSizeImage = cbBitmap;
1413
1414 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1415 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1416 }
1417
1418 if (pMap->cbBlock == 4)
1419 {
1420 const uint8_t *s = (uint8_t *)pMap->pvData;
1421 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1422 {
1423 fwrite(s, 1, pMap->cbRow, f);
1424
1425 s += pMap->cbRowPitch;
1426 }
1427 }
1428 else if (pMap->cbBlock == 1)
1429 {
1430 const uint8_t *s = (uint8_t *)pMap->pvData;
1431 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1432 {
1433 for (int32_t x = 0; x < w; ++x)
1434 {
1435 uint32_t u32Pixel = s[x];
1436 fwrite(&u32Pixel, 1, 4, f);
1437 }
1438
1439 s += pMap->cbRowPitch;
1440 }
1441 }
1442 else if (pMap->format == SVGA3D_R16G16B16A16_FLOAT)
1443 {
1444 const uint8_t *s = (uint8_t *)pMap->pvData;
1445 for (int32_t y = 0; y < h; ++y)
1446 {
1447 for (int32_t x = 0; x < w; ++x)
1448 {
1449 uint16_t const *pu16Pixel = (uint16_t *)(s + x * 8);
1450 uint8_t r = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[0]));
1451 uint8_t g = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[1]));
1452 uint8_t b = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[2]));
1453 uint8_t a = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[3]));
1454 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1455 fwrite(&u32Pixel, 1, 4, f);
1456 }
1457
1458 s += pMap->cbRowPitch;
1459 }
1460 }
1461
1462 fclose(f);
1463
1464 return VINF_SUCCESS;
1465}
1466
1467
1468void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1469{
1470 static int idxBitmap = 0;
1471 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1472 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1473 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1474 RTStrFree(pszFilename);
1475}
1476
1477
1478static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1479 PVMSVGAMOB pMob,
1480 SVGA3dSurfaceImageId const *pImage,
1481 SVGA3dBox const *pBox,
1482 SVGA3dTransferType enmTransfer)
1483{
1484 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1485
1486 VMSVGA3D_SURFACE_MAP enmMapType;
1487 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1488 enmMapType = pBox
1489 ? VMSVGA3D_SURFACE_MAP_WRITE
1490 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1491 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1492 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1493 else
1494 AssertFailedReturn(VERR_INVALID_PARAMETER);
1495
1496 VMSVGA3D_MAPPED_SURFACE map;
1497 int rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1498 if (RT_SUCCESS(rc))
1499 {
1500 /* Copy mapped surface <-> MOB. */
1501 VMSGA3D_BOX_DIMENSIONS dims;
1502 rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1503 if (RT_SUCCESS(rc))
1504 {
1505 for (uint32_t z = 0; z < map.box.d; ++z)
1506 {
1507 uint8_t *pu8Map = (uint8_t *)map.pvData + z * map.cbDepthPitch;
1508 uint32_t offMob = dims.offSubresource + dims.offBox + z * dims.cbDepthPitch;
1509
1510 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1511 {
1512 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1513 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1514 else
1515 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1516 AssertRCBreak(rc);
1517
1518 pu8Map += map.cbRowPitch;
1519 offMob += dims.cbPitch;
1520 }
1521 }
1522 }
1523
1524 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1525
1526 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1527 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1528 }
1529
1530 return rc;
1531}
1532
1533
1534/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1535static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1536{
1537 //DEBUG_BREAKPOINT_TEST();
1538 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1539
1540 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1541 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1542
1543/*
1544 SVGA3dSurfaceFormat format;
1545 SVGA3dSurface1Flags surface1Flags;
1546 uint32 numMipLevels;
1547 uint32 multisampleCount;
1548 SVGA3dTextureFilter autogenFilter;
1549 SVGA3dSize size;
1550 SVGAMobId mobid;
1551 uint32 arraySize;
1552 uint32 mobPitch;
1553 SVGA3dSurface2Flags surface2Flags;
1554 uint8 multisamplePattern;
1555 uint8 qualityLevel;
1556 uint16 bufferByteStride;
1557 float minLOD;
1558*/
1559
1560 /* "update a surface from its backing MOB." */
1561 SVGAOTableSurfaceEntry entrySurface;
1562 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1563 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1564 if (RT_SUCCESS(rc))
1565 {
1566 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1567 if (pMob)
1568 {
1569 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1570 AssertRC(rc);
1571 }
1572 }
1573}
1574
1575
1576/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1577static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1578{
1579 //DEBUG_BREAKPOINT_TEST();
1580 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1581
1582 LogFlowFunc(("sid=%u\n",
1583 pCmd->sid));
1584
1585 /* "update a surface from its backing MOB." */
1586 SVGAOTableSurfaceEntry entrySurface;
1587 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1588 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1589 if (RT_SUCCESS(rc))
1590 {
1591 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1592 if (pMob)
1593 {
1594 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1595 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1596 {
1597 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1598 {
1599 SVGA3dSurfaceImageId image;
1600 image.sid = pCmd->sid;
1601 image.face = iArray;
1602 image.mipmap = iMipmap;
1603
1604 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1605 AssertRCBreak(rc);
1606 }
1607 }
1608 }
1609 }
1610}
1611
1612
1613/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1614static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1615{
1616 //DEBUG_BREAKPOINT_TEST();
1617 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1618
1619 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1620 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1621
1622 /* Read a surface to its backing MOB. */
1623 SVGAOTableSurfaceEntry entrySurface;
1624 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1625 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1626 if (RT_SUCCESS(rc))
1627 {
1628 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1629 if (pMob)
1630 {
1631 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1632 AssertRC(rc);
1633 }
1634 }
1635}
1636
1637
1638/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1639static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1640{
1641 //DEBUG_BREAKPOINT_TEST();
1642 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1643
1644 LogFlowFunc(("sid=%u\n",
1645 pCmd->sid));
1646
1647 /* Read a surface to its backing MOB. */
1648 SVGAOTableSurfaceEntry entrySurface;
1649 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1650 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1651 if (RT_SUCCESS(rc))
1652 {
1653 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1654 if (pMob)
1655 {
1656 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1657 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1658 {
1659 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1660 {
1661 SVGA3dSurfaceImageId image;
1662 image.sid = pCmd->sid;
1663 image.face = iArray;
1664 image.mipmap = iMipmap;
1665
1666 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1667 AssertRCBreak(rc);
1668 }
1669 }
1670 }
1671 }
1672}
1673
1674
1675/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1676static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1677{
1678 //DEBUG_BREAKPOINT_TEST();
1679 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1680}
1681
1682
1683/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1684static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1685{
1686 //DEBUG_BREAKPOINT_TEST();
1687 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1688}
1689
1690
1691/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1692static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1693{
1694 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1695
1696 /*
1697 * Create a GBO for the table.
1698 */
1699 PVMSVGAGBO pGbo;
1700 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1701 {
1702 RT_UNTRUSTED_VALIDATED_FENCE();
1703 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1704 }
1705 else
1706 {
1707 ASSERT_GUEST_FAILED();
1708 pGbo = NULL;
1709 }
1710
1711 if (pGbo)
1712 {
1713 /* Recreate. */
1714 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1715 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1716 AssertRC(rc);
1717 }
1718}
1719
1720
1721/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1722static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1723{
1724 //DEBUG_BREAKPOINT_TEST();
1725 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1726
1727 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1728 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1729 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1730 RT_UNTRUSTED_VALIDATED_FENCE();
1731
1732 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1733 SVGAOTableScreenTargetEntry entry;
1734 RT_ZERO(entry);
1735 entry.image.sid = SVGA_ID_INVALID;
1736 // entry.image.face = 0;
1737 // entry.image.mipmap = 0;
1738 entry.width = pCmd->width;
1739 entry.height = pCmd->height;
1740 entry.xRoot = pCmd->xRoot;
1741 entry.yRoot = pCmd->yRoot;
1742 entry.flags = pCmd->flags;
1743 entry.dpi = pCmd->dpi;
1744
1745 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1746 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1747 if (RT_SUCCESS(rc))
1748 {
1749 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1750 /** @todo Generic screen object/target interface. */
1751 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1752 pScreen->fDefined = true;
1753 pScreen->fModified = true;
1754 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1755 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1756 pScreen->idScreen = pCmd->stid;
1757
1758 pScreen->xOrigin = pCmd->xRoot;
1759 pScreen->yOrigin = pCmd->yRoot;
1760 pScreen->cWidth = pCmd->width;
1761 pScreen->cHeight = pCmd->height;
1762 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1763 pScreen->cbPitch = pCmd->width * 4;
1764 pScreen->cBpp = 32;
1765
1766 if (RT_LIKELY(pThis->svga.f3DEnabled))
1767 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1768
1769 if (!pScreen->pHwScreen)
1770 {
1771 /* System memory buffer. */
1772 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1773 }
1774
1775 pThis->svga.fGFBRegisters = false;
1776 vmsvgaR3ChangeMode(pThis, pThisCC);
1777 }
1778}
1779
1780
1781/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1782static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1783{
1784 //DEBUG_BREAKPOINT_TEST();
1785 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1786
1787 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1788 RT_UNTRUSTED_VALIDATED_FENCE();
1789
1790 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1791 SVGAOTableScreenTargetEntry entry;
1792 RT_ZERO(entry);
1793 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1794 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1795 if (RT_SUCCESS(rc))
1796 {
1797 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1798 /** @todo Generic screen object/target interface. */
1799 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1800 pScreen->fModified = true;
1801 pScreen->fDefined = false;
1802 pScreen->idScreen = pCmd->stid;
1803
1804 if (RT_LIKELY(pThis->svga.f3DEnabled))
1805 vmsvga3dDestroyScreen(pThisCC, pScreen);
1806
1807 vmsvgaR3ChangeMode(pThis, pThisCC);
1808
1809 RTMemFree(pScreen->pvScreenBitmap);
1810 pScreen->pvScreenBitmap = NULL;
1811 }
1812}
1813
1814
1815/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1816static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1817{
1818 //DEBUG_BREAKPOINT_TEST();
1819 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1820
1821 /* "Binding a surface to a Screen Target the same as flipping" */
1822
1823 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1824 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1825 RT_UNTRUSTED_VALIDATED_FENCE();
1826
1827 /* Assign the surface to the screen target. */
1828 int rc = VINF_SUCCESS;
1829 if (pCmd->image.sid != SVGA_ID_INVALID)
1830 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1831 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1832 if (RT_SUCCESS(rc))
1833 {
1834 SVGAOTableScreenTargetEntry entry;
1835 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1836 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1837 if (RT_SUCCESS(rc))
1838 {
1839 entry.image = pCmd->image;
1840 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1841 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1842 if (RT_SUCCESS(rc))
1843 {
1844 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1845 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1846 AssertRC(rc);
1847 }
1848 }
1849 }
1850}
1851
1852
1853/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1854static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1855{
1856 //DEBUG_BREAKPOINT_TEST();
1857 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1858
1859 /* Update the screen target from its backing surface. */
1860 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1861 RT_UNTRUSTED_VALIDATED_FENCE();
1862
1863 /* Get the screen target info. */
1864 SVGAOTableScreenTargetEntry entryScreenTarget;
1865 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1866 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1867 if (RT_SUCCESS(rc))
1868 {
1869 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1870 RT_UNTRUSTED_VALIDATED_FENCE();
1871
1872 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1873 {
1874 SVGAOTableSurfaceEntry entrySurface;
1875 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1876 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1877 if (RT_SUCCESS(rc))
1878 {
1879 /* Copy entrySurface.mobid content to the screen target. */
1880 if (entrySurface.mobid != SVGA_ID_INVALID)
1881 {
1882 RT_UNTRUSTED_VALIDATED_FENCE();
1883 SVGA3dRect targetRect = pCmd->rect;
1884
1885 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1886 if (pScreen->pHwScreen)
1887 {
1888 /* Copy the screen target surface to the backend's screen. */
1889 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1890 }
1891 else if (pScreen->pvScreenBitmap)
1892 {
1893 /* Copy the screen target surface to the memory buffer. */
1894 SVGA3dBox box; /* SurfaceMap will clip the box as necessary. */
1895 box.x = pCmd->rect.x;
1896 box.y = pCmd->rect.y;
1897 box.z = 0;
1898 box.w = pCmd->rect.w;
1899 box.h = pCmd->rect.h;
1900 box.d = 1;
1901
1902 VMSVGA3D_MAPPED_SURFACE map;
1903 rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, &box, VMSVGA3D_SURFACE_MAP_READ, &map);
1904 if (RT_SUCCESS(rc))
1905 {
1906 VMSGA3D_BOX_DIMENSIONS dims;
1907 rc = vmsvga3dGetBoxDimensions(pThisCC, &entryScreenTarget.image, &map.box, &dims);
1908 if (RT_SUCCESS(rc))
1909 {
1910 uint8_t const *pu8Src = (uint8_t *)map.pvData;
1911 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap + dims.offSubresource + dims.offBox;
1912 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1913 {
1914 memcpy(pu8Dst, pu8Src, dims.cbRow);
1915
1916 pu8Src += map.cbRowPitch;
1917 pu8Dst += dims.cbPitch;
1918 }
1919 }
1920
1921 vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1922
1923 vmsvgaR3UpdateScreen(pThisCC, pScreen, map.box.x, map.box.y, map.box.w, map.box.h);
1924 }
1925 else
1926 AssertFailed();
1927 }
1928 }
1929 }
1930 }
1931 }
1932}
1933
1934
1935/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1936static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1937{
1938 //DEBUG_BREAKPOINT_TEST();
1939 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1940
1941 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1942 SVGAOTableSurfaceEntry entry;
1943 RT_ZERO(entry);
1944 entry.format = pCmd->format;
1945 entry.surface1Flags = pCmd->surfaceFlags;
1946 entry.numMipLevels = pCmd->numMipLevels;
1947 entry.multisampleCount = pCmd->multisampleCount;
1948 entry.autogenFilter = pCmd->autogenFilter;
1949 entry.size = pCmd->size;
1950 entry.mobid = SVGA_ID_INVALID;
1951 entry.arraySize = pCmd->arraySize;
1952 // entry.mobPitch = 0;
1953 // entry.mobPitch = 0;
1954 // entry.surface2Flags = 0;
1955 // entry.multisamplePattern = 0;
1956 // entry.qualityLevel = 0;
1957 // entry.bufferByteStride = 0;
1958 // entry.minLOD = 0;
1959
1960 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1961 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1962 if (RT_SUCCESS(rc))
1963 {
1964 /* Create the host surface. */
1965 /** @todo SVGAOTableSurfaceEntry as input parameter? */
1966 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1967 pCmd->multisampleCount, pCmd->autogenFilter,
1968 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
1969 }
1970}
1971
1972
1973/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1974static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1975{
1976 //DEBUG_BREAKPOINT_TEST();
1977 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1978
1979 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1980
1981 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1982 /* Allocate a structure for the MOB. */
1983 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1984 AssertPtrReturnVoid(pMob);
1985
1986 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1987 if (RT_SUCCESS(rc))
1988 {
1989 return;
1990 }
1991
1992 RTMemFree(pMob);
1993}
1994
1995
1996/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1997static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1998{
1999#ifdef VMSVGA3D_DX
2000 //DEBUG_BREAKPOINT_TEST();
2001 RT_NOREF(cbCmd);
2002
2003 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2004
2005 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2006 SVGAOTableDXContextEntry entry;
2007 RT_ZERO(entry);
2008 entry.cid = pCmd->cid;
2009 entry.mobid = SVGA_ID_INVALID;
2010 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2011 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2012 if (RT_SUCCESS(rc))
2013 {
2014 /* Create the host context. */
2015 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
2016 }
2017
2018 return rc;
2019#else
2020 RT_NOREF(pThisCC, pCmd, cbCmd);
2021 return VERR_NOT_SUPPORTED;
2022#endif
2023}
2024
2025
2026/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2027static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2028{
2029#ifdef VMSVGA3D_DX
2030 //DEBUG_BREAKPOINT_TEST();
2031 RT_NOREF(cbCmd);
2032
2033 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2034
2035 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2036 SVGAOTableDXContextEntry entry;
2037 RT_ZERO(entry);
2038 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2039 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2040
2041 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2042#else
2043 RT_NOREF(pThisCC, pCmd, cbCmd);
2044 return VERR_NOT_SUPPORTED;
2045#endif
2046}
2047
2048
2049/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2050static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2051{
2052#ifdef VMSVGA3D_DX
2053 //DEBUG_BREAKPOINT_TEST();
2054 RT_NOREF(cbCmd);
2055
2056 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2057
2058 /* Assign a mobid to a cid. */
2059 int rc = VINF_SUCCESS;
2060 if (pCmd->mobid != SVGA_ID_INVALID)
2061 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2062 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2063 if (RT_SUCCESS(rc))
2064 {
2065 SVGAOTableDXContextEntry entry;
2066 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2067 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2068 if (RT_SUCCESS(rc))
2069 {
2070 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2071 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2072 {
2073 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2074 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2075 if (pSvgaDXContext)
2076 {
2077 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2078 if (RT_SUCCESS(rc))
2079 {
2080 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2081 if (pMob)
2082 {
2083 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2084 }
2085 }
2086
2087 RTMemFree(pSvgaDXContext);
2088 pSvgaDXContext = NULL;
2089 }
2090 }
2091
2092 if (pCmd->mobid != SVGA_ID_INVALID)
2093 {
2094 /* Bind a new context. Copy existing data from the guest backing memory. */
2095 if (pCmd->validContents)
2096 {
2097 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2098 if (pMob)
2099 {
2100 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2101 if (pSvgaDXContext)
2102 {
2103 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2104 if (RT_FAILURE(rc))
2105 {
2106 RTMemFree(pSvgaDXContext);
2107 pSvgaDXContext = NULL;
2108 }
2109 }
2110 }
2111 }
2112
2113 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2114
2115 RTMemFree(pSvgaDXContext);
2116 }
2117
2118 /* Update the object table. */
2119 entry.mobid = pCmd->mobid;
2120 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2121 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2122 }
2123 }
2124
2125 return rc;
2126#else
2127 RT_NOREF(pThisCC, pCmd, cbCmd);
2128 return VERR_NOT_SUPPORTED;
2129#endif
2130}
2131
2132
2133/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2134static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2135{
2136#ifdef VMSVGA3D_DX
2137 //DEBUG_BREAKPOINT_TEST();
2138 RT_NOREF(cbCmd);
2139
2140 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2141
2142 /* "Request that the device flush the contents back into guest memory." */
2143 SVGAOTableDXContextEntry entry;
2144 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2145 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2146 if (RT_SUCCESS(rc))
2147 {
2148 if (entry.mobid != SVGA_ID_INVALID)
2149 {
2150 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2151 if (pMob)
2152 {
2153 /* Get the content. */
2154 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2155 if (pSvgaDXContext)
2156 {
2157 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2158 if (RT_SUCCESS(rc))
2159 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2160
2161 RTMemFree(pSvgaDXContext);
2162 }
2163 else
2164 rc = VERR_NO_MEMORY;
2165 }
2166 }
2167 }
2168
2169 return rc;
2170#else
2171 RT_NOREF(pThisCC, pCmd, cbCmd);
2172 return VERR_NOT_SUPPORTED;
2173#endif
2174}
2175
2176
2177/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2178static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2179{
2180#ifdef VMSVGA3D_DX
2181 DEBUG_BREAKPOINT_TEST();
2182 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2183 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2184 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2185#else
2186 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2187 return VERR_NOT_SUPPORTED;
2188#endif
2189}
2190
2191
2192/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2193static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2194{
2195#ifdef VMSVGA3D_DX
2196 //DEBUG_BREAKPOINT_TEST();
2197 RT_NOREF(cbCmd);
2198 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2199#else
2200 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2201 return VERR_NOT_SUPPORTED;
2202#endif
2203}
2204
2205
2206/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2207static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2208{
2209#ifdef VMSVGA3D_DX
2210 //DEBUG_BREAKPOINT_TEST();
2211 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2212 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2213 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2214#else
2215 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2216 return VERR_NOT_SUPPORTED;
2217#endif
2218}
2219
2220
2221/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2222static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2223{
2224#ifdef VMSVGA3D_DX
2225 //DEBUG_BREAKPOINT_TEST();
2226 RT_NOREF(cbCmd);
2227 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2228#else
2229 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2230 return VERR_NOT_SUPPORTED;
2231#endif
2232}
2233
2234
2235/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2236static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2237{
2238#ifdef VMSVGA3D_DX
2239 //DEBUG_BREAKPOINT_TEST();
2240 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2241 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2242 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2243#else
2244 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2245 return VERR_NOT_SUPPORTED;
2246#endif
2247}
2248
2249
2250/* SVGA_3D_CMD_DX_DRAW 1152 */
2251static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2252{
2253#ifdef VMSVGA3D_DX
2254 //DEBUG_BREAKPOINT_TEST();
2255 RT_NOREF(cbCmd);
2256 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2257#else
2258 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2259 return VERR_NOT_SUPPORTED;
2260#endif
2261}
2262
2263
2264/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2265static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2266{
2267#ifdef VMSVGA3D_DX
2268 //DEBUG_BREAKPOINT_TEST();
2269 RT_NOREF(cbCmd);
2270 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2271#else
2272 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2273 return VERR_NOT_SUPPORTED;
2274#endif
2275}
2276
2277
2278/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2279static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2280{
2281#ifdef VMSVGA3D_DX
2282 //DEBUG_BREAKPOINT_TEST();
2283 RT_NOREF(cbCmd);
2284 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2285#else
2286 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2287 return VERR_NOT_SUPPORTED;
2288#endif
2289}
2290
2291
2292/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2293static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2294{
2295#ifdef VMSVGA3D_DX
2296 //DEBUG_BREAKPOINT_TEST();
2297 RT_NOREF(cbCmd);
2298 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2299#else
2300 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2301 return VERR_NOT_SUPPORTED;
2302#endif
2303}
2304
2305
2306/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2307static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2308{
2309#ifdef VMSVGA3D_DX
2310 DEBUG_BREAKPOINT_TEST();
2311 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2312 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2313 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2314#else
2315 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2316 return VERR_NOT_SUPPORTED;
2317#endif
2318}
2319
2320
2321/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2322static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2323{
2324#ifdef VMSVGA3D_DX
2325 //DEBUG_BREAKPOINT_TEST();
2326 RT_NOREF(cbCmd);
2327 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2328#else
2329 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2330 return VERR_NOT_SUPPORTED;
2331#endif
2332}
2333
2334
2335/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2336static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2337{
2338#ifdef VMSVGA3D_DX
2339 //DEBUG_BREAKPOINT_TEST();
2340 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2341 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2342 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2343#else
2344 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2345 return VERR_NOT_SUPPORTED;
2346#endif
2347}
2348
2349
2350/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2351static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2352{
2353#ifdef VMSVGA3D_DX
2354 //DEBUG_BREAKPOINT_TEST();
2355 RT_NOREF(cbCmd);
2356 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2357#else
2358 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2359 return VERR_NOT_SUPPORTED;
2360#endif
2361}
2362
2363
2364/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2365static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2366{
2367#ifdef VMSVGA3D_DX
2368 //DEBUG_BREAKPOINT_TEST();
2369 RT_NOREF(cbCmd);
2370 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2371#else
2372 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2373 return VERR_NOT_SUPPORTED;
2374#endif
2375}
2376
2377
2378/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2379static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2380{
2381#ifdef VMSVGA3D_DX
2382 //DEBUG_BREAKPOINT_TEST();
2383 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2384 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2385 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2386#else
2387 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2388 return VERR_NOT_SUPPORTED;
2389#endif
2390}
2391
2392
2393/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2394static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2395{
2396#ifdef VMSVGA3D_DX
2397 //DEBUG_BREAKPOINT_TEST();
2398 RT_NOREF(cbCmd);
2399 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2400#else
2401 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2402 return VERR_NOT_SUPPORTED;
2403#endif
2404}
2405
2406
2407/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2408static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2409{
2410#ifdef VMSVGA3D_DX
2411 //DEBUG_BREAKPOINT_TEST();
2412 RT_NOREF(cbCmd);
2413 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2414#else
2415 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2416 return VERR_NOT_SUPPORTED;
2417#endif
2418}
2419
2420
2421/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2422static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2423{
2424#ifdef VMSVGA3D_DX
2425 //DEBUG_BREAKPOINT_TEST();
2426 RT_NOREF(cbCmd);
2427 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2428#else
2429 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2430 return VERR_NOT_SUPPORTED;
2431#endif
2432}
2433
2434
2435/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2436static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2437{
2438#ifdef VMSVGA3D_DX
2439 //DEBUG_BREAKPOINT_TEST();
2440 RT_NOREF(cbCmd);
2441 return vmsvga3dDXDefineQuery(pThisCC, idDXContext, pCmd);
2442#else
2443 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2444 return VERR_NOT_SUPPORTED;
2445#endif
2446}
2447
2448
2449/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2450static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2451{
2452#ifdef VMSVGA3D_DX
2453 //DEBUG_BREAKPOINT_TEST();
2454 RT_NOREF(cbCmd);
2455 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext, pCmd);
2456#else
2457 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2458 return VERR_NOT_SUPPORTED;
2459#endif
2460}
2461
2462
2463/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2464static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2465{
2466#ifdef VMSVGA3D_DX
2467 //DEBUG_BREAKPOINT_TEST();
2468 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2469 RT_NOREF(cbCmd);
2470 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2471 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2472 return vmsvga3dDXBindQuery(pThisCC, idDXContext, pCmd, pMob);
2473#else
2474 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2475 return VERR_NOT_SUPPORTED;
2476#endif
2477}
2478
2479
2480/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2481static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2482{
2483#ifdef VMSVGA3D_DX
2484 //DEBUG_BREAKPOINT_TEST();
2485 RT_NOREF(cbCmd);
2486 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext, pCmd);
2487#else
2488 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2489 return VERR_NOT_SUPPORTED;
2490#endif
2491}
2492
2493
2494/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2495static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2496{
2497#ifdef VMSVGA3D_DX
2498 //DEBUG_BREAKPOINT_TEST();
2499 RT_NOREF(cbCmd);
2500 return vmsvga3dDXBeginQuery(pThisCC, idDXContext, pCmd);
2501#else
2502 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2503 return VERR_NOT_SUPPORTED;
2504#endif
2505}
2506
2507
2508/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2509static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2510{
2511#ifdef VMSVGA3D_DX
2512 //DEBUG_BREAKPOINT_TEST();
2513 RT_NOREF(cbCmd);
2514 return vmsvga3dDXEndQuery(pThisCC, idDXContext, pCmd);
2515#else
2516 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2517 return VERR_NOT_SUPPORTED;
2518#endif
2519}
2520
2521
2522/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2523static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2524{
2525#ifdef VMSVGA3D_DX
2526 //DEBUG_BREAKPOINT_TEST();
2527 RT_NOREF(cbCmd);
2528 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext, pCmd);
2529#else
2530 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2531 return VERR_NOT_SUPPORTED;
2532#endif
2533}
2534
2535
2536/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2537static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2538{
2539#ifdef VMSVGA3D_DX
2540 //DEBUG_BREAKPOINT_TEST();
2541 RT_NOREF(cbCmd);
2542 return vmsvga3dDXSetPredication(pThisCC, idDXContext, pCmd);
2543#else
2544 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2545 return VERR_NOT_SUPPORTED;
2546#endif
2547}
2548
2549
2550/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2551static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2552{
2553#ifdef VMSVGA3D_DX
2554 //DEBUG_BREAKPOINT_TEST();
2555 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2556 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2557 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2558#else
2559 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2560 return VERR_NOT_SUPPORTED;
2561#endif
2562}
2563
2564
2565/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2566static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2567{
2568#ifdef VMSVGA3D_DX
2569 //DEBUG_BREAKPOINT_TEST();
2570 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2571 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2572 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2573#else
2574 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2575 return VERR_NOT_SUPPORTED;
2576#endif
2577}
2578
2579
2580/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2581static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2582{
2583#ifdef VMSVGA3D_DX
2584 //DEBUG_BREAKPOINT_TEST();
2585 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2586 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2587 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2588#else
2589 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2590 return VERR_NOT_SUPPORTED;
2591#endif
2592}
2593
2594
2595/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2596static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2597{
2598#ifdef VMSVGA3D_DX
2599 //DEBUG_BREAKPOINT_TEST();
2600 RT_NOREF(cbCmd);
2601 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2602#else
2603 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2604 return VERR_NOT_SUPPORTED;
2605#endif
2606}
2607
2608
2609/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2610static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2611{
2612#ifdef VMSVGA3D_DX
2613 //DEBUG_BREAKPOINT_TEST();
2614 RT_NOREF(cbCmd);
2615 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2616#else
2617 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2618 return VERR_NOT_SUPPORTED;
2619#endif
2620}
2621
2622
2623/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2624static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2625{
2626#ifdef VMSVGA3D_DX
2627 //DEBUG_BREAKPOINT_TEST();
2628 RT_NOREF(cbCmd);
2629 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2630#else
2631 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2632 return VERR_NOT_SUPPORTED;
2633#endif
2634}
2635
2636
2637/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2638static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2639{
2640#ifdef VMSVGA3D_DX
2641 //DEBUG_BREAKPOINT_TEST();
2642 RT_NOREF(cbCmd);
2643 return vmsvga3dDXPredCopy(pThisCC, idDXContext, pCmd);
2644#else
2645 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2646 return VERR_NOT_SUPPORTED;
2647#endif
2648}
2649
2650
2651/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2652static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2653{
2654#ifdef VMSVGA3D_DX
2655 DEBUG_BREAKPOINT_TEST();
2656 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2657 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2658 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2659#else
2660 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2661 return VERR_NOT_SUPPORTED;
2662#endif
2663}
2664
2665
2666/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2667static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2668{
2669#ifdef VMSVGA3D_DX
2670 //DEBUG_BREAKPOINT_TEST();
2671 RT_NOREF(cbCmd);
2672 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2673#else
2674 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2675 return VERR_NOT_SUPPORTED;
2676#endif
2677}
2678
2679
2680/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2681static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2682{
2683#ifdef VMSVGA3D_DX
2684 //DEBUG_BREAKPOINT_TEST();
2685 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2686 RT_NOREF(cbCmd);
2687
2688 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2689 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2690
2691 /* "Inform the device that the guest-contents have been updated." */
2692 SVGAOTableSurfaceEntry entrySurface;
2693 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2694 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2695 if (RT_SUCCESS(rc))
2696 {
2697 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2698 if (pMob)
2699 {
2700 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2701 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2702 /* pCmd->box will be verified by the mapping function. */
2703 RT_UNTRUSTED_VALIDATED_FENCE();
2704
2705 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2706 SVGA3dSurfaceImageId image;
2707 image.sid = pCmd->sid;
2708 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2709
2710 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2711 AssertRC(rc);
2712 }
2713 }
2714
2715 return rc;
2716#else
2717 RT_NOREF(pThisCC, pCmd, cbCmd);
2718 return VERR_NOT_SUPPORTED;
2719#endif
2720}
2721
2722
2723/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2724static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2725{
2726#ifdef VMSVGA3D_DX
2727 //DEBUG_BREAKPOINT_TEST();
2728 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2729 RT_NOREF(cbCmd);
2730
2731 LogFlowFunc(("sid=%u, subResource=%u\n",
2732 pCmd->sid, pCmd->subResource));
2733
2734 /* "Request the device to flush the dirty contents into the guest." */
2735 SVGAOTableSurfaceEntry entrySurface;
2736 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2737 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2738 if (RT_SUCCESS(rc))
2739 {
2740 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2741 if (pMob)
2742 {
2743 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2744 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2745 RT_UNTRUSTED_VALIDATED_FENCE();
2746
2747 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2748 SVGA3dSurfaceImageId image;
2749 image.sid = pCmd->sid;
2750 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2751
2752 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2753 AssertRC(rc);
2754 }
2755 }
2756
2757 return rc;
2758#else
2759 RT_NOREF(pThisCC, pCmd, cbCmd);
2760 return VERR_NOT_SUPPORTED;
2761#endif
2762}
2763
2764
2765/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2766static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2767{
2768#ifdef VMSVGA3D_DX
2769 DEBUG_BREAKPOINT_TEST();
2770 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2771 RT_NOREF(cbCmd);
2772
2773 LogFlowFunc(("sid=%u, subResource=%u\n",
2774 pCmd->sid, pCmd->subResource));
2775
2776 /* "Notify the device that the contents can be lost." */
2777 SVGAOTableSurfaceEntry entrySurface;
2778 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2779 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2780 if (RT_SUCCESS(rc))
2781 {
2782 uint32_t iFace;
2783 uint32_t iMipmap;
2784 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2785 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2786 }
2787
2788 return rc;
2789#else
2790 RT_NOREF(pThisCC, pCmd, cbCmd);
2791 return VERR_NOT_SUPPORTED;
2792#endif
2793}
2794
2795
2796/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2797static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2798{
2799#ifdef VMSVGA3D_DX
2800 //DEBUG_BREAKPOINT_TEST();
2801 RT_NOREF(cbCmd);
2802 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2803#else
2804 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2805 return VERR_NOT_SUPPORTED;
2806#endif
2807}
2808
2809
2810/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2811static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2812{
2813#ifdef VMSVGA3D_DX
2814 //DEBUG_BREAKPOINT_TEST();
2815 RT_NOREF(cbCmd);
2816 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2817#else
2818 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2819 return VERR_NOT_SUPPORTED;
2820#endif
2821}
2822
2823
2824/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2825static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2826{
2827#ifdef VMSVGA3D_DX
2828 //DEBUG_BREAKPOINT_TEST();
2829 RT_NOREF(cbCmd);
2830 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2831#else
2832 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2833 return VERR_NOT_SUPPORTED;
2834#endif
2835}
2836
2837
2838/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2839static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2840{
2841#ifdef VMSVGA3D_DX
2842 //DEBUG_BREAKPOINT_TEST();
2843 RT_NOREF(cbCmd);
2844 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2845#else
2846 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2847 return VERR_NOT_SUPPORTED;
2848#endif
2849}
2850
2851
2852/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2853static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2854{
2855#ifdef VMSVGA3D_DX
2856 //DEBUG_BREAKPOINT_TEST();
2857 RT_NOREF(cbCmd);
2858 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2859 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2860 cmd.sid = pCmd->sid;
2861 cmd.format = pCmd->format;
2862 cmd.resourceDimension = pCmd->resourceDimension;
2863 cmd.mipSlice = pCmd->mipSlice;
2864 cmd.firstArraySlice = pCmd->firstArraySlice;
2865 cmd.arraySize = pCmd->arraySize;
2866 cmd.flags = 0;
2867 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2868#else
2869 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2870 return VERR_NOT_SUPPORTED;
2871#endif
2872}
2873
2874
2875/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2876static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2877{
2878#ifdef VMSVGA3D_DX
2879 //DEBUG_BREAKPOINT_TEST();
2880 RT_NOREF(cbCmd);
2881 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2882#else
2883 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2884 return VERR_NOT_SUPPORTED;
2885#endif
2886}
2887
2888
2889/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2890static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2891{
2892#ifdef VMSVGA3D_DX
2893 //DEBUG_BREAKPOINT_TEST();
2894 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2895 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2896 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2897#else
2898 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2899 return VERR_NOT_SUPPORTED;
2900#endif
2901}
2902
2903
2904/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2905static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2906{
2907#ifdef VMSVGA3D_DX
2908 //DEBUG_BREAKPOINT_TEST();
2909 RT_NOREF(cbCmd);
2910 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext, pCmd);
2911#else
2912 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2913 return VERR_NOT_SUPPORTED;
2914#endif
2915}
2916
2917
2918/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2919static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2920{
2921#ifdef VMSVGA3D_DX
2922 //DEBUG_BREAKPOINT_TEST();
2923 RT_NOREF(cbCmd);
2924 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2925#else
2926 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2927 return VERR_NOT_SUPPORTED;
2928#endif
2929}
2930
2931
2932/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2933static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2934{
2935#ifdef VMSVGA3D_DX
2936 //DEBUG_BREAKPOINT_TEST();
2937 RT_NOREF(cbCmd);
2938 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext, pCmd);
2939#else
2940 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2941 return VERR_NOT_SUPPORTED;
2942#endif
2943}
2944
2945
2946/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2947static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2948{
2949#ifdef VMSVGA3D_DX
2950 //DEBUG_BREAKPOINT_TEST();
2951 RT_NOREF(cbCmd);
2952 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2953#else
2954 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2955 return VERR_NOT_SUPPORTED;
2956#endif
2957}
2958
2959
2960/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2961static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2962{
2963#ifdef VMSVGA3D_DX
2964 //DEBUG_BREAKPOINT_TEST();
2965 RT_NOREF(cbCmd);
2966 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd);
2967#else
2968 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2969 return VERR_NOT_SUPPORTED;
2970#endif
2971}
2972
2973
2974/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2975static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2976{
2977#ifdef VMSVGA3D_DX
2978 //DEBUG_BREAKPOINT_TEST();
2979 RT_NOREF(cbCmd);
2980 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2981#else
2982 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2983 return VERR_NOT_SUPPORTED;
2984#endif
2985}
2986
2987
2988/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2989static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2990{
2991#ifdef VMSVGA3D_DX
2992 //DEBUG_BREAKPOINT_TEST();
2993 RT_NOREF(cbCmd);
2994 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext, pCmd);
2995#else
2996 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2997 return VERR_NOT_SUPPORTED;
2998#endif
2999}
3000
3001
3002/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3003static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3004{
3005#ifdef VMSVGA3D_DX
3006 //DEBUG_BREAKPOINT_TEST();
3007 RT_NOREF(cbCmd);
3008 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3009#else
3010 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3011 return VERR_NOT_SUPPORTED;
3012#endif
3013}
3014
3015
3016/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3017static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3018{
3019#ifdef VMSVGA3D_DX
3020 //DEBUG_BREAKPOINT_TEST();
3021 RT_NOREF(cbCmd);
3022 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext, pCmd);
3023#else
3024 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3025 return VERR_NOT_SUPPORTED;
3026#endif
3027}
3028
3029
3030/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3031static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3032{
3033#ifdef VMSVGA3D_DX
3034 //DEBUG_BREAKPOINT_TEST();
3035 RT_NOREF(cbCmd);
3036 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3037#else
3038 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3039 return VERR_NOT_SUPPORTED;
3040#endif
3041}
3042
3043
3044/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3045static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3046{
3047#ifdef VMSVGA3D_DX
3048 //DEBUG_BREAKPOINT_TEST();
3049 RT_NOREF(cbCmd);
3050 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3051#else
3052 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3053 return VERR_NOT_SUPPORTED;
3054#endif
3055}
3056
3057
3058/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3059static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3060{
3061#ifdef VMSVGA3D_DX
3062 //DEBUG_BREAKPOINT_TEST();
3063 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3064 RT_NOREF(idDXContext, cbCmd);
3065 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3066 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3067 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3068#else
3069 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3070 return VERR_NOT_SUPPORTED;
3071#endif
3072}
3073
3074
3075/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3076static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3077{
3078#ifdef VMSVGA3D_DX
3079 //DEBUG_BREAKPOINT_TEST();
3080 RT_NOREF(cbCmd);
3081 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3082#else
3083 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3084 return VERR_NOT_SUPPORTED;
3085#endif
3086}
3087
3088
3089/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3090static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3091{
3092#ifdef VMSVGA3D_DX
3093 //DEBUG_BREAKPOINT_TEST();
3094 RT_NOREF(cbCmd);
3095 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3096#else
3097 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3098 return VERR_NOT_SUPPORTED;
3099#endif
3100}
3101
3102
3103/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3104static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3105{
3106#ifdef VMSVGA3D_DX
3107 //DEBUG_BREAKPOINT_TEST();
3108 RT_NOREF(cbCmd);
3109 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3110#else
3111 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3112 return VERR_NOT_SUPPORTED;
3113#endif
3114}
3115
3116
3117/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3118static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3119{
3120#ifdef VMSVGA3D_DX
3121 //DEBUG_BREAKPOINT_TEST();
3122 RT_NOREF(cbCmd);
3123 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3124 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3125 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3126 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3127#else
3128 RT_NOREF(pThisCC, pCmd, cbCmd);
3129 return VERR_NOT_SUPPORTED;
3130#endif
3131}
3132
3133
3134/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3135static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3136{
3137#ifdef VMSVGA3D_DX
3138 //DEBUG_BREAKPOINT_TEST();
3139 RT_NOREF(idDXContext, cbCmd);
3140 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3141#else
3142 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3143 return VERR_NOT_SUPPORTED;
3144#endif
3145}
3146
3147
3148/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3149static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3150{
3151#ifdef VMSVGA3D_DX
3152 //DEBUG_BREAKPOINT_TEST();
3153 RT_NOREF(idDXContext, cbCmd);
3154
3155 int rc;
3156
3157 /** @todo Backend should o the copy is both buffers have a hardware resource. */
3158 SVGA3dSurfaceImageId imageBufferSrc;
3159 imageBufferSrc.sid = pCmd->src;
3160 imageBufferSrc.face = 0;
3161 imageBufferSrc.mipmap = 0;
3162
3163 SVGA3dSurfaceImageId imageBufferDest;
3164 imageBufferDest.sid = pCmd->dest;
3165 imageBufferDest.face = 0;
3166 imageBufferDest.mipmap = 0;
3167
3168 /*
3169 * Map the source buffer.
3170 */
3171 VMSVGA3D_MAPPED_SURFACE mapBufferSrc;
3172 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferSrc, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBufferSrc);
3173 if (RT_SUCCESS(rc))
3174 {
3175 /*
3176 * Map the destination buffer.
3177 */
3178 VMSVGA3D_MAPPED_SURFACE mapBufferDest;
3179 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferDest, NULL, VMSVGA3D_SURFACE_MAP_WRITE, &mapBufferDest);
3180 if (RT_SUCCESS(rc))
3181 {
3182 /*
3183 * Copy the source buffer to the destination.
3184 */
3185 uint8_t const *pu8BufferSrc = (uint8_t *)mapBufferSrc.pvData;
3186 uint32_t const cbBufferSrc = mapBufferSrc.cbRow;
3187
3188 uint8_t *pu8BufferDest = (uint8_t *)mapBufferDest.pvData;
3189 uint32_t const cbBufferDest = mapBufferDest.cbRow;
3190
3191 if ( pCmd->srcX < cbBufferSrc
3192 && pCmd->width <= cbBufferSrc- pCmd->srcX
3193 && pCmd->destX < cbBufferDest
3194 && pCmd->width <= cbBufferDest - pCmd->destX)
3195 {
3196 RT_UNTRUSTED_VALIDATED_FENCE();
3197
3198 memcpy(&pu8BufferDest[pCmd->destX], &pu8BufferSrc[pCmd->srcX], pCmd->width);
3199 }
3200 else
3201 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3202
3203 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferDest, &mapBufferDest, true);
3204 }
3205
3206 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferSrc, &mapBufferSrc, false);
3207 }
3208
3209 return rc;
3210#else
3211 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3212 return VERR_NOT_SUPPORTED;
3213#endif
3214}
3215
3216
3217/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3218static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3219{
3220#ifdef VMSVGA3D_DX
3221 //DEBUG_BREAKPOINT_TEST();
3222 RT_NOREF(cbCmd);
3223
3224 /* Plan:
3225 * - map the buffer;
3226 * - map the surface;
3227 * - copy from buffer map to the surface map.
3228 */
3229
3230 int rc;
3231
3232 SVGA3dSurfaceImageId imageBuffer;
3233 imageBuffer.sid = pCmd->srcSid;
3234 imageBuffer.face = 0;
3235 imageBuffer.mipmap = 0;
3236
3237 SVGA3dSurfaceImageId imageSurface;
3238 imageSurface.sid = pCmd->destSid;
3239 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3240 AssertRCReturn(rc, rc);
3241
3242 /*
3243 * Map the buffer.
3244 */
3245 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3246 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3247 if (RT_SUCCESS(rc))
3248 {
3249 /*
3250 * Map the surface.
3251 */
3252 VMSVGA3D_MAPPED_SURFACE mapSurface;
3253 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3254 if (RT_SUCCESS(rc))
3255 {
3256 /*
3257 * Copy the mapped buffer to the surface. "Raw byte wise transfer"
3258 */
3259 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3260 uint32_t const cbBuffer = mapBuffer.cbRow;
3261
3262 if (pCmd->srcOffset <= cbBuffer)
3263 {
3264 RT_UNTRUSTED_VALIDATED_FENCE();
3265 uint8_t const *pu8BufferBegin = pu8Buffer;
3266 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3267
3268 pu8Buffer += pCmd->srcOffset;
3269
3270 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3271
3272 uint32_t const cbRowCopy = RT_MIN(pCmd->srcPitch, mapSurface.cbRow);
3273 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3274 {
3275 uint8_t const *pu8BufferRow = pu8Buffer;
3276 uint8_t *pu8SurfaceRow = pu8Surface;
3277 for (uint32_t iRow = 0; iRow < mapSurface.cRows; ++iRow)
3278 {
3279 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3280 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3281 && (uintptr_t)pu8BufferRow < (uintptr_t)(pu8BufferRow + cbRowCopy)
3282 && (uintptr_t)(pu8BufferRow + cbRowCopy) > (uintptr_t)pu8BufferBegin
3283 && (uintptr_t)(pu8BufferRow + cbRowCopy) <= (uintptr_t)pu8BufferEnd,
3284 rc = VERR_INVALID_PARAMETER);
3285
3286 memcpy(pu8SurfaceRow, pu8BufferRow, cbRowCopy);
3287
3288 pu8SurfaceRow += mapSurface.cbRowPitch;
3289 pu8BufferRow += pCmd->srcPitch;
3290 }
3291
3292 pu8Buffer += pCmd->srcSlicePitch;
3293 pu8Surface += mapSurface.cbDepthPitch;
3294 }
3295 }
3296 else
3297 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3298
3299 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3300 }
3301
3302 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3303 }
3304
3305 return rc;
3306#else
3307 RT_NOREF(pThisCC, pCmd, cbCmd);
3308 return VERR_NOT_SUPPORTED;
3309#endif
3310}
3311
3312
3313/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3314static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3315{
3316#ifdef VMSVGA3D_DX
3317 DEBUG_BREAKPOINT_TEST();
3318 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3319 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3320 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3321#else
3322 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3323 return VERR_NOT_SUPPORTED;
3324#endif
3325}
3326
3327
3328/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3329static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3330{
3331#ifdef VMSVGA3D_DX
3332 DEBUG_BREAKPOINT_TEST();
3333 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3334 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3335 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3336#else
3337 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3338 return VERR_NOT_SUPPORTED;
3339#endif
3340}
3341
3342
3343/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3344static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3345{
3346#ifdef VMSVGA3D_DX
3347 //DEBUG_BREAKPOINT_TEST();
3348 RT_NOREF(cbCmd);
3349 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext, pCmd);
3350#else
3351 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3352 return VERR_NOT_SUPPORTED;
3353#endif
3354}
3355
3356
3357/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3358static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3359{
3360#ifdef VMSVGA3D_DX
3361 //DEBUG_BREAKPOINT_TEST();
3362 RT_NOREF(cbCmd);
3363 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext, pCmd);
3364#else
3365 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3366 return VERR_NOT_SUPPORTED;
3367#endif
3368}
3369
3370
3371/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3372static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3373{
3374#ifdef VMSVGA3D_DX
3375 //DEBUG_BREAKPOINT_TEST();
3376 RT_NOREF(idDXContext, cbCmd);
3377
3378 /* This command is executed in a context: "The context is implied from the command buffer header."
3379 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3380 */
3381 SVGA3dCmdDXTransferFromBuffer cmd;
3382 cmd.srcSid = pCmd->srcSid;
3383 cmd.srcOffset = pCmd->srcOffset;
3384 cmd.srcPitch = pCmd->srcPitch;
3385 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3386 cmd.destSid = pCmd->destSid;
3387 cmd.destSubResource = pCmd->destSubResource;
3388 cmd.destBox = pCmd->destBox;
3389 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3390#else
3391 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3392 return VERR_NOT_SUPPORTED;
3393#endif
3394}
3395
3396
3397/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3398static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3399{
3400#ifdef VMSVGA3D_DX
3401 //DEBUG_BREAKPOINT_TEST();
3402 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3403 RT_NOREF(cbCmd);
3404
3405 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobId);
3406 ASSERT_GUEST_RETURN(pMob, VERR_INVALID_PARAMETER);
3407
3408 int rc = vmsvgaR3MobWrite(pSvgaR3State, pMob, pCmd->mobOffset, &pCmd->value, sizeof(pCmd->value));
3409 ASSERT_GUEST_RETURN(RT_SUCCESS(rc), rc);
3410
3411 return VINF_SUCCESS;
3412#else
3413 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3414 return VERR_NOT_SUPPORTED;
3415#endif
3416}
3417
3418
3419/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3420static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3421{
3422#ifdef VMSVGA3D_DX
3423 DEBUG_BREAKPOINT_TEST();
3424 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3425 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3426 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3427#else
3428 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3429 return VERR_NOT_SUPPORTED;
3430#endif
3431}
3432
3433
3434/* SVGA_3D_CMD_DX_HINT 1218 */
3435static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3436{
3437#ifdef VMSVGA3D_DX
3438 DEBUG_BREAKPOINT_TEST();
3439 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3440 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3441 return vmsvga3dDXHint(pThisCC, idDXContext);
3442#else
3443 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3444 return VERR_NOT_SUPPORTED;
3445#endif
3446}
3447
3448
3449/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3450static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3451{
3452#ifdef VMSVGA3D_DX
3453 DEBUG_BREAKPOINT_TEST();
3454 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3455 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3456 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3457#else
3458 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3459 return VERR_NOT_SUPPORTED;
3460#endif
3461}
3462
3463
3464/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3465static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3466{
3467#ifdef VMSVGA3D_DX
3468 DEBUG_BREAKPOINT_TEST();
3469 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3470 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3471 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3472#else
3473 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3474 return VERR_NOT_SUPPORTED;
3475#endif
3476}
3477
3478
3479/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3480static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3481{
3482#ifdef VMSVGA3D_DX
3483 DEBUG_BREAKPOINT_TEST();
3484 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3485 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3486 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3487#else
3488 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3489 return VERR_NOT_SUPPORTED;
3490#endif
3491}
3492
3493
3494/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3495static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3496{
3497#ifdef VMSVGA3D_DX
3498 DEBUG_BREAKPOINT_TEST();
3499 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3500 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3501 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3502#else
3503 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3504 return VERR_NOT_SUPPORTED;
3505#endif
3506}
3507
3508
3509/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3510static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3511{
3512#ifdef VMSVGA3D_DX
3513 DEBUG_BREAKPOINT_TEST();
3514 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3515 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3516 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3517#else
3518 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3519 return VERR_NOT_SUPPORTED;
3520#endif
3521}
3522
3523
3524/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3525static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3526{
3527#ifdef VMSVGA3D_DX
3528 DEBUG_BREAKPOINT_TEST();
3529 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3530 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3531 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3532#else
3533 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3534 return VERR_NOT_SUPPORTED;
3535#endif
3536}
3537
3538
3539/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3540static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3541{
3542#ifdef VMSVGA3D_DX
3543 DEBUG_BREAKPOINT_TEST();
3544 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3545 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3546 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3547#else
3548 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3549 return VERR_NOT_SUPPORTED;
3550#endif
3551}
3552
3553
3554/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3555static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3556{
3557#ifdef VMSVGA3D_DX
3558 DEBUG_BREAKPOINT_TEST();
3559 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3560 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3561 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3562#else
3563 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3564 return VERR_NOT_SUPPORTED;
3565#endif
3566}
3567
3568
3569/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3570static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3571{
3572#ifdef VMSVGA3D_DX
3573 DEBUG_BREAKPOINT_TEST();
3574 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3575 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3576 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3577#else
3578 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3579 return VERR_NOT_SUPPORTED;
3580#endif
3581}
3582
3583
3584/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3585static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3586{
3587#ifdef VMSVGA3D_DX
3588 DEBUG_BREAKPOINT_TEST();
3589 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3590 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3591 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3592#else
3593 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3594 return VERR_NOT_SUPPORTED;
3595#endif
3596}
3597
3598
3599/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3600static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3601{
3602#ifdef VMSVGA3D_DX
3603 DEBUG_BREAKPOINT_TEST();
3604 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3605 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3606 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3607#else
3608 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3609 return VERR_NOT_SUPPORTED;
3610#endif
3611}
3612
3613
3614/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3615static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3616{
3617#ifdef VMSVGA3D_DX
3618 DEBUG_BREAKPOINT_TEST();
3619 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3620 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3621 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3622#else
3623 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3624 return VERR_NOT_SUPPORTED;
3625#endif
3626}
3627
3628
3629/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3630static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd)
3631{
3632#ifdef VMSVGA3D_DX
3633 DEBUG_BREAKPOINT_TEST();
3634 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3635
3636 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
3637 SVGAOTableSurfaceEntry entry;
3638 RT_ZERO(entry);
3639 entry.format = pCmd->format;
3640 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
3641 entry.numMipLevels = pCmd->numMipLevels;
3642 entry.multisampleCount = pCmd->multisampleCount;
3643 entry.autogenFilter = pCmd->autogenFilter;
3644 entry.size = pCmd->size;
3645 entry.mobid = SVGA_ID_INVALID;
3646 entry.arraySize = pCmd->arraySize;
3647 // entry.mobPitch = 0;
3648 // entry.mobPitch = 0;
3649 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
3650 // entry.multisamplePattern = 0;
3651 // entry.qualityLevel = 0;
3652 // entry.bufferByteStride = 0;
3653 // entry.minLOD = 0;
3654
3655 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
3656 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
3657 if (RT_SUCCESS(rc))
3658 {
3659 /* Create the host surface. */
3660 /** @todo SVGAOTableSurfaceEntry as input parameter? */
3661 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
3662 pCmd->multisampleCount, pCmd->autogenFilter,
3663 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
3664 }
3665 return rc;
3666#else
3667 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3668 return VERR_NOT_SUPPORTED;
3669#endif
3670}
3671
3672
3673/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3674static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3675{
3676#ifdef VMSVGA3D_DX
3677 DEBUG_BREAKPOINT_TEST();
3678 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3679 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3680 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3681#else
3682 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3683 return VERR_NOT_SUPPORTED;
3684#endif
3685}
3686
3687
3688/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3689static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3690{
3691#ifdef VMSVGA3D_DX
3692 DEBUG_BREAKPOINT_TEST();
3693 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3694 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3695 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3696#else
3697 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3698 return VERR_NOT_SUPPORTED;
3699#endif
3700}
3701
3702
3703/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3704static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3705{
3706#ifdef VMSVGA3D_DX
3707 DEBUG_BREAKPOINT_TEST();
3708 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3709 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3710 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3711#else
3712 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3713 return VERR_NOT_SUPPORTED;
3714#endif
3715}
3716
3717
3718/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3719static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3720{
3721#ifdef VMSVGA3D_DX
3722 DEBUG_BREAKPOINT_TEST();
3723 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3724 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3725 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3726#else
3727 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3728 return VERR_NOT_SUPPORTED;
3729#endif
3730}
3731
3732
3733/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3734static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3735{
3736#ifdef VMSVGA3D_DX
3737 DEBUG_BREAKPOINT_TEST();
3738 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3739 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3740 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3741#else
3742 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3743 return VERR_NOT_SUPPORTED;
3744#endif
3745}
3746
3747
3748/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3749static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3750{
3751#ifdef VMSVGA3D_DX
3752 //DEBUG_BREAKPOINT_TEST();
3753 RT_NOREF(cbCmd);
3754 return vmsvga3dDXDefineUAView(pThisCC, idDXContext, pCmd);
3755#else
3756 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3757 return VERR_NOT_SUPPORTED;
3758#endif
3759}
3760
3761
3762/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3763static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3764{
3765#ifdef VMSVGA3D_DX
3766 //DEBUG_BREAKPOINT_TEST();
3767 RT_NOREF(cbCmd);
3768 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext, pCmd);
3769#else
3770 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3771 return VERR_NOT_SUPPORTED;
3772#endif
3773}
3774
3775
3776/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3777static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3778{
3779#ifdef VMSVGA3D_DX
3780 DEBUG_BREAKPOINT_TEST();
3781 RT_NOREF(cbCmd);
3782 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext, pCmd);
3783#else
3784 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3785 return VERR_NOT_SUPPORTED;
3786#endif
3787}
3788
3789
3790/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3791static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3792{
3793#ifdef VMSVGA3D_DX
3794 DEBUG_BREAKPOINT_TEST();
3795 RT_NOREF(cbCmd);
3796 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext, pCmd);
3797#else
3798 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3799 return VERR_NOT_SUPPORTED;
3800#endif
3801}
3802
3803
3804/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3805static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3806{
3807#ifdef VMSVGA3D_DX
3808 //DEBUG_BREAKPOINT_TEST();
3809 RT_NOREF(cbCmd);
3810 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext, pCmd);
3811#else
3812 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3813 return VERR_NOT_SUPPORTED;
3814#endif
3815}
3816
3817
3818/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3819static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3820{
3821#ifdef VMSVGA3D_DX
3822 //DEBUG_BREAKPOINT_TEST();
3823 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
3824 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
3825 return vmsvga3dDXSetUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
3826#else
3827 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3828 return VERR_NOT_SUPPORTED;
3829#endif
3830}
3831
3832
3833/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3834static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3835{
3836#ifdef VMSVGA3D_DX
3837 //DEBUG_BREAKPOINT_TEST();
3838 RT_NOREF(cbCmd);
3839 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd);
3840#else
3841 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3842 return VERR_NOT_SUPPORTED;
3843#endif
3844}
3845
3846
3847/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3848static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3849{
3850#ifdef VMSVGA3D_DX
3851 //DEBUG_BREAKPOINT_TEST();
3852 RT_NOREF(cbCmd);
3853 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd);
3854#else
3855 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3856 return VERR_NOT_SUPPORTED;
3857#endif
3858}
3859
3860
3861/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3862static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3863{
3864#ifdef VMSVGA3D_DX
3865 //DEBUG_BREAKPOINT_TEST();
3866 RT_NOREF(cbCmd);
3867 return vmsvga3dDXDispatch(pThisCC, idDXContext, pCmd);
3868#else
3869 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3870 return VERR_NOT_SUPPORTED;
3871#endif
3872}
3873
3874
3875/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3876static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3877{
3878#ifdef VMSVGA3D_DX
3879 DEBUG_BREAKPOINT_TEST();
3880 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3881 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3882 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3883#else
3884 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3885 return VERR_NOT_SUPPORTED;
3886#endif
3887}
3888
3889
3890/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3891static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3892{
3893#ifdef VMSVGA3D_DX
3894 DEBUG_BREAKPOINT_TEST();
3895 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3896 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3897 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3898#else
3899 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3900 return VERR_NOT_SUPPORTED;
3901#endif
3902}
3903
3904
3905/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3906static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3907{
3908#ifdef VMSVGA3D_DX
3909 DEBUG_BREAKPOINT_TEST();
3910 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3911 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3912 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3913#else
3914 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3915 return VERR_NOT_SUPPORTED;
3916#endif
3917}
3918
3919
3920/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3921static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3922{
3923#ifdef VMSVGA3D_DX
3924 DEBUG_BREAKPOINT_TEST();
3925 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3926 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3927 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3928#else
3929 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3930 return VERR_NOT_SUPPORTED;
3931#endif
3932}
3933
3934
3935/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3936static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3937{
3938#ifdef VMSVGA3D_DX
3939 //DEBUG_BREAKPOINT_TEST();
3940 RT_NOREF(cbCmd);
3941 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext, pCmd);
3942#else
3943 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3944 return VERR_NOT_SUPPORTED;
3945#endif
3946}
3947
3948
3949/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3950static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3951{
3952#ifdef VMSVGA3D_DX
3953 DEBUG_BREAKPOINT_TEST();
3954 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3955 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3956 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3957#else
3958 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3959 return VERR_NOT_SUPPORTED;
3960#endif
3961}
3962
3963
3964/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3965static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3966{
3967#ifdef VMSVGA3D_DX
3968 DEBUG_BREAKPOINT_TEST();
3969 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3970 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3971 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3972#else
3973 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3974 return VERR_NOT_SUPPORTED;
3975#endif
3976}
3977
3978
3979/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3980static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3981{
3982#ifdef VMSVGA3D_DX
3983 DEBUG_BREAKPOINT_TEST();
3984 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3985 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3986 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3987#else
3988 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3989 return VERR_NOT_SUPPORTED;
3990#endif
3991}
3992
3993
3994/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3995static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3996{
3997#ifdef VMSVGA3D_DX
3998 DEBUG_BREAKPOINT_TEST();
3999 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4000 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4001 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
4002#else
4003 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4004 return VERR_NOT_SUPPORTED;
4005#endif
4006}
4007
4008
4009/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
4010static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
4011{
4012#ifdef VMSVGA3D_DX
4013 DEBUG_BREAKPOINT_TEST();
4014 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4015 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4016 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
4017#else
4018 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4019 return VERR_NOT_SUPPORTED;
4020#endif
4021}
4022
4023
4024/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
4025static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
4026{
4027#ifdef VMSVGA3D_DX
4028 DEBUG_BREAKPOINT_TEST();
4029 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4030 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4031 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
4032#else
4033 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4034 return VERR_NOT_SUPPORTED;
4035#endif
4036}
4037
4038
4039/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
4040static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd)
4041{
4042#ifdef VMSVGA3D_DX
4043 //DEBUG_BREAKPOINT_TEST();
4044 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4045
4046 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
4047 SVGAOTableSurfaceEntry entry;
4048 RT_ZERO(entry);
4049 entry.format = pCmd->format;
4050 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
4051 entry.numMipLevels = pCmd->numMipLevels;
4052 entry.multisampleCount = pCmd->multisampleCount;
4053 entry.autogenFilter = pCmd->autogenFilter;
4054 entry.size = pCmd->size;
4055 entry.mobid = SVGA_ID_INVALID;
4056 entry.arraySize = pCmd->arraySize;
4057 // entry.mobPitch = 0;
4058 // entry.mobPitch = 0;
4059 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
4060 // entry.multisamplePattern = 0;
4061 // entry.qualityLevel = 0;
4062 entry.bufferByteStride = pCmd->bufferByteStride;
4063 // entry.minLOD = 0;
4064
4065 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
4066 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
4067 if (RT_SUCCESS(rc))
4068 {
4069 /* Create the host surface. */
4070 /** @todo SVGAOTableSurfaceEntry as input parameter? */
4071 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
4072 pCmd->multisampleCount, pCmd->autogenFilter,
4073 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
4074 }
4075 return rc;
4076#else
4077 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4078 return VERR_NOT_SUPPORTED;
4079#endif
4080}
4081
4082
4083/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
4084static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
4085{
4086#ifdef VMSVGA3D_DX
4087 //DEBUG_BREAKPOINT_TEST();
4088 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
4089 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
4090 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
4091#else
4092 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4093 return VERR_NOT_SUPPORTED;
4094#endif
4095}
4096
4097
4098/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
4099static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
4100{
4101#ifdef VMSVGA3D_DX
4102 DEBUG_BREAKPOINT_TEST();
4103 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4104 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4105 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4106#else
4107 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4108 return VERR_NOT_SUPPORTED;
4109#endif
4110}
4111
4112
4113/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4114static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4115{
4116#ifdef VMSVGA3D_DX
4117 //DEBUG_BREAKPOINT_TEST();
4118 RT_NOREF(cbCmd);
4119 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4120#else
4121 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4122 return VERR_NOT_SUPPORTED;
4123#endif
4124}
4125
4126
4127/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4128static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4129{
4130#ifdef VMSVGA3D_DX
4131 //DEBUG_BREAKPOINT_TEST();
4132 RT_NOREF(cbCmd);
4133 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd);
4134#else
4135 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4136 return VERR_NOT_SUPPORTED;
4137#endif
4138}
4139
4140
4141/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4142static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4143{
4144#ifdef VMSVGA3D_DX
4145 DEBUG_BREAKPOINT_TEST();
4146 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4147 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4148 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4149#else
4150 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4151 return VERR_NOT_SUPPORTED;
4152#endif
4153}
4154
4155
4156/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4157static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4158{
4159#ifdef VMSVGA3D_DX
4160 //DEBUG_BREAKPOINT_TEST();
4161 RT_NOREF(cbCmd);
4162 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext, pCmd);
4163#else
4164 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4165 return VERR_NOT_SUPPORTED;
4166#endif
4167}
4168
4169
4170/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4171static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4172{
4173#ifdef VMSVGA3D_DX
4174 DEBUG_BREAKPOINT_TEST();
4175 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4176 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4177 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4178#else
4179 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4180 return VERR_NOT_SUPPORTED;
4181#endif
4182}
4183
4184
4185/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4186static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4187{
4188#ifdef VMSVGA3D_DX
4189 DEBUG_BREAKPOINT_TEST();
4190 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4191 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4192 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4193#else
4194 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4195 return VERR_NOT_SUPPORTED;
4196#endif
4197}
4198
4199
4200/* SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION 1083 */
4201static int vmsvga3dCmdVBDXClearRenderTargetViewRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdVBDXClearRenderTargetViewRegion *pCmd, uint32_t cbCmd)
4202{
4203#ifdef VMSVGA3D_DX
4204 //DEBUG_BREAKPOINT_TEST();
4205 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4206 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4207 return vmsvga3dVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cRect, paRect);
4208#else
4209 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4210 return VERR_NOT_SUPPORTED;
4211#endif
4212}
4213
4214
4215/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4216 * Check that the 3D command has at least a_cbMin of payload bytes after the
4217 * header. Will break out of the switch if it doesn't.
4218 */
4219# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4220 if (1) { \
4221 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4222 RT_UNTRUSTED_VALIDATED_FENCE(); \
4223 } else do {} while (0)
4224
4225# define VMSVGA_3D_CMD_NOTIMPL() \
4226 if (1) { \
4227 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4228 } else do {} while (0)
4229
4230/** SVGA_3D_CMD_* handler.
4231 * This function parses the command and calls the corresponding command handler.
4232 *
4233 * @param pThis The shared VGA/VMSVGA state.
4234 * @param pThisCC The VGA/VMSVGA state for the current context.
4235 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4236 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4237 * @param cbCmd Size of the command in bytes.
4238 * @param pvCmd Pointer to the command.
4239 * @returns VBox status code if an error was detected parsing a command.
4240 */
4241int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4242{
4243 if (enmCmdId > SVGA_3D_CMD_MAX)
4244 {
4245 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4246 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4247 }
4248
4249 int rcParse = VINF_SUCCESS;
4250 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4251
4252 switch (enmCmdId)
4253 {
4254 case SVGA_3D_CMD_SURFACE_DEFINE:
4255 {
4256 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4257 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4258 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4259
4260 SVGA3dCmdDefineSurface_v2 cmd;
4261 cmd.sid = pCmd->sid;
4262 cmd.surfaceFlags = pCmd->surfaceFlags;
4263 cmd.format = pCmd->format;
4264 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4265 cmd.multisampleCount = 0;
4266 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4267
4268 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4269 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4270# ifdef DEBUG_GMR_ACCESS
4271 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4272# endif
4273 break;
4274 }
4275
4276 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4277 {
4278 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4279 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4280 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4281
4282 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4283 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4284# ifdef DEBUG_GMR_ACCESS
4285 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4286# endif
4287 break;
4288 }
4289
4290 case SVGA_3D_CMD_SURFACE_DESTROY:
4291 {
4292 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4293 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4294 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4295
4296 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4297 break;
4298 }
4299
4300 case SVGA_3D_CMD_SURFACE_COPY:
4301 {
4302 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4303 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4304 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4305
4306 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4307 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4308 break;
4309 }
4310
4311 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4312 {
4313 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4314 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4315 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4316
4317 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4318 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4319 break;
4320 }
4321
4322 case SVGA_3D_CMD_SURFACE_DMA:
4323 {
4324 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4325 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4326 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4327
4328 uint64_t u64NanoTS = 0;
4329 if (LogRelIs3Enabled())
4330 u64NanoTS = RTTimeNanoTS();
4331 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4332 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4333 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4334 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4335 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4336 if (LogRelIs3Enabled())
4337 {
4338 if (cCopyBoxes)
4339 {
4340 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4341 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4342 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4343 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4344 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4345 }
4346 }
4347 break;
4348 }
4349
4350 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4351 {
4352 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4353 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4354 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4355
4356 static uint64_t u64FrameStartNanoTS = 0;
4357 static uint64_t u64ElapsedPerSecNano = 0;
4358 static int cFrames = 0;
4359 uint64_t u64NanoTS = 0;
4360 if (LogRelIs3Enabled())
4361 u64NanoTS = RTTimeNanoTS();
4362 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4363 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4364 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4365 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4366 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4367 if (LogRelIs3Enabled())
4368 {
4369 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4370 u64ElapsedPerSecNano += u64ElapsedNano;
4371
4372 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4373 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4374 (u64ElapsedNano) / 1000ULL, cRects,
4375 pFirstRect->left, pFirstRect->top,
4376 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4377
4378 ++cFrames;
4379 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4380 {
4381 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4382 cFrames, u64ElapsedPerSecNano / 1000ULL));
4383 u64FrameStartNanoTS = u64NanoTS;
4384 cFrames = 0;
4385 u64ElapsedPerSecNano = 0;
4386 }
4387 }
4388 break;
4389 }
4390
4391 case SVGA_3D_CMD_CONTEXT_DEFINE:
4392 {
4393 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4394 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4395 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4396
4397 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4398 break;
4399 }
4400
4401 case SVGA_3D_CMD_CONTEXT_DESTROY:
4402 {
4403 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4404 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4405 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4406
4407 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4408 break;
4409 }
4410
4411 case SVGA_3D_CMD_SETTRANSFORM:
4412 {
4413 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4414 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4415 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4416
4417 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4418 break;
4419 }
4420
4421 case SVGA_3D_CMD_SETZRANGE:
4422 {
4423 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4424 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4425 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4426
4427 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4428 break;
4429 }
4430
4431 case SVGA_3D_CMD_SETRENDERSTATE:
4432 {
4433 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4434 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4435 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4436
4437 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4438 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4439 break;
4440 }
4441
4442 case SVGA_3D_CMD_SETRENDERTARGET:
4443 {
4444 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4445 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4446 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4447
4448 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4449 break;
4450 }
4451
4452 case SVGA_3D_CMD_SETTEXTURESTATE:
4453 {
4454 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4455 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4456 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4457
4458 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4459 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4460 break;
4461 }
4462
4463 case SVGA_3D_CMD_SETMATERIAL:
4464 {
4465 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4466 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4467 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4468
4469 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4470 break;
4471 }
4472
4473 case SVGA_3D_CMD_SETLIGHTDATA:
4474 {
4475 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4476 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4477 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4478
4479 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4480 break;
4481 }
4482
4483 case SVGA_3D_CMD_SETLIGHTENABLED:
4484 {
4485 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4486 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4487 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4488
4489 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4490 break;
4491 }
4492
4493 case SVGA_3D_CMD_SETVIEWPORT:
4494 {
4495 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4496 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4497 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4498
4499 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4500 break;
4501 }
4502
4503 case SVGA_3D_CMD_SETCLIPPLANE:
4504 {
4505 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4506 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4507 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4508
4509 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4510 break;
4511 }
4512
4513 case SVGA_3D_CMD_CLEAR:
4514 {
4515 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4516 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4517 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4518
4519 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4520 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4521 break;
4522 }
4523
4524 case SVGA_3D_CMD_PRESENT:
4525 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4526 {
4527 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4528 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4529 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4530 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4531 else
4532 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4533
4534 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4535 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4536 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4537 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4538 break;
4539 }
4540
4541 case SVGA_3D_CMD_SHADER_DEFINE:
4542 {
4543 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4544 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4545 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4546
4547 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4548 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4549 break;
4550 }
4551
4552 case SVGA_3D_CMD_SHADER_DESTROY:
4553 {
4554 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4555 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4556 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4557
4558 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4559 break;
4560 }
4561
4562 case SVGA_3D_CMD_SET_SHADER:
4563 {
4564 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4565 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4566 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4567
4568 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4569 break;
4570 }
4571
4572 case SVGA_3D_CMD_SET_SHADER_CONST:
4573 {
4574 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4575 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4576 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4577
4578 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4579 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4580 break;
4581 }
4582
4583 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4584 {
4585 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4586 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4587 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4588
4589 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4590 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4591 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4592 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4593 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4594
4595 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4596 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4597 RT_UNTRUSTED_VALIDATED_FENCE();
4598
4599 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4600 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4601 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4602
4603 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4604 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4605 pNumRange, cVertexDivisor, pVertexDivisor);
4606 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4607 break;
4608 }
4609
4610 case SVGA_3D_CMD_SETSCISSORRECT:
4611 {
4612 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4613 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4614 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4615
4616 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4617 break;
4618 }
4619
4620 case SVGA_3D_CMD_BEGIN_QUERY:
4621 {
4622 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4623 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4624 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4625
4626 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4627 break;
4628 }
4629
4630 case SVGA_3D_CMD_END_QUERY:
4631 {
4632 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4633 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4634 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4635
4636 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4637 break;
4638 }
4639
4640 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4641 {
4642 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4643 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4644 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4645
4646 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4647 break;
4648 }
4649
4650 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4651 {
4652 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4653 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4654 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4655
4656 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4657 break;
4658 }
4659
4660 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4661 /* context id + surface id? */
4662 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4663 break;
4664
4665 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4666 /* context id + surface id? */
4667 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4668 break;
4669
4670 /*
4671 *
4672 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4673 *
4674 */
4675 case SVGA_3D_CMD_SCREEN_DMA:
4676 {
4677 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4678 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4679 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4680 break;
4681 }
4682
4683 /* case SVGA_3D_CMD_DEAD1: New SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION */
4684 case SVGA_3D_CMD_DEAD2:
4685 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4686 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4687 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4688 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4689 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4690 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4691 {
4692 VMSVGA_3D_CMD_NOTIMPL();
4693 break;
4694 }
4695
4696 case SVGA_3D_CMD_SET_OTABLE_BASE:
4697 {
4698 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4699 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4700 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4701 break;
4702 }
4703
4704 case SVGA_3D_CMD_READBACK_OTABLE:
4705 {
4706 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4707 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4709 break;
4710 }
4711
4712 case SVGA_3D_CMD_DEFINE_GB_MOB:
4713 {
4714 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4715 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4716 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4717 break;
4718 }
4719
4720 case SVGA_3D_CMD_DESTROY_GB_MOB:
4721 {
4722 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4723 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4724 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4725 break;
4726 }
4727
4728 case SVGA_3D_CMD_DEAD3:
4729 {
4730 VMSVGA_3D_CMD_NOTIMPL();
4731 break;
4732 }
4733
4734 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4735 {
4736 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4737 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4738 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4739 break;
4740 }
4741
4742 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4743 {
4744 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4745 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4746 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4747 break;
4748 }
4749
4750 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4751 {
4752 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4753 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4754 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4755 break;
4756 }
4757
4758 case SVGA_3D_CMD_BIND_GB_SURFACE:
4759 {
4760 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4761 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4762 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4763 break;
4764 }
4765
4766 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4767 {
4768 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4769 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4770 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4771 break;
4772 }
4773
4774 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4775 {
4776 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4777 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4778 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4779 break;
4780 }
4781
4782 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4783 {
4784 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4785 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4786 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4787 break;
4788 }
4789
4790 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4791 {
4792 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4793 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4794 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4795 break;
4796 }
4797
4798 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4799 {
4800 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4801 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4802 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4803 break;
4804 }
4805
4806 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4807 {
4808 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4809 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4810 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4811 break;
4812 }
4813
4814 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4815 {
4816 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4817 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4818 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4819 break;
4820 }
4821
4822 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4823 {
4824 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4825 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4826 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4827 break;
4828 }
4829
4830 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4831 {
4832 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4833 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4834 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4835 break;
4836 }
4837
4838 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4839 {
4840 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4841 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4842 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4843 break;
4844 }
4845
4846 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4847 {
4848 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4849 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4850 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4851 break;
4852 }
4853
4854 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4855 {
4856 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4857 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4858 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4859 break;
4860 }
4861
4862 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4863 {
4864 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4865 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4866 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4867 break;
4868 }
4869
4870 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4871 {
4872 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4873 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4874 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4875 break;
4876 }
4877
4878 case SVGA_3D_CMD_BIND_GB_SHADER:
4879 {
4880 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4881 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4882 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4883 break;
4884 }
4885
4886 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4887 {
4888 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4889 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4890 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4891 break;
4892 }
4893
4894 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4895 {
4896 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4897 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4898 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4899 break;
4900 }
4901
4902 case SVGA_3D_CMD_END_GB_QUERY:
4903 {
4904 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4905 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4906 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4907 break;
4908 }
4909
4910 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4911 {
4912 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4913 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4914 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4915 break;
4916 }
4917
4918 case SVGA_3D_CMD_NOP:
4919 {
4920 /* Apparently there is nothing to do. */
4921 break;
4922 }
4923
4924 case SVGA_3D_CMD_ENABLE_GART:
4925 {
4926 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4927 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4928 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4929 break;
4930 }
4931
4932 case SVGA_3D_CMD_DISABLE_GART:
4933 {
4934 /* No corresponding SVGA3dCmd structure. */
4935 VMSVGA_3D_CMD_NOTIMPL();
4936 break;
4937 }
4938
4939 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4940 {
4941 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4942 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4943 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4944 break;
4945 }
4946
4947 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4948 {
4949 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4950 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4951 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4952 break;
4953 }
4954
4955 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4956 {
4957 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4958 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4959 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4960 break;
4961 }
4962
4963 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4964 {
4965 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4966 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4967 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4968 break;
4969 }
4970
4971 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4972 {
4973 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4974 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4975 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4976 break;
4977 }
4978
4979 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4980 {
4981 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4982 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4983 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4984 break;
4985 }
4986
4987 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4988 {
4989 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4991 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4992 break;
4993 }
4994
4995 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4996 {
4997 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4998 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4999 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5000 break;
5001 }
5002
5003 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
5004 {
5005 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
5006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5007 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5008 break;
5009 }
5010
5011 case SVGA_3D_CMD_GB_SCREEN_DMA:
5012 {
5013 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
5014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5015 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5016 break;
5017 }
5018
5019 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
5020 {
5021 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
5022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5023 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5024 break;
5025 }
5026
5027 case SVGA_3D_CMD_GB_MOB_FENCE:
5028 {
5029 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
5030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5031 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5032 break;
5033 }
5034
5035 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
5036 {
5037 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
5038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5039 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
5040 break;
5041 }
5042
5043 case SVGA_3D_CMD_DEFINE_GB_MOB64:
5044 {
5045 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
5046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5047 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
5048 break;
5049 }
5050
5051 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
5052 {
5053 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
5054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5055 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5056 break;
5057 }
5058
5059 case SVGA_3D_CMD_NOP_ERROR:
5060 {
5061 /* Apparently there is nothing to do. */
5062 break;
5063 }
5064
5065 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
5066 {
5067 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
5068 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5069 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5070 break;
5071 }
5072
5073 case SVGA_3D_CMD_SET_VERTEX_DECLS:
5074 {
5075 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
5076 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5077 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5078 break;
5079 }
5080
5081 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
5082 {
5083 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
5084 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5085 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5086 break;
5087 }
5088
5089 case SVGA_3D_CMD_DRAW:
5090 {
5091 /* No corresponding SVGA3dCmd structure. */
5092 VMSVGA_3D_CMD_NOTIMPL();
5093 break;
5094 }
5095
5096 case SVGA_3D_CMD_DRAW_INDEXED:
5097 {
5098 /* No corresponding SVGA3dCmd structure. */
5099 VMSVGA_3D_CMD_NOTIMPL();
5100 break;
5101 }
5102
5103 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
5104 {
5105 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
5106 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5107 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
5108 break;
5109 }
5110
5111 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
5112 {
5113 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
5114 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5115 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5116 break;
5117 }
5118
5119 case SVGA_3D_CMD_DX_BIND_CONTEXT:
5120 {
5121 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
5122 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5123 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5124 break;
5125 }
5126
5127 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5128 {
5129 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5130 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5131 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5132 break;
5133 }
5134
5135 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5136 {
5137 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5138 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5139 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5140 break;
5141 }
5142
5143 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5144 {
5145 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5146 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5147 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5148 break;
5149 }
5150
5151 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5152 {
5153 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5154 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5155 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5156 break;
5157 }
5158
5159 case SVGA_3D_CMD_DX_SET_SHADER:
5160 {
5161 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5162 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5163 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5164 break;
5165 }
5166
5167 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5168 {
5169 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5170 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5171 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5172 break;
5173 }
5174
5175 case SVGA_3D_CMD_DX_DRAW:
5176 {
5177 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5178 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5179 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5180 break;
5181 }
5182
5183 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5184 {
5185 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5186 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5187 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5188 break;
5189 }
5190
5191 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5192 {
5193 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5194 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5195 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5196 break;
5197 }
5198
5199 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5200 {
5201 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5202 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5203 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5204 break;
5205 }
5206
5207 case SVGA_3D_CMD_DX_DRAW_AUTO:
5208 {
5209 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5210 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5211 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5212 break;
5213 }
5214
5215 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5216 {
5217 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5218 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5219 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5220 break;
5221 }
5222
5223 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5224 {
5225 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5226 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5227 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5228 break;
5229 }
5230
5231 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5232 {
5233 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5234 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5235 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5236 break;
5237 }
5238
5239 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5240 {
5241 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5242 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5243 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5244 break;
5245 }
5246
5247 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5248 {
5249 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5250 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5251 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5252 break;
5253 }
5254
5255 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5256 {
5257 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5258 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5259 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5260 break;
5261 }
5262
5263 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5264 {
5265 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5266 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5267 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5268 break;
5269 }
5270
5271 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5272 {
5273 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5274 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5275 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5276 break;
5277 }
5278
5279 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5280 {
5281 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5282 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5283 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5284 break;
5285 }
5286
5287 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5288 {
5289 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5290 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5291 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5292 break;
5293 }
5294
5295 case SVGA_3D_CMD_DX_BIND_QUERY:
5296 {
5297 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5298 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5299 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5300 break;
5301 }
5302
5303 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5304 {
5305 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5306 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5307 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5308 break;
5309 }
5310
5311 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5312 {
5313 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5314 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5315 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5316 break;
5317 }
5318
5319 case SVGA_3D_CMD_DX_END_QUERY:
5320 {
5321 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5322 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5323 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5324 break;
5325 }
5326
5327 case SVGA_3D_CMD_DX_READBACK_QUERY:
5328 {
5329 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5330 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5331 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5332 break;
5333 }
5334
5335 case SVGA_3D_CMD_DX_SET_PREDICATION:
5336 {
5337 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5338 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5339 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5340 break;
5341 }
5342
5343 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5344 {
5345 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5346 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5347 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5348 break;
5349 }
5350
5351 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5352 {
5353 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5354 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5355 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5356 break;
5357 }
5358
5359 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5360 {
5361 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5363 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5364 break;
5365 }
5366
5367 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5368 {
5369 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5370 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5371 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5372 break;
5373 }
5374
5375 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5376 {
5377 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5378 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5379 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5380 break;
5381 }
5382
5383 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5384 {
5385 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5387 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5388 break;
5389 }
5390
5391 case SVGA_3D_CMD_DX_PRED_COPY:
5392 {
5393 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5394 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5395 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5396 break;
5397 }
5398
5399 case SVGA_3D_CMD_DX_PRESENTBLT:
5400 {
5401 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5402 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5403 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5404 break;
5405 }
5406
5407 case SVGA_3D_CMD_DX_GENMIPS:
5408 {
5409 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5410 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5411 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5412 break;
5413 }
5414
5415 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5416 {
5417 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5418 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5419 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5420 break;
5421 }
5422
5423 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5424 {
5425 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5426 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5427 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5428 break;
5429 }
5430
5431 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5432 {
5433 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5434 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5435 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5436 break;
5437 }
5438
5439 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5440 {
5441 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5442 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5443 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5444 break;
5445 }
5446
5447 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5448 {
5449 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5450 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5451 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5452 break;
5453 }
5454
5455 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5456 {
5457 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5458 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5459 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5460 break;
5461 }
5462
5463 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5464 {
5465 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5466 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5467 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5468 break;
5469 }
5470
5471 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5472 {
5473 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5474 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5475 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5476 break;
5477 }
5478
5479 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5480 {
5481 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5482 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5483 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5484 break;
5485 }
5486
5487 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5488 {
5489 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5490 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5491 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5492 break;
5493 }
5494
5495 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5496 {
5497 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5498 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5499 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5500 break;
5501 }
5502
5503 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5504 {
5505 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5506 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5507 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5508 break;
5509 }
5510
5511 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5512 {
5513 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5514 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5515 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5516 break;
5517 }
5518
5519 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5520 {
5521 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5522 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5523 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5524 break;
5525 }
5526
5527 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5528 {
5529 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5530 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5531 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5532 break;
5533 }
5534
5535 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5536 {
5537 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5538 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5539 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5540 break;
5541 }
5542
5543 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5544 {
5545 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5546 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5547 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5548 break;
5549 }
5550
5551 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5552 {
5553 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5554 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5555 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5556 break;
5557 }
5558
5559 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5560 {
5561 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5562 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5563 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5564 break;
5565 }
5566
5567 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5568 {
5569 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5570 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5571 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5572 break;
5573 }
5574
5575 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5576 {
5577 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5578 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5579 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5580 break;
5581 }
5582
5583 case SVGA_3D_CMD_DX_BIND_SHADER:
5584 {
5585 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5586 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5587 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5588 break;
5589 }
5590
5591 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5592 {
5593 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5594 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5595 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5596 break;
5597 }
5598
5599 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5600 {
5601 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5602 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5603 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5604 break;
5605 }
5606
5607 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5608 {
5609 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5610 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5611 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5612 break;
5613 }
5614
5615 case SVGA_3D_CMD_DX_SET_COTABLE:
5616 {
5617 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5618 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5619 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5620 break;
5621 }
5622
5623 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5624 {
5625 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5626 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5627 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5628 break;
5629 }
5630
5631 case SVGA_3D_CMD_DX_BUFFER_COPY:
5632 {
5633 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5634 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5635 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5636 break;
5637 }
5638
5639 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5640 {
5641 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5642 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5643 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5644 break;
5645 }
5646
5647 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5648 {
5649 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5650 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5651 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5652 break;
5653 }
5654
5655 case SVGA_3D_CMD_DX_MOVE_QUERY:
5656 {
5657 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5658 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5659 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5660 break;
5661 }
5662
5663 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5664 {
5665 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5666 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5667 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5668 break;
5669 }
5670
5671 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5672 {
5673 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5674 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5675 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5676 break;
5677 }
5678
5679 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5680 {
5681 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5682 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5683 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5684 break;
5685 }
5686
5687 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5688 {
5689 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5690 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5691 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, pCmd, cbCmd);
5692 break;
5693 }
5694
5695 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5696 {
5697 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5698 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5699 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5700 break;
5701 }
5702
5703 case SVGA_3D_CMD_DX_HINT:
5704 {
5705 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5706 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5707 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5708 break;
5709 }
5710
5711 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5712 {
5713 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5714 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5715 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5716 break;
5717 }
5718
5719 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5720 {
5721 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5722 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5723 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5724 break;
5725 }
5726
5727 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5728 {
5729 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5730 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5731 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5732 break;
5733 }
5734
5735 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5736 {
5737 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5738 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5739 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5740 break;
5741 }
5742
5743 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5744 {
5745 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5746 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5747 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5748 break;
5749 }
5750
5751 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5752 {
5753 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5754 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5755 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5756 break;
5757 }
5758
5759 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5760 {
5761 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5762 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5763 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5764 break;
5765 }
5766
5767 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5768 {
5769 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5770 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5771 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5772 break;
5773 }
5774
5775 case SVGA_3D_CMD_SCREEN_COPY:
5776 {
5777 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5778 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5779 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5780 break;
5781 }
5782
5783 case SVGA_3D_CMD_RESERVED1:
5784 {
5785 VMSVGA_3D_CMD_NOTIMPL();
5786 break;
5787 }
5788
5789 case SVGA_3D_CMD_RESERVED2:
5790 {
5791 VMSVGA_3D_CMD_NOTIMPL();
5792 break;
5793 }
5794
5795 case SVGA_3D_CMD_RESERVED3:
5796 {
5797 VMSVGA_3D_CMD_NOTIMPL();
5798 break;
5799 }
5800
5801 case SVGA_3D_CMD_RESERVED4:
5802 {
5803 VMSVGA_3D_CMD_NOTIMPL();
5804 break;
5805 }
5806
5807 case SVGA_3D_CMD_RESERVED5:
5808 {
5809 VMSVGA_3D_CMD_NOTIMPL();
5810 break;
5811 }
5812
5813 case SVGA_3D_CMD_RESERVED6:
5814 {
5815 VMSVGA_3D_CMD_NOTIMPL();
5816 break;
5817 }
5818
5819 case SVGA_3D_CMD_RESERVED7:
5820 {
5821 VMSVGA_3D_CMD_NOTIMPL();
5822 break;
5823 }
5824
5825 case SVGA_3D_CMD_RESERVED8:
5826 {
5827 VMSVGA_3D_CMD_NOTIMPL();
5828 break;
5829 }
5830
5831 case SVGA_3D_CMD_GROW_OTABLE:
5832 {
5833 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5834 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5835 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5836 break;
5837 }
5838
5839 case SVGA_3D_CMD_DX_GROW_COTABLE:
5840 {
5841 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5842 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5843 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5844 break;
5845 }
5846
5847 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5848 {
5849 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5850 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5851 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5852 break;
5853 }
5854
5855 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5856 {
5857 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5859 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd);
5860 break;
5861 }
5862
5863 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5864 {
5865 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5866 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5867 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5868 break;
5869 }
5870
5871 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5872 {
5873 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5875 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5876 break;
5877 }
5878
5879 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5880 {
5881 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5883 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5884 break;
5885 }
5886
5887 case SVGA_3D_CMD_DX_PRED_CONVERT:
5888 {
5889 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5891 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5892 break;
5893 }
5894
5895 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5896 {
5897 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5899 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5900 break;
5901 }
5902
5903 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5904 {
5905 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5906 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5907 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5908 break;
5909 }
5910
5911 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5912 {
5913 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5915 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5916 break;
5917 }
5918
5919 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5920 {
5921 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5923 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5924 break;
5925 }
5926
5927 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5928 {
5929 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5931 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5932 break;
5933 }
5934
5935 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5936 {
5937 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5939 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5940 break;
5941 }
5942
5943 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5944 {
5945 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5946 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5947 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5948 break;
5949 }
5950
5951 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5952 {
5953 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5954 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5955 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5956 break;
5957 }
5958
5959 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5960 {
5961 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5962 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5963 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5964 break;
5965 }
5966
5967 case SVGA_3D_CMD_DX_DISPATCH:
5968 {
5969 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5970 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5971 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5972 break;
5973 }
5974
5975 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5976 {
5977 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5978 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5979 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5980 break;
5981 }
5982
5983 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5984 {
5985 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5986 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5987 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5988 break;
5989 }
5990
5991 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5992 {
5993 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5994 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5995 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5996 break;
5997 }
5998
5999 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
6000 {
6001 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
6002 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6003 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
6004 break;
6005 }
6006
6007 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
6008 {
6009 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
6010 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6011 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
6012 break;
6013 }
6014
6015 case SVGA_3D_CMD_LOGICOPS_BITBLT:
6016 {
6017 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
6018 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6019 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
6020 break;
6021 }
6022
6023 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
6024 {
6025 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
6026 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6027 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
6028 break;
6029 }
6030
6031 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
6032 {
6033 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
6034 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6035 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
6036 break;
6037 }
6038
6039 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
6040 {
6041 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
6042 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6043 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
6044 break;
6045 }
6046
6047 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
6048 {
6049 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
6050 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6051 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
6052 break;
6053 }
6054
6055 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
6056 {
6057 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
6058 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6059 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
6060 break;
6061 }
6062
6063 case SVGA_3D_CMD_RESERVED2_1:
6064 {
6065 VMSVGA_3D_CMD_NOTIMPL();
6066 break;
6067 }
6068
6069 case SVGA_3D_CMD_RESERVED2_2:
6070 {
6071 VMSVGA_3D_CMD_NOTIMPL();
6072 break;
6073 }
6074
6075 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
6076 {
6077 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
6078 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6079 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd);
6080 break;
6081 }
6082
6083 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
6084 {
6085 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
6086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6087 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
6088 break;
6089 }
6090
6091 case SVGA_3D_CMD_DX_SET_MIN_LOD:
6092 {
6093 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
6094 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6095 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
6096 break;
6097 }
6098
6099 case SVGA_3D_CMD_RESERVED2_3:
6100 {
6101 VMSVGA_3D_CMD_NOTIMPL();
6102 break;
6103 }
6104
6105 case SVGA_3D_CMD_RESERVED2_4:
6106 {
6107 VMSVGA_3D_CMD_NOTIMPL();
6108 break;
6109 }
6110
6111 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
6112 {
6113 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
6114 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6115 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6116 break;
6117 }
6118
6119 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6120 {
6121 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
6122 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6123 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6124 break;
6125 }
6126
6127 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6128 {
6129 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6130 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6131 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6132 break;
6133 }
6134
6135 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6136 {
6137 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6138 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6139 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6140 break;
6141 }
6142
6143 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6144 {
6145 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6146 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6147 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6148 break;
6149 }
6150
6151 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6152 {
6153 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6154 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6155 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6156 break;
6157 }
6158
6159 case SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION:
6160 {
6161 SVGA3dCmdVBDXClearRenderTargetViewRegion *pCmd = (SVGA3dCmdVBDXClearRenderTargetViewRegion *)pvCmd;
6162 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6163 rcParse = vmsvga3dCmdVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cbCmd);
6164 break;
6165 }
6166
6167 /* Unsupported commands. */
6168 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6169 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6170 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6171 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6172 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6173 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6174 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6175 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6176 /* Prevent the compiler warning. */
6177 case SVGA_3D_CMD_LEGACY_BASE:
6178 case SVGA_3D_CMD_MAX:
6179 case SVGA_3D_CMD_FUTURE_MAX:
6180 /* No 'default' case */
6181 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6182 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6183 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6184 rcParse = VERR_NOT_IMPLEMENTED;
6185 break;
6186 }
6187
6188 return VINF_SUCCESS;
6189// return rcParse;
6190}
6191# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6192#endif /* VBOX_WITH_VMSVGA3D */
6193
6194
6195/*
6196 *
6197 * Handlers for FIFO commands.
6198 *
6199 * Every handler takes the following parameters:
6200 *
6201 * pThis The shared VGA/VMSVGA state.
6202 * pThisCC The VGA/VMSVGA state for ring-3.
6203 * pCmd The command data.
6204 */
6205
6206
6207/* SVGA_CMD_UPDATE */
6208void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6209{
6210 RT_NOREF(pThis);
6211 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6212
6213 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6214 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6215
6216 /** @todo Multiple screens? */
6217 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6218 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6219 return;
6220
6221 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6222}
6223
6224
6225/* SVGA_CMD_UPDATE_VERBOSE */
6226void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6227{
6228 RT_NOREF(pThis);
6229 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6230
6231 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6232 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6233
6234 /** @todo Multiple screens? */
6235 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6236 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6237 return;
6238
6239 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6240}
6241
6242
6243/* SVGA_CMD_RECT_FILL */
6244void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6245{
6246 RT_NOREF(pThis, pCmd);
6247 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6248
6249 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6250 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6251 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6252}
6253
6254
6255/* SVGA_CMD_RECT_COPY */
6256void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6257{
6258 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6259
6260 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6261 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6262
6263 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6264 AssertPtrReturnVoid(pScreen);
6265
6266 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6267 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6268 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6269 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6270 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6271 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6272 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6273
6274 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6275 pCmd->width, pCmd->height, pThis->vram_size);
6276 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6277}
6278
6279
6280/* SVGA_CMD_RECT_ROP_COPY */
6281void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6282{
6283 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6284
6285 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6286 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6287
6288 if (pCmd->rop != SVGA_ROP_COPY)
6289 {
6290 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6291 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6292 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6293 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6294 */
6295 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6296 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6297 return;
6298 }
6299
6300 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6301 AssertPtrReturnVoid(pScreen);
6302
6303 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6304 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6305 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6306 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6307 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6308 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6309 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6310
6311 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6312 pCmd->width, pCmd->height, pThis->vram_size);
6313 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6314}
6315
6316
6317/* SVGA_CMD_DISPLAY_CURSOR */
6318void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6319{
6320 RT_NOREF(pThis, pCmd);
6321 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6322
6323 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6324 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6325 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6326}
6327
6328
6329/* SVGA_CMD_MOVE_CURSOR */
6330void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6331{
6332 RT_NOREF(pThis, pCmd);
6333 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6334
6335 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6336 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6337 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6338}
6339
6340
6341/* SVGA_CMD_DEFINE_CURSOR */
6342void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6343{
6344 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6345
6346 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6347 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6348 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6349
6350 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6351 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6352 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6353 RT_UNTRUSTED_VALIDATED_FENCE();
6354
6355 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6356 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6357 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6358
6359 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6360 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6361
6362 uint32_t const cx = pCmd->width;
6363 uint32_t const cy = pCmd->height;
6364
6365 /*
6366 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6367 * The AND data uses 8-bit aligned scanlines.
6368 * The XOR data must be starting on a 32-bit boundrary.
6369 */
6370 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6371 uint32_t cbDstAndMask = cbDstAndLine * cy;
6372 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6373 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6374
6375 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6376 AssertReturnVoid(pbCopy);
6377
6378 /* Convert the AND mask. */
6379 uint8_t *pbDst = pbCopy;
6380 uint8_t const *pbSrc = pbSrcAndMask;
6381 switch (pCmd->andMaskDepth)
6382 {
6383 case 1:
6384 if (cbSrcAndLine == cbDstAndLine)
6385 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6386 else
6387 {
6388 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6389 for (uint32_t y = 0; y < cy; y++)
6390 {
6391 memcpy(pbDst, pbSrc, cbDstAndLine);
6392 pbDst += cbDstAndLine;
6393 pbSrc += cbSrcAndLine;
6394 }
6395 }
6396 break;
6397 /* Should take the XOR mask into account for the multi-bit AND mask. */
6398 case 8:
6399 for (uint32_t y = 0; y < cy; y++)
6400 {
6401 for (uint32_t x = 0; x < cx; )
6402 {
6403 uint8_t bDst = 0;
6404 uint8_t fBit = 0x80;
6405 do
6406 {
6407 uintptr_t const idxPal = pbSrc[x] * 3;
6408 if ((( pThis->last_palette[idxPal]
6409 | (pThis->last_palette[idxPal] >> 8)
6410 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6411 bDst |= fBit;
6412 fBit >>= 1;
6413 x++;
6414 } while (x < cx && (x & 7));
6415 pbDst[(x - 1) / 8] = bDst;
6416 }
6417 pbDst += cbDstAndLine;
6418 pbSrc += cbSrcAndLine;
6419 }
6420 break;
6421 case 15:
6422 for (uint32_t y = 0; y < cy; y++)
6423 {
6424 for (uint32_t x = 0; x < cx; )
6425 {
6426 uint8_t bDst = 0;
6427 uint8_t fBit = 0x80;
6428 do
6429 {
6430 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6431 bDst |= fBit;
6432 fBit >>= 1;
6433 x++;
6434 } while (x < cx && (x & 7));
6435 pbDst[(x - 1) / 8] = bDst;
6436 }
6437 pbDst += cbDstAndLine;
6438 pbSrc += cbSrcAndLine;
6439 }
6440 break;
6441 case 16:
6442 for (uint32_t y = 0; y < cy; y++)
6443 {
6444 for (uint32_t x = 0; x < cx; )
6445 {
6446 uint8_t bDst = 0;
6447 uint8_t fBit = 0x80;
6448 do
6449 {
6450 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6451 bDst |= fBit;
6452 fBit >>= 1;
6453 x++;
6454 } while (x < cx && (x & 7));
6455 pbDst[(x - 1) / 8] = bDst;
6456 }
6457 pbDst += cbDstAndLine;
6458 pbSrc += cbSrcAndLine;
6459 }
6460 break;
6461 case 24:
6462 for (uint32_t y = 0; y < cy; y++)
6463 {
6464 for (uint32_t x = 0; x < cx; )
6465 {
6466 uint8_t bDst = 0;
6467 uint8_t fBit = 0x80;
6468 do
6469 {
6470 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6471 bDst |= fBit;
6472 fBit >>= 1;
6473 x++;
6474 } while (x < cx && (x & 7));
6475 pbDst[(x - 1) / 8] = bDst;
6476 }
6477 pbDst += cbDstAndLine;
6478 pbSrc += cbSrcAndLine;
6479 }
6480 break;
6481 case 32:
6482 for (uint32_t y = 0; y < cy; y++)
6483 {
6484 for (uint32_t x = 0; x < cx; )
6485 {
6486 uint8_t bDst = 0;
6487 uint8_t fBit = 0x80;
6488 do
6489 {
6490 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6491 bDst |= fBit;
6492 fBit >>= 1;
6493 x++;
6494 } while (x < cx && (x & 7));
6495 pbDst[(x - 1) / 8] = bDst;
6496 }
6497 pbDst += cbDstAndLine;
6498 pbSrc += cbSrcAndLine;
6499 }
6500 break;
6501 default:
6502 RTMemFreeZ(pbCopy, cbCopy);
6503 AssertFailedReturnVoid();
6504 }
6505
6506 /* Convert the XOR mask. */
6507 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6508 pbSrc = pbSrcXorMask;
6509 switch (pCmd->xorMaskDepth)
6510 {
6511 case 1:
6512 for (uint32_t y = 0; y < cy; y++)
6513 {
6514 for (uint32_t x = 0; x < cx; )
6515 {
6516 /* most significant bit is the left most one. */
6517 uint8_t bSrc = pbSrc[x / 8];
6518 do
6519 {
6520 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6521 bSrc <<= 1;
6522 x++;
6523 } while ((x & 7) && x < cx);
6524 }
6525 pbSrc += cbSrcXorLine;
6526 }
6527 break;
6528 case 8:
6529 for (uint32_t y = 0; y < cy; y++)
6530 {
6531 for (uint32_t x = 0; x < cx; x++)
6532 {
6533 uint32_t u = pThis->last_palette[pbSrc[x]];
6534 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6535 }
6536 pbSrc += cbSrcXorLine;
6537 }
6538 break;
6539 case 15: /* Src: RGB-5-5-5 */
6540 for (uint32_t y = 0; y < cy; y++)
6541 {
6542 for (uint32_t x = 0; x < cx; x++)
6543 {
6544 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6545 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6546 ((uValue >> 5) & 0x1f) << 3,
6547 ((uValue >> 10) & 0x1f) << 3, 0);
6548 }
6549 pbSrc += cbSrcXorLine;
6550 }
6551 break;
6552 case 16: /* Src: RGB-5-6-5 */
6553 for (uint32_t y = 0; y < cy; y++)
6554 {
6555 for (uint32_t x = 0; x < cx; x++)
6556 {
6557 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6558 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6559 ((uValue >> 5) & 0x3f) << 2,
6560 ((uValue >> 11) & 0x1f) << 3, 0);
6561 }
6562 pbSrc += cbSrcXorLine;
6563 }
6564 break;
6565 case 24:
6566 for (uint32_t y = 0; y < cy; y++)
6567 {
6568 for (uint32_t x = 0; x < cx; x++)
6569 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6570 pbSrc += cbSrcXorLine;
6571 }
6572 break;
6573 case 32:
6574 for (uint32_t y = 0; y < cy; y++)
6575 {
6576 for (uint32_t x = 0; x < cx; x++)
6577 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6578 pbSrc += cbSrcXorLine;
6579 }
6580 break;
6581 default:
6582 RTMemFreeZ(pbCopy, cbCopy);
6583 AssertFailedReturnVoid();
6584 }
6585
6586 /*
6587 * Pass it to the frontend/whatever.
6588 */
6589 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6590 cx, cy, pbCopy, cbCopy);
6591}
6592
6593
6594/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6595void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6596{
6597 RT_NOREF(pThis);
6598 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6599
6600 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6601 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6602
6603 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6604 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6605 RT_UNTRUSTED_VALIDATED_FENCE();
6606
6607 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6608 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6609 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6610 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6611 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6612
6613 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6614 AssertPtrReturnVoid(pCursorCopy);
6615
6616 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6617 memset(pCursorCopy, 0xff, cbAndMask);
6618 /* Colour data */
6619 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6620
6621 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6622 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6623}
6624
6625
6626/* SVGA_CMD_ESCAPE */
6627void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6628{
6629 RT_NOREF(pThis);
6630 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6631
6632 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6633
6634 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6635 {
6636 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6637 RT_UNTRUSTED_VALIDATED_FENCE();
6638
6639 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6640 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6641
6642 switch (cmd)
6643 {
6644 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6645 {
6646 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6647 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6648 RT_UNTRUSTED_VALIDATED_FENCE();
6649
6650 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6651
6652 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6653 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6654 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6655 RT_NOREF_PV(pVideoCmd);
6656 break;
6657 }
6658
6659 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6660 {
6661 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6662 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6663 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6664 RT_NOREF_PV(pVideoCmd);
6665 break;
6666 }
6667
6668 default:
6669 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6670 break;
6671 }
6672 }
6673 else
6674 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6675}
6676
6677
6678/* SVGA_CMD_DEFINE_SCREEN */
6679void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6680{
6681 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6682
6683 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6684 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6685 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6686 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6687
6688 uint32_t const idScreen = pCmd->screen.id;
6689 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6690
6691 uint32_t const uWidth = pCmd->screen.size.width;
6692 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6693
6694 uint32_t const uHeight = pCmd->screen.size.height;
6695 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6696
6697 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6698 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6699 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6700
6701 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6702 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6703
6704 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6705 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6706 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6707 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6708 RT_UNTRUSTED_VALIDATED_FENCE();
6709
6710 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6711 pScreen->fDefined = true;
6712 pScreen->fModified = true;
6713 pScreen->fuScreen = pCmd->screen.flags;
6714 pScreen->idScreen = idScreen;
6715 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6716 {
6717 /* Not blanked. */
6718 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6719 RT_UNTRUSTED_VALIDATED_FENCE();
6720
6721 pScreen->xOrigin = pCmd->screen.root.x;
6722 pScreen->yOrigin = pCmd->screen.root.y;
6723 pScreen->cWidth = uWidth;
6724 pScreen->cHeight = uHeight;
6725 pScreen->offVRAM = uScreenOffset;
6726 pScreen->cbPitch = cbPitch;
6727 pScreen->cBpp = 32;
6728 }
6729 else
6730 {
6731 /* Screen blanked. Keep old values. */
6732 }
6733
6734 pThis->svga.fGFBRegisters = false;
6735 vmsvgaR3ChangeMode(pThis, pThisCC);
6736
6737#ifdef VBOX_WITH_VMSVGA3D
6738 if (RT_LIKELY(pThis->svga.f3DEnabled))
6739 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6740#endif
6741}
6742
6743
6744/* SVGA_CMD_DESTROY_SCREEN */
6745void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6746{
6747 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6748
6749 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6750 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6751
6752 uint32_t const idScreen = pCmd->screenId;
6753 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6754 RT_UNTRUSTED_VALIDATED_FENCE();
6755
6756 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6757 pScreen->fModified = true;
6758 pScreen->fDefined = false;
6759 pScreen->idScreen = idScreen;
6760
6761#ifdef VBOX_WITH_VMSVGA3D
6762 if (RT_LIKELY(pThis->svga.f3DEnabled))
6763 vmsvga3dDestroyScreen(pThisCC, pScreen);
6764#endif
6765 vmsvgaR3ChangeMode(pThis, pThisCC);
6766}
6767
6768
6769/* SVGA_CMD_DEFINE_GMRFB */
6770void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6771{
6772 RT_NOREF(pThis);
6773 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6774
6775 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6776 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6777 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6778
6779 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6780 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6781 pSvgaR3State->GMRFB.format = pCmd->format;
6782}
6783
6784
6785/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6786void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6787{
6788 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6789
6790 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6791 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6792 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6793
6794 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6795 RT_UNTRUSTED_VALIDATED_FENCE();
6796
6797 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6798 AssertPtrReturnVoid(pScreen);
6799
6800 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6801 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6802
6803 /* Clip destRect to the screen dimensions. */
6804 SVGASignedRect screenRect;
6805 screenRect.left = 0;
6806 screenRect.top = 0;
6807 screenRect.right = pScreen->cWidth;
6808 screenRect.bottom = pScreen->cHeight;
6809 SVGASignedRect clipRect = pCmd->destRect;
6810 vmsvgaR3ClipRect(&screenRect, &clipRect);
6811 RT_UNTRUSTED_VALIDATED_FENCE();
6812
6813 uint32_t const width = clipRect.right - clipRect.left;
6814 uint32_t const height = clipRect.bottom - clipRect.top;
6815
6816 if ( width == 0
6817 || height == 0)
6818 return; /* Nothing to do. */
6819
6820 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6821 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6822
6823 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6824 * Prepare parameters for vmsvgaR3GmrTransfer.
6825 */
6826 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6827
6828 /* Destination: host buffer which describes the screen 0 VRAM.
6829 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6830 */
6831 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6832 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6833 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6834 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6835 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6836 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6837 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6838 + cbScanline * clipRect.top;
6839 int32_t const cbHstPitch = cbScanline;
6840
6841 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6842 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6843 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6844 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6845 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6846
6847 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6848 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6849 gstPtr, offGst, cbGstPitch,
6850 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6851 AssertRC(rc);
6852 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6853}
6854
6855
6856/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6857void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6858{
6859 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6860
6861 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6862 /* Note! This can fetch 3d render results as well!! */
6863 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6864 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6865
6866 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6867 RT_UNTRUSTED_VALIDATED_FENCE();
6868
6869 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6870 AssertPtrReturnVoid(pScreen);
6871
6872 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6873 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6874
6875 /* Clip destRect to the screen dimensions. */
6876 SVGASignedRect screenRect;
6877 screenRect.left = 0;
6878 screenRect.top = 0;
6879 screenRect.right = pScreen->cWidth;
6880 screenRect.bottom = pScreen->cHeight;
6881 SVGASignedRect clipRect = pCmd->srcRect;
6882 vmsvgaR3ClipRect(&screenRect, &clipRect);
6883 RT_UNTRUSTED_VALIDATED_FENCE();
6884
6885 uint32_t const width = clipRect.right - clipRect.left;
6886 uint32_t const height = clipRect.bottom - clipRect.top;
6887
6888 if ( width == 0
6889 || height == 0)
6890 return; /* Nothing to do. */
6891
6892 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6893 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6894
6895 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6896 * Prepare parameters for vmsvgaR3GmrTransfer.
6897 */
6898 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6899
6900 /* Source: host buffer which describes the screen 0 VRAM.
6901 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6902 */
6903 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6904 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6905 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6906 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6907 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6908 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6909 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6910 + cbScanline * clipRect.top;
6911 int32_t const cbHstPitch = cbScanline;
6912
6913 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6914 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6915 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6916 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6917 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6918
6919 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6920 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6921 gstPtr, offGst, cbGstPitch,
6922 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6923 AssertRC(rc);
6924}
6925
6926
6927/* SVGA_CMD_ANNOTATION_FILL */
6928void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6929{
6930 RT_NOREF(pThis);
6931 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6932
6933 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6934 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6935
6936 pSvgaR3State->colorAnnotation = pCmd->color;
6937}
6938
6939
6940/* SVGA_CMD_ANNOTATION_COPY */
6941void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6942{
6943 RT_NOREF(pThis, pCmd);
6944 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6945
6946 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6947 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6948
6949 AssertFailed();
6950}
6951
6952
6953#ifdef VBOX_WITH_VMSVGA3D
6954/* SVGA_CMD_DEFINE_GMR2 */
6955void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6956{
6957 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6958
6959 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6960 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6961
6962 /* Validate current GMR id. */
6963 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6964 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6965 RT_UNTRUSTED_VALIDATED_FENCE();
6966
6967 if (!pCmd->numPages)
6968 {
6969 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6970 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6971 }
6972 else
6973 {
6974 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6975 if (pGMR->cMaxPages)
6976 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6977
6978 /* Not sure if we should always free the descriptor, but for simplicity
6979 we do so if the new size is smaller than the current. */
6980 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6981 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6982 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6983
6984 pGMR->cMaxPages = pCmd->numPages;
6985 /* The rest is done by the REMAP_GMR2 command. */
6986 }
6987}
6988
6989
6990/* SVGA_CMD_REMAP_GMR2 */
6991void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6992{
6993 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6994
6995 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6996 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6997
6998 /* Validate current GMR id and size. */
6999 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
7000 RT_UNTRUSTED_VALIDATED_FENCE();
7001 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
7002 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
7003 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
7004 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
7005
7006 if (pCmd->numPages == 0)
7007 return;
7008 RT_UNTRUSTED_VALIDATED_FENCE();
7009
7010 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
7011 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
7012
7013 /*
7014 * We flatten the existing descriptors into a page array, overwrite the
7015 * pages specified in this command and then recompress the descriptor.
7016 */
7017 /** @todo Optimize the GMR remap algorithm! */
7018
7019 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
7020 uint64_t *paNewPage64 = NULL;
7021 if (pGMR->paDesc)
7022 {
7023 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
7024
7025 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
7026 AssertPtrReturnVoid(paNewPage64);
7027
7028 uint32_t idxPage = 0;
7029 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
7030 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
7031 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
7032 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
7033 RT_UNTRUSTED_VALIDATED_FENCE();
7034 }
7035
7036 /* Free the old GMR if present. */
7037 if (pGMR->paDesc)
7038 RTMemFree(pGMR->paDesc);
7039
7040 /* Allocate the maximum amount possible (everything non-continuous) */
7041 PVMSVGAGMRDESCRIPTOR paDescs;
7042 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
7043 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
7044
7045 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
7046 {
7047 /** @todo */
7048 AssertFailed();
7049 pGMR->numDescriptors = 0;
7050 }
7051 else
7052 {
7053 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
7054 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
7055 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
7056
7057 uint32_t cPages;
7058 if (paNewPage64)
7059 {
7060 /* Overwrite the old page array with the new page values. */
7061 if (fGCPhys64)
7062 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7063 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
7064 else
7065 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7066 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
7067
7068 /* Use the updated page array instead of the command data. */
7069 fGCPhys64 = true;
7070 paPages64 = paNewPage64;
7071 cPages = cNewTotalPages;
7072 }
7073 else
7074 cPages = pCmd->numPages;
7075
7076 /* The first page. */
7077 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
7078 * applied to paNewPage64. */
7079 RTGCPHYS GCPhys;
7080 if (fGCPhys64)
7081 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7082 else
7083 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
7084 paDescs[0].GCPhys = GCPhys;
7085 paDescs[0].numPages = 1;
7086
7087 /* Subsequent pages. */
7088 uint32_t iDescriptor = 0;
7089 for (uint32_t i = 1; i < cPages; i++)
7090 {
7091 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
7092 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7093 else
7094 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
7095
7096 /* Continuous physical memory? */
7097 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
7098 {
7099 Assert(paDescs[iDescriptor].numPages);
7100 paDescs[iDescriptor].numPages++;
7101 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
7102 }
7103 else
7104 {
7105 iDescriptor++;
7106 paDescs[iDescriptor].GCPhys = GCPhys;
7107 paDescs[iDescriptor].numPages = 1;
7108 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
7109 }
7110 }
7111
7112 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
7113 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
7114 pGMR->numDescriptors = iDescriptor + 1;
7115 }
7116
7117 if (paNewPage64)
7118 RTMemFree(paNewPage64);
7119}
7120
7121
7122/**
7123 * Free the specified GMR
7124 *
7125 * @param pThisCC The VGA/VMSVGA state for ring-3.
7126 * @param idGMR GMR id
7127 */
7128void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7129{
7130 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7131
7132 /* Free the old descriptor if present. */
7133 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7134 if ( pGMR->numDescriptors
7135 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7136 {
7137# ifdef DEBUG_GMR_ACCESS
7138 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7139# endif
7140
7141 Assert(pGMR->paDesc);
7142 RTMemFree(pGMR->paDesc);
7143 pGMR->paDesc = NULL;
7144 pGMR->numDescriptors = 0;
7145 pGMR->cbTotal = 0;
7146 pGMR->cMaxPages = 0;
7147 }
7148 Assert(!pGMR->cMaxPages);
7149 Assert(!pGMR->cbTotal);
7150}
7151#endif /* VBOX_WITH_VMSVGA3D */
7152
7153
7154/**
7155 * Copy between a GMR and a host memory buffer.
7156 *
7157 * @returns VBox status code.
7158 * @param pThis The shared VGA/VMSVGA instance data.
7159 * @param pThisCC The VGA/VMSVGA state for ring-3.
7160 * @param enmTransferType Transfer type (read/write)
7161 * @param pbHstBuf Host buffer pointer (valid)
7162 * @param cbHstBuf Size of host buffer (valid)
7163 * @param offHst Host buffer offset of the first scanline
7164 * @param cbHstPitch Destination buffer pitch
7165 * @param gstPtr GMR description
7166 * @param offGst Guest buffer offset of the first scanline
7167 * @param cbGstPitch Guest buffer pitch
7168 * @param cbWidth Width in bytes to copy
7169 * @param cHeight Number of scanllines to copy
7170 */
7171int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7172 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7173 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7174 uint32_t cbWidth, uint32_t cHeight)
7175{
7176 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7177 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7178 int rc;
7179
7180 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7181 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7182 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7183 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7184 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7185
7186 PGMR pGMR;
7187 uint32_t cbGmr; /* The GMR size in bytes. */
7188 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7189 {
7190 pGMR = NULL;
7191 cbGmr = pThis->vram_size;
7192 }
7193 else
7194 {
7195 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7196 RT_UNTRUSTED_VALIDATED_FENCE();
7197 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7198 cbGmr = pGMR->cbTotal;
7199 }
7200
7201 /*
7202 * GMR
7203 */
7204 /* Calculate GMR offset of the data to be copied. */
7205 AssertMsgReturn(gstPtr.offset < cbGmr,
7206 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7207 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7208 VERR_INVALID_PARAMETER);
7209 RT_UNTRUSTED_VALIDATED_FENCE();
7210 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7211 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7212 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7213 VERR_INVALID_PARAMETER);
7214 RT_UNTRUSTED_VALIDATED_FENCE();
7215 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7216
7217 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7218 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7219 AssertMsgReturn(cbGmrScanline != 0,
7220 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7221 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7222 VERR_INVALID_PARAMETER);
7223 RT_UNTRUSTED_VALIDATED_FENCE();
7224 AssertMsgReturn(cbWidth <= cbGmrScanline,
7225 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7226 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7227 VERR_INVALID_PARAMETER);
7228 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7229 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7230 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7231 VERR_INVALID_PARAMETER);
7232 RT_UNTRUSTED_VALIDATED_FENCE();
7233
7234 /* How many bytes are available for the data in the GMR. */
7235 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7236
7237 /* How many scanlines would fit into the available data. */
7238 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7239 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7240 if (cbWidth <= cbGmrLastScanline)
7241 ++cGmrScanlines;
7242
7243 if (cHeight > cGmrScanlines)
7244 cHeight = cGmrScanlines;
7245
7246 AssertMsgReturn(cHeight > 0,
7247 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7248 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7249 VERR_INVALID_PARAMETER);
7250 RT_UNTRUSTED_VALIDATED_FENCE();
7251
7252 /*
7253 * Host buffer.
7254 */
7255 AssertMsgReturn(offHst < cbHstBuf,
7256 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7257 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7258 VERR_INVALID_PARAMETER);
7259
7260 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7261 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7262 AssertMsgReturn(cbHstScanline != 0,
7263 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7264 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7265 VERR_INVALID_PARAMETER);
7266 AssertMsgReturn(cbWidth <= cbHstScanline,
7267 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7268 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7269 VERR_INVALID_PARAMETER);
7270 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7271 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7272 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7273 VERR_INVALID_PARAMETER);
7274
7275 /* How many bytes are available for the data in the buffer. */
7276 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7277
7278 /* How many scanlines would fit into the available data. */
7279 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7280 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7281 if (cbWidth <= cbHstLastScanline)
7282 ++cHstScanlines;
7283
7284 if (cHeight > cHstScanlines)
7285 cHeight = cHstScanlines;
7286
7287 AssertMsgReturn(cHeight > 0,
7288 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7289 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7290 VERR_INVALID_PARAMETER);
7291
7292 uint8_t *pbHst = pbHstBuf + offHst;
7293
7294 /* Shortcut for the framebuffer. */
7295 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7296 {
7297 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7298
7299 uint8_t const *pbSrc;
7300 int32_t cbSrcPitch;
7301 uint8_t *pbDst;
7302 int32_t cbDstPitch;
7303
7304 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7305 {
7306 pbSrc = pbHst;
7307 cbSrcPitch = cbHstPitch;
7308 pbDst = pbGst;
7309 cbDstPitch = cbGstPitch;
7310 }
7311 else
7312 {
7313 pbSrc = pbGst;
7314 cbSrcPitch = cbGstPitch;
7315 pbDst = pbHst;
7316 cbDstPitch = cbHstPitch;
7317 }
7318
7319 if ( cbWidth == (uint32_t)cbGstPitch
7320 && cbGstPitch == cbHstPitch)
7321 {
7322 /* Entire scanlines, positive pitch. */
7323 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7324 }
7325 else
7326 {
7327 for (uint32_t i = 0; i < cHeight; ++i)
7328 {
7329 memcpy(pbDst, pbSrc, cbWidth);
7330
7331 pbDst += cbDstPitch;
7332 pbSrc += cbSrcPitch;
7333 }
7334 }
7335 return VINF_SUCCESS;
7336 }
7337
7338 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7339 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7340
7341 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7342 uint32_t iDesc = 0; /* Index in the descriptor array. */
7343 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7344 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7345 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7346 for (uint32_t i = 0; i < cHeight; ++i)
7347 {
7348 uint32_t cbCurrentWidth = cbWidth;
7349 uint32_t offGmrCurrent = offGmrScanline;
7350 uint8_t *pbCurrentHost = pbHstScanline;
7351
7352 /* Find the right descriptor */
7353 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7354 {
7355 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7356 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7357 ++iDesc;
7358 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7359 }
7360
7361 while (cbCurrentWidth)
7362 {
7363 uint32_t cbToCopy;
7364
7365 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7366 cbToCopy = cbCurrentWidth;
7367 else
7368 {
7369 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7370 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7371 }
7372
7373 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7374
7375 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7376
7377 /*
7378 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7379 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7380 * see @bugref{9654#c75}.
7381 */
7382 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7383 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7384 else
7385 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7386 AssertRCBreak(rc);
7387
7388 cbCurrentWidth -= cbToCopy;
7389 offGmrCurrent += cbToCopy;
7390 pbCurrentHost += cbToCopy;
7391
7392 /* Go to the next descriptor if there's anything left. */
7393 if (cbCurrentWidth)
7394 {
7395 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7396 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7397 ++iDesc;
7398 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7399 }
7400 }
7401
7402 offGmrScanline += cbGstPitch;
7403 pbHstScanline += cbHstPitch;
7404 }
7405
7406 return VINF_SUCCESS;
7407}
7408
7409
7410/**
7411 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7412 *
7413 * @param pSizeSrc Source surface dimensions.
7414 * @param pSizeDest Destination surface dimensions.
7415 * @param pBox Coordinates to be clipped.
7416 */
7417void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7418{
7419 /* Src x, w */
7420 if (pBox->srcx > pSizeSrc->width)
7421 pBox->srcx = pSizeSrc->width;
7422 if (pBox->w > pSizeSrc->width - pBox->srcx)
7423 pBox->w = pSizeSrc->width - pBox->srcx;
7424
7425 /* Src y, h */
7426 if (pBox->srcy > pSizeSrc->height)
7427 pBox->srcy = pSizeSrc->height;
7428 if (pBox->h > pSizeSrc->height - pBox->srcy)
7429 pBox->h = pSizeSrc->height - pBox->srcy;
7430
7431 /* Src z, d */
7432 if (pBox->srcz > pSizeSrc->depth)
7433 pBox->srcz = pSizeSrc->depth;
7434 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7435 pBox->d = pSizeSrc->depth - pBox->srcz;
7436
7437 /* Dest x, w */
7438 if (pBox->x > pSizeDest->width)
7439 pBox->x = pSizeDest->width;
7440 if (pBox->w > pSizeDest->width - pBox->x)
7441 pBox->w = pSizeDest->width - pBox->x;
7442
7443 /* Dest y, h */
7444 if (pBox->y > pSizeDest->height)
7445 pBox->y = pSizeDest->height;
7446 if (pBox->h > pSizeDest->height - pBox->y)
7447 pBox->h = pSizeDest->height - pBox->y;
7448
7449 /* Dest z, d */
7450 if (pBox->z > pSizeDest->depth)
7451 pBox->z = pSizeDest->depth;
7452 if (pBox->d > pSizeDest->depth - pBox->z)
7453 pBox->d = pSizeDest->depth - pBox->z;
7454}
7455
7456
7457/**
7458 * Unsigned coordinates in pBox. Clip to [0; pSize).
7459 *
7460 * @param pSize Source surface dimensions.
7461 * @param pBox Coordinates to be clipped.
7462 */
7463void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7464{
7465 /* x, w */
7466 if (pBox->x > pSize->width)
7467 pBox->x = pSize->width;
7468 if (pBox->w > pSize->width - pBox->x)
7469 pBox->w = pSize->width - pBox->x;
7470
7471 /* y, h */
7472 if (pBox->y > pSize->height)
7473 pBox->y = pSize->height;
7474 if (pBox->h > pSize->height - pBox->y)
7475 pBox->h = pSize->height - pBox->y;
7476
7477 /* z, d */
7478 if (pBox->z > pSize->depth)
7479 pBox->z = pSize->depth;
7480 if (pBox->d > pSize->depth - pBox->z)
7481 pBox->d = pSize->depth - pBox->z;
7482}
7483
7484
7485/**
7486 * Clip.
7487 *
7488 * @param pBound Bounding rectangle.
7489 * @param pRect Rectangle to be clipped.
7490 */
7491void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7492{
7493 int32_t left;
7494 int32_t top;
7495 int32_t right;
7496 int32_t bottom;
7497
7498 /* Right order. */
7499 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7500 if (pRect->left < pRect->right)
7501 {
7502 left = pRect->left;
7503 right = pRect->right;
7504 }
7505 else
7506 {
7507 left = pRect->right;
7508 right = pRect->left;
7509 }
7510 if (pRect->top < pRect->bottom)
7511 {
7512 top = pRect->top;
7513 bottom = pRect->bottom;
7514 }
7515 else
7516 {
7517 top = pRect->bottom;
7518 bottom = pRect->top;
7519 }
7520
7521 if (left < pBound->left)
7522 left = pBound->left;
7523 if (right < pBound->left)
7524 right = pBound->left;
7525
7526 if (left > pBound->right)
7527 left = pBound->right;
7528 if (right > pBound->right)
7529 right = pBound->right;
7530
7531 if (top < pBound->top)
7532 top = pBound->top;
7533 if (bottom < pBound->top)
7534 bottom = pBound->top;
7535
7536 if (top > pBound->bottom)
7537 top = pBound->bottom;
7538 if (bottom > pBound->bottom)
7539 bottom = pBound->bottom;
7540
7541 pRect->left = left;
7542 pRect->right = right;
7543 pRect->top = top;
7544 pRect->bottom = bottom;
7545}
7546
7547
7548/**
7549 * Clip.
7550 *
7551 * @param pBound Bounding rectangle.
7552 * @param pRect Rectangle to be clipped.
7553 */
7554void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7555{
7556 uint32_t const leftBound = pBound->x;
7557 uint32_t const rightBound = pBound->x + pBound->w;
7558 uint32_t const topBound = pBound->y;
7559 uint32_t const bottomBound = pBound->y + pBound->h;
7560
7561 uint32_t x = pRect->x;
7562 uint32_t y = pRect->y;
7563 uint32_t w = pRect->w;
7564 uint32_t h = pRect->h;
7565
7566 /* Make sure that right and bottom coordinates can be safely computed. */
7567 if (x > rightBound)
7568 x = rightBound;
7569 if (w > rightBound - x)
7570 w = rightBound - x;
7571 if (y > bottomBound)
7572 y = bottomBound;
7573 if (h > bottomBound - y)
7574 h = bottomBound - y;
7575
7576 /* Switch from x, y, w, h to left, top, right, bottom. */
7577 uint32_t left = x;
7578 uint32_t right = x + w;
7579 uint32_t top = y;
7580 uint32_t bottom = y + h;
7581
7582 /* A standard left, right, bottom, top clipping. */
7583 if (left < leftBound)
7584 left = leftBound;
7585 if (right < leftBound)
7586 right = leftBound;
7587
7588 if (left > rightBound)
7589 left = rightBound;
7590 if (right > rightBound)
7591 right = rightBound;
7592
7593 if (top < topBound)
7594 top = topBound;
7595 if (bottom < topBound)
7596 bottom = topBound;
7597
7598 if (top > bottomBound)
7599 top = bottomBound;
7600 if (bottom > bottomBound)
7601 bottom = bottomBound;
7602
7603 /* Back to x, y, w, h representation. */
7604 pRect->x = left;
7605 pRect->y = top;
7606 pRect->w = right - left;
7607 pRect->h = bottom - top;
7608}
7609
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