VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 95043

最後變更 在這個檔案從95043是 95017,由 vboxsync 提交於 3 年 前

Devices/Graphics: copy resource: bugref:9830
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 273.8 KB
行 
1/* $Id: DevVGA-SVGA-cmd.cpp 95017 2022-05-15 20:45:06Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#include <iprt/formats/bmp.h>
40#include <stdio.h>
41
42#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
43# define SVGA_CASE_ID2STR(idx) case idx: return #idx
44
45static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
46{
47 switch (enmCmdId)
48 {
49 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
50 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
290 }
291 return "UNKNOWN_3D";
292}
293
294/**
295 * FIFO command name lookup
296 *
297 * @returns FIFO command string or "UNKNOWN"
298 * @param u32Cmd FIFO command
299 */
300const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
301{
302 switch (u32Cmd)
303 {
304 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
305 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
306 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
307 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
309 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
310 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
311 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
314 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
315 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
316 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
317 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
318 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
320 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
323 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
324 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
325 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
327 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
328 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
329 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
330 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
331 default:
332 if ( u32Cmd >= SVGA_3D_CMD_BASE
333 && u32Cmd < SVGA_3D_CMD_MAX)
334 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
335 }
336 return "UNKNOWN";
337}
338# undef SVGA_CASE_ID2STR
339#endif /* LOG_ENABLED || VBOX_STRICT */
340
341
342/*
343 *
344 * Guest-Backed Objects (GBO).
345 *
346 */
347
348/**
349 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
350 *
351 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
352 * @param pVM VM Handle.
353 * @param pVCpu The cross context CPU structure for the calling EMT.
354 * @param GCPhys The physical address the guest is writing to.
355 * @param pvPhys The HC mapping of that address.
356 * @param pvBuf What the guest is reading/writing.
357 * @param cbBuf How much it's reading/writing.
358 * @param enmAccessType The access type.
359 * @param enmOrigin Who is making the access.
360 * @param uUser The VMM automatically sets this to the address of
361 * the device instance.
362 */
363DECLCALLBACK(VBOXSTRICTRC)
364vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
365 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, uint64_t uUser)
366{
367 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
368
369 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
370 return VINF_PGM_HANDLER_DO_DEFAULT;
371
372 PPDMDEVINS pDevIns = (PPDMDEVINS)uUser;
373 AssertPtrReturn(pDevIns, VERR_INTERNAL_ERROR_4);
374 AssertReturn(pDevIns->u32Version == PDM_DEVINSR3_VERSION, VERR_INTERNAL_ERROR_5);
375 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
376 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
377 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
378
379 /*
380 * The guest is not allowed to access the memory.
381 * Set the error condition.
382 */
383 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
384
385 /* Try to find the GBO which the guest is accessing. */
386 char const *pszTarget = NULL;
387 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
388 {
389 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
390 if (pGbo->cDescriptors)
391 {
392 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
393 {
394 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
395 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * GUEST_PAGE_SIZE)
396 {
397 switch (i)
398 {
399 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
400 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
401 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
402 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
403 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
404 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
405 default: pszTarget = "Unknown OTABLE"; break;
406 }
407 break;
408 }
409 }
410 }
411 }
412
413 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
414 "%.*Rhxd\n",
415 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
416
417 return VINF_PGM_HANDLER_DO_DEFAULT;
418}
419
420#ifdef VBOX_WITH_VMSVGA3D
421
422static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
423{
424 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
425
426 /*
427 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
428 * Content of the root page depends on the ptDepth value:
429 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
430 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
431 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
432 * The code below extracts the page addresses of the GBO.
433 */
434
435 /* Verify and normalize the ptDepth value. */
436 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
437 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
438 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
439 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
440 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
441 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
442 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
443 {
444 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
445 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
446 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
447 }
448 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
449 { }
450 else
451 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
452
453 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
454
455 pGbo->cbTotal = sizeInBytes;
456 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
457
458 /* Allocate the maximum amount possible (everything non-continuous) */
459 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
460 AssertReturn(paDescriptors, VERR_NO_MEMORY);
461
462 int rc = VINF_SUCCESS;
463 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
464 {
465 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
466 RTMemFree(paDescriptors),
467 VERR_INVALID_PARAMETER);
468
469 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
470 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471 paDescriptors[0].GCPhys = GCPhys;
472 paDescriptors[0].cPages = 1;
473 }
474 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
475 {
476 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
477 RTMemFree(paDescriptors),
478 VERR_INVALID_PARAMETER);
479
480 /* Read the root page. */
481 uint8_t au8RootPage[X86_PAGE_SIZE];
482 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
483 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
484 if (RT_SUCCESS(rc))
485 {
486 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
487 PPN *paPPN32 = (PPN *)&au8RootPage[0];
488 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
489 {
490 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
491 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
492 paDescriptors[iPPN].GCPhys = GCPhys;
493 paDescriptors[iPPN].cPages = 1;
494 }
495 }
496 }
497 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
498 {
499 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
500 RTMemFree(paDescriptors),
501 VERR_INVALID_PARAMETER);
502
503 /* Read the Level2 root page. */
504 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
505 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
506 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
507 if (RT_SUCCESS(rc))
508 {
509 uint32_t cPagesLeft = pGbo->cTotalPages;
510
511 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
512 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
513
514 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
515 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
516 {
517 /* Read the Level1 root page. */
518 uint8_t au8RootPage[X86_PAGE_SIZE];
519 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
520 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
521 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
522 if (RT_SUCCESS(rc))
523 {
524 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
525 PPN *paPPN32 = (PPN *)&au8RootPage[0];
526
527 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
528 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
529 {
530 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
531 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
532 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
533 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
534 }
535 cPagesLeft -= cPPNs;
536 }
537 }
538 }
539 }
540 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
541 {
542 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[0].GCPhys = GCPhys;
545 paDescriptors[0].cPages = pGbo->cTotalPages;
546 }
547 else
548 {
549 AssertFailed();
550 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
551 }
552
553 /* Compress the descriptors. */
554 if (ptDepth != SVGA3D_MOBFMT_RANGE)
555 {
556 uint32_t iDescriptor = 0;
557 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
558 {
559 /* Continuous physical memory? */
560 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
561 {
562 Assert(paDescriptors[iDescriptor].cPages);
563 paDescriptors[iDescriptor].cPages++;
564 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
565 }
566 else
567 {
568 iDescriptor++;
569 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
570 paDescriptors[iDescriptor].cPages = 1;
571 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
572 }
573 }
574
575 pGbo->cDescriptors = iDescriptor + 1;
576 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
577 }
578 else
579 pGbo->cDescriptors = 1;
580
581 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
582 {
583 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
584 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
585 }
586 else
587 pGbo->paDescriptors = paDescriptors;
588
589#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
590fWriteProtected = false;
591#endif
592 if (fWriteProtected)
593 {
594 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
595 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
596 {
597 rc = PDMDevHlpPGMHandlerPhysicalRegister(pSvgaR3State->pDevIns,
598 pGbo->paDescriptors[i].GCPhys,
599 pGbo->paDescriptors[i].GCPhys
600 + pGbo->paDescriptors[i].cPages * GUEST_PAGE_SIZE - 1,
601 pSvgaR3State->hGboAccessHandlerType, "VMSVGA GBO");
602 AssertRC(rc);
603 }
604 }
605
606 return VINF_SUCCESS;
607}
608
609
610static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
611{
612 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
613 {
614 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
615 {
616 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
617 {
618 int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pSvgaR3State->pDevIns, pGbo->paDescriptors[i].GCPhys);
619 AssertRC(rc);
620 }
621 }
622 RTMemFree(pGbo->paDescriptors);
623 RT_ZERO(pGbo);
624 }
625}
626
627/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
628
629typedef enum VMSVGAGboTransferDirection
630{
631 VMSVGAGboTransferDirection_Read,
632 VMSVGAGboTransferDirection_Write,
633} VMSVGAGboTransferDirection;
634
635static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
636 uint32_t off, void *pvData, uint32_t cbData,
637 VMSVGAGboTransferDirection enmDirection)
638{
639 //DEBUG_BREAKPOINT_TEST();
640 int rc = VINF_SUCCESS;
641 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
642
643 /* Find the right descriptor */
644 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
645 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
646 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
647 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
648 {
649 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
650 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
651 ++iDescriptor;
652 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
653 }
654
655 while (cbData)
656 {
657 uint32_t cbToCopy;
658 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
659 cbToCopy = cbData;
660 else
661 {
662 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
663 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
664 }
665
666 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
667 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
668
669 /*
670 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
671 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
672 * see @bugref{9654#c75}.
673 */
674 if (enmDirection == VMSVGAGboTransferDirection_Read)
675 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
676 else
677 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
678 AssertRCBreak(rc);
679
680 cbData -= cbToCopy;
681 off += cbToCopy;
682 pu8CurrentHost += cbToCopy;
683
684 /* Go to the next descriptor if there's anything left. */
685 if (cbData)
686 {
687 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
688 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
689 ++iDescriptor;
690 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
691 }
692 }
693 return rc;
694}
695
696
697static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
698 uint32_t off, void const *pvData, uint32_t cbData)
699{
700 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
701 off, (void *)pvData, cbData,
702 VMSVGAGboTransferDirection_Write);
703}
704
705
706static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
707 uint32_t off, void *pvData, uint32_t cbData)
708{
709 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
710 off, pvData, cbData,
711 VMSVGAGboTransferDirection_Read);
712}
713
714
715static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
716{
717 int rc;
718
719 /* Just reread the data if pvHost has been allocated already. */
720 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
721 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
722
723 if (pGbo->pvHost)
724 {
725 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
726 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
727 }
728 else
729 rc = VERR_NO_MEMORY;
730
731 if (RT_SUCCESS(rc))
732 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
733 else
734 {
735 RTMemFree(pGbo->pvHost);
736 pGbo->pvHost = NULL;
737 }
738 return rc;
739}
740
741
742static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
743{
744 RT_NOREF(pSvgaR3State);
745 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
746 RTMemFree(pGbo->pvHost);
747 pGbo->pvHost = NULL;
748 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
749}
750
751
752static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
753{
754 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
755 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
756}
757
758
759static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
760{
761 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
762 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
763}
764
765
766
767/*
768 *
769 * Object Tables.
770 *
771 */
772
773static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
774 uint32_t idx, uint32_t cbEntry)
775{
776 RT_NOREF(pSvgaR3State);
777
778 /* The table must exist and the index must be within the table. */
779 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
780 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
781 RT_UNTRUSTED_VALIDATED_FENCE();
782 return VINF_SUCCESS;
783}
784
785
786static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
787 uint32_t idx, uint32_t cbEntry,
788 void *pvData, uint32_t cbData)
789{
790 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
791
792 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
793 if (RT_SUCCESS(rc))
794 {
795 uint32_t const off = idx * cbEntry;
796 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
797 }
798 return rc;
799}
800
801static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
802 uint32_t idx, uint32_t cbEntry,
803 void const *pvData, uint32_t cbData)
804{
805 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
806
807 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
808 if (RT_SUCCESS(rc))
809 {
810 uint32_t const off = idx * cbEntry;
811 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
812 }
813 return rc;
814}
815
816
817int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
818{
819 return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
820 sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
821}
822
823
824/*
825 *
826 * The guest's Memory OBjects (MOB).
827 *
828 */
829
830static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
831 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
832 bool fGCPhys64, PVMSVGAMOB pMob)
833{
834 RT_ZERO(*pMob);
835
836 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
837 SVGAOTableMobEntry entry;
838 entry.ptDepth = ptDepth;
839 entry.sizeInBytes = sizeInBytes;
840 entry.base = baseAddress;
841 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
842 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
843 if (RT_SUCCESS(rc))
844 {
845 /* Create the corresponding GBO. */
846 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
847 if (RT_SUCCESS(rc))
848 {
849 /* Add to the tree of known GBOs and the LRU list. */
850 pMob->Core.Key = mobid;
851 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
852 {
853 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
854 return VINF_SUCCESS;
855 }
856
857 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
858 }
859 }
860
861 return rc;
862}
863
864
865static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
866{
867 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
868 SVGAOTableMobEntry entry;
869 RT_ZERO(entry);
870 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
871 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
872
873 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
874 if (pMob)
875 {
876 RTListNodeRemove(&pMob->nodeLRU);
877 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
878 RTMemFree(pMob);
879 return VINF_SUCCESS;
880 }
881
882 return VERR_INVALID_PARAMETER;
883}
884
885
886PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
887{
888 if (mobid == SVGA_ID_INVALID)
889 return NULL;
890
891 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
892 if (pMob)
893 {
894 /* Move to the head of the LRU list. */
895 RTListNodeRemove(&pMob->nodeLRU);
896 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
897 }
898 else
899 ASSERT_GUEST_FAILED();
900
901 return pMob;
902}
903
904
905int vmsvgaR3MobWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
906 uint32_t off, void const *pvData, uint32_t cbData)
907{
908 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
909}
910
911
912int vmsvgaR3MobRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
913 uint32_t off, void *pvData, uint32_t cbData)
914{
915 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
916}
917
918
919/** Create a host ring-3 pointer to the MOB data.
920 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
921 * @param pSvgaR3State R3 device state.
922 * @param pMob The MOB.
923 * @param cbValid How many bytes of the guest backing memory contain valid data.
924 * @return VBox status.
925 */
926/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
927int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
928{
929 AssertReturn(pMob, VERR_INVALID_PARAMETER);
930 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
931}
932
933
934void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
935{
936 if (pMob)
937 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
938}
939
940
941int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
942{
943 if (pMob)
944 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
945 return VERR_INVALID_PARAMETER;
946}
947
948
949int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
950{
951 if (pMob)
952 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
953 return VERR_INVALID_PARAMETER;
954}
955
956
957void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
958{
959 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
960 {
961 if (off <= pMob->Gbo.cbTotal)
962 return (uint8_t *)pMob->Gbo.pvHost + off;
963 }
964 return NULL;
965}
966
967#endif /* VBOX_WITH_VMSVGA3D */
968
969/*
970 * Screen objects.
971 */
972VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
973{
974 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
975 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
976 && pSVGAState
977 && pSVGAState->aScreens[idScreen].fDefined)
978 {
979 return &pSVGAState->aScreens[idScreen];
980 }
981 return NULL;
982}
983
984void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
985{
986#ifdef VBOX_WITH_VMSVGA3D
987 if (pThis->svga.f3DEnabled)
988 {
989 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
990 {
991 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
992 if (pScreen)
993 vmsvga3dDestroyScreen(pThisCC, pScreen);
994 }
995 }
996#else
997 RT_NOREF(pThis, pThisCC);
998#endif
999}
1000
1001
1002/**
1003 * Copy a rectangle of pixels within guest VRAM.
1004 */
1005static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1006 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1007{
1008 if (!width || !height)
1009 return; /* Nothing to do, don't even bother. */
1010
1011 /*
1012 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1013 * corresponding to the current display mode.
1014 */
1015 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1016 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1017 uint8_t const *pSrc;
1018 uint8_t *pDst;
1019 unsigned const cbRectWidth = width * cbPixel;
1020 unsigned uMaxOffset;
1021
1022 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1023 if (uMaxOffset >= cbFrameBuffer)
1024 {
1025 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1026 return; /* Just don't listen to a bad guest. */
1027 }
1028
1029 pSrc = pDst = pThisCC->pbVRam;
1030 pSrc += srcY * cbScanline + srcX * cbPixel;
1031 pDst += dstY * cbScanline + dstX * cbPixel;
1032
1033 if (srcY >= dstY)
1034 {
1035 /* Source below destination, copy top to bottom. */
1036 for (; height > 0; height--)
1037 {
1038 memmove(pDst, pSrc, cbRectWidth);
1039 pSrc += cbScanline;
1040 pDst += cbScanline;
1041 }
1042 }
1043 else
1044 {
1045 /* Source above destination, copy bottom to top. */
1046 pSrc += cbScanline * (height - 1);
1047 pDst += cbScanline * (height - 1);
1048 for (; height > 0; height--)
1049 {
1050 memmove(pDst, pSrc, cbRectWidth);
1051 pSrc -= cbScanline;
1052 pDst -= cbScanline;
1053 }
1054 }
1055}
1056
1057
1058/**
1059 * Common worker for changing the pointer shape.
1060 *
1061 * @param pThisCC The VGA/VMSVGA state for ring-3.
1062 * @param pSVGAState The VMSVGA ring-3 instance data.
1063 * @param fAlpha Whether there is alpha or not.
1064 * @param xHot Hotspot x coordinate.
1065 * @param yHot Hotspot y coordinate.
1066 * @param cx Width.
1067 * @param cy Height.
1068 * @param pbData Heap copy of the cursor data. Consumed.
1069 * @param cbData The size of the data.
1070 */
1071static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1072 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1073{
1074 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1075#ifdef LOG_ENABLED
1076 if (LogIs2Enabled())
1077 {
1078 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1079 if (!fAlpha)
1080 {
1081 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1082 for (uint32_t y = 0; y < cy; y++)
1083 {
1084 Log2(("%3u:", y));
1085 uint8_t const *pbLine = &pbData[y * cbAndLine];
1086 for (uint32_t x = 0; x < cx; x += 8)
1087 {
1088 uint8_t b = pbLine[x / 8];
1089 char szByte[12];
1090 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1091 szByte[1] = b & 0x40 ? '*' : ' ';
1092 szByte[2] = b & 0x20 ? '*' : ' ';
1093 szByte[3] = b & 0x10 ? '*' : ' ';
1094 szByte[4] = b & 0x08 ? '*' : ' ';
1095 szByte[5] = b & 0x04 ? '*' : ' ';
1096 szByte[6] = b & 0x02 ? '*' : ' ';
1097 szByte[7] = b & 0x01 ? '*' : ' ';
1098 szByte[8] = '\0';
1099 Log2(("%s", szByte));
1100 }
1101 Log2(("\n"));
1102 }
1103 }
1104
1105 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1106 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1107 for (uint32_t y = 0; y < cy; y++)
1108 {
1109 Log2(("%3u:", y));
1110 uint32_t const *pu32Line = &pu32Xor[y * cx];
1111 for (uint32_t x = 0; x < cx; x++)
1112 Log2((" %08x", pu32Line[x]));
1113 Log2(("\n"));
1114 }
1115 }
1116#endif
1117
1118 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1119 AssertRC(rc);
1120
1121 if (pSVGAState->Cursor.fActive)
1122 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1123
1124 pSVGAState->Cursor.fActive = true;
1125 pSVGAState->Cursor.xHotspot = xHot;
1126 pSVGAState->Cursor.yHotspot = yHot;
1127 pSVGAState->Cursor.width = cx;
1128 pSVGAState->Cursor.height = cy;
1129 pSVGAState->Cursor.cbData = cbData;
1130 pSVGAState->Cursor.pData = pbData;
1131}
1132
1133
1134#ifdef VBOX_WITH_VMSVGA3D
1135
1136/*
1137 * SVGA_3D_CMD_* handlers.
1138 */
1139
1140
1141/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1142 *
1143 * @param pThisCC The VGA/VMSVGA state for the current context.
1144 * @param pCmd The VMSVGA command.
1145 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1146 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1147 */
1148static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1149 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1150{
1151 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1152 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1153 RT_UNTRUSTED_VALIDATED_FENCE();
1154
1155 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1156 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1157 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1158 */
1159 uint32_t cRemainingMipLevels = cMipLevelSizes;
1160 uint32_t cFaces = 0;
1161 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1162 {
1163 if (pCmd->face[i].numMipLevels == 0)
1164 break;
1165
1166 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1167 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1168
1169 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1170 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1171 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1172
1173 ++cFaces;
1174 }
1175 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1176 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1177
1178 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1179 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1180
1181 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1182 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1183 RT_UNTRUSTED_VALIDATED_FENCE();
1184
1185 /* Verify paMipLevelSizes */
1186 uint32_t cWidth = paMipLevelSizes[0].width;
1187 uint32_t cHeight = paMipLevelSizes[0].height;
1188 uint32_t cDepth = paMipLevelSizes[0].depth;
1189 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1190 {
1191 cWidth >>= 1;
1192 if (cWidth == 0) cWidth = 1;
1193 cHeight >>= 1;
1194 if (cHeight == 0) cHeight = 1;
1195 cDepth >>= 1;
1196 if (cDepth == 0) cDepth = 1;
1197 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1198 {
1199 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1200 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1201 && cHeight == paMipLevelSizes[iMipLevelSize].height
1202 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1203 }
1204 }
1205 RT_UNTRUSTED_VALIDATED_FENCE();
1206
1207 /* Create the surface. */
1208 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1209 pCmd->multisampleCount, pCmd->autogenFilter,
1210 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* arraySize = */ 0, /* fAllocMipLevels = */ true);
1211}
1212
1213
1214/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1215static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1216{
1217 DEBUG_BREAKPOINT_TEST();
1218 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1219
1220 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1221
1222 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1223 /* Allocate a structure for the MOB. */
1224 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1225 AssertPtrReturnVoid(pMob);
1226
1227 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1228 if (RT_SUCCESS(rc))
1229 {
1230 return;
1231 }
1232
1233 AssertFailed();
1234
1235 RTMemFree(pMob);
1236}
1237
1238
1239/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1240static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1241{
1242 //DEBUG_BREAKPOINT_TEST();
1243 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1244
1245 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1246
1247 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1248 if (RT_SUCCESS(rc))
1249 {
1250 return;
1251 }
1252
1253 AssertFailed();
1254}
1255
1256
1257/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1258static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1259{
1260 //DEBUG_BREAKPOINT_TEST();
1261 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1262
1263 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1264 SVGAOTableSurfaceEntry entry;
1265 RT_ZERO(entry);
1266 entry.format = pCmd->format;
1267 entry.surface1Flags = pCmd->surfaceFlags;
1268 entry.numMipLevels = pCmd->numMipLevels;
1269 entry.multisampleCount = pCmd->multisampleCount;
1270 entry.autogenFilter = pCmd->autogenFilter;
1271 entry.size = pCmd->size;
1272 entry.mobid = SVGA_ID_INVALID;
1273 // entry.arraySize = 0;
1274 // entry.mobPitch = 0;
1275 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1276 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1277 if (RT_SUCCESS(rc))
1278 {
1279 /* Create the host surface. */
1280 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1281 pCmd->multisampleCount, pCmd->autogenFilter,
1282 pCmd->numMipLevels, &pCmd->size, /* arraySize = */ 0, /* fAllocMipLevels = */ false);
1283 }
1284}
1285
1286
1287/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1288static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1289{
1290 //DEBUG_BREAKPOINT_TEST();
1291 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1292
1293 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1294 SVGAOTableSurfaceEntry entry;
1295 RT_ZERO(entry);
1296 entry.mobid = SVGA_ID_INVALID;
1297 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1298 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1299
1300 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1301}
1302
1303
1304/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1305static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1306{
1307 //DEBUG_BREAKPOINT_TEST();
1308 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1309
1310 /* Assign the mobid to the surface. */
1311 int rc = VINF_SUCCESS;
1312 if (pCmd->mobid != SVGA_ID_INVALID)
1313 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1314 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1315 if (RT_SUCCESS(rc))
1316 {
1317 SVGAOTableSurfaceEntry entry;
1318 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1319 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1320 if (RT_SUCCESS(rc))
1321 {
1322 entry.mobid = pCmd->mobid;
1323 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1324 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1325 if (RT_SUCCESS(rc))
1326 {
1327 /* */
1328 }
1329 }
1330 }
1331}
1332
1333
1334typedef union
1335{
1336 float f;
1337 uint32_t u;
1338} Unsigned2Float;
1339
1340float float16ToFloat(uint16_t f16)
1341{
1342 /* Format specs from Wiki: [15] = sign, [14:10] = exponent, [9:0] = fraction */
1343 uint16_t const f = f16 & 0x3FF;
1344 uint16_t const e = (f16 >> 10) & 0x1F;
1345 uint16_t const s = (f16 >> 15) & 0x1;
1346 Unsigned2Float u2f;
1347
1348 if (e == 0)
1349 {
1350 if (f == 0)
1351 {
1352 /* zero, -0 */
1353 u2f.u = (s << 31) | (0 << 23) | 0;
1354 return u2f.f;
1355 }
1356
1357 /* subnormal numbers: (-1)^signbit * 2^-14 * 0.significantbits */
1358 float const k = 1.0f / 16384.0f; /* 2^-14 */
1359 return (s ? -1.0f : 1.0f) * k * (float)f / 1024.0f;
1360 }
1361
1362 if (e == 31)
1363 {
1364 if (f == 0)
1365 {
1366 /* +-infinity */
1367 u2f.u = (s << 31) | (0xFF << 23) | 0;
1368 return u2f.f;
1369 }
1370
1371 /* NaN */
1372 u2f.u = (s << 31) | (0xFF << 23) | 1;
1373 return u2f.f;
1374 }
1375
1376 /* normalized value: (-1)^signbit * 2^(exponent - 15) * 1.significantbits */
1377 /* Build the float, adjusting for exponent bias (float32 bias is 127, float16 is 15)
1378 * and number of bits in the fraction (float32 has 23, float16 has 10). */
1379 u2f.u = (s << 31) | ((e + 127 - 15) << 23) | (f << (23 - 10));
1380 return u2f.f;
1381}
1382
1383
1384static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1385{
1386 if (pMap->cbBlock != 4 && pMap->cbBlock != 1 && pMap->format != SVGA3D_R16G16B16A16_FLOAT)
1387 return VERR_NOT_SUPPORTED;
1388
1389 int const w = pMap->cbRow / pMap->cbBlock;
1390 int const h = pMap->cRows;
1391
1392 const int cbBitmap = pMap->cbRow * pMap->cRows * 4;
1393
1394 FILE *f = fopen(pszFilename, "wb");
1395 if (!f)
1396 return VERR_FILE_NOT_FOUND;
1397
1398 {
1399 BMPFILEHDR fileHdr;
1400 RT_ZERO(fileHdr);
1401 fileHdr.uType = BMP_HDR_MAGIC;
1402 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1403 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1404
1405 BMPWIN3XINFOHDR coreHdr;
1406 RT_ZERO(coreHdr);
1407 coreHdr.cbSize = sizeof(coreHdr);
1408 coreHdr.uWidth = w;
1409 coreHdr.uHeight = -h;
1410 coreHdr.cPlanes = 1;
1411 coreHdr.cBits = 32;
1412 coreHdr.cbSizeImage = cbBitmap;
1413
1414 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1415 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1416 }
1417
1418 if (pMap->cbBlock == 4)
1419 {
1420 const uint8_t *s = (uint8_t *)pMap->pvData;
1421 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1422 {
1423 fwrite(s, 1, pMap->cbRow, f);
1424
1425 s += pMap->cbRowPitch;
1426 }
1427 }
1428 else if (pMap->cbBlock == 1)
1429 {
1430 const uint8_t *s = (uint8_t *)pMap->pvData;
1431 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1432 {
1433 for (int32_t x = 0; x < w; ++x)
1434 {
1435 uint32_t u32Pixel = s[x];
1436 fwrite(&u32Pixel, 1, 4, f);
1437 }
1438
1439 s += pMap->cbRowPitch;
1440 }
1441 }
1442 else if (pMap->format == SVGA3D_R16G16B16A16_FLOAT)
1443 {
1444 const uint8_t *s = (uint8_t *)pMap->pvData;
1445 for (int32_t y = 0; y < h; ++y)
1446 {
1447 for (int32_t x = 0; x < w; ++x)
1448 {
1449 uint16_t const *pu16Pixel = (uint16_t *)(s + x * 8);
1450 uint8_t r = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[0]));
1451 uint8_t g = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[1]));
1452 uint8_t b = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[2]));
1453 uint8_t a = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[3]));
1454 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1455 fwrite(&u32Pixel, 1, 4, f);
1456 }
1457
1458 s += pMap->cbRowPitch;
1459 }
1460 }
1461
1462 fclose(f);
1463
1464 return VINF_SUCCESS;
1465}
1466
1467
1468void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1469{
1470 static int idxBitmap = 0;
1471 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1472 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1473 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1474 RTStrFree(pszFilename);
1475}
1476
1477
1478static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1479 PVMSVGAMOB pMob,
1480 SVGA3dSurfaceImageId const *pImage,
1481 SVGA3dBox const *pBox,
1482 SVGA3dTransferType enmTransfer)
1483{
1484 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1485
1486 VMSVGA3D_SURFACE_MAP enmMapType;
1487 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1488 enmMapType = pBox
1489 ? VMSVGA3D_SURFACE_MAP_WRITE
1490 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1491 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1492 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1493 else
1494 AssertFailedReturn(VERR_INVALID_PARAMETER);
1495
1496 VMSVGA3D_MAPPED_SURFACE map;
1497 int rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1498 if (RT_SUCCESS(rc))
1499 {
1500 /* Copy mapped surface <-> MOB. */
1501 VMSGA3D_BOX_DIMENSIONS dims;
1502 rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1503 if (RT_SUCCESS(rc))
1504 {
1505 for (uint32_t z = 0; z < map.box.d; ++z)
1506 {
1507 uint8_t *pu8Map = (uint8_t *)map.pvData + z * map.cbDepthPitch;
1508 uint32_t offMob = dims.offSubresource + dims.offBox + z * dims.cbDepthPitch;
1509
1510 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1511 {
1512 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1513 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1514 else
1515 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1516 AssertRCBreak(rc);
1517
1518 pu8Map += map.cbRowPitch;
1519 offMob += dims.cbPitch;
1520 }
1521 }
1522 }
1523
1524 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1525
1526 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1527 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1528 }
1529
1530 return rc;
1531}
1532
1533
1534/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1535static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1536{
1537 //DEBUG_BREAKPOINT_TEST();
1538 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1539
1540 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1541 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1542
1543/*
1544 SVGA3dSurfaceFormat format;
1545 SVGA3dSurface1Flags surface1Flags;
1546 uint32 numMipLevels;
1547 uint32 multisampleCount;
1548 SVGA3dTextureFilter autogenFilter;
1549 SVGA3dSize size;
1550 SVGAMobId mobid;
1551 uint32 arraySize;
1552 uint32 mobPitch;
1553 SVGA3dSurface2Flags surface2Flags;
1554 uint8 multisamplePattern;
1555 uint8 qualityLevel;
1556 uint16 bufferByteStride;
1557 float minLOD;
1558*/
1559
1560 /* "update a surface from its backing MOB." */
1561 SVGAOTableSurfaceEntry entrySurface;
1562 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1563 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1564 if (RT_SUCCESS(rc))
1565 {
1566 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1567 if (pMob)
1568 {
1569 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1570 AssertRC(rc);
1571 }
1572 }
1573}
1574
1575
1576/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1577static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1578{
1579 //DEBUG_BREAKPOINT_TEST();
1580 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1581
1582 LogFlowFunc(("sid=%u\n",
1583 pCmd->sid));
1584
1585 /* "update a surface from its backing MOB." */
1586 SVGAOTableSurfaceEntry entrySurface;
1587 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1588 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1589 if (RT_SUCCESS(rc))
1590 {
1591 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1592 if (pMob)
1593 {
1594 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1595 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1596 {
1597 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1598 {
1599 SVGA3dSurfaceImageId image;
1600 image.sid = pCmd->sid;
1601 image.face = iArray;
1602 image.mipmap = iMipmap;
1603
1604 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1605 AssertRCBreak(rc);
1606 }
1607 }
1608 }
1609 }
1610}
1611
1612
1613/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1614static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1615{
1616 //DEBUG_BREAKPOINT_TEST();
1617 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1618
1619 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1620 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1621
1622 /* Read a surface to its backing MOB. */
1623 SVGAOTableSurfaceEntry entrySurface;
1624 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1625 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1626 if (RT_SUCCESS(rc))
1627 {
1628 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1629 if (pMob)
1630 {
1631 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1632 AssertRC(rc);
1633 }
1634 }
1635}
1636
1637
1638/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1639static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1640{
1641 //DEBUG_BREAKPOINT_TEST();
1642 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1643
1644 LogFlowFunc(("sid=%u\n",
1645 pCmd->sid));
1646
1647 /* Read a surface to its backing MOB. */
1648 SVGAOTableSurfaceEntry entrySurface;
1649 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1650 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1651 if (RT_SUCCESS(rc))
1652 {
1653 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1654 if (pMob)
1655 {
1656 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1657 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1658 {
1659 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1660 {
1661 SVGA3dSurfaceImageId image;
1662 image.sid = pCmd->sid;
1663 image.face = iArray;
1664 image.mipmap = iMipmap;
1665
1666 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1667 AssertRCBreak(rc);
1668 }
1669 }
1670 }
1671 }
1672}
1673
1674
1675/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1676static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1677{
1678 //DEBUG_BREAKPOINT_TEST();
1679 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1680}
1681
1682
1683/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1684static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1685{
1686 //DEBUG_BREAKPOINT_TEST();
1687 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1688}
1689
1690
1691/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1692static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1693{
1694 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1695
1696 /*
1697 * Create a GBO for the table.
1698 */
1699 PVMSVGAGBO pGbo;
1700 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1701 {
1702 RT_UNTRUSTED_VALIDATED_FENCE();
1703 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1704 }
1705 else
1706 {
1707 ASSERT_GUEST_FAILED();
1708 pGbo = NULL;
1709 }
1710
1711 if (pGbo)
1712 {
1713 /* Recreate. */
1714 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1715 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1716 AssertRC(rc);
1717 }
1718}
1719
1720
1721/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1722static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1723{
1724 //DEBUG_BREAKPOINT_TEST();
1725 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1726
1727 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1728 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1729 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1730 RT_UNTRUSTED_VALIDATED_FENCE();
1731
1732 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1733 SVGAOTableScreenTargetEntry entry;
1734 RT_ZERO(entry);
1735 entry.image.sid = SVGA_ID_INVALID;
1736 // entry.image.face = 0;
1737 // entry.image.mipmap = 0;
1738 entry.width = pCmd->width;
1739 entry.height = pCmd->height;
1740 entry.xRoot = pCmd->xRoot;
1741 entry.yRoot = pCmd->yRoot;
1742 entry.flags = pCmd->flags;
1743 entry.dpi = pCmd->dpi;
1744
1745 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1746 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1747 if (RT_SUCCESS(rc))
1748 {
1749 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1750 /** @todo Generic screen object/target interface. */
1751 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1752 pScreen->fDefined = true;
1753 pScreen->fModified = true;
1754 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1755 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1756 pScreen->idScreen = pCmd->stid;
1757
1758 pScreen->xOrigin = pCmd->xRoot;
1759 pScreen->yOrigin = pCmd->yRoot;
1760 pScreen->cWidth = pCmd->width;
1761 pScreen->cHeight = pCmd->height;
1762 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1763 pScreen->cbPitch = pCmd->width * 4;
1764 pScreen->cBpp = 32;
1765
1766 if (RT_LIKELY(pThis->svga.f3DEnabled))
1767 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1768
1769 if (!pScreen->pHwScreen)
1770 {
1771 /* System memory buffer. */
1772 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1773 }
1774
1775 pThis->svga.fGFBRegisters = false;
1776 vmsvgaR3ChangeMode(pThis, pThisCC);
1777 }
1778}
1779
1780
1781/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1782static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1783{
1784 //DEBUG_BREAKPOINT_TEST();
1785 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1786
1787 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1788 RT_UNTRUSTED_VALIDATED_FENCE();
1789
1790 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1791 SVGAOTableScreenTargetEntry entry;
1792 RT_ZERO(entry);
1793 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1794 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1795 if (RT_SUCCESS(rc))
1796 {
1797 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1798 /** @todo Generic screen object/target interface. */
1799 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1800 pScreen->fModified = true;
1801 pScreen->fDefined = false;
1802 pScreen->idScreen = pCmd->stid;
1803
1804 if (RT_LIKELY(pThis->svga.f3DEnabled))
1805 vmsvga3dDestroyScreen(pThisCC, pScreen);
1806
1807 vmsvgaR3ChangeMode(pThis, pThisCC);
1808
1809 RTMemFree(pScreen->pvScreenBitmap);
1810 pScreen->pvScreenBitmap = NULL;
1811 }
1812}
1813
1814
1815/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1816static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1817{
1818 //DEBUG_BREAKPOINT_TEST();
1819 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1820
1821 /* "Binding a surface to a Screen Target the same as flipping" */
1822
1823 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1824 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1825 RT_UNTRUSTED_VALIDATED_FENCE();
1826
1827 /* Assign the surface to the screen target. */
1828 int rc = VINF_SUCCESS;
1829 if (pCmd->image.sid != SVGA_ID_INVALID)
1830 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1831 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1832 if (RT_SUCCESS(rc))
1833 {
1834 SVGAOTableScreenTargetEntry entry;
1835 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1836 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1837 if (RT_SUCCESS(rc))
1838 {
1839 entry.image = pCmd->image;
1840 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1841 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1842 if (RT_SUCCESS(rc))
1843 {
1844 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1845 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1846 AssertRC(rc);
1847 }
1848 }
1849 }
1850}
1851
1852
1853/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1854static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1855{
1856 //DEBUG_BREAKPOINT_TEST();
1857 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1858
1859 /* Update the screen target from its backing surface. */
1860 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1861 RT_UNTRUSTED_VALIDATED_FENCE();
1862
1863 /* Get the screen target info. */
1864 SVGAOTableScreenTargetEntry entryScreenTarget;
1865 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1866 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1867 if (RT_SUCCESS(rc))
1868 {
1869 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1870 RT_UNTRUSTED_VALIDATED_FENCE();
1871
1872 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1873 {
1874 SVGAOTableSurfaceEntry entrySurface;
1875 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1876 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1877 if (RT_SUCCESS(rc))
1878 {
1879 /* Copy entrySurface.mobid content to the screen target. */
1880 if (entrySurface.mobid != SVGA_ID_INVALID)
1881 {
1882 RT_UNTRUSTED_VALIDATED_FENCE();
1883 SVGA3dRect targetRect = pCmd->rect;
1884
1885 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1886 if (pScreen->pHwScreen)
1887 {
1888 /* Copy the screen target surface to the backend's screen. */
1889 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1890 }
1891 else if (pScreen->pvScreenBitmap)
1892 {
1893 /* Copy the screen target surface to the memory buffer. */
1894 SVGA3dBox box; /* SurfaceMap will clip the box as necessary. */
1895 box.x = pCmd->rect.x;
1896 box.y = pCmd->rect.y;
1897 box.z = 0;
1898 box.w = pCmd->rect.w;
1899 box.h = pCmd->rect.h;
1900 box.d = 1;
1901
1902 VMSVGA3D_MAPPED_SURFACE map;
1903 rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, &box, VMSVGA3D_SURFACE_MAP_READ, &map);
1904 if (RT_SUCCESS(rc))
1905 {
1906 VMSGA3D_BOX_DIMENSIONS dims;
1907 rc = vmsvga3dGetBoxDimensions(pThisCC, &entryScreenTarget.image, &map.box, &dims);
1908 if (RT_SUCCESS(rc))
1909 {
1910 uint8_t const *pu8Src = (uint8_t *)map.pvData;
1911 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap + dims.offSubresource + dims.offBox;
1912 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1913 {
1914 memcpy(pu8Dst, pu8Src, dims.cbRow);
1915
1916 pu8Src += map.cbRowPitch;
1917 pu8Dst += dims.cbPitch;
1918 }
1919 }
1920
1921 vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1922
1923 vmsvgaR3UpdateScreen(pThisCC, pScreen, map.box.x, map.box.y, map.box.w, map.box.h);
1924 }
1925 else
1926 AssertFailed();
1927 }
1928 }
1929 }
1930 }
1931 }
1932}
1933
1934
1935/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1936static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1937{
1938 //DEBUG_BREAKPOINT_TEST();
1939 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1940
1941 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1942 SVGAOTableSurfaceEntry entry;
1943 RT_ZERO(entry);
1944 entry.format = pCmd->format;
1945 entry.surface1Flags = pCmd->surfaceFlags;
1946 entry.numMipLevels = pCmd->numMipLevels;
1947 entry.multisampleCount = pCmd->multisampleCount;
1948 entry.autogenFilter = pCmd->autogenFilter;
1949 entry.size = pCmd->size;
1950 entry.mobid = SVGA_ID_INVALID;
1951 entry.arraySize = pCmd->arraySize;
1952 // entry.mobPitch = 0;
1953 // entry.mobPitch = 0;
1954 // entry.surface2Flags = 0;
1955 // entry.multisamplePattern = 0;
1956 // entry.qualityLevel = 0;
1957 // entry.bufferByteStride = 0;
1958 // entry.minLOD = 0;
1959
1960 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1961 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1962 if (RT_SUCCESS(rc))
1963 {
1964 /* Create the host surface. */
1965 /** @todo SVGAOTableSurfaceEntry as input parameter? */
1966 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1967 pCmd->multisampleCount, pCmd->autogenFilter,
1968 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
1969 }
1970}
1971
1972
1973/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1974static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1975{
1976 //DEBUG_BREAKPOINT_TEST();
1977 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1978
1979 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1980
1981 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1982 /* Allocate a structure for the MOB. */
1983 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1984 AssertPtrReturnVoid(pMob);
1985
1986 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1987 if (RT_SUCCESS(rc))
1988 {
1989 return;
1990 }
1991
1992 RTMemFree(pMob);
1993}
1994
1995
1996/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1997static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1998{
1999#ifdef VMSVGA3D_DX
2000 //DEBUG_BREAKPOINT_TEST();
2001 RT_NOREF(cbCmd);
2002
2003 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2004
2005 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2006 SVGAOTableDXContextEntry entry;
2007 RT_ZERO(entry);
2008 entry.cid = pCmd->cid;
2009 entry.mobid = SVGA_ID_INVALID;
2010 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2011 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2012 if (RT_SUCCESS(rc))
2013 {
2014 /* Create the host context. */
2015 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
2016 }
2017
2018 return rc;
2019#else
2020 RT_NOREF(pThisCC, pCmd, cbCmd);
2021 return VERR_NOT_SUPPORTED;
2022#endif
2023}
2024
2025
2026/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2027static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2028{
2029#ifdef VMSVGA3D_DX
2030 //DEBUG_BREAKPOINT_TEST();
2031 RT_NOREF(cbCmd);
2032
2033 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2034
2035 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2036 SVGAOTableDXContextEntry entry;
2037 RT_ZERO(entry);
2038 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2039 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2040
2041 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2042#else
2043 RT_NOREF(pThisCC, pCmd, cbCmd);
2044 return VERR_NOT_SUPPORTED;
2045#endif
2046}
2047
2048
2049/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2050static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2051{
2052#ifdef VMSVGA3D_DX
2053 //DEBUG_BREAKPOINT_TEST();
2054 RT_NOREF(cbCmd);
2055
2056 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2057
2058 /* Assign a mobid to a cid. */
2059 int rc = VINF_SUCCESS;
2060 if (pCmd->mobid != SVGA_ID_INVALID)
2061 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2062 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2063 if (RT_SUCCESS(rc))
2064 {
2065 SVGAOTableDXContextEntry entry;
2066 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2067 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2068 if (RT_SUCCESS(rc))
2069 {
2070 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2071 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2072 {
2073 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2074 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2075 if (pSvgaDXContext)
2076 {
2077 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2078 if (RT_SUCCESS(rc))
2079 {
2080 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2081 if (pMob)
2082 {
2083 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2084 }
2085 }
2086
2087 RTMemFree(pSvgaDXContext);
2088 pSvgaDXContext = NULL;
2089 }
2090 }
2091
2092 if (pCmd->mobid != SVGA_ID_INVALID)
2093 {
2094 /* Bind a new context. Copy existing data from the guest backing memory. */
2095 if (pCmd->validContents)
2096 {
2097 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2098 if (pMob)
2099 {
2100 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2101 if (pSvgaDXContext)
2102 {
2103 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2104 if (RT_FAILURE(rc))
2105 {
2106 RTMemFree(pSvgaDXContext);
2107 pSvgaDXContext = NULL;
2108 }
2109 }
2110 }
2111 }
2112
2113 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2114
2115 RTMemFree(pSvgaDXContext);
2116 }
2117
2118 /* Update the object table. */
2119 entry.mobid = pCmd->mobid;
2120 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2121 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2122 }
2123 }
2124
2125 return rc;
2126#else
2127 RT_NOREF(pThisCC, pCmd, cbCmd);
2128 return VERR_NOT_SUPPORTED;
2129#endif
2130}
2131
2132
2133/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2134static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2135{
2136#ifdef VMSVGA3D_DX
2137 //DEBUG_BREAKPOINT_TEST();
2138 RT_NOREF(cbCmd);
2139
2140 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2141
2142 /* "Request that the device flush the contents back into guest memory." */
2143 SVGAOTableDXContextEntry entry;
2144 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2145 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2146 if (RT_SUCCESS(rc))
2147 {
2148 if (entry.mobid != SVGA_ID_INVALID)
2149 {
2150 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2151 if (pMob)
2152 {
2153 /* Get the content. */
2154 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2155 if (pSvgaDXContext)
2156 {
2157 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2158 if (RT_SUCCESS(rc))
2159 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2160
2161 RTMemFree(pSvgaDXContext);
2162 }
2163 else
2164 rc = VERR_NO_MEMORY;
2165 }
2166 }
2167 }
2168
2169 return rc;
2170#else
2171 RT_NOREF(pThisCC, pCmd, cbCmd);
2172 return VERR_NOT_SUPPORTED;
2173#endif
2174}
2175
2176
2177/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2178static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2179{
2180#ifdef VMSVGA3D_DX
2181 DEBUG_BREAKPOINT_TEST();
2182 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2183 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2184 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2185#else
2186 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2187 return VERR_NOT_SUPPORTED;
2188#endif
2189}
2190
2191
2192/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2193static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2194{
2195#ifdef VMSVGA3D_DX
2196 //DEBUG_BREAKPOINT_TEST();
2197 RT_NOREF(cbCmd);
2198 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2199#else
2200 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2201 return VERR_NOT_SUPPORTED;
2202#endif
2203}
2204
2205
2206/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2207static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2208{
2209#ifdef VMSVGA3D_DX
2210 //DEBUG_BREAKPOINT_TEST();
2211 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2212 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2213 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2214#else
2215 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2216 return VERR_NOT_SUPPORTED;
2217#endif
2218}
2219
2220
2221/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2222static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2223{
2224#ifdef VMSVGA3D_DX
2225 //DEBUG_BREAKPOINT_TEST();
2226 RT_NOREF(cbCmd);
2227 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2228#else
2229 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2230 return VERR_NOT_SUPPORTED;
2231#endif
2232}
2233
2234
2235/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2236static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2237{
2238#ifdef VMSVGA3D_DX
2239 //DEBUG_BREAKPOINT_TEST();
2240 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2241 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2242 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2243#else
2244 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2245 return VERR_NOT_SUPPORTED;
2246#endif
2247}
2248
2249
2250/* SVGA_3D_CMD_DX_DRAW 1152 */
2251static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2252{
2253#ifdef VMSVGA3D_DX
2254 //DEBUG_BREAKPOINT_TEST();
2255 RT_NOREF(cbCmd);
2256 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2257#else
2258 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2259 return VERR_NOT_SUPPORTED;
2260#endif
2261}
2262
2263
2264/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2265static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2266{
2267#ifdef VMSVGA3D_DX
2268 //DEBUG_BREAKPOINT_TEST();
2269 RT_NOREF(cbCmd);
2270 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2271#else
2272 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2273 return VERR_NOT_SUPPORTED;
2274#endif
2275}
2276
2277
2278/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2279static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2280{
2281#ifdef VMSVGA3D_DX
2282 //DEBUG_BREAKPOINT_TEST();
2283 RT_NOREF(cbCmd);
2284 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2285#else
2286 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2287 return VERR_NOT_SUPPORTED;
2288#endif
2289}
2290
2291
2292/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2293static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2294{
2295#ifdef VMSVGA3D_DX
2296 //DEBUG_BREAKPOINT_TEST();
2297 RT_NOREF(cbCmd);
2298 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2299#else
2300 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2301 return VERR_NOT_SUPPORTED;
2302#endif
2303}
2304
2305
2306/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2307static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2308{
2309#ifdef VMSVGA3D_DX
2310 DEBUG_BREAKPOINT_TEST();
2311 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2312 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2313 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2314#else
2315 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2316 return VERR_NOT_SUPPORTED;
2317#endif
2318}
2319
2320
2321/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2322static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2323{
2324#ifdef VMSVGA3D_DX
2325 //DEBUG_BREAKPOINT_TEST();
2326 RT_NOREF(cbCmd);
2327 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2328#else
2329 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2330 return VERR_NOT_SUPPORTED;
2331#endif
2332}
2333
2334
2335/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2336static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2337{
2338#ifdef VMSVGA3D_DX
2339 //DEBUG_BREAKPOINT_TEST();
2340 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2341 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2342 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2343#else
2344 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2345 return VERR_NOT_SUPPORTED;
2346#endif
2347}
2348
2349
2350/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2351static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2352{
2353#ifdef VMSVGA3D_DX
2354 //DEBUG_BREAKPOINT_TEST();
2355 RT_NOREF(cbCmd);
2356 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2357#else
2358 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2359 return VERR_NOT_SUPPORTED;
2360#endif
2361}
2362
2363
2364/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2365static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2366{
2367#ifdef VMSVGA3D_DX
2368 //DEBUG_BREAKPOINT_TEST();
2369 RT_NOREF(cbCmd);
2370 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2371#else
2372 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2373 return VERR_NOT_SUPPORTED;
2374#endif
2375}
2376
2377
2378/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2379static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2380{
2381#ifdef VMSVGA3D_DX
2382 //DEBUG_BREAKPOINT_TEST();
2383 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2384 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2385 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2386#else
2387 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2388 return VERR_NOT_SUPPORTED;
2389#endif
2390}
2391
2392
2393/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2394static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2395{
2396#ifdef VMSVGA3D_DX
2397 //DEBUG_BREAKPOINT_TEST();
2398 RT_NOREF(cbCmd);
2399 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2400#else
2401 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2402 return VERR_NOT_SUPPORTED;
2403#endif
2404}
2405
2406
2407/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2408static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2409{
2410#ifdef VMSVGA3D_DX
2411 //DEBUG_BREAKPOINT_TEST();
2412 RT_NOREF(cbCmd);
2413 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2414#else
2415 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2416 return VERR_NOT_SUPPORTED;
2417#endif
2418}
2419
2420
2421/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2422static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2423{
2424#ifdef VMSVGA3D_DX
2425 //DEBUG_BREAKPOINT_TEST();
2426 RT_NOREF(cbCmd);
2427 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2428#else
2429 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2430 return VERR_NOT_SUPPORTED;
2431#endif
2432}
2433
2434
2435/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2436static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2437{
2438#ifdef VMSVGA3D_DX
2439 //DEBUG_BREAKPOINT_TEST();
2440 RT_NOREF(cbCmd);
2441 return vmsvga3dDXDefineQuery(pThisCC, idDXContext, pCmd);
2442#else
2443 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2444 return VERR_NOT_SUPPORTED;
2445#endif
2446}
2447
2448
2449/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2450static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2451{
2452#ifdef VMSVGA3D_DX
2453 //DEBUG_BREAKPOINT_TEST();
2454 RT_NOREF(cbCmd);
2455 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext, pCmd);
2456#else
2457 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2458 return VERR_NOT_SUPPORTED;
2459#endif
2460}
2461
2462
2463/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2464static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2465{
2466#ifdef VMSVGA3D_DX
2467 //DEBUG_BREAKPOINT_TEST();
2468 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2469 RT_NOREF(cbCmd);
2470 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2471 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2472 return vmsvga3dDXBindQuery(pThisCC, idDXContext, pCmd, pMob);
2473#else
2474 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2475 return VERR_NOT_SUPPORTED;
2476#endif
2477}
2478
2479
2480/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2481static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2482{
2483#ifdef VMSVGA3D_DX
2484 //DEBUG_BREAKPOINT_TEST();
2485 RT_NOREF(cbCmd);
2486 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext, pCmd);
2487#else
2488 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2489 return VERR_NOT_SUPPORTED;
2490#endif
2491}
2492
2493
2494/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2495static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2496{
2497#ifdef VMSVGA3D_DX
2498 //DEBUG_BREAKPOINT_TEST();
2499 RT_NOREF(cbCmd);
2500 return vmsvga3dDXBeginQuery(pThisCC, idDXContext, pCmd);
2501#else
2502 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2503 return VERR_NOT_SUPPORTED;
2504#endif
2505}
2506
2507
2508/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2509static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2510{
2511#ifdef VMSVGA3D_DX
2512 //DEBUG_BREAKPOINT_TEST();
2513 RT_NOREF(cbCmd);
2514 return vmsvga3dDXEndQuery(pThisCC, idDXContext, pCmd);
2515#else
2516 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2517 return VERR_NOT_SUPPORTED;
2518#endif
2519}
2520
2521
2522/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2523static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2524{
2525#ifdef VMSVGA3D_DX
2526 //DEBUG_BREAKPOINT_TEST();
2527 RT_NOREF(cbCmd);
2528 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext, pCmd);
2529#else
2530 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2531 return VERR_NOT_SUPPORTED;
2532#endif
2533}
2534
2535
2536/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2537static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2538{
2539#ifdef VMSVGA3D_DX
2540 //DEBUG_BREAKPOINT_TEST();
2541 RT_NOREF(cbCmd);
2542 return vmsvga3dDXSetPredication(pThisCC, idDXContext, pCmd);
2543#else
2544 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2545 return VERR_NOT_SUPPORTED;
2546#endif
2547}
2548
2549
2550/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2551static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2552{
2553#ifdef VMSVGA3D_DX
2554 //DEBUG_BREAKPOINT_TEST();
2555 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2556 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2557 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2558#else
2559 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2560 return VERR_NOT_SUPPORTED;
2561#endif
2562}
2563
2564
2565/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2566static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2567{
2568#ifdef VMSVGA3D_DX
2569 //DEBUG_BREAKPOINT_TEST();
2570 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2571 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2572 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2573#else
2574 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2575 return VERR_NOT_SUPPORTED;
2576#endif
2577}
2578
2579
2580/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2581static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2582{
2583#ifdef VMSVGA3D_DX
2584 //DEBUG_BREAKPOINT_TEST();
2585 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2586 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2587 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2588#else
2589 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2590 return VERR_NOT_SUPPORTED;
2591#endif
2592}
2593
2594
2595/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2596static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2597{
2598#ifdef VMSVGA3D_DX
2599 //DEBUG_BREAKPOINT_TEST();
2600 RT_NOREF(cbCmd);
2601 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2602#else
2603 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2604 return VERR_NOT_SUPPORTED;
2605#endif
2606}
2607
2608
2609/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2610static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2611{
2612#ifdef VMSVGA3D_DX
2613 //DEBUG_BREAKPOINT_TEST();
2614 RT_NOREF(cbCmd);
2615 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2616#else
2617 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2618 return VERR_NOT_SUPPORTED;
2619#endif
2620}
2621
2622
2623/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2624static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2625{
2626#ifdef VMSVGA3D_DX
2627 //DEBUG_BREAKPOINT_TEST();
2628 RT_NOREF(cbCmd);
2629 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2630#else
2631 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2632 return VERR_NOT_SUPPORTED;
2633#endif
2634}
2635
2636
2637/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2638static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2639{
2640#ifdef VMSVGA3D_DX
2641 //DEBUG_BREAKPOINT_TEST();
2642 RT_NOREF(cbCmd);
2643 return vmsvga3dDXPredCopy(pThisCC, idDXContext, pCmd);
2644#else
2645 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2646 return VERR_NOT_SUPPORTED;
2647#endif
2648}
2649
2650
2651/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2652static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2653{
2654#ifdef VMSVGA3D_DX
2655 DEBUG_BREAKPOINT_TEST();
2656 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2657 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2658 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2659#else
2660 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2661 return VERR_NOT_SUPPORTED;
2662#endif
2663}
2664
2665
2666/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2667static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2668{
2669#ifdef VMSVGA3D_DX
2670 //DEBUG_BREAKPOINT_TEST();
2671 RT_NOREF(cbCmd);
2672 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2673#else
2674 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2675 return VERR_NOT_SUPPORTED;
2676#endif
2677}
2678
2679
2680/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2681static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2682{
2683#ifdef VMSVGA3D_DX
2684 //DEBUG_BREAKPOINT_TEST();
2685 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2686 RT_NOREF(cbCmd);
2687
2688 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2689 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2690
2691 /* "Inform the device that the guest-contents have been updated." */
2692 SVGAOTableSurfaceEntry entrySurface;
2693 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2694 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2695 if (RT_SUCCESS(rc))
2696 {
2697 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2698 if (pMob)
2699 {
2700 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2701 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2702 /* pCmd->box will be verified by the mapping function. */
2703 RT_UNTRUSTED_VALIDATED_FENCE();
2704
2705 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2706 SVGA3dSurfaceImageId image;
2707 image.sid = pCmd->sid;
2708 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2709
2710 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2711 AssertRC(rc);
2712 }
2713 }
2714
2715 return rc;
2716#else
2717 RT_NOREF(pThisCC, pCmd, cbCmd);
2718 return VERR_NOT_SUPPORTED;
2719#endif
2720}
2721
2722
2723/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2724static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2725{
2726#ifdef VMSVGA3D_DX
2727 //DEBUG_BREAKPOINT_TEST();
2728 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2729 RT_NOREF(cbCmd);
2730
2731 LogFlowFunc(("sid=%u, subResource=%u\n",
2732 pCmd->sid, pCmd->subResource));
2733
2734 /* "Request the device to flush the dirty contents into the guest." */
2735 SVGAOTableSurfaceEntry entrySurface;
2736 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2737 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2738 if (RT_SUCCESS(rc))
2739 {
2740 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2741 if (pMob)
2742 {
2743 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2744 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2745 RT_UNTRUSTED_VALIDATED_FENCE();
2746
2747 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2748 SVGA3dSurfaceImageId image;
2749 image.sid = pCmd->sid;
2750 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2751
2752 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2753 AssertRC(rc);
2754 }
2755 }
2756
2757 return rc;
2758#else
2759 RT_NOREF(pThisCC, pCmd, cbCmd);
2760 return VERR_NOT_SUPPORTED;
2761#endif
2762}
2763
2764
2765/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2766static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2767{
2768#ifdef VMSVGA3D_DX
2769 DEBUG_BREAKPOINT_TEST();
2770 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2771 RT_NOREF(cbCmd);
2772
2773 LogFlowFunc(("sid=%u, subResource=%u\n",
2774 pCmd->sid, pCmd->subResource));
2775
2776 /* "Notify the device that the contents can be lost." */
2777 SVGAOTableSurfaceEntry entrySurface;
2778 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2779 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2780 if (RT_SUCCESS(rc))
2781 {
2782 uint32_t iFace;
2783 uint32_t iMipmap;
2784 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2785 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2786 }
2787
2788 return rc;
2789#else
2790 RT_NOREF(pThisCC, pCmd, cbCmd);
2791 return VERR_NOT_SUPPORTED;
2792#endif
2793}
2794
2795
2796/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2797static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2798{
2799#ifdef VMSVGA3D_DX
2800 //DEBUG_BREAKPOINT_TEST();
2801 RT_NOREF(cbCmd);
2802 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2803#else
2804 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2805 return VERR_NOT_SUPPORTED;
2806#endif
2807}
2808
2809
2810/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2811static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2812{
2813#ifdef VMSVGA3D_DX
2814 //DEBUG_BREAKPOINT_TEST();
2815 RT_NOREF(cbCmd);
2816 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2817#else
2818 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2819 return VERR_NOT_SUPPORTED;
2820#endif
2821}
2822
2823
2824/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2825static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2826{
2827#ifdef VMSVGA3D_DX
2828 //DEBUG_BREAKPOINT_TEST();
2829 RT_NOREF(cbCmd);
2830 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2831#else
2832 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2833 return VERR_NOT_SUPPORTED;
2834#endif
2835}
2836
2837
2838/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2839static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2840{
2841#ifdef VMSVGA3D_DX
2842 //DEBUG_BREAKPOINT_TEST();
2843 RT_NOREF(cbCmd);
2844 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2845#else
2846 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2847 return VERR_NOT_SUPPORTED;
2848#endif
2849}
2850
2851
2852/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2853static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2854{
2855#ifdef VMSVGA3D_DX
2856 //DEBUG_BREAKPOINT_TEST();
2857 RT_NOREF(cbCmd);
2858 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2859 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2860 cmd.sid = pCmd->sid;
2861 cmd.format = pCmd->format;
2862 cmd.resourceDimension = pCmd->resourceDimension;
2863 cmd.mipSlice = pCmd->mipSlice;
2864 cmd.firstArraySlice = pCmd->firstArraySlice;
2865 cmd.arraySize = pCmd->arraySize;
2866 cmd.flags = 0;
2867 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2868#else
2869 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2870 return VERR_NOT_SUPPORTED;
2871#endif
2872}
2873
2874
2875/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2876static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2877{
2878#ifdef VMSVGA3D_DX
2879 //DEBUG_BREAKPOINT_TEST();
2880 RT_NOREF(cbCmd);
2881 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2882#else
2883 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2884 return VERR_NOT_SUPPORTED;
2885#endif
2886}
2887
2888
2889/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2890static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2891{
2892#ifdef VMSVGA3D_DX
2893 //DEBUG_BREAKPOINT_TEST();
2894 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2895 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2896 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2897#else
2898 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2899 return VERR_NOT_SUPPORTED;
2900#endif
2901}
2902
2903
2904/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2905static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2906{
2907#ifdef VMSVGA3D_DX
2908 //DEBUG_BREAKPOINT_TEST();
2909 RT_NOREF(cbCmd);
2910 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext, pCmd);
2911#else
2912 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2913 return VERR_NOT_SUPPORTED;
2914#endif
2915}
2916
2917
2918/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2919static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2920{
2921#ifdef VMSVGA3D_DX
2922 //DEBUG_BREAKPOINT_TEST();
2923 RT_NOREF(cbCmd);
2924 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2925#else
2926 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2927 return VERR_NOT_SUPPORTED;
2928#endif
2929}
2930
2931
2932/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2933static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2934{
2935#ifdef VMSVGA3D_DX
2936 //DEBUG_BREAKPOINT_TEST();
2937 RT_NOREF(cbCmd);
2938 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext, pCmd);
2939#else
2940 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2941 return VERR_NOT_SUPPORTED;
2942#endif
2943}
2944
2945
2946/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2947static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2948{
2949#ifdef VMSVGA3D_DX
2950 //DEBUG_BREAKPOINT_TEST();
2951 RT_NOREF(cbCmd);
2952 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2953#else
2954 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2955 return VERR_NOT_SUPPORTED;
2956#endif
2957}
2958
2959
2960/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2961static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2962{
2963#ifdef VMSVGA3D_DX
2964 //DEBUG_BREAKPOINT_TEST();
2965 RT_NOREF(cbCmd);
2966 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd);
2967#else
2968 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2969 return VERR_NOT_SUPPORTED;
2970#endif
2971}
2972
2973
2974/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2975static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2976{
2977#ifdef VMSVGA3D_DX
2978 //DEBUG_BREAKPOINT_TEST();
2979 RT_NOREF(cbCmd);
2980 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2981#else
2982 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2983 return VERR_NOT_SUPPORTED;
2984#endif
2985}
2986
2987
2988/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2989static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2990{
2991#ifdef VMSVGA3D_DX
2992 //DEBUG_BREAKPOINT_TEST();
2993 RT_NOREF(cbCmd);
2994 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext, pCmd);
2995#else
2996 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2997 return VERR_NOT_SUPPORTED;
2998#endif
2999}
3000
3001
3002/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3003static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3004{
3005#ifdef VMSVGA3D_DX
3006 //DEBUG_BREAKPOINT_TEST();
3007 RT_NOREF(cbCmd);
3008 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3009#else
3010 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3011 return VERR_NOT_SUPPORTED;
3012#endif
3013}
3014
3015
3016/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3017static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3018{
3019#ifdef VMSVGA3D_DX
3020 //DEBUG_BREAKPOINT_TEST();
3021 RT_NOREF(cbCmd);
3022 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext, pCmd);
3023#else
3024 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3025 return VERR_NOT_SUPPORTED;
3026#endif
3027}
3028
3029
3030/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3031static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3032{
3033#ifdef VMSVGA3D_DX
3034 //DEBUG_BREAKPOINT_TEST();
3035 RT_NOREF(cbCmd);
3036 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3037#else
3038 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3039 return VERR_NOT_SUPPORTED;
3040#endif
3041}
3042
3043
3044/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3045static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3046{
3047#ifdef VMSVGA3D_DX
3048 //DEBUG_BREAKPOINT_TEST();
3049 RT_NOREF(cbCmd);
3050 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3051#else
3052 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3053 return VERR_NOT_SUPPORTED;
3054#endif
3055}
3056
3057
3058/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3059static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3060{
3061#ifdef VMSVGA3D_DX
3062 //DEBUG_BREAKPOINT_TEST();
3063 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3064 RT_NOREF(idDXContext, cbCmd);
3065 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3066 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3067 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3068#else
3069 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3070 return VERR_NOT_SUPPORTED;
3071#endif
3072}
3073
3074
3075/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3076static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3077{
3078#ifdef VMSVGA3D_DX
3079 //DEBUG_BREAKPOINT_TEST();
3080 RT_NOREF(cbCmd);
3081 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3082#else
3083 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3084 return VERR_NOT_SUPPORTED;
3085#endif
3086}
3087
3088
3089/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3090static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3091{
3092#ifdef VMSVGA3D_DX
3093 //DEBUG_BREAKPOINT_TEST();
3094 RT_NOREF(cbCmd);
3095 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3096#else
3097 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3098 return VERR_NOT_SUPPORTED;
3099#endif
3100}
3101
3102
3103/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3104static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3105{
3106#ifdef VMSVGA3D_DX
3107 //DEBUG_BREAKPOINT_TEST();
3108 RT_NOREF(cbCmd);
3109 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3110#else
3111 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3112 return VERR_NOT_SUPPORTED;
3113#endif
3114}
3115
3116
3117/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3118static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3119{
3120#ifdef VMSVGA3D_DX
3121 //DEBUG_BREAKPOINT_TEST();
3122 RT_NOREF(cbCmd);
3123 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3124 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3125 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3126 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3127#else
3128 RT_NOREF(pThisCC, pCmd, cbCmd);
3129 return VERR_NOT_SUPPORTED;
3130#endif
3131}
3132
3133
3134/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3135static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3136{
3137#ifdef VMSVGA3D_DX
3138 //DEBUG_BREAKPOINT_TEST();
3139 RT_NOREF(idDXContext, cbCmd);
3140 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3141#else
3142 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3143 return VERR_NOT_SUPPORTED;
3144#endif
3145}
3146
3147
3148/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3149static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3150{
3151#ifdef VMSVGA3D_DX
3152 //DEBUG_BREAKPOINT_TEST();
3153 RT_NOREF(idDXContext, cbCmd);
3154
3155 int rc;
3156
3157 /** @todo Backend should o the copy is both buffers have a hardware resource. */
3158 SVGA3dSurfaceImageId imageBufferSrc;
3159 imageBufferSrc.sid = pCmd->src;
3160 imageBufferSrc.face = 0;
3161 imageBufferSrc.mipmap = 0;
3162
3163 SVGA3dSurfaceImageId imageBufferDest;
3164 imageBufferDest.sid = pCmd->dest;
3165 imageBufferDest.face = 0;
3166 imageBufferDest.mipmap = 0;
3167
3168 /*
3169 * Map the source buffer.
3170 */
3171 VMSVGA3D_MAPPED_SURFACE mapBufferSrc;
3172 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferSrc, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBufferSrc);
3173 if (RT_SUCCESS(rc))
3174 {
3175 /*
3176 * Map the destination buffer.
3177 */
3178 VMSVGA3D_MAPPED_SURFACE mapBufferDest;
3179 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferDest, NULL, VMSVGA3D_SURFACE_MAP_WRITE, &mapBufferDest);
3180 if (RT_SUCCESS(rc))
3181 {
3182 /*
3183 * Copy the source buffer to the destination.
3184 */
3185 uint8_t const *pu8BufferSrc = (uint8_t *)mapBufferSrc.pvData;
3186 uint32_t const cbBufferSrc = mapBufferSrc.cbRow;
3187
3188 uint8_t *pu8BufferDest = (uint8_t *)mapBufferDest.pvData;
3189 uint32_t const cbBufferDest = mapBufferDest.cbRow;
3190
3191 if ( pCmd->srcX < cbBufferSrc
3192 && pCmd->width <= cbBufferSrc- pCmd->srcX
3193 && pCmd->destX < cbBufferDest
3194 && pCmd->width <= cbBufferDest - pCmd->destX)
3195 {
3196 RT_UNTRUSTED_VALIDATED_FENCE();
3197
3198 memcpy(&pu8BufferDest[pCmd->destX], &pu8BufferSrc[pCmd->srcX], pCmd->width);
3199 }
3200 else
3201 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3202
3203 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferDest, &mapBufferDest, true);
3204 }
3205
3206 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferSrc, &mapBufferSrc, false);
3207 }
3208
3209 return rc;
3210#else
3211 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3212 return VERR_NOT_SUPPORTED;
3213#endif
3214}
3215
3216
3217/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3218static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3219{
3220#ifdef VMSVGA3D_DX
3221 //DEBUG_BREAKPOINT_TEST();
3222 RT_NOREF(cbCmd);
3223
3224 /* Plan:
3225 * - map the buffer;
3226 * - map the surface;
3227 * - copy from buffer map to the surface map.
3228 */
3229
3230 int rc;
3231
3232 SVGA3dSurfaceImageId imageBuffer;
3233 imageBuffer.sid = pCmd->srcSid;
3234 imageBuffer.face = 0;
3235 imageBuffer.mipmap = 0;
3236
3237 SVGA3dSurfaceImageId imageSurface;
3238 imageSurface.sid = pCmd->destSid;
3239 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3240 AssertRCReturn(rc, rc);
3241
3242 /*
3243 * Map the buffer.
3244 */
3245 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3246 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3247 if (RT_SUCCESS(rc))
3248 {
3249 /*
3250 * Map the surface.
3251 */
3252 VMSVGA3D_MAPPED_SURFACE mapSurface;
3253 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3254 if (RT_SUCCESS(rc))
3255 {
3256 /*
3257 * Copy the mapped buffer to the surface. "Raw byte wise transfer"
3258 */
3259 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3260 uint32_t const cbBuffer = mapBuffer.cbRow;
3261
3262 if (pCmd->srcOffset <= cbBuffer)
3263 {
3264 RT_UNTRUSTED_VALIDATED_FENCE();
3265 uint8_t const *pu8BufferBegin = pu8Buffer;
3266 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3267
3268 pu8Buffer += pCmd->srcOffset;
3269
3270 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3271
3272 uint32_t const cbRowCopy = RT_MIN(pCmd->srcPitch, mapSurface.cbRow);
3273 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3274 {
3275 uint8_t const *pu8BufferRow = pu8Buffer;
3276 uint8_t *pu8SurfaceRow = pu8Surface;
3277 for (uint32_t iRow = 0; iRow < mapSurface.cRows; ++iRow)
3278 {
3279 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3280 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3281 && (uintptr_t)pu8BufferRow < (uintptr_t)(pu8BufferRow + cbRowCopy)
3282 && (uintptr_t)(pu8BufferRow + cbRowCopy) > (uintptr_t)pu8BufferBegin
3283 && (uintptr_t)(pu8BufferRow + cbRowCopy) <= (uintptr_t)pu8BufferEnd,
3284 rc = VERR_INVALID_PARAMETER);
3285
3286 memcpy(pu8SurfaceRow, pu8BufferRow, cbRowCopy);
3287
3288 pu8SurfaceRow += mapSurface.cbRowPitch;
3289 pu8BufferRow += pCmd->srcPitch;
3290 }
3291
3292 pu8Buffer += pCmd->srcSlicePitch;
3293 pu8Surface += mapSurface.cbDepthPitch;
3294 }
3295 }
3296 else
3297 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3298
3299 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3300 }
3301
3302 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3303 }
3304
3305 return rc;
3306#else
3307 RT_NOREF(pThisCC, pCmd, cbCmd);
3308 return VERR_NOT_SUPPORTED;
3309#endif
3310}
3311
3312
3313/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3314static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3315{
3316#ifdef VMSVGA3D_DX
3317 DEBUG_BREAKPOINT_TEST();
3318 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3319 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3320 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3321#else
3322 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3323 return VERR_NOT_SUPPORTED;
3324#endif
3325}
3326
3327
3328/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3329static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3330{
3331#ifdef VMSVGA3D_DX
3332 DEBUG_BREAKPOINT_TEST();
3333 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3334 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3335 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3336#else
3337 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3338 return VERR_NOT_SUPPORTED;
3339#endif
3340}
3341
3342
3343/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3344static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3345{
3346#ifdef VMSVGA3D_DX
3347 //DEBUG_BREAKPOINT_TEST();
3348 RT_NOREF(cbCmd);
3349 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext, pCmd);
3350#else
3351 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3352 return VERR_NOT_SUPPORTED;
3353#endif
3354}
3355
3356
3357/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3358static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3359{
3360#ifdef VMSVGA3D_DX
3361 //DEBUG_BREAKPOINT_TEST();
3362 RT_NOREF(cbCmd);
3363 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext, pCmd);
3364#else
3365 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3366 return VERR_NOT_SUPPORTED;
3367#endif
3368}
3369
3370
3371/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3372static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3373{
3374#ifdef VMSVGA3D_DX
3375 //DEBUG_BREAKPOINT_TEST();
3376 RT_NOREF(idDXContext, cbCmd);
3377
3378 /* This command is executed in a context: "The context is implied from the command buffer header."
3379 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3380 */
3381 SVGA3dCmdDXTransferFromBuffer cmd;
3382 cmd.srcSid = pCmd->srcSid;
3383 cmd.srcOffset = pCmd->srcOffset;
3384 cmd.srcPitch = pCmd->srcPitch;
3385 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3386 cmd.destSid = pCmd->destSid;
3387 cmd.destSubResource = pCmd->destSubResource;
3388 cmd.destBox = pCmd->destBox;
3389 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3390#else
3391 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3392 return VERR_NOT_SUPPORTED;
3393#endif
3394}
3395
3396
3397/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3398static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3399{
3400#ifdef VMSVGA3D_DX
3401 //DEBUG_BREAKPOINT_TEST();
3402 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3403 RT_NOREF(cbCmd);
3404
3405 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobId);
3406 ASSERT_GUEST_RETURN(pMob, VERR_INVALID_PARAMETER);
3407
3408 int rc = vmsvgaR3MobWrite(pSvgaR3State, pMob, pCmd->mobOffset, &pCmd->value, sizeof(pCmd->value));
3409 ASSERT_GUEST_RETURN(RT_SUCCESS(rc), rc);
3410
3411 return VINF_SUCCESS;
3412#else
3413 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3414 return VERR_NOT_SUPPORTED;
3415#endif
3416}
3417
3418
3419/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3420static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3421{
3422#ifdef VMSVGA3D_DX
3423 DEBUG_BREAKPOINT_TEST();
3424 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3425 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3426 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3427#else
3428 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3429 return VERR_NOT_SUPPORTED;
3430#endif
3431}
3432
3433
3434/* SVGA_3D_CMD_DX_HINT 1218 */
3435static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3436{
3437#ifdef VMSVGA3D_DX
3438 DEBUG_BREAKPOINT_TEST();
3439 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3440 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3441 return vmsvga3dDXHint(pThisCC, idDXContext);
3442#else
3443 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3444 return VERR_NOT_SUPPORTED;
3445#endif
3446}
3447
3448
3449/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3450static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3451{
3452#ifdef VMSVGA3D_DX
3453 DEBUG_BREAKPOINT_TEST();
3454 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3455 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3456 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3457#else
3458 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3459 return VERR_NOT_SUPPORTED;
3460#endif
3461}
3462
3463
3464/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3465static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3466{
3467#ifdef VMSVGA3D_DX
3468 DEBUG_BREAKPOINT_TEST();
3469 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3470 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3471 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3472#else
3473 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3474 return VERR_NOT_SUPPORTED;
3475#endif
3476}
3477
3478
3479/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3480static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3481{
3482#ifdef VMSVGA3D_DX
3483 DEBUG_BREAKPOINT_TEST();
3484 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3485 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3486 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3487#else
3488 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3489 return VERR_NOT_SUPPORTED;
3490#endif
3491}
3492
3493
3494/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3495static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3496{
3497#ifdef VMSVGA3D_DX
3498 DEBUG_BREAKPOINT_TEST();
3499 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3500 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3501 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3502#else
3503 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3504 return VERR_NOT_SUPPORTED;
3505#endif
3506}
3507
3508
3509/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3510static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3511{
3512#ifdef VMSVGA3D_DX
3513 DEBUG_BREAKPOINT_TEST();
3514 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3515 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3516 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3517#else
3518 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3519 return VERR_NOT_SUPPORTED;
3520#endif
3521}
3522
3523
3524/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3525static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3526{
3527#ifdef VMSVGA3D_DX
3528 DEBUG_BREAKPOINT_TEST();
3529 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3530 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3531 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3532#else
3533 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3534 return VERR_NOT_SUPPORTED;
3535#endif
3536}
3537
3538
3539/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3540static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3541{
3542#ifdef VMSVGA3D_DX
3543 DEBUG_BREAKPOINT_TEST();
3544 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3545 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3546 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3547#else
3548 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3549 return VERR_NOT_SUPPORTED;
3550#endif
3551}
3552
3553
3554/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3555static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3556{
3557#ifdef VMSVGA3D_DX
3558 DEBUG_BREAKPOINT_TEST();
3559 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3560 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3561 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3562#else
3563 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3564 return VERR_NOT_SUPPORTED;
3565#endif
3566}
3567
3568
3569/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3570static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3571{
3572#ifdef VMSVGA3D_DX
3573 DEBUG_BREAKPOINT_TEST();
3574 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3575 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3576 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3577#else
3578 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3579 return VERR_NOT_SUPPORTED;
3580#endif
3581}
3582
3583
3584/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3585static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3586{
3587#ifdef VMSVGA3D_DX
3588 DEBUG_BREAKPOINT_TEST();
3589 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3590 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3591 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3592#else
3593 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3594 return VERR_NOT_SUPPORTED;
3595#endif
3596}
3597
3598
3599/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3600static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3601{
3602#ifdef VMSVGA3D_DX
3603 DEBUG_BREAKPOINT_TEST();
3604 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3605 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3606 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3607#else
3608 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3609 return VERR_NOT_SUPPORTED;
3610#endif
3611}
3612
3613
3614/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3615static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3616{
3617#ifdef VMSVGA3D_DX
3618 DEBUG_BREAKPOINT_TEST();
3619 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3620 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3621 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3622#else
3623 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3624 return VERR_NOT_SUPPORTED;
3625#endif
3626}
3627
3628
3629/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3630static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd)
3631{
3632#ifdef VMSVGA3D_DX
3633 DEBUG_BREAKPOINT_TEST();
3634 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3635
3636 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
3637 SVGAOTableSurfaceEntry entry;
3638 RT_ZERO(entry);
3639 entry.format = pCmd->format;
3640 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
3641 entry.numMipLevels = pCmd->numMipLevels;
3642 entry.multisampleCount = pCmd->multisampleCount;
3643 entry.autogenFilter = pCmd->autogenFilter;
3644 entry.size = pCmd->size;
3645 entry.mobid = SVGA_ID_INVALID;
3646 entry.arraySize = pCmd->arraySize;
3647 // entry.mobPitch = 0;
3648 // entry.mobPitch = 0;
3649 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
3650 // entry.multisamplePattern = 0;
3651 // entry.qualityLevel = 0;
3652 // entry.bufferByteStride = 0;
3653 // entry.minLOD = 0;
3654
3655 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
3656 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
3657 if (RT_SUCCESS(rc))
3658 {
3659 /* Create the host surface. */
3660 /** @todo SVGAOTableSurfaceEntry as input parameter? */
3661 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
3662 pCmd->multisampleCount, pCmd->autogenFilter,
3663 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
3664 }
3665 return rc;
3666#else
3667 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3668 return VERR_NOT_SUPPORTED;
3669#endif
3670}
3671
3672
3673/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3674static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3675{
3676#ifdef VMSVGA3D_DX
3677 DEBUG_BREAKPOINT_TEST();
3678 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3679 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3680 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3681#else
3682 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3683 return VERR_NOT_SUPPORTED;
3684#endif
3685}
3686
3687
3688/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3689static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3690{
3691#ifdef VMSVGA3D_DX
3692 DEBUG_BREAKPOINT_TEST();
3693 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3694 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3695 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3696#else
3697 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3698 return VERR_NOT_SUPPORTED;
3699#endif
3700}
3701
3702
3703/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3704static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3705{
3706#ifdef VMSVGA3D_DX
3707 DEBUG_BREAKPOINT_TEST();
3708 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3709 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3710 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3711#else
3712 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3713 return VERR_NOT_SUPPORTED;
3714#endif
3715}
3716
3717
3718/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3719static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3720{
3721#ifdef VMSVGA3D_DX
3722 DEBUG_BREAKPOINT_TEST();
3723 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3724 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3725 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3726#else
3727 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3728 return VERR_NOT_SUPPORTED;
3729#endif
3730}
3731
3732
3733/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3734static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3735{
3736#ifdef VMSVGA3D_DX
3737 DEBUG_BREAKPOINT_TEST();
3738 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3739 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3740 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3741#else
3742 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3743 return VERR_NOT_SUPPORTED;
3744#endif
3745}
3746
3747
3748/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3749static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3750{
3751#ifdef VMSVGA3D_DX
3752 //DEBUG_BREAKPOINT_TEST();
3753 RT_NOREF(cbCmd);
3754 return vmsvga3dDXDefineUAView(pThisCC, idDXContext, pCmd);
3755#else
3756 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3757 return VERR_NOT_SUPPORTED;
3758#endif
3759}
3760
3761
3762/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3763static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3764{
3765#ifdef VMSVGA3D_DX
3766 //DEBUG_BREAKPOINT_TEST();
3767 RT_NOREF(cbCmd);
3768 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext, pCmd);
3769#else
3770 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3771 return VERR_NOT_SUPPORTED;
3772#endif
3773}
3774
3775
3776/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3777static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3778{
3779#ifdef VMSVGA3D_DX
3780 DEBUG_BREAKPOINT_TEST();
3781 RT_NOREF(cbCmd);
3782 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext, pCmd);
3783#else
3784 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3785 return VERR_NOT_SUPPORTED;
3786#endif
3787}
3788
3789
3790/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3791static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3792{
3793#ifdef VMSVGA3D_DX
3794 DEBUG_BREAKPOINT_TEST();
3795 RT_NOREF(cbCmd);
3796 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext, pCmd);
3797#else
3798 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3799 return VERR_NOT_SUPPORTED;
3800#endif
3801}
3802
3803
3804/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3805static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3806{
3807#ifdef VMSVGA3D_DX
3808 //DEBUG_BREAKPOINT_TEST();
3809 RT_NOREF(cbCmd);
3810 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext, pCmd);
3811#else
3812 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3813 return VERR_NOT_SUPPORTED;
3814#endif
3815}
3816
3817
3818/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3819static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3820{
3821#ifdef VMSVGA3D_DX
3822 //DEBUG_BREAKPOINT_TEST();
3823 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
3824 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
3825 return vmsvga3dDXSetUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
3826#else
3827 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3828 return VERR_NOT_SUPPORTED;
3829#endif
3830}
3831
3832
3833/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3834static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3835{
3836#ifdef VMSVGA3D_DX
3837 //DEBUG_BREAKPOINT_TEST();
3838 RT_NOREF(cbCmd);
3839 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd);
3840#else
3841 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3842 return VERR_NOT_SUPPORTED;
3843#endif
3844}
3845
3846
3847/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3848static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3849{
3850#ifdef VMSVGA3D_DX
3851 //DEBUG_BREAKPOINT_TEST();
3852 RT_NOREF(cbCmd);
3853 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd);
3854#else
3855 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3856 return VERR_NOT_SUPPORTED;
3857#endif
3858}
3859
3860
3861/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3862static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3863{
3864#ifdef VMSVGA3D_DX
3865 //DEBUG_BREAKPOINT_TEST();
3866 RT_NOREF(cbCmd);
3867 return vmsvga3dDXDispatch(pThisCC, idDXContext, pCmd);
3868#else
3869 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3870 return VERR_NOT_SUPPORTED;
3871#endif
3872}
3873
3874
3875/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3876static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3877{
3878#ifdef VMSVGA3D_DX
3879 DEBUG_BREAKPOINT_TEST();
3880 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3881 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3882 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3883#else
3884 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3885 return VERR_NOT_SUPPORTED;
3886#endif
3887}
3888
3889
3890/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3891static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3892{
3893#ifdef VMSVGA3D_DX
3894 DEBUG_BREAKPOINT_TEST();
3895 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3896 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3897 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3898#else
3899 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3900 return VERR_NOT_SUPPORTED;
3901#endif
3902}
3903
3904
3905/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3906static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3907{
3908#ifdef VMSVGA3D_DX
3909 DEBUG_BREAKPOINT_TEST();
3910 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3911 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3912 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3913#else
3914 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3915 return VERR_NOT_SUPPORTED;
3916#endif
3917}
3918
3919
3920/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3921static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3922{
3923#ifdef VMSVGA3D_DX
3924 DEBUG_BREAKPOINT_TEST();
3925 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3926 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3927 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3928#else
3929 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3930 return VERR_NOT_SUPPORTED;
3931#endif
3932}
3933
3934
3935/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3936static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3937{
3938#ifdef VMSVGA3D_DX
3939 //DEBUG_BREAKPOINT_TEST();
3940 RT_NOREF(cbCmd);
3941 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext, pCmd);
3942#else
3943 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3944 return VERR_NOT_SUPPORTED;
3945#endif
3946}
3947
3948
3949/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3950static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3951{
3952#ifdef VMSVGA3D_DX
3953 DEBUG_BREAKPOINT_TEST();
3954 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3955 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3956 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3957#else
3958 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3959 return VERR_NOT_SUPPORTED;
3960#endif
3961}
3962
3963
3964/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3965static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3966{
3967#ifdef VMSVGA3D_DX
3968 DEBUG_BREAKPOINT_TEST();
3969 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3970 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3971 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3972#else
3973 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3974 return VERR_NOT_SUPPORTED;
3975#endif
3976}
3977
3978
3979/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3980static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3981{
3982#ifdef VMSVGA3D_DX
3983 DEBUG_BREAKPOINT_TEST();
3984 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3985 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3986 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3987#else
3988 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3989 return VERR_NOT_SUPPORTED;
3990#endif
3991}
3992
3993
3994/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3995static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3996{
3997#ifdef VMSVGA3D_DX
3998 DEBUG_BREAKPOINT_TEST();
3999 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4000 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4001 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
4002#else
4003 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4004 return VERR_NOT_SUPPORTED;
4005#endif
4006}
4007
4008
4009/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
4010static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
4011{
4012#ifdef VMSVGA3D_DX
4013 DEBUG_BREAKPOINT_TEST();
4014 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4015 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4016 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
4017#else
4018 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4019 return VERR_NOT_SUPPORTED;
4020#endif
4021}
4022
4023
4024/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
4025static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
4026{
4027#ifdef VMSVGA3D_DX
4028 DEBUG_BREAKPOINT_TEST();
4029 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4030 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4031 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
4032#else
4033 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4034 return VERR_NOT_SUPPORTED;
4035#endif
4036}
4037
4038
4039/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
4040static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd)
4041{
4042#ifdef VMSVGA3D_DX
4043 //DEBUG_BREAKPOINT_TEST();
4044 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4045
4046 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
4047 SVGAOTableSurfaceEntry entry;
4048 RT_ZERO(entry);
4049 entry.format = pCmd->format;
4050 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
4051 entry.numMipLevels = pCmd->numMipLevels;
4052 entry.multisampleCount = pCmd->multisampleCount;
4053 entry.autogenFilter = pCmd->autogenFilter;
4054 entry.size = pCmd->size;
4055 entry.mobid = SVGA_ID_INVALID;
4056 entry.arraySize = pCmd->arraySize;
4057 // entry.mobPitch = 0;
4058 // entry.mobPitch = 0;
4059 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
4060 // entry.multisamplePattern = 0;
4061 // entry.qualityLevel = 0;
4062 entry.bufferByteStride = pCmd->bufferByteStride;
4063 // entry.minLOD = 0;
4064
4065 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
4066 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
4067 if (RT_SUCCESS(rc))
4068 {
4069 /* Create the host surface. */
4070 /** @todo SVGAOTableSurfaceEntry as input parameter? */
4071 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
4072 pCmd->multisampleCount, pCmd->autogenFilter,
4073 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
4074 }
4075 return rc;
4076#else
4077 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4078 return VERR_NOT_SUPPORTED;
4079#endif
4080}
4081
4082
4083/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
4084static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
4085{
4086#ifdef VMSVGA3D_DX
4087 //DEBUG_BREAKPOINT_TEST();
4088 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
4089 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
4090 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
4091#else
4092 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4093 return VERR_NOT_SUPPORTED;
4094#endif
4095}
4096
4097
4098/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
4099static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
4100{
4101#ifdef VMSVGA3D_DX
4102 DEBUG_BREAKPOINT_TEST();
4103 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4104 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4105 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4106#else
4107 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4108 return VERR_NOT_SUPPORTED;
4109#endif
4110}
4111
4112
4113/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4114static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4115{
4116#ifdef VMSVGA3D_DX
4117 //DEBUG_BREAKPOINT_TEST();
4118 RT_NOREF(cbCmd);
4119 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4120#else
4121 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4122 return VERR_NOT_SUPPORTED;
4123#endif
4124}
4125
4126
4127/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4128static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4129{
4130#ifdef VMSVGA3D_DX
4131 DEBUG_BREAKPOINT_TEST();
4132 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4133 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4134 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
4135#else
4136 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4137 return VERR_NOT_SUPPORTED;
4138#endif
4139}
4140
4141
4142/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4143static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4144{
4145#ifdef VMSVGA3D_DX
4146 DEBUG_BREAKPOINT_TEST();
4147 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4148 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4149 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4150#else
4151 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4152 return VERR_NOT_SUPPORTED;
4153#endif
4154}
4155
4156
4157/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4158static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4159{
4160#ifdef VMSVGA3D_DX
4161 DEBUG_BREAKPOINT_TEST();
4162 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4163 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4164 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
4165#else
4166 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4167 return VERR_NOT_SUPPORTED;
4168#endif
4169}
4170
4171
4172/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4173static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4174{
4175#ifdef VMSVGA3D_DX
4176 DEBUG_BREAKPOINT_TEST();
4177 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4178 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4179 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4180#else
4181 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4182 return VERR_NOT_SUPPORTED;
4183#endif
4184}
4185
4186
4187/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4188static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4189{
4190#ifdef VMSVGA3D_DX
4191 DEBUG_BREAKPOINT_TEST();
4192 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4193 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4194 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4195#else
4196 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4197 return VERR_NOT_SUPPORTED;
4198#endif
4199}
4200
4201
4202/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4203 * Check that the 3D command has at least a_cbMin of payload bytes after the
4204 * header. Will break out of the switch if it doesn't.
4205 */
4206# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4207 if (1) { \
4208 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4209 RT_UNTRUSTED_VALIDATED_FENCE(); \
4210 } else do {} while (0)
4211
4212# define VMSVGA_3D_CMD_NOTIMPL() \
4213 if (1) { \
4214 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4215 } else do {} while (0)
4216
4217/** SVGA_3D_CMD_* handler.
4218 * This function parses the command and calls the corresponding command handler.
4219 *
4220 * @param pThis The shared VGA/VMSVGA state.
4221 * @param pThisCC The VGA/VMSVGA state for the current context.
4222 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4223 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4224 * @param cbCmd Size of the command in bytes.
4225 * @param pvCmd Pointer to the command.
4226 * @returns VBox status code if an error was detected parsing a command.
4227 */
4228int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4229{
4230 if (enmCmdId > SVGA_3D_CMD_MAX)
4231 {
4232 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4233 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4234 }
4235
4236 int rcParse = VINF_SUCCESS;
4237 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4238
4239 switch (enmCmdId)
4240 {
4241 case SVGA_3D_CMD_SURFACE_DEFINE:
4242 {
4243 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4244 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4245 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4246
4247 SVGA3dCmdDefineSurface_v2 cmd;
4248 cmd.sid = pCmd->sid;
4249 cmd.surfaceFlags = pCmd->surfaceFlags;
4250 cmd.format = pCmd->format;
4251 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4252 cmd.multisampleCount = 0;
4253 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4254
4255 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4256 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4257# ifdef DEBUG_GMR_ACCESS
4258 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4259# endif
4260 break;
4261 }
4262
4263 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4264 {
4265 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4266 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4267 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4268
4269 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4270 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4271# ifdef DEBUG_GMR_ACCESS
4272 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4273# endif
4274 break;
4275 }
4276
4277 case SVGA_3D_CMD_SURFACE_DESTROY:
4278 {
4279 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4280 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4281 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4282
4283 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4284 break;
4285 }
4286
4287 case SVGA_3D_CMD_SURFACE_COPY:
4288 {
4289 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4290 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4291 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4292
4293 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4294 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4295 break;
4296 }
4297
4298 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4299 {
4300 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4301 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4302 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4303
4304 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4305 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4306 break;
4307 }
4308
4309 case SVGA_3D_CMD_SURFACE_DMA:
4310 {
4311 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4312 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4313 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4314
4315 uint64_t u64NanoTS = 0;
4316 if (LogRelIs3Enabled())
4317 u64NanoTS = RTTimeNanoTS();
4318 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4319 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4320 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4321 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4322 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4323 if (LogRelIs3Enabled())
4324 {
4325 if (cCopyBoxes)
4326 {
4327 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4328 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4329 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4330 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4331 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4332 }
4333 }
4334 break;
4335 }
4336
4337 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4338 {
4339 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4340 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4341 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4342
4343 static uint64_t u64FrameStartNanoTS = 0;
4344 static uint64_t u64ElapsedPerSecNano = 0;
4345 static int cFrames = 0;
4346 uint64_t u64NanoTS = 0;
4347 if (LogRelIs3Enabled())
4348 u64NanoTS = RTTimeNanoTS();
4349 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4350 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4351 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4352 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4353 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4354 if (LogRelIs3Enabled())
4355 {
4356 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4357 u64ElapsedPerSecNano += u64ElapsedNano;
4358
4359 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4360 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4361 (u64ElapsedNano) / 1000ULL, cRects,
4362 pFirstRect->left, pFirstRect->top,
4363 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4364
4365 ++cFrames;
4366 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4367 {
4368 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4369 cFrames, u64ElapsedPerSecNano / 1000ULL));
4370 u64FrameStartNanoTS = u64NanoTS;
4371 cFrames = 0;
4372 u64ElapsedPerSecNano = 0;
4373 }
4374 }
4375 break;
4376 }
4377
4378 case SVGA_3D_CMD_CONTEXT_DEFINE:
4379 {
4380 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4381 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4382 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4383
4384 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4385 break;
4386 }
4387
4388 case SVGA_3D_CMD_CONTEXT_DESTROY:
4389 {
4390 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4391 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4392 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4393
4394 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4395 break;
4396 }
4397
4398 case SVGA_3D_CMD_SETTRANSFORM:
4399 {
4400 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4401 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4402 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4403
4404 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4405 break;
4406 }
4407
4408 case SVGA_3D_CMD_SETZRANGE:
4409 {
4410 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4411 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4412 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4413
4414 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4415 break;
4416 }
4417
4418 case SVGA_3D_CMD_SETRENDERSTATE:
4419 {
4420 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4421 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4422 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4423
4424 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4425 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4426 break;
4427 }
4428
4429 case SVGA_3D_CMD_SETRENDERTARGET:
4430 {
4431 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4432 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4433 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4434
4435 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4436 break;
4437 }
4438
4439 case SVGA_3D_CMD_SETTEXTURESTATE:
4440 {
4441 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4442 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4443 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4444
4445 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4446 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4447 break;
4448 }
4449
4450 case SVGA_3D_CMD_SETMATERIAL:
4451 {
4452 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4453 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4454 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4455
4456 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4457 break;
4458 }
4459
4460 case SVGA_3D_CMD_SETLIGHTDATA:
4461 {
4462 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4463 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4464 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4465
4466 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4467 break;
4468 }
4469
4470 case SVGA_3D_CMD_SETLIGHTENABLED:
4471 {
4472 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4473 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4474 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4475
4476 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4477 break;
4478 }
4479
4480 case SVGA_3D_CMD_SETVIEWPORT:
4481 {
4482 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4483 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4484 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4485
4486 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4487 break;
4488 }
4489
4490 case SVGA_3D_CMD_SETCLIPPLANE:
4491 {
4492 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4493 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4494 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4495
4496 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4497 break;
4498 }
4499
4500 case SVGA_3D_CMD_CLEAR:
4501 {
4502 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4503 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4504 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4505
4506 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4507 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4508 break;
4509 }
4510
4511 case SVGA_3D_CMD_PRESENT:
4512 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4513 {
4514 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4515 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4516 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4517 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4518 else
4519 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4520
4521 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4522 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4523 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4524 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4525 break;
4526 }
4527
4528 case SVGA_3D_CMD_SHADER_DEFINE:
4529 {
4530 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4531 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4532 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4533
4534 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4535 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4536 break;
4537 }
4538
4539 case SVGA_3D_CMD_SHADER_DESTROY:
4540 {
4541 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4542 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4543 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4544
4545 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4546 break;
4547 }
4548
4549 case SVGA_3D_CMD_SET_SHADER:
4550 {
4551 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4552 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4553 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4554
4555 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4556 break;
4557 }
4558
4559 case SVGA_3D_CMD_SET_SHADER_CONST:
4560 {
4561 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4562 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4563 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4564
4565 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4566 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4567 break;
4568 }
4569
4570 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4571 {
4572 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4573 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4574 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4575
4576 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4577 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4578 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4579 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4580 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4581
4582 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4583 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4584 RT_UNTRUSTED_VALIDATED_FENCE();
4585
4586 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4587 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4588 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4589
4590 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4591 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4592 pNumRange, cVertexDivisor, pVertexDivisor);
4593 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4594 break;
4595 }
4596
4597 case SVGA_3D_CMD_SETSCISSORRECT:
4598 {
4599 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4600 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4601 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4602
4603 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4604 break;
4605 }
4606
4607 case SVGA_3D_CMD_BEGIN_QUERY:
4608 {
4609 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4610 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4611 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4612
4613 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4614 break;
4615 }
4616
4617 case SVGA_3D_CMD_END_QUERY:
4618 {
4619 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4620 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4621 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4622
4623 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4624 break;
4625 }
4626
4627 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4628 {
4629 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4631 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4632
4633 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4634 break;
4635 }
4636
4637 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4638 {
4639 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4640 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4641 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4642
4643 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4644 break;
4645 }
4646
4647 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4648 /* context id + surface id? */
4649 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4650 break;
4651
4652 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4653 /* context id + surface id? */
4654 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4655 break;
4656
4657 /*
4658 *
4659 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4660 *
4661 */
4662 case SVGA_3D_CMD_SCREEN_DMA:
4663 {
4664 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4665 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4666 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4667 break;
4668 }
4669
4670 case SVGA_3D_CMD_DEAD1:
4671 case SVGA_3D_CMD_DEAD2:
4672 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4673 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4674 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4675 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4676 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4677 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4678 {
4679 VMSVGA_3D_CMD_NOTIMPL();
4680 break;
4681 }
4682
4683 case SVGA_3D_CMD_SET_OTABLE_BASE:
4684 {
4685 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4686 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4687 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4688 break;
4689 }
4690
4691 case SVGA_3D_CMD_READBACK_OTABLE:
4692 {
4693 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4694 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4695 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4696 break;
4697 }
4698
4699 case SVGA_3D_CMD_DEFINE_GB_MOB:
4700 {
4701 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4702 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4703 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4704 break;
4705 }
4706
4707 case SVGA_3D_CMD_DESTROY_GB_MOB:
4708 {
4709 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4710 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4711 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4712 break;
4713 }
4714
4715 case SVGA_3D_CMD_DEAD3:
4716 {
4717 VMSVGA_3D_CMD_NOTIMPL();
4718 break;
4719 }
4720
4721 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4722 {
4723 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4724 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4725 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4726 break;
4727 }
4728
4729 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4730 {
4731 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4732 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4733 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4734 break;
4735 }
4736
4737 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4738 {
4739 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4740 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4741 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4742 break;
4743 }
4744
4745 case SVGA_3D_CMD_BIND_GB_SURFACE:
4746 {
4747 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4748 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4749 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4750 break;
4751 }
4752
4753 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4754 {
4755 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4756 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4757 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4758 break;
4759 }
4760
4761 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4762 {
4763 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4764 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4765 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4766 break;
4767 }
4768
4769 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4770 {
4771 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4772 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4773 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4774 break;
4775 }
4776
4777 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4778 {
4779 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4780 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4781 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4782 break;
4783 }
4784
4785 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4786 {
4787 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4788 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4789 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4790 break;
4791 }
4792
4793 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4794 {
4795 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4796 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4797 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4798 break;
4799 }
4800
4801 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4802 {
4803 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4804 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4805 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4806 break;
4807 }
4808
4809 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4810 {
4811 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4812 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4813 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4814 break;
4815 }
4816
4817 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4818 {
4819 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4820 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4821 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4822 break;
4823 }
4824
4825 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4826 {
4827 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4828 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4829 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4830 break;
4831 }
4832
4833 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4834 {
4835 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4836 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4837 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4838 break;
4839 }
4840
4841 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4842 {
4843 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4844 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4845 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4846 break;
4847 }
4848
4849 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4850 {
4851 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4852 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4853 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4854 break;
4855 }
4856
4857 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4858 {
4859 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4860 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4861 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4862 break;
4863 }
4864
4865 case SVGA_3D_CMD_BIND_GB_SHADER:
4866 {
4867 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4868 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4869 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4870 break;
4871 }
4872
4873 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4874 {
4875 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4876 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4877 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4878 break;
4879 }
4880
4881 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4882 {
4883 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4884 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4885 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4886 break;
4887 }
4888
4889 case SVGA_3D_CMD_END_GB_QUERY:
4890 {
4891 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4892 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4893 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4894 break;
4895 }
4896
4897 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4898 {
4899 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4900 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4901 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4902 break;
4903 }
4904
4905 case SVGA_3D_CMD_NOP:
4906 {
4907 /* Apparently there is nothing to do. */
4908 break;
4909 }
4910
4911 case SVGA_3D_CMD_ENABLE_GART:
4912 {
4913 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4915 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4916 break;
4917 }
4918
4919 case SVGA_3D_CMD_DISABLE_GART:
4920 {
4921 /* No corresponding SVGA3dCmd structure. */
4922 VMSVGA_3D_CMD_NOTIMPL();
4923 break;
4924 }
4925
4926 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4927 {
4928 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4929 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4930 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4931 break;
4932 }
4933
4934 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4935 {
4936 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4937 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4938 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4939 break;
4940 }
4941
4942 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4943 {
4944 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4945 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4946 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4947 break;
4948 }
4949
4950 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4951 {
4952 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4954 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4955 break;
4956 }
4957
4958 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4959 {
4960 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4961 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4962 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4963 break;
4964 }
4965
4966 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4967 {
4968 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4969 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4970 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4971 break;
4972 }
4973
4974 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4975 {
4976 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4977 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4978 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4979 break;
4980 }
4981
4982 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4983 {
4984 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4985 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4986 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4987 break;
4988 }
4989
4990 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4991 {
4992 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4993 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4994 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4995 break;
4996 }
4997
4998 case SVGA_3D_CMD_GB_SCREEN_DMA:
4999 {
5000 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
5001 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5002 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5003 break;
5004 }
5005
5006 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
5007 {
5008 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
5009 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5010 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5011 break;
5012 }
5013
5014 case SVGA_3D_CMD_GB_MOB_FENCE:
5015 {
5016 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
5017 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5018 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5019 break;
5020 }
5021
5022 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
5023 {
5024 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
5025 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5026 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
5027 break;
5028 }
5029
5030 case SVGA_3D_CMD_DEFINE_GB_MOB64:
5031 {
5032 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
5033 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5034 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
5035 break;
5036 }
5037
5038 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
5039 {
5040 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
5041 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5042 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5043 break;
5044 }
5045
5046 case SVGA_3D_CMD_NOP_ERROR:
5047 {
5048 /* Apparently there is nothing to do. */
5049 break;
5050 }
5051
5052 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
5053 {
5054 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
5055 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5056 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5057 break;
5058 }
5059
5060 case SVGA_3D_CMD_SET_VERTEX_DECLS:
5061 {
5062 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
5063 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5064 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5065 break;
5066 }
5067
5068 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
5069 {
5070 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
5071 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5072 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5073 break;
5074 }
5075
5076 case SVGA_3D_CMD_DRAW:
5077 {
5078 /* No corresponding SVGA3dCmd structure. */
5079 VMSVGA_3D_CMD_NOTIMPL();
5080 break;
5081 }
5082
5083 case SVGA_3D_CMD_DRAW_INDEXED:
5084 {
5085 /* No corresponding SVGA3dCmd structure. */
5086 VMSVGA_3D_CMD_NOTIMPL();
5087 break;
5088 }
5089
5090 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
5091 {
5092 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
5093 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5094 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
5095 break;
5096 }
5097
5098 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
5099 {
5100 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
5101 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5102 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5103 break;
5104 }
5105
5106 case SVGA_3D_CMD_DX_BIND_CONTEXT:
5107 {
5108 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
5109 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5110 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5111 break;
5112 }
5113
5114 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5115 {
5116 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5117 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5118 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5119 break;
5120 }
5121
5122 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5123 {
5124 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5125 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5126 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5127 break;
5128 }
5129
5130 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5131 {
5132 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5133 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5134 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5135 break;
5136 }
5137
5138 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5139 {
5140 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5141 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5142 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5143 break;
5144 }
5145
5146 case SVGA_3D_CMD_DX_SET_SHADER:
5147 {
5148 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5149 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5150 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5151 break;
5152 }
5153
5154 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5155 {
5156 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5157 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5158 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5159 break;
5160 }
5161
5162 case SVGA_3D_CMD_DX_DRAW:
5163 {
5164 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5165 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5166 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5167 break;
5168 }
5169
5170 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5171 {
5172 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5173 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5174 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5175 break;
5176 }
5177
5178 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5179 {
5180 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5181 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5182 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5183 break;
5184 }
5185
5186 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5187 {
5188 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5189 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5190 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5191 break;
5192 }
5193
5194 case SVGA_3D_CMD_DX_DRAW_AUTO:
5195 {
5196 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5197 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5198 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5199 break;
5200 }
5201
5202 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5203 {
5204 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5205 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5206 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5207 break;
5208 }
5209
5210 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5211 {
5212 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5213 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5214 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5215 break;
5216 }
5217
5218 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5219 {
5220 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5221 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5222 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5223 break;
5224 }
5225
5226 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5227 {
5228 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5229 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5230 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5231 break;
5232 }
5233
5234 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5235 {
5236 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5237 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5238 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5239 break;
5240 }
5241
5242 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5243 {
5244 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5245 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5246 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5247 break;
5248 }
5249
5250 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5251 {
5252 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5253 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5254 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5255 break;
5256 }
5257
5258 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5259 {
5260 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5261 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5262 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5263 break;
5264 }
5265
5266 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5267 {
5268 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5269 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5270 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5271 break;
5272 }
5273
5274 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5275 {
5276 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5277 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5278 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5279 break;
5280 }
5281
5282 case SVGA_3D_CMD_DX_BIND_QUERY:
5283 {
5284 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5285 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5286 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5287 break;
5288 }
5289
5290 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5291 {
5292 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5293 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5294 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5295 break;
5296 }
5297
5298 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5299 {
5300 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5301 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5302 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5303 break;
5304 }
5305
5306 case SVGA_3D_CMD_DX_END_QUERY:
5307 {
5308 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5309 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5310 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5311 break;
5312 }
5313
5314 case SVGA_3D_CMD_DX_READBACK_QUERY:
5315 {
5316 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5317 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5318 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5319 break;
5320 }
5321
5322 case SVGA_3D_CMD_DX_SET_PREDICATION:
5323 {
5324 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5325 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5326 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5327 break;
5328 }
5329
5330 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5331 {
5332 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5333 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5334 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5335 break;
5336 }
5337
5338 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5339 {
5340 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5341 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5342 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5343 break;
5344 }
5345
5346 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5347 {
5348 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5349 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5350 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5351 break;
5352 }
5353
5354 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5355 {
5356 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5357 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5358 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5359 break;
5360 }
5361
5362 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5363 {
5364 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5365 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5366 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5367 break;
5368 }
5369
5370 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5371 {
5372 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5373 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5374 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5375 break;
5376 }
5377
5378 case SVGA_3D_CMD_DX_PRED_COPY:
5379 {
5380 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5381 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5382 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5383 break;
5384 }
5385
5386 case SVGA_3D_CMD_DX_PRESENTBLT:
5387 {
5388 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5389 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5390 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5391 break;
5392 }
5393
5394 case SVGA_3D_CMD_DX_GENMIPS:
5395 {
5396 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5397 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5398 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5399 break;
5400 }
5401
5402 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5403 {
5404 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5405 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5406 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5407 break;
5408 }
5409
5410 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5411 {
5412 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5413 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5414 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5415 break;
5416 }
5417
5418 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5419 {
5420 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5421 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5422 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5423 break;
5424 }
5425
5426 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5427 {
5428 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5429 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5430 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5431 break;
5432 }
5433
5434 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5435 {
5436 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5437 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5438 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5439 break;
5440 }
5441
5442 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5443 {
5444 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5445 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5446 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5447 break;
5448 }
5449
5450 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5451 {
5452 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5453 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5454 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5455 break;
5456 }
5457
5458 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5459 {
5460 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5461 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5462 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5463 break;
5464 }
5465
5466 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5467 {
5468 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5469 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5470 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5471 break;
5472 }
5473
5474 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5475 {
5476 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5477 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5478 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5479 break;
5480 }
5481
5482 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5483 {
5484 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5485 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5486 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5487 break;
5488 }
5489
5490 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5491 {
5492 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5493 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5494 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5495 break;
5496 }
5497
5498 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5499 {
5500 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5501 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5502 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5503 break;
5504 }
5505
5506 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5507 {
5508 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5509 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5510 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5511 break;
5512 }
5513
5514 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5515 {
5516 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5517 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5518 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5519 break;
5520 }
5521
5522 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5523 {
5524 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5525 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5526 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5527 break;
5528 }
5529
5530 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5531 {
5532 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5533 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5534 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5535 break;
5536 }
5537
5538 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5539 {
5540 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5541 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5542 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5543 break;
5544 }
5545
5546 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5547 {
5548 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5549 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5550 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5551 break;
5552 }
5553
5554 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5555 {
5556 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5557 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5558 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5559 break;
5560 }
5561
5562 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5563 {
5564 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5565 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5566 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5567 break;
5568 }
5569
5570 case SVGA_3D_CMD_DX_BIND_SHADER:
5571 {
5572 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5573 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5574 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5575 break;
5576 }
5577
5578 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5579 {
5580 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5581 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5582 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5583 break;
5584 }
5585
5586 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5587 {
5588 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5589 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5590 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5591 break;
5592 }
5593
5594 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5595 {
5596 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5597 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5598 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5599 break;
5600 }
5601
5602 case SVGA_3D_CMD_DX_SET_COTABLE:
5603 {
5604 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5605 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5606 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5607 break;
5608 }
5609
5610 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5611 {
5612 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5613 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5614 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5615 break;
5616 }
5617
5618 case SVGA_3D_CMD_DX_BUFFER_COPY:
5619 {
5620 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5621 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5622 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5623 break;
5624 }
5625
5626 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5627 {
5628 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5629 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5630 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5631 break;
5632 }
5633
5634 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5635 {
5636 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5637 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5638 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5639 break;
5640 }
5641
5642 case SVGA_3D_CMD_DX_MOVE_QUERY:
5643 {
5644 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5645 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5646 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5647 break;
5648 }
5649
5650 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5651 {
5652 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5653 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5654 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5655 break;
5656 }
5657
5658 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5659 {
5660 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5661 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5662 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5663 break;
5664 }
5665
5666 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5667 {
5668 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5669 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5670 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5671 break;
5672 }
5673
5674 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5675 {
5676 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5677 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5678 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, pCmd, cbCmd);
5679 break;
5680 }
5681
5682 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5683 {
5684 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5685 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5686 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5687 break;
5688 }
5689
5690 case SVGA_3D_CMD_DX_HINT:
5691 {
5692 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5693 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5694 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5695 break;
5696 }
5697
5698 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5699 {
5700 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5701 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5702 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5703 break;
5704 }
5705
5706 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5707 {
5708 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5709 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5710 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5711 break;
5712 }
5713
5714 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5715 {
5716 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5717 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5718 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5719 break;
5720 }
5721
5722 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5723 {
5724 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5725 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5726 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5727 break;
5728 }
5729
5730 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5731 {
5732 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5733 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5734 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5735 break;
5736 }
5737
5738 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5739 {
5740 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5741 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5742 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5743 break;
5744 }
5745
5746 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5747 {
5748 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5749 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5750 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5751 break;
5752 }
5753
5754 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5755 {
5756 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5757 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5758 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5759 break;
5760 }
5761
5762 case SVGA_3D_CMD_SCREEN_COPY:
5763 {
5764 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5765 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5766 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5767 break;
5768 }
5769
5770 case SVGA_3D_CMD_RESERVED1:
5771 {
5772 VMSVGA_3D_CMD_NOTIMPL();
5773 break;
5774 }
5775
5776 case SVGA_3D_CMD_RESERVED2:
5777 {
5778 VMSVGA_3D_CMD_NOTIMPL();
5779 break;
5780 }
5781
5782 case SVGA_3D_CMD_RESERVED3:
5783 {
5784 VMSVGA_3D_CMD_NOTIMPL();
5785 break;
5786 }
5787
5788 case SVGA_3D_CMD_RESERVED4:
5789 {
5790 VMSVGA_3D_CMD_NOTIMPL();
5791 break;
5792 }
5793
5794 case SVGA_3D_CMD_RESERVED5:
5795 {
5796 VMSVGA_3D_CMD_NOTIMPL();
5797 break;
5798 }
5799
5800 case SVGA_3D_CMD_RESERVED6:
5801 {
5802 VMSVGA_3D_CMD_NOTIMPL();
5803 break;
5804 }
5805
5806 case SVGA_3D_CMD_RESERVED7:
5807 {
5808 VMSVGA_3D_CMD_NOTIMPL();
5809 break;
5810 }
5811
5812 case SVGA_3D_CMD_RESERVED8:
5813 {
5814 VMSVGA_3D_CMD_NOTIMPL();
5815 break;
5816 }
5817
5818 case SVGA_3D_CMD_GROW_OTABLE:
5819 {
5820 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5821 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5822 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5823 break;
5824 }
5825
5826 case SVGA_3D_CMD_DX_GROW_COTABLE:
5827 {
5828 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5829 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5830 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5831 break;
5832 }
5833
5834 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5835 {
5836 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5837 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5838 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5839 break;
5840 }
5841
5842 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5843 {
5844 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5845 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5846 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd);
5847 break;
5848 }
5849
5850 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5851 {
5852 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5853 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5854 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5855 break;
5856 }
5857
5858 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5859 {
5860 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5861 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5862 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5863 break;
5864 }
5865
5866 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5867 {
5868 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5869 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5870 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5871 break;
5872 }
5873
5874 case SVGA_3D_CMD_DX_PRED_CONVERT:
5875 {
5876 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5877 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5878 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5879 break;
5880 }
5881
5882 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5883 {
5884 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5885 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5886 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5887 break;
5888 }
5889
5890 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5891 {
5892 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5893 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5894 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5895 break;
5896 }
5897
5898 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5899 {
5900 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5901 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5902 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5903 break;
5904 }
5905
5906 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5907 {
5908 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5909 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5910 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5911 break;
5912 }
5913
5914 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5915 {
5916 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5917 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5918 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5919 break;
5920 }
5921
5922 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5923 {
5924 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5925 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5926 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5927 break;
5928 }
5929
5930 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5931 {
5932 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5933 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5934 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5935 break;
5936 }
5937
5938 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5939 {
5940 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5941 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5942 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5943 break;
5944 }
5945
5946 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5947 {
5948 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5949 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5950 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5951 break;
5952 }
5953
5954 case SVGA_3D_CMD_DX_DISPATCH:
5955 {
5956 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5957 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5958 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5959 break;
5960 }
5961
5962 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5963 {
5964 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5965 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5966 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5967 break;
5968 }
5969
5970 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5971 {
5972 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5973 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5974 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5975 break;
5976 }
5977
5978 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5979 {
5980 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5981 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5982 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5983 break;
5984 }
5985
5986 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5987 {
5988 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5989 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5990 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5991 break;
5992 }
5993
5994 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5995 {
5996 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5997 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5998 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5999 break;
6000 }
6001
6002 case SVGA_3D_CMD_LOGICOPS_BITBLT:
6003 {
6004 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
6005 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6006 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
6007 break;
6008 }
6009
6010 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
6011 {
6012 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
6013 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6014 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
6015 break;
6016 }
6017
6018 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
6019 {
6020 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
6021 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6022 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
6023 break;
6024 }
6025
6026 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
6027 {
6028 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
6029 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6030 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
6031 break;
6032 }
6033
6034 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
6035 {
6036 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
6037 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6038 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
6039 break;
6040 }
6041
6042 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
6043 {
6044 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
6045 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6046 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
6047 break;
6048 }
6049
6050 case SVGA_3D_CMD_RESERVED2_1:
6051 {
6052 VMSVGA_3D_CMD_NOTIMPL();
6053 break;
6054 }
6055
6056 case SVGA_3D_CMD_RESERVED2_2:
6057 {
6058 VMSVGA_3D_CMD_NOTIMPL();
6059 break;
6060 }
6061
6062 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
6063 {
6064 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
6065 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6066 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd);
6067 break;
6068 }
6069
6070 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
6071 {
6072 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
6073 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6074 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
6075 break;
6076 }
6077
6078 case SVGA_3D_CMD_DX_SET_MIN_LOD:
6079 {
6080 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
6081 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6082 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
6083 break;
6084 }
6085
6086 case SVGA_3D_CMD_RESERVED2_3:
6087 {
6088 VMSVGA_3D_CMD_NOTIMPL();
6089 break;
6090 }
6091
6092 case SVGA_3D_CMD_RESERVED2_4:
6093 {
6094 VMSVGA_3D_CMD_NOTIMPL();
6095 break;
6096 }
6097
6098 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
6099 {
6100 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
6101 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6102 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6103 break;
6104 }
6105
6106 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6107 {
6108 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
6109 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6110 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6111 break;
6112 }
6113
6114 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6115 {
6116 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6117 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6118 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6119 break;
6120 }
6121
6122 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6123 {
6124 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6125 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6126 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6127 break;
6128 }
6129
6130 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6131 {
6132 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6133 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6134 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6135 break;
6136 }
6137
6138 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6139 {
6140 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6141 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6142 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6143 break;
6144 }
6145
6146 /* Unsupported commands. */
6147 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6148 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6149 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6150 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6151 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6152 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6153 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6154 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6155 /* Prevent the compiler warning. */
6156 case SVGA_3D_CMD_LEGACY_BASE:
6157 case SVGA_3D_CMD_MAX:
6158 case SVGA_3D_CMD_FUTURE_MAX:
6159 /* No 'default' case */
6160 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6161 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6162 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6163 rcParse = VERR_NOT_IMPLEMENTED;
6164 break;
6165 }
6166
6167 return VINF_SUCCESS;
6168// return rcParse;
6169}
6170# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6171#endif /* VBOX_WITH_VMSVGA3D */
6172
6173
6174/*
6175 *
6176 * Handlers for FIFO commands.
6177 *
6178 * Every handler takes the following parameters:
6179 *
6180 * pThis The shared VGA/VMSVGA state.
6181 * pThisCC The VGA/VMSVGA state for ring-3.
6182 * pCmd The command data.
6183 */
6184
6185
6186/* SVGA_CMD_UPDATE */
6187void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6188{
6189 RT_NOREF(pThis);
6190 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6191
6192 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6193 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6194
6195 /** @todo Multiple screens? */
6196 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6197 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6198 return;
6199
6200 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6201}
6202
6203
6204/* SVGA_CMD_UPDATE_VERBOSE */
6205void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6206{
6207 RT_NOREF(pThis);
6208 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6209
6210 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6211 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6212
6213 /** @todo Multiple screens? */
6214 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6215 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6216 return;
6217
6218 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6219}
6220
6221
6222/* SVGA_CMD_RECT_FILL */
6223void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6224{
6225 RT_NOREF(pThis, pCmd);
6226 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6227
6228 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6229 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6230 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6231}
6232
6233
6234/* SVGA_CMD_RECT_COPY */
6235void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6236{
6237 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6238
6239 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6240 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6241
6242 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6243 AssertPtrReturnVoid(pScreen);
6244
6245 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6246 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6247 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6248 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6249 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6250 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6251 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6252
6253 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6254 pCmd->width, pCmd->height, pThis->vram_size);
6255 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6256}
6257
6258
6259/* SVGA_CMD_RECT_ROP_COPY */
6260void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6261{
6262 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6263
6264 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6265 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6266
6267 if (pCmd->rop != SVGA_ROP_COPY)
6268 {
6269 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6270 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6271 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6272 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6273 */
6274 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6275 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6276 return;
6277 }
6278
6279 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6280 AssertPtrReturnVoid(pScreen);
6281
6282 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6283 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6284 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6285 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6286 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6287 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6288 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6289
6290 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6291 pCmd->width, pCmd->height, pThis->vram_size);
6292 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6293}
6294
6295
6296/* SVGA_CMD_DISPLAY_CURSOR */
6297void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6298{
6299 RT_NOREF(pThis, pCmd);
6300 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6301
6302 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6303 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6304 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6305}
6306
6307
6308/* SVGA_CMD_MOVE_CURSOR */
6309void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6310{
6311 RT_NOREF(pThis, pCmd);
6312 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6313
6314 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6315 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6316 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6317}
6318
6319
6320/* SVGA_CMD_DEFINE_CURSOR */
6321void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6322{
6323 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6324
6325 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6326 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6327 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6328
6329 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6330 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6331 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6332 RT_UNTRUSTED_VALIDATED_FENCE();
6333
6334 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6335 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6336 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6337
6338 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6339 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6340
6341 uint32_t const cx = pCmd->width;
6342 uint32_t const cy = pCmd->height;
6343
6344 /*
6345 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6346 * The AND data uses 8-bit aligned scanlines.
6347 * The XOR data must be starting on a 32-bit boundrary.
6348 */
6349 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6350 uint32_t cbDstAndMask = cbDstAndLine * cy;
6351 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6352 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6353
6354 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6355 AssertReturnVoid(pbCopy);
6356
6357 /* Convert the AND mask. */
6358 uint8_t *pbDst = pbCopy;
6359 uint8_t const *pbSrc = pbSrcAndMask;
6360 switch (pCmd->andMaskDepth)
6361 {
6362 case 1:
6363 if (cbSrcAndLine == cbDstAndLine)
6364 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6365 else
6366 {
6367 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6368 for (uint32_t y = 0; y < cy; y++)
6369 {
6370 memcpy(pbDst, pbSrc, cbDstAndLine);
6371 pbDst += cbDstAndLine;
6372 pbSrc += cbSrcAndLine;
6373 }
6374 }
6375 break;
6376 /* Should take the XOR mask into account for the multi-bit AND mask. */
6377 case 8:
6378 for (uint32_t y = 0; y < cy; y++)
6379 {
6380 for (uint32_t x = 0; x < cx; )
6381 {
6382 uint8_t bDst = 0;
6383 uint8_t fBit = 0x80;
6384 do
6385 {
6386 uintptr_t const idxPal = pbSrc[x] * 3;
6387 if ((( pThis->last_palette[idxPal]
6388 | (pThis->last_palette[idxPal] >> 8)
6389 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6390 bDst |= fBit;
6391 fBit >>= 1;
6392 x++;
6393 } while (x < cx && (x & 7));
6394 pbDst[(x - 1) / 8] = bDst;
6395 }
6396 pbDst += cbDstAndLine;
6397 pbSrc += cbSrcAndLine;
6398 }
6399 break;
6400 case 15:
6401 for (uint32_t y = 0; y < cy; y++)
6402 {
6403 for (uint32_t x = 0; x < cx; )
6404 {
6405 uint8_t bDst = 0;
6406 uint8_t fBit = 0x80;
6407 do
6408 {
6409 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6410 bDst |= fBit;
6411 fBit >>= 1;
6412 x++;
6413 } while (x < cx && (x & 7));
6414 pbDst[(x - 1) / 8] = bDst;
6415 }
6416 pbDst += cbDstAndLine;
6417 pbSrc += cbSrcAndLine;
6418 }
6419 break;
6420 case 16:
6421 for (uint32_t y = 0; y < cy; y++)
6422 {
6423 for (uint32_t x = 0; x < cx; )
6424 {
6425 uint8_t bDst = 0;
6426 uint8_t fBit = 0x80;
6427 do
6428 {
6429 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6430 bDst |= fBit;
6431 fBit >>= 1;
6432 x++;
6433 } while (x < cx && (x & 7));
6434 pbDst[(x - 1) / 8] = bDst;
6435 }
6436 pbDst += cbDstAndLine;
6437 pbSrc += cbSrcAndLine;
6438 }
6439 break;
6440 case 24:
6441 for (uint32_t y = 0; y < cy; y++)
6442 {
6443 for (uint32_t x = 0; x < cx; )
6444 {
6445 uint8_t bDst = 0;
6446 uint8_t fBit = 0x80;
6447 do
6448 {
6449 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6450 bDst |= fBit;
6451 fBit >>= 1;
6452 x++;
6453 } while (x < cx && (x & 7));
6454 pbDst[(x - 1) / 8] = bDst;
6455 }
6456 pbDst += cbDstAndLine;
6457 pbSrc += cbSrcAndLine;
6458 }
6459 break;
6460 case 32:
6461 for (uint32_t y = 0; y < cy; y++)
6462 {
6463 for (uint32_t x = 0; x < cx; )
6464 {
6465 uint8_t bDst = 0;
6466 uint8_t fBit = 0x80;
6467 do
6468 {
6469 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6470 bDst |= fBit;
6471 fBit >>= 1;
6472 x++;
6473 } while (x < cx && (x & 7));
6474 pbDst[(x - 1) / 8] = bDst;
6475 }
6476 pbDst += cbDstAndLine;
6477 pbSrc += cbSrcAndLine;
6478 }
6479 break;
6480 default:
6481 RTMemFreeZ(pbCopy, cbCopy);
6482 AssertFailedReturnVoid();
6483 }
6484
6485 /* Convert the XOR mask. */
6486 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6487 pbSrc = pbSrcXorMask;
6488 switch (pCmd->xorMaskDepth)
6489 {
6490 case 1:
6491 for (uint32_t y = 0; y < cy; y++)
6492 {
6493 for (uint32_t x = 0; x < cx; )
6494 {
6495 /* most significant bit is the left most one. */
6496 uint8_t bSrc = pbSrc[x / 8];
6497 do
6498 {
6499 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6500 bSrc <<= 1;
6501 x++;
6502 } while ((x & 7) && x < cx);
6503 }
6504 pbSrc += cbSrcXorLine;
6505 }
6506 break;
6507 case 8:
6508 for (uint32_t y = 0; y < cy; y++)
6509 {
6510 for (uint32_t x = 0; x < cx; x++)
6511 {
6512 uint32_t u = pThis->last_palette[pbSrc[x]];
6513 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6514 }
6515 pbSrc += cbSrcXorLine;
6516 }
6517 break;
6518 case 15: /* Src: RGB-5-5-5 */
6519 for (uint32_t y = 0; y < cy; y++)
6520 {
6521 for (uint32_t x = 0; x < cx; x++)
6522 {
6523 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6524 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6525 ((uValue >> 5) & 0x1f) << 3,
6526 ((uValue >> 10) & 0x1f) << 3, 0);
6527 }
6528 pbSrc += cbSrcXorLine;
6529 }
6530 break;
6531 case 16: /* Src: RGB-5-6-5 */
6532 for (uint32_t y = 0; y < cy; y++)
6533 {
6534 for (uint32_t x = 0; x < cx; x++)
6535 {
6536 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6537 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6538 ((uValue >> 5) & 0x3f) << 2,
6539 ((uValue >> 11) & 0x1f) << 3, 0);
6540 }
6541 pbSrc += cbSrcXorLine;
6542 }
6543 break;
6544 case 24:
6545 for (uint32_t y = 0; y < cy; y++)
6546 {
6547 for (uint32_t x = 0; x < cx; x++)
6548 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6549 pbSrc += cbSrcXorLine;
6550 }
6551 break;
6552 case 32:
6553 for (uint32_t y = 0; y < cy; y++)
6554 {
6555 for (uint32_t x = 0; x < cx; x++)
6556 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6557 pbSrc += cbSrcXorLine;
6558 }
6559 break;
6560 default:
6561 RTMemFreeZ(pbCopy, cbCopy);
6562 AssertFailedReturnVoid();
6563 }
6564
6565 /*
6566 * Pass it to the frontend/whatever.
6567 */
6568 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6569 cx, cy, pbCopy, cbCopy);
6570}
6571
6572
6573/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6574void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6575{
6576 RT_NOREF(pThis);
6577 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6578
6579 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6580 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6581
6582 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6583 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6584 RT_UNTRUSTED_VALIDATED_FENCE();
6585
6586 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6587 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6588 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6589 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6590 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6591
6592 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6593 AssertPtrReturnVoid(pCursorCopy);
6594
6595 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6596 memset(pCursorCopy, 0xff, cbAndMask);
6597 /* Colour data */
6598 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6599
6600 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6601 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6602}
6603
6604
6605/* SVGA_CMD_ESCAPE */
6606void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6607{
6608 RT_NOREF(pThis);
6609 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6610
6611 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6612
6613 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6614 {
6615 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6616 RT_UNTRUSTED_VALIDATED_FENCE();
6617
6618 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6619 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6620
6621 switch (cmd)
6622 {
6623 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6624 {
6625 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6626 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6627 RT_UNTRUSTED_VALIDATED_FENCE();
6628
6629 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6630
6631 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6632 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6633 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6634 RT_NOREF_PV(pVideoCmd);
6635 break;
6636 }
6637
6638 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6639 {
6640 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6641 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6642 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6643 RT_NOREF_PV(pVideoCmd);
6644 break;
6645 }
6646
6647 default:
6648 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6649 break;
6650 }
6651 }
6652 else
6653 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6654}
6655
6656
6657/* SVGA_CMD_DEFINE_SCREEN */
6658void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6659{
6660 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6661
6662 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6663 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6664 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6665 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6666
6667 uint32_t const idScreen = pCmd->screen.id;
6668 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6669
6670 uint32_t const uWidth = pCmd->screen.size.width;
6671 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6672
6673 uint32_t const uHeight = pCmd->screen.size.height;
6674 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6675
6676 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6677 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6678 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6679
6680 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6681 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6682
6683 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6684 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6685 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6686 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6687 RT_UNTRUSTED_VALIDATED_FENCE();
6688
6689 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6690 pScreen->fDefined = true;
6691 pScreen->fModified = true;
6692 pScreen->fuScreen = pCmd->screen.flags;
6693 pScreen->idScreen = idScreen;
6694 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6695 {
6696 /* Not blanked. */
6697 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6698 RT_UNTRUSTED_VALIDATED_FENCE();
6699
6700 pScreen->xOrigin = pCmd->screen.root.x;
6701 pScreen->yOrigin = pCmd->screen.root.y;
6702 pScreen->cWidth = uWidth;
6703 pScreen->cHeight = uHeight;
6704 pScreen->offVRAM = uScreenOffset;
6705 pScreen->cbPitch = cbPitch;
6706 pScreen->cBpp = 32;
6707 }
6708 else
6709 {
6710 /* Screen blanked. Keep old values. */
6711 }
6712
6713 pThis->svga.fGFBRegisters = false;
6714 vmsvgaR3ChangeMode(pThis, pThisCC);
6715
6716#ifdef VBOX_WITH_VMSVGA3D
6717 if (RT_LIKELY(pThis->svga.f3DEnabled))
6718 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6719#endif
6720}
6721
6722
6723/* SVGA_CMD_DESTROY_SCREEN */
6724void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6725{
6726 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6727
6728 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6729 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6730
6731 uint32_t const idScreen = pCmd->screenId;
6732 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6733 RT_UNTRUSTED_VALIDATED_FENCE();
6734
6735 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6736 pScreen->fModified = true;
6737 pScreen->fDefined = false;
6738 pScreen->idScreen = idScreen;
6739
6740#ifdef VBOX_WITH_VMSVGA3D
6741 if (RT_LIKELY(pThis->svga.f3DEnabled))
6742 vmsvga3dDestroyScreen(pThisCC, pScreen);
6743#endif
6744 vmsvgaR3ChangeMode(pThis, pThisCC);
6745}
6746
6747
6748/* SVGA_CMD_DEFINE_GMRFB */
6749void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6750{
6751 RT_NOREF(pThis);
6752 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6753
6754 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6755 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6756 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6757
6758 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6759 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6760 pSvgaR3State->GMRFB.format = pCmd->format;
6761}
6762
6763
6764/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6765void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6766{
6767 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6768
6769 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6770 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6771 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6772
6773 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6774 RT_UNTRUSTED_VALIDATED_FENCE();
6775
6776 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6777 AssertPtrReturnVoid(pScreen);
6778
6779 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6780 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6781
6782 /* Clip destRect to the screen dimensions. */
6783 SVGASignedRect screenRect;
6784 screenRect.left = 0;
6785 screenRect.top = 0;
6786 screenRect.right = pScreen->cWidth;
6787 screenRect.bottom = pScreen->cHeight;
6788 SVGASignedRect clipRect = pCmd->destRect;
6789 vmsvgaR3ClipRect(&screenRect, &clipRect);
6790 RT_UNTRUSTED_VALIDATED_FENCE();
6791
6792 uint32_t const width = clipRect.right - clipRect.left;
6793 uint32_t const height = clipRect.bottom - clipRect.top;
6794
6795 if ( width == 0
6796 || height == 0)
6797 return; /* Nothing to do. */
6798
6799 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6800 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6801
6802 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6803 * Prepare parameters for vmsvgaR3GmrTransfer.
6804 */
6805 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6806
6807 /* Destination: host buffer which describes the screen 0 VRAM.
6808 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6809 */
6810 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6811 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6812 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6813 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6814 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6815 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6816 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6817 + cbScanline * clipRect.top;
6818 int32_t const cbHstPitch = cbScanline;
6819
6820 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6821 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6822 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6823 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6824 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6825
6826 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6827 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6828 gstPtr, offGst, cbGstPitch,
6829 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6830 AssertRC(rc);
6831 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6832}
6833
6834
6835/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6836void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6837{
6838 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6839
6840 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6841 /* Note! This can fetch 3d render results as well!! */
6842 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6843 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6844
6845 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6846 RT_UNTRUSTED_VALIDATED_FENCE();
6847
6848 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6849 AssertPtrReturnVoid(pScreen);
6850
6851 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6852 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6853
6854 /* Clip destRect to the screen dimensions. */
6855 SVGASignedRect screenRect;
6856 screenRect.left = 0;
6857 screenRect.top = 0;
6858 screenRect.right = pScreen->cWidth;
6859 screenRect.bottom = pScreen->cHeight;
6860 SVGASignedRect clipRect = pCmd->srcRect;
6861 vmsvgaR3ClipRect(&screenRect, &clipRect);
6862 RT_UNTRUSTED_VALIDATED_FENCE();
6863
6864 uint32_t const width = clipRect.right - clipRect.left;
6865 uint32_t const height = clipRect.bottom - clipRect.top;
6866
6867 if ( width == 0
6868 || height == 0)
6869 return; /* Nothing to do. */
6870
6871 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6872 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6873
6874 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6875 * Prepare parameters for vmsvgaR3GmrTransfer.
6876 */
6877 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6878
6879 /* Source: host buffer which describes the screen 0 VRAM.
6880 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6881 */
6882 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6883 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6884 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6885 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6886 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6887 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6888 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6889 + cbScanline * clipRect.top;
6890 int32_t const cbHstPitch = cbScanline;
6891
6892 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6893 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6894 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6895 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6896 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6897
6898 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6899 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6900 gstPtr, offGst, cbGstPitch,
6901 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6902 AssertRC(rc);
6903}
6904
6905
6906/* SVGA_CMD_ANNOTATION_FILL */
6907void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6908{
6909 RT_NOREF(pThis);
6910 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6911
6912 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6913 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6914
6915 pSvgaR3State->colorAnnotation = pCmd->color;
6916}
6917
6918
6919/* SVGA_CMD_ANNOTATION_COPY */
6920void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6921{
6922 RT_NOREF(pThis, pCmd);
6923 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6924
6925 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6926 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6927
6928 AssertFailed();
6929}
6930
6931
6932#ifdef VBOX_WITH_VMSVGA3D
6933/* SVGA_CMD_DEFINE_GMR2 */
6934void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6935{
6936 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6937
6938 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6939 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6940
6941 /* Validate current GMR id. */
6942 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6943 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6944 RT_UNTRUSTED_VALIDATED_FENCE();
6945
6946 if (!pCmd->numPages)
6947 {
6948 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6949 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6950 }
6951 else
6952 {
6953 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6954 if (pGMR->cMaxPages)
6955 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6956
6957 /* Not sure if we should always free the descriptor, but for simplicity
6958 we do so if the new size is smaller than the current. */
6959 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6960 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6961 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6962
6963 pGMR->cMaxPages = pCmd->numPages;
6964 /* The rest is done by the REMAP_GMR2 command. */
6965 }
6966}
6967
6968
6969/* SVGA_CMD_REMAP_GMR2 */
6970void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6971{
6972 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6973
6974 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6975 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6976
6977 /* Validate current GMR id and size. */
6978 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6979 RT_UNTRUSTED_VALIDATED_FENCE();
6980 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6981 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6982 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6983 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6984
6985 if (pCmd->numPages == 0)
6986 return;
6987 RT_UNTRUSTED_VALIDATED_FENCE();
6988
6989 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6990 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6991
6992 /*
6993 * We flatten the existing descriptors into a page array, overwrite the
6994 * pages specified in this command and then recompress the descriptor.
6995 */
6996 /** @todo Optimize the GMR remap algorithm! */
6997
6998 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6999 uint64_t *paNewPage64 = NULL;
7000 if (pGMR->paDesc)
7001 {
7002 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
7003
7004 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
7005 AssertPtrReturnVoid(paNewPage64);
7006
7007 uint32_t idxPage = 0;
7008 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
7009 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
7010 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
7011 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
7012 RT_UNTRUSTED_VALIDATED_FENCE();
7013 }
7014
7015 /* Free the old GMR if present. */
7016 if (pGMR->paDesc)
7017 RTMemFree(pGMR->paDesc);
7018
7019 /* Allocate the maximum amount possible (everything non-continuous) */
7020 PVMSVGAGMRDESCRIPTOR paDescs;
7021 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
7022 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
7023
7024 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
7025 {
7026 /** @todo */
7027 AssertFailed();
7028 pGMR->numDescriptors = 0;
7029 }
7030 else
7031 {
7032 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
7033 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
7034 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
7035
7036 uint32_t cPages;
7037 if (paNewPage64)
7038 {
7039 /* Overwrite the old page array with the new page values. */
7040 if (fGCPhys64)
7041 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7042 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
7043 else
7044 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7045 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
7046
7047 /* Use the updated page array instead of the command data. */
7048 fGCPhys64 = true;
7049 paPages64 = paNewPage64;
7050 cPages = cNewTotalPages;
7051 }
7052 else
7053 cPages = pCmd->numPages;
7054
7055 /* The first page. */
7056 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
7057 * applied to paNewPage64. */
7058 RTGCPHYS GCPhys;
7059 if (fGCPhys64)
7060 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7061 else
7062 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
7063 paDescs[0].GCPhys = GCPhys;
7064 paDescs[0].numPages = 1;
7065
7066 /* Subsequent pages. */
7067 uint32_t iDescriptor = 0;
7068 for (uint32_t i = 1; i < cPages; i++)
7069 {
7070 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
7071 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7072 else
7073 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
7074
7075 /* Continuous physical memory? */
7076 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
7077 {
7078 Assert(paDescs[iDescriptor].numPages);
7079 paDescs[iDescriptor].numPages++;
7080 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
7081 }
7082 else
7083 {
7084 iDescriptor++;
7085 paDescs[iDescriptor].GCPhys = GCPhys;
7086 paDescs[iDescriptor].numPages = 1;
7087 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
7088 }
7089 }
7090
7091 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
7092 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
7093 pGMR->numDescriptors = iDescriptor + 1;
7094 }
7095
7096 if (paNewPage64)
7097 RTMemFree(paNewPage64);
7098}
7099
7100
7101/**
7102 * Free the specified GMR
7103 *
7104 * @param pThisCC The VGA/VMSVGA state for ring-3.
7105 * @param idGMR GMR id
7106 */
7107void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7108{
7109 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7110
7111 /* Free the old descriptor if present. */
7112 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7113 if ( pGMR->numDescriptors
7114 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7115 {
7116# ifdef DEBUG_GMR_ACCESS
7117 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7118# endif
7119
7120 Assert(pGMR->paDesc);
7121 RTMemFree(pGMR->paDesc);
7122 pGMR->paDesc = NULL;
7123 pGMR->numDescriptors = 0;
7124 pGMR->cbTotal = 0;
7125 pGMR->cMaxPages = 0;
7126 }
7127 Assert(!pGMR->cMaxPages);
7128 Assert(!pGMR->cbTotal);
7129}
7130#endif /* VBOX_WITH_VMSVGA3D */
7131
7132
7133/**
7134 * Copy between a GMR and a host memory buffer.
7135 *
7136 * @returns VBox status code.
7137 * @param pThis The shared VGA/VMSVGA instance data.
7138 * @param pThisCC The VGA/VMSVGA state for ring-3.
7139 * @param enmTransferType Transfer type (read/write)
7140 * @param pbHstBuf Host buffer pointer (valid)
7141 * @param cbHstBuf Size of host buffer (valid)
7142 * @param offHst Host buffer offset of the first scanline
7143 * @param cbHstPitch Destination buffer pitch
7144 * @param gstPtr GMR description
7145 * @param offGst Guest buffer offset of the first scanline
7146 * @param cbGstPitch Guest buffer pitch
7147 * @param cbWidth Width in bytes to copy
7148 * @param cHeight Number of scanllines to copy
7149 */
7150int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7151 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7152 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7153 uint32_t cbWidth, uint32_t cHeight)
7154{
7155 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7156 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7157 int rc;
7158
7159 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7160 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7161 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7162 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7163 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7164
7165 PGMR pGMR;
7166 uint32_t cbGmr; /* The GMR size in bytes. */
7167 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7168 {
7169 pGMR = NULL;
7170 cbGmr = pThis->vram_size;
7171 }
7172 else
7173 {
7174 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7175 RT_UNTRUSTED_VALIDATED_FENCE();
7176 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7177 cbGmr = pGMR->cbTotal;
7178 }
7179
7180 /*
7181 * GMR
7182 */
7183 /* Calculate GMR offset of the data to be copied. */
7184 AssertMsgReturn(gstPtr.offset < cbGmr,
7185 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7186 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7187 VERR_INVALID_PARAMETER);
7188 RT_UNTRUSTED_VALIDATED_FENCE();
7189 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7190 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7191 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7192 VERR_INVALID_PARAMETER);
7193 RT_UNTRUSTED_VALIDATED_FENCE();
7194 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7195
7196 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7197 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7198 AssertMsgReturn(cbGmrScanline != 0,
7199 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7200 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7201 VERR_INVALID_PARAMETER);
7202 RT_UNTRUSTED_VALIDATED_FENCE();
7203 AssertMsgReturn(cbWidth <= cbGmrScanline,
7204 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7205 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7206 VERR_INVALID_PARAMETER);
7207 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7208 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7209 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7210 VERR_INVALID_PARAMETER);
7211 RT_UNTRUSTED_VALIDATED_FENCE();
7212
7213 /* How many bytes are available for the data in the GMR. */
7214 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7215
7216 /* How many scanlines would fit into the available data. */
7217 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7218 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7219 if (cbWidth <= cbGmrLastScanline)
7220 ++cGmrScanlines;
7221
7222 if (cHeight > cGmrScanlines)
7223 cHeight = cGmrScanlines;
7224
7225 AssertMsgReturn(cHeight > 0,
7226 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7227 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7228 VERR_INVALID_PARAMETER);
7229 RT_UNTRUSTED_VALIDATED_FENCE();
7230
7231 /*
7232 * Host buffer.
7233 */
7234 AssertMsgReturn(offHst < cbHstBuf,
7235 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7236 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7237 VERR_INVALID_PARAMETER);
7238
7239 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7240 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7241 AssertMsgReturn(cbHstScanline != 0,
7242 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7243 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7244 VERR_INVALID_PARAMETER);
7245 AssertMsgReturn(cbWidth <= cbHstScanline,
7246 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7247 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7248 VERR_INVALID_PARAMETER);
7249 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7250 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7251 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7252 VERR_INVALID_PARAMETER);
7253
7254 /* How many bytes are available for the data in the buffer. */
7255 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7256
7257 /* How many scanlines would fit into the available data. */
7258 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7259 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7260 if (cbWidth <= cbHstLastScanline)
7261 ++cHstScanlines;
7262
7263 if (cHeight > cHstScanlines)
7264 cHeight = cHstScanlines;
7265
7266 AssertMsgReturn(cHeight > 0,
7267 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7268 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7269 VERR_INVALID_PARAMETER);
7270
7271 uint8_t *pbHst = pbHstBuf + offHst;
7272
7273 /* Shortcut for the framebuffer. */
7274 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7275 {
7276 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7277
7278 uint8_t const *pbSrc;
7279 int32_t cbSrcPitch;
7280 uint8_t *pbDst;
7281 int32_t cbDstPitch;
7282
7283 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7284 {
7285 pbSrc = pbHst;
7286 cbSrcPitch = cbHstPitch;
7287 pbDst = pbGst;
7288 cbDstPitch = cbGstPitch;
7289 }
7290 else
7291 {
7292 pbSrc = pbGst;
7293 cbSrcPitch = cbGstPitch;
7294 pbDst = pbHst;
7295 cbDstPitch = cbHstPitch;
7296 }
7297
7298 if ( cbWidth == (uint32_t)cbGstPitch
7299 && cbGstPitch == cbHstPitch)
7300 {
7301 /* Entire scanlines, positive pitch. */
7302 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7303 }
7304 else
7305 {
7306 for (uint32_t i = 0; i < cHeight; ++i)
7307 {
7308 memcpy(pbDst, pbSrc, cbWidth);
7309
7310 pbDst += cbDstPitch;
7311 pbSrc += cbSrcPitch;
7312 }
7313 }
7314 return VINF_SUCCESS;
7315 }
7316
7317 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7318 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7319
7320 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7321 uint32_t iDesc = 0; /* Index in the descriptor array. */
7322 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7323 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7324 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7325 for (uint32_t i = 0; i < cHeight; ++i)
7326 {
7327 uint32_t cbCurrentWidth = cbWidth;
7328 uint32_t offGmrCurrent = offGmrScanline;
7329 uint8_t *pbCurrentHost = pbHstScanline;
7330
7331 /* Find the right descriptor */
7332 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7333 {
7334 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7335 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7336 ++iDesc;
7337 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7338 }
7339
7340 while (cbCurrentWidth)
7341 {
7342 uint32_t cbToCopy;
7343
7344 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7345 cbToCopy = cbCurrentWidth;
7346 else
7347 {
7348 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7349 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7350 }
7351
7352 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7353
7354 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7355
7356 /*
7357 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7358 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7359 * see @bugref{9654#c75}.
7360 */
7361 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7362 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7363 else
7364 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7365 AssertRCBreak(rc);
7366
7367 cbCurrentWidth -= cbToCopy;
7368 offGmrCurrent += cbToCopy;
7369 pbCurrentHost += cbToCopy;
7370
7371 /* Go to the next descriptor if there's anything left. */
7372 if (cbCurrentWidth)
7373 {
7374 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7375 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7376 ++iDesc;
7377 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7378 }
7379 }
7380
7381 offGmrScanline += cbGstPitch;
7382 pbHstScanline += cbHstPitch;
7383 }
7384
7385 return VINF_SUCCESS;
7386}
7387
7388
7389/**
7390 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7391 *
7392 * @param pSizeSrc Source surface dimensions.
7393 * @param pSizeDest Destination surface dimensions.
7394 * @param pBox Coordinates to be clipped.
7395 */
7396void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7397{
7398 /* Src x, w */
7399 if (pBox->srcx > pSizeSrc->width)
7400 pBox->srcx = pSizeSrc->width;
7401 if (pBox->w > pSizeSrc->width - pBox->srcx)
7402 pBox->w = pSizeSrc->width - pBox->srcx;
7403
7404 /* Src y, h */
7405 if (pBox->srcy > pSizeSrc->height)
7406 pBox->srcy = pSizeSrc->height;
7407 if (pBox->h > pSizeSrc->height - pBox->srcy)
7408 pBox->h = pSizeSrc->height - pBox->srcy;
7409
7410 /* Src z, d */
7411 if (pBox->srcz > pSizeSrc->depth)
7412 pBox->srcz = pSizeSrc->depth;
7413 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7414 pBox->d = pSizeSrc->depth - pBox->srcz;
7415
7416 /* Dest x, w */
7417 if (pBox->x > pSizeDest->width)
7418 pBox->x = pSizeDest->width;
7419 if (pBox->w > pSizeDest->width - pBox->x)
7420 pBox->w = pSizeDest->width - pBox->x;
7421
7422 /* Dest y, h */
7423 if (pBox->y > pSizeDest->height)
7424 pBox->y = pSizeDest->height;
7425 if (pBox->h > pSizeDest->height - pBox->y)
7426 pBox->h = pSizeDest->height - pBox->y;
7427
7428 /* Dest z, d */
7429 if (pBox->z > pSizeDest->depth)
7430 pBox->z = pSizeDest->depth;
7431 if (pBox->d > pSizeDest->depth - pBox->z)
7432 pBox->d = pSizeDest->depth - pBox->z;
7433}
7434
7435
7436/**
7437 * Unsigned coordinates in pBox. Clip to [0; pSize).
7438 *
7439 * @param pSize Source surface dimensions.
7440 * @param pBox Coordinates to be clipped.
7441 */
7442void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7443{
7444 /* x, w */
7445 if (pBox->x > pSize->width)
7446 pBox->x = pSize->width;
7447 if (pBox->w > pSize->width - pBox->x)
7448 pBox->w = pSize->width - pBox->x;
7449
7450 /* y, h */
7451 if (pBox->y > pSize->height)
7452 pBox->y = pSize->height;
7453 if (pBox->h > pSize->height - pBox->y)
7454 pBox->h = pSize->height - pBox->y;
7455
7456 /* z, d */
7457 if (pBox->z > pSize->depth)
7458 pBox->z = pSize->depth;
7459 if (pBox->d > pSize->depth - pBox->z)
7460 pBox->d = pSize->depth - pBox->z;
7461}
7462
7463
7464/**
7465 * Clip.
7466 *
7467 * @param pBound Bounding rectangle.
7468 * @param pRect Rectangle to be clipped.
7469 */
7470void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7471{
7472 int32_t left;
7473 int32_t top;
7474 int32_t right;
7475 int32_t bottom;
7476
7477 /* Right order. */
7478 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7479 if (pRect->left < pRect->right)
7480 {
7481 left = pRect->left;
7482 right = pRect->right;
7483 }
7484 else
7485 {
7486 left = pRect->right;
7487 right = pRect->left;
7488 }
7489 if (pRect->top < pRect->bottom)
7490 {
7491 top = pRect->top;
7492 bottom = pRect->bottom;
7493 }
7494 else
7495 {
7496 top = pRect->bottom;
7497 bottom = pRect->top;
7498 }
7499
7500 if (left < pBound->left)
7501 left = pBound->left;
7502 if (right < pBound->left)
7503 right = pBound->left;
7504
7505 if (left > pBound->right)
7506 left = pBound->right;
7507 if (right > pBound->right)
7508 right = pBound->right;
7509
7510 if (top < pBound->top)
7511 top = pBound->top;
7512 if (bottom < pBound->top)
7513 bottom = pBound->top;
7514
7515 if (top > pBound->bottom)
7516 top = pBound->bottom;
7517 if (bottom > pBound->bottom)
7518 bottom = pBound->bottom;
7519
7520 pRect->left = left;
7521 pRect->right = right;
7522 pRect->top = top;
7523 pRect->bottom = bottom;
7524}
7525
7526
7527/**
7528 * Clip.
7529 *
7530 * @param pBound Bounding rectangle.
7531 * @param pRect Rectangle to be clipped.
7532 */
7533void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7534{
7535 uint32_t const leftBound = pBound->x;
7536 uint32_t const rightBound = pBound->x + pBound->w;
7537 uint32_t const topBound = pBound->y;
7538 uint32_t const bottomBound = pBound->y + pBound->h;
7539
7540 uint32_t x = pRect->x;
7541 uint32_t y = pRect->y;
7542 uint32_t w = pRect->w;
7543 uint32_t h = pRect->h;
7544
7545 /* Make sure that right and bottom coordinates can be safely computed. */
7546 if (x > rightBound)
7547 x = rightBound;
7548 if (w > rightBound - x)
7549 w = rightBound - x;
7550 if (y > bottomBound)
7551 y = bottomBound;
7552 if (h > bottomBound - y)
7553 h = bottomBound - y;
7554
7555 /* Switch from x, y, w, h to left, top, right, bottom. */
7556 uint32_t left = x;
7557 uint32_t right = x + w;
7558 uint32_t top = y;
7559 uint32_t bottom = y + h;
7560
7561 /* A standard left, right, bottom, top clipping. */
7562 if (left < leftBound)
7563 left = leftBound;
7564 if (right < leftBound)
7565 right = leftBound;
7566
7567 if (left > rightBound)
7568 left = rightBound;
7569 if (right > rightBound)
7570 right = rightBound;
7571
7572 if (top < topBound)
7573 top = topBound;
7574 if (bottom < topBound)
7575 bottom = topBound;
7576
7577 if (top > bottomBound)
7578 top = bottomBound;
7579 if (bottom > bottomBound)
7580 bottom = bottomBound;
7581
7582 /* Back to x, y, w, h representation. */
7583 pRect->x = left;
7584 pRect->y = top;
7585 pRect->w = right - left;
7586 pRect->h = bottom - top;
7587}
7588
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