VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 33360

最後變更 在這個檔案從33360是 33314,由 vboxsync 提交於 14 年 前

PCI, PDM: MSI-X support (absolutely untested)
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1/* $Id: DevPciIch9.cpp 33314 2010-10-21 15:51:17Z vboxsync $ */
2/** @file
3 * DevPCI - ICH9 southbridge PCI bus emulation Device.
4 */
5
6/*
7 * Copyright (C) 2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19 * Header Files *
20 *******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_PCI
22/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23#define PCI_INCLUDE_PRIVATE
24#include <VBox/pci.h>
25#include <VBox/msi.h>
26#include <VBox/pdmdev.h>
27#include <iprt/asm.h>
28#include <iprt/assert.h>
29#include <iprt/string.h>
30
31#include "../Builtins.h"
32
33#include "MsiCommon.h"
34
35/**
36 * PCI Bus instance.
37 */
38typedef struct PCIBus
39{
40 /** Bus number. */
41 int32_t iBus;
42 /** Number of bridges attached to the bus. */
43 uint32_t cBridges;
44
45 /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
46 R3PTRTYPE(PPCIDEVICE) apDevices[256];
47 /** Array of bridges attached to the bus. */
48 R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
49
50 /** R3 pointer to the device instance. */
51 PPDMDEVINSR3 pDevInsR3;
52 /** Pointer to the PCI R3 helpers. */
53 PCPDMPCIHLPR3 pPciHlpR3;
54
55 /** R0 pointer to the device instance. */
56 PPDMDEVINSR0 pDevInsR0;
57 /** Pointer to the PCI R0 helpers. */
58 PCPDMPCIHLPR0 pPciHlpR0;
59
60 /** RC pointer to the device instance. */
61 PPDMDEVINSRC pDevInsRC;
62 /** Pointer to the PCI RC helpers. */
63 PCPDMPCIHLPRC pPciHlpRC;
64
65 /** The PCI device for the PCI bridge. */
66 PCIDEVICE aPciDev;
67
68} PCIBUS, *PPCIBUS;
69
70
71/** @def PCI_APIC_IRQ_PINS
72 * Number of pins for interrupts if the APIC is used.
73 */
74#define PCI_APIC_IRQ_PINS 8
75
76/**
77 * PCI Globals - This is the host-to-pci bridge and the root bus.
78 */
79typedef struct
80{
81 /** R3 pointer to the device instance. */
82 PPDMDEVINSR3 pDevInsR3;
83 /** R0 pointer to the device instance. */
84 PPDMDEVINSR0 pDevInsR0;
85 /** RC pointer to the device instance. */
86 PPDMDEVINSRC pDevInsRC;
87
88#if HC_ARCH_BITS == 64
89 uint32_t Alignment0;
90#endif
91
92 /** I/O APIC irq levels */
93 volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
94
95#if 1 /* Will be moved into the BIOS soon. */
96 /** The next I/O port address which the PCI BIOS will use. */
97 uint32_t uPciBiosIo;
98 /** The next MMIO address which the PCI BIOS will use. */
99 uint32_t uPciBiosMmio;
100 /** Actual bus number. */
101 uint8_t uBus;
102#endif
103 /* Physical address of PCI config space MMIO region */
104 uint64_t u64PciConfigMMioAddress;
105 /* Length of PCI config space MMIO region */
106 uint64_t u64PciConfigMMioLength;
107
108
109 /** Config register. */
110 uint32_t uConfigReg;
111
112 /** PCI bus which is attached to the host-to-PCI bridge. */
113 PCIBUS aPciBus;
114
115} PCIGLOBALS, *PPCIGLOBALS;
116
117
118typedef struct {
119 uint8_t iBus;
120 uint8_t iDeviceFunc;
121 uint16_t iRegister;
122} PciAddress;
123
124/*******************************************************************************
125 * Defined Constants And Macros *
126 *******************************************************************************/
127
128/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
129 * Saved state version of the ICH9 PCI bus device.
130 */
131#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
132#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
133#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
134
135/** Converts a bus instance pointer to a device instance pointer. */
136#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
137/** Converts a device instance pointer to a PCIGLOBALS pointer. */
138#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
139/** Converts a device instance pointer to a PCIBUS pointer. */
140#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
141/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
142 */
143#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
144
145
146/** @def PCI_LOCK
147 * Acquires the PDM lock. This is a NOP if locking is disabled. */
148/** @def PCI_UNLOCK
149 * Releases the PDM lock. This is a NOP if locking is disabled. */
150#define PCI_LOCK(pDevIns, rc) \
151 do { \
152 int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
153 if (rc2 != VINF_SUCCESS) \
154 return rc2; \
155 } while (0)
156#define PCI_UNLOCK(pDevIns) \
157 DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
158
159#ifndef VBOX_DEVICE_STRUCT_TESTCASE
160
161RT_C_DECLS_BEGIN
162
163PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
164PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
165PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
166PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
167PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
168PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
169PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
170PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
171
172RT_C_DECLS_END
173
174/* Prototypes */
175static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
176#ifdef IN_RING3
177static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
178static void ich9pciUpdateMappings(PCIDevice *pDev);
179static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
180DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
181static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
182#endif
183
184// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
185// mapping, we take n=6 approach
186DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
187{
188 GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
189 pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<8) - 1);
190 pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
191 pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
192}
193
194DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
195{
196 pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
197 pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
198 pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
199}
200
201PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
202{
203 ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
204}
205
206PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
207{
208 /*
209 * The PCI-to-PCI bridge specification defines how the interrupt pins
210 * are routed from the secondary to the primary bus (see chapter 9).
211 * iIrq gives the interrupt pin the pci device asserted.
212 * We change iIrq here according to the spec and call the SetIrq function
213 * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
214 */
215 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
216 PPCIDEVICE pPciDevBus = pPciDev;
217 int iIrqPinBridge = iIrq;
218 uint8_t uDevFnBridge = 0;
219
220 /* Walk the chain until we reach the host bus. */
221 do
222 {
223 uDevFnBridge = pBus->aPciDev.devfn;
224 iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
225
226 /* Get the parent. */
227 pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
228 pPciDevBus = &pBus->aPciDev;
229 } while (pBus->iBus != 0);
230
231 AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
232 ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
233}
234
235/**
236 * Port I/O Handler for PCI address OUT operations.
237 *
238 * @returns VBox status code.
239 *
240 * @param pDevIns The device instance.
241 * @param pvUser User argument - ignored.
242 * @param uPort Port number used for the OUT operation.
243 * @param u32 The value to output.
244 * @param cb The value size in bytes.
245 */
246PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
247{
248 Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
249 NOREF(pvUser);
250 if (cb == 4)
251 {
252 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
253 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
254 pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
255 PCI_UNLOCK(pDevIns);
256 }
257 return VINF_SUCCESS;
258}
259
260/**
261 * Port I/O Handler for PCI address IN operations.
262 *
263 * @returns VBox status code.
264 *
265 * @param pDevIns The device instance.
266 * @param pvUser User argument - ignored.
267 * @param uPort Port number used for the IN operation.
268 * @param pu32 Where to store the result.
269 * @param cb Number of bytes read.
270 */
271PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
272{
273 NOREF(pvUser);
274 if (cb == 4)
275 {
276 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
277 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
278 *pu32 = pThis->uConfigReg;
279 PCI_UNLOCK(pDevIns);
280 Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
281 return VINF_SUCCESS;
282 }
283
284 Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
285
286 return VERR_IOM_IOPORT_UNUSED;
287}
288
289static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
290{
291
292 if (pAddr->iRegister > 0xff)
293 {
294 LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
295 return 0;
296 }
297
298 if (pAddr->iBus != 0)
299 {
300 if (pGlobals->aPciBus.cBridges)
301 {
302#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
303 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
304 if (pBridgeDevice)
305 {
306 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
307 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);
308 }
309#else
310 return VINF_IOM_HC_IOPORT_WRITE;
311#endif
312 }
313 }
314 else
315 {
316 if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
317 {
318#ifdef IN_RING3
319 R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
320 Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));
321 aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);
322#else
323 return VINF_IOM_HC_IOPORT_WRITE;
324#endif
325 }
326 }
327 return VINF_SUCCESS;
328}
329
330static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
331{
332 PciAddress aPciAddr;
333
334 Log(("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
335
336 if (!(pGlobals->uConfigReg & (1 << 31)))
337 return VINF_SUCCESS;
338
339 if ((pGlobals->uConfigReg & 0x3) != 0)
340 return VINF_SUCCESS;
341
342 /* Compute destination device */
343 ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
344
345 return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
346}
347
348/**
349 * Port I/O Handler for PCI data OUT operations.
350 *
351 * @returns VBox status code.
352 *
353 * @param pDevIns The device instance.
354 * @param pvUser User argument - ignored.
355 * @param uPort Port number used for the OUT operation.
356 * @param u32 The value to output.
357 * @param cb The value size in bytes.
358 */
359PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
360{
361 Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
362 NOREF(pvUser);
363 int rc = VINF_SUCCESS;
364 if (!(Port % cb))
365 {
366 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
367 rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
368 PCI_UNLOCK(pDevIns);
369 }
370 else
371 AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
372 return rc;
373}
374
375static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
376{
377 if (pPciAddr->iRegister > 0xff)
378 {
379 LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
380 *pu32 = 0;
381 return 0;
382 }
383
384
385 if (pPciAddr->iBus != 0)
386 {
387 if (pGlobals->aPciBus.cBridges)
388 {
389#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
390 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
391 if (pBridgeDevice)
392 {
393 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
394 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);
395 }
396#else
397 return VINF_IOM_HC_IOPORT_READ;
398#endif
399 }
400 }
401 else
402 {
403 if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
404 {
405#ifdef IN_RING3
406 R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
407 *pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, len);
408 Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
409#else
410 return VINF_IOM_HC_IOPORT_READ;
411#endif
412 }
413 }
414
415 return VINF_SUCCESS;
416}
417
418static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
419{
420 PciAddress aPciAddr;
421
422 *pu32 = 0xffffffff;
423
424 if (!(pGlobals->uConfigReg & (1 << 31)))
425 return VINF_SUCCESS;
426
427 if ((pGlobals->uConfigReg & 0x3) != 0)
428 return VINF_SUCCESS;
429
430 /* Compute destination device */
431 ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
432
433 return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32);
434}
435
436/**
437 * Port I/O Handler for PCI data IN operations.
438 *
439 * @returns VBox status code.
440 *
441 * @param pDevIns The device instance.
442 * @param pvUser User argument - ignored.
443 * @param uPort Port number used for the IN operation.
444 * @param pu32 Where to store the result.
445 * @param cb Number of bytes read.
446 */
447PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
448{
449 NOREF(pvUser);
450 if (!(Port % cb))
451 {
452 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
453 int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
454 PCI_UNLOCK(pDevIns);
455 Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
456 return rc;
457 }
458 AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
459 return VERR_IOM_IOPORT_UNUSED;
460}
461
462/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
463DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
464{
465 return (irq_num + uSlot) & 7;
466}
467
468/* Add one more level up request on APIC input line */
469DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
470{
471 ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
472}
473
474/* Remove one level up request on APIC input line */
475DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
476{
477 ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
478}
479
480static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
481{
482 /* This is only allowed to be called with a pointer to the root bus. */
483 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
484
485 if (iForcedIrq == -1)
486 {
487 int apic_irq, apic_level;
488 PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
489 int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
490
491 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
492 ich9pciApicLevelUp(pGlobals, irq_num);
493 else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
494 ich9pciApicLevelDown(pGlobals, irq_num);
495
496 apic_irq = irq_num + 0x10;
497 apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
498 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
499 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
500 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
501
502 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
503 {
504 /**
505 * we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
506 * PDM_IRQ_LEVEL_HIGH bit set
507 */
508 ich9pciApicLevelDown(pGlobals, irq_num);
509 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
510 apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
511 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
512 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
513 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
514 }
515 } else {
516 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
517 R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
518 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
519 }
520}
521
522static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
523{
524
525 if (PCIDevIsIntxDisabled(pPciDev))
526 {
527 if (MsiIsEnabled(pPciDev))
528 {
529 Log2(("MSI interrupt: %d level=%d\n", iIrq, iLevel));
530 PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
531 MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
532 }
533
534 if (MsixIsEnabled(pPciDev))
535 {
536 Log2(("MSI-X interrupt: %d level=%d\n", iIrq, iLevel));
537 PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
538 MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
539 }
540 return;
541 }
542
543 PPCIBUS pBus = &pGlobals->aPciBus;
544 const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
545
546 /* Check if the state changed. */
547 if (pPciDev->Int.s.uIrqPinState != iLevel)
548 {
549 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
550
551 /* Send interrupt to I/O APIC only now. */
552 if (fIsAcpiDevice)
553 /*
554 * ACPI needs special treatment since SCI is hardwired and
555 * should not be affected by PCI IRQ routing tables at the
556 * same time SCI IRQ is shared in PCI sense hence this
557 * kludge (i.e. we fetch the hardwired value from ACPIs
558 * PCI device configuration space).
559 */
560 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
561 else
562 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
563 }
564}
565
566PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
567{
568 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
569 PciAddress aDest;
570 uint32_t u32 = 0;
571
572 Log2(("ich9pciMcfgMMIOWrite: %p(%d) \n", GCPhysAddr, cb));
573
574 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
575
576 ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
577
578 switch (cb)
579 {
580 case 1:
581 u32 = *(uint8_t*)pv;
582 break;
583 case 2:
584 u32 = *(uint16_t*)pv;
585 break;
586 case 4:
587 u32 = *(uint32_t*)pv;
588 break;
589 default:
590 Assert(false);
591 break;
592 }
593 int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
594 PCI_UNLOCK(pDevIns);
595
596 return rc;
597}
598
599PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
600{
601 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
602 PciAddress aDest;
603 uint32_t rv = 0xffffffff;
604
605 Log2(("ich9pciMcfgMMIORead: %p(%d) \n", GCPhysAddr, cb));
606
607 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
608
609 ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
610
611 int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv);
612
613 switch (cb)
614 {
615 case 1:
616 *(uint8_t*)pv = (uint8_t)rv;
617 break;
618 case 2:
619 *(uint16_t*)pv = (uint16_t)rv;
620 break;
621 case 4:
622 *(uint32_t*)pv = (uint32_t)rv;
623 break;
624 default:
625 Assert(false);
626 break;
627 }
628 PCI_UNLOCK(pDevIns);
629
630 return rc;
631}
632
633#ifdef IN_RING3
634
635DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
636{
637 /* Search for a fitting bridge. */
638 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
639 {
640 /*
641 * Examine secondary and subordinate bus number.
642 * If the target bus is in the range we pass the request on to the bridge.
643 */
644 PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
645 AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
646 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
647
648 if ( iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS)
649 && iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS))
650 return pBridgeTemp;
651 }
652
653 /* Nothing found. */
654 return NULL;
655}
656
657DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
658{
659 return (iRegion == PCI_ROM_SLOT) ?
660 VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
661}
662
663#define INVALID_PCI_ADDRESS ~0U
664
665static void ich9pciUpdateMappings(PCIDevice* pDev)
666{
667 PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
668 uint32_t uLast, uNew;
669
670 int iCmd = PCIDevGetCommand(pDev);
671 for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
672 {
673 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
674 uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
675 int32_t iRegionSize = pRegion->size;
676 int rc;
677
678 if (iRegionSize == 0)
679 continue;
680
681 if (pRegion->type & PCI_ADDRESS_SPACE_IO)
682 {
683 /* port IO region */
684 if (iCmd & PCI_COMMAND_IOACCESS)
685 {
686 /* IO access allowed */
687 uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
688 uNew &= ~(iRegionSize - 1);
689 uLast = uNew + iRegionSize - 1;
690 /* only 64K ioports on PC */
691 if (uLast <= uNew || uNew == 0 || uLast >= 0x10000)
692 uNew = INVALID_PCI_ADDRESS;
693 } else
694 uNew = INVALID_PCI_ADDRESS;
695 }
696 else
697 {
698 /* MMIO region */
699 if (iCmd & PCI_COMMAND_MEMACCESS)
700 {
701 uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
702 /* the ROM slot has a specific enable bit */
703 if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
704 uNew = INVALID_PCI_ADDRESS;
705 else
706 {
707 uNew &= ~(iRegionSize - 1);
708 uLast = uNew + iRegionSize - 1;
709 /* NOTE: we do not support wrapping */
710 /* XXX: as we cannot support really dynamic
711 mappings, we handle specific values as invalid
712 mappings. */
713 if (uLast <= uNew || uNew == 0 || uLast == INVALID_PCI_ADDRESS)
714 uNew = INVALID_PCI_ADDRESS;
715 }
716 } else
717 uNew = INVALID_PCI_ADDRESS;
718 }
719 /* now do the real mapping */
720 if (uNew != pRegion->addr)
721 {
722 if (pRegion->addr != INVALID_PCI_ADDRESS)
723 {
724 if (pRegion->type & PCI_ADDRESS_SPACE_IO)
725 {
726 /* Port IO */
727 rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
728 AssertRC(rc);
729 }
730 else
731 {
732 RTGCPHYS GCPhysBase = pRegion->addr;
733 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
734 {
735 /* unmap it. */
736 rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
737 AssertRC(rc);
738 rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
739 }
740 else
741 rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
742 AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
743 }
744 }
745 pRegion->addr = uNew;
746 if (pRegion->addr != INVALID_PCI_ADDRESS)
747 {
748 /* finally, map the region */
749 rc = pRegion->map_func(pDev, iRegion,
750 pRegion->addr, pRegion->size,
751 (PCIADDRESSSPACE)(pRegion->type));
752 AssertRC(rc);
753 }
754 }
755 }
756}
757
758static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
759{
760 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
761
762 /*
763 * Check input.
764 */
765 if ( !pszName
766 || !pPciDev
767 || iDev >= (int)RT_ELEMENTS(pBus->apDevices)
768 )
769 {
770 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
771 return VERR_INVALID_PARAMETER;
772 }
773
774 /*
775 * Register the device.
776 */
777 return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
778}
779
780
781static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
782{
783 int rc;
784
785 rc = MsiInit(pPciDev, pMsiReg);
786 if (rc != VINF_SUCCESS)
787 return rc;
788
789 rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
790 if (rc != VINF_SUCCESS)
791 return rc;
792
793 return rc;
794}
795
796
797static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
798{
799
800 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
801
802 /*
803 * Check input.
804 */
805 if ( !pszName
806 || !pPciDev
807 || iDev >= (int)RT_ELEMENTS(pBus->apDevices))
808 {
809 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
810 return VERR_INVALID_PARAMETER;
811 }
812
813 /*
814 * Register the device.
815 */
816 return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
817}
818
819static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
820{
821 /*
822 * Validate.
823 */
824 AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
825 || enmType == PCI_ADDRESS_SPACE_IO
826 || enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
827 ("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
828 VERR_INVALID_PARAMETER);
829 AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
830 ("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
831 VERR_INVALID_PARAMETER);
832 int iLastSet = ASMBitLastSetU32(cbRegion);
833 AssertMsgReturn( iLastSet != 0
834 && RT_BIT_32(iLastSet - 1) == cbRegion,
835 ("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
836 VERR_INVALID_PARAMETER);
837
838 /*
839 * Register the I/O region.
840 */
841 PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
842 pRegion->addr = INVALID_PCI_ADDRESS;
843 pRegion->size = cbRegion;
844 pRegion->type = enmType;
845 pRegion->map_func = pfnCallback;
846
847 /* Set type in the config space. */
848 uint32_t u32Address = ich9pciGetRegionReg(iRegion);
849 uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
850 | (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
851 PCIDevSetDWord(pPciDev, u32Address, u32Value);
852
853 return VINF_SUCCESS;
854}
855
856static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
857 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
858{
859 if (ppfnReadOld)
860 *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
861 pPciDev->Int.s.pfnConfigRead = pfnRead;
862
863 if (ppfnWriteOld)
864 *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
865 pPciDev->Int.s.pfnConfigWrite = pfnWrite;
866}
867
868/**
869 * Saves a state of the PCI device.
870 *
871 * @returns VBox status code.
872 * @param pDevIns Device instance of the PCI Bus.
873 * @param pPciDev Pointer to PCI device.
874 * @param pSSM The handle to save the state to.
875 */
876static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
877{
878 return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
879}
880
881static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
882{
883 /*
884 * Iterate thru all the devices.
885 */
886 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
887 {
888 PPCIDEVICE pDev = pBus->apDevices[i];
889 if (pDev)
890 {
891 /* Device position */
892 SSMR3PutU32(pSSM, i);
893 /* PCI config registers */
894 SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
895
896 /* Device flags */
897 int rc = SSMR3PutU32(pSSM, pDev->Int.s.uFlags);
898 if (RT_FAILURE(rc))
899 return rc;
900
901 /* IRQ pin state */
902 rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
903 if (RT_FAILURE(rc))
904 return rc;
905
906 /* MSI info */
907 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
908 if (RT_FAILURE(rc))
909 return rc;
910 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
911 if (RT_FAILURE(rc))
912 return rc;
913
914 /* MSI-X info */
915 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
916 if (RT_FAILURE(rc))
917 return rc;
918 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
919 if (RT_FAILURE(rc))
920 return rc;
921 }
922 }
923 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
924}
925
926static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
927{
928 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
929
930 /*
931 * Bus state data.
932 */
933 SSMR3PutU32(pSSM, pThis->uConfigReg);
934
935 /*
936 * Save IRQ states.
937 */
938 for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
939 SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
940
941 SSMR3PutU32(pSSM, ~0); /* separator */
942
943 return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
944}
945
946
947static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
948{
949 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
950 return ich9pciR3CommonSaveExec(pThis, pSSM);
951}
952
953
954static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
955{
956 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
957
958 LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
959
960 /* If the current bus is not the target bus search for the bus which contains the device. */
961 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
962 {
963 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
964 if (pBridgeDevice)
965 {
966 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
967 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
968 }
969 }
970 else
971 {
972 /* This is the target bus, pass the write to the device. */
973 PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
974 if (pPciDev)
975 {
976 Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
977 pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
978 }
979 }
980}
981
982static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
983{
984 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
985 uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
986
987 LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
988
989 /* If the current bus is not the target bus search for the bus which contains the device. */
990 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
991 {
992 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
993 if (pBridgeDevice)
994 {
995 AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
996 u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
997 }
998 }
999 else
1000 {
1001 /* This is the target bus, pass the read to the device. */
1002 PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1003 if (pPciDev)
1004 {
1005 u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1006 Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1007 }
1008 }
1009
1010 return u32Value;
1011}
1012
1013
1014/**
1015 * Common routine for restoring the config registers of a PCI device.
1016 *
1017 * @param pDev The PCI device.
1018 * @param pbSrcConfig The configuration register values to be loaded.
1019 * @param fIsBridge Whether this is a bridge device or not.
1020 */
1021static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1022{
1023 /*
1024 * This table defines the fields for normal devices and bridge devices, and
1025 * the order in which they need to be restored.
1026 */
1027 static const struct PciField
1028 {
1029 uint8_t off;
1030 uint8_t cb;
1031 uint8_t fWritable;
1032 uint8_t fBridge;
1033 const char *pszName;
1034 } s_aFields[] =
1035 {
1036 /* off,cb,fW,fB, pszName */
1037 { VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1038 { VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1039 { VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1040 { VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1041 { VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1042 { VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1043 { VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1044 { VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1045 { VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1046 { VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1047 { VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1048 { VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1049 { VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1050 { VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1051 { VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1052 { VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1053 { VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1054 { VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1055 { VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1056 { VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1057 { VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1058 { VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1059 { VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1060 { VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1061 { VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1062 { VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1063 { VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1064 { VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1065 { VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1066 { VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1067 { VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1068 { VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1069 { VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1070 { VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1071 { VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1072 { VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1073 { VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1074 { VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1075 { VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1076 { VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1077 { VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1078 { VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1079 { VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1080 { VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1081 /* The COMMAND register must come last as it requires the *ADDRESS*
1082 registers to be restored before we pretent to change it from 0 to
1083 whatever value the guest assigned it. */
1084 { VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1085 };
1086
1087#ifdef RT_STRICT
1088 /* Check that we've got full register coverage. */
1089 uint32_t bmDevice[0x40 / 32];
1090 uint32_t bmBridge[0x40 / 32];
1091 RT_ZERO(bmDevice);
1092 RT_ZERO(bmBridge);
1093 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1094 {
1095 uint8_t off = s_aFields[i].off;
1096 uint8_t cb = s_aFields[i].cb;
1097 uint8_t f = s_aFields[i].fBridge;
1098 while (cb-- > 0)
1099 {
1100 if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1101 if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1102 if (f & 1) ASMBitSet(bmDevice, off);
1103 if (f & 2) ASMBitSet(bmBridge, off);
1104 off++;
1105 }
1106 }
1107 for (uint32_t off = 0; off < 0x40; off++)
1108 {
1109 AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1110 AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1111 }
1112#endif
1113
1114 /*
1115 * Loop thru the fields covering the 64 bytes of standard registers.
1116 */
1117 uint8_t const fBridge = fIsBridge ? 2 : 1;
1118 uint8_t *pbDstConfig = &pDev->config[0];
1119 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1120 if (s_aFields[i].fBridge & fBridge)
1121 {
1122 uint8_t const off = s_aFields[i].off;
1123 uint8_t const cb = s_aFields[i].cb;
1124 uint32_t u32Src;
1125 uint32_t u32Dst;
1126 switch (cb)
1127 {
1128 case 1:
1129 u32Src = pbSrcConfig[off];
1130 u32Dst = pbDstConfig[off];
1131 break;
1132 case 2:
1133 u32Src = *(uint16_t const *)&pbSrcConfig[off];
1134 u32Dst = *(uint16_t const *)&pbDstConfig[off];
1135 break;
1136 case 4:
1137 u32Src = *(uint32_t const *)&pbSrcConfig[off];
1138 u32Dst = *(uint32_t const *)&pbDstConfig[off];
1139 break;
1140 default:
1141 AssertFailed();
1142 continue;
1143 }
1144
1145 if ( u32Src != u32Dst
1146 || off == VBOX_PCI_COMMAND)
1147 {
1148 if (u32Src != u32Dst)
1149 {
1150 if (!s_aFields[i].fWritable)
1151 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1152 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1153 else
1154 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1155 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1156 }
1157 if (off == VBOX_PCI_COMMAND)
1158 PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1159 pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1160 }
1161 }
1162
1163 /*
1164 * The device dependent registers.
1165 *
1166 * We will not use ConfigWrite here as we have no clue about the size
1167 * of the registers, so the device is responsible for correctly
1168 * restoring functionality governed by these registers.
1169 */
1170 for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1171 if (pbDstConfig[off] != pbSrcConfig[off])
1172 {
1173 LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1174 pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1175 pbDstConfig[off] = pbSrcConfig[off];
1176 }
1177}
1178
1179/**
1180 * Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1181 *
1182 * @returns VBox status code.
1183 * @param pBus The bus which data is being loaded.
1184 * @param pSSM The saved state handle.
1185 * @param uVersion The data version.
1186 * @param uPass The pass.
1187 */
1188static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1189{
1190 uint32_t u32;
1191 uint32_t i;
1192 int rc;
1193
1194 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1195
1196 /*
1197 * Iterate thru all the devices and write 0 to the COMMAND register so
1198 * that all the memory is unmapped before we start restoring the saved
1199 * mapping locations.
1200 *
1201 * The register value is restored afterwards so we can do proper
1202 * LogRels in pciR3CommonRestoreConfig.
1203 */
1204 for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1205 {
1206 PPCIDEVICE pDev = pBus->apDevices[i];
1207 if (pDev)
1208 {
1209 uint16_t u16 = PCIDevGetCommand(pDev);
1210 pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1211 PCIDevSetCommand(pDev, u16);
1212 Assert(PCIDevGetCommand(pDev) == u16);
1213 }
1214 }
1215
1216 /*
1217 * Iterate all the devices.
1218 */
1219 for (i = 0;; i++)
1220 {
1221 PCIDEVICE DevTmp;
1222 PPCIDEVICE pDev;
1223
1224 /* index / terminator */
1225 rc = SSMR3GetU32(pSSM, &u32);
1226 if (RT_FAILURE(rc))
1227 return rc;
1228 if (u32 == (uint32_t)~0)
1229 break;
1230 if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1231 || u32 < i)
1232 {
1233 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1234 return rc;
1235 }
1236
1237 /* skip forward to the device checking that no new devices are present. */
1238 for (; i < u32; i++)
1239 {
1240 pDev = pBus->apDevices[i];
1241 if (pDev)
1242 {
1243 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1244 PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1245 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1246 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1247 i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1248 }
1249 }
1250
1251 /* get the data */
1252 DevTmp.Int.s.uFlags = 0;
1253 DevTmp.Int.s.u8MsiCapOffset = 0;
1254 DevTmp.Int.s.u8MsiCapSize = 0;
1255 DevTmp.Int.s.u8MsixCapOffset = 0;
1256 DevTmp.Int.s.u8MsixCapSize = 0;
1257 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1258 SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1259
1260 rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.uFlags);
1261 if (RT_FAILURE(rc))
1262 return rc;
1263
1264 rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1265 if (RT_FAILURE(rc))
1266 return rc;
1267
1268 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1269 if (RT_FAILURE(rc))
1270 return rc;
1271
1272 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1273 if (RT_FAILURE(rc))
1274 return rc;
1275
1276 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1277 if (RT_FAILURE(rc))
1278 return rc;
1279
1280 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1281 if (RT_FAILURE(rc))
1282 return rc;
1283
1284 /* check that it's still around. */
1285 pDev = pBus->apDevices[i];
1286 if (!pDev)
1287 {
1288 LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1289 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1290 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1291 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1292 i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1293 continue;
1294 }
1295
1296 /* match the vendor id assuming that this will never be changed. */
1297 if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1298 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1299 i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1300
1301 /* commit the loaded device config. */
1302 pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1303
1304 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1305 }
1306
1307 return VINF_SUCCESS;
1308}
1309
1310/**
1311 * Loads a saved PCI device state.
1312 *
1313 * @returns VBox status code.
1314 * @param pDevIns Device instance of the PCI Bus.
1315 * @param pPciDev Pointer to PCI device.
1316 * @param pSSM The handle to the saved state.
1317 */
1318static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1319{
1320 return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1321}
1322
1323static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1324{
1325 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1326 PPCIBUS pBus = &pThis->aPciBus;
1327 uint32_t u32;
1328 int rc;
1329
1330 /* We ignore this version as there's no saved state with it anyway */
1331 if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1332 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1333 if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1334 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1335
1336 /*
1337 * Bus state data.
1338 */
1339 SSMR3GetU32(pSSM, &pThis->uConfigReg);
1340
1341 /*
1342 * Load IRQ states.
1343 */
1344 for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1345 SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1346
1347 /* separator */
1348 rc = SSMR3GetU32(pSSM, &u32);
1349 if (RT_FAILURE(rc))
1350 return rc;
1351 if (u32 != (uint32_t)~0)
1352 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1353
1354 return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1355}
1356
1357static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1358{
1359 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1360 if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1361 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1362 return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1363}
1364
1365static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1366{
1367 uint32_t u32Val = 0xffffffff;
1368 PciAddress aPciAddr;
1369
1370 aPciAddr.iBus = uBus;
1371 aPciAddr.iDeviceFunc = uDevFn;
1372 aPciAddr.iRegister = addr;
1373
1374 int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val);
1375 AssertRC(rc);
1376 switch (len)
1377 {
1378 case 1:
1379 u32Val &= 0xff;
1380 break;
1381 case 2:
1382 u32Val &= 0xffff;
1383 break;
1384 }
1385 return u32Val;
1386}
1387
1388static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1389{
1390 PciAddress aPciAddr;
1391
1392 aPciAddr.iBus = uBus;
1393 aPciAddr.iDeviceFunc = uDevFn;
1394 aPciAddr.iRegister = addr;
1395
1396 ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
1397}
1398
1399static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1400{
1401 uint32_t uReg = ich9pciGetRegionReg(iRegion);
1402
1403 /* Read memory type first. */
1404 uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1405 /* Read command register. */
1406 uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1407
1408 if ( iRegion == PCI_ROM_SLOT )
1409 uCmd |= PCI_COMMAND_MEMACCESS;
1410 else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1411 uCmd |= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1412 else /* The region is MMIO. */
1413 uCmd |= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1414
1415 /* Write address of the device. */
1416 ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1417
1418 /* enable memory mappings */
1419 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1420}
1421
1422
1423static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1424{
1425 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1426 /* Temporary until we know how many other bridges are behind this one. */
1427 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1428
1429 /* Add position of this bridge into the array. */
1430 paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1431
1432 /*
1433 * The I/O range for the bridge must be aligned to a 4KB boundary.
1434 * This does not change anything really as the access to the device is not going
1435 * through the bridge but we want to be compliant to the spec.
1436 */
1437 if ((pGlobals->uPciBiosIo % 4096) != 0)
1438 {
1439 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1440 Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1441 }
1442 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1443
1444 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1445 if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1446 {
1447 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1448 Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1449 }
1450 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1451
1452 /* Save values to compare later to. */
1453 uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1454 uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1455
1456 /* Init devices behind the bridge and possibly other bridges as well. */
1457 for (int iDev = 0; iDev <= 255; iDev++)
1458 ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1459
1460 /* The number of bridges behind the this one is now available. */
1461 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1462
1463 /*
1464 * Set I/O limit register. If there is no device with I/O space behind the bridge
1465 * we set a lower value than in the base register.
1466 * The result with a real bridge is that no I/O transactions are passed to the secondary
1467 * interface. Again this doesn't really matter here but we want to be compliant to the spec.
1468 */
1469 if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1470 {
1471 /* The upper boundary must be one byte less than a 4KB boundary. */
1472 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1473 }
1474
1475 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1476
1477 /* Same with the MMIO limit register but with 1MB boundary here. */
1478 if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1479 {
1480 /* The upper boundary must be one byte less than a 1MB boundary. */
1481 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1482 }
1483 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1484
1485 /*
1486 * Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1487 * which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1488 * the base register than in the limit register.
1489 */
1490 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1491 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1492 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1493 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1494}
1495
1496static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1497{
1498 uint32_t *paddr;
1499 uint16_t uDevClass, uVendor, uDevice;
1500 uint8_t uCmd;
1501
1502 uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1503 uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1504 uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1505
1506 /* If device is present */
1507 if (uVendor == 0xffff)
1508 return;
1509
1510 switch (uDevClass)
1511 {
1512 case 0x0101:
1513 /* IDE controller */
1514 ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1515 ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1516 goto default_map;
1517 break;
1518 case 0x0300:
1519 /* VGA controller */
1520 if (uVendor != 0x80ee)
1521 goto default_map;
1522 /* VGA: map frame buffer to default Bochs VBE address */
1523 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1524 /*
1525 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1526 * only the framebuffer (i.e., a memory region) is explicitly registered via
1527 * ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1528 */
1529 uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1530 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1531 /* Enable I/O space access. */
1532 uCmd | PCI_COMMAND_IOACCESS,
1533 1);
1534 break;
1535 case 0x0800:
1536 /* PIC */
1537 if (uVendor == 0x1014)
1538 {
1539 /* IBM */
1540 if (uDevice == 0x0046 || uDevice == 0xFFFF)
1541 /* MPIC & MPIC2 */
1542 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1543 }
1544 break;
1545 case 0xff00:
1546 if ((uVendor == 0x0106b)
1547 && (uDevice == 0x0017 || uDevice == 0x0022))
1548 {
1549 /* macio bridge */
1550 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000);
1551 }
1552 break;
1553 case 0x0604:
1554 /* PCI-to-PCI bridge. */
1555 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1556
1557 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1558 pGlobals->uBus++;
1559 ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1560 break;
1561 default:
1562 default_map:
1563 {
1564 /* default memory mappings */
1565 /*
1566 * We ignore ROM region here.
1567 */
1568 for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1569 {
1570 uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1571
1572 /* Calculate size. */
1573 uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1574 ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1575 uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1576 /* Clear resource information depending on resource type. */
1577 if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1578 u32Size &= ~(0x01);
1579 else /* MMIO */
1580 u32Size &= ~(0x0f);
1581
1582 bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1583 /*
1584 * Invert all bits and add 1 to get size of the region.
1585 * (From PCI implementation note)
1586 */
1587 if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1588 u32Size = (~(u32Size | UINT32_C(0xffff0000))) + 1;
1589 else
1590 u32Size = (~u32Size) + 1;
1591
1592 Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1593
1594 if (u32Size)
1595 {
1596 paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1597 *paddr = (*paddr + u32Size - 1) & ~(u32Size - 1);
1598 Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1599 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1600 *paddr += u32Size;
1601 Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1602 }
1603 }
1604 break;
1605 }
1606 }
1607
1608 /* map the interrupt */
1609 uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1610 if (uPin != 0)
1611 {
1612 uint8_t uBridgeDevFn = uDevFn;
1613 uPin--;
1614
1615 /* We need to go up to the host bus to see which irq this device will assert there. */
1616 while (cBridgeDepth != 0)
1617 {
1618 /* Get the pin the device would assert on the bridge. */
1619 uPin = ((uBridgeDevFn >> 3) + uPin) & 3;
1620 uBridgeDevFn = paBridgePositions[cBridgeDepth];
1621 cBridgeDepth--;
1622 }
1623 }
1624}
1625
1626static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 };
1627
1628static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1629{
1630 unsigned i;
1631 uint8_t elcr[2] = {0, 0};
1632 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1633 PVM pVM = PDMDevHlpGetVM(pDevIns);
1634 Assert(pVM);
1635
1636 /*
1637 * Set the start addresses.
1638 */
1639 pGlobals->uPciBiosIo = 0xd000;
1640 pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1641 pGlobals->uBus = 0;
1642
1643 /*
1644 * Activate IRQ mappings.
1645 */
1646 for (i = 0; i < 4; i++)
1647 {
1648 uint8_t irq = auPciIrqs[i];
1649 /* Set to trigger level. */
1650 elcr[irq >> 3] |= (1 << (irq & 7));
1651 }
1652
1653 /* Tell to the PIC. */
1654 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1655 if (rcStrict == VINF_SUCCESS)
1656 rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1657 if (rcStrict != VINF_SUCCESS)
1658 {
1659 AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1660 return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1661 }
1662
1663 /*
1664 * Init the devices.
1665 */
1666 for (i = 0; i < 256; i++)
1667 {
1668 uint8_t aBridgePositions[256];
1669
1670 memset(aBridgePositions, 0, sizeof(aBridgePositions));
1671 Log2(("PCI: Initializing device %d (%#x)\n",
1672 i, 0x80000000 | (i << 8)));
1673 ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1674 }
1675
1676 return VINF_SUCCESS;
1677}
1678
1679static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1680{
1681 if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1682 {
1683 AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1684 }
1685
1686 if ( PCIIsMsiCapable(aDev)
1687 && (u32Address >= aDev->Int.s.u8MsiCapOffset)
1688 && (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1689 )
1690 {
1691 return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1692 }
1693
1694 if ( PCIIsMsixCapable(aDev)
1695 && (u32Address >= aDev->Int.s.u8MsixCapOffset)
1696 && (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1697 )
1698 {
1699 return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1700 }
1701
1702 AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1703 0);
1704 switch (len)
1705 {
1706 case 1:
1707 return PCIDevGetByte(aDev, u32Address);
1708 case 2:
1709 return PCIDevGetWord(aDev, u32Address);
1710 case 4:
1711 return PCIDevGetDWord(aDev, u32Address);
1712 default:
1713 Assert(false);
1714 return 0;
1715 }
1716}
1717
1718
1719/**
1720 * See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1721 * registers and their writability policy.
1722 */
1723static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1724 uint32_t val, unsigned len)
1725{
1726 Assert(len <= 4);
1727
1728 if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1729 {
1730 AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1731 }
1732
1733 AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1734
1735 if ( PCIIsMsiCapable(aDev)
1736 && (u32Address >= aDev->Int.s.u8MsiCapOffset)
1737 && (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1738 )
1739 {
1740 MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1741 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1742 aDev, u32Address, val, len);
1743 return;
1744 }
1745
1746 if ( PCIIsMsixCapable(aDev)
1747 && (u32Address >= aDev->Int.s.u8MsixCapOffset)
1748 && (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1749 )
1750 {
1751 MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1752 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1753 aDev, u32Address, val, len);
1754 return;
1755 }
1756
1757
1758 /* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
1759 while ( len == 4
1760 && ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
1761 && u32Address < VBOX_PCI_BASE_ADDRESS_0 + 6 * 4)
1762 || ( u32Address >= VBOX_PCI_ROM_ADDRESS
1763 && u32Address < VBOX_PCI_ROM_ADDRESS+4)
1764 )
1765 )
1766 {
1767 PCIIORegion *pRegion;
1768 int reg, regionSize;
1769
1770 reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1771 pRegion = &aDev->Int.s.aIORegions[reg];
1772 regionSize = pRegion->size;
1773 if (regionSize == 0)
1774 break;
1775 /* compute the stored value */
1776 if (reg == PCI_ROM_SLOT) {
1777 /* keep ROM enable bit */
1778 val &= (~(regionSize - 1)) | 1;
1779 } else {
1780 val &= ~(regionSize - 1);
1781 val |= pRegion->type;
1782 }
1783 PCIDevSetDWord(aDev, u32Address, val);
1784 ich9pciUpdateMappings(aDev);
1785 return;
1786 }
1787
1788 uint32_t addr = u32Address;
1789 bool fUpdateMappings = false;
1790 for (uint32_t i = 0; i < len; i++)
1791 {
1792 bool fWritable = false;
1793 switch (PCIDevGetHeaderType(aDev))
1794 {
1795 case 0x00: /* normal device */
1796 case 0x80: /* multi-function device */
1797 switch (addr)
1798 {
1799 /* Read-only registers */
1800 case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1801 case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1802 case VBOX_PCI_REVISION_ID:
1803 case VBOX_PCI_CLASS_PROG:
1804 case VBOX_PCI_CLASS_SUB:
1805 case VBOX_PCI_CLASS_BASE:
1806 case VBOX_PCI_HEADER_TYPE:
1807 case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1808 case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1809 case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1810 case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1811 case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1812 case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1813 case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1814 case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1815 case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1816 case VBOX_PCI_CAPABILITY_LIST:
1817 case VBOX_PCI_INTERRUPT_PIN:
1818 fWritable = false;
1819 break;
1820 /* Others can be written */
1821 default:
1822 fWritable = true;
1823 break;
1824 }
1825 break;
1826 default:
1827 case 0x01: /* PCI-PCI bridge */
1828 switch (addr)
1829 {
1830 /* Read-only registers */
1831 case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1832 case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1833 case VBOX_PCI_REVISION_ID:
1834 case VBOX_PCI_CLASS_PROG:
1835 case VBOX_PCI_CLASS_SUB:
1836 case VBOX_PCI_CLASS_BASE:
1837 case VBOX_PCI_HEADER_TYPE:
1838 case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1839 case VBOX_PCI_INTERRUPT_PIN:
1840 fWritable = false;
1841 break;
1842 default:
1843 fWritable = true;
1844 break;
1845 }
1846 break;
1847 }
1848
1849 uint8_t u8Val = (uint8_t)val;
1850
1851 switch (addr)
1852 {
1853 case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1854 fUpdateMappings = true;
1855 PCIDevSetByte(aDev, addr, u8Val);
1856 break;
1857 case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1858 /* don't change reserved bits (11-15) */
1859 u8Val &= UINT32_C(~0xf8);
1860 fUpdateMappings = true;
1861 PCIDevSetByte(aDev, addr, u8Val);
1862 break;
1863 case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1864 /* don't change read-only bits => actually all lower bits are read-only */
1865 u8Val &= UINT32_C(~0xff);
1866 /* status register, low part: clear bits by writing a '1' to the corresponding bit */
1867 aDev->config[addr] &= ~u8Val;
1868 break;
1869 case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1870 /* don't change read-only bits */
1871 u8Val &= UINT32_C(~0x06);
1872 /* status register, high part: clear bits by writing a '1' to the corresponding bit */
1873 aDev->config[addr] &= ~u8Val;
1874 break;
1875 default:
1876 if (fWritable)
1877 PCIDevSetByte(aDev, addr, u8Val);
1878 }
1879 addr++;
1880 val >>= 8;
1881 }
1882
1883 if (fUpdateMappings)
1884 /* if the command register is modified, we must modify the mappings */
1885 ich9pciUpdateMappings(aDev);
1886}
1887
1888/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1889static const struct {
1890 const char* pszName;
1891 int32_t iSlot;
1892 int32_t iFunction;
1893} PciSlotAssignments[] = {
1894 {
1895 "lan", 25, 0 /* LAN controller */
1896 },
1897 {
1898 "hda", 27, 0 /* High Definition Audio */
1899 },
1900 {
1901 "i82801", 30, 0 /* Host Controller */
1902 },
1903 /**
1904 * Please note, that for devices being functions, like we do here, device 0
1905 * must be multifunction, i.e. have header type 0x80. Our LPC device is.
1906 * Alternative approach is to assign separate slot to each device.
1907 */
1908 {
1909 "lpc", 31, 0 /* Low Pin Count bus */
1910 },
1911 {
1912 "piix3ide", 31, 1 /* IDE controller */
1913 },
1914 /* Disable, if we may wish to have multiple AHCI controllers */
1915#if 1
1916 {
1917 "ahci", 31, 2 /* SATA controller */
1918 },
1919#endif
1920 {
1921 "smbus", 31, 3 /* System Management Bus */
1922 },
1923 {
1924 "usb-ohci", 31, 4 /* OHCI USB controller */
1925 },
1926 {
1927 "usb-ehci", 31, 5 /* EHCI USB controller */
1928 },
1929 {
1930 "thermal", 31, 6 /* Thermal controller */
1931 },
1932};
1933
1934static bool assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn, PciAddress* aPosition)
1935{
1936 aPosition->iBus = 0;
1937 aPosition->iDeviceFunc = iDevFn;
1938 aPosition->iRegister = 0; /* N/A */
1939
1940 /* Hardcoded slots/functions, per chipset spec */
1941 for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1942 {
1943 if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1944 {
1945 PCISetRequestedDevfunc(pPciDev);
1946 aPosition->iDeviceFunc =
1947 (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1948 return true;
1949 }
1950 }
1951
1952 /* Explicit slot request */
1953 if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
1954 return true;
1955
1956 /* Otherwise when assigning a slot, we need to make sure all its functions are available */
1957 for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
1958 {
1959 if ( !pBus->apDevices[iPos]
1960 && !pBus->apDevices[iPos + 1]
1961 && !pBus->apDevices[iPos + 2]
1962 && !pBus->apDevices[iPos + 3]
1963 && !pBus->apDevices[iPos + 4]
1964 && !pBus->apDevices[iPos + 5]
1965 && !pBus->apDevices[iPos + 6]
1966 && !pBus->apDevices[iPos + 7])
1967 {
1968 PCIClearRequestedDevfunc(pPciDev);
1969 aPosition->iDeviceFunc = iPos;
1970 return true;
1971 }
1972 }
1973
1974 return false;
1975}
1976
1977static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
1978{
1979 PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
1980
1981 return (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
1982 || (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
1983 || (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
1984 || (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
1985 || (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
1986 || (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
1987 || (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
1988 || (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
1989 ;
1990}
1991
1992static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1993{
1994 PciAddress aPosition = {0, 0, 0};
1995
1996 /*
1997 * Find device position
1998 */
1999 if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2000 {
2001 AssertMsgFailed(("Couldn't asssign position!\n"));
2002 return VERR_PDM_TOO_PCI_MANY_DEVICES;
2003 }
2004
2005 AssertMsgReturn(aPosition.iBus == 0,
2006 ("Assigning behind the bridge not implemented yet\n"),
2007 VERR_PDM_TOO_PCI_MANY_DEVICES);
2008
2009
2010 iDev = aPosition.iDeviceFunc;
2011 /*
2012 * Check if we can really take this slot, possibly by relocating
2013 * its current habitant, if it wasn't hard assigned too.
2014 */
2015 if (PCIIsRequestedDevfunc(pPciDev) &&
2016 pBus->apDevices[iDev] &&
2017 PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
2018 {
2019 AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2020 pszName, pBus->apDevices[iDev]->name, iDev));
2021 return VERR_INTERNAL_ERROR;
2022 }
2023
2024 if (pBus->apDevices[iDev])
2025 {
2026 /* if we got here, we shall (and usually can) relocate the device */
2027 bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2028 AssertMsgReturn(aPosition.iBus == 0,
2029 ("Assigning behind the bridge not implemented yet\n"),
2030 VERR_PDM_TOO_PCI_MANY_DEVICES);
2031 int iRelDev = aPosition.iDeviceFunc;
2032 if (!assigned || iRelDev == iDev)
2033 {
2034 AssertMsgFailed(("Couldn't find free spot!\n"));
2035 return VERR_PDM_TOO_PCI_MANY_DEVICES;
2036 }
2037 /* Copy device function by function to its new position */
2038 for (int i = 0; i < 8; i++)
2039 {
2040 if (!pBus->apDevices[iDev + i])
2041 continue;
2042 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2043 pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2044 pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2045 pBus->apDevices[iDev + i] = NULL;
2046 }
2047 }
2048
2049 /*
2050 * Fill in device information.
2051 */
2052 pPciDev->devfn = iDev;
2053 pPciDev->name = pszName;
2054 pPciDev->Int.s.pBusR3 = pBus;
2055 pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2056 pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2057 pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2058 pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2059 pBus->apDevices[iDev] = pPciDev;
2060 if (PCIIsPci2PciBridge(pPciDev))
2061 {
2062 AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2063 AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2064 ("device is a bridge but does not implement read/write functions\n"));
2065 pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2066 pBus->cBridges++;
2067 }
2068
2069 Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
2070 iDev >> 3, iDev & 7, 0x80000000 | (iDev << 8), pszName));
2071
2072 return VINF_SUCCESS;
2073}
2074
2075
2076/**
2077 * Info handler, device version.
2078 *
2079 * @param pDevIns Device instance which registered the info.
2080 * @param pHlp Callback functions for doing output.
2081 * @param pszArgs Argument string. Optional and specific to the handler.
2082 */
2083static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2084{
2085 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2086 uint32_t iBus = 0, iDev;
2087
2088
2089 for (iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2090 {
2091 PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2092 if (pPciDev != NULL)
2093 pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %x-%x\n",
2094 iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2095 pPciDev->name,
2096 PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev)
2097 );
2098 }
2099}
2100
2101
2102static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2103 int iInstance,
2104 PCFGMNODE pCfg)
2105{
2106 int rc;
2107 Assert(iInstance == 0);
2108
2109 /*
2110 * Validate and read configuration.
2111 */
2112 if (!CFGMR3AreValuesValid(pCfg,
2113 "IOAPIC\0"
2114 "GCEnabled\0"
2115 "R0Enabled\0"
2116 "McfgBase\0"
2117 "McfgLength\0"
2118 ))
2119 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2120
2121 /* query whether we got an IOAPIC */
2122 bool fUseIoApic;
2123 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2124 if (RT_FAILURE(rc))
2125 return PDMDEV_SET_ERROR(pDevIns, rc,
2126 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2127
2128 /* check if RC code is enabled. */
2129 bool fGCEnabled;
2130 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2131 if (RT_FAILURE(rc))
2132 return PDMDEV_SET_ERROR(pDevIns, rc,
2133 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2134
2135 /* check if R0 code is enabled. */
2136 bool fR0Enabled;
2137 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2138 if (RT_FAILURE(rc))
2139 return PDMDEV_SET_ERROR(pDevIns, rc,
2140 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2141
2142 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2143
2144 /*
2145 * Init data.
2146 */
2147 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2148 PPCIBUS pBus = &pGlobals->aPciBus;
2149 /* Zero out everything */
2150 memset(pGlobals, 0, sizeof(*pGlobals));
2151 /* And fill values */
2152 if (!fUseIoApic)
2153 return PDMDEV_SET_ERROR(pDevIns, rc,
2154 N_("Must use IO-APIC with ICH9 chipset"));
2155 rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2156 if (RT_FAILURE(rc))
2157 return PDMDEV_SET_ERROR(pDevIns, rc,
2158 N_("Configuration error: Failed to read \"McfgBase\""));
2159 rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2160 if (RT_FAILURE(rc))
2161 return PDMDEV_SET_ERROR(pDevIns, rc,
2162 N_("Configuration error: Failed to read \"McfgLength\""));
2163
2164 pGlobals->pDevInsR3 = pDevIns;
2165 pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2166 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2167
2168 pGlobals->aPciBus.pDevInsR3 = pDevIns;
2169 pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2170 pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2171 pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2172
2173 /*
2174 * Register bus
2175 */
2176 PDMPCIBUSREG PciBusReg;
2177 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2178 PciBusReg.pfnRegisterR3 = ich9pciRegister;
2179 PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2180 PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2181 PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2182 PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2183 PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2184 PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2185 PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2186 PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2187 PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2188 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2189 if (RT_FAILURE(rc))
2190 return PDMDEV_SET_ERROR(pDevIns, rc,
2191 N_("Failed to register ourselves as a PCI Bus"));
2192 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2193 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2194 N_("PCI helper version mismatch; got %#x expected %#x"),
2195 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2196
2197 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2198 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2199
2200 /*
2201 * Fill in PCI configs and add them to the bus.
2202 */
2203
2204 /**
2205 * We emulate 82801IB ICH9 IO chip used in Q35,
2206 * see http://ark.intel.com/Product.aspx?id=31892
2207 *
2208 * Stepping S-Spec Top Marking
2209 *
2210 * A2 SLA9M NH82801IB
2211 */
2212 PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2213 PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2214 PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2215 PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2216 PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2217 PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* normal device */
2218
2219 pBus->aPciDev.pDevIns = pDevIns;
2220 /* We register Host<->PCI controller on the bus */
2221 ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2222
2223 /*
2224 * Register I/O ports and save state.
2225 */
2226 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2227 if (RT_FAILURE(rc))
2228 return rc;
2229 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2230 if (RT_FAILURE(rc))
2231 return rc;
2232 if (fGCEnabled)
2233 {
2234 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2235 if (RT_FAILURE(rc))
2236 return rc;
2237 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2238 if (RT_FAILURE(rc))
2239 return rc;
2240 }
2241 if (fR0Enabled)
2242 {
2243 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2244 if (RT_FAILURE(rc))
2245 return rc;
2246 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2247 if (RT_FAILURE(rc))
2248 return rc;
2249 }
2250
2251 if (pGlobals->u64PciConfigMMioAddress != 0)
2252 {
2253 rc = PDMDevHlpMMIORegister(pDevIns,
2254 pGlobals->u64PciConfigMMioAddress,
2255 pGlobals->u64PciConfigMMioLength,
2256 0,
2257 ich9pciMcfgMMIOWrite,
2258 ich9pciMcfgMMIORead,
2259 NULL /* fill */,
2260 "MCFG ranges");
2261 if (RT_FAILURE(rc))
2262 {
2263 AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2264 return rc;
2265 }
2266
2267 if (fGCEnabled)
2268 {
2269
2270 rc = PDMDevHlpMMIORegisterRC(pDevIns,
2271 pGlobals->u64PciConfigMMioAddress,
2272 pGlobals->u64PciConfigMMioLength,
2273 0,
2274 "ich9pciMcfgMMIOWrite",
2275 "ich9pciMcfgMMIORead",
2276 NULL /* fill */);
2277 if (RT_FAILURE(rc))
2278 {
2279 AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2280 return rc;
2281 }
2282 }
2283
2284
2285 if (fR0Enabled)
2286 {
2287
2288 rc = PDMDevHlpMMIORegisterR0(pDevIns,
2289 pGlobals->u64PciConfigMMioAddress,
2290 pGlobals->u64PciConfigMMioLength,
2291 0,
2292 "ich9pciMcfgMMIOWrite",
2293 "ich9pciMcfgMMIORead",
2294 NULL /* fill */);
2295 if (RT_FAILURE(rc))
2296 {
2297 AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2298 return rc;
2299 }
2300 }
2301 }
2302
2303 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2304 sizeof(*pBus) + 16*128, "pgm",
2305 NULL, NULL, NULL,
2306 NULL, ich9pciR3SaveExec, NULL,
2307 NULL, ich9pciR3LoadExec, NULL);
2308 if (RT_FAILURE(rc))
2309 return rc;
2310
2311
2312 /** @todo: other chipset devices shall be registered too */
2313 /** @todo: what to with bridges? */
2314
2315 PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2316
2317 return VINF_SUCCESS;
2318}
2319
2320static void ich9pciResetDevice(PPCIDEVICE pDev)
2321{
2322 pDev->config[VBOX_PCI_COMMAND] &= ~(VBOX_PCI_COMMAND_IO | VBOX_PCI_COMMAND_MEMORY |
2323 VBOX_PCI_COMMAND_MASTER);
2324
2325 if (!PCIIsPci2PciBridge(pDev))
2326 {
2327 PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2328 PCIDevSetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
2329 }
2330 /* Regions ? */
2331}
2332
2333
2334/**
2335 * @copydoc FNPDMDEVRESET
2336 */
2337static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2338{
2339 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2340 PPCIBUS pBus = &pGlobals->aPciBus;
2341
2342 /* Relocate RC pointers for the attached pci devices. */
2343 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2344 {
2345 if (pBus->apDevices[i])
2346 ich9pciResetDevice(pBus->apDevices[i]);
2347 }
2348}
2349
2350/**
2351 * @copydoc FNPDMDEVRELOCATE
2352 */
2353static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2354{
2355 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2356 PPCIBUS pBus = &pGlobals->aPciBus;
2357 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2358
2359 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2360 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2361
2362 /* Relocate RC pointers for the attached pci devices. */
2363 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2364 {
2365 if (pBus->apDevices[i])
2366 pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2367 }
2368
2369}
2370
2371/**
2372 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2373 */
2374static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2375 int iInstance,
2376 PCFGMNODE pCfg)
2377{
2378 int rc;
2379
2380 /*
2381 * Validate and read configuration.
2382 */
2383 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2384 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2385
2386 /* check if RC code is enabled. */
2387 bool fGCEnabled;
2388 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2389 if (RT_FAILURE(rc))
2390 return PDMDEV_SET_ERROR(pDevIns, rc,
2391 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2392
2393 /* check if R0 code is enabled. */
2394 bool fR0Enabled;
2395 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2396 if (RT_FAILURE(rc))
2397 return PDMDEV_SET_ERROR(pDevIns, rc,
2398 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2399 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2400
2401 /*
2402 * Init data and register the PCI bus.
2403 */
2404 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2405 pBus->pDevInsR3 = pDevIns;
2406 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2407 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2408 pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->apDevices));
2409
2410 PDMPCIBUSREG PciBusReg;
2411 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2412 PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2413 PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2414 PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2415 PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2416 PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2417 PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2418 PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2419 PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2420 PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2421 PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2422 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2423 if (RT_FAILURE(rc))
2424 return PDMDEV_SET_ERROR(pDevIns, rc,
2425 N_("Failed to register ourselves as a PCI Bus"));
2426 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2427 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2428 N_("PCI helper version mismatch; got %#x expected %#x"),
2429 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2430
2431 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2432 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2433
2434 /*
2435 * Fill in PCI configs and add them to the bus.
2436 */
2437 PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2438 PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2439 PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2440 PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2441 PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2442 PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2443 PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2444 PCIDevSetCommand( &pBus->aPciDev, 0x00);
2445 PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2446 PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2447
2448 /*
2449 * This device does not generate interrupts. Interrupt delivery from
2450 * devices attached to the bus is unaffected.
2451 */
2452 PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2453
2454 pBus->aPciDev.pDevIns = pDevIns;
2455
2456 /* Bridge-specific data */
2457 PCISetPci2PciBridge(&pBus->aPciDev);
2458 pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2459 pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2460
2461 /*
2462 * Register this PCI bridge. The called function will take care on which bus we will get registered.
2463 */
2464 rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2465 if (RT_FAILURE(rc))
2466 return rc;
2467
2468 /*
2469 * The iBus property doesn't really represent the bus number
2470 * because the guest and the BIOS can choose different bus numbers
2471 * for them.
2472 * The bus number is mainly for the setIrq function to indicate
2473 * when the host bus is reached which will have iBus = 0.
2474 * Thathswhy the + 1.
2475 */
2476 pBus->iBus = iInstance + 1;
2477
2478 /*
2479 * Register SSM handlers. We use the same saved state version as for the host bridge
2480 * to make changes easier.
2481 */
2482 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2483 sizeof(*pBus) + 16*128,
2484 "pgm" /* before */,
2485 NULL, NULL, NULL,
2486 NULL, ich9pcibridgeR3SaveExec, NULL,
2487 NULL, ich9pcibridgeR3LoadExec, NULL);
2488 if (RT_FAILURE(rc))
2489 return rc;
2490
2491
2492 return VINF_SUCCESS;
2493}
2494
2495/**
2496 * @copydoc FNPDMDEVRESET
2497 */
2498static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
2499{
2500 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2501
2502 /* Reset config space to default values. */
2503 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2504 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2505 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2506}
2507
2508
2509/**
2510 * @copydoc FNPDMDEVRELOCATE
2511 */
2512static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2513{
2514 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2515 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2516
2517 /* Relocate RC pointers for the attached pci devices. */
2518 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2519 {
2520 if (pBus->apDevices[i])
2521 pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2522 }
2523
2524}
2525
2526/**
2527 * The PCI bus device registration structure.
2528 */
2529const PDMDEVREG g_DevicePciIch9 =
2530{
2531 /* u32Version */
2532 PDM_DEVREG_VERSION,
2533 /* szName */
2534 "ich9pci",
2535 /* szRCMod */
2536 "VBoxDDGC.gc",
2537 /* szR0Mod */
2538 "VBoxDDR0.r0",
2539 /* pszDescription */
2540 "ICH9 PCI bridge",
2541 /* fFlags */
2542 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2543 /* fClass */
2544 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
2545 /* cMaxInstances */
2546 1,
2547 /* cbInstance */
2548 sizeof(PCIGLOBALS),
2549 /* pfnConstruct */
2550 ich9pciConstruct,
2551 /* pfnDestruct */
2552 NULL,
2553 /* pfnRelocate */
2554 ich9pciRelocate,
2555 /* pfnIOCtl */
2556 NULL,
2557 /* pfnPowerOn */
2558 NULL,
2559 /* pfnReset */
2560 ich9pciReset,
2561 /* pfnSuspend */
2562 NULL,
2563 /* pfnResume */
2564 NULL,
2565 /* pfnAttach */
2566 NULL,
2567 /* pfnDetach */
2568 NULL,
2569 /* pfnQueryInterface */
2570 NULL,
2571 /* pfnInitComplete */
2572 NULL,
2573 /* pfnPowerOff */
2574 NULL,
2575 /* pfnSoftReset */
2576 NULL,
2577 /* u32VersionEnd */
2578 PDM_DEVREG_VERSION
2579};
2580
2581/**
2582 * The device registration structure
2583 * for the PCI-to-PCI bridge.
2584 */
2585const PDMDEVREG g_DevicePciIch9Bridge =
2586{
2587 /* u32Version */
2588 PDM_DEVREG_VERSION,
2589 /* szName */
2590 "ich9pcibridge",
2591 /* szRCMod */
2592 "VBoxDDGC.gc",
2593 /* szR0Mod */
2594 "VBoxDDR0.r0",
2595 /* pszDescription */
2596 "ICH9 PCI to PCI bridge",
2597 /* fFlags */
2598 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2599 /* fClass */
2600 PDM_DEVREG_CLASS_BUS_PCI,
2601 /* cMaxInstances */
2602 ~0,
2603 /* cbInstance */
2604 sizeof(PCIBUS),
2605 /* pfnConstruct */
2606 ich9pcibridgeConstruct,
2607 /* pfnDestruct */
2608 NULL,
2609 /* pfnRelocate */
2610 ich9pcibridgeRelocate,
2611 /* pfnIOCtl */
2612 NULL,
2613 /* pfnPowerOn */
2614 NULL,
2615 /* pfnReset */
2616 ich9pcibridgeReset,
2617 /* pfnSuspend */
2618 NULL,
2619 /* pfnResume */
2620 NULL,
2621 /* pfnAttach */
2622 NULL,
2623 /* pfnDetach */
2624 NULL,
2625 /* pfnQueryInterface */
2626 NULL,
2627 /* pfnInitComplete */
2628 NULL,
2629 /* pfnPowerOff */
2630 NULL,
2631 /* pfnSoftReset */
2632 NULL,
2633 /* u32VersionEnd */
2634 PDM_DEVREG_VERSION
2635};
2636
2637#endif /* IN_RING3 */
2638#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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