DevPciIch9.cpp@ 32861

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PCI: MSI per-vector masking, saved states
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1	/* $Id: DevPciIch9.cpp 32860 2010-10-01 11:30:38Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/msi.h>
26	#include <VBox/pdmdev.h>
27	#include <iprt/asm.h>
28	#include <iprt/assert.h>
29	#include <iprt/string.h>
30
31	#include "../Builtins.h"
32
33	#include "MsiCommon.h"
34
35	/**
36	* PCI Bus instance.
37	*/
38	typedef struct PCIBus
39	{
40	/** Bus number. */
41	int32_t iBus;
42	/** Number of bridges attached to the bus. */
43	uint32_t cBridges;
44
45	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
46	R3PTRTYPE(PPCIDEVICE) apDevices[256];
47	/** Array of bridges attached to the bus. */
48	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
49
50	/** R3 pointer to the device instance. */
51	PPDMDEVINSR3 pDevInsR3;
52	/** Pointer to the PCI R3 helpers. */
53	PCPDMPCIHLPR3 pPciHlpR3;
54
55	/** R0 pointer to the device instance. */
56	PPDMDEVINSR0 pDevInsR0;
57	/** Pointer to the PCI R0 helpers. */
58	PCPDMPCIHLPR0 pPciHlpR0;
59
60	/** RC pointer to the device instance. */
61	PPDMDEVINSRC pDevInsRC;
62	/** Pointer to the PCI RC helpers. */
63	PCPDMPCIHLPRC pPciHlpRC;
64
65	/** The PCI device for the PCI bridge. */
66	PCIDEVICE aPciDev;
67
68	} PCIBUS, *PPCIBUS;
69
70
71	/** @def PCI_IRQ_PINS
72	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
73	*/
74	#define PCI_IRQ_PINS 4
75
76	/** @def PCI_APIC_IRQ_PINS
77	* Number of pins for interrupts if the APIC is used.
78	*/
79	#define PCI_APIC_IRQ_PINS 8
80
81	/**
82	* PCI Globals - This is the host-to-pci bridge and the root bus.
83	*/
84	typedef struct
85	{
86	/** R3 pointer to the device instance. */
87	PPDMDEVINSR3 pDevInsR3;
88	/** R0 pointer to the device instance. */
89	PPDMDEVINSR0 pDevInsR0;
90	/** RC pointer to the device instance. */
91	PPDMDEVINSRC pDevInsRC;
92
93	#if HC_ARCH_BITS == 64
94	uint32_t Alignment0;
95	#endif
96
97	/** I/O APIC irq levels */
98	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
99
100	#if 1 /* Will be moved into the BIOS soon. */
101	/** The next I/O port address which the PCI BIOS will use. */
102	uint32_t uPciBiosIo;
103	/** The next MMIO address which the PCI BIOS will use. */
104	uint32_t uPciBiosMmio;
105	/** Actual bus number. */
106	uint8_t uBus;
107	#endif
108	/* Physical address of PCI config space MMIO region */
109	uint64_t u64PciConfigMMioAddress;
110	/* Length of PCI config space MMIO region */
111	uint64_t u64PciConfigMMioLength;
112
113
114	/** Config register. */
115	uint32_t uConfigReg;
116
117	/** PCI bus which is attached to the host-to-PCI bridge. */
118	PCIBUS aPciBus;
119
120	} PCIGLOBALS, *PPCIGLOBALS;
121
122
123	typedef struct {
124	uint8_t iBus;
125	uint8_t iDeviceFunc;
126	uint16_t iRegister;
127	} PciAddress;
128
129	/*******************************************************************************
130	* Defined Constants And Macros *
131	*******************************************************************************/
132
133	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
134	* Saved state version of the ICH9 PCI bus device.
135	*/
136	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
137	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
138	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
139
140	/** Converts a bus instance pointer to a device instance pointer. */
141	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
142	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
143	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
144	/** Converts a device instance pointer to a PCIBUS pointer. */
145	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
146	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
147	*/
148	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
149
150
151	/** @def PCI_LOCK
152	* Acquires the PDM lock. This is a NOP if locking is disabled. */
153	/** @def PCI_UNLOCK
154	* Releases the PDM lock. This is a NOP if locking is disabled. */
155	#define PCI_LOCK(pDevIns, rc) \
156	do { \
157	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
158	if (rc2 != VINF_SUCCESS) \
159	return rc2; \
160	} while (0)
161	#define PCI_UNLOCK(pDevIns) \
162	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
163
164	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
165
166	RT_C_DECLS_BEGIN
167
168	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
169	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
170	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
171	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
172	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
173	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
174	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
175	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
176
177	RT_C_DECLS_END
178
179	/* Prototypes */
180	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
181	#ifdef IN_RING3
182	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
183	static void ich9pciUpdateMappings(PCIDevice *pDev);
184	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
185	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
186	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
187	#endif
188
189	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
190	// mapping, we take n=6 approach
191	DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
192	{
193	GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
194	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<8) - 1);
195	pPciAddr->iDeviceFunc = (GCPhysAddr >> 15) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
196	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
197	}
198
199	DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
200	{
201	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
202	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
203	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
204	}
205
206	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
207	{
208	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
209	}
210
211	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
212	{
213	/*
214	* The PCI-to-PCI bridge specification defines how the interrupt pins
215	* are routed from the secondary to the primary bus (see chapter 9).
216	* iIrq gives the interrupt pin the pci device asserted.
217	* We change iIrq here according to the spec and call the SetIrq function
218	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
219	*/
220	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
221	PPCIDEVICE pPciDevBus = pPciDev;
222	int iIrqPinBridge = iIrq;
223	uint8_t uDevFnBridge = 0;
224
225	/* Walk the chain until we reach the host bus. */
226	do
227	{
228	uDevFnBridge = pBus->aPciDev.devfn;
229	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
230
231	/* Get the parent. */
232	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
233	pPciDevBus = &pBus->aPciDev;
234	} while (pBus->iBus != 0);
235
236	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
237	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
238	}
239
240	/**
241	* Port I/O Handler for PCI address OUT operations.
242	*
243	* @returns VBox status code.
244	*
245	* @param pDevIns The device instance.
246	* @param pvUser User argument - ignored.
247	* @param uPort Port number used for the OUT operation.
248	* @param u32 The value to output.
249	* @param cb The value size in bytes.
250	*/
251	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
252	{
253	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
254	NOREF(pvUser);
255	if (cb == 4)
256	{
257	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
258	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
259	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
260	PCI_UNLOCK(pDevIns);
261	}
262	return VINF_SUCCESS;
263	}
264
265	/**
266	* Port I/O Handler for PCI address IN operations.
267	*
268	* @returns VBox status code.
269	*
270	* @param pDevIns The device instance.
271	* @param pvUser User argument - ignored.
272	* @param uPort Port number used for the IN operation.
273	* @param pu32 Where to store the result.
274	* @param cb Number of bytes read.
275	*/
276	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
277	{
278	NOREF(pvUser);
279	if (cb == 4)
280	{
281	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
282	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
283	*pu32 = pThis->uConfigReg;
284	PCI_UNLOCK(pDevIns);
285	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
286	return VINF_SUCCESS;
287	}
288
289	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
290
291	return VERR_IOM_IOPORT_UNUSED;
292	}
293
294	static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
295	{
296
297	if (pAddr->iRegister > 0xff)
298	{
299	LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
300	return 0;
301	}
302
303	if (pAddr->iBus != 0)
304	{
305	if (pGlobals->aPciBus.cBridges)
306	{
307	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
308	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
309	if (pBridgeDevice)
310	{
311	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
312	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);
313	}
314	#else
315	return VINF_IOM_HC_IOPORT_WRITE;
316	#endif
317	}
318	}
319	else
320	{
321	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
322	{
323	#ifdef IN_RING3
324	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
325	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));
326	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);
327	#else
328	return VINF_IOM_HC_IOPORT_WRITE;
329	#endif
330	}
331	}
332	return VINF_SUCCESS;
333	}
334
335	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
336	{
337	PciAddress aPciAddr;
338
339	Log(("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
340
341	if (!(pGlobals->uConfigReg & (1 << 31)))
342	return VINF_SUCCESS;
343
344	if ((pGlobals->uConfigReg & 0x3) != 0)
345	return VINF_SUCCESS;
346
347	/* Compute destination device */
348	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
349
350	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
351	}
352
353	/**
354	* Port I/O Handler for PCI data OUT operations.
355	*
356	* @returns VBox status code.
357	*
358	* @param pDevIns The device instance.
359	* @param pvUser User argument - ignored.
360	* @param uPort Port number used for the OUT operation.
361	* @param u32 The value to output.
362	* @param cb The value size in bytes.
363	*/
364	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
365	{
366	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
367	NOREF(pvUser);
368	int rc = VINF_SUCCESS;
369	if (!(Port % cb))
370	{
371	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
372	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
373	PCI_UNLOCK(pDevIns);
374	}
375	else
376	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
377	return rc;
378	}
379
380	static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
381	{
382	if (pPciAddr->iRegister > 0xff)
383	{
384	LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
385	*pu32 = 0;
386	return 0;
387	}
388
389
390	if (pPciAddr->iBus != 0)
391	{
392	if (pGlobals->aPciBus.cBridges)
393	{
394	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
395	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
396	if (pBridgeDevice)
397	{
398	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
399	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);
400	}
401	#else
402	return VINF_IOM_HC_IOPORT_READ;
403	#endif
404	}
405	}
406	else
407	{
408	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
409	{
410	#ifdef IN_RING3
411	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
412	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, len);
413	Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
414	#else
415	return VINF_IOM_HC_IOPORT_READ;
416	#endif
417	}
418	}
419
420	return VINF_SUCCESS;
421	}
422
423
424	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
425	{
426	PciAddress aPciAddr;
427
428	*pu32 = 0xffffffff;
429
430	if (!(pGlobals->uConfigReg & (1 << 31)))
431	return VINF_SUCCESS;
432
433	if ((pGlobals->uConfigReg & 0x3) != 0)
434	return VINF_SUCCESS;
435
436	/* Compute destination device */
437	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
438
439	return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32);
440	}
441
442	/**
443	* Port I/O Handler for PCI data IN operations.
444	*
445	* @returns VBox status code.
446	*
447	* @param pDevIns The device instance.
448	* @param pvUser User argument - ignored.
449	* @param uPort Port number used for the IN operation.
450	* @param pu32 Where to store the result.
451	* @param cb Number of bytes read.
452	*/
453	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
454	{
455	NOREF(pvUser);
456	if (!(Port % cb))
457	{
458	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
459	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
460	PCI_UNLOCK(pDevIns);
461	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
462	return rc;
463	}
464	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
465	return VERR_IOM_IOPORT_UNUSED;
466	}
467
468	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
469	static inline int ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
470	{
471	return (irq_num + uSlot) & 7;
472	}
473
474	/* Add one more level up request on APIC input line */
475	static inline void ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
476	{
477	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
478	}
479
480	/* Remove one level up request on APIC input line */
481	static inline void ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
482	{
483	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
484	}
485
486	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
487	{
488	/* This is only allowed to be called with a pointer to the root bus. */
489	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
490
491	if (iForcedIrq == -1)
492	{
493	int apic_irq, apic_level;
494	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
495	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
496
497	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
498	ich9pciApicLevelUp(pGlobals, irq_num);
499	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
500	ich9pciApicLevelDown(pGlobals, irq_num);
501
502	apic_irq = irq_num + 0x10;
503	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
504	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
505	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
506	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
507
508	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
509	{
510	/**
511	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
512	* PDM_IRQ_LEVEL_HIGH bit set
513	*/
514	ich9pciApicLevelDown(pGlobals, irq_num);
515	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
516	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
517	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
518	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
519	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
520	}
521	} else {
522	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
523	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
524	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
525	}
526	}
527
528	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
529	{
530	if (MSIIsEnabled(pPciDev))
531	{
532	Log2(("Raise a MSI interrupt: %d\n", iIrq));
533	/* We only trigger MSI on level up, as technically it's matching flip-flop best (maybe even assert that level == PDM_IRQ_LEVEL_FLIP_FLOP) */
534	if ((iLevel & PDM_IRQ_LEVEL_HIGH) != 0)
535	MSINotify(pGlobals->aPciBus.CTX_SUFF(pDevIns), pPciDev, iIrq);
536	return;
537	}
538
539	PPCIBUS pBus = &pGlobals->aPciBus;
540	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
541
542	/* Check if the state changed. */
543	if (pPciDev->Int.s.uIrqPinState != iLevel)
544	{
545	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
546
547	/* Send interrupt to I/O APIC only now. */
548	if (fIsAcpiDevice)
549	/*
550	* ACPI needs special treatment since SCI is hardwired and
551	* should not be affected by PCI IRQ routing tables at the
552	* same time SCI IRQ is shared in PCI sense hence this
553	* kludge (i.e. we fetch the hardwired value from ACPIs
554	* PCI device configuration space).
555	*/
556	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
557	else
558	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
559	}
560	}
561
562	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
563	{
564	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
565	PciAddress aDest;
566	uint32_t u32 = 0;
567
568	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
569
570	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
571	switch (cb)
572	{
573	case 1:
574	u32 = (uint8_t)pv;
575	break;
576	case 2:
577	u32 = (uint16_t)pv;
578	break;
579	case 4:
580	u32 = (uint32_t)pv;
581	break;
582	default:
583	Assert(false);
584	break;
585	}
586	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
587	PCI_UNLOCK(pDevIns);
588
589	return rc;
590	}
591
592	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
593	{
594	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
595	PciAddress aDest;
596	uint32_t rv = 0;
597
598	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
599
600	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
601	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv);
602	if (rc == VINF_SUCCESS)
603	{
604	switch (cb)
605	{
606	case 1:
607	(uint8_t)pv = (uint8_t)rv;
608	break;
609	case 2:
610	(uint16_t)pv = (uint16_t)rv;
611	break;
612	case 4:
613	(uint32_t)pv = (uint32_t)rv;
614	break;
615	default:
616	Assert(false);
617	break;
618	}
619	}
620	PCI_UNLOCK(pDevIns);
621
622	return rc;
623	}
624
625	#ifdef IN_RING3
626
627	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
628	{
629	/* Search for a fitting bridge. */
630	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
631	{
632	/*
633	* Examine secondary and subordinate bus number.
634	* If the target bus is in the range we pass the request on to the bridge.
635	*/
636	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
637	AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
638	("Device is not a PCI bridge but on the list of PCI bridges\n"));
639
640	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
641	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
642	return pBridgeTemp;
643	}
644
645	/* Nothing found. */
646	return NULL;
647	}
648
649	static inline uint32_t ich9pciGetRegionReg(int iRegion)
650	{
651	return (iRegion == PCI_ROM_SLOT) ?
652	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
653	}
654
655	#define INVALID_PCI_ADDRESS ~0U
656
657	static void ich9pciUpdateMappings(PCIDevice* pDev)
658	{
659	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
660	uint32_t uLast, uNew;
661
662	int iCmd = PCIDevGetCommand(pDev);
663	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
664	{
665	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
666	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
667	int32_t iRegionSize = pRegion->size;
668	int rc;
669
670	if (iRegionSize == 0)
671	continue;
672
673	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
674	{
675	/* port IO region */
676	if (iCmd & PCI_COMMAND_IOACCESS)
677	{
678	/* IO access allowed */
679	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
680	uNew &= ~(iRegionSize - 1);
681	uLast = uNew + iRegionSize - 1;
682	/* only 64K ioports on PC */
683	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
684	uNew = INVALID_PCI_ADDRESS;
685	} else
686	uNew = INVALID_PCI_ADDRESS;
687	}
688	else
689	{
690	/* MMIO region */
691	if (iCmd & PCI_COMMAND_MEMACCESS)
692	{
693	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
694	/* the ROM slot has a specific enable bit */
695	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
696	uNew = INVALID_PCI_ADDRESS;
697	else
698	{
699	uNew &= ~(iRegionSize - 1);
700	uLast = uNew + iRegionSize - 1;
701	/* NOTE: we do not support wrapping */
702	/* XXX: as we cannot support really dynamic
703	mappings, we handle specific values as invalid
704	mappings. */
705	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
706	uNew = INVALID_PCI_ADDRESS;
707	}
708	} else
709	uNew = INVALID_PCI_ADDRESS;
710	}
711	/* now do the real mapping */
712	if (uNew != pRegion->addr)
713	{
714	if (pRegion->addr != INVALID_PCI_ADDRESS)
715	{
716	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
717	{
718	/* Port IO */
719	int devclass;
720	/* NOTE: specific hack for IDE in PC case:
721	only one byte must be mapped. */
722	/// @todo: do we need it?
723	devclass = pDev->config[0x0a] \| (pDev->config[0x0b] << 8);
724	if (devclass == 0x0101 && iRegionSize == 4)
725	{
726	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr + 2, 1);
727	AssertRC(rc);
728	}
729	else
730	{
731	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
732	AssertRC(rc);
733	}
734	}
735	else
736	{
737	RTGCPHYS GCPhysBase = pRegion->addr;
738	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
739	{
740	/* unmap it. */
741	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
742	AssertRC(rc);
743	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
744	}
745	else
746	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
747	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
748	}
749	}
750	pRegion->addr = uNew;
751	if (pRegion->addr != INVALID_PCI_ADDRESS)
752	{
753	/* finally, map the region */
754	rc = pRegion->map_func(pDev, iRegion,
755	pRegion->addr, pRegion->size,
756	(PCIADDRESSSPACE)(pRegion->type));
757	AssertRC(rc);
758	}
759	}
760	}
761	}
762
763	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
764	{
765	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
766
767	/*
768	* Check input.
769	*/
770	if ( !pszName
771	\|\| !pPciDev
772	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
773	)
774	{
775	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
776	return VERR_INVALID_PARAMETER;
777	}
778
779	/*
780	* Register the device.
781	*/
782	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
783	}
784
785
786	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
787	{
788	return MSIInit(pPciDev, pMsiReg);
789	}
790
791
792	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
793	{
794
795	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
796
797	/*
798	* Check input.
799	*/
800	if ( !pszName
801	\|\| !pPciDev
802	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
803	{
804	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
805	return VERR_INVALID_PARAMETER;
806	}
807
808	/*
809	* Register the device.
810	*/
811	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
812	}
813
814	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
815	{
816	/*
817	* Validate.
818	*/
819	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
820	\|\| enmType == PCI_ADDRESS_SPACE_IO
821	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
822	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
823	VERR_INVALID_PARAMETER);
824	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
825	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
826	VERR_INVALID_PARAMETER);
827	int iLastSet = ASMBitLastSetU32(cbRegion);
828	AssertMsgReturn( iLastSet != 0
829	&& RT_BIT_32(iLastSet - 1) == cbRegion,
830	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
831	VERR_INVALID_PARAMETER);
832
833	/*
834	* Register the I/O region.
835	*/
836	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
837	pRegion->addr = INVALID_PCI_ADDRESS;
838	pRegion->size = cbRegion;
839	pRegion->type = enmType;
840	pRegion->map_func = pfnCallback;
841
842	/* Set type in the config space. */
843	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
844	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
845	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
846	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
847
848	return VINF_SUCCESS;
849	}
850
851	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
852	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
853	{
854	if (ppfnReadOld)
855	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
856	pPciDev->Int.s.pfnConfigRead = pfnRead;
857
858	if (ppfnWriteOld)
859	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
860	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
861	}
862
863	/**
864	* Saves a state of the PCI device.
865	*
866	* @returns VBox status code.
867	* @param pDevIns Device instance of the PCI Bus.
868	* @param pPciDev Pointer to PCI device.
869	* @param pSSM The handle to save the state to.
870	*/
871	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
872	{
873	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
874	}
875
876	static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
877	{
878	/*
879	* Iterate thru all the devices.
880	*/
881	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
882	{
883	PPCIDEVICE pDev = pBus->apDevices[i];
884	if (pDev)
885	{
886	/* Device position */
887	SSMR3PutU32(pSSM, i);
888	/* PCI config registers */
889	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
890
891	/* Device flags */
892	int rc = SSMR3PutU32(pSSM, pDev->Int.s.uFlags);
893	if (RT_FAILURE(rc))
894	return rc;
895
896	/* IRQ pin state */
897	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
898	if (RT_FAILURE(rc))
899	return rc;
900
901	/* MSI info */
902	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
903	if (RT_FAILURE(rc))
904	return rc;
905	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
906	if (RT_FAILURE(rc))
907	return rc;
908
909	/* MSI-X info */
910	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
911	if (RT_FAILURE(rc))
912	return rc;
913	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
914	if (RT_FAILURE(rc))
915	return rc;
916	}
917	}
918	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
919	}
920
921	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
922	{
923	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
924
925	/*
926	* Bus state data.
927	*/
928	SSMR3PutU32(pSSM, pThis->uConfigReg);
929
930	/*
931	* Save IRQ states.
932	*/
933	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
934	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
935
936	SSMR3PutU32(pSSM, ~0); /* separator */
937
938	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
939	}
940
941
942	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
943	{
944	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
945	return ich9pciR3CommonSaveExec(pThis, pSSM);
946	}
947
948
949	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
950	{
951	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
952
953	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
954
955	/* If the current bus is not the target bus search for the bus which contains the device. */
956	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
957	{
958	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
959	if (pBridgeDevice)
960	{
961	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
962	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
963	}
964	}
965	else
966	{
967	/* This is the target bus, pass the write to the device. */
968	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
969	if (pPciDev)
970	{
971	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
972	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
973	}
974	}
975	}
976
977	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
978	{
979	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
980	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
981
982	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
983
984	/* If the current bus is not the target bus search for the bus which contains the device. */
985	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
986	{
987	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
988	if (pBridgeDevice)
989	{
990	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
991	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
992	}
993	}
994	else
995	{
996	/* This is the target bus, pass the read to the device. */
997	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
998	if (pPciDev)
999	{
1000	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1001	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1002	}
1003	}
1004
1005	return u32Value;
1006	}
1007
1008
1009	/**
1010	* Common routine for restoring the config registers of a PCI device.
1011	*
1012	* @param pDev The PCI device.
1013	* @param pbSrcConfig The configuration register values to be loaded.
1014	* @param fIsBridge Whether this is a bridge device or not.
1015	*/
1016	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1017	{
1018	/*
1019	* This table defines the fields for normal devices and bridge devices, and
1020	* the order in which they need to be restored.
1021	*/
1022	static const struct PciField
1023	{
1024	uint8_t off;
1025	uint8_t cb;
1026	uint8_t fWritable;
1027	uint8_t fBridge;
1028	const char *pszName;
1029	} s_aFields[] =
1030	{
1031	/* off,cb,fW,fB, pszName */
1032	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1033	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1034	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1035	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1036	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1037	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1038	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1039	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1040	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1041	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1042	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1043	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1044	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1045	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1046	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1047	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1048	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1049	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1050	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1051	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1052	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1053	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1054	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1055	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1056	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1057	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1058	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1059	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1060	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1061	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1062	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1063	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1064	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1065	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1066	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1067	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1068	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1069	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1070	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1071	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1072	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1073	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1074	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1075	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1076	/* The COMMAND register must come last as it requires the ADDRESS
1077	registers to be restored before we pretent to change it from 0 to
1078	whatever value the guest assigned it. */
1079	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1080	};
1081
1082	#ifdef RT_STRICT
1083	/* Check that we've got full register coverage. */
1084	uint32_t bmDevice[0x40 / 32];
1085	uint32_t bmBridge[0x40 / 32];
1086	RT_ZERO(bmDevice);
1087	RT_ZERO(bmBridge);
1088	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1089	{
1090	uint8_t off = s_aFields[i].off;
1091	uint8_t cb = s_aFields[i].cb;
1092	uint8_t f = s_aFields[i].fBridge;
1093	while (cb-- > 0)
1094	{
1095	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1096	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1097	if (f & 1) ASMBitSet(bmDevice, off);
1098	if (f & 2) ASMBitSet(bmBridge, off);
1099	off++;
1100	}
1101	}
1102	for (uint32_t off = 0; off < 0x40; off++)
1103	{
1104	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1105	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1106	}
1107	#endif
1108
1109	/*
1110	* Loop thru the fields covering the 64 bytes of standard registers.
1111	*/
1112	uint8_t const fBridge = fIsBridge ? 2 : 1;
1113	uint8_t *pbDstConfig = &pDev->config[0];
1114	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1115	if (s_aFields[i].fBridge & fBridge)
1116	{
1117	uint8_t const off = s_aFields[i].off;
1118	uint8_t const cb = s_aFields[i].cb;
1119	uint32_t u32Src;
1120	uint32_t u32Dst;
1121	switch (cb)
1122	{
1123	case 1:
1124	u32Src = pbSrcConfig[off];
1125	u32Dst = pbDstConfig[off];
1126	break;
1127	case 2:
1128	u32Src = (uint16_t const )&pbSrcConfig[off];
1129	u32Dst = (uint16_t const )&pbDstConfig[off];
1130	break;
1131	case 4:
1132	u32Src = (uint32_t const )&pbSrcConfig[off];
1133	u32Dst = (uint32_t const )&pbDstConfig[off];
1134	break;
1135	default:
1136	AssertFailed();
1137	continue;
1138	}
1139
1140	if ( u32Src != u32Dst
1141	\|\| off == VBOX_PCI_COMMAND)
1142	{
1143	if (u32Src != u32Dst)
1144	{
1145	if (!s_aFields[i].fWritable)
1146	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1147	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1148	else
1149	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1150	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1151	}
1152	if (off == VBOX_PCI_COMMAND)
1153	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1154	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1155	}
1156	}
1157
1158	/*
1159	* The device dependent registers.
1160	*
1161	* We will not use ConfigWrite here as we have no clue about the size
1162	* of the registers, so the device is responsible for correctly
1163	* restoring functionality governed by these registers.
1164	*/
1165	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1166	if (pbDstConfig[off] != pbSrcConfig[off])
1167	{
1168	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1169	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1170	pbDstConfig[off] = pbSrcConfig[off];
1171	}
1172	}
1173
1174	/**
1175	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1176	*
1177	* @returns VBox status code.
1178	* @param pBus The bus which data is being loaded.
1179	* @param pSSM The saved state handle.
1180	* @param uVersion The data version.
1181	* @param uPass The pass.
1182	*/
1183	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1184	{
1185	uint32_t u32;
1186	uint32_t i;
1187	int rc;
1188
1189	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1190
1191	/*
1192	* Iterate thru all the devices and write 0 to the COMMAND register so
1193	* that all the memory is unmapped before we start restoring the saved
1194	* mapping locations.
1195	*
1196	* The register value is restored afterwards so we can do proper
1197	* LogRels in pciR3CommonRestoreConfig.
1198	*/
1199	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1200	{
1201	PPCIDEVICE pDev = pBus->apDevices[i];
1202	if (pDev)
1203	{
1204	uint16_t u16 = PCIDevGetCommand(pDev);
1205	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1206	PCIDevSetCommand(pDev, u16);
1207	Assert(PCIDevGetCommand(pDev) == u16);
1208	}
1209	}
1210
1211	/*
1212	* Iterate all the devices.
1213	*/
1214	for (i = 0;; i++)
1215	{
1216	PCIDEVICE DevTmp;
1217	PPCIDEVICE pDev;
1218
1219	/* index / terminator */
1220	rc = SSMR3GetU32(pSSM, &u32);
1221	if (RT_FAILURE(rc))
1222	return rc;
1223	if (u32 == (uint32_t)~0)
1224	break;
1225	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1226	\|\| u32 < i)
1227	{
1228	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1229	return rc;
1230	}
1231
1232	/* skip forward to the device checking that no new devices are present. */
1233	for (; i < u32; i++)
1234	{
1235	pDev = pBus->apDevices[i];
1236	if (pDev)
1237	{
1238	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1239	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1240	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1241	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1242	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1243	}
1244	}
1245
1246	/* get the data */
1247	DevTmp.Int.s.uFlags = 0;
1248	DevTmp.Int.s.u8MsiCapOffset = 0;
1249	DevTmp.Int.s.u8MsiCapSize = 0;
1250	DevTmp.Int.s.u8MsixCapOffset = 0;
1251	DevTmp.Int.s.u8MsixCapSize = 0;
1252	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1253	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1254
1255	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.uFlags);
1256	if (RT_FAILURE(rc))
1257	return rc;
1258
1259	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1260	if (RT_FAILURE(rc))
1261	return rc;
1262
1263	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1264	if (RT_FAILURE(rc))
1265	return rc;
1266
1267	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1268	if (RT_FAILURE(rc))
1269	return rc;
1270
1271	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1272	if (RT_FAILURE(rc))
1273	return rc;
1274
1275	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1276	if (RT_FAILURE(rc))
1277	return rc;
1278
1279	/* check that it's still around. */
1280	pDev = pBus->apDevices[i];
1281	if (!pDev)
1282	{
1283	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1284	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1285	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1286	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1287	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1288	continue;
1289	}
1290
1291	/* match the vendor id assuming that this will never be changed. */
1292	if ( DevTmp.config[0] != pDev->config[0]
1293	\|\| DevTmp.config[1] != pDev->config[1])
1294	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1295	i, pDev->name, DevTmp.config, pDev->config);
1296
1297	/* commit the loaded device config. */
1298	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1299
1300	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1301	}
1302
1303	return VINF_SUCCESS;
1304	}
1305
1306	/**
1307	* Loads a saved PCI device state.
1308	*
1309	* @returns VBox status code.
1310	* @param pDevIns Device instance of the PCI Bus.
1311	* @param pPciDev Pointer to PCI device.
1312	* @param pSSM The handle to the saved state.
1313	*/
1314	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1315	{
1316	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1317	}
1318
1319	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1320	{
1321	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1322	PPCIBUS pBus = &pThis->aPciBus;
1323	uint32_t u32;
1324	int rc;
1325
1326	/* We ignore this version as there's no saved state with it anyway */
1327	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1328	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1329	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1330	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1331
1332	/*
1333	* Bus state data.
1334	*/
1335	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1336
1337	/*
1338	* Load IRQ states.
1339	*/
1340	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1341	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1342
1343	/* separator */
1344	rc = SSMR3GetU32(pSSM, &u32);
1345	if (RT_FAILURE(rc))
1346	return rc;
1347	if (u32 != (uint32_t)~0)
1348	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1349
1350	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1351	}
1352
1353	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1354	{
1355	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1356	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1357	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1358	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1359	}
1360
1361	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1362	{
1363	/* Set destination address */
1364	/// @todo: device locking?
1365	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
1366	(uDevFn << 8) \| (addr & ~3);
1367	uint32_t u32Val;
1368	int rc = ich9pciDataRead(pGlobals, addr & 3, len, &u32Val);
1369	AssertRC(rc);
1370	switch (len)
1371	{
1372	case 1:
1373	u32Val &= 0xff;
1374	break;
1375	case 2:
1376	u32Val &= 0xffff;
1377	break;
1378	}
1379	return u32Val;
1380	}
1381
1382	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1383	{
1384	/* Set destination address */
1385	/// @todo: device locking?
1386	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
1387	(uDevFn << 8) \| addr;
1388	ich9pciDataWrite(pGlobals, 0, val, len);
1389	}
1390
1391	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1392	{
1393	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1394
1395	/* Read memory type first. */
1396	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1397	/* Read command register. */
1398	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1399
1400	if ( iRegion == PCI_ROM_SLOT )
1401	uCmd \|= PCI_COMMAND_MEMACCESS;
1402	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1403	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1404	else /* The region is MMIO. */
1405	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1406
1407	/* Write address of the device. */
1408	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1409
1410	/* enable memory mappings */
1411	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1412	}
1413
1414
1415	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1416	{
1417	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1418	/* Temporary until we know how many other bridges are behind this one. */
1419	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1420
1421	/* Add position of this bridge into the array. */
1422	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1423
1424	/*
1425	* The I/O range for the bridge must be aligned to a 4KB boundary.
1426	* This does not change anything really as the access to the device is not going
1427	* through the bridge but we want to be compliant to the spec.
1428	*/
1429	if ((pGlobals->uPciBiosIo % 4096) != 0)
1430	{
1431	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1432	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1433	}
1434	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1435
1436	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1437	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1438	{
1439	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1440	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1441	}
1442	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1443
1444	/* Save values to compare later to. */
1445	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1446	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1447
1448	/* Init devices behind the bridge and possibly other bridges as well. */
1449	for (int iDev = 0; iDev <= 255; iDev++)
1450	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1451
1452	/* The number of bridges behind the this one is now available. */
1453	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1454
1455	/*
1456	* Set I/O limit register. If there is no device with I/O space behind the bridge
1457	* we set a lower value than in the base register.
1458	* The result with a real bridge is that no I/O transactions are passed to the secondary
1459	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1460	*/
1461	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1462	{
1463	/* The upper boundary must be one byte less than a 4KB boundary. */
1464	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1465	}
1466
1467	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1468
1469	/* Same with the MMIO limit register but with 1MB boundary here. */
1470	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1471	{
1472	/* The upper boundary must be one byte less than a 1MB boundary. */
1473	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1474	}
1475	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1476
1477	/*
1478	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1479	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1480	* the base register than in the limit register.
1481	*/
1482	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1483	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1484	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1485	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1486	}
1487
1488	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1489	{
1490	uint32_t *paddr;
1491	uint16_t uDevClass, uVendor, uDevice;
1492	uint8_t uCmd;
1493
1494	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1495	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1496	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1497
1498	/* If device is present */
1499	if (uVendor == 0xffff)
1500	return;
1501
1502	switch (uDevClass)
1503	{
1504	case 0x0101:
1505	/* IDE controller */
1506	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1507	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1508	goto default_map;
1509	break;
1510	case 0x0300:
1511	/* VGA controller */
1512	if (uVendor != 0x80ee)
1513	goto default_map;
1514	/* VGA: map frame buffer to default Bochs VBE address */
1515	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1516	/*
1517	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1518	* only the framebuffer (i.e., a memory region) is explicitly registered via
1519	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1520	*/
1521	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1522	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1523	/* Enable I/O space access. */
1524	uCmd \| PCI_COMMAND_IOACCESS,
1525	1);
1526	break;
1527	case 0x0800:
1528	/* PIC */
1529	if (uVendor == 0x1014)
1530	{
1531	/* IBM */
1532	if (uDevice == 0x0046 \|\| uDevice == 0xFFFF)
1533	/* MPIC & MPIC2 */
1534	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1535	}
1536	break;
1537	case 0xff00:
1538	if ((uVendor == 0x0106b)
1539	&& (uDevice == 0x0017 \|\| uDevice == 0x0022))
1540	{
1541	/* macio bridge */
1542	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000);
1543	}
1544	break;
1545	case 0x0604:
1546	/* PCI-to-PCI bridge. */
1547	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1548
1549	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1550	pGlobals->uBus++;
1551	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1552	break;
1553	default:
1554	default_map:
1555	{
1556	/* default memory mappings */
1557	/*
1558	* We ignore ROM region here.
1559	*/
1560	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1561	{
1562	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1563
1564	/* Calculate size. */
1565	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1566	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1567	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1568	/* Clear resource information depending on resource type. */
1569	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1570	u32Size &= ~(0x01);
1571	else /* MMIO */
1572	u32Size &= ~(0x0f);
1573
1574	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1575	/*
1576	* Invert all bits and add 1 to get size of the region.
1577	* (From PCI implementation note)
1578	*/
1579	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1580	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1581	else
1582	u32Size = (~u32Size) + 1;
1583
1584	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1585
1586	if (u32Size)
1587	{
1588	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1589	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1590	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1591	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1592	*paddr += u32Size;
1593	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1594	}
1595	}
1596	break;
1597	}
1598	}
1599
1600	/* map the interrupt */
1601	uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1602	if (uPin != 0)
1603	{
1604	uint8_t uBridgeDevFn = uDevFn;
1605	uPin--;
1606
1607	/* We need to go up to the host bus to see which irq this device will assert there. */
1608	while (cBridgeDepth != 0)
1609	{
1610	/* Get the pin the device would assert on the bridge. */
1611	uPin = ((uBridgeDevFn >> 3) + uPin) & 3;
1612	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1613	cBridgeDepth--;
1614	}
1615	#if 0
1616	uPin = pci_slot_get_pirq(uDevFn, pin);
1617	pic_irq = pci_irqs[pin];
1618	ich9pciConfigWrite(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1619	#endif
1620	}
1621	}
1622
1623	static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 };
1624
1625	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1626	{
1627	unsigned i;
1628	uint8_t elcr[2] = {0, 0};
1629	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1630	PVM pVM = PDMDevHlpGetVM(pDevIns);
1631	Assert(pVM);
1632
1633	/*
1634	* Set the start addresses.
1635	*/
1636	pGlobals->uPciBiosIo = 0xd000;
1637	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1638	pGlobals->uBus = 0;
1639
1640	/*
1641	* Activate IRQ mappings.
1642	*/
1643	for (i = 0; i < 4; i++)
1644	{
1645	uint8_t irq = auPciIrqs[i];
1646	/* Set to trigger level. */
1647	elcr[irq >> 3] \|= (1 << (irq & 7));
1648	}
1649
1650	/* Tell to the PIC. */
1651	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1652	if (rcStrict == VINF_SUCCESS)
1653	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1654	if (rcStrict != VINF_SUCCESS)
1655	{
1656	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1657	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1658	}
1659
1660	/*
1661	* Init the devices.
1662	*/
1663	for (i = 0; i < 256; i++)
1664	{
1665	uint8_t aBridgePositions[256];
1666
1667	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1668	Log2(("PCI: Initializing device %d (%#x)\n",
1669	i, 0x80000000 \| (i << 8)));
1670	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1671	}
1672
1673	return VINF_SUCCESS;
1674	}
1675
1676	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1677	{
1678	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1679	{
1680	AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1681	}
1682
1683	if ( PCIIsMsiCapable(aDev)
1684	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1685	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1686	)
1687	{
1688	return MSIPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1689	}
1690
1691	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1692	0);
1693	switch (len)
1694	{
1695	case 1:
1696	return PCIDevGetByte(aDev, u32Address);
1697	case 2:
1698	return PCIDevGetWord(aDev, u32Address);
1699	default:
1700	case 4:
1701	return PCIDevGetDWord(aDev, u32Address);
1702	}
1703	}
1704
1705
1706	/**
1707	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1708	* registers and their writability policy.
1709	*/
1710	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1711	uint32_t val, unsigned len)
1712	{
1713	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1714	{
1715	AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1716	}
1717
1718	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1719
1720	if ( PCIIsMsiCapable(aDev)
1721	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1722	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1723	)
1724	{
1725	MSIPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, val, len);
1726	return;
1727	}
1728
1729
1730	/* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
1731	while ( len == 4
1732	&& ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
1733	&& u32Address < VBOX_PCI_BASE_ADDRESS_0 + 6 * 4)
1734	\|\| ( u32Address >= VBOX_PCI_ROM_ADDRESS
1735	&& u32Address < VBOX_PCI_ROM_ADDRESS+4)
1736	)
1737	)
1738	{
1739	PCIIORegion *pRegion;
1740	int reg, regionSize;
1741
1742	reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1743	pRegion = &aDev->Int.s.aIORegions[reg];
1744	regionSize = pRegion->size;
1745	if (regionSize == 0)
1746	break;
1747	/* compute the stored value */
1748	if (reg == PCI_ROM_SLOT) {
1749	/* keep ROM enable bit */
1750	val &= (~(regionSize - 1)) \| 1;
1751	} else {
1752	val &= ~(regionSize - 1);
1753	val \|= pRegion->type;
1754	}
1755	PCIDevSetDWord(aDev, u32Address, val);
1756	ich9pciUpdateMappings(aDev);
1757	return;
1758	}
1759
1760	uint32_t addr = u32Address;
1761	bool fUpdateMappings = false;
1762	for (uint32_t i = 0; i < len; i++)
1763	{
1764	bool fWritable = false;
1765	switch (PCIDevGetHeaderType(aDev))
1766	{
1767	case 0x00: /* normal device */
1768	case 0x80: /* multi-function device */
1769	switch (addr)
1770	{
1771	/* Read-only registers */
1772	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1773	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1774	case VBOX_PCI_REVISION_ID:
1775	case VBOX_PCI_CLASS_PROG:
1776	case VBOX_PCI_CLASS_SUB:
1777	case VBOX_PCI_CLASS_BASE:
1778	case VBOX_PCI_HEADER_TYPE:
1779	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1780	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1781	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1782	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1783	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1784	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1785	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1786	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1787	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1788	case VBOX_PCI_CAPABILITY_LIST:
1789	case VBOX_PCI_INTERRUPT_PIN:
1790	fWritable = false;
1791	break;
1792	/* Others can be written */
1793	default:
1794	fWritable = true;
1795	break;
1796	}
1797	break;
1798	default:
1799	case 0x01: /* bridge */
1800	switch (addr)
1801	{
1802	/* Read-only registers */
1803	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1804	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1805	case VBOX_PCI_REVISION_ID:
1806	case VBOX_PCI_CLASS_PROG:
1807	case VBOX_PCI_CLASS_SUB:
1808	case VBOX_PCI_CLASS_BASE:
1809	case VBOX_PCI_HEADER_TYPE:
1810	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1811	case VBOX_PCI_INTERRUPT_PIN:
1812	fWritable = false;
1813	break;
1814	default:
1815	fWritable = true;
1816	break;
1817	}
1818	break;
1819	}
1820
1821	switch (addr)
1822	{
1823	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1824	fUpdateMappings = true;
1825	aDev->config[addr] = val;
1826	break;
1827	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1828	/* don't change reserved bits (11-15) */
1829	val &= UINT32_C(~0xf8);
1830	fUpdateMappings = true;
1831	aDev->config[addr] = val;
1832	break;
1833	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1834	/* don't change read-only bits => actually all lower bits are read-only */
1835	val &= UINT32_C(~0xff);
1836	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1837	aDev->config[addr] &= ~val;
1838	break;
1839	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1840	/* don't change read-only bits */
1841	val &= UINT32_C(~0x06);
1842	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1843	aDev->config[addr] &= ~val;
1844	break;
1845	default:
1846	if (fWritable)
1847	aDev->config[addr] = val;
1848	}
1849	addr++;
1850	val >>= 8;
1851	}
1852
1853	if (fUpdateMappings)
1854	/* if the command register is modified, we must modify the mappings */
1855	ich9pciUpdateMappings(aDev);
1856	}
1857
1858	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1859	static const struct {
1860	const char* pszName;
1861	int32_t iSlot;
1862	int32_t iFunction;
1863	} PciSlotAssignments[] = {
1864	{
1865	"piix3ide", 1, 1 // do we really need it?
1866	},
1867	{
1868	"lan", 25, 0 /* LAN controller */
1869	},
1870	{
1871	"hda", 27, 0 /* High Definition Audio */
1872	},
1873	{
1874	"i82801", 30, 0 /* Host Controller */
1875	},
1876	{
1877	"lpc", 31, 0 /* Low Pin Count bus */
1878	},
1879	{
1880	"ahci", 31, 2 /* SATA controller */
1881	},
1882	{
1883	"smbus", 31, 3 /* System Management Bus */
1884	},
1885	{
1886	"thermal", 31, 6 /* Thermal controller */
1887	},
1888	};
1889
1890	static int assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName)
1891	{
1892	/* Hardcoded slots/functions, per chipset spec */
1893	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1894	{
1895	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1896	{
1897	PCISetRequestedDevfunc(pPciDev);
1898	return (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1899	}
1900	}
1901
1902	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
1903	for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
1904	if ( !pBus->apDevices[iPos]
1905	&& !pBus->apDevices[iPos + 1]
1906	&& !pBus->apDevices[iPos + 2]
1907	&& !pBus->apDevices[iPos + 3]
1908	&& !pBus->apDevices[iPos + 4]
1909	&& !pBus->apDevices[iPos + 5]
1910	&& !pBus->apDevices[iPos + 6]
1911	&& !pBus->apDevices[iPos + 7])
1912	{
1913	PCIClearRequestedDevfunc(pPciDev);
1914	return iPos;
1915	}
1916
1917	return -1;
1918	}
1919
1920	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
1921	{
1922	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
1923
1924	return (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
1925	\|\| (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
1926	\|\| (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
1927	\|\| (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
1928	\|\| (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
1929	\|\| (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
1930	\|\| (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
1931	\|\| (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
1932	;
1933	}
1934
1935	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1936	{
1937	/*
1938	* Find device position
1939	*/
1940	if (iDev < 0)
1941	{
1942	iDev = assignPosition(pBus, pPciDev, pszName);
1943	if (iDev < 0)
1944	{
1945	AssertMsgFailed(("Couldn't find free spot!\n"));
1946	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1947	}
1948	}
1949
1950	/*
1951	* Check if we can really take this slot, possibly by relocating
1952	* its current habitant, if it wasn't hard assigned too.
1953	*/
1954	if (PCIIsRequestedDevfunc(pPciDev) &&
1955	pBus->apDevices[iDev] &&
1956	PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
1957	{
1958	/*
1959	* Smth like hasHardAssignedDevsInSlot(pBus, iDev >> 3) shall be use to make
1960	* it compatible with DevPCI.cpp version, but this way we cannot assign
1961	* in accordance with the chipset spec.
1962	*/
1963	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1964	pszName, pBus->apDevices[iDev]->name, iDev));
1965	return VERR_INTERNAL_ERROR;
1966	}
1967
1968	if (pBus->apDevices[iDev])
1969	{
1970	/* if we got here, we shall (and usually can) relocate the device */
1971	int iRelDev = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name);
1972	if (iRelDev < 0 \|\| iRelDev == iDev)
1973	{
1974	AssertMsgFailed(("Couldn't find free spot!\n"));
1975	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1976	}
1977	/* Copy device function by function to its new position */
1978	for (int i = 0; i < 8; i++)
1979	{
1980	if (!pBus->apDevices[iDev + i])
1981	continue;
1982	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
1983	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
1984	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
1985	pBus->apDevices[iDev + i] = NULL;
1986	}
1987	}
1988
1989	/*
1990	* Fill in device information.
1991	*/
1992	pPciDev->devfn = iDev;
1993	pPciDev->name = pszName;
1994	pPciDev->Int.s.pBusR3 = pBus;
1995	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1996	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1997	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
1998	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
1999	pBus->apDevices[iDev] = pPciDev;
2000	if (PCIIsPci2PciBridge(pPciDev))
2001	{
2002	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2003	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2004	("device is a bridge but does not implement read/write functions\n"));
2005	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2006	pBus->cBridges++;
2007	}
2008
2009	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
2010	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
2011
2012	return VINF_SUCCESS;
2013	}
2014
2015
2016	/**
2017	* Info handler, device version.
2018	*
2019	* @param pDevIns Device instance which registered the info.
2020	* @param pHlp Callback functions for doing output.
2021	* @param pszArgs Argument string. Optional and specific to the handler.
2022	*/
2023	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2024	{
2025	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2026	uint32_t iBus = 0, iDev;
2027
2028
2029	for (iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2030	{
2031	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2032	if (pPciDev != NULL)
2033	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %x-%x\n",
2034	iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2035	pPciDev->name,
2036	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev)
2037	);
2038	}
2039	}
2040
2041
2042	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2043	int iInstance,
2044	PCFGMNODE pCfg)
2045	{
2046	int rc;
2047	Assert(iInstance == 0);
2048
2049	/*
2050	* Validate and read configuration.
2051	*/
2052	if (!CFGMR3AreValuesValid(pCfg,
2053	"IOAPIC\0"
2054	"GCEnabled\0"
2055	"R0Enabled\0"
2056	"McfgBase\0"
2057	"McfgLength\0"
2058	))
2059	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2060
2061	/* query whether we got an IOAPIC */
2062	bool fUseIoApic;
2063	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2064	if (RT_FAILURE(rc))
2065	return PDMDEV_SET_ERROR(pDevIns, rc,
2066	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2067
2068	/* check if RC code is enabled. */
2069	bool fGCEnabled;
2070	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2071	if (RT_FAILURE(rc))
2072	return PDMDEV_SET_ERROR(pDevIns, rc,
2073	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2074
2075	/* check if R0 code is enabled. */
2076	bool fR0Enabled;
2077	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2078	if (RT_FAILURE(rc))
2079	return PDMDEV_SET_ERROR(pDevIns, rc,
2080	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2081
2082	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2083
2084	/*
2085	* Init data.
2086	*/
2087	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2088	PPCIBUS pBus = &pGlobals->aPciBus;
2089	/* Zero out everything */
2090	memset(pGlobals, 0, sizeof(*pGlobals));
2091	/* And fill values */
2092	if (!fUseIoApic)
2093	return PDMDEV_SET_ERROR(pDevIns, rc,
2094	N_("Must use IO-APIC with ICH9 chipset"));
2095	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2096	if (RT_FAILURE(rc))
2097	return PDMDEV_SET_ERROR(pDevIns, rc,
2098	N_("Configuration error: Failed to read \"McfgBase\""));
2099	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2100	if (RT_FAILURE(rc))
2101	return PDMDEV_SET_ERROR(pDevIns, rc,
2102	N_("Configuration error: Failed to read \"McfgLength\""));
2103
2104	pGlobals->pDevInsR3 = pDevIns;
2105	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2106	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2107
2108	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2109	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2110	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2111	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2112
2113	/*
2114	* Register bus
2115	*/
2116	PDMPCIBUSREG PciBusReg;
2117	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2118	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2119	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2120	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2121	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2122	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2123	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2124	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2125	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2126	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2127	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2128	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2129	if (RT_FAILURE(rc))
2130	return PDMDEV_SET_ERROR(pDevIns, rc,
2131	N_("Failed to register ourselves as a PCI Bus"));
2132	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2133	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2134	N_("PCI helper version mismatch; got %#x expected %#x"),
2135	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2136
2137	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2138	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2139
2140	/*
2141	* Fill in PCI configs and add them to the bus.
2142	*/
2143
2144	/**
2145	* We emulate 82801IB ICH9 IO chip used in Q35,
2146	* see http://ark.intel.com/Product.aspx?id=31892
2147	*
2148	* Stepping S-Spec Top Marking
2149	*
2150	* A2 SLA9M NH82801IB
2151	*/
2152	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2153	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2154	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2155	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2156	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2157	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* normal device */
2158
2159	pBus->aPciDev.pDevIns = pDevIns;
2160	/* We register Host<->PCI controller on the bus */
2161	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2162
2163	/*
2164	* Register I/O ports and save state.
2165	*/
2166	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2167	if (RT_FAILURE(rc))
2168	return rc;
2169	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2170	if (RT_FAILURE(rc))
2171	return rc;
2172	if (fGCEnabled)
2173	{
2174	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2175	if (RT_FAILURE(rc))
2176	return rc;
2177	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2178	if (RT_FAILURE(rc))
2179	return rc;
2180	}
2181	if (fR0Enabled)
2182	{
2183	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2184	if (RT_FAILURE(rc))
2185	return rc;
2186	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2187	if (RT_FAILURE(rc))
2188	return rc;
2189	}
2190
2191	if (pGlobals->u64PciConfigMMioAddress != 0)
2192	{
2193	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, pGlobals,
2194	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, NULL, "MCFG ranges");
2195	if (RT_FAILURE(rc))
2196	{
2197	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2198	return rc;
2199	}
2200
2201	if (fGCEnabled)
2202	{
2203
2204	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2205	pGlobals->u64PciConfigMMioAddress,
2206	pGlobals->u64PciConfigMMioLength,
2207	0,
2208	"ich9pciMcfgMMIOWrite",
2209	"ich9pciMcfgMMIORead",
2210	NULL);
2211	if (RT_FAILURE(rc))
2212	{
2213	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2214	return rc;
2215	}
2216	}
2217
2218
2219	if (fR0Enabled)
2220	{
2221
2222	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2223	pGlobals->u64PciConfigMMioAddress,
2224	pGlobals->u64PciConfigMMioLength,
2225	0,
2226	"ich9pciMcfgMMIOWrite",
2227	"ich9pciMcfgMMIORead",
2228	NULL);
2229	if (RT_FAILURE(rc))
2230	{
2231	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2232	return rc;
2233	}
2234	}
2235	}
2236
2237	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2238	sizeof(pBus) + 16128, "pgm",
2239	NULL, NULL, NULL,
2240	NULL, ich9pciR3SaveExec, NULL,
2241	NULL, ich9pciR3LoadExec, NULL);
2242	if (RT_FAILURE(rc))
2243	return rc;
2244
2245
2246	/** @todo: other chipset devices shall be registered too */
2247	/** @todo: what to with bridges? */
2248
2249	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2250
2251	return VINF_SUCCESS;
2252	}
2253
2254	/**
2255	* @copydoc FNPDMDEVRELOCATE
2256	*/
2257	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2258	{
2259	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2260	PPCIBUS pBus = &pGlobals->aPciBus;
2261	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2262
2263	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2264	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2265
2266	/* Relocate RC pointers for the attached pci devices. */
2267	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2268	{
2269	if (pBus->apDevices[i])
2270	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2271	}
2272
2273	}
2274
2275	/**
2276	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2277	*/
2278	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2279	int iInstance,
2280	PCFGMNODE pCfg)
2281	{
2282	int rc;
2283
2284	/*
2285	* Validate and read configuration.
2286	*/
2287	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2288	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2289
2290	/* check if RC code is enabled. */
2291	bool fGCEnabled;
2292	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2293	if (RT_FAILURE(rc))
2294	return PDMDEV_SET_ERROR(pDevIns, rc,
2295	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2296
2297	/* check if R0 code is enabled. */
2298	bool fR0Enabled;
2299	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2300	if (RT_FAILURE(rc))
2301	return PDMDEV_SET_ERROR(pDevIns, rc,
2302	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2303	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2304
2305	/*
2306	* Init data and register the PCI bus.
2307	*/
2308	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2309	pBus->pDevInsR3 = pDevIns;
2310	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2311	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2312	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2313
2314	PDMPCIBUSREG PciBusReg;
2315	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2316	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2317	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2318	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2319	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2320	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2321	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2322	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2323	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2324	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2325	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2326	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2327	if (RT_FAILURE(rc))
2328	return PDMDEV_SET_ERROR(pDevIns, rc,
2329	N_("Failed to register ourselves as a PCI Bus"));
2330	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2331	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2332	N_("PCI helper version mismatch; got %#x expected %#x"),
2333	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2334
2335	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2336	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2337
2338	/*
2339	* Fill in PCI configs and add them to the bus.
2340	*/
2341	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2342	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2343	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2344	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2345	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2346	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2347	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2348	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2349	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2350	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2351
2352	/*
2353	* This device does not generate interrupts. Interrupt delivery from
2354	* devices attached to the bus is unaffected.
2355	*/
2356	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2357
2358	pBus->aPciDev.pDevIns = pDevIns;
2359
2360	/* Bridge-specific data */
2361	PCISetPci2PciBridge(&pBus->aPciDev);
2362	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2363	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2364
2365	/*
2366	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2367	*/
2368	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2369	if (RT_FAILURE(rc))
2370	return rc;
2371
2372	/*
2373	* The iBus property doesn't really represent the bus number
2374	* because the guest and the BIOS can choose different bus numbers
2375	* for them.
2376	* The bus number is mainly for the setIrq function to indicate
2377	* when the host bus is reached which will have iBus = 0.
2378	* Thathswhy the + 1.
2379	*/
2380	pBus->iBus = iInstance + 1;
2381
2382	/*
2383	* Register SSM handlers. We use the same saved state version as for the host bridge
2384	* to make changes easier.
2385	*/
2386	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2387	sizeof(pBus) + 16128,
2388	"pgm" /* before */,
2389	NULL, NULL, NULL,
2390	NULL, ich9pcibridgeR3SaveExec, NULL,
2391	NULL, ich9pcibridgeR3LoadExec, NULL);
2392	if (RT_FAILURE(rc))
2393	return rc;
2394
2395
2396	return VINF_SUCCESS;
2397	}
2398
2399	/**
2400	* @copydoc FNPDMDEVRESET
2401	*/
2402	static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
2403	{
2404	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2405
2406	/* Reset config space to default values. */
2407	pBus->aPciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2408	pBus->aPciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2409	pBus->aPciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2410	}
2411
2412
2413	/**
2414	* @copydoc FNPDMDEVRELOCATE
2415	*/
2416	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2417	{
2418	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2419	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2420
2421	/* Relocate RC pointers for the attached pci devices. */
2422	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2423	{
2424	if (pBus->apDevices[i])
2425	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2426	}
2427
2428	}
2429
2430	/**
2431	* The PCI bus device registration structure.
2432	*/
2433	const PDMDEVREG g_DevicePciIch9 =
2434	{
2435	/* u32Version */
2436	PDM_DEVREG_VERSION,
2437	/* szName */
2438	"ich9pci",
2439	/* szRCMod */
2440	"VBoxDDGC.gc",
2441	/* szR0Mod */
2442	"VBoxDDR0.r0",
2443	/* pszDescription */
2444	"ICH9 PCI bridge",
2445	/* fFlags */
2446	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2447	/* fClass */
2448	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2449	/* cMaxInstances */
2450	1,
2451	/* cbInstance */
2452	sizeof(PCIGLOBALS),
2453	/* pfnConstruct */
2454	ich9pciConstruct,
2455	/* pfnDestruct */
2456	NULL,
2457	/* pfnRelocate */
2458	ich9pciRelocate,
2459	/* pfnIOCtl */
2460	NULL,
2461	/* pfnPowerOn */
2462	NULL,
2463	/* pfnReset */
2464	NULL,
2465	/* pfnSuspend */
2466	NULL,
2467	/* pfnResume */
2468	NULL,
2469	/* pfnAttach */
2470	NULL,
2471	/* pfnDetach */
2472	NULL,
2473	/* pfnQueryInterface */
2474	NULL,
2475	/* pfnInitComplete */
2476	NULL,
2477	/* pfnPowerOff */
2478	NULL,
2479	/* pfnSoftReset */
2480	NULL,
2481	/* u32VersionEnd */
2482	PDM_DEVREG_VERSION
2483	};
2484
2485	/**
2486	* The device registration structure
2487	* for the PCI-to-PCI bridge.
2488	*/
2489	const PDMDEVREG g_DevicePciIch9Bridge =
2490	{
2491	/* u32Version */
2492	PDM_DEVREG_VERSION,
2493	/* szName */
2494	"ich9pcibridge",
2495	/* szRCMod */
2496	"VBoxDDGC.gc",
2497	/* szR0Mod */
2498	"VBoxDDR0.r0",
2499	/* pszDescription */
2500	"ICH9 PCI to PCI bridge",
2501	/* fFlags */
2502	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2503	/* fClass */
2504	PDM_DEVREG_CLASS_BUS_PCI,
2505	/* cMaxInstances */
2506	~0,
2507	/* cbInstance */
2508	sizeof(PCIBUS),
2509	/* pfnConstruct */
2510	ich9pcibridgeConstruct,
2511	/* pfnDestruct */
2512	NULL,
2513	/* pfnRelocate */
2514	ich9pcibridgeRelocate,
2515	/* pfnIOCtl */
2516	NULL,
2517	/* pfnPowerOn */
2518	NULL,
2519	/* pfnReset */
2520	ich9pcibridgeReset,
2521	/* pfnSuspend */
2522	NULL,
2523	/* pfnResume */
2524	NULL,
2525	/* pfnAttach */
2526	NULL,
2527	/* pfnDetach */
2528	NULL,
2529	/* pfnQueryInterface */
2530	NULL,
2531	/* pfnInitComplete */
2532	NULL,
2533	/* pfnPowerOff */
2534	NULL,
2535	/* pfnSoftReset */
2536	NULL,
2537	/* u32VersionEnd */
2538	PDM_DEVREG_VERSION
2539	};
2540
2541	#endif /* IN_RING3 */
2542	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 32861

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