DevIommuIntel.cpp@ 89589

最後變更在這個檔案從89589是 89589,由 vboxsync 提交於 4 年前
Intel IOMMU: bugref:9967 Padding and avoid including iommu-intel.h in DevIommuIntel.h.
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1	/* $Id: DevIommuIntel.cpp 89589 2021-06-10 08:41:38Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <VBox/iommu-intel.h>
27	#include <iprt/mem.h>
28	#include <iprt/string.h>
29
30
31	/*********************************************************************************************************************************
32	* Defined Constants And Macros *
33	*********************************************************************************************************************************/
34	/** Gets the low uint32_t of a uint64_t or something equivalent.
35	*
36	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
37	* used as it asserts for correctness when compiling on certain compilers). */
38	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
39
40	/** Gets the high uint32_t of a uint64_t or something equivalent.
41	*
42	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
43	* used as it asserts for correctness when compiling on certain compilers). */
44	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
45
46	/** Asserts MMIO access' offset and size are valid or returns appropriate error
47	* code suitable for returning from MMIO access handlers. */
48	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
49	do { \
50	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
51	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
52	} while (0)
53
54	/** Checks if the MMIO offset is valid. */
55	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
56	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
57
58	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
59	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
60	do { \
61	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
62	{ /* likely */ } \
63	else \
64	return (a_rcBusy); \
65	} while (0)
66
67	/** Acquires the DMAR lock (not expected to fail). */
68	#ifdef IN_RING3
69	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
70	#else
71	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
72	do { \
73	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
74	AssertRC(rcLock); \
75	} while (0)
76	#endif
77
78	/** Release the DMAR lock. */
79	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
80
81	/** Asserts that the calling thread owns the DMAR lock. */
82	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
83	do { \
84	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
85	RT_NOREF1(a_pThisCC); \
86	} while (0)
87
88	/** Asserts that the calling thread does not own the DMAR lock. */
89	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
90	do { \
91	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
92	RT_NOREF1(a_pThisCC); \
93	} while (0)
94
95	/** The number of fault recording registers our implementation supports.
96	* Normal guest operation shouldn't trigger faults anyway, so we only support the
97	* minimum number of registers (which is 1).
98	*
99	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
100	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
101
102	/** Number of register groups (used in saved states). */
103	#define DMAR_MMIO_GROUP_COUNT 2
104	/** Offset of first register in group 0. */
105	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
106	/** Offset of last register in group 0 (inclusive). */
107	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
108	/** Last valid offset in group 0 (exclusive). */
109	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
110	/** Size of the group 0 (in bytes). */
111	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
112	/*< Implementation-specific MMIO offset of IVA_REG. /
113	#define DMAR_MMIO_OFF_IVA_REG 0xe50
114	/*< Implementation-specific MMIO offset of IOTLB_REG. /
115	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
116	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
117	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
118	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
119	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
120	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
121
122	/** Offset of first register in group 1. */
123	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
124	/** Offset of last register in group 1 (inclusive). */
125	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
126	/** Last valid offset in group 1 (exclusive). */
127	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
128	/** Size of the group 1 (in bytes). */
129	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
130
131	/** DMAR implementation's major version number (exposed to software).
132	* We report 6 as the major version since we support queued-invalidations as
133	* software may make assumptions based on that.
134	*
135	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
136	#define DMAR_VER_MAJOR 6
137	/** DMAR implementation's minor version number (exposed to software). */
138	#define DMAR_VER_MINOR 0
139
140	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
141	* 7=Reserved). */
142	#define DMAR_ND 6
143
144	/** @name DMAR_PERM_XXX: DMA request permissions.
145	* The order of R, W, X bits is important as it corresponds to those bits in
146	* page-table entries.
147	*
148	* @{ */
149	/** DMA request permission: Read. */
150	#define DMAR_PERM_READ RT_BIT(0)
151	/** DMA request permission: Write. */
152	#define DMAR_PERM_WRITE RT_BIT(1)
153	/** DMA request permission: Execute (ER). */
154	#define DMAR_PERM_EXE RT_BIT(2)
155	/** DMA request permission: Supervisor privilege (PR). */
156	#define DMAR_PERM_PRIV RT_BIT(3)
157	/** DMA request permissions: All. */
158	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
159	/** @} */
160
161	/** Release log prefix string. */
162	#define DMAR_LOG_PFX "Intel-IOMMU"
163	/** The current saved state version. */
164	#define DMAR_SAVED_STATE_VERSION 1
165
166
167	/*********************************************************************************************************************************
168	* Structures and Typedefs *
169	*********************************************************************************************************************************/
170	/**
171	* DMAR error diagnostics.
172	* Sorted alphabetically so it's easier to add and locate items, no other reason.
173	*
174	* @note Members of this enum are used as array indices, so no gaps in enum
175	* values are not allowed. Update g_apszDmarDiagDesc when you modify
176	* fields in this enum.
177	*/
178	typedef enum
179	{
180	/* No error, this must be zero! */
181	kDmarDiag_None = 0,
182
183	/* Address Translation Faults. */
184	kDmarDiag_At_Lm_CtxEntry_Not_Present,
185	kDmarDiag_At_Lm_CtxEntry_Read_Failed,
186	kDmarDiag_At_Lm_CtxEntry_Rsvd,
187	kDmarDiag_At_Lm_Pt_At_Block,
188	kDmarDiag_At_Lm_Pt_Aw_Invalid,
189	kDmarDiag_At_Lm_RootEntry_Not_Present,
190	kDmarDiag_At_Lm_RootEntry_Read_Failed,
191	kDmarDiag_At_Lm_RootEntry_Rsvd,
192	kDmarDiag_At_Lm_Tt_Invalid,
193	kDmarDiag_At_Lm_Ut_At_Block,
194	kDmarDiag_At_Lm_Ut_Aw_Invalid,
195	kDmarDiag_At_Rta_Adms_Not_Supported,
196	kDmarDiag_At_Rta_Rsvd,
197	kDmarDiag_At_Rta_Smts_Not_Supported,
198	kDmarDiag_At_Xm_AddrIn_Invalid,
199	kDmarDiag_At_Xm_AddrOut_Invalid,
200	kDmarDiag_At_Xm_Perm_Denied,
201	kDmarDiag_At_Xm_Pte_Rsvd,
202	kDmarDiag_At_Xm_Pte_Sllps_Invalid,
203	kDmarDiag_At_Xm_Read_Pte_Failed,
204	kDmarDiag_At_Xm_Slpptr_Read_Failed,
205
206	/* CCMD_REG faults. */
207	kDmarDiag_CcmdReg_Not_Supported,
208	kDmarDiag_CcmdReg_Qi_Enabled,
209	kDmarDiag_CcmdReg_Ttm_Invalid,
210
211	/* IQA_REG faults. */
212	kDmarDiag_IqaReg_Dsc_Fetch_Error,
213	kDmarDiag_IqaReg_Dw_128_Invalid,
214	kDmarDiag_IqaReg_Dw_256_Invalid,
215
216	/* Invalidation Queue Error Info. */
217	kDmarDiag_Iqei_Dsc_Type_Invalid,
218	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
219	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
220	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
221	kDmarDiag_Iqei_Ttm_Rsvd,
222
223	/* IQT_REG faults. */
224	kDmarDiag_IqtReg_Qt_Invalid,
225	kDmarDiag_IqtReg_Qt_Not_Aligned,
226
227	/* Interrupt Remapping Faults. */
228	kDmarDiag_Ir_Cfi_Blocked,
229	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
230	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
231	kDmarDiag_Ir_Rfi_Irte_Not_Present,
232	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
233	kDmarDiag_Ir_Rfi_Irte_Rsvd,
234	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
235	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
236	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
237	kDmarDiag_Ir_Rfi_Rsvd,
238
239	/* Member for determining array index limit. */
240	kDmarDiag_End,
241
242	/* Usual 32-bit type size hack. */
243	kDmarDiag_32Bit_Hack = 0x7fffffff
244	} DMARDIAG;
245	AssertCompileSize(DMARDIAG, 4);
246
247	/** DMAR diagnostic enum description expansion.
248	* The below construct ensures typos in the input to this macro are caught
249	* during compile time. */
250	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
251
252	/** DMAR diagnostics description for members in DMARDIAG. */
253	static const char *const g_apszDmarDiagDesc[] =
254	{
255	DMARDIAG_DESC(None ),
256
257	/* Address Translation Faults. */
258	DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
259	DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
260	DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
261	DMARDIAG_DESC(At_Lm_Pt_At_Block ),
262	DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
263	DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
264	DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
265	DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
266	DMARDIAG_DESC(At_Lm_Tt_Invalid ),
267	DMARDIAG_DESC(At_Lm_Ut_At_Block ),
268	DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
269	DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
270	DMARDIAG_DESC(At_Rta_Rsvd ),
271	DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
272	DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
273	DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
274	DMARDIAG_DESC(At_Xm_Perm_Denied ),
275	DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
276	DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
277	DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
278	DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
279
280	/* CCMD_REG faults. */
281	DMARDIAG_DESC(CcmdReg_Not_Supported ),
282	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
283	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
284
285	/* IQA_REG faults. */
286	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
287	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
288	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
289
290	/* Invalidation Queue Error Info. */
291	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
292	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
293	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
294	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
295	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
296
297	/* IQT_REG faults. */
298	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
299	DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
300
301	/* Interrupt remapping faults. */
302	DMARDIAG_DESC(Ir_Cfi_Blocked ),
303	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
304	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
305	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
306	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
307	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
308	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
309	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
310	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
311	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
312	/* kDmarDiag_End */
313	};
314	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
315	#undef DMARDIAG_DESC
316
317	/**
318	* The shared DMAR device state.
319	*/
320	typedef struct DMAR
321	{
322	/** IOMMU device index. */
323	uint32_t idxIommu;
324	/** Padding. */
325	uint32_t u32Padding0;
326
327	/** Registers (group 0). */
328	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
329	/** Registers (group 1). */
330	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
331
332	/** @name Lazily activated registers.
333	* These are the active values for lazily activated registers. Software is free to
334	* modify the actual register values while remapping/translation is enabled but they
335	* take effect only when explicitly signaled by software, hence we need to hold the
336	* active values separately.
337	* @{ */
338	/** Currently active IRTA_REG. */
339	uint64_t uIrtaReg;
340	/** Currently active RTADDR_REG. */
341	uint64_t uRtaddrReg;
342	/** @} */
343
344	/** @name Register copies for a tiny bit faster and more convenient access.
345	* @{ */
346	/** Copy of VER_REG. */
347	uint8_t uVerReg;
348	/** Alignment. */
349	uint8_t abPadding0[7];
350	/** Copy of CAP_REG. */
351	uint64_t fCapReg;
352	/** Copy of ECAP_REG. */
353	uint64_t fExtCapReg;
354	/** @} */
355
356	/** Host-address width (HAW) base address mask. */
357	uint64_t fHawBaseMask;
358	/** Maximum guest-address width (MGAW) invalid address mask. */
359	uint64_t fMgawInvMask;
360	/** Maximum supported paging level (3, 4 or 5). */
361	uint8_t cMaxPagingLevel;
362	/** DMA request valid permissions mask. */
363	uint8_t fPermValidMask;
364	/** Alignment. */
365	uint8_t abPadding1[6];
366
367	/** The event semaphore the invalidation-queue thread waits on. */
368	SUPSEMEVENT hEvtInvQueue;
369	/** Error diagnostic. */
370	DMARDIAG enmDiag;
371	/** Padding. */
372	uint32_t uPadding0;
373	/** The MMIO handle. */
374	IOMMMIOHANDLE hMmio;
375
376	#ifdef VBOX_WITH_STATISTICS
377	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
378	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
379	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
380	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
381
382	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
383	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
384	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
385	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
386
387	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
388	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
389	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
390	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
391
392	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
393	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
394	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
395	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
396
397	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
398	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
399	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
400	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
401	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
402	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
403	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
404	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
405	#endif
406	} DMAR;
407	/** Pointer to the DMAR device state. */
408	typedef DMAR *PDMAR;
409	/** Pointer to the const DMAR device state. */
410	typedef DMAR const *PCDMAR;
411	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
412	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
413
414	/**
415	* The ring-3 DMAR device state.
416	*/
417	typedef struct DMARR3
418	{
419	/** Device instance. */
420	PPDMDEVINSR3 pDevInsR3;
421	/** The IOMMU helper. */
422	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
423	/** The invalidation-queue thread. */
424	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
425	} DMARR3;
426	/** Pointer to the ring-3 DMAR device state. */
427	typedef DMARR3 *PDMARR3;
428	/** Pointer to the const ring-3 DMAR device state. */
429	typedef DMARR3 const *PCDMARR3;
430
431	/**
432	* The ring-0 DMAR device state.
433	*/
434	typedef struct DMARR0
435	{
436	/** Device instance. */
437	PPDMDEVINSR0 pDevInsR0;
438	/** The IOMMU helper. */
439	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
440	} DMARR0;
441	/** Pointer to the ring-0 IOMMU device state. */
442	typedef DMARR0 *PDMARR0;
443	/** Pointer to the const ring-0 IOMMU device state. */
444	typedef DMARR0 const *PCDMARR0;
445
446	/**
447	* The raw-mode DMAR device state.
448	*/
449	typedef struct DMARRC
450	{
451	/** Device instance. */
452	PPDMDEVINSRC pDevInsRC;
453	/** The IOMMU helper. */
454	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
455	} DMARRC;
456	/** Pointer to the raw-mode DMAR device state. */
457	typedef DMARRC *PDMARRC;
458	/** Pointer to the const raw-mode DMAR device state. */
459	typedef DMARRC const *PCIDMARRC;
460
461	/** The DMAR device state for the current context. */
462	typedef CTX_SUFF(DMAR) DMARCC;
463	/** Pointer to the DMAR device state for the current context. */
464	typedef CTX_SUFF(PDMAR) PDMARCC;
465	/** Pointer to the const DMAR device state for the current context. */
466	typedef CTX_SUFF(PDMAR) const PCDMARCC;
467
468	/**
469	* DMAR originated events that generate interrupts.
470	*/
471	typedef enum DMAREVENTTYPE
472	{
473	/** Invalidation completion event. */
474	DMAREVENTTYPE_INV_COMPLETE = 0,
475	/** Fault event. */
476	DMAREVENTTYPE_FAULT
477	} DMAREVENTTYPE;
478
479	/**
480	* I/O Page.
481	*/
482	typedef struct DMARIOPAGE
483	{
484	/** The base DMA address of a page. */
485	RTGCPHYS GCPhysBase;
486	/** The page shift. */
487	uint8_t cShift;
488	/** The permissions of this page (DMAR_PERM_XXX). */
489	uint8_t fPerm;
490	} DMARIOPAGE;
491	/** Pointer to an I/O page. */
492	typedef DMARIOPAGE *PDMARIOPAGE;
493	/** Pointer to a const I/O address range. */
494	typedef DMARIOPAGE const *PCDMARIOPAGE;
495
496	/**
497	* I/O Address Range.
498	*/
499	typedef struct DMARIOADDRRANGE
500	{
501	/** The starting DMA address of this range. */
502	uint64_t uAddr;
503	/** The size of the range (in bytes). */
504	size_t cb;
505	/** The permissions of this range (DMAR_PERM_XXX). */
506	uint8_t fPerm;
507	} DMARIOADDRRANGE;
508	/** Pointer to an I/O address range. */
509	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
510	/** Pointer to a const I/O address range. */
511	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
512
513	/**
514	* DMA Memory Request (Input).
515	*/
516	typedef struct DMARMEMREQIN
517	{
518	/** The address range being accessed. */
519	DMARIOADDRRANGE AddrRange;
520	/** The source device ID (bus, device, function). */
521	uint16_t idDevice;
522	/** The PASID if present (can be NIL_PCIPASID). */
523	PCIPASID Pasid;
524	/* The address translation type. */
525	PCIADDRTYPE enmAddrType;
526	/** The request type. */
527	VTDREQTYPE enmReqType;
528	} DMARMEMREQIN;
529	/** Pointer to a DMA memory request input. */
530	typedef DMARMEMREQIN *PDMARMEMREQIN;
531	/** Pointer to a const DMA memory input. */
532	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
533
534	/**
535	* DMA Memory Request (Output).
536	*/
537	typedef struct DMARMEMREQOUT
538	{
539	/** The address range of the translated region. */
540	DMARIOADDRRANGE AddrRange;
541	/** The domain ID of the translated region. */
542	uint16_t idDomain;
543	} DMARMEMREQOUT;
544	/** Pointer to a DMA memory request output. */
545	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
546	/** Pointer to a const DMA memory request output. */
547	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
548
549	/**
550	* DMA Memory Request (Auxiliary Info).
551	* These get updated and used as part of the translation process.
552	*/
553	typedef struct DMARMEMREQAUX
554	{
555	/** The table translation mode (VTD_TTM_XXX). */
556	uint8_t fTtm;
557	/** The fault processing disabled (FPD) bit. */
558	uint8_t fFpd;
559	/** The paging level of the translation. */
560	uint8_t cPagingLevel;
561	uint8_t abPadding[5];
562	/** The address of the first-level page-table. */
563	uint64_t GCPhysFlPt;
564	/** The address of second-level page-table. */
565	uint64_t GCPhysSlPt;
566	} DMARMEMREQAUX;
567	/** Pointer to a DMA memory request output. */
568	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
569	/** Pointer to a const DMA memory request output. */
570	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
571
572	/**
573	* DMA Memory Request Remapping Information.
574	*/
575	typedef struct DMARMEMREQREMAP
576	{
577	/** The DMA memory request input. */
578	DMARMEMREQIN In;
579	/** DMA memory request auxiliary information. */
580	DMARMEMREQAUX Aux;
581	/** The DMA memory request output. */
582	DMARMEMREQOUT Out;
583	} DMARMEMREQREMAP;
584	/** Pointer to a DMA remap info. */
585	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
586	/** Pointer to a const DMA remap info. */
587	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
588
589	/**
590	* Callback function to lookup a DMA address.
591	*
592	* @returns VBox status code.
593	* @param pDevIns The IOMMU device instance.
594	* @param pMemReqIn The DMA memory request input.
595	* @param pMemReqAux The DMA memory request auxiliary info.
596	* @param pIoPageOut Where to store the output of the lookup.
597	*/
598	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
599	PDMARIOPAGE pIoPageOut));
600	/** Pointer to a DMA address-lookup function. */
601	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
602
603
604	/*********************************************************************************************************************************
605	* Global Variables *
606	*********************************************************************************************************************************/
607	/**
608	* Read-write masks for DMAR registers (group 0).
609	*/
610	static uint32_t const g_au32RwMasks0[] =
611	{
612	/* Offset Register Low High */
613	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
614	/* 0x004 Reserved */ 0,
615	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
616	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
617	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
618	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
619	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
620	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
621	/* 0x030 Reserved */ 0,
622	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
623	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
624	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
625	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
626	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
627	/* 0x048 Reserved */ 0, 0,
628	/* 0x050 Reserved */ 0, 0,
629	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
630	/* 0x060 Reserved */ 0,
631	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
632	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
633	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
634	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
635	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
636	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
637	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
638	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
639	/* 0x098 Reserved */ 0,
640	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
641	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
642	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
643	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
644	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
645	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
646	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
647	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
648	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
649	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
650	/* 0x0d8 Reserved */ 0,
651	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
652	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
653	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
654	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
655	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
656	/* 0x0f0 Reserved */ 0, 0,
657	/* 0x0f8 Reserved */ 0, 0,
658	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
659	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
660	/* 0x110 Reserved */ 0, 0,
661	/* 0x118 Reserved */ 0, 0,
662	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
663	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
664	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
665	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
666	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
667	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
668	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
669	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
670	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
671	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
672	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
673	/* 0x178 Reserved */ 0, 0,
674	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
675	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
676	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
677	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
678	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
679	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
680	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
681	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
682	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
683	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
684	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
685	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
686	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
687	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
688	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
689	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
690	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
691	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
692	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
693	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
694	};
695	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
696
697	/**
698	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
699	*/
700	static uint32_t const g_au32Rw1cMasks0[] =
701	{
702	/* Offset Register Low High */
703	/* 0x000 VER_REG */ 0,
704	/* 0x004 Reserved */ 0,
705	/* 0x008 CAP_REG */ 0, 0,
706	/* 0x010 ECAP_REG */ 0, 0,
707	/* 0x018 GCMD_REG */ 0,
708	/* 0x01c GSTS_REG */ 0,
709	/* 0x020 RTADDR_REG */ 0, 0,
710	/* 0x028 CCMD_REG */ 0, 0,
711	/* 0x030 Reserved */ 0,
712	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
713	/* 0x038 FECTL_REG */ 0,
714	/* 0x03c FEDATA_REG */ 0,
715	/* 0x040 FEADDR_REG */ 0,
716	/* 0x044 FEUADDR_REG */ 0,
717	/* 0x048 Reserved */ 0, 0,
718	/* 0x050 Reserved */ 0, 0,
719	/* 0x058 AFLOG_REG */ 0, 0,
720	/* 0x060 Reserved */ 0,
721	/* 0x064 PMEN_REG */ 0,
722	/* 0x068 PLMBASE_REG */ 0,
723	/* 0x06c PLMLIMIT_REG */ 0,
724	/* 0x070 PHMBASE_REG */ 0, 0,
725	/* 0x078 PHMLIMIT_REG */ 0, 0,
726	/* 0x080 IQH_REG */ 0, 0,
727	/* 0x088 IQT_REG */ 0, 0,
728	/* 0x090 IQA_REG */ 0, 0,
729	/* 0x098 Reserved */ 0,
730	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
731	/* 0x0a0 IECTL_REG */ 0,
732	/* 0x0a4 IEDATA_REG */ 0,
733	/* 0x0a8 IEADDR_REG */ 0,
734	/* 0x0ac IEUADDR_REG */ 0,
735	/* 0x0b0 IQERCD_REG */ 0, 0,
736	/* 0x0b8 IRTA_REG */ 0, 0,
737	/* 0x0c0 PQH_REG */ 0, 0,
738	/* 0x0c8 PQT_REG */ 0, 0,
739	/* 0x0d0 PQA_REG */ 0, 0,
740	/* 0x0d8 Reserved */ 0,
741	/* 0x0dc PRS_REG */ 0,
742	/* 0x0e0 PECTL_REG */ 0,
743	/* 0x0e4 PEDATA_REG */ 0,
744	/* 0x0e8 PEADDR_REG */ 0,
745	/* 0x0ec PEUADDR_REG */ 0,
746	/* 0x0f0 Reserved */ 0, 0,
747	/* 0x0f8 Reserved */ 0, 0,
748	/* 0x100 MTRRCAP_REG */ 0, 0,
749	/* 0x108 MTRRDEF_REG */ 0, 0,
750	/* 0x110 Reserved */ 0, 0,
751	/* 0x118 Reserved */ 0, 0,
752	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
753	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
754	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
755	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
756	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
757	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
758	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
759	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
760	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
761	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
762	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
763	/* 0x178 Reserved */ 0, 0,
764	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
765	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
766	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
767	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
768	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
769	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
770	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
771	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
772	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
773	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
774	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
775	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
776	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
777	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
778	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
779	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
780	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
781	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
782	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
783	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
784	};
785	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
786
787	/**
788	* Read-write masks for DMAR registers (group 1).
789	*/
790	static uint32_t const g_au32RwMasks1[] =
791	{
792	/* Offset Register Low High */
793	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
794	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
795	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
796	/* 0xe18 VCMDRSVD_REG */ 0, 0,
797	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
798	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
799	/* 0xe30 Reserved */ 0, 0,
800	/* 0xe38 Reserved */ 0, 0,
801	/* 0xe40 Reserved */ 0, 0,
802	/* 0xe48 Reserved */ 0, 0,
803	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
804	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
805	/* 0xe60 Reserved */ 0, 0,
806	/* 0xe68 Reserved */ 0, 0,
807	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
808	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
809	};
810	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
811	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
812
813	/**
814	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
815	*/
816	static uint32_t const g_au32Rw1cMasks1[] =
817	{
818	/* Offset Register Low High */
819	/* 0xe00 VCCAP_REG */ 0, 0,
820	/* 0xe08 VCMD_EO_REG */ 0, 0,
821	/* 0xe10 VCMD_REG */ 0, 0,
822	/* 0xe18 VCMDRSVD_REG */ 0, 0,
823	/* 0xe20 VCRSP_REG */ 0, 0,
824	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
825	/* 0xe30 Reserved */ 0, 0,
826	/* 0xe38 Reserved */ 0, 0,
827	/* 0xe40 Reserved */ 0, 0,
828	/* 0xe48 Reserved */ 0, 0,
829	/* 0xe50 IVA_REG */ 0, 0,
830	/* 0xe58 IOTLB_REG */ 0, 0,
831	/* 0xe60 Reserved */ 0, 0,
832	/* 0xe68 Reserved */ 0, 0,
833	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
834	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
835	};
836	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
837
838	/** Array of RW masks for each register group. */
839	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
840
841	/** Array of RW1C masks for each register group. */
842	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
843
844	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
845	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
846
847	/** Array of valid domain-ID bits. */
848	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
849	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
850
851
852	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
853	/** @todo Add IOMMU struct size/alignment verification, see
854	* Devices/testcase/Makefile.kmk and
855	* Devices/testcase/tstDeviceStructSize[RC].cpp */
856
857	/**
858	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
859	* guest address width (MGAW).
860	*
861	* @returns The CAP_REG.SAGAW value.
862	* @param uMgaw The CAP_REG.MGAW value.
863	*/
864	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
865	{
866	/*
867	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
868	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
869	* are always OR'ed in below.
870	*
871	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
872	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
873	*
874	* See Intel VT-d spec. 10.4.2 "Capability Register".
875	*/
876	++uMgaw;
877	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
878	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
879	: uMgaw >= 39 ? RT_BIT(1)
880	: 0;
881	return fSagaw;
882	}
883
884
885	/**
886	* Returns the maximum supported paging level given the supported adjusted
887	* guest-address width (SAGAW) field.
888	*
889	* @returns The highest paging level supported, 0 if invalid.
890	* @param fSagaw The CAP_REG.SAGAW value.
891	*/
892	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
893	{
894	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
895	: fSagaw & RT_BIT(2) ? 4
896	: fSagaw & RT_BIT(1) ? 3
897	: 0;
898	return cMaxPagingLevel;
899	}
900
901
902	/**
903	* Returns whether the interrupt remapping (IR) fault is qualified or not.
904	*
905	* @returns @c true if qualified, @c false otherwise.
906	* @param enmIrFault The interrupt remapping fault condition.
907	*/
908	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
909	{
910	switch (enmIrFault)
911	{
912	case VTDIRFAULT_IRTE_NOT_PRESENT:
913	case VTDIRFAULT_IRTE_PRESENT_RSVD:
914	case VTDIRFAULT_IRTE_PRESENT_INVALID:
915	case VTDIRFAULT_PID_READ_FAILED:
916	case VTDIRFAULT_PID_RSVD:
917	return true;
918	default:
919	return false;
920	}
921	}
922
923
924	/**
925	* Returns table translation mode's descriptive name.
926	*
927	* @returns The descriptive name.
928	* @param uTtm The RTADDR_REG.TTM value.
929	*/
930	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
931	{
932	Assert(!(uTtm & 3));
933	static const char* s_apszTtmNames[] =
934	{
935	"Legacy Mode",
936	"Scalable Mode",
937	"Reserved",
938	"Abort-DMA Mode"
939	};
940	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
941	}
942
943
944	/**
945	* Gets the index of the group the register belongs to given its MMIO offset.
946	*
947	* @returns The group index.
948	* @param offReg The MMIO offset of the register.
949	* @param cbReg The size of the access being made (for bounds checking on
950	* debug builds).
951	*/
952	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
953	{
954	uint16_t const offLast = offReg + cbReg - 1;
955	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
956	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
957	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
958	}
959
960
961	/**
962	* Gets the group the register belongs to given its MMIO offset.
963	*
964	* @returns Pointer to the first element of the register group.
965	* @param pThis The shared DMAR device state.
966	* @param offReg The MMIO offset of the register.
967	* @param cbReg The size of the access being made (for bounds checking on
968	* debug builds).
969	* @param pIdxGroup Where to store the index of the register group the register
970	* belongs to.
971	*/
972	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
973	{
974	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
975	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
976	return apbRegs[*pIdxGroup];
977	}
978
979
980	/**
981	* Const/read-only version of dmarRegGetGroup.
982	*
983	* @copydoc dmarRegGetGroup
984	*/
985	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
986	{
987	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
988	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
989	return apbRegs[*pIdxGroup];
990	}
991
992
993	/**
994	* Writes a 32-bit register with the exactly the supplied value.
995	*
996	* @param pThis The shared DMAR device state.
997	* @param offReg The MMIO offset of the register.
998	* @param uReg The 32-bit value to write.
999	*/
1000	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
1001	{
1002	uint8_t idxGroup;
1003	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
1004	NOREF(idxGroup);
1005	(uint32_t )(pabRegs + offReg) = uReg;
1006	}
1007
1008
1009	/**
1010	* Writes a 64-bit register with the exactly the supplied value.
1011	*
1012	* @param pThis The shared DMAR device state.
1013	* @param offReg The MMIO offset of the register.
1014	* @param uReg The 64-bit value to write.
1015	*/
1016	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1017	{
1018	uint8_t idxGroup;
1019	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1020	NOREF(idxGroup);
1021	(uint64_t )(pabRegs + offReg) = uReg;
1022	}
1023
1024
1025	/**
1026	* Reads a 32-bit register with exactly the value it contains.
1027	*
1028	* @returns The raw register value.
1029	* @param pThis The shared DMAR device state.
1030	* @param offReg The MMIO offset of the register.
1031	*/
1032	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1033	{
1034	uint8_t idxGroup;
1035	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1036	NOREF(idxGroup);
1037	return (uint32_t )(pabRegs + offReg);
1038	}
1039
1040
1041	/**
1042	* Reads a 64-bit register with exactly the value it contains.
1043	*
1044	* @returns The raw register value.
1045	* @param pThis The shared DMAR device state.
1046	* @param offReg The MMIO offset of the register.
1047	*/
1048	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1049	{
1050	uint8_t idxGroup;
1051	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1052	NOREF(idxGroup);
1053	return (uint64_t )(pabRegs + offReg);
1054	}
1055
1056
1057	/**
1058	* Reads a 32-bit register with exactly the value it contains along with their
1059	* corresponding masks
1060	*
1061	* @param pThis The shared DMAR device state.
1062	* @param offReg The MMIO offset of the register.
1063	* @param puReg Where to store the raw 32-bit register value.
1064	* @param pfRwMask Where to store the RW mask corresponding to this register.
1065	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1066	*/
1067	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1068	{
1069	uint8_t idxGroup;
1070	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1071	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1072	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1073	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1074	puReg = (uint32_t *)(pabRegs + offReg);
1075	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1076	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1077	}
1078
1079
1080	/**
1081	* Reads a 64-bit register with exactly the value it contains along with their
1082	* corresponding masks.
1083	*
1084	* @param pThis The shared DMAR device state.
1085	* @param offReg The MMIO offset of the register.
1086	* @param puReg Where to store the raw 64-bit register value.
1087	* @param pfRwMask Where to store the RW mask corresponding to this register.
1088	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1089	*/
1090	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1091	{
1092	uint8_t idxGroup;
1093	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1094	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1095	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1096	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1097	puReg = (uint64_t *)(pabRegs + offReg);
1098	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1099	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1100	}
1101
1102
1103	/**
1104	* Writes a 32-bit register as it would be when written by software.
1105	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1106	*
1107	* @returns The value that's actually written to the register.
1108	* @param pThis The shared DMAR device state.
1109	* @param offReg The MMIO offset of the register.
1110	* @param uReg The 32-bit value to write.
1111	* @param puPrev Where to store the register value prior to writing.
1112	*/
1113	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1114	{
1115	/* Read current value from the 32-bit register. */
1116	uint32_t uCurReg;
1117	uint32_t fRwMask;
1118	uint32_t fRw1cMask;
1119	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1120	*puPrev = uCurReg;
1121
1122	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1123	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1124	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1125	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1126
1127	/* Write new value to the 32-bit register. */
1128	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1129	return uNewReg;
1130	}
1131
1132
1133	/**
1134	* Writes a 64-bit register as it would be when written by software.
1135	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1136	*
1137	* @returns The value that's actually written to the register.
1138	* @param pThis The shared DMAR device state.
1139	* @param offReg The MMIO offset of the register.
1140	* @param uReg The 64-bit value to write.
1141	* @param puPrev Where to store the register value prior to writing.
1142	*/
1143	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1144	{
1145	/* Read current value from the 64-bit register. */
1146	uint64_t uCurReg;
1147	uint64_t fRwMask;
1148	uint64_t fRw1cMask;
1149	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1150	*puPrev = uCurReg;
1151
1152	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1153	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1154	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1155	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1156
1157	/* Write new value to the 64-bit register. */
1158	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1159	return uNewReg;
1160	}
1161
1162
1163	/**
1164	* Reads a 32-bit register as it would be when read by software.
1165	*
1166	* @returns The register value.
1167	* @param pThis The shared DMAR device state.
1168	* @param offReg The MMIO offset of the register.
1169	*/
1170	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1171	{
1172	return dmarRegReadRaw32(pThis, offReg);
1173	}
1174
1175
1176	/**
1177	* Reads a 64-bit register as it would be when read by software.
1178	*
1179	* @returns The register value.
1180	* @param pThis The shared DMAR device state.
1181	* @param offReg The MMIO offset of the register.
1182	*/
1183	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1184	{
1185	return dmarRegReadRaw64(pThis, offReg);
1186	}
1187
1188
1189	/**
1190	* Modifies a 32-bit register.
1191	*
1192	* @param pThis The shared DMAR device state.
1193	* @param offReg The MMIO offset of the register.
1194	* @param fAndMask The AND mask (applied first).
1195	* @param fOrMask The OR mask.
1196	* @remarks This does NOT apply RO or RW1C masks while modifying the
1197	* register.
1198	*/
1199	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1200	{
1201	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1202	uReg = (uReg & fAndMask) \| fOrMask;
1203	dmarRegWriteRaw32(pThis, offReg, uReg);
1204	}
1205
1206
1207	/**
1208	* Modifies a 64-bit register.
1209	*
1210	* @param pThis The shared DMAR device state.
1211	* @param offReg The MMIO offset of the register.
1212	* @param fAndMask The AND mask (applied first).
1213	* @param fOrMask The OR mask.
1214	* @remarks This does NOT apply RO or RW1C masks while modifying the
1215	* register.
1216	*/
1217	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1218	{
1219	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1220	uReg = (uReg & fAndMask) \| fOrMask;
1221	dmarRegWriteRaw64(pThis, offReg, uReg);
1222	}
1223
1224
1225	/**
1226	* Checks if the invalidation-queue is empty.
1227	*
1228	* Extended version which optionally returns the current queue head and tail
1229	* offsets.
1230	*
1231	* @returns @c true if empty, @c false otherwise.
1232	* @param pThis The shared DMAR device state.
1233	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1234	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1235	*/
1236	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1237	{
1238	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1239	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1240	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1241
1242	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1243	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1244	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1245	if (poffQh)
1246	*poffQh = uIqhReg;
1247	if (poffQt)
1248	*poffQt = uIqtReg;
1249	return uIqtReg == uIqhReg;
1250	}
1251
1252
1253	/**
1254	* Checks if the invalidation-queue is empty.
1255	*
1256	* @returns @c true if empty, @c false otherwise.
1257	* @param pThis The shared DMAR device state.
1258	*/
1259	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1260	{
1261	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1262	}
1263
1264
1265	/**
1266	* Checks if the invalidation-queue is capable of processing requests.
1267	*
1268	* @returns @c true if the invalidation-queue can process requests, @c false
1269	* otherwise.
1270	* @param pThis The shared DMAR device state.
1271	*/
1272	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1273	{
1274	/* Check if queued-invalidation is enabled. */
1275	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1276	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1277	{
1278	/* Check if there are no invalidation-queue or timeout errors. */
1279	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1280	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1281	return true;
1282	}
1283	return false;
1284	}
1285
1286
1287	/**
1288	* Wakes up the invalidation-queue thread if there are requests to be processed.
1289	*
1290	* @param pDevIns The IOMMU device instance.
1291	*/
1292	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1293	{
1294	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1295	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1296	LogFlowFunc(("\n"));
1297
1298	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1299
1300	if ( dmarInvQueueCanProcessRequests(pThis)
1301	&& !dmarInvQueueIsEmpty(pThis))
1302	{
1303	Log4Func(("Signaling the invalidation-queue thread\n"));
1304	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1305	}
1306	}
1307
1308
1309	/**
1310	* Raises an event on behalf of the DMAR.
1311	*
1312	* These are events that are generated by the DMAR itself (like faults and
1313	* invalidation completion notifications).
1314	*
1315	* @param pDevIns The IOMMU device instance.
1316	* @param enmEventType The DMAR event type.
1317	*
1318	* @remarks The DMAR lock must be held while calling this function.
1319	*/
1320	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1321	{
1322	uint16_t offCtlReg;
1323	uint32_t fIntrMaskedMask;
1324	uint32_t fIntrPendingMask;
1325	uint16_t offMsiAddrLoReg;
1326	uint16_t offMsiAddrHiReg;
1327	uint16_t offMsiDataReg;
1328	switch (enmEventType)
1329	{
1330	case DMAREVENTTYPE_INV_COMPLETE:
1331	{
1332	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1333	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1334	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1335	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1336	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1337	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1338	break;
1339	}
1340
1341	case DMAREVENTTYPE_FAULT:
1342	{
1343	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1344	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1345	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1346	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1347	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1348	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1349	break;
1350	}
1351
1352	default:
1353	{
1354	/* Shouldn't ever happen. */
1355	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1356	}
1357	}
1358
1359	/* Check if software has masked the interrupt. */
1360	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1361	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1362	if (!(uCtlReg & fIntrMaskedMask))
1363	{
1364	/*
1365	* Interrupt is unmasked, raise it.
1366	* Interrupts generated by the DMAR have trigger mode and level as 0.
1367	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1368	*/
1369	MSIMSG Msi;
1370	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1371	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1372	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1373	Assert(Msi.Data.n.u1Level == 0);
1374	Assert(Msi.Data.n.u1TriggerMode == 0);
1375
1376	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1377	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1378
1379	/* Clear interrupt pending bit. */
1380	uCtlReg &= ~fIntrPendingMask;
1381	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1382	}
1383	else
1384	{
1385	/* Interrupt is masked, set the interrupt pending bit. */
1386	uCtlReg \|= fIntrPendingMask;
1387	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1388	}
1389	}
1390
1391
1392	/**
1393	* Raises an interrupt in response to a fault event.
1394	*
1395	* @param pDevIns The IOMMU device instance.
1396	*
1397	* @remarks This assumes the caller has already set the required status bits in the
1398	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1399	*/
1400	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1401	{
1402	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1403	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1404	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1405
1406	#ifdef RT_STRICT
1407	{
1408	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1409	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1410	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1411	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1412	\| VTD_BF_FSTS_REG_IQE_MASK;
1413	Assert(uFstsReg & fFaultMask);
1414	}
1415	#endif
1416	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1417	}
1418
1419
1420	#ifdef IN_RING3
1421	/**
1422	* Raises an interrupt in response to an invalidation (complete) event.
1423	*
1424	* @param pDevIns The IOMMU device instance.
1425	*/
1426	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1427	{
1428	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1429	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1430	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1431
1432	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1433	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1434	{
1435	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1436	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1437	}
1438	}
1439	#endif /* IN_RING3 */
1440
1441
1442	/**
1443	* Checks if a primary fault can be recorded.
1444	*
1445	* @returns @c true if the fault can be recorded, @c false otherwise.
1446	* @param pDevIns The IOMMU device instance.
1447	* @param pThis The shared DMAR device state.
1448	*
1449	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1450	* NOT call it unless there is a fault condition!
1451	*/
1452	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1453	{
1454	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1455	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1456
1457	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1458	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1459	return false;
1460
1461	/*
1462	* If we add more FRCD registers, we'll have to loop through them here.
1463	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1464	* nor do we need to increment FRI.
1465	*
1466	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1467	*/
1468	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1469	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1470	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1471	{
1472	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1473	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1474	return false;
1475	}
1476
1477	return true;
1478	}
1479
1480
1481	/**
1482	* Records a primary fault.
1483	*
1484	* @param pDevIns The IOMMU device instance.
1485	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1486	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1487	*/
1488	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1489	{
1490	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1491	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1492
1493	DMAR_LOCK(pDevIns, pThisCC);
1494
1495	/* We don't support advance fault logging. */
1496	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1497
1498	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1499	{
1500	/* Update the fault recording registers with the fault information. */
1501	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1502	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1503
1504	/* Set the Pending Primary Fault (PPF) field in the status register. */
1505	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1506
1507	/* Raise interrupt if necessary. */
1508	dmarFaultEventRaiseInterrupt(pDevIns);
1509	}
1510
1511	DMAR_UNLOCK(pDevIns, pThisCC);
1512	}
1513
1514
1515	/**
1516	* Records an interrupt request fault.
1517	*
1518	* @param pDevIns The IOMMU device instance.
1519	* @param enmDiag The diagnostic reason.
1520	* @param idDevice The device ID (bus, device, function).
1521	* @param idxIntr The interrupt index.
1522	* @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1523	* not qualified.
1524	*/
1525	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1526	{
1527	/*
1528	* Update the diagnostic reason (even if software wants to supress faults).
1529	*/
1530	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1531	pThis->enmDiag = enmDiag;
1532
1533	/*
1534	* Figure out the fault reason to report to software from our diagnostic code.
1535	* The case labels below are sorted alphabetically for convenience.
1536	*/
1537	VTDIRFAULT enmIrFault;
1538	switch (enmDiag)
1539	{
1540	case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1541	case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1542	case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1543	case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1544	case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1545	case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1546	case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1547	case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1548	case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1549	case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1550
1551	/* Shouldn't ever happen. */
1552	default:
1553	{
1554	AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1555	enmDiag));
1556	}
1557	}
1558
1559	/*
1560	* Qualified faults are those that can be suppressed by software using the FPD bit
1561	* in the interrupt-remapping table entry.
1562	*/
1563	bool fFpd;
1564	bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1565	if (fQualifiedFault)
1566	{
1567	AssertReturnVoid(pIrte);
1568	fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1569	}
1570	else
1571	fFpd = false;
1572
1573	if (!fFpd)
1574	{
1575	/* Construct and record the error. */
1576	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1577	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1578	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1579	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1580	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1581	}
1582	}
1583
1584
1585	/**
1586	* Records an address translation fault.
1587	*
1588	* @param pDevIns The IOMMU device instance.
1589	* @param enmDiag The diagnostic reason.
1590	* @param pMemReqIn The DMA memory request input.
1591	* @param pMemReqAux The DMA memory request auxiliary info.
1592	*/
1593	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1594	{
1595	/*
1596	* Update the diagnostic reason (even if software wants to supress faults).
1597	*/
1598	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1599	pThis->enmDiag = enmDiag;
1600
1601	/*
1602	* Qualified faults are those that can be suppressed by software using the FPD bit
1603	* in the context entry, scalable-mode context entry etc.
1604	*/
1605	if (!pMemReqAux->fFpd)
1606	{
1607	/*
1608	* Figure out the fault reason to report to software from our diagnostic code.
1609	* The case labels below are sorted alphabetically for convenience.
1610	*/
1611	VTDATFAULT enmAtFault;
1612	bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1613	switch (enmDiag)
1614	{
1615	/* LM (Legacy Mode) faults. */
1616	case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1617	case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1618	case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1619	case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1620	case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1621	case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1622	case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1623	case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1624	case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1625	case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1626	case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1627
1628	/* RTA (Root Table Address) faults. */
1629	case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1630	case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1631	case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1632
1633	/* XM (Legacy mode or Scalable Mode) faults. */
1634	case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1635	case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1636	case kDmarDiag_At_Xm_Perm_Denied: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1637	case kDmarDiag_At_Xm_Pte_Rsvd:
1638	case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1639	case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1640	case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1641
1642	/* Shouldn't ever happen. */
1643	default:
1644	{
1645	AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1646	DMAR_LOG_PFX, enmDiag));
1647	}
1648	}
1649
1650	/* Construct and record the error. */
1651	uint16_t const idDevice = pMemReqIn->idDevice;
1652	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1653	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1654	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1655	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1656	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1657	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1658	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1659
1660	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1661	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1662	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1663	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1664	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1665	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1666	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1667	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1668	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1669	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1670	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1671	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1672	}
1673	}
1674
1675
1676	/**
1677	* Records an IQE fault.
1678	*
1679	* @param pDevIns The IOMMU device instance.
1680	* @param enmIqei The IQE information.
1681	* @param enmDiag The diagnostic reason.
1682	*/
1683	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1684	{
1685	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1686	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1687
1688	DMAR_LOCK(pDevIns, pThisCC);
1689
1690	/* Update the diagnostic reason. */
1691	pThis->enmDiag = enmDiag;
1692
1693	/* Set the error bit. */
1694	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1695	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1696
1697	/* Set the error information. */
1698	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1699	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1700
1701	dmarFaultEventRaiseInterrupt(pDevIns);
1702
1703	DMAR_UNLOCK(pDevIns, pThisCC);
1704	}
1705
1706
1707	/**
1708	* Handles writes to GCMD_REG.
1709	*
1710	* @returns Strict VBox status code.
1711	* @param pDevIns The IOMMU device instance.
1712	* @param uGcmdReg The value written to GCMD_REG.
1713	*/
1714	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1715	{
1716	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1717	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1718	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1719	uint64_t const fExtCapReg = pThis->fExtCapReg;
1720
1721	/* Queued-invalidation. */
1722	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1723	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1724	{
1725	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1726	{
1727	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1728	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1729	}
1730	else
1731	{
1732	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1733	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1734	}
1735	}
1736
1737	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1738	{
1739	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1740	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1741	{
1742	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1743	* supported. */
1744	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1745	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1746	}
1747
1748	/* Interrupt remapping. */
1749	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1750	{
1751	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1752	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1753	else
1754	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1755	}
1756
1757	/* Compatibility format interrupts. */
1758	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1759	{
1760	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1761	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1762	else
1763	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1764	}
1765	}
1766
1767	/* Set Root Table Pointer (SRTP). */
1768	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1769	{
1770	/** @todo Perform global invalidation of all remapping translation caches when
1771	* ESRTPS is supported. */
1772	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1773	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1774	}
1775
1776	/* Translation (DMA remapping). */
1777	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1778	{
1779	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1780	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1781	else
1782	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1783	}
1784
1785	return VINF_SUCCESS;
1786	}
1787
1788
1789	/**
1790	* Handles writes to CCMD_REG.
1791	*
1792	* @returns Strict VBox status code.
1793	* @param pDevIns The IOMMU device instance.
1794	* @param offReg The MMIO register offset.
1795	* @param cbReg The size of the MMIO access (in bytes).
1796	* @param uCcmdReg The value written to CCMD_REG.
1797	*/
1798	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1799	{
1800	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1801	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1802	{
1803	/* Check if we need to invalidate the context-context. */
1804	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1805	if (fIcc)
1806	{
1807	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1808	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1809	if (uMajorVersion < 6)
1810	{
1811	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1812	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1813	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1814	{
1815	/* Verify table translation mode is legacy. */
1816	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1817	if (fTtm == VTD_TTM_LEGACY_MODE)
1818	{
1819	/** @todo Invalidate. */
1820	return VINF_SUCCESS;
1821	}
1822	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1823	}
1824	else
1825	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1826	}
1827	else
1828	pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1829	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1830	}
1831	}
1832	return VINF_SUCCESS;
1833	}
1834
1835
1836	/**
1837	* Handles writes to FECTL_REG.
1838	*
1839	* @returns Strict VBox status code.
1840	* @param pDevIns The IOMMU device instance.
1841	* @param uFectlReg The value written to FECTL_REG.
1842	*/
1843	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1844	{
1845	/*
1846	* If software unmasks the interrupt when the interrupt is pending, we must raise
1847	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1848	*/
1849	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1850	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1851	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1852	return VINF_SUCCESS;
1853	}
1854
1855
1856	/**
1857	* Handles writes to FSTS_REG.
1858	*
1859	* @returns Strict VBox status code.
1860	* @param pDevIns The IOMMU device instance.
1861	* @param uFstsReg The value written to FSTS_REG.
1862	* @param uPrev The value in FSTS_REG prior to writing it.
1863	*/
1864	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1865	{
1866	/*
1867	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1868	* the interrupt pending (IP) bit must be cleared.
1869	*
1870	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1871	*/
1872	uint32_t const fChanged = uPrev ^ uFstsReg;
1873	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1874	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1875	{
1876	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1877	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1878	}
1879	return VINF_SUCCESS;
1880	}
1881
1882
1883	/**
1884	* Handles writes to IQT_REG.
1885	*
1886	* @returns Strict VBox status code.
1887	* @param pDevIns The IOMMU device instance.
1888	* @param offReg The MMIO register offset.
1889	* @param uIqtReg The value written to IQT_REG.
1890	*/
1891	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1892	{
1893	/* We only care about the low 32-bits, high 32-bits are reserved. */
1894	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1895	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1896
1897	/* Paranoia. */
1898	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1899
1900	uint32_t const offQt = uIqtReg;
1901	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1902	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1903
1904	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1905	if ( fDw != VTD_IQA_REG_DW_256_BIT
1906	\|\| !(offQt & RT_BIT(4)))
1907	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1908	else
1909	{
1910	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1911	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1912	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1913	}
1914	return VINF_SUCCESS;
1915	}
1916
1917
1918	/**
1919	* Handles writes to IQA_REG.
1920	*
1921	* @returns Strict VBox status code.
1922	* @param pDevIns The IOMMU device instance.
1923	* @param offReg The MMIO register offset.
1924	* @param uIqaReg The value written to IQA_REG.
1925	*/
1926	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1927	{
1928	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1929	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1930
1931	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1932	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1933	* cannot happen or that it's ignored when it does happen. */
1934
1935	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1936	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1937	if (fDw == VTD_IQA_REG_DW_256_BIT)
1938	{
1939	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1940	if (fSupports256BitDw)
1941	{ /* likely */ }
1942	else
1943	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1944	}
1945	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1946
1947	return VINF_SUCCESS;
1948	}
1949
1950
1951	/**
1952	* Handles writes to ICS_REG.
1953	*
1954	* @returns Strict VBox status code.
1955	* @param pDevIns The IOMMU device instance.
1956	* @param uIcsReg The value written to ICS_REG.
1957	*/
1958	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1959	{
1960	/*
1961	* If the IP field is set when software services the interrupt condition,
1962	* (by clearing the IWC field), the IP field must be cleared.
1963	*/
1964	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1965	{
1966	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1967	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1968	}
1969	return VINF_SUCCESS;
1970	}
1971
1972
1973	/**
1974	* Handles writes to IECTL_REG.
1975	*
1976	* @returns Strict VBox status code.
1977	* @param pDevIns The IOMMU device instance.
1978	* @param uIectlReg The value written to IECTL_REG.
1979	*/
1980	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1981	{
1982	/*
1983	* If software unmasks the interrupt when the interrupt is pending, we must raise
1984	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1985	*/
1986	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1987	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1988	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1989	return VINF_SUCCESS;
1990	}
1991
1992
1993	/**
1994	* Handles writes to FRCD_REG (High 64-bits).
1995	*
1996	* @returns Strict VBox status code.
1997	* @param pDevIns The IOMMU device instance.
1998	* @param offReg The MMIO register offset.
1999	* @param cbReg The size of the MMIO access (in bytes).
2000	* @param uFrcdHiReg The value written to FRCD_REG.
2001	* @param uPrev The value in FRCD_REG prior to writing it.
2002	*/
2003	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
2004	{
2005	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
2006	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2007	{
2008	/*
2009	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2010	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2011	* has only 1 FRCD register.
2012	*
2013	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2014	*/
2015	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2016	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2017	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2018	{
2019	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2020	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2021	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2022	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2023	}
2024	}
2025	return VINF_SUCCESS;
2026	}
2027
2028
2029	/**
2030	* Performs a PCI target abort for a DMA remapping (DR) operation.
2031	*
2032	* @param pDevIns The IOMMU device instance.
2033	*/
2034	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2035	{
2036	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2037	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2038	* who knows. */
2039	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2040	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2041	PDMPciDevSetStatus(pPciDev, u16Status);
2042	}
2043
2044
2045	/**
2046	* Checks whether the address width (AW) is supported by our hardware
2047	* implementation for legacy mode address translation.
2048	*
2049	* @returns @c true if it's supported, @c false otherwise.
2050	* @param pThis The shared DMAR device state.
2051	* @param pCtxEntry The context entry.
2052	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2053	*/
2054	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2055	{
2056	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2057	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2058	uint8_t const fAwMask = RT_BIT(fAw);
2059	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2060	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
2061
2062	uint8_t const cPagingLevel = fAw + 2;
2063	if (pcPagingLevel)
2064	*pcPagingLevel = cPagingLevel;
2065
2066	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
2067	if (fTt == VTD_TT_UNTRANSLATED_PT)
2068	{
2069	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2070	return cPagingLevel == pThis->cMaxPagingLevel;
2071	}
2072
2073	/* The address width must be any of the ones supported by hardware. */
2074	if (fAw < 4)
2075	return (fSagaw & fAwMask) != 0;
2076
2077	return false;
2078	}
2079
2080
2081	/**
2082	* Reads a root entry from guest memory.
2083	*
2084	* @returns VBox status code.
2085	* @param pDevIns The IOMMU device instance.
2086	* @param uRtaddrReg The current RTADDR_REG value.
2087	* @param idxRootEntry The index of the root entry to read.
2088	* @param pRootEntry Where to store the read root entry.
2089	*/
2090	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2091	{
2092	size_t const cbRootEntry = sizeof(*pRootEntry);
2093	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2094	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2095	}
2096
2097
2098	/**
2099	* Reads a context entry from guest memory.
2100	*
2101	* @returns VBox status code.
2102	* @param pDevIns The IOMMU device instance.
2103	* @param GCPhysCtxTable The physical address of the context table.
2104	* @param idxCtxEntry The index of the context entry to read.
2105	* @param pCtxEntry Where to store the read context entry.
2106	*/
2107	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2108	{
2109	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2110	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2111	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2112	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2113	}
2114
2115
2116	/**
2117	* Validates and updates the output I/O page of a translation.
2118	*
2119	* @returns VBox status code.
2120	* @param pDevIns The IOMMU device instance.
2121	* @param GCPhysBase The output address of the translation.
2122	* @param cShift The page shift of the translated address.
2123	* @param fPerm The permissions granted for the translated region.
2124	* @param pMemReqIn The DMA memory request input.
2125	* @param pMemReqAux The DMA memory request auxiliary info.
2126	* @param pIoPageOut Where to store the output of the translation.
2127	*/
2128	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2129	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2130	{
2131	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2132
2133	/* Ensure the output address is not in the interrupt address range. */
2134	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2135	{
2136	pIoPageOut->GCPhysBase = GCPhysBase;
2137	pIoPageOut->cShift = cShift;
2138	pIoPageOut->fPerm = fPerm;
2139	return VINF_SUCCESS;
2140	}
2141
2142	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2143	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2144	}
2145
2146
2147	/**
2148	* Performs second level translation by walking the I/O page tables.
2149	*
2150	* This is a DMA address-lookup callback function which performs the translation
2151	* (and access control) as part of the lookup.
2152	*
2153	* @returns VBox status code.
2154	* @param pDevIns The IOMMU device instance.
2155	* @param pMemReqIn The DMA memory request input.
2156	* @param pMemReqAux The DMA memory request auxiliary info.
2157	* @param pIoPageOut Where to store the output of the translation.
2158	*/
2159	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2160	PDMARIOPAGE pIoPageOut)
2161	{
2162	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2163
2164	/* Sanity. */
2165	Assert(pIoPageOut);
2166	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2167	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2168	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2169	Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2170
2171	/* Mask of valid paging entry bits. */
2172	static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
2173	VTD_SL_PDE_VALID_MASK,
2174	VTD_SL_PDPE_VALID_MASK,
2175	VTD_SL_PML4E_VALID_MASK,
2176	VTD_SL_PML5E_VALID_MASK };
2177
2178	/* Paranoia. */
2179	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2180	AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2181
2182	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2183	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2184	if (!(uAddrIn & pThis->fMgawInvMask))
2185	{ /* likely */ }
2186	else
2187	{
2188	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2189	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2190	}
2191
2192	/*
2193	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2194	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2195	*/
2196	uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2197	for (int8_t idxLevel = pMemReqAux->cPagingLevel - 1; idxLevel >= 0; idxLevel--)
2198	{
2199	/*
2200	* Read the paging entry for the current level.
2201	*/
2202	uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2203	{
2204	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2205	uint16_t const offPte = idxPte << 3;
2206	RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) \| offPte;
2207	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2208	if (RT_SUCCESS(rc))
2209	{ /* likely */ }
2210	else
2211	{
2212	if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2213	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2214	else
2215	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2216	break;
2217	}
2218	}
2219
2220	/*
2221	* Check I/O permissions.
2222	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2223	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2224	*/
2225	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2226	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2227	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2228	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2229	if ((fPtPerm & fReqPerm) == fReqPerm)
2230	{ /* likely */ }
2231	else
2232	{
2233	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Denied, pMemReqIn, pMemReqAux);
2234	break;
2235	}
2236
2237	/*
2238	* Validate reserved bits of the current paging entry.
2239	*/
2240	if (!(uPtEntity & ~s_auPtEntityRsvd[idxLevel]))
2241	{ /* likely */ }
2242	else
2243	{
2244	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2245	break;
2246	}
2247
2248	/*
2249	* Check if this is a 1GB page or a 2MB page.
2250	*/
2251	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2252	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2253	if (fLargePage && idxLevel > 0)
2254	{
2255	Assert(idxLevel == 1 \|\| idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2256	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2257	if (fSllpsMask & RT_BIT(idxLevel - 1))
2258	{
2259	/*
2260	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2261	* All other reserved bits are identical to the regular page-size paging entity which we've already
2262	* checked above.
2263	*/
2264	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2265
2266	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2267	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2268	}
2269
2270	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2271	break;
2272	}
2273
2274	/*
2275	* If this is the final PTE, compute the translation address and we're done.
2276	*/
2277	if (idxLevel == 0)
2278	{
2279	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2280	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2281	}
2282	}
2283
2284	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2285	}
2286
2287
2288	/**
2289	* Checks whether two consecutive I/O page results of a DMA memory request
2290	* translates to a physically contiguous region.
2291	*
2292	* @returns @c true if the I/O pages are contiguous, @c false otherwise.
2293	* @param pIoPagePrev The previous I/O page.
2294	* @param pIoPage The current I/O page.
2295	*/
2296	static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2297	{
2298	/* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2299	Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2300
2301	size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2302	RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2303	RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2304	#ifdef RT_STRICT
2305	/* Paranoia: Ensure offset bits are 0. */
2306	{
2307	uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2308	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2309	Assert(!(GCPhysPrev & fOffMaskPrev));
2310	Assert(!(GCPhys & fOffMask));
2311	}
2312	#endif
2313	return GCPhysPrev + cbPrev == GCPhys;
2314	}
2315
2316
2317	/**
2318	* Looks up the range of addresses for a DMA memory request remapping.
2319	*
2320	* @returns VBox status code.
2321	* @param pDevIns The IOMMU device instance.
2322	* @param pfnLookup The DMA address lookup function.
2323	* @param pMemReqRemap The DMA memory request remapping info.
2324	*/
2325	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2326	{
2327	AssertPtr(pfnLookup);
2328
2329	RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2330	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2331	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2332	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2333	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2334	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2335	size_t cbRemaining = cbAddrIn;
2336
2337	int rc;
2338	DMARIOPAGE IoPagePrev;
2339	RT_ZERO(IoPagePrev);
2340	for (;;)
2341	{
2342	/* Update the input memory request with the next address in our range that needs translation. */
2343	MemReqIn.AddrRange.uAddr = uAddrInBase;
2344	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2345
2346	DMARIOPAGE IoPage;
2347	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2348	if (RT_SUCCESS(rc))
2349	{
2350	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2351
2352	/* Store the translated address before continuing to access more pages. */
2353	if (cbRemaining == cbAddrIn)
2354	{
2355	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2356	uint64_t const offAddrOut = uAddrIn & fOffMask;
2357	Assert(!(IoPage.GCPhysBase & fOffMask));
2358	GCPhysAddr = IoPage.GCPhysBase \| offAddrOut;
2359	}
2360	/* Check if addresses translated so far result in a physically contiguous region. */
2361	else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2362	{
2363	rc = VERR_OUT_OF_RANGE;
2364	break;
2365	}
2366
2367	/* Store the I/O page lookup from the first/previous access. */
2368	IoPagePrev = IoPage;
2369
2370	/* Check if we need to access more pages. */
2371	size_t const cbPage = RT_BIT_64(IoPage.cShift);
2372	if (cbRemaining > cbPage - offAddrIn)
2373	{
2374	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2375	uAddrInBase += cbPage; /* Update address of the next access. */
2376	offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2377	}
2378	else
2379	{
2380	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2381	cbRemaining = 0;
2382	break;
2383	}
2384	}
2385	else
2386	break;
2387	}
2388
2389	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2390	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2391	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2392	return rc;
2393	}
2394
2395
2396	/**
2397	* Handles legacy mode DMA address remapping.
2398	*
2399	* @returns VBox status code.
2400	* @param pDevIns The IOMMU device instance.
2401	* @param uRtaddrReg The current RTADDR_REG value.
2402	* @param pMemReqRemap The DMA memory request remapping info.
2403	*/
2404	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2405	{
2406	PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2407	PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2408	PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2409	Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2410
2411	/* Read the root-entry from guest memory. */
2412	uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2413	VTD_ROOT_ENTRY_T RootEntry;
2414	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2415	if (RT_SUCCESS(rc))
2416	{
2417	/* Check if the root entry is present (must be done before validating reserved bits). */
2418	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2419	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2420	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2421	if (fRootEntryPresent)
2422	{
2423	/* Validate reserved bits in the root entry. */
2424	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2425	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2426	{
2427	/* Read the context-entry from guest memory. */
2428	RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2429	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2430	VTD_CONTEXT_ENTRY_T CtxEntry;
2431	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2432	if (RT_SUCCESS(rc))
2433	{
2434	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2435	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2436
2437	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2438	pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2439
2440	/* Check if the context-entry is present (must be done before validating reserved bits). */
2441	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2442	if (fCtxEntryPresent)
2443	{
2444	/* Validate reserved bits in the context-entry. */
2445	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2446	&& !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2447	{
2448	/* Get the domain ID for this mapping. */
2449	pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2450
2451	/* Validate the translation type (TT). */
2452	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2453	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2454	switch (fTt)
2455	{
2456	case VTD_TT_UNTRANSLATED_SLP:
2457	{
2458	/*
2459	* Untranslated requests are translated using second-level paging structures referenced
2460	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2461	*/
2462	if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2463	{
2464	/* Validate the address width and get the paging level. */
2465	uint8_t cPagingLevel;
2466	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2467	{
2468	/*
2469	* The second-level page table is located at the physical address specified
2470	* in the context entry with which we can finally perform second-level translation.
2471	*/
2472	pMemReqAux->cPagingLevel = cPagingLevel;
2473	pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2474	return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2475	}
2476	else
2477	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2478	}
2479	else
2480	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2481	break;
2482	}
2483
2484	case VTD_TT_UNTRANSLATED_PT:
2485	{
2486	/*
2487	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2488	* Translated and translation requests are blocked. If PT isn't supported this TT value
2489	* is reserved which I assume raises a fault (hence fallthru below).
2490	*/
2491	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2492	{
2493	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2494	{
2495	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2496	{
2497	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2498	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2499	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2500	pOut->AddrRange.cb = pIn->AddrRange.cb;
2501	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2502	return VINF_SUCCESS;
2503	}
2504	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2505	}
2506	else
2507	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2508	break;
2509	}
2510	RT_FALL_THRU();
2511	}
2512
2513	case VTD_TT_UNTRANSLATED_DEV_TLB:
2514	{
2515	/*
2516	* Untranslated, translated and translation requests are supported but requires
2517	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2518	*/
2519	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2520	RT_FALL_THRU();
2521	}
2522
2523	default:
2524	{
2525	/* Any other TT value is reserved. */
2526	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2527	break;
2528	}
2529	}
2530	}
2531	else
2532	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2533	}
2534	else
2535	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2536	}
2537	else
2538	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2539	}
2540	else
2541	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2542	}
2543	else
2544	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2545	}
2546	else
2547	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2548	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2549	}
2550
2551
2552	/**
2553	* Handles remapping of DMA address requests in scalable mode.
2554	*
2555	* @returns VBox status code.
2556	* @param pDevIns The IOMMU device instance.
2557	* @param uRtaddrReg The current RTADDR_REG value.
2558	* @param pMemReqRemap The DMA memory request remapping info.
2559	*/
2560	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2561	{
2562	RT_NOREF2(uRtaddrReg, pMemReqRemap);
2563	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2564	Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK);
2565	return VERR_NOT_IMPLEMENTED;
2566	}
2567
2568
2569	/**
2570	* Gets the DMA access permissions and the address-translation request
2571	* type given the PDM IOMMU memory access flags.
2572	*
2573	* @param pDevIns The IOMMU device instance.
2574	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2575	* @param fBulk Whether this is a bulk memory access (used for
2576	* statistics).
2577	* @param penmReqType Where to store the address-translation request type.
2578	* @param pfReqPerm Where to store the DMA access permissions.
2579	*/
2580	static void dmarDrGetPermAndReqType(PPDMDEVINS pDevIns, uint32_t fFlags, bool fBulk, PVTDREQTYPE penmReqType, uint8_t *pfReqPerm)
2581	{
2582	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2583	if (fFlags & PDMIOMMU_MEM_F_READ)
2584	{
2585	*penmReqType = VTDREQTYPE_READ;
2586	*pfReqPerm = DMAR_PERM_READ;
2587	#ifdef VBOX_WITH_STATISTICS
2588	if (!fBulk)
2589	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2590	else
2591	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2592	#else
2593	RT_NOREF2(pThis, fBulk);
2594	#endif
2595	}
2596	else
2597	{
2598	*penmReqType = VTDREQTYPE_WRITE;
2599	*pfReqPerm = DMAR_PERM_WRITE;
2600	#ifdef VBOX_WITH_STATISTICS
2601	if (!fBulk)
2602	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2603	else
2604	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2605	#else
2606	RT_NOREF2(pThis, fBulk);
2607	#endif
2608	}
2609	}
2610
2611
2612	/**
2613	* Handles DMA remapping based on the table translation mode (TTM).
2614	*
2615	* @returns VBox status code.
2616	* @param pDevIns The IOMMU device instance.
2617	* @param uRtaddrReg The current RTADDR_REG value.
2618	* @param pMemReqRemap The DMA memory request remapping info.
2619	*/
2620	static int dmarDrMemReqRemap(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2621	{
2622	int rc;
2623	switch (pMemReqRemap->Aux.fTtm)
2624	{
2625	case VTD_TTM_LEGACY_MODE:
2626	{
2627	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2628	break;
2629	}
2630
2631	case VTD_TTM_SCALABLE_MODE:
2632	{
2633	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2634	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2635	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2636	else
2637	{
2638	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2639	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2640	}
2641	break;
2642	}
2643
2644	case VTD_TTM_ABORT_DMA_MODE:
2645	{
2646	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2647	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2648	dmarDrTargetAbort(pDevIns);
2649	else
2650	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2651	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2652	break;
2653	}
2654
2655	default:
2656	{
2657	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2658	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &pMemReqRemap->In, &pMemReqRemap->Aux);
2659	break;
2660	}
2661	}
2662	return rc;
2663	}
2664
2665
2666	/**
2667	* Memory access bulk (one or more 4K pages) request from a device.
2668	*
2669	* @returns VBox status code.
2670	* @param pDevIns The IOMMU device instance.
2671	* @param idDevice The device ID (bus, device, function).
2672	* @param cIovas The number of addresses being accessed.
2673	* @param pauIovas The I/O virtual addresses for each page being accessed.
2674	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2675	* @param paGCPhysSpa Where to store the translated physical addresses.
2676	*
2677	* @thread Any.
2678	*/
2679	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2680	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2681	{
2682	/* Validate. */
2683	AssertPtr(pDevIns);
2684	Assert(cIovas > 0);
2685	AssertPtr(pauIovas);
2686	AssertPtr(paGCPhysSpa);
2687	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2688
2689	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2690	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2691
2692	DMAR_LOCK(pDevIns, pThisCC);
2693	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2694	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2695	DMAR_UNLOCK(pDevIns, pThisCC);
2696
2697	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2698	{
2699	VTDREQTYPE enmReqType;
2700	uint8_t fReqPerm;
2701	dmarDrGetPermAndReqType(pDevIns, fFlags, true /* fBulk */, &enmReqType, &fReqPerm);
2702
2703	DMARMEMREQREMAP MemReqRemap;
2704	RT_ZERO(MemReqRemap);
2705	MemReqRemap.In.AddrRange.cb = X86_PAGE_SIZE;
2706	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2707	MemReqRemap.In.idDevice = idDevice;
2708	MemReqRemap.In.Pasid = NIL_PCIPASID;
2709	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2710	MemReqRemap.In.enmReqType = enmReqType;
2711	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2712	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2713
2714	for (size_t i = 0; i < cIovas; i++)
2715	{
2716	MemReqRemap.In.AddrRange.uAddr = pauIovas[i] & X86_PAGE_BASE_MASK;
2717	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2718	if (RT_SUCCESS(rc))
2719	{
2720	paGCPhysSpa[i] = MemReqRemap.Out.AddrRange.uAddr \| (pauIovas[i] & X86_PAGE_OFFSET_MASK);
2721	Assert(MemReqRemap.Out.AddrRange.cb == MemReqRemap.In.AddrRange.cb);
2722	}
2723	else
2724	{
2725	LogFlowFunc(("idDevice=%#x uIova=%#RX64 fPerm=%#x rc=%Rrc\n", idDevice, pauIovas[i], fReqPerm, rc));
2726	return rc;
2727	}
2728	}
2729	}
2730	else
2731	{
2732	/* Addresses are forwarded without translation when the translation is disabled. */
2733	for (size_t i = 0; i < cIovas; i++)
2734	paGCPhysSpa[i] = pauIovas[i];
2735	}
2736
2737	return VINF_SUCCESS;
2738	}
2739
2740
2741	/**
2742	* Memory access transaction from a device.
2743	*
2744	* @returns VBox status code.
2745	* @param pDevIns The IOMMU device instance.
2746	* @param idDevice The device ID (bus, device, function).
2747	* @param uIova The I/O virtual address being accessed.
2748	* @param cbIova The size of the access.
2749	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2750	* @param pGCPhysSpa Where to store the translated system physical address.
2751	* @param pcbContiguous Where to store the number of contiguous bytes translated
2752	* and permission-checked.
2753	*
2754	* @thread Any.
2755	*/
2756	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2757	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2758	{
2759	/* Validate. */
2760	AssertPtr(pDevIns);
2761	AssertPtr(pGCPhysSpa);
2762	AssertPtr(pcbContiguous);
2763	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2764	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2765
2766	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2767	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2768
2769	DMAR_LOCK(pDevIns, pThisCC);
2770	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2771	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2772	DMAR_UNLOCK(pDevIns, pThisCC);
2773
2774	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2775	{
2776	VTDREQTYPE enmReqType;
2777	uint8_t fReqPerm;
2778	dmarDrGetPermAndReqType(pDevIns, fFlags, false /* fBulk */, &enmReqType, &fReqPerm);
2779
2780	DMARMEMREQREMAP MemReqRemap;
2781	RT_ZERO(MemReqRemap);
2782	MemReqRemap.In.AddrRange.uAddr = uIova;
2783	MemReqRemap.In.AddrRange.cb = cbIova;
2784	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2785	MemReqRemap.In.idDevice = idDevice;
2786	MemReqRemap.In.Pasid = NIL_PCIPASID;
2787	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2788	MemReqRemap.In.enmReqType = enmReqType;
2789	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2790	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2791
2792	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2793	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2794	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2795	return rc;
2796	}
2797
2798	*pGCPhysSpa = uIova;
2799	*pcbContiguous = cbIova;
2800	return VINF_SUCCESS;
2801	}
2802
2803
2804	/**
2805	* Reads an IRTE from guest memory.
2806	*
2807	* @returns VBox status code.
2808	* @param pDevIns The IOMMU device instance.
2809	* @param uIrtaReg The IRTA_REG.
2810	* @param idxIntr The interrupt index.
2811	* @param pIrte Where to store the read IRTE.
2812	*/
2813	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2814	{
2815	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2816
2817	size_t const cbIrte = sizeof(*pIrte);
2818	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2819	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2820	}
2821
2822
2823	/**
2824	* Remaps the source MSI to the destination MSI given the IRTE.
2825	*
2826	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2827	* IRTA_REG.EIME).
2828	* @param pIrte The IRTE used for the remapping.
2829	* @param pMsiIn The source MSI (currently unused).
2830	* @param pMsiOut Where to store the remapped MSI.
2831	*/
2832	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2833	{
2834	NOREF(pMsiIn);
2835	uint64_t const uIrteQword0 = pIrte->au64[0];
2836
2837	/*
2838	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2839	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2840	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2841	* it copies it from the source MSI.
2842	*/
2843	RT_ZERO(*pMsiOut);
2844	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2845	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2846	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2847	if (fExtIntrMode)
2848	{
2849	/*
2850	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2851	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2852	*/
2853	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2854	pMsiOut->Addr.n.u8DestId = idDest;
2855	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2856	}
2857	else
2858	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2859
2860	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2861	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2862	pMsiOut->Data.n.u1Level = 1;
2863	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2864	}
2865
2866
2867	/**
2868	* Handles remapping of interrupts in remappable interrupt format.
2869	*
2870	* @returns VBox status code.
2871	* @param pDevIns The IOMMU device instance.
2872	* @param uIrtaReg The IRTA_REG.
2873	* @param idDevice The device ID (bus, device, function).
2874	* @param pMsiIn The source MSI.
2875	* @param pMsiOut Where to store the remapped MSI.
2876	*/
2877	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2878	{
2879	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2880
2881	/* Validate reserved bits in the interrupt request. */
2882	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2883	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2884	{
2885	/* Compute the index into the interrupt remap table. */
2886	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2887	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2888	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2889	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2890	uint16_t const idxIntr = fSubHandleValid
2891	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2892	: uHandle;
2893
2894	/* Validate the index. */
2895	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2896	if (idxIntr < cEntries)
2897	{
2898	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2899
2900	/* Read the interrupt remap table entry (IRTE) at the index. */
2901	VTD_IRTE_T Irte;
2902	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2903	if (RT_SUCCESS(rc))
2904	{
2905	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2906	uint64_t const uIrteQword0 = Irte.au64[0];
2907	uint64_t const uIrteQword1 = Irte.au64[1];
2908	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2909	if (fPresent)
2910	{
2911	/* Validate reserved bits in the IRTE. */
2912	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2913	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2914	if ( !(uIrteQword0 & ~fQw0ValidMask)
2915	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2916	{
2917	/* Validate requester id (the device ID) as configured in the IRTE. */
2918	bool fSrcValid;
2919	DMARDIAG enmIrDiag;
2920	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2921	switch (fSvt)
2922	{
2923	case VTD_IRTE_SVT_NONE:
2924	{
2925	fSrcValid = true;
2926	enmIrDiag = kDmarDiag_None;
2927	break;
2928	}
2929
2930	case VTD_IRTE_SVT_VALIDATE_MASK:
2931	{
2932	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2933	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2934	uint16_t const fValidMask = s_afValidMasks[idxMask];
2935	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2936	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2937	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2938	break;
2939	}
2940
2941	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2942	{
2943	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2944	uint8_t const uBusFirst = RT_HI_U8(idSource);
2945	uint8_t const uBusLast = RT_LO_U8(idSource);
2946	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2947	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2948	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2949	break;
2950	}
2951
2952	default:
2953	{
2954	fSrcValid = false;
2955	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2956	break;
2957	}
2958	}
2959
2960	if (fSrcValid)
2961	{
2962	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2963	if (!fPostedMode)
2964	{
2965	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2966	return VINF_SUCCESS;
2967	}
2968	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2969	}
2970	else
2971	dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2972	}
2973	else
2974	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2975	}
2976	else
2977	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2978	}
2979	else
2980	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2981	}
2982	else
2983	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2984	}
2985	else
2986	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr /, NULL / pIrte */);
2987	return VERR_IOMMU_INTR_REMAP_DENIED;
2988	}
2989
2990
2991	/**
2992	* Interrupt remap request from a device.
2993	*
2994	* @returns VBox status code.
2995	* @param pDevIns The IOMMU device instance.
2996	* @param idDevice The device ID (bus, device, function).
2997	* @param pMsiIn The source MSI.
2998	* @param pMsiOut Where to store the remapped MSI.
2999	*/
3000	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3001	{
3002	/* Validate. */
3003	Assert(pDevIns);
3004	Assert(pMsiIn);
3005	Assert(pMsiOut);
3006	RT_NOREF1(idDevice);
3007
3008	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3009	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3010
3011	/* Lock and read all registers required for interrupt remapping up-front. */
3012	DMAR_LOCK(pDevIns, pThisCC);
3013	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3014	uint64_t const uIrtaReg = pThis->uIrtaReg;
3015	DMAR_UNLOCK(pDevIns, pThisCC);
3016
3017	/* Check if interrupt remapping is enabled. */
3018	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
3019	{
3020	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
3021	if (!fIsRemappable)
3022	{
3023	/* Handle compatibility format interrupts. */
3024	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
3025
3026	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
3027	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
3028	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
3029	{
3030	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
3031	return VERR_IOMMU_INTR_REMAP_DENIED;
3032	}
3033
3034	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
3035	pMsiOut = pMsiIn;
3036	return VINF_SUCCESS;
3037	}
3038
3039	/* Handle remappable format interrupts. */
3040	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
3041	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
3042	}
3043
3044	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
3045	pMsiOut = pMsiIn;
3046	return VINF_SUCCESS;
3047	}
3048
3049
3050	/**
3051	* @callback_method_impl{FNIOMMMIONEWWRITE}
3052	*/
3053	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3054	{
3055	RT_NOREF1(pvUser);
3056	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3057
3058	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3059	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
3060
3061	uint16_t const offReg = off;
3062	uint16_t const offLast = offReg + cb - 1;
3063	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3064	{
3065	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3066	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
3067
3068	uint64_t uPrev = 0;
3069	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
3070	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
3071	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3072	switch (off)
3073	{
3074	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
3075	{
3076	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
3077	break;
3078	}
3079
3080	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
3081	case VTD_MMIO_OFF_CCMD_REG + 4:
3082	{
3083	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
3084	break;
3085	}
3086
3087	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3088	{
3089	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3090	break;
3091	}
3092
3093	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3094	{
3095	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3096	break;
3097	}
3098
3099	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3100	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
3101	{
3102	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3103	break;
3104	}
3105
3106	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3107	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
3108	{
3109	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3110	break;
3111	}
3112
3113	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3114	{
3115	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3116	break;
3117	}
3118
3119	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3120	{
3121	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3122	break;
3123	}
3124
3125	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3126	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3127	{
3128	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3129	break;
3130	}
3131	}
3132
3133	DMAR_UNLOCK(pDevIns, pThisCC);
3134	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3135	return rcStrict;
3136	}
3137
3138	return VINF_IOM_MMIO_UNUSED_FF;
3139	}
3140
3141
3142	/**
3143	* @callback_method_impl{FNIOMMMIONEWREAD}
3144	*/
3145	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3146	{
3147	RT_NOREF1(pvUser);
3148	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3149
3150	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3151	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3152
3153	uint16_t const offReg = off;
3154	uint16_t const offLast = offReg + cb - 1;
3155	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3156	{
3157	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3158	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3159
3160	if (cb == 8)
3161	{
3162	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3163	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3164	}
3165	else
3166	{
3167	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3168	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3169	}
3170
3171	DMAR_UNLOCK(pDevIns, pThisCC);
3172	return VINF_SUCCESS;
3173	}
3174
3175	return VINF_IOM_MMIO_UNUSED_FF;
3176	}
3177
3178
3179	#ifdef IN_RING3
3180	/**
3181	* Process requests in the invalidation queue.
3182	*
3183	* @param pDevIns The IOMMU device instance.
3184	* @param pvRequests The requests to process.
3185	* @param cbRequests The size of all requests (in bytes).
3186	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3187	* VTD_IQA_REG_DW_256_BIT).
3188	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3189	*/
3190	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3191	uint8_t fTtm)
3192	{
3193	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3194	do \
3195	{ \
3196	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3197	return; \
3198	} while (0)
3199
3200	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3201	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3202
3203	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3204	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3205
3206	/*
3207	* The below check is redundant since we check both TTM and DW for each
3208	* descriptor type we process. However, the order of errors reported by hardware
3209	* may differ hence this is kept commented out but not removed if we need to
3210	* change this in the future.
3211	*
3212	* In our implementation, we would report the descriptor type as invalid,
3213	* while on real hardware it may report descriptor width as invalid.
3214	* The Intel VT-d spec. is not clear which error takes preceedence.
3215	*/
3216	#if 0
3217	/*
3218	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3219	* We don't check this while software writes IQA_REG but defer it until now because
3220	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3221	* -IS- performed when software writes IQA_REG since it only requires checking against
3222	* immutable hardware features.
3223	*/
3224	if ( fTtm != VTD_TTM_SCALABLE_MODE
3225	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3226	{ /* likely */ }
3227	else
3228	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3229	#endif
3230
3231	/*
3232	* Process requests in FIFO order.
3233	*/
3234	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3235	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3236	{
3237	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3238	uint64_t const uQword0 = puDscQwords[0];
3239	uint64_t const uQword1 = puDscQwords[1];
3240	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3241	switch (fDscType)
3242	{
3243	case VTD_INV_WAIT_DSC_TYPE:
3244	{
3245	/* Validate descriptor type. */
3246	if ( fTtm == VTD_TTM_LEGACY_MODE
3247	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3248	{ /* likely */ }
3249	else
3250	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3251
3252	/* Validate reserved bits. */
3253	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3254	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3255	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3256	if ( !(uQword0 & ~fValidMask0)
3257	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3258	{ /* likely */ }
3259	else
3260	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3261
3262	if (fDw == VTD_IQA_REG_DW_256_BIT)
3263	{
3264	if ( !puDscQwords[2]
3265	&& !puDscQwords[3])
3266	{ /* likely */ }
3267	else
3268	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3269	}
3270
3271	/* Perform status write (this must be done prior to generating the completion interrupt). */
3272	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3273	if (fSw)
3274	{
3275	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3276	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3277	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3278	AssertRC(rc);
3279	}
3280
3281	/* Generate invalidation event interrupt. */
3282	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3283	if (fIf)
3284	{
3285	DMAR_LOCK(pDevIns, pThisR3);
3286	dmarR3InvEventRaiseInterrupt(pDevIns);
3287	DMAR_UNLOCK(pDevIns, pThisR3);
3288	}
3289
3290	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3291	break;
3292	}
3293
3294	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3295	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3296	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3297	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3298	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3299	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3300	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3301	default:
3302	{
3303	/* Stop processing further requests. */
3304	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3305	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3306	}
3307	}
3308	}
3309	#undef DMAR_IQE_FAULT_RECORD_RET
3310	}
3311
3312
3313	/**
3314	* The invalidation-queue thread.
3315	*
3316	* @returns VBox status code.
3317	* @param pDevIns The IOMMU device instance.
3318	* @param pThread The command thread.
3319	*/
3320	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3321	{
3322	NOREF(pThread);
3323	LogFlowFunc(("\n"));
3324
3325	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3326	return VINF_SUCCESS;
3327
3328	/*
3329	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3330	* This prevents trashing the heap as well as deal with out-of-memory situations
3331	* up-front while starting the VM. It also simplifies the code from having to
3332	* dynamically grow/shrink the allocation based on how software sizes the queue.
3333	* Guests normally don't alter the queue size all the time, but that's not an
3334	* assumption we can make.
3335	*/
3336	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3337	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3338	void *pvRequests = RTMemAllocZ(cbMaxQs);
3339	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3340
3341	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3342	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3343
3344	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3345	{
3346	/*
3347	* Sleep until we are woken up.
3348	*/
3349	{
3350	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3351	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3352	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3353	break;
3354	}
3355
3356	DMAR_LOCK(pDevIns, pThisR3);
3357	if (dmarInvQueueCanProcessRequests(pThis))
3358	{
3359	uint32_t offQueueHead;
3360	uint32_t offQueueTail;
3361	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3362	if (!fIsEmpty)
3363	{
3364	/*
3365	* Get the current queue size, descriptor width, queue base address and the
3366	* table translation mode while the lock is still held.
3367	*/
3368	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3369	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3370	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3371	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3372	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3373	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3374
3375	/* Paranoia. */
3376	Assert(cbQueue <= cbMaxQs);
3377	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3378	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3379	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3380	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3381	Assert(offQueueHead < cbQueue);
3382
3383	/*
3384	* A table translation mode of "reserved" isn't valid for any descriptor type.
3385	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3386	* but if ESRTPS is support, we will perform a global invalidation when software
3387	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3388	* So caching TTM while reading all descriptors should not be a problem.
3389	*
3390	* Also, validate the queue tail offset as it's mutable by software.
3391	*/
3392	if ( fTtm != VTD_TTM_RSVD
3393	&& offQueueTail < cbQueue)
3394	{
3395	/* Don't hold the lock while reading (a potentially large amount of) requests */
3396	DMAR_UNLOCK(pDevIns, pThisR3);
3397
3398	int rc;
3399	uint32_t cbRequests;
3400	if (offQueueTail > offQueueHead)
3401	{
3402	/* The requests have not wrapped around, read them in one go. */
3403	cbRequests = offQueueTail - offQueueHead;
3404	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3405	}
3406	else
3407	{
3408	/* The requests have wrapped around, read forward and wrapped-around. */
3409	uint32_t const cbForward = cbQueue - offQueueHead;
3410	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3411
3412	uint32_t const cbWrapped = offQueueTail;
3413	if ( RT_SUCCESS(rc)
3414	&& cbWrapped > 0)
3415	{
3416	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3417	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3418	}
3419	cbRequests = cbForward + cbWrapped;
3420	}
3421
3422	/* Re-acquire the lock since we need to update device state. */
3423	DMAR_LOCK(pDevIns, pThisR3);
3424
3425	if (RT_SUCCESS(rc))
3426	{
3427	/* Indicate to software we've fetched all requests. */
3428	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3429
3430	/* Don't hold the lock while processing requests. */
3431	DMAR_UNLOCK(pDevIns, pThisR3);
3432
3433	/* Process all requests. */
3434	Assert(cbRequests <= cbQueue);
3435	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3436
3437	/*
3438	* We've processed all requests and the lock shouldn't be held at this point.
3439	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3440	* it again before going back to the thread loop. It's a bit ugly but it certainly
3441	* helps with performance.
3442	*/
3443	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3444	continue;
3445	}
3446	else
3447	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3448	}
3449	else
3450	{
3451	if (fTtm == VTD_TTM_RSVD)
3452	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3453	else
3454	{
3455	Assert(offQueueTail >= cbQueue);
3456	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3457	}
3458	}
3459	}
3460	}
3461	DMAR_UNLOCK(pDevIns, pThisR3);
3462	}
3463
3464	RTMemFree(pvRequests);
3465	pvRequests = NULL;
3466
3467	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3468	return VINF_SUCCESS;
3469	}
3470
3471
3472	/**
3473	* Wakes up the invalidation-queue thread so it can respond to a state
3474	* change.
3475	*
3476	* @returns VBox status code.
3477	* @param pDevIns The IOMMU device instance.
3478	* @param pThread The invalidation-queue thread.
3479	*
3480	* @thread EMT.
3481	*/
3482	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3483	{
3484	RT_NOREF(pThread);
3485	LogFlowFunc(("\n"));
3486	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3487	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3488	}
3489
3490
3491	/**
3492	* @callback_method_impl{FNDBGFHANDLERDEV}
3493	*/
3494	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3495	{
3496	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3497	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3498	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3499
3500	/*
3501	* We lock the device to get a consistent register state as it is
3502	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3503	* ones we care about here) into temporaries and release the lock ASAP.
3504	*
3505	* Order of register being read and outputted is in accordance with the
3506	* spec. for no particular reason.
3507	* See Intel VT-d spec. 10.4 "Register Descriptions".
3508	*/
3509	DMAR_LOCK(pDevIns, pThisR3);
3510
3511	DMARDIAG const enmDiag = pThis->enmDiag;
3512	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3513	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3514	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3515	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3516	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3517	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3518	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3519	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3520	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3521	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3522	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3523	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3524	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3525	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3526	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3527	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3528	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3529	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3530	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3531	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3532	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3533	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3534	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3535	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3536	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3537	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3538	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3539	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3540	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3541	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3542	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3543	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3544	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3545	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3546	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3547	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3548	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3549	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3550
3551	DMAR_UNLOCK(pDevIns, pThisR3);
3552
3553	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3554	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3555	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3556
3557	/*
3558	* Non-verbose output.
3559	*/
3560	if (!fVerbose)
3561	{
3562	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3563	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3564	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3565	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3566	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3567	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3568	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3569	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3570	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3571	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3572	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3573	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3574	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3575	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3576	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3577	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3578	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3579	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3580	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3581	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3582	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3583	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3584	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3585	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3586	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3587	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3588	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3589	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3590	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3591	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3592	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3593	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3594	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3595	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3596	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3597	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3598	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3599	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3600	pHlp->pfnPrintf(pHlp, "\n");
3601	return;
3602	}
3603
3604	/*
3605	* Verbose output.
3606	*/
3607	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3608	{
3609	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3610	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3611	}
3612	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3613	{
3614	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3615	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3616	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3617	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3618	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3619	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3620	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3621	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3622	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3623	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3624	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3625	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3626	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3627	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3628	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3629	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3630	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3631	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3632	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3633	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3634	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3635	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3636	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3637	}
3638	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3639	{
3640	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3641	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3642	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3643	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3644	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3645	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3646	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3647	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3648	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3649	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3650	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3651	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3652	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3653	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3654	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3655	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3656	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3657	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3658	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3659	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3660	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3661	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3662	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3663	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3664	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3665	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3666	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3667	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3668	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3669	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3670	}
3671	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3672	{
3673	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3674	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3675	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3676	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3677	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3678	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3679	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3680	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3681	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3682	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3683	}
3684	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3685	{
3686	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3687	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3688	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3689	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3690	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3691	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3692	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3693	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3694	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3695	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3696	}
3697	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3698	{
3699	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3700	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3701	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3702	}
3703	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3704	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3705	{
3706	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3707	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3708	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3709	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3710	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3711	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3712	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3713	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3714	}
3715	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3716	{
3717	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3718	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3719	}
3720	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3721	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3722	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3723	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3724	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3725	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3726	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3727	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3728	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3729	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3730	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3731	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3732	{
3733	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3734	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3735	uint8_t const cQueuePages = 1 << fQs;
3736	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3737	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3738	}
3739	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3740	{
3741	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3742	}
3743	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3744	{
3745	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3746	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3747	}
3748	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3749	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3750	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3751	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3752	{
3753	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3754	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3755	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3756	}
3757	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3758	{
3759	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3760	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3761	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3762	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3763	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3764	}
3765	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3766	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3767	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3768	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3769	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3770	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3771	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3772	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3773	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3774	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3775	pHlp->pfnPrintf(pHlp, "\n");
3776	}
3777
3778
3779	/**
3780	* Initializes all registers in the DMAR unit.
3781	*
3782	* @param pDevIns The IOMMU device instance.
3783	*/
3784	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3785	{
3786	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3787	LogFlowFunc(("\n"));
3788
3789	/*
3790	* Wipe all registers (required on reset).
3791	*/
3792	RT_ZERO(pThis->abRegs0);
3793	RT_ZERO(pThis->abRegs1);
3794
3795	/*
3796	* Initialize registers not mutable by software prior to initializing other registers.
3797	*/
3798	/* VER_REG */
3799	{
3800	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3801	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3802	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3803	}
3804
3805	uint8_t const fFlts = 0; /* First-level translation support. */
3806	uint8_t const fSlts = 1; /* Second-level translation support. */
3807	uint8_t const fPt = 1; /* Pass-Through support. */
3808	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3809	uint8_t const fNest = 0; /* Nested translation support. */
3810
3811	/* CAP_REG */
3812	{
3813	uint8_t cGstPhysAddrBits;
3814	uint8_t cGstLinearAddrBits;
3815	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3816
3817	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3818	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3819	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3820	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3821	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3822	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3823	: X86_PAGE_2M_SHIFT)
3824	- X86_PAGE_4K_SHIFT;
3825	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3826	uint8_t const fPsi = 1; /* Page selective invalidation. */
3827	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3828	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3829	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3830	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3831	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3832	AssertCompile(DMAR_ND <= 6);
3833
3834	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3835	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3836	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3837	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3838	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3839	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3840	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3841	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3842	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3843	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3844	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3845	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3846	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3847	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3848	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3849	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3850	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3851	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3852	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3853	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3854	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3855	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3856
3857	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3858	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3859	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3860	}
3861
3862	/* ECAP_REG */
3863	{
3864	uint8_t const fQi = 1; /* Queued-invalidations. */
3865	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3866	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3867	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3868	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3869	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3870	uint8_t const fErs = 0; /* Execute Request (not supported). */
3871
3872	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3873	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3874	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3875	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3876	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3877	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3878	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3879	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3880	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3881	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3882	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3883	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3884	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3885	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3886	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3887	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3888	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3889	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3890	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3891	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3892	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3893	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3894	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3895	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3896	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3897	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3898	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3899	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3900	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3901	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3902
3903	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3904	if (fErs)
3905	pThis->fPermValidMask = DMAR_PERM_EXE;
3906	}
3907
3908	/*
3909	* Initialize registers mutable by software.
3910	*/
3911	/* FECTL_REG */
3912	{
3913	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3914	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3915	}
3916
3917	/* ICETL_REG */
3918	{
3919	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3920	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3921	}
3922
3923	#ifdef VBOX_STRICT
3924	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3925	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3926	#endif
3927	}
3928
3929
3930	/**
3931	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3932	*/
3933	static DECLCALLBACK(int) dmarR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3934	{
3935	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
3936	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3937	LogFlowFunc(("\n"));
3938
3939	/* First, save software-immutable registers that we validate on state load. */
3940	pHlp->pfnSSMPutU32(pSSM, pThis->uVerReg);
3941	pHlp->pfnSSMPutU64(pSSM, pThis->fCapReg);
3942	pHlp->pfnSSMPutU64(pSSM, pThis->fExtCapReg);
3943
3944	/* Save MMIO registers. */
3945	pHlp->pfnSSMPutU32(pSSM, DMAR_MMIO_GROUP_COUNT);
3946	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs0));
3947	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs0[0], sizeof(pThis->abRegs0));
3948	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs1));
3949	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
3950
3951	/* Save lazily activated registers. */
3952	pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
3953	pHlp->pfnSSMPutU64(pSSM, pThis->uRtaddrReg);
3954
3955	/* Save terminator marker and return status. */
3956	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
3957	}
3958
3959
3960	/**
3961	* @callback_method_impl{FNSSMDEVLOADEXEC}
3962	*/
3963	static DECLCALLBACK(int) dmarR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3964	{
3965	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3966	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3967	int const rcDataErr = VERR_SSM_UNEXPECTED_DATA;
3968	int const rcFmtErr = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3969	LogFlowFunc(("\n"));
3970
3971	/*
3972	* Validate saved-state version.
3973	*/
3974	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
3975	if (uVersion != DMAR_SAVED_STATE_VERSION)
3976	{
3977	LogRel(("%s: Invalid saved-state version %#x\n", DMAR_LOG_PFX, uVersion));
3978	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3979	}
3980
3981	/*
3982	* Load and validate software-immutable registers.
3983	* The features we had exposed to the guest (in the saved state) must be identical
3984	* to what is currently emulated.
3985	*/
3986	{
3987	/* VER_REG */
3988	uint32_t uVerReg;
3989	int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
3990	AssertRCReturn(rc, rc);
3991	AssertLogRelMsgReturn(uVerReg == pThis->uVerReg,
3992	("%s: VER_REG mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, pThis->uVerReg, uVerReg),
3993	rcDataErr);
3994	/* CAP_REG */
3995	uint64_t fCapReg;
3996	pHlp->pfnSSMGetU64(pSSM, &fCapReg);
3997	AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
3998	("%s: CAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fCapReg, fCapReg),
3999	rcDataErr);
4000	/* ECAP_REG */
4001	uint64_t fExtCapReg;
4002	pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
4003	AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
4004	("%s: ECAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fExtCapReg,
4005	fExtCapReg), rcDataErr);
4006	}
4007
4008	/*
4009	* Load MMIO registers.
4010	*/
4011	{
4012	/* Group count. */
4013	uint32_t cRegGroups;
4014	pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
4015	AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
4016	("%s: MMIO group count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_GROUP_COUNT,
4017	cRegGroups), rcFmtErr);
4018	/* Group 0. */
4019	uint32_t cbRegs0;
4020	pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
4021	AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
4022	("%s: MMIO group 0 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs0),
4023	cbRegs0), rcFmtErr);
4024	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
4025	/* Group 1. */
4026	uint32_t cbRegs1;
4027	pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
4028	AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
4029	("%s: MMIO group 1 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs1),
4030	cbRegs1), rcFmtErr);
4031	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
4032	}
4033
4034	/*
4035	* Load lazily activated registers.
4036	*/
4037	{
4038	/* Active IRTA_REG. */
4039	pHlp->pfnSSMGetU64(pSSM, &pThis->uIrtaReg);
4040	AssertLogRelMsgReturn(!(pThis->uIrtaReg & ~VTD_IRTA_REG_RW_MASK),
4041	("%s: IRTA_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uIrtaReg), rcDataErr);
4042	/* Active RTADDR_REG. */
4043	pHlp->pfnSSMGetU64(pSSM, &pThis->uRtaddrReg);
4044	AssertLogRelMsgReturn(!(pThis->uRtaddrReg & ~VTD_RTADDR_REG_RW_MASK),
4045	("%s: RTADDR_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uRtaddrReg), rcDataErr);
4046	}
4047
4048	/*
4049	* Verify terminator marker.
4050	*/
4051	{
4052	uint32_t uEndMarker;
4053	int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
4054	AssertRCReturn(rc, rc);
4055	AssertLogRelMsgReturn(uEndMarker == UINT32_MAX,
4056	("%s: End marker mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, UINT32_MAX, uEndMarker),
4057	rcFmtErr);
4058	}
4059	return VINF_SUCCESS;
4060	}
4061
4062
4063	/**
4064	* @callback_method_impl{FNSSMDEVLOADDONE}
4065	*/
4066	static DECLCALLBACK(int) dmarR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4067	{
4068	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4069	LogFlowFunc(("\n"));
4070	RT_NOREF(pSSM);
4071	AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
4072
4073	DMAR_LOCK(pDevIns, pThisR3);
4074	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
4075	DMAR_UNLOCK(pDevIns, pThisR3);
4076	return VINF_SUCCESS;
4077	}
4078
4079
4080	/**
4081	* @interface_method_impl{PDMDEVREG,pfnReset}
4082	*/
4083	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
4084	{
4085	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4086	LogFlowFunc(("\n"));
4087
4088	DMAR_LOCK(pDevIns, pThisR3);
4089	dmarR3RegsInit(pDevIns);
4090	DMAR_UNLOCK(pDevIns, pThisR3);
4091	}
4092
4093
4094	/**
4095	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4096	*/
4097	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
4098	{
4099	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4100	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4101	LogFlowFunc(("\n"));
4102
4103	DMAR_LOCK(pDevIns, pThisR3);
4104
4105	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
4106	{
4107	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
4108	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
4109	}
4110
4111	DMAR_UNLOCK(pDevIns, pThisR3);
4112	return VINF_SUCCESS;
4113	}
4114
4115
4116	/**
4117	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4118	*/
4119	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4120	{
4121	RT_NOREF(pCfg);
4122
4123	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4124	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4125	pThisR3->pDevInsR3 = pDevIns;
4126
4127	LogFlowFunc(("iInstance=%d\n", iInstance));
4128	NOREF(iInstance);
4129
4130	/*
4131	* Register the IOMMU with PDM.
4132	*/
4133	PDMIOMMUREGR3 IommuReg;
4134	RT_ZERO(IommuReg);
4135	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4136	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4137	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4138	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4139	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4140	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4141	if (RT_FAILURE(rc))
4142	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4143	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4144	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4145	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4146	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4147	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4148	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4149	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4150	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4151	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
4152	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
4153	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
4154	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
4155
4156	/*
4157	* Use PDM's critical section (via helpers) for the IOMMU device.
4158	*/
4159	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4160	AssertRCReturn(rc, rc);
4161
4162	/*
4163	* Initialize PCI configuration registers.
4164	*/
4165	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4166	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4167
4168	/* Header. */
4169	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4170	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4171	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4172	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4173	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
4174	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
4175	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4176	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4177
4178	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
4179	PDMPciDevSetStatus(pPciDev, 0);
4180	PDMPciDevSetCapabilityList(pPciDev, 0);
4181	/** @todo VTBAR at 0x180? */
4182
4183	/*
4184	* Register the PCI function with PDM.
4185	*/
4186	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4187	AssertLogRelRCReturn(rc, rc);
4188
4189	/*
4190	* Register MMIO region.
4191	*/
4192	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
4193	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
4194	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
4195	&pThis->hMmio);
4196	AssertLogRelRCReturn(rc, rc);
4197
4198	/*
4199	* Register saved state handlers.
4200	*/
4201	rc = PDMDevHlpSSMRegisterEx(pDevIns, DMAR_SAVED_STATE_VERSION, sizeof(DMAR), NULL /* pszBefore */,
4202	NULL /* pfnLivePrep /, NULL / pfnLiveExec /, NULL / pfnLiveVote */,
4203	NULL /* pfnSavePrep /, dmarR3SaveExec, NULL / pfnSaveDone */,
4204	NULL /* pfnLoadPrep */, dmarR3LoadExec, dmarR3LoadDone);
4205	AssertLogRelRCReturn(rc, rc);
4206
4207	/*
4208	* Register debugger info items.
4209	*/
4210	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
4211	AssertLogRelRCReturn(rc, rc);
4212
4213	#ifdef VBOX_WITH_STATISTICS
4214	/*
4215	* Statistics.
4216	*/
4217	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4218	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4219
4220	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4221	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4222
4223	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
4224	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
4225	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
4226	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
4227
4228	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4229	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4230
4231	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4232	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4233
4234	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4235	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4236
4237	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4238	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4239
4240	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4241	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4242	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4243	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4244	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4245	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4246	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4247	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4248	#endif
4249
4250	/*
4251	* Initialize registers.
4252	*/
4253	dmarR3RegsInit(pDevIns);
4254
4255	/*
4256	* Create invalidation-queue thread and semaphore.
4257	*/
4258	char szInvQueueThread[32];
4259	RT_ZERO(szInvQueueThread);
4260	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4261	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4262	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4263	AssertLogRelRCReturn(rc, rc);
4264
4265	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4266	AssertLogRelRCReturn(rc, rc);
4267
4268	/*
4269	* Log some of the features exposed to software.
4270	*/
4271	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4272	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4273	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4274	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4275	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4276	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4277	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4278	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4279	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4280	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4281	pThis->fMgawInvMask, offFrcd, offIva));
4282	return VINF_SUCCESS;
4283	}
4284
4285	#else
4286
4287	/**
4288	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4289	*/
4290	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4291	{
4292	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4293	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4294	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4295	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4296
4297	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4298	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4299	AssertRCReturn(rc, rc);
4300
4301	/* Set up the MMIO RZ handlers. */
4302	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4303	AssertRCReturn(rc, rc);
4304
4305	/* Set up the IOMMU RZ callbacks. */
4306	PDMIOMMUREGCC IommuReg;
4307	RT_ZERO(IommuReg);
4308	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4309	IommuReg.idxIommu = pThis->idxIommu;
4310	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4311	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4312	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4313	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4314
4315	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4316	AssertRCReturn(rc, rc);
4317	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4318	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4319	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4320	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4321	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4322	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4323	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4324
4325	return VINF_SUCCESS;
4326	}
4327
4328	#endif
4329
4330
4331	/**
4332	* The device registration structure.
4333	*/
4334	PDMDEVREG const g_DeviceIommuIntel =
4335	{
4336	/* .u32Version = */ PDM_DEVREG_VERSION,
4337	/* .uReserved0 = */ 0,
4338	/* .szName = */ "iommu-intel",
4339	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4340	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4341	/* .cMaxInstances = */ 1,
4342	/* .uSharedVersion = */ 42,
4343	/* .cbInstanceShared = */ sizeof(DMAR),
4344	/* .cbInstanceCC = */ sizeof(DMARCC),
4345	/* .cbInstanceRC = */ sizeof(DMARRC),
4346	/* .cMaxPciDevices = */ 1,
4347	/* .cMaxMsixVectors = */ 0,
4348	/* .pszDescription = */ "IOMMU (Intel)",
4349	#if defined(IN_RING3)
4350	/* .pszRCMod = */ "VBoxDDRC.rc",
4351	/* .pszR0Mod = */ "VBoxDDR0.r0",
4352	/* .pfnConstruct = */ iommuIntelR3Construct,
4353	/* .pfnDestruct = */ iommuIntelR3Destruct,
4354	/* .pfnRelocate = */ NULL,
4355	/* .pfnMemSetup = */ NULL,
4356	/* .pfnPowerOn = */ NULL,
4357	/* .pfnReset = */ iommuIntelR3Reset,
4358	/* .pfnSuspend = */ NULL,
4359	/* .pfnResume = */ NULL,
4360	/* .pfnAttach = */ NULL,
4361	/* .pfnDetach = */ NULL,
4362	/* .pfnQueryInterface = */ NULL,
4363	/* .pfnInitComplete = */ NULL,
4364	/* .pfnPowerOff = */ NULL,
4365	/* .pfnSoftReset = */ NULL,
4366	/* .pfnReserved0 = */ NULL,
4367	/* .pfnReserved1 = */ NULL,
4368	/* .pfnReserved2 = */ NULL,
4369	/* .pfnReserved3 = */ NULL,
4370	/* .pfnReserved4 = */ NULL,
4371	/* .pfnReserved5 = */ NULL,
4372	/* .pfnReserved6 = */ NULL,
4373	/* .pfnReserved7 = */ NULL,
4374	#elif defined(IN_RING0)
4375	/* .pfnEarlyConstruct = */ NULL,
4376	/* .pfnConstruct = */ iommuIntelRZConstruct,
4377	/* .pfnDestruct = */ NULL,
4378	/* .pfnFinalDestruct = */ NULL,
4379	/* .pfnRequest = */ NULL,
4380	/* .pfnReserved0 = */ NULL,
4381	/* .pfnReserved1 = */ NULL,
4382	/* .pfnReserved2 = */ NULL,
4383	/* .pfnReserved3 = */ NULL,
4384	/* .pfnReserved4 = */ NULL,
4385	/* .pfnReserved5 = */ NULL,
4386	/* .pfnReserved6 = */ NULL,
4387	/* .pfnReserved7 = */ NULL,
4388	#elif defined(IN_RC)
4389	/* .pfnConstruct = */ iommuIntelRZConstruct,
4390	/* .pfnReserved0 = */ NULL,
4391	/* .pfnReserved1 = */ NULL,
4392	/* .pfnReserved2 = */ NULL,
4393	/* .pfnReserved3 = */ NULL,
4394	/* .pfnReserved4 = */ NULL,
4395	/* .pfnReserved5 = */ NULL,
4396	/* .pfnReserved6 = */ NULL,
4397	/* .pfnReserved7 = */ NULL,
4398	#else
4399	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4400	#endif
4401	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4402	};
4403
4404	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4405

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89589

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