VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89270

最後變更 在這個檔案從89270是 89257,由 vboxsync 提交於 4 年 前

Intel IOMMU: bugref:9967 Address translation, typo.
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1/* $Id: DevIommuIntel.cpp 89257 2021-05-25 07:19:41Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - Intel implementation.
4 */
5
6/*
7 * Copyright (C) 2021 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include "VBoxDD.h"
24#include "DevIommuIntel.h"
25
26#include <iprt/mem.h>
27#include <iprt/string.h>
28
29
30/*********************************************************************************************************************************
31* Defined Constants And Macros *
32*********************************************************************************************************************************/
33/** Gets the low uint32_t of a uint64_t or something equivalent.
34 *
35 * This is suitable for casting constants outside code (since RT_LO_U32 can't be
36 * used as it asserts for correctness when compiling on certain compilers). */
37#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39/** Gets the high uint32_t of a uint64_t or something equivalent.
40 *
41 * This is suitable for casting constants outside code (since RT_HI_U32 can't be
42 * used as it asserts for correctness when compiling on certain compilers). */
43#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45/** Asserts MMIO access' offset and size are valid or returns appropriate error
46 * code suitable for returning from MMIO access handlers. */
47#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48 do { \
49 AssertReturn((a_cb) == 4 || (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50 AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51 } while (0)
52
53/** Checks if the MMIO offset is valid. */
54#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55 || (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59 do { \
60 if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61 { /* likely */ } \
62 else \
63 return (a_rcBusy); \
64 } while (0)
65
66/** Acquires the DMAR lock (not expected to fail). */
67#ifdef IN_RING3
68# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69#else
70# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71 do { \
72 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73 AssertRC(rcLock); \
74 } while (0)
75#endif
76
77/** Release the DMAR lock. */
78#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80/** Asserts that the calling thread owns the DMAR lock. */
81#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82 do { \
83 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84 RT_NOREF1(a_pThisCC); \
85 } while (0)
86
87/** Asserts that the calling thread does not own the DMAR lock. */
88#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89 do { \
90 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91 RT_NOREF1(a_pThisCC); \
92 } while (0)
93
94/** The number of fault recording registers our implementation supports.
95 * Normal guest operation shouldn't trigger faults anyway, so we only support the
96 * minimum number of registers (which is 1).
97 *
98 * See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101/** Offset of first register in group 0. */
102#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103/** Offset of last register in group 0 (inclusive). */
104#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105/** Last valid offset in group 0 (exclusive). */
106#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107/** Size of the group 0 (in bytes). */
108#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109/**< Implementation-specific MMIO offset of IVA_REG. */
110#define DMAR_MMIO_OFF_IVA_REG 0xe50
111/**< Implementation-specific MMIO offset of IOTLB_REG. */
112#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113/**< Implementation-specific MMIO offset of FRCD_LO_REG. */
114#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115/**< Implementation-specific MMIO offset of FRCD_HI_REG. */
116#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119/** Offset of first register in group 1. */
120#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121/** Offset of last register in group 1 (inclusive). */
122#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123/** Last valid offset in group 1 (exclusive). */
124#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125/** Size of the group 1 (in bytes). */
126#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128/** DMAR implementation's major version number (exposed to software).
129 * We report 6 as the major version since we support queued-invalidations as
130 * software may make assumptions based on that.
131 *
132 * See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133#define DMAR_VER_MAJOR 6
134/** DMAR implementation's minor version number (exposed to software). */
135#define DMAR_VER_MINOR 0
136
137/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
138 * 7=Reserved). */
139#define DMAR_ND 6
140
141/** Release log prefix string. */
142#define DMAR_LOG_PFX "Intel-IOMMU"
143/** The current saved state version. */
144#define DMAR_SAVED_STATE_VERSION 1
145
146
147/*********************************************************************************************************************************
148* Structures and Typedefs *
149*********************************************************************************************************************************/
150/**
151 * DMAR error diagnostics.
152 * Sorted alphabetically so it's easier to add and locate items, no other reason.
153 *
154 * @note Members of this enum are used as array indices, so no gaps in enum
155 * values are not allowed. Update g_apszDmarDiagDesc when you modify
156 * fields in this enum.
157 */
158typedef enum
159{
160 /* No error, this must be zero! */
161 kDmarDiag_None = 0,
162
163 /* Address Translation Faults. */
164 kDmarDiag_Atf_Lct_1,
165 kDmarDiag_Atf_Lct_2,
166 kDmarDiag_Atf_Lct_3,
167 kDmarDiag_Atf_Lct_4_1,
168 kDmarDiag_Atf_Lct_4_2,
169 kDmarDiag_Atf_Lct_4_3,
170 kDmarDiag_Atf_Lrt_1,
171 kDmarDiag_Atf_Lrt_2,
172 kDmarDiag_Atf_Lrt_3,
173 kDmarDiag_Atf_Rta_1_1,
174 kDmarDiag_Atf_Rta_1_2,
175 kDmarDiag_Atf_Rta_1_3,
176
177 /* CCMD_REG faults. */
178 kDmarDiag_CcmdReg_NotSupported,
179 kDmarDiag_CcmdReg_Qi_Enabled,
180 kDmarDiag_CcmdReg_Ttm_Invalid,
181
182 /* IQA_REG faults. */
183 kDmarDiag_IqaReg_Dsc_Fetch_Error,
184 kDmarDiag_IqaReg_Dw_128_Invalid,
185 kDmarDiag_IqaReg_Dw_256_Invalid,
186
187 /* Invalidation Queue Error Info. */
188 kDmarDiag_Iqei_Dsc_Type_Invalid,
189 kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
190 kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
191 kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
192 kDmarDiag_Iqei_Ttm_Rsvd,
193
194 /* IQT_REG faults. */
195 kDmarDiag_IqtReg_Qt_Invalid,
196 kDmarDiag_IqtReg_Qt_NotAligned,
197
198 /* Compatibility Format Interrupt Faults. */
199 kDmarDiag_Ir_Cfi_Blocked,
200
201 /* Remappable Format Interrupt Faults. */
202 kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
203 kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
204 kDmarDiag_Ir_Rfi_Irte_Not_Present,
205 kDmarDiag_Ir_Rfi_Irte_Read_Failed,
206 kDmarDiag_Ir_Rfi_Irte_Rsvd,
207 kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
208 kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
209 kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
210 kDmarDiag_Ir_Rfi_Rsvd,
211
212 /* Member for determining array index limit. */
213 kDmarDiag_End,
214
215 /* Usual 32-bit type size hack. */
216 kDmarDiag_32Bit_Hack = 0x7fffffff
217} DMARDIAG;
218AssertCompileSize(DMARDIAG, 4);
219
220/** DMAR diagnostic enum description expansion.
221 * The below construct ensures typos in the input to this macro are caught
222 * during compile time. */
223#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
224
225/** DMAR diagnostics description for members in DMARDIAG. */
226static const char *const g_apszDmarDiagDesc[] =
227{
228 DMARDIAG_DESC(None ),
229 DMARDIAG_DESC(Atf_Lct_1 ),
230 DMARDIAG_DESC(Atf_Lct_2 ),
231 DMARDIAG_DESC(Atf_Lct_3 ),
232 DMARDIAG_DESC(Atf_Lct_4_1 ),
233 DMARDIAG_DESC(Atf_Lct_4_2 ),
234 DMARDIAG_DESC(Atf_Lct_4_3 ),
235 DMARDIAG_DESC(Atf_Lrt_1 ),
236 DMARDIAG_DESC(Atf_Lrt_2 ),
237 DMARDIAG_DESC(Atf_Lrt_3 ),
238 DMARDIAG_DESC(Atf_Rta_1_1 ),
239 DMARDIAG_DESC(Atf_Rta_1_2 ),
240 DMARDIAG_DESC(Atf_Rta_1_3 ),
241 DMARDIAG_DESC(CcmdReg_NotSupported ),
242 DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
243 DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
244 DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
245 DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
246 DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
247 DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
248 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
249 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
250 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
251 DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
252 DMARDIAG_DESC(IqtReg_Qt_Invalid ),
253 DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
254 DMARDIAG_DESC(Ir_Cfi_Blocked ),
255 DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
256 DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
257 DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
258 DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
259 DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
260 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
261 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
262 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
263 DMARDIAG_DESC(Ir_Rfi_Rsvd ),
264 /* kDmarDiag_End */
265};
266AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
267#undef DMARDIAG_DESC
268
269/**
270 * The shared DMAR device state.
271 */
272typedef struct DMAR
273{
274 /** IOMMU device index. */
275 uint32_t idxIommu;
276 /** DMAR magic. */
277 uint32_t u32Magic;
278
279 /** Registers (group 0). */
280 uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
281 /** Registers (group 1). */
282 uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
283
284 /** @name Lazily activated registers.
285 * These are the active values for lazily activated registers. Software is free to
286 * modify the actual register values while remapping/translation is enabled but they
287 * take effect only when explicitly signaled by software, hence we need to hold the
288 * active values separately.
289 * @{ */
290 /** Currently active IRTA_REG. */
291 uint64_t uIrtaReg;
292 /** Currently active RTADDR_REG. */
293 uint64_t uRtaddrReg;
294 /** @} */
295
296 /** @name Register copies for a tiny bit faster and more convenient access.
297 * @{ */
298 /** Copy of VER_REG. */
299 uint8_t uVerReg;
300 /** Alignment. */
301 uint8_t abPadding[7];
302 /** Copy of CAP_REG. */
303 uint64_t fCapReg;
304 /** Copy of ECAP_REG. */
305 uint64_t fExtCapReg;
306 /** @} */
307
308 /** The event semaphore the invalidation-queue thread waits on. */
309 SUPSEMEVENT hEvtInvQueue;
310 /** Padding. */
311 uint32_t uPadding0;
312 /** Error diagnostic. */
313 DMARDIAG enmDiag;
314 /** The MMIO handle. */
315 IOMMMIOHANDLE hMmio;
316
317#ifdef VBOX_WITH_STATISTICS
318 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
319 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
320 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
321 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
322
323 STAMCOUNTER StatMsiRemapCfiR3; /**< Number of compatibility-format interrupts remap requests in R3. */
324 STAMCOUNTER StatMsiRemapCfiRZ; /**< Number of compatibility-format interrupts remap requests in RZ. */
325 STAMCOUNTER StatMsiRemapRfiR3; /**< Number of remappable-format interrupts remap requests in R3. */
326 STAMCOUNTER StatMsiRemapRfiRZ; /**< Number of remappable-format interrupts remap requests in RZ. */
327
328 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
329 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
330 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
331 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
332
333 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
334 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
335 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
336 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
337
338 STAMCOUNTER StatCcInvDsc; /**< Number of Context-cache descriptors processed. */
339 STAMCOUNTER StatIotlbInvDsc; /**< Number of IOTLB descriptors processed. */
340 STAMCOUNTER StatDevtlbInvDsc; /**< Number of Device-TLB descriptors processed. */
341 STAMCOUNTER StatIecInvDsc; /**< Number of Interrupt-Entry cache descriptors processed. */
342 STAMCOUNTER StatInvWaitDsc; /**< Number of Invalidation wait descriptors processed. */
343 STAMCOUNTER StatPasidIotlbInvDsc; /**< Number of PASID-based IOTLB descriptors processed. */
344 STAMCOUNTER StatPasidCacheInvDsc; /**< Number of PASID-cache descriptors processed. */
345 STAMCOUNTER StatPasidDevtlbInvDsc; /**< Number of PASID-based device-TLB descriptors processed. */
346#endif
347} DMAR;
348/** Pointer to the DMAR device state. */
349typedef DMAR *PDMAR;
350/** Pointer to the const DMAR device state. */
351typedef DMAR const *PCDMAR;
352AssertCompileMemberAlignment(DMAR, abRegs0, 8);
353AssertCompileMemberAlignment(DMAR, abRegs1, 8);
354
355/**
356 * The ring-3 DMAR device state.
357 */
358typedef struct DMARR3
359{
360 /** Device instance. */
361 PPDMDEVINSR3 pDevInsR3;
362 /** The IOMMU helper. */
363 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
364 /** The invalidation-queue thread. */
365 R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
366} DMARR3;
367/** Pointer to the ring-3 DMAR device state. */
368typedef DMARR3 *PDMARR3;
369/** Pointer to the const ring-3 DMAR device state. */
370typedef DMARR3 const *PCDMARR3;
371
372/**
373 * The ring-0 DMAR device state.
374 */
375typedef struct DMARR0
376{
377 /** Device instance. */
378 PPDMDEVINSR0 pDevInsR0;
379 /** The IOMMU helper. */
380 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
381} DMARR0;
382/** Pointer to the ring-0 IOMMU device state. */
383typedef DMARR0 *PDMARR0;
384/** Pointer to the const ring-0 IOMMU device state. */
385typedef DMARR0 const *PCDMARR0;
386
387/**
388 * The raw-mode DMAR device state.
389 */
390typedef struct DMARRC
391{
392 /** Device instance. */
393 PPDMDEVINSRC pDevInsRC;
394 /** The IOMMU helper. */
395 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
396} DMARRC;
397/** Pointer to the raw-mode DMAR device state. */
398typedef DMARRC *PDMARRC;
399/** Pointer to the const raw-mode DMAR device state. */
400typedef DMARRC const *PCIDMARRC;
401
402/** The DMAR device state for the current context. */
403typedef CTX_SUFF(DMAR) DMARCC;
404/** Pointer to the DMAR device state for the current context. */
405typedef CTX_SUFF(PDMAR) PDMARCC;
406/** Pointer to the const DMAR device state for the current context. */
407typedef CTX_SUFF(PDMAR) const PCDMARCC;
408
409/**
410 * Type of DMAR originated events that generate interrupts.
411 */
412typedef enum DMAREVENTTYPE
413{
414 /** Invalidation completion event. */
415 DMAREVENTTYPE_INV_COMPLETE = 0,
416 /** Fault event. */
417 DMAREVENTTYPE_FAULT
418} DMAREVENTTYPE;
419
420
421/**
422 * DMA address map.
423 * This structure holds information about a DMA address translation.
424 */
425typedef struct DMARADDRMAP
426{
427 /** The device ID (bus, device, function). */
428 uint16_t idDevice;
429 uint16_t uPadding0;
430 /** The DMA remapping operation request type. */
431 VTDREQTYPE enmReqType;
432 /** The DMA address being accessed. */
433 uint64_t uDmaAddr;
434 /** The size of the DMA access (in bytes). */
435 size_t cbDma;
436 /** The translated system-physical address (HPA). */
437 RTGCPHYS GCPhysSpa;
438 /** The size of the contiguous translated region (in bytes). */
439 size_t cbContiguous;
440} DMARADDRMAP;
441/** Pointer to a DMA address map. */
442typedef DMARADDRMAP *PDMARADDRMAP;
443/** Pointer to a const DMA address map. */
444typedef DMARADDRMAP const *PCDMARADDRMAP;
445
446
447/*********************************************************************************************************************************
448* Global Variables *
449*********************************************************************************************************************************/
450/**
451 * Read-write masks for DMAR registers (group 0).
452 */
453static uint32_t const g_au32RwMasks0[] =
454{
455 /* Offset Register Low High */
456 /* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
457 /* 0x004 Reserved */ 0,
458 /* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
459 /* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
460 /* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
461 /* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
462 /* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
463 /* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
464 /* 0x030 Reserved */ 0,
465 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
466 /* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
467 /* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
468 /* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
469 /* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
470 /* 0x048 Reserved */ 0, 0,
471 /* 0x050 Reserved */ 0, 0,
472 /* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
473 /* 0x060 Reserved */ 0,
474 /* 0x064 PMEN_REG */ 0, /* RO as we don't support PLMR and PHMR. */
475 /* 0x068 PLMBASE_REG */ 0, /* RO as we don't support PLMR. */
476 /* 0x06c PLMLIMIT_REG */ 0, /* RO as we don't support PLMR. */
477 /* 0x070 PHMBASE_REG */ 0, 0, /* RO as we don't support PHMR. */
478 /* 0x078 PHMLIMIT_REG */ 0, 0, /* RO as we don't support PHMR. */
479 /* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
480 /* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
481 /* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
482 /* 0x098 Reserved */ 0,
483 /* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
484 /* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
485 /* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
486 /* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
487 /* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
488 /* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
489 /* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
490 /* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
491 /* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
492 /* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
493 /* 0x0d8 Reserved */ 0,
494 /* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
495 /* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
496 /* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
497 /* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
498 /* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
499 /* 0x0f0 Reserved */ 0, 0,
500 /* 0x0f8 Reserved */ 0, 0,
501 /* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
502 /* 0x108 MTRRDEF_REG */ 0, 0, /* RO as we don't support MTS. */
503 /* 0x110 Reserved */ 0, 0,
504 /* 0x118 Reserved */ 0, 0,
505 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0, /* RO as we don't support MTS. */
506 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
507 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
508 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
509 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
510 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
511 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
512 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
513 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
514 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
515 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
516 /* 0x178 Reserved */ 0, 0,
517 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0, /* RO as we don't support MTS. */
518 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
519 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
520 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
521 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
522 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
523 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
524 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
525 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
526 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
527 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
528 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
529 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
530 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
531 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
532 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
533 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
534 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
535 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
536 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
537};
538AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
539
540/**
541 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
542 */
543static uint32_t const g_au32Rw1cMasks0[] =
544{
545 /* Offset Register Low High */
546 /* 0x000 VER_REG */ 0,
547 /* 0x004 Reserved */ 0,
548 /* 0x008 CAP_REG */ 0, 0,
549 /* 0x010 ECAP_REG */ 0, 0,
550 /* 0x018 GCMD_REG */ 0,
551 /* 0x01c GSTS_REG */ 0,
552 /* 0x020 RTADDR_REG */ 0, 0,
553 /* 0x028 CCMD_REG */ 0, 0,
554 /* 0x030 Reserved */ 0,
555 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
556 /* 0x038 FECTL_REG */ 0,
557 /* 0x03c FEDATA_REG */ 0,
558 /* 0x040 FEADDR_REG */ 0,
559 /* 0x044 FEUADDR_REG */ 0,
560 /* 0x048 Reserved */ 0, 0,
561 /* 0x050 Reserved */ 0, 0,
562 /* 0x058 AFLOG_REG */ 0, 0,
563 /* 0x060 Reserved */ 0,
564 /* 0x064 PMEN_REG */ 0,
565 /* 0x068 PLMBASE_REG */ 0,
566 /* 0x06c PLMLIMIT_REG */ 0,
567 /* 0x070 PHMBASE_REG */ 0, 0,
568 /* 0x078 PHMLIMIT_REG */ 0, 0,
569 /* 0x080 IQH_REG */ 0, 0,
570 /* 0x088 IQT_REG */ 0, 0,
571 /* 0x090 IQA_REG */ 0, 0,
572 /* 0x098 Reserved */ 0,
573 /* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
574 /* 0x0a0 IECTL_REG */ 0,
575 /* 0x0a4 IEDATA_REG */ 0,
576 /* 0x0a8 IEADDR_REG */ 0,
577 /* 0x0ac IEUADDR_REG */ 0,
578 /* 0x0b0 IQERCD_REG */ 0, 0,
579 /* 0x0b8 IRTA_REG */ 0, 0,
580 /* 0x0c0 PQH_REG */ 0, 0,
581 /* 0x0c8 PQT_REG */ 0, 0,
582 /* 0x0d0 PQA_REG */ 0, 0,
583 /* 0x0d8 Reserved */ 0,
584 /* 0x0dc PRS_REG */ 0,
585 /* 0x0e0 PECTL_REG */ 0,
586 /* 0x0e4 PEDATA_REG */ 0,
587 /* 0x0e8 PEADDR_REG */ 0,
588 /* 0x0ec PEUADDR_REG */ 0,
589 /* 0x0f0 Reserved */ 0, 0,
590 /* 0x0f8 Reserved */ 0, 0,
591 /* 0x100 MTRRCAP_REG */ 0, 0,
592 /* 0x108 MTRRDEF_REG */ 0, 0,
593 /* 0x110 Reserved */ 0, 0,
594 /* 0x118 Reserved */ 0, 0,
595 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
596 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
597 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
598 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
599 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
600 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
601 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
602 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
603 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
604 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
605 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
606 /* 0x178 Reserved */ 0, 0,
607 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
608 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
609 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
610 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
611 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
612 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
613 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
614 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
615 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
616 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
617 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
618 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
619 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
620 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
621 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
622 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
623 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
624 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
625 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
626 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
627};
628AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
629
630/**
631 * Read-write masks for DMAR registers (group 1).
632 */
633static uint32_t const g_au32RwMasks1[] =
634{
635 /* Offset Register Low High */
636 /* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
637 /* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
638 /* 0xe10 VCMD_REG */ 0, 0, /* RO: VCS not supported. */
639 /* 0xe18 VCMDRSVD_REG */ 0, 0,
640 /* 0xe20 VCRSP_REG */ 0, 0, /* RO: VCS not supported. */
641 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
642 /* 0xe30 Reserved */ 0, 0,
643 /* 0xe38 Reserved */ 0, 0,
644 /* 0xe40 Reserved */ 0, 0,
645 /* 0xe48 Reserved */ 0, 0,
646 /* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
647 /* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
648 /* 0xe60 Reserved */ 0, 0,
649 /* 0xe68 Reserved */ 0, 0,
650 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
651 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
652};
653AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
654AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
655
656/**
657 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
658 */
659static uint32_t const g_au32Rw1cMasks1[] =
660{
661 /* Offset Register Low High */
662 /* 0xe00 VCCAP_REG */ 0, 0,
663 /* 0xe08 VCMD_EO_REG */ 0, 0,
664 /* 0xe10 VCMD_REG */ 0, 0,
665 /* 0xe18 VCMDRSVD_REG */ 0, 0,
666 /* 0xe20 VCRSP_REG */ 0, 0,
667 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
668 /* 0xe30 Reserved */ 0, 0,
669 /* 0xe38 Reserved */ 0, 0,
670 /* 0xe40 Reserved */ 0, 0,
671 /* 0xe48 Reserved */ 0, 0,
672 /* 0xe50 IVA_REG */ 0, 0,
673 /* 0xe58 IOTLB_REG */ 0, 0,
674 /* 0xe60 Reserved */ 0, 0,
675 /* 0xe68 Reserved */ 0, 0,
676 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
677 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
678};
679AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
680
681/** Array of RW masks for each register group. */
682static uint8_t const *g_apbRwMasks[] = { (uint8_t *)&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
683
684/** Array of RW1C masks for each register group. */
685static uint8_t const *g_apbRw1cMasks[] = { (uint8_t *)&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
686
687/* Masks arrays must be identical in size (even bounds checking code assumes this). */
688AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
689
690/** Array of valid domain-ID bits. */
691static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
692AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
693
694
695#ifndef VBOX_DEVICE_STRUCT_TESTCASE
696/** @todo Add IOMMU struct size/alignment verification, see
697 * Devices/testcase/Makefile.kmk and
698 * Devices/testcase/tstDeviceStructSize[RC].cpp */
699
700/**
701 * Returns the number of supported adjusted guest-address width (SAGAW) in bits
702 * given a CAP_REG.SAGAW value.
703 *
704 * @returns Number of SAGAW bits.
705 * @param uSagaw The CAP_REG.SAGAW value.
706 */
707static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
708{
709 if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
710 return 30 + (uSagaw * 9);
711 return 0;
712}
713
714
715/**
716 * Returns the supported adjusted guest-address width (SAGAW) given the maximum
717 * guest address width (MGAW).
718 *
719 * @returns The CAP_REG.SAGAW value.
720 * @param uMgaw The CAP_REG.MGAW value.
721 */
722static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
723{
724 switch (uMgaw + 1)
725 {
726 case 39: return 1;
727 case 48: return 2;
728 case 57: return 3;
729 }
730 return 0;
731}
732
733
734/**
735 * Returns whether the interrupt remapping (IR) fault is qualified or not.
736 *
737 * @returns @c true if qualified, @c false otherwise.
738 * @param enmIrFault The interrupt remapping fault condition.
739 */
740static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
741{
742 switch (enmIrFault)
743 {
744 case VTDIRFAULT_IRTE_NOT_PRESENT:
745 case VTDIRFAULT_IRTE_PRESENT_RSVD:
746 case VTDIRFAULT_IRTE_PRESENT_INVALID:
747 case VTDIRFAULT_PID_READ_FAILED:
748 case VTDIRFAULT_PID_RSVD:
749 return true;
750 default:
751 return false;
752 }
753}
754
755
756/**
757 * Returns table translation mode's descriptive name.
758 *
759 * @returns The descriptive name.
760 * @param uTtm The RTADDR_REG.TTM value.
761 */
762static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
763{
764 Assert(!(uTtm & 3));
765 static const char* s_apszTtmNames[] =
766 {
767 "Legacy Mode",
768 "Scalable Mode",
769 "Reserved",
770 "Abort-DMA Mode"
771 };
772 return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
773}
774
775
776/**
777 * Gets the index of the group the register belongs to given its MMIO offset.
778 *
779 * @returns The group index.
780 * @param offReg The MMIO offset of the register.
781 * @param cbReg The size of the access being made (for bounds checking on
782 * debug builds).
783 */
784DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
785{
786 uint16_t const offLast = offReg + cbReg - 1;
787 AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
788 AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
789 return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
790}
791
792
793/**
794 * Gets the group the register belongs to given its MMIO offset.
795 *
796 * @returns Pointer to the first element of the register group.
797 * @param pThis The shared DMAR device state.
798 * @param offReg The MMIO offset of the register.
799 * @param cbReg The size of the access being made (for bounds checking on
800 * debug builds).
801 * @param pIdxGroup Where to store the index of the register group the register
802 * belongs to.
803 */
804DECLINLINE(uint8_t *) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
805{
806 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
807 uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
808 return apbRegs[*pIdxGroup];
809}
810
811
812/**
813 * Const/read-only version of dmarRegGetGroup.
814 *
815 * @copydoc dmarRegGetGroup
816 */
817DECLINLINE(uint8_t const*) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
818{
819 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
820 uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
821 return apbRegs[*pIdxGroup];
822}
823
824
825/**
826 * Writes a 32-bit register with the exactly the supplied value.
827 *
828 * @param pThis The shared DMAR device state.
829 * @param offReg The MMIO offset of the register.
830 * @param uReg The 32-bit value to write.
831 */
832static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
833{
834 uint8_t idxGroup;
835 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
836 NOREF(idxGroup);
837 *(uint32_t *)(pabRegs + offReg) = uReg;
838}
839
840
841/**
842 * Writes a 64-bit register with the exactly the supplied value.
843 *
844 * @param pThis The shared DMAR device state.
845 * @param offReg The MMIO offset of the register.
846 * @param uReg The 64-bit value to write.
847 */
848static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
849{
850 uint8_t idxGroup;
851 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
852 NOREF(idxGroup);
853 *(uint64_t *)(pabRegs + offReg) = uReg;
854}
855
856
857/**
858 * Reads a 32-bit register with exactly the value it contains.
859 *
860 * @returns The raw register value.
861 * @param pThis The shared DMAR device state.
862 * @param offReg The MMIO offset of the register.
863 */
864static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
865{
866 uint8_t idxGroup;
867 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
868 NOREF(idxGroup);
869 return *(uint32_t *)(pabRegs + offReg);
870}
871
872
873/**
874 * Reads a 64-bit register with exactly the value it contains.
875 *
876 * @returns The raw register value.
877 * @param pThis The shared DMAR device state.
878 * @param offReg The MMIO offset of the register.
879 */
880static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
881{
882 uint8_t idxGroup;
883 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
884 NOREF(idxGroup);
885 return *(uint64_t *)(pabRegs + offReg);
886}
887
888
889/**
890 * Reads a 32-bit register with exactly the value it contains along with their
891 * corresponding masks
892 *
893 * @param pThis The shared DMAR device state.
894 * @param offReg The MMIO offset of the register.
895 * @param puReg Where to store the raw 32-bit register value.
896 * @param pfRwMask Where to store the RW mask corresponding to this register.
897 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
898 */
899static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)
900{
901 uint8_t idxGroup;
902 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
903 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
904 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
905 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
906 *puReg = *(uint32_t *)(pabRegs + offReg);
907 *pfRwMask = *(uint32_t *)(pabRwMasks + offReg);
908 *pfRw1cMask = *(uint32_t *)(pabRw1cMasks + offReg);
909}
910
911
912/**
913 * Reads a 64-bit register with exactly the value it contains along with their
914 * corresponding masks.
915 *
916 * @param pThis The shared DMAR device state.
917 * @param offReg The MMIO offset of the register.
918 * @param puReg Where to store the raw 64-bit register value.
919 * @param pfRwMask Where to store the RW mask corresponding to this register.
920 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
921 */
922static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)
923{
924 uint8_t idxGroup;
925 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
926 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
927 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
928 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
929 *puReg = *(uint64_t *)(pabRegs + offReg);
930 *pfRwMask = *(uint64_t *)(pabRwMasks + offReg);
931 *pfRw1cMask = *(uint64_t *)(pabRw1cMasks + offReg);
932}
933
934
935/**
936 * Writes a 32-bit register as it would be when written by software.
937 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
938 *
939 * @returns The value that's actually written to the register.
940 * @param pThis The shared DMAR device state.
941 * @param offReg The MMIO offset of the register.
942 * @param uReg The 32-bit value to write.
943 * @param puPrev Where to store the register value prior to writing.
944 */
945static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
946{
947 /* Read current value from the 32-bit register. */
948 uint32_t uCurReg;
949 uint32_t fRwMask;
950 uint32_t fRw1cMask;
951 dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
952 *puPrev = uCurReg;
953
954 uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
955 uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
956 uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
957 uint32_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
958
959 /* Write new value to the 32-bit register. */
960 dmarRegWriteRaw32(pThis, offReg, uNewReg);
961 return uNewReg;
962}
963
964
965/**
966 * Writes a 64-bit register as it would be when written by software.
967 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
968 *
969 * @returns The value that's actually written to the register.
970 * @param pThis The shared DMAR device state.
971 * @param offReg The MMIO offset of the register.
972 * @param uReg The 64-bit value to write.
973 * @param puPrev Where to store the register value prior to writing.
974 */
975static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
976{
977 /* Read current value from the 64-bit register. */
978 uint64_t uCurReg;
979 uint64_t fRwMask;
980 uint64_t fRw1cMask;
981 dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
982 *puPrev = uCurReg;
983
984 uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
985 uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
986 uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
987 uint64_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
988
989 /* Write new value to the 64-bit register. */
990 dmarRegWriteRaw64(pThis, offReg, uNewReg);
991 return uNewReg;
992}
993
994
995/**
996 * Reads a 32-bit register as it would be when read by software.
997 *
998 * @returns The register value.
999 * @param pThis The shared DMAR device state.
1000 * @param offReg The MMIO offset of the register.
1001 */
1002static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1003{
1004 return dmarRegReadRaw32(pThis, offReg);
1005}
1006
1007
1008/**
1009 * Reads a 64-bit register as it would be when read by software.
1010 *
1011 * @returns The register value.
1012 * @param pThis The shared DMAR device state.
1013 * @param offReg The MMIO offset of the register.
1014 */
1015static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1016{
1017 return dmarRegReadRaw64(pThis, offReg);
1018}
1019
1020
1021/**
1022 * Modifies a 32-bit register.
1023 *
1024 * @param pThis The shared DMAR device state.
1025 * @param offReg The MMIO offset of the register.
1026 * @param fAndMask The AND mask (applied first).
1027 * @param fOrMask The OR mask.
1028 * @remarks This does NOT apply RO or RW1C masks while modifying the
1029 * register.
1030 */
1031static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1032{
1033 uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1034 uReg = (uReg & fAndMask) | fOrMask;
1035 dmarRegWriteRaw32(pThis, offReg, uReg);
1036}
1037
1038
1039/**
1040 * Modifies a 64-bit register.
1041 *
1042 * @param pThis The shared DMAR device state.
1043 * @param offReg The MMIO offset of the register.
1044 * @param fAndMask The AND mask (applied first).
1045 * @param fOrMask The OR mask.
1046 * @remarks This does NOT apply RO or RW1C masks while modifying the
1047 * register.
1048 */
1049static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1050{
1051 uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1052 uReg = (uReg & fAndMask) | fOrMask;
1053 dmarRegWriteRaw64(pThis, offReg, uReg);
1054}
1055
1056
1057/**
1058 * Checks if the invalidation-queue is empty.
1059 *
1060 * Extended version which optionally returns the current queue head and tail
1061 * offsets.
1062 *
1063 * @returns @c true if empty, @c false otherwise.
1064 * @param pThis The shared DMAR device state.
1065 * @param poffQh Where to store the queue head offset. Optional, can be NULL.
1066 * @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1067 */
1068static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t *poffQh, uint32_t *poffQt)
1069{
1070 /* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1071 uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1072 uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1073
1074 /* Don't bother masking QT, QH since other bits are RsvdZ. */
1075 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1076 Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1077 if (poffQh)
1078 *poffQh = uIqhReg;
1079 if (poffQt)
1080 *poffQt = uIqtReg;
1081 return uIqtReg == uIqhReg;
1082}
1083
1084
1085/**
1086 * Checks if the invalidation-queue is empty.
1087 *
1088 * @returns @c true if empty, @c false otherwise.
1089 * @param pThis The shared DMAR device state.
1090 */
1091static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1092{
1093 return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh */, NULL /* poffQt */);
1094}
1095
1096
1097/**
1098 * Checks if the invalidation-queue is capable of processing requests.
1099 *
1100 * @returns @c true if the invalidation-queue can process requests, @c false
1101 * otherwise.
1102 * @param pThis The shared DMAR device state.
1103 */
1104static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1105{
1106 /* Check if queued-invalidation is enabled. */
1107 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1108 if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1109 {
1110 /* Check if there are no invalidation-queue or timeout errors. */
1111 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1112 if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_ITE_MASK)))
1113 return true;
1114 }
1115 return false;
1116}
1117
1118
1119/**
1120 * Wakes up the invalidation-queue thread if there are requests to be processed.
1121 *
1122 * @param pDevIns The IOMMU device instance.
1123 */
1124static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1125{
1126 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1127 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1128 Log4Func(("\n"));
1129
1130 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1131
1132 if ( dmarInvQueueCanProcessRequests(pThis)
1133 && !dmarInvQueueIsEmpty(pThis))
1134 {
1135 Log4Func(("Signaling the invalidation-queue thread\n"));
1136 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1137 }
1138}
1139
1140
1141/**
1142 * Raises an event on behalf of the DMAR.
1143 *
1144 * These are events that are generated by the DMAR itself (like faults and
1145 * invalidation completion notifications).
1146 *
1147 * @param pDevIns The IOMMU device instance.
1148 * @param enmEventType The DMAR event type.
1149 *
1150 * @remarks The DMAR lock must be held while calling this function.
1151 */
1152static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1153{
1154 uint16_t offCtlReg;
1155 uint32_t fIntrMaskedMask;
1156 uint32_t fIntrPendingMask;
1157 uint16_t offMsiAddrLoReg;
1158 uint16_t offMsiAddrHiReg;
1159 uint16_t offMsiDataReg;
1160 switch (enmEventType)
1161 {
1162 case DMAREVENTTYPE_INV_COMPLETE:
1163 {
1164 offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1165 fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1166 fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1167 offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1168 offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1169 offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1170 break;
1171 }
1172
1173 case DMAREVENTTYPE_FAULT:
1174 {
1175 offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1176 fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1177 fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1178 offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1179 offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1180 offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1181 break;
1182 }
1183
1184 default:
1185 {
1186 /* Shouldn't ever happen. */
1187 AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1188 }
1189 }
1190
1191 /* Check if software has masked the interrupt. */
1192 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1193 uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1194 if (!(uCtlReg & fIntrMaskedMask))
1195 {
1196 /*
1197 * Interrupt is unmasked, raise it.
1198 * Interrupts generated by the DMAR have trigger mode and level as 0.
1199 * See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1200 */
1201 MSIMSG Msi;
1202 Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1203 Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1204 Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1205 Assert(Msi.Data.n.u1Level == 0);
1206 Assert(Msi.Data.n.u1TriggerMode == 0);
1207
1208 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1209 pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1210
1211 /* Clear interrupt pending bit. */
1212 uCtlReg &= ~fIntrPendingMask;
1213 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1214 }
1215 else
1216 {
1217 /* Interrupt is masked, set the interrupt pending bit. */
1218 uCtlReg |= fIntrPendingMask;
1219 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1220 }
1221}
1222
1223
1224/**
1225 * Raises an interrupt in response to a fault event.
1226 *
1227 * @param pDevIns The IOMMU device instance.
1228 *
1229 * @remarks This assumes the caller has already set the required status bits in the
1230 * FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1231 */
1232static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1233{
1234 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1235 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1236 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1237
1238#ifdef RT_STRICT
1239 {
1240 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1241 uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK | VTD_BF_FSTS_REG_PFO_MASK
1242 /* | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_AFO_MASK */ /* AFL not supported */
1243 /* | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK */ /* Device-TLBs not supported */
1244 | VTD_BF_FSTS_REG_IQE_MASK;
1245 Assert(uFstsReg & fFaultMask);
1246 }
1247#endif
1248 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1249}
1250
1251
1252#ifdef IN_RING3
1253/**
1254 * Raises an interrupt in response to an invalidation (complete) event.
1255 *
1256 * @param pDevIns The IOMMU device instance.
1257 */
1258static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1259{
1260 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1261 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1262 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1263
1264 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1265 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1266 {
1267 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1268 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1269 }
1270}
1271#endif /* IN_RING3 */
1272
1273
1274/**
1275 * Checks if a primary fault can be recorded.
1276 *
1277 * @returns @c true if the fault can be recorded, @c false otherwise.
1278 * @param pDevIns The IOMMU device instance.
1279 * @param pThis The shared DMAR device state.
1280 *
1281 * @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1282 * NOT call it unless there is a fault condition!
1283 */
1284static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1285{
1286 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1287 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1288
1289 uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1290 if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1291 return false;
1292
1293 /*
1294 * If we add more FRCD registers, we'll have to loop through them here.
1295 * Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1296 * nor do we need to increment FRI.
1297 *
1298 * See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1299 */
1300 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1301 uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1302 if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1303 {
1304 uFstsReg |= VTD_BF_FSTS_REG_PFO_MASK;
1305 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1306 return false;
1307 }
1308
1309 return true;
1310}
1311
1312
1313/**
1314 * Records a primary fault.
1315 *
1316 * @param pDevIns The IOMMU device instance.
1317 * @param enmDiag The diagnostic reason.
1318 * @param uFrcdHi The FRCD_HI_REG value for this fault.
1319 * @param uFrcdLo The FRCD_LO_REG value for this fault.
1320 */
1321static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint64_t uFrcdHi, uint64_t uFrcdLo)
1322{
1323 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1324 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1325
1326 DMAR_LOCK(pDevIns, pThisCC);
1327
1328 /* Update the diagnostic reason. */
1329 pThis->enmDiag = enmDiag;
1330
1331 /* We don't support advance fault logging. */
1332 Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1333
1334 if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1335 {
1336 /* Update the fault recording registers with the fault information. */
1337 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1338 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1339
1340 /* Set the Pending Primary Fault (PPF) field in the status register. */
1341 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1342
1343 /* Raise interrupt if necessary. */
1344 dmarFaultEventRaiseInterrupt(pDevIns);
1345 }
1346
1347 DMAR_UNLOCK(pDevIns, pThisCC);
1348}
1349
1350
1351/**
1352 * Records an interrupt request fault.
1353 *
1354 * @param pDevIns The IOMMU device instance.
1355 * @param enmDiag The diagnostic reason.
1356 * @param enmIrFault The interrupt fault reason.
1357 * @param idDevice The device ID (bus, device, function).
1358 * @param idxIntr The interrupt index.
1359 */
1360static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice, uint16_t idxIntr)
1361{
1362 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1363 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1364 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1365 uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1366 dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1367}
1368
1369
1370/**
1371 * Records a qualified interrupt request fault.
1372 *
1373 * Qualified faults are those that can be suppressed by software using the FPD bit
1374 * in the IRTE.
1375 *
1376 * @param pDevIns The IOMMU device instance.
1377 * @param enmDiag The diagnostic reason.
1378 * @param enmIrFault The interrupt fault reason.
1379 * @param idDevice The device ID (bus, device, function).
1380 * @param idxIntr The interrupt index.
1381 * @param pIrte The IRTE that caused this fault.
1382 */
1383static void dmarIrFaultRecordQualified(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice,
1384 uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1385{
1386 Assert(vtdIrFaultIsQualified(enmIrFault));
1387 Assert(pIrte);
1388 if (!(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK))
1389 return dmarIrFaultRecord(pDevIns, enmDiag, enmIrFault, idDevice, idxIntr);
1390}
1391
1392
1393/**
1394 * Records an address translation fault (extensive version).
1395 *
1396 * @param pDevIns The IOMMU device instance.
1397 * @param enmDiag The diagnostic reason.
1398 * @param enmAtFault The address translation fault reason.
1399 * @param idDevice The device ID (bus, device, function).
1400 * @param uFaultAddr The page address of the faulted request.
1401 * @param enmReqType The type of the faulted request.
1402 * @param uAddrType The address type of the faulted request (only applicable
1403 * when device-TLB is supported).
1404 * @param fHasPasid Whether the faulted request has a PASID TLP prefix.
1405 * @param uPasid The PASID value when a PASID TLP prefix is present.
1406 * @param fReqAttr The attributes of the faulted requested (VTD_REQ_ATTR_XXX).
1407 */
1408static void dmarAtFaultRecordEx(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, uint16_t idDevice,
1409 uint64_t uFaultAddr, VTDREQTYPE enmReqType, uint8_t uAddrType, bool fHasPasid, uint32_t uPasid,
1410 uint8_t fReqAttr)
1411{
1412 uint8_t const fType1 = enmReqType & RT_BIT(1);
1413 uint8_t const fType2 = enmReqType & RT_BIT(0);
1414 uint8_t const fExec = fReqAttr & VTD_REQ_ATTR_EXE;
1415 uint8_t const fPriv = fReqAttr & VTD_REQ_ATTR_PRIV;
1416 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1417 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1418 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1419 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1420 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1421 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1422 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1423 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, uAddrType)
1424 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1425 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1426 uint64_t const uFrcdLo = uFaultAddr & X86_PAGE_BASE_MASK;
1427 dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1428}
1429
1430
1431/**
1432 * Records an address translation fault.
1433 *
1434 * This is to be used when Device-TLB, and PASIDs are not supported or for requests
1435 * where the device-TLB and PASID is not relevant/present.
1436 *
1437 * @param pDevIns The IOMMU device instance.
1438 * @param enmDiag The diagnostic reason.
1439 * @param enmAtFault The address translation fault reason.
1440 * @param idDevice The device ID (bus, device, function).
1441 * @param uFaultAddr The page address of the faulted request.
1442 * @param enmReqType The type of the faulted request.
1443 */
1444static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, uint16_t idDevice,
1445 uint64_t uFaultAddr, VTDREQTYPE enmReqType)
1446{
1447 dmarAtFaultRecordEx(pDevIns, enmDiag, enmAtFault, idDevice, uFaultAddr, enmReqType, 0 /* uAddrType */,
1448 false /* fHasPasid */, 0 /* uPasid */, 0 /* fReqAttr */);
1449}
1450
1451
1452/**
1453 * Records a qualified address translation fault.
1454 *
1455 * Qualified faults are those that can be suppressed by software using the FPD bit
1456 * in the contex entry, scalable-mode context entry etc.
1457 *
1458 * This is to be used when Device-TLB, and PASIDs are not supported or for requests
1459 * where the device-TLB and PASID is not relevant/present.
1460 *
1461 * @param pDevIns The IOMMU device instance.
1462 * @param enmDiag The diagnostic reason.
1463 * @param enmAtFault The address translation fault reason.
1464 * @param idDevice The device ID (bus, device, function).
1465 * @param uFaultAddr The page address of the faulted request.
1466 * @param enmReqType The type of the faulted request.
1467 * @param uPagingEntryQw0 The first qword of the paging entry.
1468 */
1469static void dmarAtFaultQualifiedRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, uint16_t idDevice,
1470 uint64_t uFaultAddr, VTDREQTYPE enmReqType, uint64_t uPagingEntryQw0)
1471{
1472 AssertCompile( VTD_BF_0_CONTEXT_ENTRY_FPD_MASK == 0x2
1473 && VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK == 0x2
1474 && VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK == 0x2
1475 && VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK == 0x2
1476 && VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK == 0x2);
1477 if (!(uPagingEntryQw0 & VTD_BF_0_CONTEXT_ENTRY_FPD_MASK))
1478 dmarAtFaultRecordEx(pDevIns, enmDiag, enmAtFault, idDevice, uFaultAddr, enmReqType, 0 /* uAddrType */,
1479 false /* fHasPasid */, 0 /* uPasid */, 0 /* fReqAttr */);
1480}
1481
1482
1483/**
1484 * Records an IQE fault.
1485 *
1486 * @param pDevIns The IOMMU device instance.
1487 * @param enmIqei The IQE information.
1488 * @param enmDiag The diagnostic reason.
1489 */
1490static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1491{
1492 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1493 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1494
1495 DMAR_LOCK(pDevIns, pThisCC);
1496
1497 /* Update the diagnostic reason. */
1498 pThis->enmDiag = enmDiag;
1499
1500 /* Set the error bit. */
1501 uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1502 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1503
1504 /* Set the error information. */
1505 uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1506 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1507
1508 dmarFaultEventRaiseInterrupt(pDevIns);
1509
1510 DMAR_UNLOCK(pDevIns, pThisCC);
1511}
1512
1513
1514/**
1515 * Handles writes to GCMD_REG.
1516 *
1517 * @returns Strict VBox status code.
1518 * @param pDevIns The IOMMU device instance.
1519 * @param uGcmdReg The value written to GCMD_REG.
1520 */
1521static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1522{
1523 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1524 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1525 uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1526 uint64_t const fExtCapReg = pThis->fExtCapReg;
1527
1528 /* Queued-invalidation. */
1529 if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1530 && (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1531 {
1532 if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1533 {
1534 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1535 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1536 }
1537 else
1538 {
1539 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1540 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1541 }
1542 }
1543
1544 if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1545 {
1546 /* Set Interrupt Remapping Table Pointer (SIRTP). */
1547 if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1548 {
1549 /** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1550 * supported. */
1551 pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1552 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1553 }
1554
1555 /* Interrupt remapping. */
1556 if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1557 {
1558 if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1559 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1560 else
1561 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1562 }
1563
1564 /* Compatibility format interrupts. */
1565 if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1566 {
1567 if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1568 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1569 else
1570 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1571 }
1572 }
1573
1574 /* Set Root Table Pointer (SRTP). */
1575 if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1576 {
1577 /** @todo Perform global invalidation of all remapping translation caches when
1578 * ESRTPS is supported. */
1579 pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1580 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1581 }
1582
1583 /* Translation (DMA remapping). */
1584 if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1585 {
1586 if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1587 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1588 else
1589 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1590 }
1591
1592 return VINF_SUCCESS;
1593}
1594
1595
1596/**
1597 * Handles writes to CCMD_REG.
1598 *
1599 * @returns Strict VBox status code.
1600 * @param pDevIns The IOMMU device instance.
1601 * @param offReg The MMIO register offset.
1602 * @param cbReg The size of the MMIO access (in bytes).
1603 * @param uCcmdReg The value written to CCMD_REG.
1604 */
1605static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1606{
1607 /* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1608 if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1609 {
1610 /* Check if we need to invalidate the context-context. */
1611 bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1612 if (fIcc)
1613 {
1614 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1615 uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1616 if (uMajorVersion < 6)
1617 {
1618 /* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1619 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1620 if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1621 {
1622 /* Verify table translation mode is legacy. */
1623 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1624 if (fTtm == VTD_TTM_LEGACY_MODE)
1625 {
1626 /** @todo Invalidate. */
1627 return VINF_SUCCESS;
1628 }
1629 pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1630 }
1631 else
1632 pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1633 }
1634 else
1635 pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1636 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1637 }
1638 }
1639 return VINF_SUCCESS;
1640}
1641
1642
1643/**
1644 * Handles writes to FECTL_REG.
1645 *
1646 * @returns Strict VBox status code.
1647 * @param pDevIns The IOMMU device instance.
1648 * @param uFectlReg The value written to FECTL_REG.
1649 */
1650static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1651{
1652 /*
1653 * If software unmasks the interrupt when the interrupt is pending, we must raise
1654 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1655 */
1656 if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1657 && ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1658 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1659 return VINF_SUCCESS;
1660}
1661
1662
1663/**
1664 * Handles writes to FSTS_REG.
1665 *
1666 * @returns Strict VBox status code.
1667 * @param pDevIns The IOMMU device instance.
1668 * @param uFstsReg The value written to FSTS_REG.
1669 * @param uPrev The value in FSTS_REG prior to writing it.
1670 */
1671static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1672{
1673 /*
1674 * If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1675 * the interrupt pending (IP) bit must be cleared.
1676 *
1677 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1678 */
1679 uint32_t const fChanged = uPrev ^ uFstsReg;
1680 if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK
1681 | VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_PFO_MASK))
1682 {
1683 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1684 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1685 }
1686 return VINF_SUCCESS;
1687}
1688
1689
1690/**
1691 * Handles writes to IQT_REG.
1692 *
1693 * @returns Strict VBox status code.
1694 * @param pDevIns The IOMMU device instance.
1695 * @param offReg The MMIO register offset.
1696 * @param uIqtReg The value written to IQT_REG.
1697 */
1698static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1699{
1700 /* We only care about the low 32-bits, high 32-bits are reserved. */
1701 Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1702 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1703
1704 /* Paranoia. */
1705 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1706
1707 uint32_t const offQt = uIqtReg;
1708 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1709 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1710
1711 /* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1712 if ( fDw != VTD_IQA_REG_DW_256_BIT
1713 || !(offQt & RT_BIT(4)))
1714 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1715 else
1716 {
1717 /* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1718 dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1719 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1720 }
1721 return VINF_SUCCESS;
1722}
1723
1724
1725/**
1726 * Handles writes to IQA_REG.
1727 *
1728 * @returns Strict VBox status code.
1729 * @param pDevIns The IOMMU device instance.
1730 * @param offReg The MMIO register offset.
1731 * @param uIqaReg The value written to IQA_REG.
1732 */
1733static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1734{
1735 /* At present, we only care about the low 32-bits, high 32-bits are data. */
1736 Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1737
1738 /** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1739 * returns true? The Intel VT-d spec. doesn't state anywhere that it
1740 * cannot happen or that it's ignored when it does happen. */
1741
1742 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1743 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1744 if (fDw == VTD_IQA_REG_DW_256_BIT)
1745 {
1746 bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK | VTD_BF_ECAP_REG_ADMS_MASK));
1747 if (fSupports256BitDw)
1748 { /* likely */ }
1749 else
1750 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1751 }
1752 /* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1753
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/**
1759 * Handles writes to ICS_REG.
1760 *
1761 * @returns Strict VBox status code.
1762 * @param pDevIns The IOMMU device instance.
1763 * @param uIcsReg The value written to ICS_REG.
1764 */
1765static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1766{
1767 /*
1768 * If the IP field is set when software services the interrupt condition,
1769 * (by clearing the IWC field), the IP field must be cleared.
1770 */
1771 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1772 {
1773 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1774 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1775 }
1776 return VINF_SUCCESS;
1777}
1778
1779
1780/**
1781 * Handles writes to IECTL_REG.
1782 *
1783 * @returns Strict VBox status code.
1784 * @param pDevIns The IOMMU device instance.
1785 * @param uIectlReg The value written to IECTL_REG.
1786 */
1787static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1788{
1789 /*
1790 * If software unmasks the interrupt when the interrupt is pending, we must raise
1791 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1792 */
1793 if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1794 && ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1795 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1796 return VINF_SUCCESS;
1797}
1798
1799
1800/**
1801 * Handles writes to FRCD_REG (High 64-bits).
1802 *
1803 * @returns Strict VBox status code.
1804 * @param pDevIns The IOMMU device instance.
1805 * @param offReg The MMIO register offset.
1806 * @param cbReg The size of the MMIO access (in bytes).
1807 * @param uFrcdHiReg The value written to FRCD_REG.
1808 * @param uPrev The value in FRCD_REG prior to writing it.
1809 */
1810static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
1811{
1812 /* We only care about responding to high 32-bits, low 32-bits are read-only. */
1813 if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
1814 {
1815 /*
1816 * If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
1817 * Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
1818 * has only 1 FRCD register.
1819 *
1820 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1821 */
1822 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1823 uint64_t const fChanged = uPrev ^ uFrcdHiReg;
1824 if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
1825 {
1826 Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
1827 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1828 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
1829 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1830 }
1831 }
1832 return VINF_SUCCESS;
1833}
1834
1835
1836/**
1837 * Performs a PCI target abort for a DMA remapping (DR) operation.
1838 *
1839 * @param pDevIns The IOMMU device instance.
1840 */
1841static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
1842{
1843 /** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
1844 * as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
1845 * who knows. */
1846 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1847 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1848 PDMPciDevSetStatus(pPciDev, u16Status);
1849}
1850
1851
1852/**
1853 * Reads a root entry from guest memory.
1854 *
1855 * @returns VBox status code.
1856 * @param pDevIns The IOMMU device instance.
1857 * @param uRtaddrReg The current RTADDR_REG value.
1858 * @param idxRootEntry The index of the root entry to read.
1859 * @param pRootEntry Where to store the read root entry.
1860 */
1861static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
1862{
1863 size_t const cbRootEntry = sizeof(*pRootEntry);
1864 RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
1865 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
1866}
1867
1868
1869/**
1870 * Reads a context entry from guest memory.
1871 *
1872 * @returns VBox status code.
1873 * @param pDevIns The IOMMU device instance.
1874 * @param GCPhysCtxTable The physical address of the context table.
1875 * @param idxCtxEntry The index of the context entry to read.
1876 * @param pCtxEntry Where to store the read context entry.
1877 */
1878static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
1879{
1880 size_t const cbCtxEntry = sizeof(*pCtxEntry);
1881 RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
1882 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
1883}
1884
1885
1886/**
1887 * Handles remapping of DMA address requests in legacy mode.
1888 *
1889 * @returns VBox status code.
1890 * @param pDevIns The IOMMU device instance.
1891 * @param uRtaddrReg The current RTADDR_REG value.
1892 * @param pAddrRemap The DMA address remap info.
1893 */
1894static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARADDRMAP pAddrRemap)
1895{
1896 uint8_t const idxRootEntry = RT_HI_U8(pAddrRemap->idDevice);
1897 VTD_ROOT_ENTRY_T RootEntry;
1898 int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
1899 if (RT_SUCCESS(rc))
1900 {
1901 uint64_t const uRootEntryQword0 = RootEntry.au64[0];
1902 uint64_t const uRootEntryQword1 = RootEntry.au64[1];
1903 bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
1904 if (fRootEntryPresent)
1905 {
1906 if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
1907 && !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
1908 {
1909 RTGCPHYS const GCPhysCtxTable = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_CTP);
1910 uint8_t const idxCtxEntry = RT_LO_U8(pAddrRemap->idDevice);
1911 VTD_CONTEXT_ENTRY_T CtxEntry;
1912 rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
1913 if (RT_SUCCESS(rc))
1914 {
1915 uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
1916 uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
1917 bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
1918 if (fCtxEntryPresent)
1919 {
1920 if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
1921 && !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
1922 {
1923 /** @todo Handle context entry validation and processing. */
1924 return VERR_NOT_IMPLEMENTED;
1925 }
1926 else
1927 dmarAtFaultQualifiedRecord(pDevIns, kDmarDiag_Atf_Lct_3, VTDATFAULT_LCT_3, pAddrRemap->idDevice,
1928 pAddrRemap->uDmaAddr, pAddrRemap->enmReqType, uCtxEntryQword0);
1929 }
1930 else
1931 dmarAtFaultQualifiedRecord(pDevIns, kDmarDiag_Atf_Lct_2, VTDATFAULT_LCT_2, pAddrRemap->idDevice,
1932 pAddrRemap->uDmaAddr, pAddrRemap->enmReqType, uCtxEntryQword0);
1933 }
1934 else
1935 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_1, VTDATFAULT_LCT_1, pAddrRemap->idDevice, pAddrRemap->uDmaAddr,
1936 pAddrRemap->enmReqType);
1937 }
1938 else
1939 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_3, VTDATFAULT_LRT_3, pAddrRemap->idDevice, pAddrRemap->uDmaAddr,
1940 pAddrRemap->enmReqType);
1941 }
1942 else
1943 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_2, VTDATFAULT_LRT_2, pAddrRemap->idDevice, pAddrRemap->uDmaAddr,
1944 pAddrRemap->enmReqType);
1945 }
1946 else
1947 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_1, VTDATFAULT_LRT_1, pAddrRemap->idDevice, pAddrRemap->uDmaAddr,
1948 pAddrRemap->enmReqType);
1949 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
1950}
1951
1952
1953/**
1954 * Handles remapping of DMA address requests in scalable mode.
1955 *
1956 * @returns VBox status code.
1957 * @param pDevIns The IOMMU device instance.
1958 * @param uRtaddrReg The current RTADDR_REG value.
1959 * @param pAddrRemap The DMA address remap info.
1960 */
1961static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARADDRMAP pAddrRemap)
1962{
1963 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1964 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
1965 {
1966 RT_NOREF1(uRtaddrReg);
1967 return VERR_NOT_IMPLEMENTED;
1968 }
1969
1970 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_3, VTDATFAULT_RTA_1_3, pAddrRemap->idDevice, pAddrRemap->uDmaAddr,
1971 pAddrRemap->enmReqType);
1972 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
1973}
1974
1975
1976/**
1977 * Memory access bulk (one or more 4K pages) request from a device.
1978 *
1979 * @returns VBox status code.
1980 * @param pDevIns The IOMMU device instance.
1981 * @param idDevice The device ID (bus, device, function).
1982 * @param cIovas The number of addresses being accessed.
1983 * @param pauIovas The I/O virtual addresses for each page being accessed.
1984 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1985 * @param paGCPhysSpa Where to store the translated physical addresses.
1986 *
1987 * @thread Any.
1988 */
1989static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1990 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1991{
1992 RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1993 return VERR_NOT_IMPLEMENTED;
1994}
1995
1996
1997/**
1998 * Memory access transaction from a device.
1999 *
2000 * @returns VBox status code.
2001 * @param pDevIns The IOMMU device instance.
2002 * @param idDevice The device ID (bus, device, function).
2003 * @param uIova The I/O virtual address being accessed.
2004 * @param cbIova The size of the access.
2005 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2006 * @param pGCPhysSpa Where to store the translated system physical address.
2007 * @param pcbContiguous Where to store the number of contiguous bytes translated
2008 * and permission-checked.
2009 *
2010 * @thread Any.
2011 */
2012static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2013 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2014{
2015 /* Validate. */
2016 AssertPtr(pDevIns);
2017 AssertPtr(pGCPhysSpa);
2018 AssertPtr(pcbContiguous);
2019 Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2020 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2021
2022 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2023 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2024
2025 DMAR_LOCK(pDevIns, pThisCC);
2026 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2027 uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2028 DMAR_UNLOCK(pDevIns, pThisCC);
2029
2030 if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2031 {
2032 VTDREQTYPE enmReqType;
2033 if (fFlags & PDMIOMMU_MEM_F_READ)
2034 {
2035 enmReqType = VTDREQTYPE_READ;
2036 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2037 }
2038 else
2039 {
2040 enmReqType = VTDREQTYPE_WRITE;
2041 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2042 }
2043
2044 DMARADDRMAP AddrRemap;
2045 AddrRemap.idDevice = idDevice;
2046 AddrRemap.enmReqType = enmReqType;
2047 AddrRemap.uDmaAddr = uIova;
2048 AddrRemap.cbDma = cbIova;
2049 AddrRemap.GCPhysSpa = NIL_RTGCPHYS;
2050 AddrRemap.cbContiguous = 0;
2051
2052 int rc;
2053 uint8_t const fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2054 switch (fTtm)
2055 {
2056 case VTD_TTM_LEGACY_MODE:
2057 {
2058 rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, &AddrRemap);
2059 break;
2060 }
2061
2062 case VTD_TTM_SCALABLE_MODE:
2063 {
2064 rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, &AddrRemap);
2065 break;
2066 }
2067
2068 case VTD_TTM_ABORT_DMA_MODE:
2069 {
2070 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2071 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2072 dmarDrTargetAbort(pDevIns);
2073 else
2074 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_1, VTDATFAULT_RTA_1_1, idDevice, uIova, enmReqType);
2075 break;
2076 }
2077
2078 default:
2079 {
2080 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2081 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_2, VTDATFAULT_RTA_1_2, idDevice, uIova, enmReqType);
2082 break;
2083 }
2084 }
2085
2086 *pcbContiguous = AddrRemap.cbContiguous;
2087 *pGCPhysSpa = AddrRemap.GCPhysSpa;
2088 return rc;
2089 }
2090
2091 *pGCPhysSpa = uIova;
2092 *pcbContiguous = cbIova;
2093 return VINF_SUCCESS;
2094}
2095
2096
2097/**
2098 * Reads an IRTE from guest memory.
2099 *
2100 * @returns VBox status code.
2101 * @param pDevIns The IOMMU device instance.
2102 * @param uIrtaReg The IRTA_REG.
2103 * @param idxIntr The interrupt index.
2104 * @param pIrte Where to store the read IRTE.
2105 */
2106static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2107{
2108 Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2109
2110 size_t const cbIrte = sizeof(*pIrte);
2111 RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2112 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2113}
2114
2115
2116/**
2117 * Remaps the source MSI to the destination MSI given the IRTE.
2118 *
2119 * @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2120 * IRTA_REG.EIME).
2121 * @param pIrte The IRTE used for the remapping.
2122 * @param pMsiIn The source MSI (currently unused).
2123 * @param pMsiOut Where to store the remapped MSI.
2124 */
2125static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2126{
2127 NOREF(pMsiIn);
2128 uint64_t const uIrteQword0 = pIrte->au64[0];
2129
2130 /*
2131 * Let's start with a clean slate and preserve unspecified bits if the need arises.
2132 * For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2133 * but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2134 * it copies it from the source MSI.
2135 */
2136 RT_ZERO(*pMsiOut);
2137 pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2138 pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2139 pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2140 if (fExtIntrMode)
2141 {
2142 /*
2143 * Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2144 * high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2145 */
2146 uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2147 pMsiOut->Addr.n.u8DestId = idDest;
2148 pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2149 }
2150 else
2151 pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2152
2153 pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2154 pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2155 pMsiOut->Data.n.u1Level = 1;
2156 pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2157}
2158
2159
2160/**
2161 * Handles remapping of interrupts in remappable interrupt format.
2162 *
2163 * @returns VBox status code.
2164 * @param pDevIns The IOMMU device instance.
2165 * @param uIrtaReg The IRTA_REG.
2166 * @param idDevice The device ID (bus, device, function).
2167 * @param pMsiIn The source MSI.
2168 * @param pMsiOut Where to store the remapped MSI.
2169 */
2170static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2171{
2172 Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2173
2174 /* Validate reserved bits in the interrupt request. */
2175 AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2176 if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2177 {
2178 /* Compute the index into the interrupt remap table. */
2179 uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2180 uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2181 uint16_t const uHandle = uHandleLo | (uHandleHi << 15);
2182 bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2183 uint16_t const idxIntr = fSubHandleValid
2184 ? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2185 : uHandle;
2186
2187 /* Validate the index. */
2188 uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2189 if (idxIntr < cEntries)
2190 {
2191 /** @todo Implement and read IRTE from interrupt-entry cache here. */
2192
2193 /* Read the interrupt remap table entry (IRTE) at the index. */
2194 VTD_IRTE_T Irte;
2195 int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2196 if (RT_SUCCESS(rc))
2197 {
2198 /* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2199 uint64_t const uIrteQword0 = Irte.au64[0];
2200 uint64_t const uIrteQword1 = Irte.au64[1];
2201 bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2202 if (fPresent)
2203 {
2204 /* Validate reserved bits in the IRTE. */
2205 bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2206 uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2207 if ( !(uIrteQword0 & ~fQw0ValidMask)
2208 && !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2209 {
2210 /* Validate requester id (the device ID) as configured in the IRTE. */
2211 bool fSrcValid;
2212 DMARDIAG enmIrDiag;
2213 uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2214 switch (fSvt)
2215 {
2216 case VTD_IRTE_SVT_NONE:
2217 {
2218 fSrcValid = true;
2219 enmIrDiag = kDmarDiag_None;
2220 break;
2221 }
2222
2223 case VTD_IRTE_SVT_VALIDATE_MASK:
2224 {
2225 static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2226 uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2227 uint16_t const fValidMask = s_afValidMasks[idxMask];
2228 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2229 fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2230 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2231 break;
2232 }
2233
2234 case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2235 {
2236 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2237 uint8_t const uBusFirst = RT_HI_U8(idSource);
2238 uint8_t const uBusLast = RT_LO_U8(idSource);
2239 uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2240 fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2241 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2242 break;
2243 }
2244
2245 default:
2246 {
2247 fSrcValid = false;
2248 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2249 break;
2250 }
2251 }
2252
2253 if (fSrcValid)
2254 {
2255 uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2256 if (!fPostedMode)
2257 {
2258 dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2259 return VINF_SUCCESS;
2260 }
2261 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
2262 VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr, &Irte);
2263 }
2264 else
2265 dmarIrFaultRecordQualified(pDevIns, enmIrDiag, VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr,
2266 &Irte);
2267 }
2268 else
2269 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, VTDIRFAULT_IRTE_PRESENT_RSVD,
2270 idDevice, idxIntr, &Irte);
2271 }
2272 else
2273 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, VTDIRFAULT_IRTE_NOT_PRESENT,
2274 idDevice, idxIntr, &Irte);
2275 }
2276 else
2277 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, VTDIRFAULT_IRTE_READ_FAILED, idDevice, idxIntr);
2278 }
2279 else
2280 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, VTDIRFAULT_INTR_INDEX_INVALID, idDevice, idxIntr);
2281 }
2282 else
2283 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, VTDIRFAULT_REMAPPABLE_INTR_RSVD, idDevice, 0 /* idxIntr */);
2284 return VERR_IOMMU_INTR_REMAP_DENIED;
2285}
2286
2287
2288/**
2289 * Interrupt remap request from a device.
2290 *
2291 * @returns VBox status code.
2292 * @param pDevIns The IOMMU device instance.
2293 * @param idDevice The device ID (bus, device, function).
2294 * @param pMsiIn The source MSI.
2295 * @param pMsiOut Where to store the remapped MSI.
2296 */
2297static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2298{
2299 /* Validate. */
2300 Assert(pDevIns);
2301 Assert(pMsiIn);
2302 Assert(pMsiOut);
2303 RT_NOREF1(idDevice);
2304
2305 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2306 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2307
2308 /* Lock and read all registers required for interrupt remapping up-front. */
2309 DMAR_LOCK(pDevIns, pThisCC);
2310 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2311 uint64_t const uIrtaReg = pThis->uIrtaReg;
2312 DMAR_UNLOCK(pDevIns, pThisCC);
2313
2314 /* Check if interrupt remapping is enabled. */
2315 if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
2316 {
2317 bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
2318 if (!fIsRemappable)
2319 {
2320 /* Handle compatibility format interrupts. */
2321 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
2322
2323 /* If EIME is enabled or CFIs are disabled, block the interrupt. */
2324 if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
2325 || !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
2326 {
2327 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
2328 return VERR_IOMMU_INTR_REMAP_DENIED;
2329 }
2330
2331 /* Interrupt isn't subject to remapping, pass-through the interrupt. */
2332 *pMsiOut = *pMsiIn;
2333 return VINF_SUCCESS;
2334 }
2335
2336 /* Handle remappable format interrupts. */
2337 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
2338 return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
2339 }
2340
2341 /* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
2342 *pMsiOut = *pMsiIn;
2343 return VINF_SUCCESS;
2344}
2345
2346
2347/**
2348 * @callback_method_impl{FNIOMMMIONEWWRITE}
2349 */
2350static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2351{
2352 RT_NOREF1(pvUser);
2353 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2354
2355 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2356 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
2357
2358 uint16_t const offReg = off;
2359 uint16_t const offLast = offReg + cb - 1;
2360 if (DMAR_IS_MMIO_OFF_VALID(offLast))
2361 {
2362 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2363 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2364
2365 uint64_t uPrev = 0;
2366 uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, *(uint64_t *)pv, &uPrev)
2367 : dmarRegWrite32(pThis, offReg, *(uint32_t *)pv, (uint32_t *)&uPrev);
2368 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2369 switch (off)
2370 {
2371 case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
2372 {
2373 rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
2374 break;
2375 }
2376
2377 case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
2378 case VTD_MMIO_OFF_CCMD_REG + 4:
2379 {
2380 rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
2381 break;
2382 }
2383
2384 case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
2385 {
2386 rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
2387 break;
2388 }
2389
2390 case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
2391 {
2392 rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
2393 break;
2394 }
2395
2396 case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
2397 /* VTD_MMIO_OFF_IQT_REG + 4: */ /* High 32-bits reserved. */
2398 {
2399 rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
2400 break;
2401 }
2402
2403 case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
2404 /* VTD_MMIO_OFF_IQA_REG + 4: */ /* High 32-bits data. */
2405 {
2406 rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
2407 break;
2408 }
2409
2410 case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
2411 {
2412 rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
2413 break;
2414 }
2415
2416 case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
2417 {
2418 rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
2419 break;
2420 }
2421
2422 case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
2423 case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
2424 {
2425 rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
2426 break;
2427 }
2428 }
2429
2430 DMAR_UNLOCK(pDevIns, pThisCC);
2431 LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
2432 return rcStrict;
2433 }
2434
2435 return VINF_IOM_MMIO_UNUSED_FF;
2436}
2437
2438
2439/**
2440 * @callback_method_impl{FNIOMMMIONEWREAD}
2441 */
2442static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
2443{
2444 RT_NOREF1(pvUser);
2445 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2446
2447 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2448 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
2449
2450 uint16_t const offReg = off;
2451 uint16_t const offLast = offReg + cb - 1;
2452 if (DMAR_IS_MMIO_OFF_VALID(offLast))
2453 {
2454 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2455 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2456
2457 if (cb == 8)
2458 {
2459 *(uint64_t *)pv = dmarRegRead64(pThis, offReg);
2460 LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, *(uint64_t *)pv));
2461 }
2462 else
2463 {
2464 *(uint32_t *)pv = dmarRegRead32(pThis, offReg);
2465 LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, *(uint32_t *)pv));
2466 }
2467
2468 DMAR_UNLOCK(pDevIns, pThisCC);
2469 return VINF_SUCCESS;
2470 }
2471
2472 return VINF_IOM_MMIO_UNUSED_FF;
2473}
2474
2475
2476#ifdef IN_RING3
2477/**
2478 * Process requests in the invalidation queue.
2479 *
2480 * @param pDevIns The IOMMU device instance.
2481 * @param pvRequests The requests to process.
2482 * @param cbRequests The size of all requests (in bytes).
2483 * @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
2484 * VTD_IQA_REG_DW_256_BIT).
2485 * @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
2486 */
2487static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
2488 uint8_t fTtm)
2489{
2490#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
2491 do \
2492 { \
2493 dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
2494 return; \
2495 } while (0)
2496
2497 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2498 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2499
2500 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2501 Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
2502
2503 /*
2504 * The below check is redundant since we check both TTM and DW for each
2505 * descriptor type we process. However, the error reported by hardware
2506 * may differ hence this is kept commented out but not removed from the code
2507 * if we need to change this in the future.
2508 *
2509 * In our implementation, we would report the descriptor type as invalid,
2510 * while on real hardware it may report descriptor width as invalid.
2511 * The Intel VT-d spec. is not clear which error takes preceedence.
2512 */
2513#if 0
2514 /*
2515 * Verify that 128-bit descriptors are not used when operating in scalable mode.
2516 * We don't check this while software writes IQA_REG but defer it until now because
2517 * RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
2518 * -IS- performed when software writes IQA_REG since it only requires checking against
2519 * immutable hardware features.
2520 */
2521 if ( fTtm != VTD_TTM_SCALABLE_MODE
2522 || fDw != VTD_IQA_REG_DW_128_BIT)
2523 { /* likely */ }
2524 else
2525 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
2526#endif
2527
2528 /*
2529 * Process requests in FIFO order.
2530 */
2531 uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
2532 for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
2533 {
2534 uint64_t const *puDscQwords = (uint64_t const *)((uintptr_t)pvRequests + offDsc);
2535 uint64_t const uQword0 = puDscQwords[0];
2536 uint64_t const uQword1 = puDscQwords[1];
2537 uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
2538 switch (fDscType)
2539 {
2540 case VTD_INV_WAIT_DSC_TYPE:
2541 {
2542 /* Validate descriptor type. */
2543 if ( fTtm == VTD_TTM_LEGACY_MODE
2544 || fDw == VTD_IQA_REG_DW_256_BIT)
2545 { /* likely */ }
2546 else
2547 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
2548
2549 /* Validate reserved bits. */
2550 uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
2551 ? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
2552 : VTD_INV_WAIT_DSC_0_VALID_MASK;
2553 if ( !(uQword0 & ~fValidMask0)
2554 && !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
2555 { /* likely */ }
2556 else
2557 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
2558
2559 if (fDw == VTD_IQA_REG_DW_256_BIT)
2560 {
2561 if ( !puDscQwords[2]
2562 && !puDscQwords[3])
2563 { /* likely */ }
2564 else
2565 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
2566 }
2567
2568 /* Perform status write (this must be done prior to generating the completion interrupt). */
2569 bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
2570 if (fSw)
2571 {
2572 uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
2573 RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
2574 int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
2575 AssertRC(rc);
2576 }
2577
2578 /* Generate invalidation event interrupt. */
2579 bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
2580 if (fIf)
2581 {
2582 DMAR_LOCK(pDevIns, pThisR3);
2583 dmarR3InvEventRaiseInterrupt(pDevIns);
2584 DMAR_UNLOCK(pDevIns, pThisR3);
2585 }
2586
2587 STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
2588 break;
2589 }
2590
2591 case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
2592 case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
2593 case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
2594 case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
2595 case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
2596 case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
2597 case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
2598 default:
2599 {
2600 /* Stop processing further requests. */
2601 LogFunc(("Invalid descriptor type: %#x\n", fDscType));
2602 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
2603 }
2604 }
2605 }
2606#undef DMAR_IQE_FAULT_RECORD_RET
2607}
2608
2609
2610/**
2611 * The invalidation-queue thread.
2612 *
2613 * @returns VBox status code.
2614 * @param pDevIns The IOMMU device instance.
2615 * @param pThread The command thread.
2616 */
2617static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2618{
2619 NOREF(pThread);
2620 LogFlowFunc(("\n"));
2621
2622 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2623 return VINF_SUCCESS;
2624
2625 /*
2626 * Pre-allocate the maximum size of the invalidation queue allowed by the spec.
2627 * This prevents trashing the heap as well as deal with out-of-memory situations
2628 * up-front while starting the VM. It also simplifies the code from having to
2629 * dynamically grow/shrink the allocation based on how software sizes the queue.
2630 * Guests normally don't alter the queue size all the time, but that's not an
2631 * assumption we can make.
2632 */
2633 uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
2634 size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
2635 void *pvRequests = RTMemAllocZ(cbMaxQs);
2636 AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
2637
2638 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2639 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2640
2641 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2642 {
2643 /*
2644 * Sleep until we are woken up.
2645 */
2646 {
2647 int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
2648 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2649 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2650 break;
2651 }
2652
2653 DMAR_LOCK(pDevIns, pThisR3);
2654 if (dmarInvQueueCanProcessRequests(pThis))
2655 {
2656 uint32_t offQueueHead;
2657 uint32_t offQueueTail;
2658 bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
2659 if (!fIsEmpty)
2660 {
2661 /*
2662 * Get the current queue size, descriptor width, queue base address and the
2663 * table translation mode while the lock is still held.
2664 */
2665 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2666 uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
2667 uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
2668 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2669 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2670 RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
2671
2672 /* Paranoia. */
2673 Assert(cbQueue <= cbMaxQs);
2674 Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
2675 Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
2676 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueTail & RT_BIT(4)));
2677 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueHead & RT_BIT(4)));
2678 Assert(offQueueHead < cbQueue);
2679
2680 /*
2681 * A table translation mode of "reserved" isn't valid for any descriptor type.
2682 * However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
2683 * but if ESRTPS is support, we will perform a global invalidation when software
2684 * changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
2685 * So caching TTM while reading all descriptors should not be a problem.
2686 *
2687 * Also, validate the queue tail offset as it's mutable by software.
2688 */
2689 if ( fTtm != VTD_TTM_RSVD
2690 && offQueueTail < cbQueue)
2691 {
2692 /* Don't hold the lock while reading (a potentially large amount of) requests */
2693 DMAR_UNLOCK(pDevIns, pThisR3);
2694
2695 int rc;
2696 uint32_t cbRequests;
2697 if (offQueueTail > offQueueHead)
2698 {
2699 /* The requests have not wrapped around, read them in one go. */
2700 cbRequests = offQueueTail - offQueueHead;
2701 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
2702 }
2703 else
2704 {
2705 /* The requests have wrapped around, read forward and wrapped-around. */
2706 uint32_t const cbForward = cbQueue - offQueueHead;
2707 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
2708
2709 uint32_t const cbWrapped = offQueueTail;
2710 if ( RT_SUCCESS(rc)
2711 && cbWrapped > 0)
2712 {
2713 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
2714 (void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
2715 }
2716 cbRequests = cbForward + cbWrapped;
2717 }
2718
2719 /* Re-acquire the lock since we need to update device state. */
2720 DMAR_LOCK(pDevIns, pThisR3);
2721
2722 if (RT_SUCCESS(rc))
2723 {
2724 /* Indicate to software we've fetched all requests. */
2725 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
2726
2727 /* Don't hold the lock while processing requests. */
2728 DMAR_UNLOCK(pDevIns, pThisR3);
2729
2730 /* Process all requests. */
2731 Assert(cbRequests <= cbQueue);
2732 dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
2733
2734 /*
2735 * We've processed all requests and the lock shouldn't be held at this point.
2736 * Using 'continue' here allows us to skip re-acquiring the lock just to release
2737 * it again before going back to the thread loop. It's a bit ugly but it certainly
2738 * helps with performance.
2739 */
2740 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2741 continue;
2742 }
2743 else
2744 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
2745 }
2746 else
2747 {
2748 if (fTtm == VTD_TTM_RSVD)
2749 dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
2750 else
2751 {
2752 Assert(offQueueTail >= cbQueue);
2753 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
2754 }
2755 }
2756 }
2757 }
2758 DMAR_UNLOCK(pDevIns, pThisR3);
2759 }
2760
2761 RTMemFree(pvRequests);
2762 pvRequests = NULL;
2763
2764 LogFlowFunc(("Invalidation-queue thread terminating\n"));
2765 return VINF_SUCCESS;
2766}
2767
2768
2769/**
2770 * Wakes up the invalidation-queue thread so it can respond to a state
2771 * change.
2772 *
2773 * @returns VBox status code.
2774 * @param pDevIns The IOMMU device instance.
2775 * @param pThread The invalidation-queue thread.
2776 *
2777 * @thread EMT.
2778 */
2779static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2780{
2781 RT_NOREF(pThread);
2782 LogFlowFunc(("\n"));
2783 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2784 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
2785}
2786
2787
2788/**
2789 * @callback_method_impl{FNDBGFHANDLERDEV}
2790 */
2791static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2792{
2793 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2794 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2795 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
2796
2797 /*
2798 * We lock the device to get a consistent register state as it is
2799 * ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
2800 * ones we care about here) into temporaries and release the lock ASAP.
2801 *
2802 * Order of register being read and outputted is in accordance with the
2803 * spec. for no particular reason.
2804 * See Intel VT-d spec. 10.4 "Register Descriptions".
2805 */
2806 DMAR_LOCK(pDevIns, pThisR3);
2807
2808 DMARDIAG const enmDiag = pThis->enmDiag;
2809 uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
2810 uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
2811 uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
2812 uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
2813 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2814 uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
2815 uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
2816 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
2817 uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
2818 uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
2819 uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
2820 uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
2821 uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
2822 uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
2823 uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
2824 uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
2825 uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
2826 uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
2827 uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
2828 uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
2829 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2830 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
2831 uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
2832 uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
2833 uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
2834 uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
2835 uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
2836 uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
2837 uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
2838 uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
2839 uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
2840 uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
2841 uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
2842 uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
2843 uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
2844 uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
2845 uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
2846 uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
2847
2848 DMAR_UNLOCK(pDevIns, pThisR3);
2849
2850 const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
2851 pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
2852 pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
2853
2854 /*
2855 * Non-verbose output.
2856 */
2857 if (!fVerbose)
2858 {
2859 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2860 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2861 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2862 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2863 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2864 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2865 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2866 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2867 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2868 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2869 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2870 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2871 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2872 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2873 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2874 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2875 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2876 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2877 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2878 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2879 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2880 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2881 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2882 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2883 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2884 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2885 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2886 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2887 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2888 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2889 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2890 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2891 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2892 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2893 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2894 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2895 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2896 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2897 pHlp->pfnPrintf(pHlp, "\n");
2898 return;
2899 }
2900
2901 /*
2902 * Verbose output.
2903 */
2904 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2905 {
2906 pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
2907 pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
2908 }
2909 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2910 {
2911 uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
2912 uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
2913 uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
2914 pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
2915 pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
2916 pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
2917 pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
2918 pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
2919 pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
2920 pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
2921 pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
2922 pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
2923 pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
2924 pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
2925 pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
2926 pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
2927 pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
2928 pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
2929 pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
2930 pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
2931 pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
2932 pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
2933 pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
2934 pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
2935 }
2936 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2937 {
2938 uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
2939 pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
2940 pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
2941 pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
2942 pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
2943 pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
2944 pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
2945 pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
2946 pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
2947 pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
2948 pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
2949 pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
2950 pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
2951 pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
2952 pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
2953 pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
2954 pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
2955 pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
2956 pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
2957 pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
2958 pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
2959 pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
2960 pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
2961 pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
2962 pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
2963 pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
2964 pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
2965 pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
2966 pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
2967 pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
2968 }
2969 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2970 {
2971 uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
2972 pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
2973 pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
2974 pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
2975 pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
2976 pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
2977 pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2978 pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2979 pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
2980 pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
2981 }
2982 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2983 {
2984 uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
2985 pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
2986 pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
2987 pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
2988 pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
2989 pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
2990 pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
2991 pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
2992 pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
2993 pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
2994 }
2995 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2996 {
2997 uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2998 pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
2999 pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3000 }
3001 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3002 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3003 {
3004 pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3005 pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3006 pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3007 pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3008 pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3009 pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3010 pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3011 pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3012 }
3013 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3014 {
3015 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3016 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3017 }
3018 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3019 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3020 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3021 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3022 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3023 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3024 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3025 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3026 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3027 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3028 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3029 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3030 {
3031 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3032 uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3033 uint8_t const cQueuePages = 1 << fQs;
3034 pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3035 pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3036 }
3037 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3038 {
3039 pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3040 }
3041 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3042 {
3043 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3044 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3045 }
3046 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3047 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3048 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3049 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3050 {
3051 pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3052 pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3053 pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3054 }
3055 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3056 {
3057 uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3058 uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3059 pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3060 pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3061 pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3062 }
3063 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3064 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3065 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3066 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3067 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3068 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3069 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3070 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3071 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3072 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3073 pHlp->pfnPrintf(pHlp, "\n");
3074}
3075
3076
3077/**
3078 * Initializes all registers in the DMAR unit.
3079 *
3080 * @param pDevIns The IOMMU device instance.
3081 */
3082static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3083{
3084 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3085
3086 /*
3087 * Wipe all registers (required on reset).
3088 */
3089 RT_ZERO(pThis->abRegs0);
3090 RT_ZERO(pThis->abRegs1);
3091
3092 /*
3093 * Initialize registers not mutable by software prior to initializing other registers.
3094 */
3095 /* VER_REG */
3096 {
3097 pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3098 | RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3099 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3100 }
3101
3102 uint8_t const fFlts = 1; /* First-Level translation support. */
3103 uint8_t const fSlts = 1; /* Second-Level translation support. */
3104 uint8_t const fPt = 1; /* Pass-Through support. */
3105 uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3106 uint8_t const fNest = 0; /* Nested translation support. */
3107
3108 /* CAP_REG */
3109 {
3110 uint8_t cGstPhysAddrBits;
3111 uint8_t cGstLinearAddrBits;
3112 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3113
3114 uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
3115 uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3116 uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
3117 uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
3118 uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
3119 | ((fSl2mp & fFl1gp) & RT_BIT(1));
3120 uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3121 : X86_PAGE_2M_SHIFT)
3122 - X86_PAGE_4K_SHIFT;
3123 uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3124 uint8_t const fPsi = 1; /* Page selective invalidation. */
3125 uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3126 uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3127 uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3128 uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3129 uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3130 AssertCompile(DMAR_ND <= 6);
3131
3132 pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3133 | RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3134 | RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3135 | RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3136 | RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3137 | RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3138 | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
3139 | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3140 | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3141 | RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3142 | RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3143 | RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3144 | RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3145 | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3146 | RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3147 | RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3148 | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3149 | RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3150 | RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3151 | RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3152 | RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3153 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3154 }
3155
3156 /* ECAP_REG */
3157 {
3158 uint8_t const fQi = 1; /* Queued-invalidations. */
3159 uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3160 uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3161 uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3162 uint8_t const fEim = 1; /* Extended interrupt mode.*/
3163 uint8_t const fAdms = 1; /* Abort DMA mode support. */
3164
3165 pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3166 | RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3167 | RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3168 | RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3169 | RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3170 | RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3171 | RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3172 | RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3173 | RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3174 | RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3175 | RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3176 | RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3177 | RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
3178 | RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3179 | RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3180 | RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
3181 | RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3182 | RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
3183 | RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3184 | RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3185 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3186 | RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3187 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3188 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3189 | RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3190 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3191 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3192 | RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3193 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3194 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3195 }
3196
3197 /*
3198 * Initialize registers mutable by software.
3199 */
3200 /* FECTL_REG */
3201 {
3202 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3203 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3204 }
3205
3206 /* ICETL_REG */
3207 {
3208 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3209 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3210 }
3211
3212#ifdef VBOX_STRICT
3213 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3214 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3215#endif
3216}
3217
3218
3219/**
3220 * @interface_method_impl{PDMDEVREG,pfnReset}
3221 */
3222static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
3223{
3224 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3225 LogFlowFunc(("\n"));
3226
3227 DMAR_LOCK(pDevIns, pThisR3);
3228 dmarR3RegsInit(pDevIns);
3229 DMAR_UNLOCK(pDevIns, pThisR3);
3230}
3231
3232
3233/**
3234 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3235 */
3236static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
3237{
3238 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3239 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3240 LogFlowFunc(("\n"));
3241
3242 DMAR_LOCK(pDevIns, pThisR3);
3243
3244 if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
3245 {
3246 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
3247 pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
3248 }
3249
3250 DMAR_UNLOCK(pDevIns, pThisR3);
3251 return VINF_SUCCESS;
3252}
3253
3254
3255/**
3256 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3257 */
3258static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3259{
3260 RT_NOREF(pCfg);
3261
3262 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3263 PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
3264 pThisR3->pDevInsR3 = pDevIns;
3265
3266 LogFlowFunc(("iInstance=%d\n", iInstance));
3267 NOREF(iInstance);
3268
3269 /*
3270 * Register the IOMMU with PDM.
3271 */
3272 PDMIOMMUREGR3 IommuReg;
3273 RT_ZERO(IommuReg);
3274 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3275 IommuReg.pfnMemAccess = iommuIntelMemAccess;
3276 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3277 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3278 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3279 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3280 if (RT_FAILURE(rc))
3281 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3282 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3283 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3284 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3285 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3286 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3287 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3288 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3289 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3290 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
3291 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
3292 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
3293 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
3294
3295 /*
3296 * Use PDM's critical section (via helpers) for the IOMMU device.
3297 */
3298 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3299 AssertRCReturn(rc, rc);
3300
3301 /*
3302 * Initialize PCI configuration registers.
3303 */
3304 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3305 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3306
3307 /* Header. */
3308 PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3309 PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3310 PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3311 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3312 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
3313 PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
3314 PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3315 PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3316
3317 /** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
3318 PDMPciDevSetStatus(pPciDev, 0);
3319 PDMPciDevSetCapabilityList(pPciDev, 0);
3320
3321 /** @todo VTBAR at 0x180? */
3322
3323 /*
3324 * Register the PCI function with PDM.
3325 */
3326 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3327 AssertLogRelRCReturn(rc, rc);
3328
3329 /** @todo Register MSI but what's the MSI capability offset? */
3330#if 0
3331 /*
3332 * Register MSI support for the PCI device.
3333 * This must be done -after- registering it as a PCI device!
3334 */
3335#endif
3336
3337 /*
3338 * Register MMIO region.
3339 */
3340 AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
3341 rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
3342 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
3343 &pThis->hMmio);
3344 AssertLogRelRCReturn(rc, rc);
3345
3346 /*
3347 * Register debugger info items.
3348 */
3349 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
3350 AssertLogRelRCReturn(rc, rc);
3351
3352#ifdef VBOX_WITH_STATISTICS
3353 /*
3354 * Statistics.
3355 */
3356 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
3357 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
3358
3359 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
3360 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
3361
3362 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
3363 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
3364 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
3365 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
3366
3367 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
3368 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
3369
3370 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
3371 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
3372
3373 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
3374 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
3375
3376 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
3377 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
3378
3379 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
3380 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
3381 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
3382 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
3383 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
3384 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
3385 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
3386 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
3387#endif
3388
3389 /*
3390 * Initialize registers.
3391 */
3392 dmarR3RegsInit(pDevIns);
3393
3394 /*
3395 * Create invalidation-queue thread and semaphore.
3396 */
3397 char szInvQueueThread[32];
3398 RT_ZERO(szInvQueueThread);
3399 RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
3400 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
3401 0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
3402 AssertLogRelRCReturn(rc, rc);
3403
3404 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
3405 AssertLogRelRCReturn(rc, rc);
3406
3407 /*
3408 * Log some of the features exposed to software.
3409 */
3410 uint32_t const uVerReg = pThis->uVerReg;
3411 uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
3412 uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW));
3413 uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
3414 uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
3415 LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
3416 DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
3417 pThis->fCapReg, pThis->fExtCapReg, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
3418
3419 return VINF_SUCCESS;
3420}
3421
3422#else
3423
3424/**
3425 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
3426 */
3427static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
3428{
3429 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3430 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3431 PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
3432 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
3433
3434 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
3435 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3436 AssertRCReturn(rc, rc);
3437
3438 /* Set up the MMIO RZ handlers. */
3439 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
3440 AssertRCReturn(rc, rc);
3441
3442 /* Set up the IOMMU RZ callbacks. */
3443 PDMIOMMUREGCC IommuReg;
3444 RT_ZERO(IommuReg);
3445 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3446 IommuReg.idxIommu = pThis->idxIommu;
3447 IommuReg.pfnMemAccess = iommuIntelMemAccess;
3448 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3449 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3450 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3451
3452 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
3453 AssertRCReturn(rc, rc);
3454 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
3455 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3456 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3457 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
3458 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
3459 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
3460 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
3461
3462 return VINF_SUCCESS;
3463}
3464
3465#endif
3466
3467
3468/**
3469 * The device registration structure.
3470 */
3471PDMDEVREG const g_DeviceIommuIntel =
3472{
3473 /* .u32Version = */ PDM_DEVREG_VERSION,
3474 /* .uReserved0 = */ 0,
3475 /* .szName = */ "iommu-intel",
3476 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
3477 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
3478 /* .cMaxInstances = */ 1,
3479 /* .uSharedVersion = */ 42,
3480 /* .cbInstanceShared = */ sizeof(DMAR),
3481 /* .cbInstanceCC = */ sizeof(DMARCC),
3482 /* .cbInstanceRC = */ sizeof(DMARRC),
3483 /* .cMaxPciDevices = */ 1,
3484 /* .cMaxMsixVectors = */ 0,
3485 /* .pszDescription = */ "IOMMU (Intel)",
3486#if defined(IN_RING3)
3487 /* .pszRCMod = */ "VBoxDDRC.rc",
3488 /* .pszR0Mod = */ "VBoxDDR0.r0",
3489 /* .pfnConstruct = */ iommuIntelR3Construct,
3490 /* .pfnDestruct = */ iommuIntelR3Destruct,
3491 /* .pfnRelocate = */ NULL,
3492 /* .pfnMemSetup = */ NULL,
3493 /* .pfnPowerOn = */ NULL,
3494 /* .pfnReset = */ iommuIntelR3Reset,
3495 /* .pfnSuspend = */ NULL,
3496 /* .pfnResume = */ NULL,
3497 /* .pfnAttach = */ NULL,
3498 /* .pfnDetach = */ NULL,
3499 /* .pfnQueryInterface = */ NULL,
3500 /* .pfnInitComplete = */ NULL,
3501 /* .pfnPowerOff = */ NULL,
3502 /* .pfnSoftReset = */ NULL,
3503 /* .pfnReserved0 = */ NULL,
3504 /* .pfnReserved1 = */ NULL,
3505 /* .pfnReserved2 = */ NULL,
3506 /* .pfnReserved3 = */ NULL,
3507 /* .pfnReserved4 = */ NULL,
3508 /* .pfnReserved5 = */ NULL,
3509 /* .pfnReserved6 = */ NULL,
3510 /* .pfnReserved7 = */ NULL,
3511#elif defined(IN_RING0)
3512 /* .pfnEarlyConstruct = */ NULL,
3513 /* .pfnConstruct = */ iommuIntelRZConstruct,
3514 /* .pfnDestruct = */ NULL,
3515 /* .pfnFinalDestruct = */ NULL,
3516 /* .pfnRequest = */ NULL,
3517 /* .pfnReserved0 = */ NULL,
3518 /* .pfnReserved1 = */ NULL,
3519 /* .pfnReserved2 = */ NULL,
3520 /* .pfnReserved3 = */ NULL,
3521 /* .pfnReserved4 = */ NULL,
3522 /* .pfnReserved5 = */ NULL,
3523 /* .pfnReserved6 = */ NULL,
3524 /* .pfnReserved7 = */ NULL,
3525#elif defined(IN_RC)
3526 /* .pfnConstruct = */ iommuIntelRZConstruct,
3527 /* .pfnReserved0 = */ NULL,
3528 /* .pfnReserved1 = */ NULL,
3529 /* .pfnReserved2 = */ NULL,
3530 /* .pfnReserved3 = */ NULL,
3531 /* .pfnReserved4 = */ NULL,
3532 /* .pfnReserved5 = */ NULL,
3533 /* .pfnReserved6 = */ NULL,
3534 /* .pfnReserved7 = */ NULL,
3535#else
3536# error "Not in IN_RING3, IN_RING0 or IN_RC!"
3537#endif
3538 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
3539};
3540
3541#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
3542
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