DevIommuIntel.cpp@ 88841

最後變更在這個檔案從88841是 88841,由 vboxsync 提交於 4 年前
Intel IOMMU: bugref:9967 Interrupt remapping WIP.
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1	/* $Id: DevIommuIntel.cpp 88841 2021-05-03 16:13:23Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock and is not expected to fail. */
67	#define DMAR_LOCK(a_pDevIns, a_pThisCC) \
68	do { \
69	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED); \
70	Assert(rcLock == VINF_SUCCESS); \
71	} while (0)
72
73	/** Release the DMAR lock. */
74	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
75
76	/** Asserts that the calling thread owns the DMAR lock. */
77	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
78	do { \
79	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
80	RT_NOREF1(a_pThisCC); \
81	} while (0)
82
83	/** Asserts that the calling thread does not own the DMAR lock. */
84	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
85	do { \
86	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
87	RT_NOREF1(a_pThisCC); \
88	} while (0)
89
90	/** The number of fault recording registers our implementation supports.
91	* Normal guest operation shouldn't trigger faults anyway, so we only support the
92	* minimum number of registers (which is 1).
93	*
94	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
95	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
96
97	/** Offset of first register in group 0. */
98	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
99	/** Offset of last register in group 0 (inclusive). */
100	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
101	/** Last valid offset in group 0 (exclusive). */
102	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
103	/** Size of the group 0 (in bytes). */
104	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
105	/*< Implementation-specific MMIO offset of IVA_REG. /
106	#define DMAR_MMIO_OFF_IVA_REG 0xe50
107	/*< Implementation-specific MMIO offset of IOTLB_REG. /
108	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
109	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
110	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
111	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
112	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
113	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
114
115	/** Offset of first register in group 1. */
116	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
117	/** Offset of last register in group 1 (inclusive). */
118	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
119	/** Last valid offset in group 1 (exclusive). */
120	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
121	/** Size of the group 1 (in bytes). */
122	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
123
124	/** DMAR implementation's major version number (exposed to software).
125	* We report 6 as the major version since we support queued-invalidations as
126	* software may make assumptions based on that.
127	*
128	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
129	#define DMAR_VER_MAJOR 6
130	/** DMAR implementation's minor version number (exposed to software). */
131	#define DMAR_VER_MINOR 0
132
133	/** Release log prefix string. */
134	#define DMAR_LOG_PFX "Intel-IOMMU"
135	/** The current saved state version. */
136	#define DMAR_SAVED_STATE_VERSION 1
137
138
139	/*********************************************************************************************************************************
140	* Structures and Typedefs *
141	*********************************************************************************************************************************/
142	/**
143	* DMAR error diagnostics.
144	* Sorted alphabetically so it's easier to add and locate items, no other reason.
145	*
146	* @note Members of this enum are used as array indices, so no gaps in enum
147	* values are not allowed. Update g_apszDmarDiagDesc when you modify
148	* fields in this enum.
149	*/
150	typedef enum
151	{
152	kDmarDiag_None = 0,
153	kDmarDiag_CcmdReg_NotSupported,
154	kDmarDiag_CcmdReg_Qi_Enabled,
155	kDmarDiag_CcmdReg_Ttm_Invalid,
156	kDmarDiag_IqaReg_Dsc_Fetch_Error,
157	kDmarDiag_IqaReg_Dw_128_Invalid,
158	kDmarDiag_IqaReg_Dw_256_Invalid,
159	kDmarDiag_Iqei_Dsc_Type_Invalid,
160	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
161	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
162	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
163	kDmarDiag_Iqei_Ttm_Rsvd,
164	kDmarDiag_IqtReg_Qt_Invalid,
165	kDmarDiag_IqtReg_Qt_NotAligned,
166	/* Member for determining array index limit. */
167	kDmarDiag_End,
168	/* Type size hack. */
169	kDmarDiag_32Bit_Hack = 0x7fffffff
170	} DMARDIAG;
171	AssertCompileSize(DMARDIAG, 4);
172
173	/** DMAR diagnostic enum description expansion.
174	* The below construct ensures typos in the input to this macro are caught
175	* during compile time. */
176	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
177
178	/** DMAR diagnostics description for members in DMARDIAG. */
179	static const char *const g_apszDmarDiagDesc[] =
180	{
181	DMARDIAG_DESC(None ),
182	DMARDIAG_DESC(CcmdReg_NotSupported ),
183	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
184	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
185	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
186	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
187	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
188	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
189	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
190	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
191	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
192	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
193	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
194	DMARDIAG_DESC(IqtReg_Qt_NotAligned )
195	/* kDmarDiag_End */
196	};
197	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
198	#undef DMARDIAG_DESC
199
200	/**
201	* The shared DMAR device state.
202	*/
203	typedef struct DMAR
204	{
205	/** IOMMU device index. */
206	uint32_t idxIommu;
207	/** DMAR magic. */
208	uint32_t u32Magic;
209
210	/** Registers (group 0). */
211	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
212	/** Registers (group 1). */
213	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
214
215	/** @name Lazily activated registers.
216	* These are the active values for lazily activated registers. Software is free to
217	* modify the actual register values while remapping/translation is enabled but they
218	* take effect only when explicitly signaled by software, hence we need to hold the
219	* active values separately.
220	* @{ */
221	/** Currently active IRTA_REG. */
222	uint64_t uIrtaReg;
223	/** Currently active RTADDR_REG. */
224	uint64_t uRtaddrReg;
225	/** @} */
226
227	/** @name Register copies for a tiny bit faster and more convenient access.
228	* @{ */
229	/** Copy of VER_REG. */
230	uint8_t uVerReg;
231	/** Alignment. */
232	uint8_t abPadding[7];
233	/** Copy of CAP_REG. */
234	uint64_t fCapReg;
235	/** Copy of ECAP_REG. */
236	uint64_t fExtCapReg;
237	/** @} */
238
239	/** The event semaphore the invalidation-queue thread waits on. */
240	SUPSEMEVENT hEvtInvQueue;
241	/** Whether the invalidation-queue thread has been signaled. */
242	bool volatile fInvQueueThreadSignaled;
243	/** Padding. */
244	bool afPadding0[3];
245	/** Error diagnostic. */
246	DMARDIAG enmDiag;
247	/** The MMIO handle. */
248	IOMMMIOHANDLE hMmio;
249
250	#ifdef VBOX_WITH_STATISTICS
251	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
252	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
253	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
254	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
255
256	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
257	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
258
259	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
260	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
261	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
262	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
263
264	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
265	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
266	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
267	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
268
269	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
270	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
271	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
272	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
273	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
274	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
275	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
276	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
277	#endif
278	} DMAR;
279	/** Pointer to the DMAR device state. */
280	typedef DMAR *PDMAR;
281	/** Pointer to the const DMAR device state. */
282	typedef DMAR const *PCDMAR;
283	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
284	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
285
286	/**
287	* The ring-3 DMAR device state.
288	*/
289	typedef struct DMARR3
290	{
291	/** Device instance. */
292	PPDMDEVINSR3 pDevInsR3;
293	/** The IOMMU helper. */
294	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
295	/** The invalidation-queue thread. */
296	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
297	} DMARR3;
298	/** Pointer to the ring-3 DMAR device state. */
299	typedef DMARR3 *PDMARR3;
300	/** Pointer to the const ring-3 DMAR device state. */
301	typedef DMARR3 const *PCDMARR3;
302
303	/**
304	* The ring-0 DMAR device state.
305	*/
306	typedef struct DMARR0
307	{
308	/** Device instance. */
309	PPDMDEVINSR0 pDevInsR0;
310	/** The IOMMU helper. */
311	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
312	} DMARR0;
313	/** Pointer to the ring-0 IOMMU device state. */
314	typedef DMARR0 *PDMARR0;
315	/** Pointer to the const ring-0 IOMMU device state. */
316	typedef DMARR0 const *PCDMARR0;
317
318	/**
319	* The raw-mode DMAR device state.
320	*/
321	typedef struct DMARRC
322	{
323	/** Device instance. */
324	PPDMDEVINSRC pDevInsRC;
325	/** The IOMMU helper. */
326	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
327	} DMARRC;
328	/** Pointer to the raw-mode DMAR device state. */
329	typedef DMARRC *PDMARRC;
330	/** Pointer to the const raw-mode DMAR device state. */
331	typedef DMARRC const *PCIDMARRC;
332
333	/** The DMAR device state for the current context. */
334	typedef CTX_SUFF(DMAR) DMARCC;
335	/** Pointer to the DMAR device state for the current context. */
336	typedef CTX_SUFF(PDMAR) PDMARCC;
337	/** Pointer to the const DMAR device state for the current context. */
338	typedef CTX_SUFF(PDMAR) const PCDMARCC;
339
340
341	/*********************************************************************************************************************************
342	* Global Variables *
343	*********************************************************************************************************************************/
344	/**
345	* Read-write masks for DMAR registers (group 0).
346	*/
347	static uint32_t const g_au32RwMasks0[] =
348	{
349	/* Offset Register Low High */
350	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
351	/* 0x004 Reserved */ 0,
352	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
353	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
354	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
355	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
356	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
357	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
358	/* 0x030 Reserved */ 0,
359	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
360	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
361	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
362	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
363	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
364	/* 0x048 Reserved */ 0, 0,
365	/* 0x050 Reserved */ 0, 0,
366	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
367	/* 0x060 Reserved */ 0,
368	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
369	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
370	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
371	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
372	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
373	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
374	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
375	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
376	/* 0x098 Reserved */ 0,
377	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
378	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
379	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
380	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
381	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
382	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
383	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
384	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
385	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
386	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
387	/* 0x0d8 Reserved */ 0,
388	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
389	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
390	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
391	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
392	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
393	/* 0x0f0 Reserved */ 0, 0,
394	/* 0x0f8 Reserved */ 0, 0,
395	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
396	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
397	/* 0x110 Reserved */ 0, 0,
398	/* 0x118 Reserved */ 0, 0,
399	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
400	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
401	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
402	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
403	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
404	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
405	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
406	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
407	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
408	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
409	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
410	/* 0x178 Reserved */ 0, 0,
411	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
412	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
413	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
414	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
415	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
416	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
417	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
418	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
419	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
420	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
421	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
422	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
423	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
424	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
425	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
426	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
427	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
428	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
429	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
430	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
431	};
432	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
433
434	/**
435	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
436	*/
437	static uint32_t const g_au32Rw1cMasks0[] =
438	{
439	/* Offset Register Low High */
440	/* 0x000 VER_REG */ 0,
441	/* 0x004 Reserved */ 0,
442	/* 0x008 CAP_REG */ 0, 0,
443	/* 0x010 ECAP_REG */ 0, 0,
444	/* 0x018 GCMD_REG */ 0,
445	/* 0x01c GSTS_REG */ 0,
446	/* 0x020 RTADDR_REG */ 0, 0,
447	/* 0x028 CCMD_REG */ 0, 0,
448	/* 0x030 Reserved */ 0,
449	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
450	/* 0x038 FECTL_REG */ 0,
451	/* 0x03c FEDATA_REG */ 0,
452	/* 0x040 FEADDR_REG */ 0,
453	/* 0x044 FEUADDR_REG */ 0,
454	/* 0x048 Reserved */ 0, 0,
455	/* 0x050 Reserved */ 0, 0,
456	/* 0x058 AFLOG_REG */ 0, 0,
457	/* 0x060 Reserved */ 0,
458	/* 0x064 PMEN_REG */ 0,
459	/* 0x068 PLMBASE_REG */ 0,
460	/* 0x06c PLMLIMIT_REG */ 0,
461	/* 0x070 PHMBASE_REG */ 0, 0,
462	/* 0x078 PHMLIMIT_REG */ 0, 0,
463	/* 0x080 IQH_REG */ 0, 0,
464	/* 0x088 IQT_REG */ 0, 0,
465	/* 0x090 IQA_REG */ 0, 0,
466	/* 0x098 Reserved */ 0,
467	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
468	/* 0x0a0 IECTL_REG */ 0,
469	/* 0x0a4 IEDATA_REG */ 0,
470	/* 0x0a8 IEADDR_REG */ 0,
471	/* 0x0ac IEUADDR_REG */ 0,
472	/* 0x0b0 IQERCD_REG */ 0, 0,
473	/* 0x0b8 IRTA_REG */ 0, 0,
474	/* 0x0c0 PQH_REG */ 0, 0,
475	/* 0x0c8 PQT_REG */ 0, 0,
476	/* 0x0d0 PQA_REG */ 0, 0,
477	/* 0x0d8 Reserved */ 0,
478	/* 0x0dc PRS_REG */ 0,
479	/* 0x0e0 PECTL_REG */ 0,
480	/* 0x0e4 PEDATA_REG */ 0,
481	/* 0x0e8 PEADDR_REG */ 0,
482	/* 0x0ec PEUADDR_REG */ 0,
483	/* 0x0f0 Reserved */ 0, 0,
484	/* 0x0f8 Reserved */ 0, 0,
485	/* 0x100 MTRRCAP_REG */ 0, 0,
486	/* 0x108 MTRRDEF_REG */ 0, 0,
487	/* 0x110 Reserved */ 0, 0,
488	/* 0x118 Reserved */ 0, 0,
489	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
490	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
491	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
492	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
493	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
494	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
495	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
496	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
497	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
498	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
499	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
500	/* 0x178 Reserved */ 0, 0,
501	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
502	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
503	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
504	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
505	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
506	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
507	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
508	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
509	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
510	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
511	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
512	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
513	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
514	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
515	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
516	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
517	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
518	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
519	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
520	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
521	};
522	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
523
524	/**
525	* Read-write masks for DMAR registers (group 1).
526	*/
527	static uint32_t const g_au32RwMasks1[] =
528	{
529	/* Offset Register Low High */
530	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
531	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
532	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
533	/* 0xe18 VCMDRSVD_REG */ 0, 0,
534	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
535	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
536	/* 0xe30 Reserved */ 0, 0,
537	/* 0xe38 Reserved */ 0, 0,
538	/* 0xe40 Reserved */ 0, 0,
539	/* 0xe48 Reserved */ 0, 0,
540	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
541	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
542	/* 0xe60 Reserved */ 0, 0,
543	/* 0xe68 Reserved */ 0, 0,
544	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
545	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
546	};
547	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
548	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
549
550	/**
551	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
552	*/
553	static uint32_t const g_au32Rw1cMasks1[] =
554	{
555	/* Offset Register Low High */
556	/* 0xe00 VCCAP_REG */ 0, 0,
557	/* 0xe08 VCMD_EO_REG */ 0, 0,
558	/* 0xe10 VCMD_REG */ 0, 0,
559	/* 0xe18 VCMDRSVD_REG */ 0, 0,
560	/* 0xe20 VCRSP_REG */ 0, 0,
561	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
562	/* 0xe30 Reserved */ 0, 0,
563	/* 0xe38 Reserved */ 0, 0,
564	/* 0xe40 Reserved */ 0, 0,
565	/* 0xe48 Reserved */ 0, 0,
566	/* 0xe50 IVA_REG */ 0, 0,
567	/* 0xe58 IOTLB_REG */ 0, 0,
568	/* 0xe60 Reserved */ 0, 0,
569	/* 0xe68 Reserved */ 0, 0,
570	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
571	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
572	};
573	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
574
575	/** Array of RW masks for each register group. */
576	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
577
578	/** Array of RW1C masks for each register group. */
579	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
580
581	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
582	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
583
584
585	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
586	/** @todo Add IOMMU struct size/alignment verification, see
587	* Devices/testcase/Makefile.kmk and
588	* Devices/testcase/tstDeviceStructSize[RC].cpp */
589
590	/**
591	* Returns the number of supported adjusted guest-address width (SAGAW) in bits
592	* given a CAP_REG.SAGAW value.
593	*
594	* @returns Number of SAGAW bits.
595	* @param uSagaw The CAP_REG.SAGAW value.
596	*/
597	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
598	{
599	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
600	return 30 + (uSagaw * 9);
601	return 0;
602	}
603
604
605	/**
606	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
607	* guest address width (MGAW).
608	*
609	* @returns The CAP_REG.SAGAW value.
610	* @param uMgaw The CAP_REG.MGAW value.
611	*/
612	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
613	{
614	switch (uMgaw + 1)
615	{
616	case 39: return 1;
617	case 48: return 2;
618	case 57: return 3;
619	}
620	return 0;
621	}
622
623
624	/**
625	* Returns table translation mode's descriptive name.
626	*
627	* @returns The descriptive name.
628	* @param uTtm The RTADDR_REG.TTM value.
629	*/
630	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
631	{
632	Assert(!(uTtm & 3));
633	static const char* s_apszTtmNames[] =
634	{
635	"Legacy Mode",
636	"Scalable Mode",
637	"Reserved",
638	"Abort-DMA Mode"
639	};
640	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
641	}
642
643
644	/**
645	* Gets the index of the group the register belongs to given its MMIO offset.
646	*
647	* @returns The group index.
648	* @param offReg The MMIO offset of the register.
649	* @param cbReg The size of the access being made (for bounds checking on
650	* debug builds).
651	*/
652	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
653	{
654	uint16_t const offLast = offReg + cbReg - 1;
655	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
656	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
657	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
658	}
659
660
661	/**
662	* Gets the group the register belongs to given its MMIO offset.
663	*
664	* @returns Pointer to the first element of the register group.
665	* @param pThis The shared DMAR device state.
666	* @param offReg The MMIO offset of the register.
667	* @param cbReg The size of the access being made (for bounds checking on
668	* debug builds).
669	* @param pIdxGroup Where to store the index of the register group the register
670	* belongs to.
671	*/
672	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
673	{
674	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
675	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
676	return apbRegs[*pIdxGroup];
677	}
678
679
680	/**
681	* Const/read-only version of dmarRegGetGroup.
682	*
683	* @copydoc dmarRegGetGroup
684	*/
685	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
686	{
687	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
688	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
689	return apbRegs[*pIdxGroup];
690	}
691
692
693	/**
694	* Writes a 32-bit register with the exactly the supplied value.
695	*
696	* @param pThis The shared DMAR device state.
697	* @param offReg The MMIO offset of the register.
698	* @param uReg The 32-bit value to write.
699	*/
700	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
701	{
702	uint8_t idxGroup;
703	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
704	NOREF(idxGroup);
705	(uint32_t )(pabRegs + offReg) = uReg;
706	}
707
708
709	/**
710	* Writes a 64-bit register with the exactly the supplied value.
711	*
712	* @param pThis The shared DMAR device state.
713	* @param offReg The MMIO offset of the register.
714	* @param uReg The 64-bit value to write.
715	*/
716	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
717	{
718	uint8_t idxGroup;
719	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
720	NOREF(idxGroup);
721	(uint64_t )(pabRegs + offReg) = uReg;
722	}
723
724
725	/**
726	* Reads a 32-bit register with exactly the value it contains.
727	*
728	* @returns The raw register value.
729	* @param pThis The shared DMAR device state.
730	* @param offReg The MMIO offset of the register.
731	*/
732	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
733	{
734	uint8_t idxGroup;
735	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
736	NOREF(idxGroup);
737	return (uint32_t )(pabRegs + offReg);
738	}
739
740
741	/**
742	* Reads a 64-bit register with exactly the value it contains.
743	*
744	* @returns The raw register value.
745	* @param pThis The shared DMAR device state.
746	* @param offReg The MMIO offset of the register.
747	*/
748	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
749	{
750	uint8_t idxGroup;
751	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
752	NOREF(idxGroup);
753	return (uint64_t )(pabRegs + offReg);
754	}
755
756
757	/**
758	* Reads a 32-bit register with exactly the value it contains along with their
759	* corresponding masks
760	*
761	* @param pThis The shared DMAR device state.
762	* @param offReg The MMIO offset of the register.
763	* @param puReg Where to store the raw 32-bit register value.
764	* @param pfRwMask Where to store the RW mask corresponding to this register.
765	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
766	*/
767	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
768	{
769	uint8_t idxGroup;
770	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
771	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
772	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
773	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
774	puReg = (uint32_t *)(pabRegs + offReg);
775	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
776	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
777	}
778
779
780	/**
781	* Reads a 64-bit register with exactly the value it contains along with their
782	* corresponding masks.
783	*
784	* @param pThis The shared DMAR device state.
785	* @param offReg The MMIO offset of the register.
786	* @param puReg Where to store the raw 64-bit register value.
787	* @param pfRwMask Where to store the RW mask corresponding to this register.
788	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
789	*/
790	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
791	{
792	uint8_t idxGroup;
793	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
794	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
795	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
796	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
797	puReg = (uint64_t *)(pabRegs + offReg);
798	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
799	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
800	}
801
802
803	/**
804	* Writes a 32-bit register as it would be when written by software.
805	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
806	*
807	* @returns The value that's actually written to the register.
808	* @param pThis The shared DMAR device state.
809	* @param offReg The MMIO offset of the register.
810	* @param uReg The 32-bit value to write.
811	*/
812	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
813	{
814	/* Read current value from the 32-bit register. */
815	uint32_t uCurReg;
816	uint32_t fRwMask;
817	uint32_t fRw1cMask;
818	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
819
820	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
821	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
822	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
823	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
824
825	/* Write new value to the 32-bit register. */
826	dmarRegWriteRaw32(pThis, offReg, uNewReg);
827	return uNewReg;
828	}
829
830
831	/**
832	* Writes a 64-bit register as it would be when written by software.
833	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
834	*
835	* @returns The value that's actually written to the register.
836	* @param pThis The shared DMAR device state.
837	* @param offReg The MMIO offset of the register.
838	* @param uReg The 64-bit value to write.
839	*/
840	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
841	{
842	/* Read current value from the 64-bit register. */
843	uint64_t uCurReg;
844	uint64_t fRwMask;
845	uint64_t fRw1cMask;
846	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
847
848	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
849	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
850	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
851	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
852
853	/* Write new value to the 64-bit register. */
854	dmarRegWriteRaw64(pThis, offReg, uNewReg);
855	return uNewReg;
856	}
857
858
859	/**
860	* Reads a 32-bit register as it would be when read by software.
861	*
862	* @returns The register value.
863	* @param pThis The shared DMAR device state.
864	* @param offReg The MMIO offset of the register.
865	*/
866	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
867	{
868	return dmarRegReadRaw32(pThis, offReg);
869	}
870
871
872	/**
873	* Reads a 64-bit register as it would be when read by software.
874	*
875	* @returns The register value.
876	* @param pThis The shared DMAR device state.
877	* @param offReg The MMIO offset of the register.
878	*/
879	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
880	{
881	return dmarRegReadRaw64(pThis, offReg);
882	}
883
884
885	/**
886	* Modifies a 32-bit register.
887	*
888	* @param pThis The shared DMAR device state.
889	* @param offReg The MMIO offset of the register.
890	* @param fAndMask The AND mask (applied first).
891	* @param fOrMask The OR mask.
892	* @remarks This does NOT apply RO or RW1C masks while modifying the
893	* register.
894	*/
895	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
896	{
897	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
898	uReg = (uReg & fAndMask) \| fOrMask;
899	dmarRegWriteRaw32(pThis, offReg, uReg);
900	}
901
902
903	/**
904	* Modifies a 64-bit register.
905	*
906	* @param pThis The shared DMAR device state.
907	* @param offReg The MMIO offset of the register.
908	* @param fAndMask The AND mask (applied first).
909	* @param fOrMask The OR mask.
910	* @remarks This does NOT apply RO or RW1C masks while modifying the
911	* register.
912	*/
913	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
914	{
915	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
916	uReg = (uReg & fAndMask) \| fOrMask;
917	dmarRegWriteRaw64(pThis, offReg, uReg);
918	}
919
920
921	/**
922	* Checks if the invalidation-queue is empty.
923	*
924	* Extended version which optionally returns the current queue head and tail
925	* offsets.
926	*
927	* @returns @c true if empty, @c false otherwise.
928	* @param pThis The shared DMAR device state.
929	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
930	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
931	*/
932	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
933	{
934	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
935	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
936	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
937
938	/* Don't bother masking QT, QH since other bits are RsvdZ. */
939	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
940	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
941	if (poffQh)
942	*poffQh = uIqhReg;
943	if (poffQt)
944	*poffQt = uIqtReg;
945	return uIqtReg == uIqhReg;
946	}
947
948
949	/**
950	* Checks if the invalidation-queue is empty.
951	*
952	* @returns @c true if empty, @c false otherwise.
953	* @param pThis The shared DMAR device state.
954	*/
955	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
956	{
957	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
958	}
959
960
961	/**
962	* Checks if the invalidation-queue is capable of processing requests.
963	*
964	* @returns @c true if the invalidation-queue can process requests, @c false
965	* otherwise.
966	* @param pThis The shared DMAR device state.
967	*/
968	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
969	{
970	/* Check if queued-invalidation is enabled. */
971	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
972	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
973	{
974	/* Check if there are no invalidation-queue or timeout errors. */
975	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
976	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
977	return true;
978	}
979	return false;
980	}
981
982
983	/**
984	* Wakes up the invalidation-queue thread if there are requests to be processed.
985	*
986	* @param pDevIns The IOMMU device instance.
987	*/
988	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
989	{
990	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
991	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
992	Log4Func(("\n"));
993
994	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
995
996	if ( dmarInvQueueCanProcessRequests(pThis)
997	&& !dmarInvQueueIsEmpty(pThis)
998	&& !ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, true))
999	{
1000	Log4Func(("Signaling the invalidation-queue thread\n"));
1001	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1002	}
1003	}
1004
1005
1006	/**
1007	* Raises an interrupt in response to a fault event.
1008	*
1009	* @param pDevIns The IOMMU device instance.
1010	*/
1011	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1012	{
1013	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1014	#ifdef RT_STRICT
1015	{
1016	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1017	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1018	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1019	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1020	\| VTD_BF_FSTS_REG_IQE_MASK;
1021	Assert(uFstsReg & fFaultMask);
1022	}
1023	#endif
1024
1025	uint32_t uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1026	if (!(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1027	{
1028	/* Software has unmasked the interrupt, raise it. */
1029	MSIMSG Msi;
1030	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
1031	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
1032	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1033
1034	/** @todo Assert Msi.Addr is in the MSR_IA32_APICBASE_ADDR range and ensure on
1035	* FEADD_REG write it can't be anything else? */
1036	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1037	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1038
1039	/* Clear interrupt pending bit. */
1040	uFectlReg &= ~VTD_BF_FECTL_REG_IP_MASK;
1041	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1042	}
1043	else
1044	{
1045	/* Interrupt is masked, set the interrupt pending bit. */
1046	uFectlReg \|= VTD_BF_FECTL_REG_IP_MASK;
1047	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1048	}
1049	}
1050
1051
1052	#ifdef IN_RING3
1053	/**
1054	* Raises an interrupt in response to an invalidation (complete) event.
1055	*
1056	* @param pDevIns The IOMMU device instance.
1057	*/
1058	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1059	{
1060	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1061	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1062	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1063
1064	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1065	if (uIcsReg & VTD_BF_ICS_REG_IWC_MASK)
1066	return;
1067
1068	uint32_t uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
1069	if (!(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1070	{
1071	/* Software has unmasked the interrupt, raise it. */
1072	MSIMSG Msi;
1073	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
1074	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
1075	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
1076
1077	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1078
1079	/* Clear interrupt pending bit. */
1080	uIectlReg &= ~VTD_BF_IECTL_REG_IP_MASK;
1081	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1082	}
1083	else
1084	{
1085	/* Interrupt is masked, set the interrupt pending bit. */
1086	uIectlReg \|= VTD_BF_IECTL_REG_IP_MASK;
1087	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1088	}
1089	}
1090	#endif /* IN_RING3 */
1091
1092
1093	#if 0
1094	/**
1095	* Checks if a primary fault can be recorded.
1096	*
1097	* @returns @c true if the fault can be recorded, @c false otherwise.
1098	* @param pDevIns The IOMMU device instance.
1099	* @param pThis The shared DMAR device state.
1100	*/
1101	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1102	{
1103	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1104	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1105
1106	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1107	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1108	return false;
1109
1110	/*
1111	* If we add more FRCD registers, we'll have to loop through them here.
1112	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1113	* nor do we need to increment FRI.
1114	*
1115	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1116	*/
1117	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1118	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1119	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1120	{
1121	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1122	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1123	return false;
1124	}
1125
1126	uFstsReg \|= VTD_BF_FSTS_REG_PPF_MASK;
1127	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1128	return true;
1129	}
1130	#endif
1131
1132
1133	/**
1134	* Records an IQE fault.
1135	*
1136	* @param pDevIns The IOMMU device instance.
1137	* @param enmIqei The IQE information.
1138	* @param enmDiag The diagnostic reason.
1139	*/
1140	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQEI_T enmIqei)
1141	{
1142	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1143	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1144	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1145
1146	/* Update the diagnostic reason. */
1147	pThis->enmDiag = enmDiag;
1148
1149	/* Set the error bit. */
1150	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1151	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1152
1153	/* Set the error information. */
1154	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1155	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1156
1157	dmarFaultEventRaiseInterrupt(pDevIns);
1158	}
1159
1160
1161	/**
1162	* Handles writes to GCMD_REG.
1163	*
1164	* @returns Strict VBox status code.
1165	* @param pDevIns The IOMMU device instance.
1166	* @param uGcmdReg The value written to GCMD_REG.
1167	*/
1168	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1169	{
1170	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1171	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1172	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1173	uint64_t const fExtCapReg = pThis->fExtCapReg;
1174
1175	/*
1176	* Queued-invalidation.
1177	*/
1178	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1179	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1180	{
1181	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1182	{
1183	/* Enable the invalidation-queue. */
1184	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask /, VTD_BF_GSTS_REG_QIES_MASK / fOrMask */);
1185	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1186	}
1187	else
1188	{
1189	/* Disable the invalidation-queue. */
1190	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK /* fAndMask /, 0 / fOrMask */);
1191	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1192	}
1193	}
1194
1195	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1196	{
1197	/*
1198	* Set Interrupt Remapping Table Pointer (SIRTP).
1199	*/
1200	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1201	{
1202	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1203	* supported. */
1204	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1205	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask /, VTD_BF_GSTS_REG_IRTPS_MASK / fOrMask */);
1206	}
1207
1208	/*
1209	* Interrupt remapping.
1210	*/
1211	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1212	{
1213	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1214	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask */,
1215	VTD_BF_GSTS_REG_IRES_MASK /* fOrMask */);
1216	else
1217	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK /* fAndMask /, 0 / fOrMask */);
1218	}
1219	}
1220
1221	/*
1222	* Set Root Table Pointer (SRTP).
1223	*/
1224	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1225	{
1226	/** @todo Perform global invalidation of all remapping translation caches when
1227	* ESRTPS is supported. */
1228	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1229	}
1230
1231	/** @todo Rest of the bits. */
1232
1233	return VINF_SUCCESS;
1234	}
1235
1236
1237	/**
1238	* Handles writes to CCMD_REG.
1239	*
1240	* @returns Strict VBox status code.
1241	* @param pDevIns The IOMMU device instance.
1242	* @param offReg The MMIO register offset.
1243	* @param cbReg The size of the MMIO access (in bytes).
1244	* @param uCcmdReg The value written to CCMD_REG.
1245	*/
1246	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1247	{
1248	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1249	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1250	{
1251	/* Check if we need to invalidate the context-context. */
1252	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1253	if (fIcc)
1254	{
1255	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1256	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1257	if (uMajorVersion < 6)
1258	{
1259	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1260	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1261	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1262	{
1263	/* Verify table translation mode is legacy. */
1264	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1265	if (fTtm == VTD_TTM_LEGACY_MODE)
1266	{
1267	/** @todo Invalidate. */
1268	return VINF_SUCCESS;
1269	}
1270	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1271	}
1272	else
1273	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1274	}
1275	else
1276	pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1277	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK /* fAndMask /, 0 / fOrMask */);
1278	}
1279	}
1280	return VINF_SUCCESS;
1281	}
1282
1283
1284	/**
1285	* Handles writes to IQT_REG.
1286	*
1287	* @returns Strict VBox status code.
1288	* @param pDevIns The IOMMU device instance.
1289	* @param offReg The MMIO register offset.
1290	* @param uIqtReg The value written to IQT_REG.
1291	*/
1292	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1293	{
1294	/* We only care about the low 32-bits, high 32-bits are reserved. */
1295	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1296	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1297
1298	/* Paranoia. */
1299	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1300
1301	uint32_t const offQt = uIqtReg;
1302	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1303	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1304
1305	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1306	if ( fDw != VTD_IQA_REG_DW_256_BIT
1307	\|\| !(offQt & RT_BIT(4)))
1308	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1309	else
1310	{
1311	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1312	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4) /* fAndMask/ , 0 / fOrMask */);
1313	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kIqei_QueueTailNotAligned);
1314	}
1315	return VINF_SUCCESS;
1316	}
1317
1318
1319	/**
1320	* Handles writes to IQA_REG.
1321	*
1322	* @returns Strict VBox status code.
1323	* @param pDevIns The IOMMU device instance.
1324	* @param offReg The MMIO register offset.
1325	* @param uIqaReg The value written to IQA_REG.
1326	*/
1327	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1328	{
1329	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1330	Assert(offReg == VTD_MMIO_OFF_IQA_REG);
1331
1332	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1333	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1334	* cannot happen or that it's ignored when it does happen. */
1335
1336	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1337	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1338	if (fDw == VTD_IQA_REG_DW_256_BIT)
1339	{
1340	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1341	if (fSupports256BitDw)
1342	{ /* likely */ }
1343	else
1344	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, kIqei_InvalidDescriptorWidth);
1345	}
1346	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1347
1348	return VINF_SUCCESS;
1349	}
1350
1351
1352	/**
1353	* Memory access bulk (one or more 4K pages) request from a device.
1354	*
1355	* @returns VBox status code.
1356	* @param pDevIns The IOMMU device instance.
1357	* @param idDevice The device ID (bus, device, function).
1358	* @param cIovas The number of addresses being accessed.
1359	* @param pauIovas The I/O virtual addresses for each page being accessed.
1360	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1361	* @param paGCPhysSpa Where to store the translated physical addresses.
1362	*
1363	* @thread Any.
1364	*/
1365	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1366	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1367	{
1368	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1369	return VERR_NOT_IMPLEMENTED;
1370	}
1371
1372
1373	/**
1374	* Memory access transaction from a device.
1375	*
1376	* @returns VBox status code.
1377	* @param pDevIns The IOMMU device instance.
1378	* @param idDevice The device ID (bus, device, function).
1379	* @param uIova The I/O virtual address being accessed.
1380	* @param cbIova The size of the access.
1381	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1382	* @param pGCPhysSpa Where to store the translated system physical address.
1383	* @param pcbContiguous Where to store the number of contiguous bytes translated
1384	* and permission-checked.
1385	*
1386	* @thread Any.
1387	*/
1388	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1389	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1390	{
1391	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
1392	return VERR_NOT_IMPLEMENTED;
1393	}
1394
1395
1396	/**
1397	* Interrupt remap request from a device.
1398	*
1399	* @returns VBox status code.
1400	* @param pDevIns The IOMMU device instance.
1401	* @param idDevice The device ID (bus, device, function).
1402	* @param pMsiIn The source MSI.
1403	* @param pMsiOut Where to store the remapped MSI.
1404	*/
1405	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1406	{
1407	/* Validate. */
1408	Assert(pDevIns);
1409	Assert(pMsiIn);
1410	Assert(pMsiOut);
1411	RT_NOREF1(idDevice);
1412
1413	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1414	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1415
1416	/* Lock and read all registers required for interrupt remapping up-front. */
1417	DMAR_LOCK(pDevIns, pThisCC);
1418	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1419	uint64_t const uIrtaReg = pThis->uIrtaReg;
1420	DMAR_UNLOCK(pDevIns, pThisCC);
1421
1422	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
1423	{
1424	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
1425
1426	/*
1427	* Handle interrupts in compatibility format.
1428	*/
1429	uint8_t const fIntrFormat = VTD_MSI_ADDR_GET_INTR_FORMAT(pMsiIn->Addr.u64);
1430	if (fIntrFormat == VTD_INTR_FORMAT_COMPAT)
1431	{
1432	/* If Extended Interrupt Mode (EIM) is enabled or compatibility format interrupts (CFI) are disabled,
1433	block the interrupt. */
1434	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
1435	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
1436	return VERR_IOMMU_INTR_REMAP_DENIED;
1437
1438	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
1439	pMsiOut = pMsiIn;
1440	return VINF_SUCCESS;
1441	}
1442
1443	/*
1444	* Handle interrupts in remappable format.
1445	*/
1446	/** @todo index IRTA. */
1447	}
1448	else
1449	{
1450	/* If interrupt-remapping isn't enabled, all interrupts are pass-through. */
1451	pMsiOut = pMsiIn;
1452	}
1453
1454	return VINF_SUCCESS;
1455	}
1456
1457
1458	/**
1459	* @callback_method_impl{FNIOMMMIONEWWRITE}
1460	*/
1461	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1462	{
1463	RT_NOREF1(pvUser);
1464	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1465
1466	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1467	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1468
1469	uint16_t const offReg = off;
1470	uint16_t const offLast = offReg + cb - 1;
1471	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1472	{
1473	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1474	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
1475
1476	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
1477	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
1478	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1479	switch (off)
1480	{
1481	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
1482	{
1483	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
1484	break;
1485	}
1486
1487	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
1488	case VTD_MMIO_OFF_CCMD_REG + 4:
1489	{
1490	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
1491	break;
1492	}
1493
1494	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
1495	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
1496	{
1497	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
1498	break;
1499	}
1500
1501	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
1502	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
1503	{
1504	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
1505	break;
1506	}
1507	}
1508
1509	DMAR_UNLOCK(pDevIns, pThisCC);
1510	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
1511	return rcStrict;
1512	}
1513
1514	return VINF_IOM_MMIO_UNUSED_FF;
1515	}
1516
1517
1518	/**
1519	* @callback_method_impl{FNIOMMMIONEWREAD}
1520	*/
1521	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1522	{
1523	RT_NOREF1(pvUser);
1524	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1525
1526	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1527	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1528
1529	uint16_t const offReg = off;
1530	uint16_t const offLast = offReg + cb - 1;
1531	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1532	{
1533	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1534	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
1535
1536	if (cb == 8)
1537	{
1538	(uint64_t )pv = dmarRegRead64(pThis, offReg);
1539	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
1540	}
1541	else
1542	{
1543	(uint32_t )pv = dmarRegRead32(pThis, offReg);
1544	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
1545	}
1546
1547	DMAR_UNLOCK(pDevIns, pThisCC);
1548	return VINF_SUCCESS;
1549	}
1550
1551	return VINF_IOM_MMIO_UNUSED_FF;
1552	}
1553
1554
1555	#ifdef IN_RING3
1556	/**
1557	* Process requests in the invalidation queue.
1558	*
1559	* @param pDevIns The IOMMU device instance.
1560	* @param pvRequests The requests to process.
1561	* @param cbRequests The size of all requests (in bytes).
1562	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
1563	* VTD_IQA_REG_DW_256_BIT).
1564	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
1565	*/
1566	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
1567	uint8_t fTtm)
1568	{
1569	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
1570	do \
1571	{ \
1572	DMAR_LOCK(pDevIns, pThisR3); \
1573	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
1574	DMAR_UNLOCK(pDevIns, pThisR3); \
1575	return; \
1576	} while (0)
1577
1578	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1579	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1580
1581	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
1582	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
1583
1584	/*
1585	* The below check is redundant since we check both TTM and DW for each
1586	* descriptor type we process. However, the error reported by hardware
1587	* may differ hence this is kept commented out but not removed from the code
1588	* if we need to change this in the future.
1589	*
1590	* In our implementation, we would report the descriptor type as invalid,
1591	* while on real hardware it may report descriptor width as invalid.
1592	* The Intel VT-d spec. is not clear which error takes preceedence.
1593	*/
1594	#if 0
1595	/*
1596	* Verify that 128-bit descriptors are not used when operating in scalable mode.
1597	* We don't check this while software writes IQA_REG but defer it until now because
1598	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
1599	* -IS- performed when software writes IQA_REG since it only requires checking against
1600	* immutable hardware features.
1601	*/
1602	if ( fTtm != VTD_TTM_SCALABLE_MODE
1603	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
1604	{ /* likely */ }
1605	else
1606	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, kIqei_InvalidDescriptorWidth);
1607	#endif
1608
1609	/*
1610	* Process requests in FIFO order.
1611	*/
1612	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
1613	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
1614	{
1615	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
1616	uint64_t const uQword0 = puDscQwords[0];
1617	uint64_t const uQword1 = puDscQwords[1];
1618	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
1619	switch (fDscType)
1620	{
1621	case VTD_INV_WAIT_DSC_TYPE:
1622	{
1623	/* Validate descriptor type. */
1624	if ( fTtm == VTD_TTM_LEGACY_MODE
1625	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
1626	{ /* likely */ }
1627	else
1628	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, kIqei_InvalidDescriptorType);
1629
1630	/* Validate reserved bits. */
1631	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
1632	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
1633	: VTD_INV_WAIT_DSC_0_VALID_MASK;
1634	if ( !(uQword0 & ~fValidMask0)
1635	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
1636	{ /* likely */ }
1637	else
1638	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, kIqei_RsvdFieldViolation);
1639
1640	if (fDw == VTD_IQA_REG_DW_256_BIT)
1641	{
1642	if ( !puDscQwords[2]
1643	&& !puDscQwords[3])
1644	{ /* likely */ }
1645	else
1646	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, kIqei_RsvdFieldViolation);
1647	}
1648
1649	/* Perform status write (this must be done prior to generating the completion interrupt). */
1650	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
1651	if (fSw)
1652	{
1653	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
1654	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
1655	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
1656	AssertRC(rc);
1657	}
1658
1659	/* Generate invalidation event interrupt. */
1660	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
1661	if (fIf)
1662	{
1663	DMAR_LOCK(pDevIns, pThisR3);
1664	dmarR3InvEventRaiseInterrupt(pDevIns);
1665	DMAR_UNLOCK(pDevIns, pThisR3);
1666	}
1667
1668	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
1669	break;
1670	}
1671
1672	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
1673	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
1674	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
1675	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
1676	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
1677	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
1678	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
1679	default:
1680	{
1681	/* Stop processing further requests. */
1682	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
1683	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, kIqei_InvalidDescriptorType);
1684	}
1685	}
1686	}
1687	#undef DMAR_IQE_FAULT_RECORD_RET
1688	}
1689
1690
1691	/**
1692	* The invalidation-queue thread.
1693	*
1694	* @returns VBox status code.
1695	* @param pDevIns The IOMMU device instance.
1696	* @param pThread The command thread.
1697	*/
1698	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1699	{
1700	NOREF(pThread);
1701	LogFlowFunc(("\n"));
1702
1703	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
1704	return VINF_SUCCESS;
1705
1706	/*
1707	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
1708	* This prevents trashing the heap as well as deal with out-of-memory situations
1709	* up-front while starting the VM. It also simplifies the code from having to
1710	* dynamically grow/shrink the allocation based on how software sizes the queue.
1711	* Guests normally don't alter the queue size all the time, but that's not an
1712	* assumption we can make.
1713	*/
1714	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
1715	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
1716	void *pvRequests = RTMemAllocZ(cbMaxQs);
1717	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
1718
1719	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1720	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1721
1722	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
1723	{
1724	/*
1725	* Sleep until we are woken up.
1726	*/
1727	bool const fSignaled = ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, false);
1728	if (!fSignaled)
1729	{
1730	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
1731	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
1732	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
1733	break;
1734	ASMAtomicWriteBool(&pThis->fInvQueueThreadSignaled, false);
1735	}
1736
1737	DMAR_LOCK(pDevIns, pThisR3);
1738	if (dmarInvQueueCanProcessRequests(pThis))
1739	{
1740	uint32_t offQueueHead;
1741	uint32_t offQueueTail;
1742	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
1743	if (!fIsEmpty)
1744	{
1745	/*
1746	* Get the current queue size, descriptor width, queue base address and the
1747	* table translation mode while the lock is still held.
1748	*/
1749	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1750	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
1751	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
1752	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1753	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1754	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
1755
1756	/* Paranoia. */
1757	Assert(cbQueue <= cbMaxQs);
1758	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
1759	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
1760	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
1761	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
1762	Assert(offQueueHead < cbQueue);
1763
1764	/*
1765	* A table translation mode of "reserved" isn't valid for any descriptor type.
1766	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
1767	* but if ESRTPS is support, we will perform a global invalidation when software
1768	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
1769	* So caching TTM while reading all descriptors should not be a problem.
1770	*
1771	* Also, validate the queue tail offset as it's mutable by software.
1772	*/
1773	if ( fTtm != VTD_TTM_RSVD
1774	&& offQueueTail < cbQueue)
1775	{
1776	/* Don't hold the lock while reading (a potentially large amount of) requests */
1777	DMAR_UNLOCK(pDevIns, pThisR3);
1778
1779	int rc;
1780	uint32_t cbRequests;
1781	if (offQueueTail > offQueueHead)
1782	{
1783	/* The requests have not wrapped around, read them in one go. */
1784	cbRequests = offQueueTail - offQueueHead;
1785	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbRequests);
1786	}
1787	else
1788	{
1789	/* The requests have wrapped around, read forward and wrapped-around. */
1790	uint32_t const cbForward = cbQueue - offQueueHead;
1791	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbForward);
1792
1793	uint32_t const cbWrapped = offQueueTail;
1794	if ( RT_SUCCESS(rc)
1795	&& cbWrapped > 0)
1796	{
1797	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests + cbForward,
1798	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
1799	}
1800	cbRequests = cbForward + cbWrapped;
1801	}
1802
1803	/* Re-acquire the lock since we need to update device state. */
1804	DMAR_LOCK(pDevIns, pThisR3);
1805
1806	if (RT_SUCCESS(rc))
1807	{
1808	/* Indicate to software we've fetched all requests. */
1809	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
1810
1811	/* Don't hold the lock while processing requests. */
1812	DMAR_UNLOCK(pDevIns, pThisR3);
1813
1814	/* Process all requests. */
1815	Assert(cbRequests <= cbQueue);
1816	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
1817
1818	/*
1819	* We've processed all requests and the lock shouldn't be held at this point.
1820	* Using 'continue' here allows us to skip re-acquiring the lock just to release
1821	* it again before going back to the thread loop. It's a bit ugly but it certainly
1822	* helps with performance.
1823	*/
1824	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
1825	continue;
1826	}
1827	else
1828	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, kIqei_FetchDescriptorError);
1829	}
1830	else
1831	{
1832	if (fTtm == VTD_TTM_RSVD)
1833	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, kIqei_InvalidTtm);
1834	else
1835	{
1836	Assert(offQueueTail >= cbQueue);
1837	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, kIqei_InvalidTailPointer);
1838	}
1839	}
1840	}
1841	}
1842	DMAR_UNLOCK(pDevIns, pThisR3);
1843	}
1844
1845	RTMemFree(pvRequests);
1846	pvRequests = NULL;
1847
1848	LogFlowFunc(("Invalidation-queue thread terminating\n"));
1849	return VINF_SUCCESS;
1850	}
1851
1852
1853	/**
1854	* Wakes up the invalidation-queue thread so it can respond to a state
1855	* change.
1856	*
1857	* @returns VBox status code.
1858	* @param pDevIns The IOMMU device instance.
1859	* @param pThread The invalidation-queue thread.
1860	*
1861	* @thread EMT.
1862	*/
1863	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1864	{
1865	RT_NOREF(pThread);
1866	LogFlowFunc(("\n"));
1867	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1868	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1869	}
1870
1871
1872	/**
1873	* @callback_method_impl{FNDBGFHANDLERDEV}
1874	*/
1875	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1876	{
1877	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1878	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1879	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1880	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1881
1882	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
1883
1884	/*
1885	* We lock the device to get a consistent register state, but it is
1886	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers into
1887	* temporaries and release the lock ASAP.
1888	*
1889	* Order of register being read and outputted is in accordance with the
1890	* spec. for no particular reason.
1891	* See Intel VT-d spec. 10.4 "Register Descriptions".
1892	*/
1893	DMAR_LOCK(pDevIns, pThisR3);
1894
1895	DMARDIAG const enmDiag = pThis->enmDiag;
1896	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
1897	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
1898	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
1899	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
1900	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1901	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1902	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
1903	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1904	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1905	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1906	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
1907	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
1908	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
1909	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
1910	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
1911	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
1912	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
1913	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
1914	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
1915	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
1916	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1917	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1918	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
1919	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
1920	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
1921	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
1922	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
1923	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1924	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
1925	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
1926	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
1927	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
1928	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
1929	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
1930	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
1931	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
1932	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
1933	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
1934	/** @todo Do other registers as required, we don't implement them for now. */
1935
1936	DMAR_UNLOCK(pDevIns, pThisR3);
1937
1938	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
1939	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
1940	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
1941	if (!fVerbose)
1942	{
1943	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
1944	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
1945	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
1946	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
1947	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
1948	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
1949	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
1950	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
1951	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
1952	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
1953	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
1954	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
1955	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
1956	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
1957	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
1958	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
1959	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
1960	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
1961	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
1962	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
1963	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
1964	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
1965	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
1966	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
1967	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
1968	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
1969	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
1970	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
1971	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
1972	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
1973	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
1974	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
1975	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
1976	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
1977	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
1978	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
1979	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
1980	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
1981	pHlp->pfnPrintf(pHlp, "\n");
1982	}
1983	else
1984	{
1985	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
1986	{
1987	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
1988	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
1989	}
1990	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
1991	{
1992	uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
1993	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
1994	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
1995	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
1996	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
1997	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
1998	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
1999	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
2000	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
2001	pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
2002	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
2003	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
2004	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
2005	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
2006	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
2007	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
2008	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
2009	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
2010	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
2011	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
2012	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
2013	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
2014	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
2015	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
2016	}
2017	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2018	{
2019	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
2020	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
2021	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
2022	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
2023	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
2024	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
2025	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
2026	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
2027	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
2028	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
2029	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
2030	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
2031	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
2032	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
2033	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
2034	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
2035	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
2036	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
2037	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
2038	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
2039	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
2040	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
2041	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
2042	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
2043	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
2044	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
2045	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
2046	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
2047	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
2048	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
2049	}
2050	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2051	{
2052	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
2053	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Bypass interrupt remapping"
2054	: "Block compatible format interrupts");
2055	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
2056	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
2057	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
2058	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
2059	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2060	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2061	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
2062	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
2063	}
2064	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2065	{
2066	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
2067	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Bypass interrupt remapping"
2068	: "Block compatible format interrupts");
2069	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
2070	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
2071	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
2072	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
2073	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
2074	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
2075	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
2076	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
2077	}
2078	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2079	{
2080	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2081	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
2082	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_RTA));
2083	}
2084	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2085	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2086	{
2087	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
2088	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
2089	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
2090	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
2091	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
2092	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
2093	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
2094	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
2095	}
2096	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2097	{
2098	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
2099	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
2100	}
2101	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2102	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2103	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2104	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2105	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2106	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2107	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2108	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2109	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2110	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2111	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2112	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2113	{
2114	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2115	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
2116	uint8_t const cQueuePages = 1 << fQs;
2117	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
2118	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
2119	}
2120	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2121	{
2122	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
2123	}
2124	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2125	{
2126	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
2127	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
2128	}
2129	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2130	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2131	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2132	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2133	{
2134	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
2135	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
2136	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
2137	}
2138	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2139	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2140	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2141	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2142	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2143	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2144	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2145	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2146	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2147	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2148	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2149	pHlp->pfnPrintf(pHlp, "\n");
2150	}
2151	}
2152
2153
2154	/**
2155	* Initializes all registers in the DMAR unit.
2156	*
2157	* @param pDevIns The IOMMU device instance.
2158	*/
2159	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
2160	{
2161	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2162
2163	/*
2164	* Wipe all registers (required on reset).
2165	*/
2166	RT_ZERO(pThis->abRegs0);
2167	RT_ZERO(pThis->abRegs1);
2168
2169	/*
2170	* Initialize registers not mutable by software prior to initializing other registers.
2171	*/
2172	/* VER_REG */
2173	{
2174	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
2175	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
2176	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
2177	}
2178
2179	uint8_t const fFlts = 1; /* First-Level translation support. */
2180	uint8_t const fSlts = 1; /* Second-Level translation support. */
2181	uint8_t const fPt = 1; /* Pass-Through support. */
2182	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
2183	uint8_t const fNest = 0; /* Nested translation support. */
2184
2185	/* CAP_REG */
2186	{
2187	uint8_t cGstPhysAddrBits;
2188	uint8_t cGstLinearAddrBits;
2189	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
2190
2191	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
2192	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
2193	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
2194	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
2195	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
2196	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
2197	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
2198	: X86_PAGE_2M_SHIFT)
2199	- X86_PAGE_4K_SHIFT;
2200	uint8_t const fNd = 2; /* Number of domains supported (0=16, 1=64, 2=256, 3=1K, 4=4K,
2201	5=16K, 6=64K, 7=Reserved). */
2202	uint8_t const fPsi = 1; /* Page selective invalidation. */
2203	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
2204	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
2205	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
2206	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
2207	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
2208
2209	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
2210	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
2211	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
2212	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
2213	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
2214	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
2215	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
2216	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
2217	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
2218	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
2219	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
2220	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
2221	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
2222	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
2223	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
2224	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
2225	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
2226	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
2227	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
2228	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
2229	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
2230	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
2231	}
2232
2233	/* ECAP_REG */
2234	{
2235	uint8_t const fQi = 1; /* Queued-invalidations. */
2236	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
2237	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
2238	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
2239	uint8_t const fSrs = 1; /* Supervisor request support. */
2240	uint8_t const fEim = 1; /* Extended interrupt mode.*/
2241	uint8_t const fAdms = 1; /* Abort DMA mode support. */
2242
2243	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
2244	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
2245	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
2246	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
2247	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
2248	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
2249	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
2250	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
2251	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
2252	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
2253	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
2254	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
2255	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
2256	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
2257	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
2258	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
2259	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
2260	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
2261	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
2262	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
2263	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
2264	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
2265	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
2266	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
2267	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
2268	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
2269	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
2270	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
2271	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
2272	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
2273	}
2274
2275	/*
2276	* Initialize registers mutable by software.
2277	*/
2278	/* FECTL_REG */
2279	{
2280	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
2281	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
2282	}
2283
2284	/* ICETL_REG */
2285	{
2286	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
2287	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
2288	}
2289
2290	#ifdef VBOX_STRICT
2291	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
2292	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
2293	#endif
2294	}
2295
2296
2297	/**
2298	* @interface_method_impl{PDMDEVREG,pfnReset}
2299	*/
2300	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
2301	{
2302	RT_NOREF1(pDevIns);
2303	LogFlowFunc(("\n"));
2304
2305	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2306	DMAR_LOCK(pDevIns, pThisR3);
2307
2308	dmarR3RegsInit(pDevIns);
2309
2310	DMAR_UNLOCK(pDevIns, pThisR3);
2311	}
2312
2313
2314	/**
2315	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2316	*/
2317	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
2318	{
2319	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2320	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2321	LogFlowFunc(("\n"));
2322
2323	DMAR_LOCK(pDevIns, pThisR3);
2324
2325	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
2326	{
2327	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
2328	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
2329	}
2330
2331	DMAR_UNLOCK(pDevIns, pThisR3);
2332	return VINF_SUCCESS;
2333	}
2334
2335
2336	/**
2337	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2338	*/
2339	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2340	{
2341	RT_NOREF(pCfg);
2342
2343	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2344	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
2345	pThisR3->pDevInsR3 = pDevIns;
2346
2347	LogFlowFunc(("iInstance=%d\n", iInstance));
2348	NOREF(iInstance);
2349
2350	/*
2351	* Register the IOMMU with PDM.
2352	*/
2353	PDMIOMMUREGR3 IommuReg;
2354	RT_ZERO(IommuReg);
2355	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2356	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2357	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2358	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2359	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2360	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
2361	if (RT_FAILURE(rc))
2362	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
2363	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
2364	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2365	N_("IOMMU helper version mismatch; got %#x expected %#x"),
2366	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
2367	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
2368	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2369	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
2370	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
2371	/*
2372	* Use PDM's critical section (via helpers) for the IOMMU device.
2373	*/
2374	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2375	AssertRCReturn(rc, rc);
2376
2377	/*
2378	* Initialize PCI configuration registers.
2379	*/
2380	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2381	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2382
2383	/* Header. */
2384	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2385	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2386	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
2387	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
2388	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
2389	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
2390	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2391	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2392
2393	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
2394	PDMPciDevSetStatus(pPciDev, 0);
2395	PDMPciDevSetCapabilityList(pPciDev, 0);
2396
2397	/** @todo VTBAR at 0x180? */
2398
2399	/*
2400	* Register the PCI function with PDM.
2401	*/
2402	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
2403	AssertLogRelRCReturn(rc, rc);
2404
2405	/** @todo Register MSI but what's the MSI capability offset? */
2406	#if 0
2407	/*
2408	* Register MSI support for the PCI device.
2409	* This must be done -after- registering it as a PCI device!
2410	*/
2411	#endif
2412
2413	/*
2414	* Register MMIO region.
2415	*/
2416	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
2417	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
2418	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
2419	&pThis->hMmio);
2420	AssertLogRelRCReturn(rc, rc);
2421
2422	/*
2423	* Register debugger info items.
2424	*/
2425	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
2426	AssertLogRelRCReturn(rc, rc);
2427
2428	#ifdef VBOX_WITH_STATISTICS
2429	/*
2430	* Statistics.
2431	*/
2432	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
2433	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
2434
2435	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
2436	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
2437
2438	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
2439	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
2440
2441	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
2442	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
2443
2444	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
2445	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
2446
2447	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
2448	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
2449
2450	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
2451	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
2452
2453	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
2454	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
2455	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
2456	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
2457	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
2458	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
2459	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
2460	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
2461	#endif
2462
2463	/*
2464	* Initialize registers.
2465	*/
2466	dmarR3RegsInit(pDevIns);
2467
2468	/*
2469	* Create invalidation-queue thread and semaphore.
2470	*/
2471	char szInvQueueThread[32];
2472	RT_ZERO(szInvQueueThread);
2473	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
2474	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
2475	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
2476	AssertLogRelRCReturn(rc, rc);
2477
2478	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
2479	AssertLogRelRCReturn(rc, rc);
2480
2481	/*
2482	* Log some of the features exposed to software.
2483	*/
2484	uint32_t const uVerReg = pThis->uVerReg;
2485	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
2486	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW));
2487	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
2488	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
2489	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
2490	DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
2491	pThis->fCapReg, pThis->fExtCapReg, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
2492
2493	return VINF_SUCCESS;
2494	}
2495
2496	#else
2497
2498	/**
2499	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
2500	*/
2501	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
2502	{
2503	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2504	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2505	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
2506	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
2507
2508	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
2509	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2510	AssertRCReturn(rc, rc);
2511
2512	/* Set up the MMIO RZ handlers. */
2513	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
2514	AssertRCReturn(rc, rc);
2515
2516	/* Set up the IOMMU RZ callbacks. */
2517	PDMIOMMUREGCC IommuReg;
2518	RT_ZERO(IommuReg);
2519	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2520	IommuReg.idxIommu = pThis->idxIommu;
2521	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2522	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2523	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2524	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2525
2526	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
2527	AssertRCReturn(rc, rc);
2528	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
2529	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2530	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2531	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
2532	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
2533	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
2534	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
2535
2536	return VINF_SUCCESS;
2537	}
2538
2539	#endif
2540
2541
2542	/**
2543	* The device registration structure.
2544	*/
2545	PDMDEVREG const g_DeviceIommuIntel =
2546	{
2547	/* .u32Version = */ PDM_DEVREG_VERSION,
2548	/* .uReserved0 = */ 0,
2549	/* .szName = */ "iommu-intel",
2550	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
2551	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
2552	/* .cMaxInstances = */ 1,
2553	/* .uSharedVersion = */ 42,
2554	/* .cbInstanceShared = */ sizeof(DMAR),
2555	/* .cbInstanceCC = */ sizeof(DMARCC),
2556	/* .cbInstanceRC = */ sizeof(DMARRC),
2557	/* .cMaxPciDevices = */ 1,
2558	/* .cMaxMsixVectors = */ 0,
2559	/* .pszDescription = */ "IOMMU (Intel)",
2560	#if defined(IN_RING3)
2561	/* .pszRCMod = */ "VBoxDDRC.rc",
2562	/* .pszR0Mod = */ "VBoxDDR0.r0",
2563	/* .pfnConstruct = */ iommuIntelR3Construct,
2564	/* .pfnDestruct = */ iommuIntelR3Destruct,
2565	/* .pfnRelocate = */ NULL,
2566	/* .pfnMemSetup = */ NULL,
2567	/* .pfnPowerOn = */ NULL,
2568	/* .pfnReset = */ iommuIntelR3Reset,
2569	/* .pfnSuspend = */ NULL,
2570	/* .pfnResume = */ NULL,
2571	/* .pfnAttach = */ NULL,
2572	/* .pfnDetach = */ NULL,
2573	/* .pfnQueryInterface = */ NULL,
2574	/* .pfnInitComplete = */ NULL,
2575	/* .pfnPowerOff = */ NULL,
2576	/* .pfnSoftReset = */ NULL,
2577	/* .pfnReserved0 = */ NULL,
2578	/* .pfnReserved1 = */ NULL,
2579	/* .pfnReserved2 = */ NULL,
2580	/* .pfnReserved3 = */ NULL,
2581	/* .pfnReserved4 = */ NULL,
2582	/* .pfnReserved5 = */ NULL,
2583	/* .pfnReserved6 = */ NULL,
2584	/* .pfnReserved7 = */ NULL,
2585	#elif defined(IN_RING0)
2586	/* .pfnEarlyConstruct = */ NULL,
2587	/* .pfnConstruct = */ iommuIntelRZConstruct,
2588	/* .pfnDestruct = */ NULL,
2589	/* .pfnFinalDestruct = */ NULL,
2590	/* .pfnRequest = */ NULL,
2591	/* .pfnReserved0 = */ NULL,
2592	/* .pfnReserved1 = */ NULL,
2593	/* .pfnReserved2 = */ NULL,
2594	/* .pfnReserved3 = */ NULL,
2595	/* .pfnReserved4 = */ NULL,
2596	/* .pfnReserved5 = */ NULL,
2597	/* .pfnReserved6 = */ NULL,
2598	/* .pfnReserved7 = */ NULL,
2599	#elif defined(IN_RC)
2600	/* .pfnConstruct = */ iommuIntelRZConstruct,
2601	/* .pfnReserved0 = */ NULL,
2602	/* .pfnReserved1 = */ NULL,
2603	/* .pfnReserved2 = */ NULL,
2604	/* .pfnReserved3 = */ NULL,
2605	/* .pfnReserved4 = */ NULL,
2606	/* .pfnReserved5 = */ NULL,
2607	/* .pfnReserved6 = */ NULL,
2608	/* .pfnReserved7 = */ NULL,
2609	#else
2610	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
2611	#endif
2612	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
2613	};
2614
2615	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2616

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88841

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