DevIommuIntel.cpp@ 89123

最後變更在這個檔案從89123是 89068,由 vboxsync 提交於 4 年前
Intel IOMMU: bugref:9967 Debug asserts here is sufficient, not expected to fail.
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1	/* $Id: DevIommuIntel.cpp 89068 2021-05-17 05:42:05Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock (not expected to fail). */
67	#ifdef IN_RING3
68	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69	#else
70	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71	do { \
72	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73	AssertRC(rcLock); \
74	} while (0)
75	#endif
76
77	/** Release the DMAR lock. */
78	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80	/** Asserts that the calling thread owns the DMAR lock. */
81	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82	do { \
83	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84	RT_NOREF1(a_pThisCC); \
85	} while (0)
86
87	/** Asserts that the calling thread does not own the DMAR lock. */
88	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89	do { \
90	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91	RT_NOREF1(a_pThisCC); \
92	} while (0)
93
94	/** The number of fault recording registers our implementation supports.
95	* Normal guest operation shouldn't trigger faults anyway, so we only support the
96	* minimum number of registers (which is 1).
97	*
98	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101	/** Offset of first register in group 0. */
102	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103	/** Offset of last register in group 0 (inclusive). */
104	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105	/** Last valid offset in group 0 (exclusive). */
106	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107	/** Size of the group 0 (in bytes). */
108	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109	/*< Implementation-specific MMIO offset of IVA_REG. /
110	#define DMAR_MMIO_OFF_IVA_REG 0xe50
111	/*< Implementation-specific MMIO offset of IOTLB_REG. /
112	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
114	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
116	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119	/** Offset of first register in group 1. */
120	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121	/** Offset of last register in group 1 (inclusive). */
122	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123	/** Last valid offset in group 1 (exclusive). */
124	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125	/** Size of the group 1 (in bytes). */
126	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128	/** DMAR implementation's major version number (exposed to software).
129	* We report 6 as the major version since we support queued-invalidations as
130	* software may make assumptions based on that.
131	*
132	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133	#define DMAR_VER_MAJOR 6
134	/** DMAR implementation's minor version number (exposed to software). */
135	#define DMAR_VER_MINOR 0
136
137	/** Release log prefix string. */
138	#define DMAR_LOG_PFX "Intel-IOMMU"
139	/** The current saved state version. */
140	#define DMAR_SAVED_STATE_VERSION 1
141
142
143	/*********************************************************************************************************************************
144	* Structures and Typedefs *
145	*********************************************************************************************************************************/
146	/**
147	* DMAR error diagnostics.
148	* Sorted alphabetically so it's easier to add and locate items, no other reason.
149	*
150	* @note Members of this enum are used as array indices, so no gaps in enum
151	* values are not allowed. Update g_apszDmarDiagDesc when you modify
152	* fields in this enum.
153	*/
154	typedef enum
155	{
156	kDmarDiag_None = 0,
157	kDmarDiag_CcmdReg_NotSupported,
158	kDmarDiag_CcmdReg_Qi_Enabled,
159	kDmarDiag_CcmdReg_Ttm_Invalid,
160	kDmarDiag_IqaReg_Dsc_Fetch_Error,
161	kDmarDiag_IqaReg_Dw_128_Invalid,
162	kDmarDiag_IqaReg_Dw_256_Invalid,
163	kDmarDiag_Iqei_Dsc_Type_Invalid,
164	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
165	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
166	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
167	kDmarDiag_Iqei_Ttm_Rsvd,
168	kDmarDiag_IqtReg_Qt_Invalid,
169	kDmarDiag_IqtReg_Qt_NotAligned,
170	kDmarDiag_Ir_Cfi_Blocked,
171	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
172	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
173	kDmarDiag_Ir_Rfi_Irte_Not_Present,
174	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
175	kDmarDiag_Ir_Rfi_Irte_Rsvd,
176	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
177	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
178	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
179	kDmarDiag_Ir_Rfi_Rsvd,
180	/* Member for determining array index limit. */
181	kDmarDiag_End,
182	/* Type size hack. */
183	kDmarDiag_32Bit_Hack = 0x7fffffff
184	} DMARDIAG;
185	AssertCompileSize(DMARDIAG, 4);
186
187	/** DMAR diagnostic enum description expansion.
188	* The below construct ensures typos in the input to this macro are caught
189	* during compile time. */
190	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
191
192	/** DMAR diagnostics description for members in DMARDIAG. */
193	static const char *const g_apszDmarDiagDesc[] =
194	{
195	DMARDIAG_DESC(None ),
196	DMARDIAG_DESC(CcmdReg_NotSupported ),
197	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
198	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
199	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
200	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
201	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
202	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
203	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
204	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
205	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
206	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
207	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
208	DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
209	DMARDIAG_DESC(Ir_Cfi_Blocked ),
210	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
211	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
212	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
213	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
214	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
215	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
216	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
217	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
218	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
219	/* kDmarDiag_End */
220	};
221	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
222	#undef DMARDIAG_DESC
223
224	/**
225	* The shared DMAR device state.
226	*/
227	typedef struct DMAR
228	{
229	/** IOMMU device index. */
230	uint32_t idxIommu;
231	/** DMAR magic. */
232	uint32_t u32Magic;
233
234	/** Registers (group 0). */
235	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
236	/** Registers (group 1). */
237	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
238
239	/** @name Lazily activated registers.
240	* These are the active values for lazily activated registers. Software is free to
241	* modify the actual register values while remapping/translation is enabled but they
242	* take effect only when explicitly signaled by software, hence we need to hold the
243	* active values separately.
244	* @{ */
245	/** Currently active IRTA_REG. */
246	uint64_t uIrtaReg;
247	/** Currently active RTADDR_REG. */
248	uint64_t uRtaddrReg;
249	/** @} */
250
251	/** @name Register copies for a tiny bit faster and more convenient access.
252	* @{ */
253	/** Copy of VER_REG. */
254	uint8_t uVerReg;
255	/** Alignment. */
256	uint8_t abPadding[7];
257	/** Copy of CAP_REG. */
258	uint64_t fCapReg;
259	/** Copy of ECAP_REG. */
260	uint64_t fExtCapReg;
261	/** @} */
262
263	/** The event semaphore the invalidation-queue thread waits on. */
264	SUPSEMEVENT hEvtInvQueue;
265	/** Whether the invalidation-queue thread has been signaled. */
266	bool volatile fInvQueueThreadSignaled;
267	/** Padding. */
268	bool afPadding0[3];
269	/** Error diagnostic. */
270	DMARDIAG enmDiag;
271	/** The MMIO handle. */
272	IOMMMIOHANDLE hMmio;
273
274	#ifdef VBOX_WITH_STATISTICS
275	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
276	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
277	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
278	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
279
280	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
281	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
282	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
283	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
284
285	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
286	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
287	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
288	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
289
290	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
291	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
292	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
293	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
294
295	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
296	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
297	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
298	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
299	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
300	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
301	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
302	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
303	#endif
304	} DMAR;
305	/** Pointer to the DMAR device state. */
306	typedef DMAR *PDMAR;
307	/** Pointer to the const DMAR device state. */
308	typedef DMAR const *PCDMAR;
309	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
310	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
311
312	/**
313	* The ring-3 DMAR device state.
314	*/
315	typedef struct DMARR3
316	{
317	/** Device instance. */
318	PPDMDEVINSR3 pDevInsR3;
319	/** The IOMMU helper. */
320	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
321	/** The invalidation-queue thread. */
322	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
323	} DMARR3;
324	/** Pointer to the ring-3 DMAR device state. */
325	typedef DMARR3 *PDMARR3;
326	/** Pointer to the const ring-3 DMAR device state. */
327	typedef DMARR3 const *PCDMARR3;
328
329	/**
330	* The ring-0 DMAR device state.
331	*/
332	typedef struct DMARR0
333	{
334	/** Device instance. */
335	PPDMDEVINSR0 pDevInsR0;
336	/** The IOMMU helper. */
337	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
338	} DMARR0;
339	/** Pointer to the ring-0 IOMMU device state. */
340	typedef DMARR0 *PDMARR0;
341	/** Pointer to the const ring-0 IOMMU device state. */
342	typedef DMARR0 const *PCDMARR0;
343
344	/**
345	* The raw-mode DMAR device state.
346	*/
347	typedef struct DMARRC
348	{
349	/** Device instance. */
350	PPDMDEVINSRC pDevInsRC;
351	/** The IOMMU helper. */
352	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
353	} DMARRC;
354	/** Pointer to the raw-mode DMAR device state. */
355	typedef DMARRC *PDMARRC;
356	/** Pointer to the const raw-mode DMAR device state. */
357	typedef DMARRC const *PCIDMARRC;
358
359	/** The DMAR device state for the current context. */
360	typedef CTX_SUFF(DMAR) DMARCC;
361	/** Pointer to the DMAR device state for the current context. */
362	typedef CTX_SUFF(PDMAR) PDMARCC;
363	/** Pointer to the const DMAR device state for the current context. */
364	typedef CTX_SUFF(PDMAR) const PCDMARCC;
365
366	/**
367	* Type of DMAR originated events that generate interrupts.
368	*/
369	typedef enum DMAREVENTTYPE
370	{
371	/** Invalidation completion event. */
372	DMAREVENTTYPE_INV_COMPLETE = 0,
373	/** Fault event. */
374	DMAREVENTTYPE_FAULT
375	} DMAREVENTTYPE;
376
377
378	/*********************************************************************************************************************************
379	* Global Variables *
380	*********************************************************************************************************************************/
381	/**
382	* Read-write masks for DMAR registers (group 0).
383	*/
384	static uint32_t const g_au32RwMasks0[] =
385	{
386	/* Offset Register Low High */
387	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
388	/* 0x004 Reserved */ 0,
389	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
390	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
391	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
392	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
393	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
394	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
395	/* 0x030 Reserved */ 0,
396	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
397	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
398	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
399	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
400	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
401	/* 0x048 Reserved */ 0, 0,
402	/* 0x050 Reserved */ 0, 0,
403	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
404	/* 0x060 Reserved */ 0,
405	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
406	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
407	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
408	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
409	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
410	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
411	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
412	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
413	/* 0x098 Reserved */ 0,
414	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
415	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
416	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
417	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
418	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
419	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
420	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
421	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
422	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
423	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
424	/* 0x0d8 Reserved */ 0,
425	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
426	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
427	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
428	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
429	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
430	/* 0x0f0 Reserved */ 0, 0,
431	/* 0x0f8 Reserved */ 0, 0,
432	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
433	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
434	/* 0x110 Reserved */ 0, 0,
435	/* 0x118 Reserved */ 0, 0,
436	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
437	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
438	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
439	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
440	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
441	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
442	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
443	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
444	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
445	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
446	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
447	/* 0x178 Reserved */ 0, 0,
448	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
449	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
450	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
451	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
452	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
453	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
454	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
455	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
456	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
457	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
458	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
459	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
460	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
461	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
462	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
463	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
464	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
465	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
466	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
467	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
468	};
469	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
470
471	/**
472	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
473	*/
474	static uint32_t const g_au32Rw1cMasks0[] =
475	{
476	/* Offset Register Low High */
477	/* 0x000 VER_REG */ 0,
478	/* 0x004 Reserved */ 0,
479	/* 0x008 CAP_REG */ 0, 0,
480	/* 0x010 ECAP_REG */ 0, 0,
481	/* 0x018 GCMD_REG */ 0,
482	/* 0x01c GSTS_REG */ 0,
483	/* 0x020 RTADDR_REG */ 0, 0,
484	/* 0x028 CCMD_REG */ 0, 0,
485	/* 0x030 Reserved */ 0,
486	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
487	/* 0x038 FECTL_REG */ 0,
488	/* 0x03c FEDATA_REG */ 0,
489	/* 0x040 FEADDR_REG */ 0,
490	/* 0x044 FEUADDR_REG */ 0,
491	/* 0x048 Reserved */ 0, 0,
492	/* 0x050 Reserved */ 0, 0,
493	/* 0x058 AFLOG_REG */ 0, 0,
494	/* 0x060 Reserved */ 0,
495	/* 0x064 PMEN_REG */ 0,
496	/* 0x068 PLMBASE_REG */ 0,
497	/* 0x06c PLMLIMIT_REG */ 0,
498	/* 0x070 PHMBASE_REG */ 0, 0,
499	/* 0x078 PHMLIMIT_REG */ 0, 0,
500	/* 0x080 IQH_REG */ 0, 0,
501	/* 0x088 IQT_REG */ 0, 0,
502	/* 0x090 IQA_REG */ 0, 0,
503	/* 0x098 Reserved */ 0,
504	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
505	/* 0x0a0 IECTL_REG */ 0,
506	/* 0x0a4 IEDATA_REG */ 0,
507	/* 0x0a8 IEADDR_REG */ 0,
508	/* 0x0ac IEUADDR_REG */ 0,
509	/* 0x0b0 IQERCD_REG */ 0, 0,
510	/* 0x0b8 IRTA_REG */ 0, 0,
511	/* 0x0c0 PQH_REG */ 0, 0,
512	/* 0x0c8 PQT_REG */ 0, 0,
513	/* 0x0d0 PQA_REG */ 0, 0,
514	/* 0x0d8 Reserved */ 0,
515	/* 0x0dc PRS_REG */ 0,
516	/* 0x0e0 PECTL_REG */ 0,
517	/* 0x0e4 PEDATA_REG */ 0,
518	/* 0x0e8 PEADDR_REG */ 0,
519	/* 0x0ec PEUADDR_REG */ 0,
520	/* 0x0f0 Reserved */ 0, 0,
521	/* 0x0f8 Reserved */ 0, 0,
522	/* 0x100 MTRRCAP_REG */ 0, 0,
523	/* 0x108 MTRRDEF_REG */ 0, 0,
524	/* 0x110 Reserved */ 0, 0,
525	/* 0x118 Reserved */ 0, 0,
526	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
527	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
528	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
529	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
530	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
531	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
532	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
533	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
534	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
535	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
536	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
537	/* 0x178 Reserved */ 0, 0,
538	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
539	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
540	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
541	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
542	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
543	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
544	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
545	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
546	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
547	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
548	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
549	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
550	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
551	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
552	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
553	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
554	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
555	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
556	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
557	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
558	};
559	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
560
561	/**
562	* Read-write masks for DMAR registers (group 1).
563	*/
564	static uint32_t const g_au32RwMasks1[] =
565	{
566	/* Offset Register Low High */
567	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
568	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
569	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
570	/* 0xe18 VCMDRSVD_REG */ 0, 0,
571	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
572	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
573	/* 0xe30 Reserved */ 0, 0,
574	/* 0xe38 Reserved */ 0, 0,
575	/* 0xe40 Reserved */ 0, 0,
576	/* 0xe48 Reserved */ 0, 0,
577	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
578	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
579	/* 0xe60 Reserved */ 0, 0,
580	/* 0xe68 Reserved */ 0, 0,
581	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
582	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
583	};
584	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
585	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
586
587	/**
588	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
589	*/
590	static uint32_t const g_au32Rw1cMasks1[] =
591	{
592	/* Offset Register Low High */
593	/* 0xe00 VCCAP_REG */ 0, 0,
594	/* 0xe08 VCMD_EO_REG */ 0, 0,
595	/* 0xe10 VCMD_REG */ 0, 0,
596	/* 0xe18 VCMDRSVD_REG */ 0, 0,
597	/* 0xe20 VCRSP_REG */ 0, 0,
598	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
599	/* 0xe30 Reserved */ 0, 0,
600	/* 0xe38 Reserved */ 0, 0,
601	/* 0xe40 Reserved */ 0, 0,
602	/* 0xe48 Reserved */ 0, 0,
603	/* 0xe50 IVA_REG */ 0, 0,
604	/* 0xe58 IOTLB_REG */ 0, 0,
605	/* 0xe60 Reserved */ 0, 0,
606	/* 0xe68 Reserved */ 0, 0,
607	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
608	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
609	};
610	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
611
612	/** Array of RW masks for each register group. */
613	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
614
615	/** Array of RW1C masks for each register group. */
616	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
617
618	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
619	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
620
621
622	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
623	/** @todo Add IOMMU struct size/alignment verification, see
624	* Devices/testcase/Makefile.kmk and
625	* Devices/testcase/tstDeviceStructSize[RC].cpp */
626
627	/**
628	* Returns the number of supported adjusted guest-address width (SAGAW) in bits
629	* given a CAP_REG.SAGAW value.
630	*
631	* @returns Number of SAGAW bits.
632	* @param uSagaw The CAP_REG.SAGAW value.
633	*/
634	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
635	{
636	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
637	return 30 + (uSagaw * 9);
638	return 0;
639	}
640
641
642	/**
643	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
644	* guest address width (MGAW).
645	*
646	* @returns The CAP_REG.SAGAW value.
647	* @param uMgaw The CAP_REG.MGAW value.
648	*/
649	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
650	{
651	switch (uMgaw + 1)
652	{
653	case 39: return 1;
654	case 48: return 2;
655	case 57: return 3;
656	}
657	return 0;
658	}
659
660
661	/**
662	* Returns whether the interrupt remapping fault is qualified or not.
663	*
664	* @returns @c true if qualified, @c false otherwise.
665	* @param enmIrFault The interrupt remapping fault condition.
666	*/
667	static bool vtdIrFaultIsQualified(VTD_IR_FAULT_T enmIrFault)
668	{
669	switch (enmIrFault)
670	{
671	case kIrf_Irte_Not_Present:
672	case kIrf_Irte_Present_Rsvd:
673	case kIrf_Irte_Present_Invalid:
674	case kIrf_Pid_Read_Failed:
675	case kIrf_Pid_Rsvd:
676	return true;
677	default:
678	return false;
679	}
680	}
681
682
683	/**
684	* Returns table translation mode's descriptive name.
685	*
686	* @returns The descriptive name.
687	* @param uTtm The RTADDR_REG.TTM value.
688	*/
689	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
690	{
691	Assert(!(uTtm & 3));
692	static const char* s_apszTtmNames[] =
693	{
694	"Legacy Mode",
695	"Scalable Mode",
696	"Reserved",
697	"Abort-DMA Mode"
698	};
699	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
700	}
701
702
703	/**
704	* Gets the index of the group the register belongs to given its MMIO offset.
705	*
706	* @returns The group index.
707	* @param offReg The MMIO offset of the register.
708	* @param cbReg The size of the access being made (for bounds checking on
709	* debug builds).
710	*/
711	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
712	{
713	uint16_t const offLast = offReg + cbReg - 1;
714	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
715	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
716	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
717	}
718
719
720	/**
721	* Gets the group the register belongs to given its MMIO offset.
722	*
723	* @returns Pointer to the first element of the register group.
724	* @param pThis The shared DMAR device state.
725	* @param offReg The MMIO offset of the register.
726	* @param cbReg The size of the access being made (for bounds checking on
727	* debug builds).
728	* @param pIdxGroup Where to store the index of the register group the register
729	* belongs to.
730	*/
731	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
732	{
733	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
734	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
735	return apbRegs[*pIdxGroup];
736	}
737
738
739	/**
740	* Const/read-only version of dmarRegGetGroup.
741	*
742	* @copydoc dmarRegGetGroup
743	*/
744	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
745	{
746	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
747	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
748	return apbRegs[*pIdxGroup];
749	}
750
751
752	/**
753	* Writes a 32-bit register with the exactly the supplied value.
754	*
755	* @param pThis The shared DMAR device state.
756	* @param offReg The MMIO offset of the register.
757	* @param uReg The 32-bit value to write.
758	*/
759	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
760	{
761	uint8_t idxGroup;
762	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
763	NOREF(idxGroup);
764	(uint32_t )(pabRegs + offReg) = uReg;
765	}
766
767
768	/**
769	* Writes a 64-bit register with the exactly the supplied value.
770	*
771	* @param pThis The shared DMAR device state.
772	* @param offReg The MMIO offset of the register.
773	* @param uReg The 64-bit value to write.
774	*/
775	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
776	{
777	uint8_t idxGroup;
778	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
779	NOREF(idxGroup);
780	(uint64_t )(pabRegs + offReg) = uReg;
781	}
782
783
784	/**
785	* Reads a 32-bit register with exactly the value it contains.
786	*
787	* @returns The raw register value.
788	* @param pThis The shared DMAR device state.
789	* @param offReg The MMIO offset of the register.
790	*/
791	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
792	{
793	uint8_t idxGroup;
794	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
795	NOREF(idxGroup);
796	return (uint32_t )(pabRegs + offReg);
797	}
798
799
800	/**
801	* Reads a 64-bit register with exactly the value it contains.
802	*
803	* @returns The raw register value.
804	* @param pThis The shared DMAR device state.
805	* @param offReg The MMIO offset of the register.
806	*/
807	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
808	{
809	uint8_t idxGroup;
810	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
811	NOREF(idxGroup);
812	return (uint64_t )(pabRegs + offReg);
813	}
814
815
816	/**
817	* Reads a 32-bit register with exactly the value it contains along with their
818	* corresponding masks
819	*
820	* @param pThis The shared DMAR device state.
821	* @param offReg The MMIO offset of the register.
822	* @param puReg Where to store the raw 32-bit register value.
823	* @param pfRwMask Where to store the RW mask corresponding to this register.
824	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
825	*/
826	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
827	{
828	uint8_t idxGroup;
829	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
830	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
831	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
832	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
833	puReg = (uint32_t *)(pabRegs + offReg);
834	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
835	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
836	}
837
838
839	/**
840	* Reads a 64-bit register with exactly the value it contains along with their
841	* corresponding masks.
842	*
843	* @param pThis The shared DMAR device state.
844	* @param offReg The MMIO offset of the register.
845	* @param puReg Where to store the raw 64-bit register value.
846	* @param pfRwMask Where to store the RW mask corresponding to this register.
847	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
848	*/
849	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
850	{
851	uint8_t idxGroup;
852	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
853	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
854	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
855	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
856	puReg = (uint64_t *)(pabRegs + offReg);
857	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
858	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
859	}
860
861
862	/**
863	* Writes a 32-bit register as it would be when written by software.
864	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
865	*
866	* @returns The value that's actually written to the register.
867	* @param pThis The shared DMAR device state.
868	* @param offReg The MMIO offset of the register.
869	* @param uReg The 32-bit value to write.
870	* @param puPrev Where to store the register value prior to writing.
871	*/
872	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
873	{
874	/* Read current value from the 32-bit register. */
875	uint32_t uCurReg;
876	uint32_t fRwMask;
877	uint32_t fRw1cMask;
878	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
879	*puPrev = uCurReg;
880
881	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
882	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
883	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
884	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
885
886	/* Write new value to the 32-bit register. */
887	dmarRegWriteRaw32(pThis, offReg, uNewReg);
888	return uNewReg;
889	}
890
891
892	/**
893	* Writes a 64-bit register as it would be when written by software.
894	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
895	*
896	* @returns The value that's actually written to the register.
897	* @param pThis The shared DMAR device state.
898	* @param offReg The MMIO offset of the register.
899	* @param uReg The 64-bit value to write.
900	* @param puPrev Where to store the register value prior to writing.
901	*/
902	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
903	{
904	/* Read current value from the 64-bit register. */
905	uint64_t uCurReg;
906	uint64_t fRwMask;
907	uint64_t fRw1cMask;
908	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
909	*puPrev = uCurReg;
910
911	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
912	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
913	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
914	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
915
916	/* Write new value to the 64-bit register. */
917	dmarRegWriteRaw64(pThis, offReg, uNewReg);
918	return uNewReg;
919	}
920
921
922	/**
923	* Reads a 32-bit register as it would be when read by software.
924	*
925	* @returns The register value.
926	* @param pThis The shared DMAR device state.
927	* @param offReg The MMIO offset of the register.
928	*/
929	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
930	{
931	return dmarRegReadRaw32(pThis, offReg);
932	}
933
934
935	/**
936	* Reads a 64-bit register as it would be when read by software.
937	*
938	* @returns The register value.
939	* @param pThis The shared DMAR device state.
940	* @param offReg The MMIO offset of the register.
941	*/
942	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
943	{
944	return dmarRegReadRaw64(pThis, offReg);
945	}
946
947
948	/**
949	* Modifies a 32-bit register.
950	*
951	* @param pThis The shared DMAR device state.
952	* @param offReg The MMIO offset of the register.
953	* @param fAndMask The AND mask (applied first).
954	* @param fOrMask The OR mask.
955	* @remarks This does NOT apply RO or RW1C masks while modifying the
956	* register.
957	*/
958	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
959	{
960	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
961	uReg = (uReg & fAndMask) \| fOrMask;
962	dmarRegWriteRaw32(pThis, offReg, uReg);
963	}
964
965
966	/**
967	* Modifies a 64-bit register.
968	*
969	* @param pThis The shared DMAR device state.
970	* @param offReg The MMIO offset of the register.
971	* @param fAndMask The AND mask (applied first).
972	* @param fOrMask The OR mask.
973	* @remarks This does NOT apply RO or RW1C masks while modifying the
974	* register.
975	*/
976	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
977	{
978	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
979	uReg = (uReg & fAndMask) \| fOrMask;
980	dmarRegWriteRaw64(pThis, offReg, uReg);
981	}
982
983
984	/**
985	* Checks if the invalidation-queue is empty.
986	*
987	* Extended version which optionally returns the current queue head and tail
988	* offsets.
989	*
990	* @returns @c true if empty, @c false otherwise.
991	* @param pThis The shared DMAR device state.
992	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
993	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
994	*/
995	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
996	{
997	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
998	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
999	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1000
1001	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1002	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1003	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1004	if (poffQh)
1005	*poffQh = uIqhReg;
1006	if (poffQt)
1007	*poffQt = uIqtReg;
1008	return uIqtReg == uIqhReg;
1009	}
1010
1011
1012	/**
1013	* Checks if the invalidation-queue is empty.
1014	*
1015	* @returns @c true if empty, @c false otherwise.
1016	* @param pThis The shared DMAR device state.
1017	*/
1018	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1019	{
1020	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1021	}
1022
1023
1024	/**
1025	* Checks if the invalidation-queue is capable of processing requests.
1026	*
1027	* @returns @c true if the invalidation-queue can process requests, @c false
1028	* otherwise.
1029	* @param pThis The shared DMAR device state.
1030	*/
1031	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1032	{
1033	/* Check if queued-invalidation is enabled. */
1034	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1035	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1036	{
1037	/* Check if there are no invalidation-queue or timeout errors. */
1038	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1039	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1040	return true;
1041	}
1042	return false;
1043	}
1044
1045
1046	/**
1047	* Wakes up the invalidation-queue thread if there are requests to be processed.
1048	*
1049	* @param pDevIns The IOMMU device instance.
1050	*/
1051	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1052	{
1053	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1054	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1055	Log4Func(("\n"));
1056
1057	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1058
1059	if ( dmarInvQueueCanProcessRequests(pThis)
1060	&& !dmarInvQueueIsEmpty(pThis)
1061	&& !ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, true))
1062	{
1063	Log4Func(("Signaling the invalidation-queue thread\n"));
1064	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1065	}
1066	}
1067
1068
1069	/**
1070	* Raises an event on behalf of the DMAR.
1071	*
1072	* These are events that are generated by the DMAR itself (like faults and
1073	* invalidation completion notifications).
1074	*
1075	* @param pDevIns The IOMMU device instance.
1076	* @param enmEventType The DMAR event type.
1077	*
1078	* @remarks The DMAR lock must be held while calling this function.
1079	*/
1080	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1081	{
1082	uint16_t offCtlReg;
1083	uint32_t fIntrMaskedMask;
1084	uint32_t fIntrPendingMask;
1085	uint16_t offMsiAddrLoReg;
1086	uint16_t offMsiAddrHiReg;
1087	uint16_t offMsiDataReg;
1088	switch (enmEventType)
1089	{
1090	case DMAREVENTTYPE_INV_COMPLETE:
1091	{
1092	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1093	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1094	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1095	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1096	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1097	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1098	break;
1099	}
1100
1101	case DMAREVENTTYPE_FAULT:
1102	{
1103	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1104	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1105	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1106	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1107	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1108	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1109	break;
1110	}
1111
1112	default:
1113	{
1114	/* Shouldn't ever happen. */
1115	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1116	}
1117	}
1118
1119	/* Check if software has masked the interrupt. */
1120	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1121	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1122	if (!(uCtlReg & fIntrMaskedMask))
1123	{
1124	/*
1125	* Interrupt is unmasked, raise it.
1126	* Interrupts generated by the DMAR have trigger mode and level as 0.
1127	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1128	*/
1129	MSIMSG Msi;
1130	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1131	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1132	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1133	Assert(Msi.Data.n.u1Level == 0);
1134	Assert(Msi.Data.n.u1TriggerMode == 0);
1135
1136	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1137	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1138
1139	/* Clear interrupt pending bit. */
1140	uCtlReg &= ~fIntrPendingMask;
1141	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1142	}
1143	else
1144	{
1145	/* Interrupt is masked, set the interrupt pending bit. */
1146	uCtlReg \|= fIntrPendingMask;
1147	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1148	}
1149	}
1150
1151
1152	/**
1153	* Raises an interrupt in response to a fault event.
1154	*
1155	* @param pDevIns The IOMMU device instance.
1156	*
1157	* @remarks This assumes the caller has already set the required status bits in the
1158	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1159	*/
1160	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1161	{
1162	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1163	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1164	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1165
1166	#ifdef RT_STRICT
1167	{
1168	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1169	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1170	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1171	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1172	\| VTD_BF_FSTS_REG_IQE_MASK;
1173	Assert(uFstsReg & fFaultMask);
1174	}
1175	#endif
1176	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1177	}
1178
1179
1180	#ifdef IN_RING3
1181	/**
1182	* Raises an interrupt in response to an invalidation (complete) event.
1183	*
1184	* @param pDevIns The IOMMU device instance.
1185	*/
1186	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1187	{
1188	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1189	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1190	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1191
1192	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1193	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1194	{
1195	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1196	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1197	}
1198	}
1199	#endif /* IN_RING3 */
1200
1201
1202	/**
1203	* Checks if a primary fault can be recorded.
1204	*
1205	* @returns @c true if the fault can be recorded, @c false otherwise.
1206	* @param pDevIns The IOMMU device instance.
1207	* @param pThis The shared DMAR device state.
1208	*
1209	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1210	* NOT call it unless there is a fault condition!
1211	*/
1212	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1213	{
1214	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1215	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1216
1217	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1218	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1219	return false;
1220
1221	/*
1222	* If we add more FRCD registers, we'll have to loop through them here.
1223	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1224	* nor do we need to increment FRI.
1225	*
1226	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1227	*/
1228	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1229	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1230	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1231	{
1232	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1233	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1234	return false;
1235	}
1236
1237	return true;
1238	}
1239
1240
1241	/**
1242	* Records an interrupt request fault.
1243	*
1244	* @param pDevIns The IOMMU device instance.
1245	* @param enmDiag The diagnostic reason.
1246	* @param enmIrFault The interrupt fault reason.
1247	* @param idDevice The device ID (bus, device, function).
1248	* @param idxIntr The interrupt index.
1249	*/
1250	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IR_FAULT_T enmIrFault, uint16_t idDevice,
1251	uint16_t idxIntr)
1252	{
1253	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1254	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1255
1256	DMAR_LOCK(pDevIns, pThisCC);
1257
1258	/* Update the diagnostic reason. */
1259	pThis->enmDiag = enmDiag;
1260
1261	/* We don't support advance fault logging. */
1262	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1263
1264	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1265	{
1266	/* Update the fault recording registers with the fault information. */
1267	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1268	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1269	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1270	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1271	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1272	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1273
1274	/* Set the Pending Primary Fault (PPF) field in the status register. */
1275	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1276
1277	/* Raise interrupt if necessary. */
1278	dmarFaultEventRaiseInterrupt(pDevIns);
1279	}
1280
1281	DMAR_UNLOCK(pDevIns, pThisCC);
1282	}
1283
1284
1285	/**
1286	* Records a qualified interrupt request fault.
1287	*
1288	* Qualified faults are those that can be suppressed by software using the FPD bit
1289	* in the IRTE.
1290	*
1291	* @param pDevIns The IOMMU device instance.
1292	* @param enmDiag The diagnostic reason.
1293	* @param enmIrFault The interrupt fault reason.
1294	* @param idDevice The device ID (bus, device, function).
1295	* @param idxIntr The interrupt index.
1296	* @param pIrte The IRTE that caused this fault.
1297	*/
1298	static void dmarIrFaultRecordQualified(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IR_FAULT_T enmIrFault, uint16_t idDevice,
1299	uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1300	{
1301	Assert(vtdIrFaultIsQualified(enmIrFault));
1302	Assert(pIrte);
1303	if (!(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK))
1304	return dmarIrFaultRecord(pDevIns, enmDiag, enmIrFault, idDevice, idxIntr);
1305	}
1306
1307
1308	/**
1309	* Records an IQE fault.
1310	*
1311	* @param pDevIns The IOMMU device instance.
1312	* @param enmIqei The IQE information.
1313	* @param enmDiag The diagnostic reason.
1314	*/
1315	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQEI_T enmIqei)
1316	{
1317	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1318	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1319
1320	DMAR_LOCK(pDevIns, pThisCC);
1321
1322	/* Update the diagnostic reason. */
1323	pThis->enmDiag = enmDiag;
1324
1325	/* Set the error bit. */
1326	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1327	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1328
1329	/* Set the error information. */
1330	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1331	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1332
1333	dmarFaultEventRaiseInterrupt(pDevIns);
1334
1335	DMAR_UNLOCK(pDevIns, pThisCC);
1336	}
1337
1338
1339	/**
1340	* Handles writes to GCMD_REG.
1341	*
1342	* @returns Strict VBox status code.
1343	* @param pDevIns The IOMMU device instance.
1344	* @param uGcmdReg The value written to GCMD_REG.
1345	*/
1346	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1347	{
1348	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1349	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1350	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1351	uint64_t const fExtCapReg = pThis->fExtCapReg;
1352
1353	/* Queued-invalidation. */
1354	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1355	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1356	{
1357	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1358	{
1359	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1360	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1361	}
1362	else
1363	{
1364	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1365	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1366	}
1367	}
1368
1369	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1370	{
1371	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1372	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1373	{
1374	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1375	* supported. */
1376	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1377	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1378	}
1379
1380	/* Interrupt remapping. */
1381	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1382	{
1383	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1384	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1385	else
1386	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1387	}
1388
1389	/* Compatibility format interrupts. */
1390	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1391	{
1392	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1393	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1394	else
1395	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1396	}
1397	}
1398
1399	/* Set Root Table Pointer (SRTP). */
1400	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1401	{
1402	/** @todo Perform global invalidation of all remapping translation caches when
1403	* ESRTPS is supported. */
1404	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1405	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1406	}
1407
1408	/* Translation (DMA remapping). */
1409	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1410	{
1411	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1412	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1413	else
1414	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1415	}
1416
1417	return VINF_SUCCESS;
1418	}
1419
1420
1421	/**
1422	* Handles writes to CCMD_REG.
1423	*
1424	* @returns Strict VBox status code.
1425	* @param pDevIns The IOMMU device instance.
1426	* @param offReg The MMIO register offset.
1427	* @param cbReg The size of the MMIO access (in bytes).
1428	* @param uCcmdReg The value written to CCMD_REG.
1429	*/
1430	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1431	{
1432	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1433	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1434	{
1435	/* Check if we need to invalidate the context-context. */
1436	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1437	if (fIcc)
1438	{
1439	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1440	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1441	if (uMajorVersion < 6)
1442	{
1443	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1444	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1445	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1446	{
1447	/* Verify table translation mode is legacy. */
1448	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1449	if (fTtm == VTD_TTM_LEGACY_MODE)
1450	{
1451	/** @todo Invalidate. */
1452	return VINF_SUCCESS;
1453	}
1454	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1455	}
1456	else
1457	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1458	}
1459	else
1460	pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1461	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1462	}
1463	}
1464	return VINF_SUCCESS;
1465	}
1466
1467
1468	/**
1469	* Handles writes to FECTL_REG.
1470	*
1471	* @returns Strict VBox status code.
1472	* @param pDevIns The IOMMU device instance.
1473	* @param uFectlReg The value written to FECTL_REG.
1474	*/
1475	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1476	{
1477	/*
1478	* If software unmasks the interrupt when the interrupt is pending, we must raise
1479	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1480	*/
1481	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1482	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1483	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1484	return VINF_SUCCESS;
1485	}
1486
1487
1488	/**
1489	* Handles writes to FSTS_REG.
1490	*
1491	* @returns Strict VBox status code.
1492	* @param pDevIns The IOMMU device instance.
1493	* @param uFstsReg The value written to FSTS_REG.
1494	* @param uPrev The value in FSTS_REG prior to writing it.
1495	*/
1496	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1497	{
1498	/*
1499	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1500	* the interrupt pending (IP) bit must be cleared.
1501	*
1502	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1503	*/
1504	uint32_t const fChanged = uPrev ^ uFstsReg;
1505	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1506	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1507	{
1508	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1509	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1510	}
1511	return VINF_SUCCESS;
1512	}
1513
1514
1515	/**
1516	* Handles writes to IQT_REG.
1517	*
1518	* @returns Strict VBox status code.
1519	* @param pDevIns The IOMMU device instance.
1520	* @param offReg The MMIO register offset.
1521	* @param uIqtReg The value written to IQT_REG.
1522	*/
1523	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1524	{
1525	/* We only care about the low 32-bits, high 32-bits are reserved. */
1526	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1527	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1528
1529	/* Paranoia. */
1530	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1531
1532	uint32_t const offQt = uIqtReg;
1533	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1534	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1535
1536	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1537	if ( fDw != VTD_IQA_REG_DW_256_BIT
1538	\|\| !(offQt & RT_BIT(4)))
1539	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1540	else
1541	{
1542	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1543	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1544	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kIqei_QueueTailNotAligned);
1545	}
1546	return VINF_SUCCESS;
1547	}
1548
1549
1550	/**
1551	* Handles writes to IQA_REG.
1552	*
1553	* @returns Strict VBox status code.
1554	* @param pDevIns The IOMMU device instance.
1555	* @param offReg The MMIO register offset.
1556	* @param uIqaReg The value written to IQA_REG.
1557	*/
1558	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1559	{
1560	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1561	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1562
1563	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1564	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1565	* cannot happen or that it's ignored when it does happen. */
1566
1567	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1568	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1569	if (fDw == VTD_IQA_REG_DW_256_BIT)
1570	{
1571	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1572	if (fSupports256BitDw)
1573	{ /* likely */ }
1574	else
1575	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, kIqei_InvalidDescriptorWidth);
1576	}
1577	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1578
1579	return VINF_SUCCESS;
1580	}
1581
1582
1583	/**
1584	* Handles writes to ICS_REG.
1585	*
1586	* @returns Strict VBox status code.
1587	* @param pDevIns The IOMMU device instance.
1588	* @param uIcsReg The value written to ICS_REG.
1589	*/
1590	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1591	{
1592	/*
1593	* If the IP field is set when software services the interrupt condition,
1594	* (by clearing the IWC field), the IP field must be cleared.
1595	*/
1596	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1597	{
1598	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1599	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1600	}
1601	return VINF_SUCCESS;
1602	}
1603
1604
1605	/**
1606	* Handles writes to IECTL_REG.
1607	*
1608	* @returns Strict VBox status code.
1609	* @param pDevIns The IOMMU device instance.
1610	* @param uIectlReg The value written to IECTL_REG.
1611	*/
1612	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1613	{
1614	/*
1615	* If software unmasks the interrupt when the interrupt is pending, we must raise
1616	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1617	*/
1618	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1619	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1620	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1621	return VINF_SUCCESS;
1622	}
1623
1624
1625	/**
1626	* Handles writes to FRCD_REG (High 64-bits).
1627	*
1628	* @returns Strict VBox status code.
1629	* @param pDevIns The IOMMU device instance.
1630	* @param offReg The MMIO register offset.
1631	* @param cbReg The size of the MMIO access (in bytes).
1632	* @param uFrcdHiReg The value written to FRCD_REG.
1633	* @param uPrev The value in FRCD_REG prior to writing it.
1634	*/
1635	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
1636	{
1637	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
1638	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
1639	{
1640	/*
1641	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
1642	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
1643	* has only 1 FRCD register.
1644	*
1645	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1646	*/
1647	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1648	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
1649	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
1650	{
1651	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
1652	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1653	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
1654	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1655	}
1656	}
1657	return VINF_SUCCESS;
1658	}
1659
1660
1661	/**
1662	* Memory access bulk (one or more 4K pages) request from a device.
1663	*
1664	* @returns VBox status code.
1665	* @param pDevIns The IOMMU device instance.
1666	* @param idDevice The device ID (bus, device, function).
1667	* @param cIovas The number of addresses being accessed.
1668	* @param pauIovas The I/O virtual addresses for each page being accessed.
1669	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1670	* @param paGCPhysSpa Where to store the translated physical addresses.
1671	*
1672	* @thread Any.
1673	*/
1674	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1675	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1676	{
1677	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1678	return VERR_NOT_IMPLEMENTED;
1679	}
1680
1681
1682	/**
1683	* Memory access transaction from a device.
1684	*
1685	* @returns VBox status code.
1686	* @param pDevIns The IOMMU device instance.
1687	* @param idDevice The device ID (bus, device, function).
1688	* @param uIova The I/O virtual address being accessed.
1689	* @param cbIova The size of the access.
1690	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1691	* @param pGCPhysSpa Where to store the translated system physical address.
1692	* @param pcbContiguous Where to store the number of contiguous bytes translated
1693	* and permission-checked.
1694	*
1695	* @thread Any.
1696	*/
1697	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1698	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1699	{
1700	RT_NOREF6(idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
1701
1702	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1703	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1704
1705	DMAR_LOCK(pDevIns, pThisCC);
1706	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1707	DMAR_UNLOCK(pDevIns, pThisCC);
1708
1709	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
1710	{
1711	if (fFlags & PDMIOMMU_MEM_F_READ)
1712	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
1713	else
1714	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
1715
1716	return VERR_NOT_IMPLEMENTED;
1717	}
1718
1719	*pGCPhysSpa = uIova;
1720	*pcbContiguous = cbIova;
1721	return VINF_SUCCESS;
1722	}
1723
1724
1725	/**
1726	* Reads an IRTE from guest memory.
1727	*
1728	* @returns VBox status code.
1729	* @param pDevIns The IOMMU device instance.
1730	* @param uIrtaReg The IRTA_REG.
1731	* @param idxIntr The interrupt index.
1732	* @param pIrte Where to store the read IRTE.
1733	*/
1734	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
1735	{
1736	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
1737
1738	size_t const cbIrte = sizeof(*pIrte);
1739	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
1740	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
1741	}
1742
1743
1744	/**
1745	* Remaps the source MSI to the destination MSI given the IRTE.
1746	*
1747	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
1748	* IRTA_REG.EIME).
1749	* @param pIrte The IRTE used for the remapping.
1750	* @param pMsiIn The source MSI (currently unused).
1751	* @param pMsiOut Where to store the remapped MSI.
1752	*/
1753	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1754	{
1755	NOREF(pMsiIn);
1756	uint64_t const uIrteQword0 = pIrte->au64[0];
1757
1758	/*
1759	* Let's start with a clean slate and preserve unspecified bits if the need arises.
1760	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
1761	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
1762	* it copies it from the source MSI.
1763	*/
1764	RT_ZERO(*pMsiOut);
1765	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
1766	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
1767	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
1768	if (fExtIntrMode)
1769	{
1770	/*
1771	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
1772	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
1773	*/
1774	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
1775	pMsiOut->Addr.n.u8DestId = idDest;
1776	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
1777	}
1778	else
1779	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
1780
1781	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
1782	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
1783	pMsiOut->Data.n.u1Level = 1;
1784	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
1785	}
1786
1787
1788	/**
1789	* Handles remapping of interrupts in remappable interrupt format.
1790	*
1791	* @returns VBox status code.
1792	* @param pDevIns The IOMMU device instance.
1793	* @param uIrtaReg The IRTA_REG.
1794	* @param idDevice The device ID (bus, device, function).
1795	* @param pMsiIn The source MSI.
1796	* @param pMsiOut Where to store the remapped MSI.
1797	*/
1798	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1799	{
1800	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
1801
1802	/* Validate reserved bits in the interrupt request. */
1803	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
1804	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
1805	{
1806	/* Compute the index into the interrupt remap table. */
1807	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
1808	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
1809	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
1810	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
1811	uint16_t const idxIntr = fSubHandleValid
1812	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
1813	: uHandle;
1814
1815	/* Validate the index. */
1816	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
1817	if (idxIntr < cEntries)
1818	{
1819	/** @todo Implement and read IRTE from interrupt-entry cache here. */
1820
1821	/* Read the interrupt remap table entry (IRTE) at the index. */
1822	VTD_IRTE_T Irte;
1823	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
1824	if (RT_SUCCESS(rc))
1825	{
1826	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
1827	uint64_t const uIrteQword0 = Irte.au64[0];
1828	uint64_t const uIrteQword1 = Irte.au64[1];
1829	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
1830	if (fPresent)
1831	{
1832	/* Validate reserved bits in the IRTE. */
1833	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
1834	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
1835	if ( !(uIrteQword0 & ~fQw0ValidMask)
1836	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
1837	{
1838	/* Validate requester id (the device ID) as configured in the IRTE. */
1839	bool fSrcValid;
1840	DMARDIAG enmIrDiag;
1841	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
1842	switch (fSvt)
1843	{
1844	case VTD_IRTE_SVT_NONE:
1845	{
1846	fSrcValid = true;
1847	enmIrDiag = kDmarDiag_None;
1848	break;
1849	}
1850
1851	case VTD_IRTE_SVT_VALIDATE_MASK:
1852	{
1853	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
1854	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
1855	uint16_t const fValidMask = s_afValidMasks[idxMask];
1856	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
1857	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
1858	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
1859	break;
1860	}
1861
1862	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
1863	{
1864	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
1865	uint8_t const uBusFirst = RT_HI_U8(idSource);
1866	uint8_t const uBusLast = RT_LO_U8(idSource);
1867	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
1868	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
1869	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
1870	break;
1871	}
1872
1873	default:
1874	{
1875	fSrcValid = false;
1876	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
1877	break;
1878	}
1879	}
1880
1881	if (fSrcValid)
1882	{
1883	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
1884	if (!fPostedMode)
1885	{
1886	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
1887	return VINF_SUCCESS;
1888	}
1889	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, kIrf_Irte_Present_Rsvd,
1890	idDevice, idxIntr, &Irte);
1891	}
1892	else
1893	dmarIrFaultRecordQualified(pDevIns, enmIrDiag, kIrf_Irte_Present_Rsvd, idDevice, idxIntr, &Irte);
1894	}
1895	else
1896	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, kIrf_Irte_Present_Rsvd, idDevice,
1897	idxIntr, &Irte);
1898	}
1899	else
1900	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, kIrf_Irte_Not_Present, idDevice,
1901	idxIntr, &Irte);
1902	}
1903	else
1904	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, kIrf_Irte_Read_Failed, idDevice, idxIntr);
1905	}
1906	else
1907	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, kIrf_Intr_Index_Invalid, idDevice, idxIntr);
1908	}
1909	else
1910	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, kIrf_Remappable_Intr_Rsvd, idDevice, 0 /* idxIntr */);
1911	return VERR_IOMMU_INTR_REMAP_DENIED;
1912	}
1913
1914
1915	/**
1916	* Interrupt remap request from a device.
1917	*
1918	* @returns VBox status code.
1919	* @param pDevIns The IOMMU device instance.
1920	* @param idDevice The device ID (bus, device, function).
1921	* @param pMsiIn The source MSI.
1922	* @param pMsiOut Where to store the remapped MSI.
1923	*/
1924	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1925	{
1926	/* Validate. */
1927	Assert(pDevIns);
1928	Assert(pMsiIn);
1929	Assert(pMsiOut);
1930	RT_NOREF1(idDevice);
1931
1932	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1933	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1934
1935	/* Lock and read all registers required for interrupt remapping up-front. */
1936	DMAR_LOCK(pDevIns, pThisCC);
1937	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1938	uint64_t const uIrtaReg = pThis->uIrtaReg;
1939	DMAR_UNLOCK(pDevIns, pThisCC);
1940
1941	/* Check if interrupt remapping is enabled. */
1942	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
1943	{
1944	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
1945	if (!fIsRemappable)
1946	{
1947	/* Handle compatibility format interrupts. */
1948	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
1949
1950	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
1951	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
1952	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
1953	{
1954	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, kIrf_Cfi_Blocked, idDevice, 0 /* idxIntr */);
1955	return VERR_IOMMU_INTR_REMAP_DENIED;
1956	}
1957
1958	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
1959	pMsiOut = pMsiIn;
1960	return VINF_SUCCESS;
1961	}
1962
1963	/* Handle remappable format interrupts. */
1964	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
1965	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
1966	}
1967
1968	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
1969	pMsiOut = pMsiIn;
1970	return VINF_SUCCESS;
1971	}
1972
1973
1974	/**
1975	* @callback_method_impl{FNIOMMMIONEWWRITE}
1976	*/
1977	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1978	{
1979	RT_NOREF1(pvUser);
1980	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1981
1982	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1983	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1984
1985	uint16_t const offReg = off;
1986	uint16_t const offLast = offReg + cb - 1;
1987	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1988	{
1989	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1990	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
1991
1992	uint64_t uPrev = 0;
1993	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
1994	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
1995	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1996	switch (off)
1997	{
1998	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
1999	{
2000	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
2001	break;
2002	}
2003
2004	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
2005	case VTD_MMIO_OFF_CCMD_REG + 4:
2006	{
2007	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
2008	break;
2009	}
2010
2011	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
2012	{
2013	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
2014	break;
2015	}
2016
2017	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
2018	{
2019	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
2020	break;
2021	}
2022
2023	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
2024	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
2025	{
2026	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
2027	break;
2028	}
2029
2030	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
2031	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
2032	{
2033	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
2034	break;
2035	}
2036
2037	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
2038	{
2039	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
2040	break;
2041	}
2042
2043	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
2044	{
2045	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
2046	break;
2047	}
2048
2049	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
2050	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
2051	{
2052	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
2053	break;
2054	}
2055	}
2056
2057	DMAR_UNLOCK(pDevIns, pThisCC);
2058	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
2059	return rcStrict;
2060	}
2061
2062	return VINF_IOM_MMIO_UNUSED_FF;
2063	}
2064
2065
2066	/**
2067	* @callback_method_impl{FNIOMMMIONEWREAD}
2068	*/
2069	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
2070	{
2071	RT_NOREF1(pvUser);
2072	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2073
2074	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2075	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
2076
2077	uint16_t const offReg = off;
2078	uint16_t const offLast = offReg + cb - 1;
2079	if (DMAR_IS_MMIO_OFF_VALID(offLast))
2080	{
2081	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2082	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2083
2084	if (cb == 8)
2085	{
2086	(uint64_t )pv = dmarRegRead64(pThis, offReg);
2087	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
2088	}
2089	else
2090	{
2091	(uint32_t )pv = dmarRegRead32(pThis, offReg);
2092	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
2093	}
2094
2095	DMAR_UNLOCK(pDevIns, pThisCC);
2096	return VINF_SUCCESS;
2097	}
2098
2099	return VINF_IOM_MMIO_UNUSED_FF;
2100	}
2101
2102
2103	#ifdef IN_RING3
2104	/**
2105	* Process requests in the invalidation queue.
2106	*
2107	* @param pDevIns The IOMMU device instance.
2108	* @param pvRequests The requests to process.
2109	* @param cbRequests The size of all requests (in bytes).
2110	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
2111	* VTD_IQA_REG_DW_256_BIT).
2112	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
2113	*/
2114	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
2115	uint8_t fTtm)
2116	{
2117	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
2118	do \
2119	{ \
2120	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
2121	return; \
2122	} while (0)
2123
2124	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2125	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2126
2127	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2128	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
2129
2130	/*
2131	* The below check is redundant since we check both TTM and DW for each
2132	* descriptor type we process. However, the error reported by hardware
2133	* may differ hence this is kept commented out but not removed from the code
2134	* if we need to change this in the future.
2135	*
2136	* In our implementation, we would report the descriptor type as invalid,
2137	* while on real hardware it may report descriptor width as invalid.
2138	* The Intel VT-d spec. is not clear which error takes preceedence.
2139	*/
2140	#if 0
2141	/*
2142	* Verify that 128-bit descriptors are not used when operating in scalable mode.
2143	* We don't check this while software writes IQA_REG but defer it until now because
2144	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
2145	* -IS- performed when software writes IQA_REG since it only requires checking against
2146	* immutable hardware features.
2147	*/
2148	if ( fTtm != VTD_TTM_SCALABLE_MODE
2149	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
2150	{ /* likely */ }
2151	else
2152	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, kIqei_InvalidDescriptorWidth);
2153	#endif
2154
2155	/*
2156	* Process requests in FIFO order.
2157	*/
2158	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
2159	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
2160	{
2161	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
2162	uint64_t const uQword0 = puDscQwords[0];
2163	uint64_t const uQword1 = puDscQwords[1];
2164	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
2165	switch (fDscType)
2166	{
2167	case VTD_INV_WAIT_DSC_TYPE:
2168	{
2169	/* Validate descriptor type. */
2170	if ( fTtm == VTD_TTM_LEGACY_MODE
2171	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
2172	{ /* likely */ }
2173	else
2174	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, kIqei_InvalidDescriptorType);
2175
2176	/* Validate reserved bits. */
2177	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
2178	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
2179	: VTD_INV_WAIT_DSC_0_VALID_MASK;
2180	if ( !(uQword0 & ~fValidMask0)
2181	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
2182	{ /* likely */ }
2183	else
2184	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, kIqei_RsvdFieldViolation);
2185
2186	if (fDw == VTD_IQA_REG_DW_256_BIT)
2187	{
2188	if ( !puDscQwords[2]
2189	&& !puDscQwords[3])
2190	{ /* likely */ }
2191	else
2192	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, kIqei_RsvdFieldViolation);
2193	}
2194
2195	/* Perform status write (this must be done prior to generating the completion interrupt). */
2196	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
2197	if (fSw)
2198	{
2199	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
2200	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
2201	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
2202	AssertRC(rc);
2203	}
2204
2205	/* Generate invalidation event interrupt. */
2206	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
2207	if (fIf)
2208	{
2209	DMAR_LOCK(pDevIns, pThisR3);
2210	dmarR3InvEventRaiseInterrupt(pDevIns);
2211	DMAR_UNLOCK(pDevIns, pThisR3);
2212	}
2213
2214	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
2215	break;
2216	}
2217
2218	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
2219	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
2220	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
2221	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
2222	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
2223	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
2224	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
2225	default:
2226	{
2227	/* Stop processing further requests. */
2228	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
2229	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, kIqei_InvalidDescriptorType);
2230	}
2231	}
2232	}
2233	#undef DMAR_IQE_FAULT_RECORD_RET
2234	}
2235
2236
2237	/**
2238	* The invalidation-queue thread.
2239	*
2240	* @returns VBox status code.
2241	* @param pDevIns The IOMMU device instance.
2242	* @param pThread The command thread.
2243	*/
2244	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2245	{
2246	NOREF(pThread);
2247	LogFlowFunc(("\n"));
2248
2249	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2250	return VINF_SUCCESS;
2251
2252	/*
2253	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
2254	* This prevents trashing the heap as well as deal with out-of-memory situations
2255	* up-front while starting the VM. It also simplifies the code from having to
2256	* dynamically grow/shrink the allocation based on how software sizes the queue.
2257	* Guests normally don't alter the queue size all the time, but that's not an
2258	* assumption we can make.
2259	*/
2260	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
2261	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
2262	void *pvRequests = RTMemAllocZ(cbMaxQs);
2263	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
2264
2265	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2266	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2267
2268	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2269	{
2270	/*
2271	* Sleep until we are woken up.
2272	*/
2273	bool const fSignaled = ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, false);
2274	if (!fSignaled)
2275	{
2276	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
2277	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2278	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2279	break;
2280	ASMAtomicWriteBool(&pThis->fInvQueueThreadSignaled, false);
2281	}
2282
2283	DMAR_LOCK(pDevIns, pThisR3);
2284	if (dmarInvQueueCanProcessRequests(pThis))
2285	{
2286	uint32_t offQueueHead;
2287	uint32_t offQueueTail;
2288	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
2289	if (!fIsEmpty)
2290	{
2291	/*
2292	* Get the current queue size, descriptor width, queue base address and the
2293	* table translation mode while the lock is still held.
2294	*/
2295	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2296	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
2297	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
2298	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2299	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2300	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
2301
2302	/* Paranoia. */
2303	Assert(cbQueue <= cbMaxQs);
2304	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
2305	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
2306	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
2307	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
2308	Assert(offQueueHead < cbQueue);
2309
2310	/*
2311	* A table translation mode of "reserved" isn't valid for any descriptor type.
2312	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
2313	* but if ESRTPS is support, we will perform a global invalidation when software
2314	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
2315	* So caching TTM while reading all descriptors should not be a problem.
2316	*
2317	* Also, validate the queue tail offset as it's mutable by software.
2318	*/
2319	if ( fTtm != VTD_TTM_RSVD
2320	&& offQueueTail < cbQueue)
2321	{
2322	/* Don't hold the lock while reading (a potentially large amount of) requests */
2323	DMAR_UNLOCK(pDevIns, pThisR3);
2324
2325	int rc;
2326	uint32_t cbRequests;
2327	if (offQueueTail > offQueueHead)
2328	{
2329	/* The requests have not wrapped around, read them in one go. */
2330	cbRequests = offQueueTail - offQueueHead;
2331	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
2332	}
2333	else
2334	{
2335	/* The requests have wrapped around, read forward and wrapped-around. */
2336	uint32_t const cbForward = cbQueue - offQueueHead;
2337	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
2338
2339	uint32_t const cbWrapped = offQueueTail;
2340	if ( RT_SUCCESS(rc)
2341	&& cbWrapped > 0)
2342	{
2343	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
2344	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
2345	}
2346	cbRequests = cbForward + cbWrapped;
2347	}
2348
2349	/* Re-acquire the lock since we need to update device state. */
2350	DMAR_LOCK(pDevIns, pThisR3);
2351
2352	if (RT_SUCCESS(rc))
2353	{
2354	/* Indicate to software we've fetched all requests. */
2355	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
2356
2357	/* Don't hold the lock while processing requests. */
2358	DMAR_UNLOCK(pDevIns, pThisR3);
2359
2360	/* Process all requests. */
2361	Assert(cbRequests <= cbQueue);
2362	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
2363
2364	/*
2365	* We've processed all requests and the lock shouldn't be held at this point.
2366	* Using 'continue' here allows us to skip re-acquiring the lock just to release
2367	* it again before going back to the thread loop. It's a bit ugly but it certainly
2368	* helps with performance.
2369	*/
2370	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2371	continue;
2372	}
2373	else
2374	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, kIqei_FetchDescriptorError);
2375	}
2376	else
2377	{
2378	if (fTtm == VTD_TTM_RSVD)
2379	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, kIqei_InvalidTtm);
2380	else
2381	{
2382	Assert(offQueueTail >= cbQueue);
2383	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, kIqei_InvalidTailPointer);
2384	}
2385	}
2386	}
2387	}
2388	DMAR_UNLOCK(pDevIns, pThisR3);
2389	}
2390
2391	RTMemFree(pvRequests);
2392	pvRequests = NULL;
2393
2394	LogFlowFunc(("Invalidation-queue thread terminating\n"));
2395	return VINF_SUCCESS;
2396	}
2397
2398
2399	/**
2400	* Wakes up the invalidation-queue thread so it can respond to a state
2401	* change.
2402	*
2403	* @returns VBox status code.
2404	* @param pDevIns The IOMMU device instance.
2405	* @param pThread The invalidation-queue thread.
2406	*
2407	* @thread EMT.
2408	*/
2409	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2410	{
2411	RT_NOREF(pThread);
2412	LogFlowFunc(("\n"));
2413	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2414	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
2415	}
2416
2417
2418	/**
2419	* @callback_method_impl{FNDBGFHANDLERDEV}
2420	*/
2421	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2422	{
2423	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2424	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2425	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
2426
2427	/*
2428	* We lock the device to get a consistent register state as it is
2429	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
2430	* ones we care about here) into temporaries and release the lock ASAP.
2431	*
2432	* Order of register being read and outputted is in accordance with the
2433	* spec. for no particular reason.
2434	* See Intel VT-d spec. 10.4 "Register Descriptions".
2435	*/
2436	DMAR_LOCK(pDevIns, pThisR3);
2437
2438	DMARDIAG const enmDiag = pThis->enmDiag;
2439	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
2440	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
2441	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
2442	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
2443	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2444	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
2445	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
2446	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
2447	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
2448	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
2449	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
2450	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
2451	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
2452	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
2453	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
2454	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
2455	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
2456	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
2457	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
2458	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
2459	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2460	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
2461	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
2462	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
2463	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
2464	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
2465	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
2466	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
2467	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
2468	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
2469	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
2470	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
2471	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
2472	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
2473	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
2474	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
2475	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
2476	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
2477
2478	DMAR_UNLOCK(pDevIns, pThisR3);
2479
2480	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
2481	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
2482	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
2483
2484	/*
2485	* Non-verbose output.
2486	*/
2487	if (!fVerbose)
2488	{
2489	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2490	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2491	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2492	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2493	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2494	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2495	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2496	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2497	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2498	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2499	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2500	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2501	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2502	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2503	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2504	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2505	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2506	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2507	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2508	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2509	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2510	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2511	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2512	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2513	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2514	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2515	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2516	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2517	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2518	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2519	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2520	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2521	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2522	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2523	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2524	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2525	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2526	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2527	pHlp->pfnPrintf(pHlp, "\n");
2528	return;
2529	}
2530
2531	/*
2532	* Verbose output.
2533	*/
2534	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2535	{
2536	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
2537	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
2538	}
2539	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2540	{
2541	uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
2542	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
2543	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
2544	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
2545	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
2546	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
2547	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
2548	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
2549	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
2550	pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
2551	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
2552	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
2553	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
2554	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
2555	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
2556	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
2557	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
2558	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
2559	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
2560	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
2561	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
2562	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
2563	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
2564	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
2565	}
2566	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2567	{
2568	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
2569	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
2570	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
2571	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
2572	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
2573	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
2574	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
2575	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
2576	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
2577	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
2578	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
2579	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
2580	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
2581	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
2582	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
2583	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
2584	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
2585	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
2586	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
2587	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
2588	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
2589	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
2590	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
2591	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
2592	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
2593	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
2594	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
2595	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
2596	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
2597	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
2598	}
2599	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2600	{
2601	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
2602	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
2603	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
2604	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
2605	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
2606	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
2607	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2608	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2609	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
2610	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
2611	}
2612	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2613	{
2614	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
2615	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
2616	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
2617	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
2618	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
2619	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
2620	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
2621	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
2622	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
2623	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
2624	}
2625	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2626	{
2627	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2628	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
2629	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
2630	}
2631	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2632	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2633	{
2634	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
2635	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
2636	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
2637	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
2638	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
2639	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
2640	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
2641	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
2642	}
2643	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2644	{
2645	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
2646	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
2647	}
2648	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2649	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2650	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2651	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2652	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2653	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2654	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2655	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2656	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2657	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2658	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2659	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2660	{
2661	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2662	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
2663	uint8_t const cQueuePages = 1 << fQs;
2664	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
2665	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
2666	}
2667	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2668	{
2669	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
2670	}
2671	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2672	{
2673	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
2674	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
2675	}
2676	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2677	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2678	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2679	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2680	{
2681	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
2682	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
2683	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
2684	}
2685	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2686	{
2687	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2688	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
2689	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
2690	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
2691	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
2692	}
2693	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2694	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2695	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2696	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2697	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2698	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2699	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2700	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2701	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2702	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2703	pHlp->pfnPrintf(pHlp, "\n");
2704	}
2705
2706
2707	/**
2708	* Initializes all registers in the DMAR unit.
2709	*
2710	* @param pDevIns The IOMMU device instance.
2711	*/
2712	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
2713	{
2714	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2715
2716	/*
2717	* Wipe all registers (required on reset).
2718	*/
2719	RT_ZERO(pThis->abRegs0);
2720	RT_ZERO(pThis->abRegs1);
2721
2722	/*
2723	* Initialize registers not mutable by software prior to initializing other registers.
2724	*/
2725	/* VER_REG */
2726	{
2727	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
2728	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
2729	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
2730	}
2731
2732	uint8_t const fFlts = 1; /* First-Level translation support. */
2733	uint8_t const fSlts = 1; /* Second-Level translation support. */
2734	uint8_t const fPt = 1; /* Pass-Through support. */
2735	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
2736	uint8_t const fNest = 0; /* Nested translation support. */
2737
2738	/* CAP_REG */
2739	{
2740	uint8_t cGstPhysAddrBits;
2741	uint8_t cGstLinearAddrBits;
2742	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
2743
2744	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
2745	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
2746	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
2747	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
2748	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
2749	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
2750	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
2751	: X86_PAGE_2M_SHIFT)
2752	- X86_PAGE_4K_SHIFT;
2753	uint8_t const fNd = 2; /* Number of domains supported (0=16, 1=64, 2=256, 3=1K, 4=4K,
2754	5=16K, 6=64K, 7=Reserved). */
2755	uint8_t const fPsi = 1; /* Page selective invalidation. */
2756	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
2757	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
2758	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
2759	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
2760	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
2761
2762	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
2763	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
2764	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
2765	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
2766	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
2767	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
2768	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
2769	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
2770	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
2771	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
2772	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
2773	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
2774	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
2775	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
2776	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
2777	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
2778	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
2779	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
2780	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
2781	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
2782	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
2783	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
2784	}
2785
2786	/* ECAP_REG */
2787	{
2788	uint8_t const fQi = 1; /* Queued-invalidations. */
2789	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
2790	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
2791	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
2792	uint8_t const fEim = 1; /* Extended interrupt mode.*/
2793	uint8_t const fAdms = 1; /* Abort DMA mode support. */
2794
2795	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
2796	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
2797	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
2798	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
2799	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
2800	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
2801	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
2802	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
2803	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
2804	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
2805	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
2806	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
2807	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
2808	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
2809	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
2810	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
2811	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
2812	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
2813	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
2814	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
2815	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
2816	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
2817	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
2818	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
2819	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
2820	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
2821	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
2822	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
2823	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
2824	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
2825	}
2826
2827	/*
2828	* Initialize registers mutable by software.
2829	*/
2830	/* FECTL_REG */
2831	{
2832	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
2833	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
2834	}
2835
2836	/* ICETL_REG */
2837	{
2838	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
2839	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
2840	}
2841
2842	#ifdef VBOX_STRICT
2843	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
2844	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
2845	#endif
2846	}
2847
2848
2849	/**
2850	* @interface_method_impl{PDMDEVREG,pfnReset}
2851	*/
2852	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
2853	{
2854	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2855	LogFlowFunc(("\n"));
2856
2857	DMAR_LOCK(pDevIns, pThisR3);
2858	dmarR3RegsInit(pDevIns);
2859	DMAR_UNLOCK(pDevIns, pThisR3);
2860	}
2861
2862
2863	/**
2864	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2865	*/
2866	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
2867	{
2868	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2869	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2870	LogFlowFunc(("\n"));
2871
2872	DMAR_LOCK(pDevIns, pThisR3);
2873
2874	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
2875	{
2876	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
2877	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
2878	}
2879
2880	DMAR_UNLOCK(pDevIns, pThisR3);
2881	return VINF_SUCCESS;
2882	}
2883
2884
2885	/**
2886	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2887	*/
2888	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2889	{
2890	RT_NOREF(pCfg);
2891
2892	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2893	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
2894	pThisR3->pDevInsR3 = pDevIns;
2895
2896	LogFlowFunc(("iInstance=%d\n", iInstance));
2897	NOREF(iInstance);
2898
2899	/*
2900	* Register the IOMMU with PDM.
2901	*/
2902	PDMIOMMUREGR3 IommuReg;
2903	RT_ZERO(IommuReg);
2904	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2905	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2906	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2907	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2908	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2909	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
2910	if (RT_FAILURE(rc))
2911	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
2912	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
2913	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2914	N_("IOMMU helper version mismatch; got %#x expected %#x"),
2915	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
2916	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
2917	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2918	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
2919	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
2920	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
2921	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
2922	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
2923	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
2924
2925	/*
2926	* Use PDM's critical section (via helpers) for the IOMMU device.
2927	*/
2928	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2929	AssertRCReturn(rc, rc);
2930
2931	/*
2932	* Initialize PCI configuration registers.
2933	*/
2934	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2935	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2936
2937	/* Header. */
2938	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2939	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2940	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
2941	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
2942	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
2943	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
2944	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2945	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2946
2947	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
2948	PDMPciDevSetStatus(pPciDev, 0);
2949	PDMPciDevSetCapabilityList(pPciDev, 0);
2950
2951	/** @todo VTBAR at 0x180? */
2952
2953	/*
2954	* Register the PCI function with PDM.
2955	*/
2956	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
2957	AssertLogRelRCReturn(rc, rc);
2958
2959	/** @todo Register MSI but what's the MSI capability offset? */
2960	#if 0
2961	/*
2962	* Register MSI support for the PCI device.
2963	* This must be done -after- registering it as a PCI device!
2964	*/
2965	#endif
2966
2967	/*
2968	* Register MMIO region.
2969	*/
2970	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
2971	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
2972	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
2973	&pThis->hMmio);
2974	AssertLogRelRCReturn(rc, rc);
2975
2976	/*
2977	* Register debugger info items.
2978	*/
2979	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
2980	AssertLogRelRCReturn(rc, rc);
2981
2982	#ifdef VBOX_WITH_STATISTICS
2983	/*
2984	* Statistics.
2985	*/
2986	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
2987	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
2988
2989	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
2990	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
2991
2992	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
2993	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
2994	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
2995	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
2996
2997	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
2998	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
2999
3000	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
3001	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
3002
3003	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
3004	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
3005
3006	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
3007	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
3008
3009	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
3010	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
3011	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
3012	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
3013	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
3014	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
3015	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
3016	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
3017	#endif
3018
3019	/*
3020	* Initialize registers.
3021	*/
3022	dmarR3RegsInit(pDevIns);
3023
3024	/*
3025	* Create invalidation-queue thread and semaphore.
3026	*/
3027	char szInvQueueThread[32];
3028	RT_ZERO(szInvQueueThread);
3029	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
3030	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
3031	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
3032	AssertLogRelRCReturn(rc, rc);
3033
3034	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
3035	AssertLogRelRCReturn(rc, rc);
3036
3037	/*
3038	* Log some of the features exposed to software.
3039	*/
3040	uint32_t const uVerReg = pThis->uVerReg;
3041	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
3042	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW));
3043	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
3044	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
3045	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
3046	DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
3047	pThis->fCapReg, pThis->fExtCapReg, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
3048
3049	return VINF_SUCCESS;
3050	}
3051
3052	#else
3053
3054	/**
3055	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
3056	*/
3057	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
3058	{
3059	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3060	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3061	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
3062	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
3063
3064	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
3065	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3066	AssertRCReturn(rc, rc);
3067
3068	/* Set up the MMIO RZ handlers. */
3069	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
3070	AssertRCReturn(rc, rc);
3071
3072	/* Set up the IOMMU RZ callbacks. */
3073	PDMIOMMUREGCC IommuReg;
3074	RT_ZERO(IommuReg);
3075	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3076	IommuReg.idxIommu = pThis->idxIommu;
3077	IommuReg.pfnMemAccess = iommuIntelMemAccess;
3078	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3079	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3080	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3081
3082	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
3083	AssertRCReturn(rc, rc);
3084	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
3085	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3086	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3087	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
3088	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
3089	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
3090	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
3091
3092	return VINF_SUCCESS;
3093	}
3094
3095	#endif
3096
3097
3098	/**
3099	* The device registration structure.
3100	*/
3101	PDMDEVREG const g_DeviceIommuIntel =
3102	{
3103	/* .u32Version = */ PDM_DEVREG_VERSION,
3104	/* .uReserved0 = */ 0,
3105	/* .szName = */ "iommu-intel",
3106	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
3107	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
3108	/* .cMaxInstances = */ 1,
3109	/* .uSharedVersion = */ 42,
3110	/* .cbInstanceShared = */ sizeof(DMAR),
3111	/* .cbInstanceCC = */ sizeof(DMARCC),
3112	/* .cbInstanceRC = */ sizeof(DMARRC),
3113	/* .cMaxPciDevices = */ 1,
3114	/* .cMaxMsixVectors = */ 0,
3115	/* .pszDescription = */ "IOMMU (Intel)",
3116	#if defined(IN_RING3)
3117	/* .pszRCMod = */ "VBoxDDRC.rc",
3118	/* .pszR0Mod = */ "VBoxDDR0.r0",
3119	/* .pfnConstruct = */ iommuIntelR3Construct,
3120	/* .pfnDestruct = */ iommuIntelR3Destruct,
3121	/* .pfnRelocate = */ NULL,
3122	/* .pfnMemSetup = */ NULL,
3123	/* .pfnPowerOn = */ NULL,
3124	/* .pfnReset = */ iommuIntelR3Reset,
3125	/* .pfnSuspend = */ NULL,
3126	/* .pfnResume = */ NULL,
3127	/* .pfnAttach = */ NULL,
3128	/* .pfnDetach = */ NULL,
3129	/* .pfnQueryInterface = */ NULL,
3130	/* .pfnInitComplete = */ NULL,
3131	/* .pfnPowerOff = */ NULL,
3132	/* .pfnSoftReset = */ NULL,
3133	/* .pfnReserved0 = */ NULL,
3134	/* .pfnReserved1 = */ NULL,
3135	/* .pfnReserved2 = */ NULL,
3136	/* .pfnReserved3 = */ NULL,
3137	/* .pfnReserved4 = */ NULL,
3138	/* .pfnReserved5 = */ NULL,
3139	/* .pfnReserved6 = */ NULL,
3140	/* .pfnReserved7 = */ NULL,
3141	#elif defined(IN_RING0)
3142	/* .pfnEarlyConstruct = */ NULL,
3143	/* .pfnConstruct = */ iommuIntelRZConstruct,
3144	/* .pfnDestruct = */ NULL,
3145	/* .pfnFinalDestruct = */ NULL,
3146	/* .pfnRequest = */ NULL,
3147	/* .pfnReserved0 = */ NULL,
3148	/* .pfnReserved1 = */ NULL,
3149	/* .pfnReserved2 = */ NULL,
3150	/* .pfnReserved3 = */ NULL,
3151	/* .pfnReserved4 = */ NULL,
3152	/* .pfnReserved5 = */ NULL,
3153	/* .pfnReserved6 = */ NULL,
3154	/* .pfnReserved7 = */ NULL,
3155	#elif defined(IN_RC)
3156	/* .pfnConstruct = */ iommuIntelRZConstruct,
3157	/* .pfnReserved0 = */ NULL,
3158	/* .pfnReserved1 = */ NULL,
3159	/* .pfnReserved2 = */ NULL,
3160	/* .pfnReserved3 = */ NULL,
3161	/* .pfnReserved4 = */ NULL,
3162	/* .pfnReserved5 = */ NULL,
3163	/* .pfnReserved6 = */ NULL,
3164	/* .pfnReserved7 = */ NULL,
3165	#else
3166	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
3167	#endif
3168	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
3169	};
3170
3171	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
3172

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89123

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