DevIommuAmd.cpp@ 84509

最後變更在這個檔案從84509是 84432,由 vboxsync 提交於 5 年前
AMD IOMMU: bugref:9654 Interrupt remapping bits.
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1	/* $Id: DevIommuAmd.cpp 84432 2020-05-21 13:04:54Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/AssertGuest.h>
26
27	#include "VBoxDD.h"
28	#include <iprt/x86.h>
29	#include <iprt/string.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/**
446	* @name IOMMU Control Register Bits.
447	* In accordance with the AMD spec.
448	* @{
449	*/
450	/** IommuEn: Enable the IOMMU. */
451	#define IOMMU_CTRL_IOMMU_EN RT_BIT_64(0)
452	/** HtTunEn: HyperTransport tunnel translation enable. */
453	#define IOMMU_CTRL_HT_TUNNEL_EN RT_BIT_64(1)
454	/** EventLogEn: Event log enable. */
455	#define IOMMU_CTRL_EVT_LOG_EN RT_BIT_64(2)
456	/** EventIntEn: Event interrupt enable. */
457	#define IOMMU_CTRL_EVT_INTR_EN RT_BIT_64(3)
458	/** ComWaitIntEn: Completion wait interrupt enable. */
459	#define IOMMU_CTRL_COMPLETION_WAIT_INTR_EN RT_BIT_64(4)
460	/** InvTimeout: Invalidation timeout. */
461	#define IOMMU_CTRL_INV_TIMEOUT RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7)
462	/** @todo IOMMU: the rest or remove it. */
463	/** @} */
464
465	/** @name Miscellaneous IOMMU defines.
466	* @{ */
467	/** Log prefix string. */
468	#define IOMMU_LOG_PFX "AMD_IOMMU"
469	/** The current saved state version. */
470	#define IOMMU_SAVED_STATE_VERSION 1
471	/** AMD's vendor ID. */
472	#define IOMMU_PCI_VENDOR_ID 0x1022
473	/** VirtualBox IOMMU device ID. */
474	#define IOMMU_PCI_DEVICE_ID 0xc0de
475	/** VirtualBox IOMMU device revision ID. */
476	#define IOMMU_PCI_REVISION_ID 0x01
477	/** Size of the MMIO region in bytes. */
478	#define IOMMU_MMIO_REGION_SIZE _16K
479	/** Number of device table segments supported (power of 2). */
480	#define IOMMU_MAX_DEV_TAB_SEGMENTS 3
481	/** Maximum host address translation level supported (inclusive). */
482	#define IOMMU_MAX_HOST_PT_LEVEL 6
483	/** The IOTLB entry magic. */
484	#define IOMMU_IOTLBE_MAGIC 0x10acce55
485	/** The device-specific feature major revision. */
486	#define IOMMU_DEVSPEC_FEAT_MAJOR_VERSION 0x1
487	/** The device-specific feature minor revision. */
488	#define IOMMU_DEVSPEC_FEAT_MINOR_VERSION 0x0
489	/** The device-specific control major revision. */
490	#define IOMMU_DEVSPEC_CTRL_MAJOR_VERSION 0x1
491	/** The device-specific control minor revision. */
492	#define IOMMU_DEVSPEC_CTRL_MINOR_VERSION 0x0
493	/** The device-specific status major revision. */
494	#define IOMMU_DEVSPEC_STATUS_MAJOR_VERSION 0x1
495	/** The device-specific status minor revision. */
496	#define IOMMU_DEVSPEC_STATUS_MINOR_VERSION 0x0
497	/** @} */
498
499	/**
500	* Acquires the IOMMU PDM lock.
501	* This will make a long jump to ring-3 to acquire the lock if necessary.
502	*/
503	#define IOMMU_LOCK(a_pDevIns) \
504	do { \
505	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
506	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
507	{ /* likely */ } \
508	else \
509	return rcLock; \
510	} while (0)
511
512	/**
513	* Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
514	* This will make a long jump to ring-3 to acquire the lock if necessary.
515	*/
516	#define IOMMU_LOCK_NORET(a_pDevIns) \
517	do { \
518	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
519	AssertRC(rcLock); \
520	} while (0)
521
522	/**
523	* Releases the IOMMU PDM lock.
524	*/
525	#define IOMMU_UNLOCK(a_pDevIns) \
526	do { \
527	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
528	} while (0)
529
530	/**
531	* Asserts that the critsect is owned by this thread.
532	*/
533	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
534	do { \
535	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
536	} while (0)
537
538	/**
539	* Asserts that the critsect is not owned by this thread.
540	*/
541	#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
542	do { \
543	Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
544	} while (0)
545
546	/**
547	* Gets the device table size given the size field.
548	*/
549	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
550
551
552	/*********************************************************************************************************************************
553	* Structures and Typedefs *
554	*********************************************************************************************************************************/
555	/**
556	* The Device ID.
557	* In accordance with VirtualBox's PCI configuration.
558	*/
559	typedef union
560	{
561	struct
562	{
563	uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
564	uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
565	uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
566	} n;
567	/** The unsigned integer view. */
568	uint16_t u;
569	} DEVICE_ID_T;
570	AssertCompileSize(DEVICE_ID_T, 2);
571
572	/**
573	* Device Table Entry (DTE).
574	* In accordance with the AMD spec.
575	*/
576	typedef union
577	{
578	struct
579	{
580	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
581	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
582	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
583	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
584	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
585	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
586	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
587	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
588	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
589	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
590	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
591	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
592	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
593	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
594	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
595	RT_GCC_EXTENSION uint64_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
596	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
597	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
598	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
599	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
600	RT_GCC_EXTENSION uint64_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
601	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
602	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
603	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
604	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
605	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
606	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
607	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
608	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
609	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
610	RT_GCC_EXTENSION uint64_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
611	RT_GCC_EXTENSION uint64_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
612	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
613	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
614	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
615	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
616	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
617	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
618	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
619	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
620	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
621	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
622	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
623	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
624	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
625	} n;
626	/** The 32-bit unsigned integer view. */
627	uint32_t au32[8];
628	/** The 64-bit unsigned integer view. */
629	uint64_t au64[4];
630	} DTE_T;
631	AssertCompileSize(DTE_T, 32);
632	/** Pointer to a device table entry. */
633	typedef DTE_T *PDTE_T;
634	/** Pointer to a const device table entry. */
635	typedef DTE_T const *PCDTE_T;
636
637	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
638	* Support) feature (bits 52:53). */
639	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
640
641	/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
642	* bits 80:95). */
643	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
644	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
645
646	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
647	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
648
649	/* Mask of valid DTE feature bits. */
650	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
651	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
652	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
653	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
654
655	/* Mask of all valid DTE bits (including all feature bits). */
656	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
657	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
658	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xf70fffffffffffff)
659	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
660
661	/**
662	* I/O Page Translation Entry.
663	* In accordance with the AMD spec.
664	*/
665	typedef union
666	{
667	struct
668	{
669	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
670	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
671	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
672	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
673	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
674	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
675	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
676	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
677	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
678	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
679	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
680	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
681	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
682	} n;
683	/** The 64-bit unsigned integer view. */
684	uint64_t u64;
685	} IOPTE_T;
686	AssertCompileSize(IOPTE_T, 8);
687
688	/**
689	* I/O Page Directory Entry.
690	* In accordance with the AMD spec.
691	*/
692	typedef union
693	{
694	struct
695	{
696	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
697	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
698	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
699	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
700	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
701	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
702	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
703	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
704	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
705	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
706	} n;
707	/** The 64-bit unsigned integer view. */
708	uint64_t u64;
709	} IOPDE_T;
710	AssertCompileSize(IOPDE_T, 8);
711
712	/**
713	* I/O Page Table Entity.
714	* In accordance with the AMD spec.
715	*
716	* This a common subset of an DTE.au64[0], PTE and PDE.
717	* Named as an "entity" to avoid confusing it with PTE.
718	*/
719	typedef union
720	{
721	struct
722	{
723	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
724	RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /*< Bits 8:1 - Ignored. /
725	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Mode / Next Level: Next page translation level. /
726	RT_GCC_EXTENSION uint64_t u40Addr : 40; /*< Bits 51:12 - Page address. /
727	RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /*< Bits 60:52 - Ignored. /
728	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
729	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
730	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
731	} n;
732	/** The 64-bit unsigned integer view. */
733	uint64_t u64;
734	} IOPTENTITY_T;
735	AssertCompileSize(IOPTENTITY_T, 8);
736	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
737	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
738	/** Pointer to an IOPT_ENTITY_T struct. */
739	typedef IOPTENTITY_T *PIOPTENTITY_T;
740	/** Pointer to a const IOPT_ENTITY_T struct. */
741	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
742	/** Mask of the address field. */
743	#define IOMMU_PTENTITY_ADDR_MASK UINT64_C(0x000ffffffffff000)
744
745	/**
746	* Interrupt Remapping Table Entry (IRTE).
747	* In accordance with the AMD spec.
748	*/
749	typedef union
750	{
751	struct
752	{
753	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
754	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
755	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
756	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
757	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
758	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
759	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
760	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
761	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
762	} n;
763	/** The 32-bit unsigned integer view. */
764	uint32_t u32;
765	} IRTE_T;
766	AssertCompileSize(IRTE_T, 4);
767	/** Pointer to an IRTE_T struct. */
768	typedef IRTE_T *PIRTE_T;
769	/** Pointer to a const IRTE_T struct. */
770	typedef IRTE_T const *PCIRTE_T;
771
772	/**
773	* Command: Generic Command Buffer Entry.
774	* In accordance with the AMD spec.
775	*/
776	typedef union
777	{
778	struct
779	{
780	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
781	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
782	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
783	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
784	} n;
785	/** The 64-bit unsigned integer view. */
786	uint64_t au64[2];
787	} CMD_GENERIC_T;
788	AssertCompileSize(CMD_GENERIC_T, 16);
789	/** Pointer to a generic command buffer entry. */
790	typedef CMD_GENERIC_T *PCMD_GENERIC_T;
791	/** Pointer to a const generic command buffer entry. */
792	typedef CMD_GENERIC_T const *PCCMD_GENERIC_T;
793
794	/** Number of bits to shift the byte offset of a command in the command buffer to
795	* get its index. */
796	#define IOMMU_CMD_GENERIC_SHIFT 4
797
798	/**
799	* Command: COMPLETION_WAIT.
800	* In accordance with the AMD spec.
801	*/
802	typedef union
803	{
804	struct
805	{
806	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
807	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
808	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
809	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
810	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
811	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
812	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
813	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
814	} n;
815	/** The 64-bit unsigned integer view. */
816	uint64_t au64[2];
817	} CMD_COMWAIT_T;
818	AssertCompileSize(CMD_COMWAIT_T, 16);
819	/** Pointer to a completion wait command. */
820	typedef CMD_COMWAIT_T *PCMD_COMWAIT_T;
821	/** Pointer to a const completion wait command. */
822	typedef CMD_COMWAIT_T const *PCCMD_COMWAIT_T;
823	#define IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK UINT64_C(0xf00fffffffffffff)
824
825	/**
826	* Command: INVALIDATE_DEVTAB_ENTRY.
827	* In accordance with the AMD spec.
828	*/
829	typedef union
830	{
831	struct
832	{
833	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
834	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
835	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
836	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
837	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
838	} n;
839	/** The 64-bit unsigned integer view. */
840	uint64_t au64[2];
841	} CMD_INV_DTE_T;
842	AssertCompileSize(CMD_INV_DTE_T, 16);
843
844	/**
845	* Command: INVALIDATE_IOMMU_PAGES.
846	* In accordance with the AMD spec.
847	*/
848	typedef union
849	{
850	struct
851	{
852	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
853	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
854	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
855	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
856	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
857	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
858	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
859	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
860	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
861	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
862	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
863	} n;
864	/** The 64-bit unsigned integer view. */
865	uint64_t au64[2];
866	} CMD_INV_IOMMU_PAGES_T;
867	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
868
869	/**
870	* Command: INVALIDATE_IOTLB_PAGES.
871	* In accordance with the AMD spec.
872	*/
873	typedef union
874	{
875	struct
876	{
877	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
878	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
879	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
880	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
881	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
882	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
883	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
884	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
885	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
886	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
887	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
888	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
889	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
890	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
891	} n;
892	/** The 64-bit unsigned integer view. */
893	uint64_t au64[2];
894	} CMD_INV_IOTLB_PAGES_T;
895	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
896
897	/**
898	* Command: INVALIDATE_INTR_TABLE.
899	* In accordance with the AMD spec.
900	*/
901	typedef union
902	{
903	struct
904	{
905	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
906	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
907	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
908	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
909	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
910	} u;
911	/** The 64-bit unsigned integer view. */
912	uint64_t au64[2];
913	} CMD_INV_INTR_TABLE_T;
914	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
915
916	/**
917	* Command: COMPLETE_PPR_REQ.
918	* In accordance with the AMD spec.
919	*/
920	typedef union
921	{
922	struct
923	{
924	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
925	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
926	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
927	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
928	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
929	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
930	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
931	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
932	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
933	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
934	} n;
935	/** The 64-bit unsigned integer view. */
936	uint64_t au64[2];
937	} CMD_COMPLETE_PPR_REQ_T;
938	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
939
940	/**
941	* Command: INV_IOMMU_ALL.
942	* In accordance with the AMD spec.
943	*/
944	typedef union
945	{
946	struct
947	{
948	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
949	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
950	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
951	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
952	} n;
953	/** The 64-bit unsigned integer view. */
954	uint64_t au64[2];
955	} CMD_IOMMU_ALL_T;
956	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
957
958	/**
959	* Event Log Entry: Generic.
960	* In accordance with the AMD spec.
961	*/
962	typedef union
963	{
964	struct
965	{
966	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
967	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
968	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
969	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
970	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
971	} n;
972	/** The 32-bit unsigned integer view. */
973	uint32_t au32[4];
974	} EVT_GENERIC_T;
975	AssertCompileSize(EVT_GENERIC_T, 16);
976	/** Number of bits to shift the byte offset of an event entry in the event log
977	* buffer to get its index. */
978	#define IOMMU_EVT_GENERIC_SHIFT 4
979	/** Pointer to a generic event log entry. */
980	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
981	/** Pointer to a const generic event log entry. */
982	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
983
984	/**
985	* Hardware event types.
986	* In accordance with the AMD spec.
987	*/
988	typedef enum HWEVTTYPE
989	{
990	HWEVTTYPE_RSVD = 0,
991	HWEVTTYPE_MASTER_ABORT,
992	HWEVTTYPE_TARGET_ABORT,
993	HWEVTTYPE_DATA_ERROR
994	} HWEVTTYPE;
995	AssertCompileSize(HWEVTTYPE, 4);
996
997	/**
998	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
999	* In accordance with the AMD spec.
1000	*/
1001	typedef union
1002	{
1003	struct
1004	{
1005	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1006	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1007	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
1008	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1009	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1010	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1011	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1012	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1013	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1014	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
1015	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1016	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1017	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
1018	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1019	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1020	} n;
1021	/** The 32-bit unsigned integer view. */
1022	uint32_t au32[4];
1023	/** The 64-bit unsigned integer view. */
1024	uint64_t au64[2];
1025	} EVT_ILLEGAL_DTE_T;
1026	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
1027	/** Pointer to an illegal device table entry event. */
1028	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
1029	/** Pointer to a const illegal device table entry event. */
1030	typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
1031
1032	/**
1033	* Event Log Entry: IO_PAGE_FAULT_EVENT.
1034	* In accordance with the AMD spec.
1035	*/
1036	typedef union
1037	{
1038	struct
1039	{
1040	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1041	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1042	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1043	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1044	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
1045	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
1046	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1047	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
1048	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1049	uint16_t u1PermDenied : 1; /*< Bit 54 - PE: Permission Indicator. /
1050	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1051	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1052	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
1053	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1054	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1055	} n;
1056	/** The 32-bit unsigned integer view. */
1057	uint32_t au32[4];
1058	/** The 64-bit unsigned integer view. */
1059	uint64_t au64[2];
1060	} EVT_IO_PAGE_FAULT_T;
1061	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1062	/** Pointer to an I/O page fault event. */
1063	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1064	/** Pointer to a const I/O page fault event. */
1065	typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
1066
1067
1068	/**
1069	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1070	* In accordance with the AMD spec.
1071	*/
1072	typedef union
1073	{
1074	struct
1075	{
1076	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1077	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1078	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
1079	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
1080	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1081	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
1082	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
1083	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
1084	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1085	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1086	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1087	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1088	} n;
1089	/** The 32-bit unsigned integer view. */
1090	uint32_t au32[4];
1091	/** The 64-bit unsigned integer view. */
1092	uint64_t au64[2];
1093	} EVT_DEV_TAB_HW_ERROR_T;
1094	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1095	/** Pointer to a device table hardware error event. */
1096	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1097	/** Pointer to a const device table hardware error event. */
1098	typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1099
1100	/**
1101	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1102	* In accordance with the AMD spec.
1103	*/
1104	typedef union
1105	{
1106	struct
1107	{
1108	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1109	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1110	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1111	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1112	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1113	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1114	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1115	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1116	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1117	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1118	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1119	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1120	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1121	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1122	* table 58 mentions Addr[31:4], we just use the full 64-bits. Looks like a
1123	* typo in the figure.See AMD AMD IOMMU spec (3.05-PUB, Jan 2020). */
1124	uint64_t u64Addr; /** Bits 127:64 - Address: SPA of the page table entry. */
1125	} n;
1126	/** The 32-bit unsigned integer view. */
1127	uint32_t au32[4];
1128	/** The 64-bit unsigned integer view. */
1129	uint64_t au64[2];
1130	} EVT_PAGE_TAB_HW_ERR_T;
1131	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1132	/** Pointer to a page table hardware error event. */
1133	typedef EVT_PAGE_TAB_HW_ERR_T *PEVT_PAGE_TAB_HW_ERR_T;
1134	/** Pointer to a const page table hardware error event. */
1135	typedef EVT_PAGE_TAB_HW_ERR_T const *PCEVT_PAGE_TAB_HW_ERR_T;
1136
1137	/**
1138	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1139	* In accordance with the AMD spec.
1140	*/
1141	typedef union
1142	{
1143	struct
1144	{
1145	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1146	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1147	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1148	uint64_t u64Addr; /*< Bits 127:64 - Address: SPA of the invalid command. /
1149	} n;
1150	/** The 32-bit unsigned integer view. */
1151	uint32_t au32[4];
1152	/** The 64-bit unsigned integer view. */
1153	uint64_t au64[2];
1154	} EVT_ILLEGAL_CMD_ERR_T;
1155	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1156	/** Pointer to an illegal command error event. */
1157	typedef EVT_ILLEGAL_CMD_ERR_T *PEVT_ILLEGAL_CMD_ERR_T;
1158	/** Pointer to a const illegal command error event. */
1159	typedef EVT_ILLEGAL_CMD_ERR_T const *PCEVT_ILLEGAL_CMD_ERR_T;
1160
1161	/**
1162	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1163	* In accordance with the AMD spec.
1164	*/
1165	typedef union
1166	{
1167	struct
1168	{
1169	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1170	uint32_t u25Rsvd1 : 25; /*< Bits 56:32 - Reserved. /
1171	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1172	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1173	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1174	uint64_t u64Addr; /*< Bits 128:64 - Address: SPA of the attempted access. /
1175	} n;
1176	/** The 32-bit unsigned integer view. */
1177	uint32_t au32[4];
1178	/** The 64-bit unsigned integer view. */
1179	uint64_t au64[2];
1180	} EVT_CMD_HW_ERR_T;
1181	AssertCompileSize(EVT_CMD_HW_ERR_T, 16);
1182	/** Pointer to a command hardware error event. */
1183	typedef EVT_CMD_HW_ERR_T *PEVT_CMD_HW_ERR_T;
1184	/** Pointer to a const command hardware error event. */
1185	typedef EVT_CMD_HW_ERR_T const *PCEVT_CMD_HW_ERR_T;
1186
1187	/**
1188	* Event Log Entry: IOTLB_INV_TIMEOUT.
1189	* In accordance with the AMD spec.
1190	*/
1191	typedef union
1192	{
1193	struct
1194	{
1195	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1196	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1197	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1198	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1199	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1200	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1201	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1202	} n;
1203	/** The 32-bit unsigned integer view. */
1204	uint32_t au32[4];
1205	} EVT_IOTLB_INV_TIMEOUT_T;
1206	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1207
1208	/**
1209	* Event Log Entry: INVALID_DEVICE_REQUEST.
1210	* In accordance with the AMD spec.
1211	*/
1212	typedef union
1213	{
1214	struct
1215	{
1216	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1217	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1218	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1219	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1220	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1221	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1222	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1223	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1224	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1225	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1226	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1227	} n;
1228	/** The 32-bit unsigned integer view. */
1229	uint32_t au32[4];
1230	} EVT_INVALID_DEV_REQ_T;
1231	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1232
1233	/**
1234	* Event Log Entry: EVENT_COUNTER_ZERO.
1235	* In accordance with the AMD spec.
1236	*/
1237	typedef union
1238	{
1239	struct
1240	{
1241	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1242	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1243	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1244	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1245	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1246	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1247	} n;
1248	/** The 32-bit unsigned integer view. */
1249	uint32_t au32[4];
1250	} EVT_EVENT_COUNTER_ZERO_T;
1251	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1252
1253	/**
1254	* IOMMU Capability Header (PCI).
1255	* In accordance with the AMD spec.
1256	*/
1257	typedef union
1258	{
1259	struct
1260	{
1261	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1262	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1263	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1264	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1265	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1266	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1267	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1268	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1269	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1270	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1271	} n;
1272	/** The 32-bit unsigned integer view. */
1273	uint32_t u32;
1274	} IOMMU_CAP_HDR_T;
1275	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1276
1277	/**
1278	* IOMMU Base Address (Lo and Hi) Register (PCI).
1279	* In accordance with the AMD spec.
1280	*/
1281	typedef union
1282	{
1283	struct
1284	{
1285	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1286	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1287	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1288	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1289	} n;
1290	/** The 32-bit unsigned integer view. */
1291	uint32_t au32[2];
1292	/** The 64-bit unsigned integer view. */
1293	uint64_t u64;
1294	} IOMMU_BAR_T;
1295	AssertCompileSize(IOMMU_BAR_T, 8);
1296	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1297
1298	/**
1299	* IOMMU Range Register (PCI).
1300	* In accordance with the AMD spec.
1301	*/
1302	typedef union
1303	{
1304	struct
1305	{
1306	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1307	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1308	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1309	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1310	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1311	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1312	} n;
1313	/** The 32-bit unsigned integer view. */
1314	uint32_t u32;
1315	} IOMMU_RANGE_T;
1316	AssertCompileSize(IOMMU_RANGE_T, 4);
1317
1318	/**
1319	* Device Table Base Address Register (MMIO).
1320	* In accordance with the AMD spec.
1321	*/
1322	typedef union
1323	{
1324	struct
1325	{
1326	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1327	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1328	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1329	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1330	} n;
1331	/** The 64-bit unsigned integer view. */
1332	uint64_t u64;
1333	} DEV_TAB_BAR_T;
1334	AssertCompileSize(DEV_TAB_BAR_T, 8);
1335	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1336	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1337
1338	/**
1339	* Command Buffer Base Address Register (MMIO).
1340	* In accordance with the AMD spec.
1341	*/
1342	typedef union
1343	{
1344	struct
1345	{
1346	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1347	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1348	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1349	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1350	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1351	} n;
1352	/** The 64-bit unsigned integer view. */
1353	uint64_t u64;
1354	} CMD_BUF_BAR_T;
1355	AssertCompileSize(CMD_BUF_BAR_T, 8);
1356	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1357
1358	/**
1359	* Event Log Base Address Register (MMIO).
1360	* In accordance with the AMD spec.
1361	*/
1362	typedef union
1363	{
1364	struct
1365	{
1366	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1367	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1368	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1369	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1370	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1371	} n;
1372	/** The 64-bit unsigned integer view. */
1373	uint64_t u64;
1374	} EVT_LOG_BAR_T;
1375	AssertCompileSize(EVT_LOG_BAR_T, 8);
1376	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1377
1378	/**
1379	* IOMMU Control Register (MMIO).
1380	* In accordance with the AMD spec.
1381	*/
1382	typedef union
1383	{
1384	struct
1385	{
1386	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1387	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1388	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1389	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1390	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1391	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1392	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1393	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1394	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1395	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1396	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1397	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1398	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1399	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1400	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1401	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1402	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1403	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1404	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1405	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1406	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1407	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1408	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1409	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1410	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1411	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1412	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1413	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1414	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1415	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1416	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1417	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1418	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1419	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1420	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1421	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1422	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1423	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1424	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1425	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1426	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1427	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1428	} n;
1429	/** The 64-bit unsigned integer view. */
1430	uint64_t u64;
1431	} IOMMU_CTRL_T;
1432	AssertCompileSize(IOMMU_CTRL_T, 8);
1433	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1434	#define IOMMU_CTRL_CMD_BUF_EN_MASK UINT64_C(0x0000000000001001)
1435
1436	/**
1437	* IOMMU Exclusion Base Register (MMIO).
1438	* In accordance with the AMD spec.
1439	*/
1440	typedef union
1441	{
1442	struct
1443	{
1444	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1445	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1446	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1447	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1448	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1449	} n;
1450	/** The 64-bit unsigned integer view. */
1451	uint64_t u64;
1452	} IOMMU_EXCL_RANGE_BAR_T;
1453	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1454	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1455
1456	/**
1457	* IOMMU Exclusion Range Limit Register (MMIO).
1458	* In accordance with the AMD spec.
1459	*/
1460	typedef union
1461	{
1462	struct
1463	{
1464	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1465	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1466	} n;
1467	/** The 64-bit unsigned integer view. */
1468	uint64_t u64;
1469	} IOMMU_EXCL_RANGE_LIMIT_T;
1470	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1471	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1472
1473	/**
1474	* IOMMU Extended Feature Register (MMIO).
1475	* In accordance with the AMD spec.
1476	*/
1477	typedef union
1478	{
1479	struct
1480	{
1481	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1482	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1483	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1484	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1485	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1486	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1487	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1488	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1489	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1490	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1491	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1492	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1493	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1494	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1495	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1496	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1497	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1498	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1499	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1500	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1501	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1502	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1503	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1504	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1505	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1506	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1507	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1508	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1509	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1510	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1511	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1512	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1513	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1514	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1515	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1516	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1517	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1518	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1519	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1520	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1521	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1522	} n;
1523	/** The 64-bit unsigned integer view. */
1524	uint64_t u64;
1525	} IOMMU_EXT_FEAT_T;
1526	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1527
1528	/**
1529	* Peripheral Page Request Log Base Address Register (MMIO).
1530	* In accordance with the AMD spec.
1531	*/
1532	typedef union
1533	{
1534	struct
1535	{
1536	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1537	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1538	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1539	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1540	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1541	} n;
1542	/** The 64-bit unsigned integer view. */
1543	uint64_t u64;
1544	} PPR_LOG_BAR_T;
1545	AssertCompileSize(PPR_LOG_BAR_T, 8);
1546	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1547
1548	/**
1549	* IOMMU Hardware Event Upper Register (MMIO).
1550	* In accordance with the AMD spec.
1551	*/
1552	typedef union
1553	{
1554	struct
1555	{
1556	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1557	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1558	} n;
1559	/** The 64-bit unsigned integer view. */
1560	uint64_t u64;
1561	} IOMMU_HW_EVT_HI_T;
1562	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1563
1564	/**
1565	* IOMMU Hardware Event Lower Register (MMIO).
1566	* In accordance with the AMD spec.
1567	*/
1568	typedef uint64_t IOMMU_HW_EVT_LO_T;
1569
1570	/**
1571	* IOMMU Hardware Event Status (MMIO).
1572	* In accordance with the AMD spec.
1573	*/
1574	typedef union
1575	{
1576	struct
1577	{
1578	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1579	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1580	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1581	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1582	} n;
1583	/** The 64-bit unsigned integer view. */
1584	uint64_t u64;
1585	} IOMMU_HW_EVT_STATUS_T;
1586	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1587	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1588
1589	/**
1590	* Guest Virtual-APIC Log Base Address Register (MMIO).
1591	* In accordance with the AMD spec.
1592	*/
1593	typedef union
1594	{
1595	struct
1596	{
1597	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1598	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1599	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1600	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1601	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1602	} n;
1603	/** The 64-bit unsigned integer view. */
1604	uint64_t u64;
1605	} GALOG_BAR_T;
1606	AssertCompileSize(GALOG_BAR_T, 8);
1607
1608	/**
1609	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1610	* In accordance with the AMD spec.
1611	*/
1612	typedef union
1613	{
1614	struct
1615	{
1616	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1617	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1618	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1619	} n;
1620	/** The 64-bit unsigned integer view. */
1621	uint64_t u64;
1622	} GALOG_TAIL_ADDR_T;
1623	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1624
1625	/**
1626	* PPR Log B Base Address Register (MMIO).
1627	* In accordance with the AMD spec.
1628	* Currently identical to PPR_LOG_BAR_T.
1629	*/
1630	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1631
1632	/**
1633	* Event Log B Base Address Register (MMIO).
1634	* In accordance with the AMD spec.
1635	* Currently identical to EVT_LOG_BAR_T.
1636	*/
1637	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1638
1639	/**
1640	* Device-specific Feature Extension (DSFX) Register (MMIO).
1641	* In accordance with the AMD spec.
1642	*/
1643	typedef union
1644	{
1645	struct
1646	{
1647	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1648	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1649	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1650	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1651	} n;
1652	/** The 64-bit unsigned integer view. */
1653	uint64_t u64;
1654	} DEV_SPECIFIC_FEAT_T;
1655	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1656
1657	/**
1658	* Device-specific Control Extension (DSCX) Register (MMIO).
1659	* In accordance with the AMD spec.
1660	*/
1661	typedef union
1662	{
1663	struct
1664	{
1665	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1666	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1667	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1668	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1669	} n;
1670	/** The 64-bit unsigned integer view. */
1671	uint64_t u64;
1672	} DEV_SPECIFIC_CTRL_T;
1673	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1674
1675	/**
1676	* Device-specific Status Extension (DSSX) Register (MMIO).
1677	* In accordance with the AMD spec.
1678	*/
1679	typedef union
1680	{
1681	struct
1682	{
1683	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1684	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1685	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1686	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1687	} n;
1688	/** The 64-bit unsigned integer view. */
1689	uint64_t u64;
1690	} DEV_SPECIFIC_STATUS_T;
1691	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1692
1693	/**
1694	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1695	* In accordance with the AMD spec.
1696	*/
1697	typedef union
1698	{
1699	struct
1700	{
1701	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1702	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1703	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1704	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1705	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1706	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1707	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1708	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1709	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1710	} n;
1711	/** The 32-bit unsigned integer view. */
1712	uint32_t au32[2];
1713	/** The 64-bit unsigned integer view. */
1714	uint64_t u64;
1715	} MSI_MISC_INFO_T;
1716	AssertCompileSize(MSI_MISC_INFO_T, 8);
1717	/** MSI Vector Register 0 and 1 (MMIO). */
1718	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1719
1720	/**
1721	* MSI Capability Header Register (PCI + MMIO).
1722	* In accordance with the AMD spec.
1723	*/
1724	typedef union
1725	{
1726	struct
1727	{
1728	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1729	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1730	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1731	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1732	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1733	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1734	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1735	} n;
1736	/** The 32-bit unsigned integer view. */
1737	uint32_t u32;
1738	} MSI_CAP_HDR_T;
1739	AssertCompileSize(MSI_CAP_HDR_T, 4);
1740	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1741
1742	/**
1743	* MSI Address Register (PCI + MMIO).
1744	* In accordance to the Intel spec.
1745	* See Intel spec. 10.11.1 "Message Address Register Format".
1746	*
1747	* This also conforms to the AMD IOMMU spec. which omits specifying individual
1748	* fields but specifies reserved bits.
1749	*/
1750	typedef union
1751	{
1752	struct
1753	{
1754	uint32_t u2Ign0 : 2; /*< Bits 1:0 - Ignored (read as 0, writes ignored). /
1755	uint32_t u1DestMode : 1; /*< Bit 2 - DM: Destination Mode. /
1756	uint32_t u1RedirHint : 1; /*< Bit 3 - RH: Redirection Hint. /
1757	uint32_t u8Rsvd0 : 8; /*< Bits 11:4 - Reserved. /
1758	uint32_t u8DestId : 8; /*< Bits 19:12 - Destination Id. /
1759	uint32_t u12Addr : 12; /*< Bits 31:20 - Address. /
1760	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1761	} n;
1762	/** The 32-bit unsigned integer view. */
1763	uint32_t au32[2];
1764	/** The 64-bit unsigned integer view. */
1765	uint64_t u64;
1766	} MSI_ADDR_T;
1767	AssertCompileSize(MSI_ADDR_T, 8);
1768	/** According to the AMD IOMMU spec. the top 32-bits are not reserved. From a
1769	* PCI/IOMMU standpoint this makes sense. However, when dealing with the CPU side
1770	* of things we might want to ensure the upper bits are reserved. Does x86/x64
1771	* really support a 64-bit MSI address? */
1772	#define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
1773	/** Pointer to an MSI address register. */
1774	typedef MSI_ADDR_T *PMSI_ADDR_T;
1775	/** Pointer to a const MSI address register. */
1776	typedef MSI_ADDR_T const *PCMSI_ADDR_T;
1777
1778	/**
1779	* MSI Data Register (PCI + MMIO).
1780	* In accordance to the Intel spec.
1781	* See Intel spec. 10.11.2 "Message Data Register Format".
1782	*
1783	* This also conforms to the AMD IOMMU spec. which omits specifying individual
1784	* fields but specifies reserved bits.
1785	*/
1786	typedef union
1787	{
1788	struct
1789	{
1790	uint32_t u8Vector : 8; /*< Bits 7:0 - Vector. /
1791	uint32_t u3DeliveryMode : 3; /*< Bits 10:8 - Delivery Mode. /
1792	uint32_t u3Rsvd0 : 3; /*< Bits 13:11 - Reserved. /
1793	uint32_t u1Level : 1; /*< Bit 14 - Level. /
1794	uint32_t u1TriggerMode : 1; /*< Bit 15 - Trigger Mode (0=edge, 1=level). /
1795	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
1796	} n;
1797	/** The 32-bit unsigned integer view. */
1798	uint32_t u32;
1799	} MSI_DATA_T;
1800	AssertCompileSize(MSI_DATA_T, 4);
1801	#define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
1802	/** Pointer to an MSI data register. */
1803	typedef MSI_DATA_T *PMSI_DATA_T;
1804	/** Pointer to a const MSI data register. */
1805	typedef MSI_DATA_T const *PCMSI_DATA_T;
1806
1807	/**
1808	* MSI Mapping Capability Header Register (PCI + MMIO).
1809	* In accordance with the AMD spec.
1810	*/
1811	typedef union
1812	{
1813	struct
1814	{
1815	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1816	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1817	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1818	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1819	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1820	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1821	} n;
1822	/** The 32-bit unsigned integer view. */
1823	uint32_t u32;
1824	} MSI_MAP_CAP_HDR_T;
1825	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1826
1827	/**
1828	* Performance Optimization Control Register (MMIO).
1829	* In accordance with the AMD spec.
1830	*/
1831	typedef union
1832	{
1833	struct
1834	{
1835	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1836	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1837	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1838	} n;
1839	/** The 32-bit unsigned integer view. */
1840	uint32_t u32;
1841	} IOMMU_PERF_OPT_CTRL_T;
1842	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1843
1844	/**
1845	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1846	* In accordance with the AMD spec.
1847	*/
1848	typedef union
1849	{
1850	struct
1851	{
1852	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1853	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1854	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1855	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1856	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1857	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1858	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1859	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1860	} n;
1861	/** The 64-bit unsigned integer view. */
1862	uint64_t u64;
1863	} IOMMU_XT_GEN_INTR_CTRL_T;
1864	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1865
1866	/**
1867	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1868	* In accordance with the AMD spec.
1869	*/
1870	typedef union
1871	{
1872	struct
1873	{
1874	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1875	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1876	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1877	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1878	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1879	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1880	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1881	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1882	} n;
1883	/** The 64-bit unsigned integer view. */
1884	uint64_t u64;
1885	} IOMMU_XT_INTR_CTRL_T;
1886	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1887
1888	/**
1889	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1890	* In accordance with the AMD spec.
1891	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1892	*/
1893	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1894
1895	/**
1896	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1897	* In accordance with the AMD spec.
1898	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1899	*/
1900	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1901
1902	/**
1903	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1904	* In accordance with the AMD spec.
1905	*/
1906	typedef union
1907	{
1908	struct
1909	{
1910	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1911	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1912	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1913	} n;
1914	/** The 64-bit unsigned integer view. */
1915	uint64_t u64;
1916	} MARC_APER_BAR_T;
1917	AssertCompileSize(MARC_APER_BAR_T, 8);
1918
1919	/**
1920	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1921	* In accordance with the AMD spec.
1922	*/
1923	typedef union
1924	{
1925	struct
1926	{
1927	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1928	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1929	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1930	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1931	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1932	} n;
1933	/** The 64-bit unsigned integer view. */
1934	uint64_t u64;
1935	} MARC_APER_RELOC_T;
1936	AssertCompileSize(MARC_APER_RELOC_T, 8);
1937
1938	/**
1939	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1940	* In accordance with the AMD spec.
1941	*/
1942	typedef union
1943	{
1944	struct
1945	{
1946	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1947	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1948	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1949	} n;
1950	/** The 64-bit unsigned integer view. */
1951	uint64_t u64;
1952	} MARC_APER_LEN_T;
1953
1954	/**
1955	* Memory Access and Routing Control (MARC) Aperture Register.
1956	* This combines other registers to match the MMIO layout for convenient access.
1957	*/
1958	typedef struct
1959	{
1960	MARC_APER_BAR_T Base;
1961	MARC_APER_RELOC_T Reloc;
1962	MARC_APER_LEN_T Length;
1963	} MARC_APER_T;
1964	AssertCompileSize(MARC_APER_T, 24);
1965
1966	/**
1967	* IOMMU Reserved Register (MMIO).
1968	* In accordance with the AMD spec.
1969	* This register is reserved for hardware use (although RW?).
1970	*/
1971	typedef uint64_t IOMMU_RSVD_REG_T;
1972
1973	/**
1974	* Command Buffer Head Pointer Register (MMIO).
1975	* In accordance with the AMD spec.
1976	*/
1977	typedef union
1978	{
1979	struct
1980	{
1981	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
1982	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1983	} n;
1984	/** The 32-bit unsigned integer view. */
1985	uint32_t au32[2];
1986	/** The 64-bit unsigned integer view. */
1987	uint64_t u64;
1988	} CMD_BUF_HEAD_PTR_T;
1989	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1990	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1991
1992	/**
1993	* Command Buffer Tail Pointer Register (MMIO).
1994	* In accordance with the AMD spec.
1995	* Currently identical to CMD_BUF_HEAD_PTR_T.
1996	*/
1997	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1998	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1999
2000	/**
2001	* Event Log Head Pointer Register (MMIO).
2002	* In accordance with the AMD spec.
2003	* Currently identical to CMD_BUF_HEAD_PTR_T.
2004	*/
2005	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
2006	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
2007
2008	/**
2009	* Event Log Tail Pointer Register (MMIO).
2010	* In accordance with the AMD spec.
2011	* Currently identical to CMD_BUF_HEAD_PTR_T.
2012	*/
2013	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
2014	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
2015
2016
2017	/**
2018	* IOMMU Status Register (MMIO).
2019	* In accordance with the AMD spec.
2020	*/
2021	typedef union
2022	{
2023	struct
2024	{
2025	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
2026	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
2027	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
2028	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
2029	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
2030	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
2031	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
2032	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
2033	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
2034	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
2035	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
2036	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
2037	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
2038	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
2039	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
2040	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
2041	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
2042	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
2043	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
2044	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
2045	} n;
2046	/** The 32-bit unsigned integer view. */
2047	uint32_t au32[2];
2048	/** The 64-bit unsigned integer view. */
2049	uint64_t u64;
2050	} IOMMU_STATUS_T;
2051	AssertCompileSize(IOMMU_STATUS_T, 8);
2052	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
2053	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
2054
2055	/**
2056	* PPR Log Head Pointer Register (MMIO).
2057	* In accordance with the AMD spec.
2058	* Currently identical to CMD_BUF_HEAD_PTR_T.
2059	*/
2060	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
2061
2062	/**
2063	* PPR Log Tail Pointer Register (MMIO).
2064	* In accordance with the AMD spec.
2065	* Currently identical to CMD_BUF_HEAD_PTR_T.
2066	*/
2067	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
2068
2069	/**
2070	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
2071	* In accordance with the AMD spec.
2072	*/
2073	typedef union
2074	{
2075	struct
2076	{
2077	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
2078	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
2079	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
2080	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2081	} n;
2082	/** The 32-bit unsigned integer view. */
2083	uint32_t au32[2];
2084	/** The 64-bit unsigned integer view. */
2085	uint64_t u64;
2086	} GALOG_HEAD_PTR_T;
2087	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
2088
2089	/**
2090	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
2091	* In accordance with the AMD spec.
2092	* Currently identical to GALOG_HEAD_PTR_T.
2093	*/
2094	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
2095
2096	/**
2097	* PPR Log B Head Pointer Register (MMIO).
2098	* In accordance with the AMD spec.
2099	* Currently identical to CMD_BUF_HEAD_PTR_T.
2100	*/
2101	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
2102
2103	/**
2104	* PPR Log B Tail Pointer Register (MMIO).
2105	* In accordance with the AMD spec.
2106	* Currently identical to CMD_BUF_HEAD_PTR_T.
2107	*/
2108	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2109
2110	/**
2111	* Event Log B Head Pointer Register (MMIO).
2112	* In accordance with the AMD spec.
2113	* Currently identical to CMD_BUF_HEAD_PTR_T.
2114	*/
2115	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2116
2117	/**
2118	* Event Log B Tail Pointer Register (MMIO).
2119	* In accordance with the AMD spec.
2120	* Currently identical to CMD_BUF_HEAD_PTR_T.
2121	*/
2122	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2123
2124	/**
2125	* PPR Log Auto Response Register (MMIO).
2126	* In accordance with the AMD spec.
2127	*/
2128	typedef union
2129	{
2130	struct
2131	{
2132	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
2133	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
2134	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
2135	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
2136	} n;
2137	/** The 32-bit unsigned integer view. */
2138	uint32_t au32[2];
2139	/** The 64-bit unsigned integer view. */
2140	uint64_t u64;
2141	} PPR_LOG_AUTO_RESP_T;
2142	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2143
2144	/**
2145	* PPR Log Overflow Early Indicator Register (MMIO).
2146	* In accordance with the AMD spec.
2147	*/
2148	typedef union
2149	{
2150	struct
2151	{
2152	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2153	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2154	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2155	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2156	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2157	} n;
2158	/** The 32-bit unsigned integer view. */
2159	uint32_t au32[2];
2160	/** The 64-bit unsigned integer view. */
2161	uint64_t u64;
2162	} PPR_LOG_OVERFLOW_EARLY_T;
2163	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2164
2165	/**
2166	* PPR Log B Overflow Early Indicator Register (MMIO).
2167	* In accordance with the AMD spec.
2168	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2169	*/
2170	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2171
2172	/**
2173	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2174	* In accordance with the AMD spec.
2175	*/
2176	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2177	{
2178	kIllegalDteType_RsvdNotZero = 0,
2179	kIllegalDteType_RsvdIntTab,
2180	kIllegalDteType_RsvdIoCtl,
2181	kIllegalDteType_RsvdIntCtl
2182	} EVT_ILLEGAL_DTE_TYPE_T;
2183
2184	/**
2185	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2186	* In accordance with the AMD spec.
2187	*/
2188	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2189	{
2190	/* Memory transaction. */
2191	kIoPageFaultType_DteRsvdPagingMode = 0,
2192	kIoPageFaultType_PteInvalidPageSize,
2193	kIoPageFaultType_PteInvalidLvlEncoding,
2194	kIoPageFaultType_SkippedLevelIovaNotZero,
2195	kIoPageFaultType_PteRsvdNotZero,
2196	kIoPageFaultType_PteValidNotSet,
2197	kIoPageFaultType_DteTranslationDisabled,
2198	kIoPageFaultType_PasidInvalidRange,
2199	kIoPageFaultType_PermDenied,
2200	kIoPageFaultType_UserSupervisor,
2201	/* Interrupt remapping */
2202	kIoPageFaultType_IrteAddrInvalid,
2203	kIoPageFaultType_IrteRsvdNotZero,
2204	kIoPageFaultType_IrteRemapEn,
2205	kIoPageFaultType_IrteRsvdIntType,
2206	kIoPageFaultType_IntrReqAborted,
2207	kIoPageFaultType_IntrWithPasid,
2208	kIoPageFaultType_SmiFilterMismatch,
2209	/* Memory transaction or interrupt remapping. */
2210	kIoPageFaultType_DevId_Invalid
2211	} EVT_IO_PAGE_FAULT_TYPE_T;
2212
2213	/**
2214	* IOTLB_INV_TIMEOUT Event Types.
2215	* In accordance with the AMD spec.
2216	*/
2217	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2218	{
2219	InvTimeoutType_NoResponse = 0
2220	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2221
2222	/**
2223	* INVALID_DEVICE_REQUEST Event Types.
2224	* In accordance with the AMD spec.
2225	*/
2226	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2227	{
2228	/* Access. */
2229	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2230	kInvalidDevReqType_PretranslatedTransaction,
2231	kInvalidDevReqType_PortIo,
2232	kInvalidDevReqType_SysMgt,
2233	kInvalidDevReqType_IntrRange,
2234	kInvalidDevReqType_RsvdIntrRange,
2235	kInvalidDevReqType_SysMgtAddr,
2236	/* Translation Request. */
2237	kInvalidDevReqType_TrAccessInvalid,
2238	kInvalidDevReqType_TrDisabled,
2239	kInvalidDevReqType_DevIdInvalid,
2240	} EVT_INVALID_DEV_REQ_TYPE_T;
2241
2242	/**
2243	* INVALID_PPR_REQUEST Event Types.
2244	* In accordance with the AMD spec.
2245	*/
2246	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2247	{
2248	kInvalidPprReqType_PriNotSupported,
2249	kInvalidPprReqType_GstTranslateDisabled
2250	} EVT_INVALID_PPR_REQ_TYPE_T;
2251
2252	/**
2253	* IOMMU operations (transaction) types.
2254	*/
2255	typedef enum IOMMUOP
2256	{
2257	/** Address translation request. */
2258	IOMMUOP_TRANSLATE_REQ = 0,
2259	/** Memory read request. */
2260	IOMMUOP_MEM_READ,
2261	/** Memory write request. */
2262	IOMMUOP_MEM_WRITE,
2263	/** Interrupt request. */
2264	IOMMUOP_INTR_REQ,
2265	/** Command. */
2266	IOMMUOP_CMD
2267	} IOMMUOP;
2268	AssertCompileSize(IOMMUOP, 4);
2269
2270	/**
2271	* I/O page walk result.
2272	*/
2273	typedef struct
2274	{
2275	/** The translated system physical address. */
2276	RTGCPHYS GCPhysSpa;
2277	/** The number of offset bits in the system physical address. */
2278	uint8_t cShift;
2279	/** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
2280	uint8_t fIoPerm;
2281	/** Padding. */
2282	uint8_t abPadding[2];
2283	} IOWALKRESULT;
2284	/** Pointer to an I/O walk result struct. */
2285	typedef IOWALKRESULT *PIOWALKRESULT;
2286	/** Pointer to a const I/O walk result struct. */
2287	typedef IOWALKRESULT *PCIOWALKRESULT;
2288
2289	/**
2290	* IOMMU I/O TLB Entry.
2291	* Keep this as small and aligned as possible.
2292	*/
2293	typedef struct
2294	{
2295	/** The translated system physical address (SPA) of the page. */
2296	RTGCPHYS GCPhysSpa;
2297	/** The index of the 4K page within a large page. */
2298	uint32_t idxSubPage;
2299	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
2300	uint8_t fIoPerm;
2301	/** The number of offset bits in the translation indicating page size. */
2302	uint8_t cShift;
2303	/** Alignment padding. */
2304	uint8_t afPadding[2];
2305	} IOTLBE_T;
2306	AssertCompileSize(IOTLBE_T, 16);
2307	/** Pointer to an IOMMU I/O TLB entry struct. */
2308	typedef IOTLBE_T *PIOTLBE_T;
2309	/** Pointer to a const IOMMU I/O TLB entry struct. */
2310	typedef IOTLBE_T const *PCIOTLBE_T;
2311
2312	/**
2313	* MSI Message (Address and Data Register Pair).
2314	*/
2315	typedef struct
2316	{
2317	/** The MSI Address Register. */
2318	MSI_ADDR_T MsiAddr;
2319	/** The MSI Data Register. */
2320	MSI_DATA_T MsiData;
2321	} MSI_MSG_T;
2322	/** Pointer to an MSI message struct. */
2323	typedef MSI_MSG_T *PMSI_MSG_T;
2324	/** Pointer to a const MSI message struct. */
2325	typedef MSI_MSG_T const *PCMSI_MSG_T;
2326
2327	/**
2328	* The shared IOMMU device state.
2329	*/
2330	typedef struct IOMMU
2331	{
2332	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
2333	uint32_t idxIommu;
2334	/** Alignment padding. */
2335	uint32_t uPadding0;
2336
2337	/** Whether the command thread is sleeping. */
2338	bool volatile fCmdThreadSleeping;
2339	/** Alignment padding. */
2340	uint8_t afPadding0[3];
2341	/** Whether the command thread has been signaled for wake up. */
2342	bool volatile fCmdThreadSignaled;
2343	/** Alignment padding. */
2344	uint8_t afPadding1[3];
2345
2346	/** The event semaphore the command thread waits on. */
2347	SUPSEMEVENT hEvtCmdThread;
2348	/** The MMIO handle. */
2349	IOMMMIOHANDLE hMmio;
2350
2351	/** @name PCI: Base capability block registers.
2352	* @{ */
2353	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
2354	/** @} */
2355
2356	/** @name MMIO: Control and status registers.
2357	* @{ */
2358	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
2359	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
2360	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
2361	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
2362	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
2363	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
2364	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
2365	/** @} */
2366
2367	/** @name MMIO: PPR Log registers.
2368	* @{ */
2369	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
2370	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
2371	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
2372	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
2373	/** @} */
2374
2375	/** @todo IOMMU: SMI filter. */
2376
2377	/** @name MMIO: Guest Virtual-APIC Log registers.
2378	* @{ */
2379	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
2380	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
2381	/** @} */
2382
2383	/** @name MMIO: Alternate PPR and Event Log registers.
2384	* @{ */
2385	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
2386	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
2387	/** @} */
2388
2389	/** @name MMIO: Device-specific feature registers.
2390	* @{ */
2391	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
2392	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
2393	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
2394	/** @} */
2395
2396	/** @name MMIO: MSI Capability Block registers.
2397	* @{ */
2398	MSI_MISC_INFO_T MsiMiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
2399	/** @} */
2400
2401	/** @name MMIO: Performance Optimization Control registers.
2402	* @{ */
2403	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
2404	/** @} */
2405
2406	/** @name MMIO: x2APIC Control registers.
2407	* @{ */
2408	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
2409	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
2410	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
2411	/** @} */
2412
2413	/** @name MMIO: MARC registers.
2414	* @{ */
2415	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
2416	/** @} */
2417
2418	/** @name MMIO: Reserved register.
2419	* @{ */
2420	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
2421	/** @} */
2422
2423	/** @name MMIO: Command and Event Log pointer registers.
2424	* @{ */
2425	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
2426	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
2427	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
2428	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
2429	/** @} */
2430
2431	/** @name MMIO: Command and Event Status register.
2432	* @{ */
2433	IOMMU_STATUS_T Status; /*< IOMMU status register. /
2434	/** @} */
2435
2436	/** @name MMIO: PPR Log Head and Tail pointer registers.
2437	* @{ */
2438	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
2439	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
2440	/** @} */
2441
2442	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
2443	* @{ */
2444	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2445	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2446	/** @} */
2447
2448	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2449	* @{ */
2450	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2451	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2452	/** @} */
2453
2454	/** @name MMIO: Event Log B Head and Tail pointer registers.
2455	* @{ */
2456	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2457	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2458	/** @} */
2459
2460	/** @name MMIO: PPR Log Overflow protection registers.
2461	* @{ */
2462	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2463	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2464	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2465	/** @} */
2466
2467	/** @todo IOMMU: IOMMU Event counter registers. */
2468
2469	/** @todo IOMMU: Stat counters. */
2470	} IOMMU;
2471	/** Pointer to the IOMMU device state. */
2472	typedef struct IOMMU *PIOMMU;
2473	/** Pointer to the const IOMMU device state. */
2474	typedef const struct IOMMU *PCIOMMU;
2475	AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
2476	AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
2477	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
2478	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
2479	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
2480
2481	/**
2482	* The ring-3 IOMMU device state.
2483	*/
2484	typedef struct IOMMUR3
2485	{
2486	/** Device instance. */
2487	PPDMDEVINSR3 pDevInsR3;
2488	/** The IOMMU helpers. */
2489	PCPDMIOMMUHLPR3 pIommuHlpR3;
2490	/** The command thread handle. */
2491	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2492	} IOMMUR3;
2493	/** Pointer to the ring-3 IOMMU device state. */
2494	typedef IOMMUR3 *PIOMMUR3;
2495
2496	/**
2497	* The ring-0 IOMMU device state.
2498	*/
2499	typedef struct IOMMUR0
2500	{
2501	/** Device instance. */
2502	PPDMDEVINSR0 pDevInsR0;
2503	/** The IOMMU helpers. */
2504	PCPDMIOMMUHLPR0 pIommuHlpR0;
2505	} IOMMUR0;
2506	/** Pointer to the ring-0 IOMMU device state. */
2507	typedef IOMMUR0 *PIOMMUR0;
2508
2509	/**
2510	* The raw-mode IOMMU device state.
2511	*/
2512	typedef struct IOMMURC
2513	{
2514	/** Device instance. */
2515	PPDMDEVINSR0 pDevInsRC;
2516	/** The IOMMU helpers. */
2517	PCPDMIOMMUHLPRC pIommuHlpRC;
2518	} IOMMURC;
2519	/** Pointer to the raw-mode IOMMU device state. */
2520	typedef IOMMURC *PIOMMURC;
2521
2522	/** The IOMMU device state for the current context. */
2523	typedef CTX_SUFF(IOMMU) IOMMUCC;
2524	/** Pointer to the IOMMU device state for the current context. */
2525	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2526
2527	/**
2528	* IOMMU register access routines.
2529	*/
2530	typedef struct
2531	{
2532	const char *pszName;
2533	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2534	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2535	bool f64BitReg;
2536	} IOMMUREGACC;
2537
2538
2539	/*********************************************************************************************************************************
2540	* Global Variables *
2541	*********************************************************************************************************************************/
2542	/**
2543	* An array of the number of device table segments supported.
2544	* Indexed by u2DevTabSegSup.
2545	*/
2546	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
2547
2548	/**
2549	* An array of the masks to select the device table segment index from a device ID.
2550	*/
2551	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
2552
2553	/**
2554	* The maximum size (inclusive) of each device table segment (0 to 7).
2555	* Indexed by the device table segment index.
2556	*/
2557	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
2558
2559
2560	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2561	/**
2562	* Gets the maximum number of buffer entries for the given buffer length.
2563	*
2564	* @returns Number of buffer entries.
2565	* @param uEncodedLen The length (power-of-2 encoded).
2566	*/
2567	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
2568	{
2569	Assert(uEncodedLen > 7);
2570	return 2 << (uEncodedLen - 1);
2571	}
2572
2573
2574	/**
2575	* Gets the total length of the buffer given a base register's encoded length.
2576	*
2577	* @returns The length of the buffer in bytes.
2578	* @param uEncodedLen The length (power-of-2 encoded).
2579	*/
2580	DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
2581	{
2582	Assert(uEncodedLen > 7);
2583	return (2 << (uEncodedLen - 1)) << 4;
2584	}
2585
2586
2587	/**
2588	* Gets the number of (unconsumed) entries in the event log.
2589	*
2590	* @returns The number of entries in the event log.
2591	* @param pThis The IOMMU device state.
2592	*/
2593	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
2594	{
2595	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2596	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2597	if (idxTail >= idxHead)
2598	return idxTail - idxHead;
2599
2600	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2601	return cMaxEvts - idxHead + idxTail;
2602	}
2603
2604
2605	/**
2606	* Gets the number of (unconsumed) commands in the command buffer.
2607	*
2608	* @returns The number of commands in the command buffer.
2609	* @param pThis The IOMMU device state.
2610	*/
2611	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
2612	{
2613	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2614	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2615	if (idxTail >= idxHead)
2616	return idxTail - idxHead;
2617
2618	uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
2619	return cMaxCmds - idxHead + idxTail;
2620	}
2621
2622
2623	DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2624	{
2625	IOMMU_STATUS_T Status;
2626	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2627	return Status;
2628	}
2629
2630
2631	DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
2632	{
2633	IOMMU_CTRL_T Ctrl;
2634	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
2635	return Ctrl;
2636	}
2637
2638
2639	/**
2640	* Returns whether MSI is enabled for the IOMMU.
2641	*
2642	* @returns Whether MSI is enabled.
2643	* @param pDevIns The IOMMU device instance.
2644	*
2645	* @note There should be a PCIDevXxx function for this.
2646	*/
2647	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
2648	{
2649	MSI_CAP_HDR_T MsiCapHdr;
2650	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
2651	return MsiCapHdr.n.u1MsiEnable;
2652	}
2653
2654
2655	/**
2656	* Signals a PCI target abort.
2657	*
2658	* @param pDevIns The IOMMU device instance.
2659	*/
2660	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
2661	{
2662	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2663	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2664	PDMPciDevSetStatus(pPciDev, u16Status);
2665	}
2666
2667
2668	/**
2669	* Wakes up the command thread if there are commands to be processed or if
2670	* processing is requested to be stopped by software.
2671	*
2672	* @param pDevIns The IOMMU device instance.
2673	*/
2674	static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
2675	{
2676	IOMMU_ASSERT_LOCKED(pDevIns);
2677
2678	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2679	if ( !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true)
2680	&& ASMAtomicReadBool(&pThis->fCmdThreadSleeping))
2681	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2682	}
2683
2684
2685	/**
2686	* Writes to a read-only register.
2687	*/
2688	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2689	{
2690	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2691	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2692	return VINF_SUCCESS;
2693	}
2694
2695
2696	/**
2697	* Writes the Device Table Base Address Register.
2698	*/
2699	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2700	{
2701	RT_NOREF(pDevIns, iReg);
2702
2703	/* Mask out all unrecognized bits. */
2704	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2705
2706	/* Update the register. */
2707	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2708	return VINF_SUCCESS;
2709	}
2710
2711
2712	/**
2713	* Writes the Command Buffer Base Address Register.
2714	*/
2715	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2716	{
2717	RT_NOREF(pDevIns, iReg);
2718
2719	/*
2720	* While this is not explicitly specified like the event log base address register,
2721	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2722	* Inconsistent specs :/
2723	*/
2724	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2725	if (Status.n.u1CmdBufRunning)
2726	{
2727	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2728	return VINF_SUCCESS;
2729	}
2730
2731	/* Mask out all unrecognized bits. */
2732	CMD_BUF_BAR_T CmdBufBaseAddr;
2733	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2734
2735	/* Validate the length. */
2736	if (CmdBufBaseAddr.n.u4Len >= 8)
2737	{
2738	/* Update the register. */
2739	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2740
2741	/*
2742	* Writing the command buffer base address, clears the command buffer head and tail pointers.
2743	* See AMD spec. 2.4 "Commands".
2744	*/
2745	pThis->CmdBufHeadPtr.u64 = 0;
2746	pThis->CmdBufTailPtr.u64 = 0;
2747	}
2748	else
2749	Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2750
2751	return VINF_SUCCESS;
2752	}
2753
2754
2755	/**
2756	* Writes the Event Log Base Address Register.
2757	*/
2758	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2759	{
2760	RT_NOREF(pDevIns, iReg);
2761
2762	/*
2763	* IOMMU behavior is undefined when software writes this register when event logging is running.
2764	* In our emulation, we ignore the write entirely.
2765	* See AMD IOMMU spec. "Event Log Base Address Register".
2766	*/
2767	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2768	if (Status.n.u1EvtLogRunning)
2769	{
2770	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2771	return VINF_SUCCESS;
2772	}
2773
2774	/* Mask out all unrecognized bits. */
2775	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2776	EVT_LOG_BAR_T EvtLogBaseAddr;
2777	EvtLogBaseAddr.u64 = u64Value;
2778
2779	/* Validate the length. */
2780	if (EvtLogBaseAddr.n.u4Len >= 8)
2781	{
2782	/* Update the register. */
2783	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2784
2785	/*
2786	* Writing the event log base address, clears the event log head and tail pointers.
2787	* See AMD spec. 2.5 "Event Logging".
2788	*/
2789	pThis->EvtLogHeadPtr.u64 = 0;
2790	pThis->EvtLogTailPtr.u64 = 0;
2791	}
2792	else
2793	Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2794
2795	return VINF_SUCCESS;
2796	}
2797
2798
2799	/**
2800	* Writes the Control Register.
2801	*/
2802	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2803	{
2804	RT_NOREF(pDevIns, iReg);
2805
2806	/* Mask out all unrecognized bits. */
2807	u64Value &= IOMMU_CTRL_VALID_MASK;
2808
2809	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
2810	IOMMU_CTRL_T NewCtrl;
2811	NewCtrl.u64 = u64Value;
2812
2813	/* Update the register. */
2814	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2815
2816	/* Enable or disable event logging when the bit transitions. */
2817	bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2818	bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2819	bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2820	if (fOldEvtLogEn != fNewEvtLogEn)
2821	{
2822	if ( fNewIommuEn
2823	&& fNewEvtLogEn)
2824	{
2825	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2826	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2827	}
2828	else
2829	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2830	}
2831
2832	/* Enable or disable command buffer processing when the bit transitions. */
2833	bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2834	bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2835	if (fOldCmdBufEn != fNewCmdBufEn)
2836	{
2837	if ( fNewIommuEn
2838	&& fNewCmdBufEn)
2839	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2840	else
2841	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2842
2843	/* Wake up the command thread to start or stop processing commands. */
2844	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2845	}
2846	}
2847
2848
2849	/**
2850	* Writes to the Excluse Range Base Address Register.
2851	*/
2852	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2853	{
2854	RT_NOREF(pDevIns, iReg);
2855	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2856	return VINF_SUCCESS;
2857	}
2858
2859
2860	/**
2861	* Writes to the Excluse Range Limit Register.
2862	*/
2863	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2864	{
2865	RT_NOREF(pDevIns, iReg);
2866	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2867	u64Value \|= UINT64_C(0xfff);
2868	pThis->ExclRangeLimit.u64 = u64Value;
2869	return VINF_SUCCESS;
2870	}
2871
2872
2873	/**
2874	* Writes the Hardware Event Register (Hi).
2875	*/
2876	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2877	{
2878	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2879	RT_NOREF(pDevIns, iReg);
2880	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2881	pThis->HwEvtHi.u64 = u64Value;
2882	return VINF_SUCCESS;
2883	}
2884
2885
2886	/**
2887	* Writes the Hardware Event Register (Lo).
2888	*/
2889	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2890	{
2891	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2892	RT_NOREF(pDevIns, iReg);
2893	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2894	pThis->HwEvtLo = u64Value;
2895	return VINF_SUCCESS;
2896	}
2897
2898
2899	/**
2900	* Writes the Hardware Event Status Register.
2901	*/
2902	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2903	{
2904	RT_NOREF(pDevIns, iReg);
2905
2906	/* Mask out all unrecognized bits. */
2907	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2908
2909	/*
2910	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2911	* If the current status bits or the bits being written are both 0, we've nothing to do.
2912	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2913	*/
2914	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2915	if (!(HwStatus & RT_BIT(0)))
2916	return VINF_SUCCESS;
2917	if (u64Value & HwStatus & RT_BIT_64(0))
2918	HwStatus &= ~RT_BIT_64(0);
2919	if (u64Value & HwStatus & RT_BIT_64(1))
2920	HwStatus &= ~RT_BIT_64(1);
2921
2922	/* Update the register. */
2923	pThis->HwEvtStatus.u64 = HwStatus;
2924	return VINF_SUCCESS;
2925	}
2926
2927
2928	/**
2929	* Writes the Device Table Segment Base Address Register.
2930	*/
2931	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2932	{
2933	RT_NOREF(pDevIns);
2934
2935	/* Figure out which segment is being written. */
2936	uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2937	uint8_t const idxSegment = offSegment + 1;
2938	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2939
2940	/* Mask out all unrecognized bits. */
2941	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2942	DEV_TAB_BAR_T DevTabSegBar;
2943	DevTabSegBar.u64 = u64Value;
2944
2945	/* Validate the size. */
2946	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2947	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2948	if (uSegSize <= uMaxSegSize)
2949	{
2950	/* Update the register. */
2951	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2952	}
2953	else
2954	Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2955
2956	return VINF_SUCCESS;
2957	}
2958
2959
2960	/**
2961	* Writes the MSI Capability Header Register.
2962	*/
2963	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2964	{
2965	RT_NOREF(pThis, iReg);
2966	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2967	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2968	MSI_CAP_HDR_T MsiCapHdr;
2969	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2970	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2971	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2972	return VINF_SUCCESS;
2973	}
2974
2975
2976	/**
2977	* Writes the MSI Address (Lo) Register (32-bit).
2978	*/
2979	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2980	{
2981	RT_NOREF(pThis, iReg);
2982	Assert(!RT_HI_U32(u64Value));
2983	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2984	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2985	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & IOMMU_MSI_ADDR_VALID_MASK);
2986	return VINF_SUCCESS;
2987	}
2988
2989
2990	/**
2991	* Writes the MSI Address (Hi) Register (32-bit).
2992	*/
2993	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2994	{
2995	RT_NOREF(pThis, iReg);
2996	Assert(!RT_HI_U32(u64Value));
2997	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2998	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2999	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
3000	return VINF_SUCCESS;
3001	}
3002
3003
3004	/**
3005	* Writes the MSI Data Register (32-bit).
3006	*/
3007	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3008	{
3009	RT_NOREF(pThis, iReg);
3010	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3011	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3012	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & IOMMU_MSI_DATA_VALID_MASK);
3013	return VINF_SUCCESS;
3014	}
3015
3016
3017	/**
3018	* Writes the Command Buffer Head Pointer Register (32-bit).
3019	*/
3020	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3021	{
3022	RT_NOREF(pDevIns, iReg);
3023
3024	/*
3025	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
3026	* In our emulation, we ignore the write entirely.
3027	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3028	*/
3029	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3030	if (Status.n.u1CmdBufRunning)
3031	{
3032	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
3033	return VINF_SUCCESS;
3034	}
3035
3036	/*
3037	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3038	* In our emulation, we ignore the write entirely.
3039	*/
3040	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
3041	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3042	Assert(cbBuf <= _512K);
3043	if (offBuf >= cbBuf)
3044	{
3045	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
3046	offBuf, cbBuf));
3047	return VINF_SUCCESS;
3048	}
3049
3050	/* Update the register. */
3051	pThis->CmdBufHeadPtr.au32[0] = offBuf;
3052
3053	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3054
3055	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
3056	return VINF_SUCCESS;
3057	}
3058
3059
3060	/**
3061	* Writes the Command Buffer Tail Pointer Register (32-bit).
3062	*/
3063	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3064	{
3065	RT_NOREF(pDevIns, iReg);
3066
3067	/*
3068	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3069	* In our emulation, we ignore the write entirely.
3070	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3071	*/
3072	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
3073	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3074	Assert(cbBuf <= _512K);
3075	if (offBuf >= cbBuf)
3076	{
3077	Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3078	offBuf, cbBuf));
3079	return VINF_SUCCESS;
3080	}
3081
3082	/*
3083	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
3084	* head pointer after adding one or more commands to the buffer.
3085	*
3086	* However, we cannot enforce this strictly because it's legal for software to shrink the
3087	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
3088	* at 0). Software might even make the queue empty by making head and tail equal which is
3089	* allowed. I don't think we can or should try too hard to prevent software shooting itself
3090	* in the foot here. As long as we make sure the offset value is within the circular buffer
3091	* bounds (which we do by masking bits above) it should be sufficient.
3092	*/
3093	pThis->CmdBufTailPtr.au32[0] = offBuf;
3094
3095	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3096
3097	LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
3098	return VINF_SUCCESS;
3099	}
3100
3101
3102	/**
3103	* Writes the Event Log Head Pointer Register (32-bit).
3104	*/
3105	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3106	{
3107	RT_NOREF(pDevIns, iReg);
3108
3109	/*
3110	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3111	* In our emulation, we ignore the write entirely.
3112	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3113	*/
3114	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
3115	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3116	Assert(cbBuf <= _512K);
3117	if (offBuf >= cbBuf)
3118	{
3119	Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3120	offBuf, cbBuf));
3121	return VINF_SUCCESS;
3122	}
3123
3124	/* Update the register. */
3125	pThis->EvtLogHeadPtr.au32[0] = offBuf;
3126
3127	LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
3128	return VINF_SUCCESS;
3129	}
3130
3131
3132	/**
3133	* Writes the Event Log Tail Pointer Register (32-bit).
3134	*/
3135	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3136	{
3137	RT_NOREF(pDevIns, iReg);
3138	NOREF(pThis);
3139
3140	/*
3141	* IOMMU behavior is undefined when software writes this register when the event log is running.
3142	* In our emulation, we ignore the write entirely.
3143	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3144	*/
3145	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3146	if (Status.n.u1EvtLogRunning)
3147	{
3148	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
3149	return VINF_SUCCESS;
3150	}
3151
3152	/*
3153	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3154	* In our emulation, we ignore the write entirely.
3155	*/
3156	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
3157	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3158	Assert(cbBuf <= _512K);
3159	if (offBuf >= cbBuf)
3160	{
3161	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3162	offBuf, cbBuf));
3163	return VINF_SUCCESS;
3164	}
3165
3166	/* Update the register. */
3167	pThis->EvtLogTailPtr.au32[0] = offBuf;
3168
3169	LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
3170	return VINF_SUCCESS;
3171	}
3172
3173
3174	/**
3175	* Writes the Status Register (64-bit).
3176	*/
3177	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3178	{
3179	RT_NOREF(pDevIns, iReg);
3180
3181	/* Mask out all unrecognized bits. */
3182	u64Value &= IOMMU_STATUS_VALID_MASK;
3183
3184	/*
3185	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
3186	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
3187	*/
3188	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
3189	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
3190	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
3191	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
3192
3193	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
3194
3195	/* Update the register. */
3196	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
3197	return VINF_SUCCESS;
3198	}
3199
3200
3201	#if 0
3202	/**
3203	* Table 0: Registers-access table.
3204	*/
3205	static const IOMMUREGACC g_aTable0Regs[] =
3206	{
3207
3208	};
3209
3210	/**
3211	* Table 1: Registers-access table.
3212	*/
3213	static const IOMMUREGACC g_aTable1Regs[] =
3214	{
3215	};
3216	#endif
3217
3218
3219	/**
3220	* Writes an IOMMU register (32-bit and 64-bit).
3221	*
3222	* @returns Strict VBox status code.
3223	* @param pDevIns The IOMMU device instance.
3224	* @param off MMIO byte offset to the register.
3225	* @param cb The size of the write access.
3226	* @param uValue The value being written.
3227	*
3228	* @thread EMT.
3229	*/
3230	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
3231	{
3232	Assert(off < IOMMU_MMIO_REGION_SIZE);
3233	Assert(cb == 4 \|\| cb == 8);
3234	Assert(!(off & (cb - 1)));
3235
3236	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3237	switch (off)
3238	{
3239	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
3240	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
3241	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
3242	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
3243	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
3244	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
3245	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3246
3247	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3248	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
3249	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
3250	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
3251
3252	case IOMMU_MMIO_OFF_GALOG_BAR:
3253	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3254
3255	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
3256	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3257
3258	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3259	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3260	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3261	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3262	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3263	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3264	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
3265
3266	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
3267	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
3268	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3269
3270	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
3271	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3272	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3273	{
3274	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
3275	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3276	return rcStrict;
3277	uValue >>= 32;
3278	RT_FALL_THRU();
3279	}
3280	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
3281	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3282	{
3283	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
3284	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3285	return rcStrict;
3286	uValue >>= 32;
3287	RT_FALL_THRU();
3288	}
3289	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
3290	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3291
3292	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3293
3294	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
3295	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
3296	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3297
3298	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
3299	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
3300	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
3301	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
3302	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
3303	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
3304	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
3305	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
3306	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
3307	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
3308	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
3309	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3310
3311	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3312
3313	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
3314	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
3315	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
3316	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
3317
3318	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
3319
3320	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
3321	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
3322
3323	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
3324	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
3325
3326	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
3327	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
3328
3329	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
3330	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3331
3332	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
3333	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
3334	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
3335
3336	/* Not implemented. */
3337	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3338	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3339	{
3340	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
3341	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3342	return VINF_SUCCESS;
3343	}
3344
3345	/* Unknown. */
3346	default:
3347	{
3348	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
3349	return VINF_SUCCESS;
3350	}
3351	}
3352	}
3353
3354
3355	/**
3356	* Reads an IOMMU register (64-bit) given its MMIO offset.
3357	*
3358	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
3359	* boundary include the lower half of the subsequent register.
3360	*
3361	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
3362	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
3363	* software will only perform 32-bit reads on those 32-bit registers that are
3364	* aligned on 8-byte boundaries.
3365	*
3366	* @returns Strict VBox status code.
3367	* @param pDevIns The IOMMU device instance.
3368	* @param off The MMIO offset of the register in bytes.
3369	* @param puResult Where to store the value being read.
3370	*
3371	* @thread EMT.
3372	*/
3373	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
3374	{
3375	Assert(off < IOMMU_MMIO_REGION_SIZE);
3376	Assert(!(off & 7) \|\| !(off & 3));
3377
3378	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3379	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3380	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3381
3382	/** @todo IOMMU: fine-grained locking? */
3383	uint64_t uReg;
3384	switch (off)
3385	{
3386	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
3387	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
3388	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
3389	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
3390	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
3391	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
3392	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
3393
3394	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
3395	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
3396	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
3397	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
3398
3399	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
3400	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
3401
3402	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
3403	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
3404
3405	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3406	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3407	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3408	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3409	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3410	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3411	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
3412	{
3413	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
3414	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
3415	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3416	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
3417	break;
3418	}
3419
3420	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
3421	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
3422	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
3423
3424	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MsiMiscInfo.u64; break;
3425	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MsiMiscInfo.au32[1]; break;
3426	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3427	{
3428	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3429	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3430	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
3431	break;
3432	}
3433	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
3434	{
3435	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3436	break;
3437	}
3438	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3439	{
3440	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3441	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3442	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
3443	break;
3444	}
3445	case IOMMU_MMIO_OFF_MSI_DATA:
3446	{
3447	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3448	break;
3449	}
3450	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
3451	{
3452	/*
3453	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
3454	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
3455	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
3456	* 0 for this register.
3457	*/
3458	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
3459	break;
3460	}
3461
3462	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
3463
3464	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
3465	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
3466	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
3467
3468	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
3469	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
3470	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
3471	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
3472	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
3473	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
3474	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
3475	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
3476	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
3477	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
3478	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
3479	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
3480
3481	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
3482
3483	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
3484	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
3485	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
3486	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
3487
3488	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
3489
3490	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
3491	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
3492
3493	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
3494	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
3495
3496	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
3497	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
3498
3499	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
3500	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
3501
3502	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
3503	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
3504	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
3505
3506	/* Not implemented. */
3507	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3508	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3509	{
3510	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3511	uReg = 0;
3512	break;
3513	}
3514
3515	/* Unknown. */
3516	default:
3517	{
3518	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
3519	uReg = 0;
3520	return VINF_IOM_MMIO_UNUSED_00;
3521	}
3522	}
3523
3524	*puResult = uReg;
3525	return VINF_SUCCESS;
3526	}
3527
3528
3529	/**
3530	* Raises the MSI interrupt for the IOMMU device.
3531	*
3532	* @param pDevIns The IOMMU device instance.
3533	*
3534	* @thread Any.
3535	*/
3536	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
3537	{
3538	if (iommuAmdIsMsiEnabled(pDevIns))
3539	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
3540	}
3541
3542
3543	/**
3544	* Clears the MSI interrupt for the IOMMU device.
3545	*
3546	* @param pDevIns The IOMMU device instance.
3547	*
3548	* @thread Any.
3549	*/
3550	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
3551	{
3552	if (iommuAmdIsMsiEnabled(pDevIns))
3553	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3554	}
3555
3556
3557	/**
3558	* Writes an entry to the event log in memory.
3559	*
3560	* @returns VBox status code.
3561	* @param pDevIns The IOMMU device instance.
3562	* @param pEvent The event to log.
3563	*
3564	* @thread Any.
3565	*/
3566	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3567	{
3568	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3569
3570	IOMMU_ASSERT_LOCKED(pDevIns);
3571
3572	/* Check if event logging is active and the log has not overflowed. */
3573	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3574	if ( Status.n.u1EvtLogRunning
3575	&& !Status.n.u1EvtOverflow)
3576	{
3577	uint32_t const cbEvt = sizeof(*pEvent);
3578
3579	/* Get the offset we need to write the event to in memory (circular buffer offset). */
3580	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3581	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3582
3583	/* Ensure we have space in the event log. */
3584	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3585	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3586	if (cEvts + 1 < cMaxEvts)
3587	{
3588	/* Write the event log entry to memory. */
3589	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3590	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3591	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3592	if (RT_FAILURE(rc))
3593	Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3594
3595	/* Increment the event log tail pointer. */
3596	uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3597	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3598
3599	/* Indicate that an event log entry was written. */
3600	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3601
3602	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3603	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3604	if (Ctrl.n.u1EvtIntrEn)
3605	iommuAmdRaiseMsiInterrupt(pDevIns);
3606	}
3607	else
3608	{
3609	/* Indicate that the event log has overflowed. */
3610	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3611
3612	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3613	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3614	if (Ctrl.n.u1EvtIntrEn)
3615	iommuAmdRaiseMsiInterrupt(pDevIns);
3616	}
3617	}
3618	}
3619
3620
3621	/**
3622	* Sets an event in the hardware error registers.
3623	*
3624	* @param pDevIns The IOMMU device instance.
3625	* @param pEvent The event.
3626	*
3627	* @thread Any.
3628	*/
3629	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3630	{
3631	IOMMU_ASSERT_LOCKED(pDevIns);
3632
3633	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3634	if (pThis->ExtFeat.n.u1HwErrorSup)
3635	{
3636	if (pThis->HwEvtStatus.n.u1Valid)
3637	pThis->HwEvtStatus.n.u1Overflow = 1;
3638	pThis->HwEvtStatus.n.u1Valid = 1;
3639	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3640	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3641	Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
3642	}
3643	}
3644
3645
3646	/**
3647	* Initializes a PAGE_TAB_HARDWARE_ERROR event.
3648	*
3649	* @param uDevId The device ID.
3650	* @param uDomainId The domain ID.
3651	* @param GCPhysPtEntity The system physical address of the page table
3652	* entity.
3653	* @param enmOp The IOMMU operation being performed.
3654	* @param pEvtPageTabHwErr Where to store the initialized event.
3655	*/
3656	static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3657	PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3658	{
3659	memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3660	pEvtPageTabHwErr->n.u16DevId = uDevId;
3661	pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
3662	pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3663	pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3664	pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3665	pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3666	pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3667	pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3668	pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3669	}
3670
3671
3672	/**
3673	* Raises a PAGE_TAB_HARDWARE_ERROR event.
3674	*
3675	* @param pDevIns The IOMMU device instance.
3676	* @param enmOp The IOMMU operation being performed.
3677	* @param pEvtPageTabHwErr The page table hardware error event.
3678	*
3679	* @thread Any.
3680	*/
3681	static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3682	{
3683	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3684	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3685
3686	IOMMU_LOCK_NORET(pDevIns);
3687
3688	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3689	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3690	if (enmOp != IOMMUOP_CMD)
3691	iommuAmdSetPciTargetAbort(pDevIns);
3692
3693	IOMMU_UNLOCK(pDevIns);
3694
3695	Log((IOMMU_LOG_PFX ": Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3696	pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3697	pEvtPageTabHwErr->n.u2Type));
3698	}
3699
3700
3701	/**
3702	* Initializes a COMMAND_HARDWARE_ERROR event.
3703	*
3704	* @param GCPhysAddr The system physical address the IOMMU attempted to access.
3705	* @param pEvtCmdHwErr Where to store the initialized event.
3706	*/
3707	static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3708	{
3709	memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3710	pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3711	pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3712	pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3713	}
3714
3715
3716	/**
3717	* Raises a COMMAND_HARDWARE_ERROR event.
3718	*
3719	* @param pDevIns The IOMMU device instance.
3720	* @param pEvtCmdHwErr The command hardware error event.
3721	*
3722	* @thread Any.
3723	*/
3724	static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3725	{
3726	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3727	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3728	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3729
3730	IOMMU_LOCK_NORET(pDevIns);
3731
3732	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3733	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3734	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3735
3736	IOMMU_UNLOCK(pDevIns);
3737
3738	Log((IOMMU_LOG_PFX ": Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr,
3739	pEvtCmdHwErr->n.u2Type));
3740	}
3741
3742
3743	/**
3744	* Initializes a DEV_TAB_HARDWARE_ERROR event.
3745	*
3746	* @param uDevId The device ID.
3747	* @param GCPhysDte The system physical address of the failed device table
3748	* access.
3749	* @param enmOp The IOMMU operation being performed.
3750	* @param pEvtDevTabHwErr Where to store the initialized event.
3751	*/
3752	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3753	PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3754	{
3755	memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3756	pEvtDevTabHwErr->n.u16DevId = uDevId;
3757	pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3758	/** @todo IOMMU: Any other transaction type that can set read/write bit? */
3759	pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3760	pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3761	pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3762	pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3763	pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3764	}
3765
3766
3767	/**
3768	* Raises a DEV_TAB_HARDWARE_ERROR event.
3769	*
3770	* @param pDevIns The IOMMU device instance.
3771	* @param enmOp The IOMMU operation being performed.
3772	* @param pEvtDevTabHwErr The device table hardware error event.
3773	*
3774	* @thread Any.
3775	*/
3776	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3777	{
3778	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3779	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3780
3781	IOMMU_LOCK_NORET(pDevIns);
3782
3783	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3784	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3785	if (enmOp != IOMMUOP_CMD)
3786	iommuAmdSetPciTargetAbort(pDevIns);
3787
3788	IOMMU_UNLOCK(pDevIns);
3789
3790	Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n",
3791	pEvtDevTabHwErr->n.u16DevId, pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3792	}
3793
3794
3795	/**
3796	* Initializes an ILLEGAL_COMMAND_ERROR event.
3797	*
3798	* @param GCPhysCmd The system physical address of the failed command
3799	* access.
3800	* @param pEvtIllegalCmd Where to store the initialized event.
3801	*/
3802	static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3803	{
3804	Assert(!(GCPhysCmd & UINT64_C(0xf)));
3805	memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3806	pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3807	pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3808	}
3809
3810
3811	/**
3812	* Raises an ILLEGAL_COMMAND_ERROR event.
3813	*
3814	* @param pDevIns The IOMMU device instance.
3815	* @param pEvtIllegalCmd The illegal command error event.
3816	*/
3817	static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3818	{
3819	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3820	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3821	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3822
3823	IOMMU_LOCK_NORET(pDevIns);
3824
3825	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3826	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3827
3828	IOMMU_UNLOCK(pDevIns);
3829
3830	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3831	}
3832
3833
3834	/**
3835	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3836	*
3837	* @param uDevId The device ID.
3838	* @param uIova The I/O virtual address.
3839	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3840	* event was caused by an invalid level encoding in the
3841	* DTE.
3842	* @param enmOp The IOMMU operation being performed.
3843	* @param pEvtIllegalDte Where to store the initialized event.
3844	*/
3845	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3846	PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3847	{
3848	memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3849	pEvtIllegalDte->n.u16DevId = uDevId;
3850	pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3851	pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3852	pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3853	pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3854	pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3855	pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3856	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3857	* IOMMU spec here but not for this field for I/O page fault event. */
3858	Assert(!(uIova & UINT64_C(0x3)));
3859	}
3860
3861
3862	/**
3863	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3864	*
3865	* @param pDevIns The IOMMU instance data.
3866	* @param enmOp The IOMMU operation being performed.
3867	* @param pEvtIllegalDte The illegal device table entry event.
3868	* @param enmEvtType The illegal device table entry event type.
3869	*
3870	* @thread Any.
3871	*/
3872	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3873	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3874	{
3875	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3876	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3877
3878	IOMMU_LOCK_NORET(pDevIns);
3879
3880	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3881	if (enmOp != IOMMUOP_CMD)
3882	iommuAmdSetPciTargetAbort(pDevIns);
3883
3884	IOMMU_UNLOCK(pDevIns);
3885
3886	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3887	pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3888	NOREF(enmEvtType);
3889	}
3890
3891
3892	/**
3893	* Initializes an IO_PAGE_FAULT event.
3894	*
3895	* @param uDevId The device ID.
3896	* @param uDomainId The domain ID.
3897	* @param uIova The I/O virtual address being accessed.
3898	* @param fPresent Transaction to a page marked as present (including
3899	* DTE.V=1) or interrupt marked as remapped
3900	* (IRTE.RemapEn=1).
3901	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3902	* the I/O page fault was caused by invalid level
3903	* encoding.
3904	* @param fPermDenied Permission denied for the address being accessed.
3905	* @param enmOp The IOMMU operation being performed.
3906	* @param pEvtIoPageFault Where to store the initialized event.
3907	*/
3908	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3909	bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3910	{
3911	Assert(!fPermDenied \|\| fPresent);
3912	memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3913	pEvtIoPageFault->n.u16DevId = uDevId;
3914	//pEvtIoPageFault->n.u4PasidHi = 0;
3915	pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3916	//pEvtIoPageFault->n.u1GuestOrNested = 0;
3917	//pEvtIoPageFault->n.u1NoExecute = 0;
3918	//pEvtIoPageFault->n.u1User = 0;
3919	pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3920	pEvtIoPageFault->n.u1Present = fPresent;
3921	pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3922	pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3923	pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3924	pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3925	pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3926	pEvtIoPageFault->n.u64Addr = uIova;
3927	}
3928
3929
3930	/**
3931	* Raises an IO_PAGE_FAULT event.
3932	*
3933	* @param pDevIns The IOMMU instance data.
3934	* @param pDte The device table entry. Optional, can be NULL
3935	* depending on @a enmOp.
3936	* @param pIrte The interrupt remapping table entry. Optional, can
3937	* be NULL depending on @a enmOp.
3938	* @param enmOp The IOMMU operation being performed.
3939	* @param pEvtIoPageFault The I/O page fault event.
3940	* @param enmEvtType The I/O page fault event type.
3941	*
3942	* @thread Any.
3943	*/
3944	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3945	PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3946	{
3947	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3948	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3949
3950	IOMMU_LOCK_NORET(pDevIns);
3951
3952	bool fSuppressEvtLogging = false;
3953	if ( enmOp == IOMMUOP_MEM_READ
3954	\|\| enmOp == IOMMUOP_MEM_WRITE)
3955	{
3956	if ( pDte
3957	&& pDte->n.u1Valid)
3958	{
3959	fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
3960	/** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
3961	* suppression. Perhaps will be possible when we complete IOTLB/cache
3962	* handling. */
3963	}
3964	}
3965	else if (enmOp == IOMMUOP_INTR_REQ)
3966	{
3967	if ( pDte
3968	&& pDte->n.u1IntrMapValid)
3969	fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
3970
3971	if ( !fSuppressEvtLogging
3972	&& pIrte)
3973	fSuppressEvtLogging = pIrte->n.u1SuppressPf;
3974	}
3975	/* else: Events are never suppressed for commands. */
3976
3977	switch (enmEvtType)
3978	{
3979	case kIoPageFaultType_PermDenied:
3980	{
3981	/* Cannot be triggered by a command. */
3982	Assert(enmOp != IOMMUOP_CMD);
3983	RT_FALL_THRU();
3984	}
3985	case kIoPageFaultType_DteRsvdPagingMode:
3986	case kIoPageFaultType_PteInvalidPageSize:
3987	case kIoPageFaultType_PteInvalidLvlEncoding:
3988	case kIoPageFaultType_SkippedLevelIovaNotZero:
3989	case kIoPageFaultType_PteRsvdNotZero:
3990	case kIoPageFaultType_PteValidNotSet:
3991	case kIoPageFaultType_DteTranslationDisabled:
3992	case kIoPageFaultType_PasidInvalidRange:
3993	{
3994	/*
3995	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3996	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
3997	*/
3998	if (enmOp != IOMMUOP_TRANSLATE_REQ)
3999	{
4000	if (!fSuppressEvtLogging)
4001	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4002	if (enmOp != IOMMUOP_CMD)
4003	iommuAmdSetPciTargetAbort(pDevIns);
4004	}
4005	break;
4006	}
4007
4008	case kIoPageFaultType_UserSupervisor:
4009	{
4010	/* Access is blocked and only creates an event log entry. */
4011	if (!fSuppressEvtLogging)
4012	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4013	break;
4014	}
4015
4016	case kIoPageFaultType_IrteAddrInvalid:
4017	case kIoPageFaultType_IrteRsvdNotZero:
4018	case kIoPageFaultType_IrteRemapEn:
4019	case kIoPageFaultType_IrteRsvdIntType:
4020	case kIoPageFaultType_IntrReqAborted:
4021	case kIoPageFaultType_IntrWithPasid:
4022	{
4023	/* Only trigerred by interrupt requests. */
4024	Assert(enmOp == IOMMUOP_INTR_REQ);
4025	if (!fSuppressEvtLogging)
4026	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4027	iommuAmdSetPciTargetAbort(pDevIns);
4028	break;
4029	}
4030
4031	case kIoPageFaultType_SmiFilterMismatch:
4032	{
4033	/* Not supported and probably will never be, assert. */
4034	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
4035	break;
4036	}
4037
4038	case kIoPageFaultType_DevId_Invalid:
4039	{
4040	/* Cannot be triggered by a command. */
4041	Assert(enmOp != IOMMUOP_CMD);
4042	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
4043	if (!fSuppressEvtLogging)
4044	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4045	if ( enmOp == IOMMUOP_MEM_READ
4046	\|\| enmOp == IOMMUOP_MEM_WRITE)
4047	iommuAmdSetPciTargetAbort(pDevIns);
4048	break;
4049	}
4050	}
4051
4052	IOMMU_UNLOCK(pDevIns);
4053	}
4054
4055
4056	/**
4057	* Returns whether the I/O virtual address is to be excluded from translation and
4058	* permission checks.
4059	*
4060	* @returns @c true if the DVA is excluded, @c false otherwise.
4061	* @param pThis The IOMMU device state.
4062	* @param pDte The device table entry.
4063	* @param uIova The I/O virtual address.
4064	*
4065	* @remarks Ensure the exclusion range is enabled prior to calling this function.
4066	*
4067	* @thread Any.
4068	*/
4069	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
4070	{
4071	/* Ensure the exclusion range is enabled. */
4072	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
4073
4074	/* Check if the IOVA falls within the exclusion range. */
4075	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
4076	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
4077	if (uIovaExclLast - uIova >= uIovaExclFirst)
4078	{
4079	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
4080	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
4081	\|\| pDte->n.u1AllowExclusion)
4082	return true;
4083	}
4084	return false;
4085	}
4086
4087
4088	/**
4089	* Reads a device table entry from guest memory given the device ID.
4090	*
4091	* @returns VBox status code.
4092	* @param pDevIns The IOMMU device instance.
4093	* @param uDevId The device ID.
4094	* @param enmOp The IOMMU operation being performed.
4095	* @param pDte Where to store the device table entry.
4096	*
4097	* @thread Any.
4098	*/
4099	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
4100	{
4101	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4102	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4103
4104	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
4105	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
4106
4107	uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
4108	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
4109
4110	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
4111	uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
4112	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
4113
4114	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
4115	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
4116	if (RT_FAILURE(rc))
4117	{
4118	Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
4119
4120	EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
4121	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
4122	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
4123	return VERR_IOMMU_IPE_1;
4124	}
4125
4126	return rc;
4127	}
4128
4129
4130	/**
4131	* Walks the I/O page table to translate the I/O virtual address to a system
4132	* physical address.
4133	*
4134	* @returns VBox status code.
4135	* @param pDevIns The IOMMU device instance.
4136	* @param uIova The I/O virtual address to translate. Must be 4K aligned.
4137	* @param uDevId The device ID.
4138	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4139	* permissions for the access being made.
4140	* @param pDte The device table entry.
4141	* @param enmOp The IOMMU operation being performed.
4142	* @param pWalkResult Where to store the results of the I/O page walk. This is
4143	* only updated when VINF_SUCCESS is returned.
4144	*
4145	* @thread Any.
4146	*/
4147	static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
4148	IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
4149	{
4150	Assert(pDte->n.u1Valid);
4151	Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
4152
4153	/* If the translation is not valid, raise an I/O page fault. */
4154	if (pDte->n.u1TranslationValid)
4155	{ /* likely */ }
4156	else
4157	{
4158	/** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
4159	* doesn't explicitly say whether an I/O page fault is raised. From other
4160	* places in the spec. it seems early page walk terminations (starting with
4161	* the DTE) return the state computed so far and raises an I/O page fault. So
4162	* returning an invalid translation rather than skipping translation. */
4163	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4164	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4165	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4166	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4167	kIoPageFaultType_DteTranslationDisabled);
4168	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4169	}
4170
4171	/* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
4172	uint8_t const uMaxLevel = pDte->n.u3Mode;
4173	if (uMaxLevel != 0)
4174	{ /* likely */ }
4175	else
4176	{
4177	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4178	if ((fAccess & fDtePerm) != fAccess)
4179	{
4180	Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
4181	return VERR_IOMMU_ADDR_ACCESS_DENIED;
4182	}
4183	pWalkResult->GCPhysSpa = uIova;
4184	pWalkResult->cShift = 0;
4185	pWalkResult->fIoPerm = fDtePerm;
4186	return VINF_SUCCESS;
4187	}
4188
4189	/* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
4190	if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4191	{ /* likely */ }
4192	else
4193	{
4194	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
4195	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
4196	* I'm just going with I/O page fault. */
4197	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4198	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4199	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4200	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4201	kIoPageFaultType_PteInvalidLvlEncoding);
4202	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4203	}
4204
4205	/* Check permissions bits of the root page table. */
4206	uint8_t const fPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4207	if ((fAccess & fPtePerm) == fAccess)
4208	{ /* likely */ }
4209	else
4210	{
4211	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4212	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4213	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4214	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4215	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4216	}
4217
4218	/** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
4219	* function called iommuAmdWalkIoPageDirectory() and call it for multi-page
4220	* accesses from the 2nd page. We can avoid re-checking the DTE root-page
4221	* table entry every time. Not sure if it's worth optimizing that case now
4222	* or if at all. */
4223
4224	/* The virtual address bits indexing table. */
4225	static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
4226	static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
4227	UINT64_C(0x00000000001ff000),
4228	UINT64_C(0x000000003fe00000),
4229	UINT64_C(0x0000007fc0000000),
4230	UINT64_C(0x0000ff8000000000),
4231	UINT64_C(0x01ff000000000000),
4232	UINT64_C(0xfe00000000000000),
4233	UINT64_C(0x0000000000000000) };
4234	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
4235	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
4236
4237	/* Traverse the I/O page table starting with the page directory in the DTE. */
4238	IOPTENTITY_T PtEntity;
4239	PtEntity.u64 = pDte->au64[0];
4240	for (;;)
4241	{
4242	/* Figure out the system physical address of the page table at the current level. */
4243	uint8_t const uLevel = PtEntity.n.u3NextLevel;
4244
4245	/* Read the page table entity at the current level. */
4246	{
4247	Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
4248	Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4249	uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
4250	uint64_t const offPte = idxPte << 3;
4251	RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
4252	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
4253	if (RT_FAILURE(rc))
4254	{
4255	Log((IOMMU_LOG_PFX ": Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
4256	EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
4257	iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
4258	iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
4259	return VERR_IOMMU_IPE_2;
4260	}
4261	}
4262
4263	/* Check present bit. */
4264	if (PtEntity.n.u1Present)
4265	{ /* likely */ }
4266	else
4267	{
4268	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4269	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4270	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4271	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4272	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4273	}
4274
4275	/* Check permission bits. */
4276	uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4277	if ((fAccess & fPtePerm) == fAccess)
4278	{ /* likely */ }
4279	else
4280	{
4281	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4282	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4283	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4284	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4285	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4286	}
4287
4288	/* If this is a PTE, we're at the final level and we're done. */
4289	uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
4290	if (uNextLevel == 0)
4291	{
4292	/* The page size of the translation is the default (4K). */
4293	pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4294	pWalkResult->cShift = X86_PAGE_4K_SHIFT;
4295	pWalkResult->fIoPerm = fPtePerm;
4296	return VINF_SUCCESS;
4297	}
4298	if (uNextLevel == 7)
4299	{
4300	/* The default page size of the translation is overriden. */
4301	RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4302	uint8_t cShift = X86_PAGE_4K_SHIFT;
4303	while (GCPhysPte & RT_BIT_64(cShift++))
4304	;
4305
4306	/* The page size must be larger than the default size and lower than the default size of the higher level. */
4307	Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
4308	if ( cShift > s_acIovaLevelShifts[uLevel]
4309	&& cShift < s_acIovaLevelShifts[uLevel + 1])
4310	{
4311	pWalkResult->GCPhysSpa = GCPhysPte;
4312	pWalkResult->cShift = cShift;
4313	pWalkResult->fIoPerm = fPtePerm;
4314	return VINF_SUCCESS;
4315	}
4316
4317	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4318	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4319	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4320	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4321	kIoPageFaultType_PteInvalidPageSize);
4322	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4323	}
4324
4325	/* Validate the next level encoding of the PDE. */
4326	#if IOMMU_MAX_HOST_PT_LEVEL < 6
4327	if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4328	{ /* likely */ }
4329	else
4330	{
4331	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4332	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4333	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4334	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4335	kIoPageFaultType_PteInvalidLvlEncoding);
4336	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4337	}
4338	#else
4339	Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4340	#endif
4341
4342	/* Validate level transition. */
4343	if (uNextLevel < uLevel)
4344	{ /* likely */ }
4345	else
4346	{
4347	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4348	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4349	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4350	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4351	kIoPageFaultType_PteInvalidLvlEncoding);
4352	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4353	}
4354
4355	/* Ensure IOVA bits of skipped levels are zero. */
4356	Assert(uLevel > 0);
4357	uint64_t uIovaSkipMask = 0;
4358	for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
4359	uIovaSkipMask \|= s_auIovaLevelMasks[idxLevel];
4360	if (!(uIova & uIovaSkipMask))
4361	{ /* likely */ }
4362	else
4363	{
4364	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4365	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4366	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4367	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4368	kIoPageFaultType_SkippedLevelIovaNotZero);
4369	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4370	}
4371
4372	/* Continue with traversing the page directory at this level. */
4373	}
4374
4375	/* Shouldn't really get here. */
4376	return VERR_IOMMU_IPE_3;
4377	}
4378
4379
4380	/**
4381	* Looks up an I/O virtual address from the device table.
4382	*
4383	* @returns VBox status code.
4384	* @param pDevIns The IOMMU instance data.
4385	* @param uDevId The device ID.
4386	* @param uIova The I/O virtual address to lookup.
4387	* @param cbAccess The size of the access.
4388	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4389	* permissions for the access being made.
4390	* @param enmOp The IOMMU operation being performed.
4391	* @param pGCPhysSpa Where to store the translated system physical address. Only
4392	* valid when translation succeeds and VINF_SUCCESS is
4393	* returned!
4394	*
4395	* @thread Any.
4396	*/
4397	static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
4398	IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
4399	{
4400	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4401
4402	/* Read the device table entry from memory. */
4403	DTE_T Dte;
4404	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4405	if (RT_SUCCESS(rc))
4406	{
4407	/* If the DTE is not valid, addresses are forwarded without translation */
4408	if (Dte.n.u1Valid)
4409	{ /* likely */ }
4410	else
4411	{
4412	/** @todo IOMMU: Add to IOLTB cache. */
4413	*pGCPhysSpa = uIova;
4414	return VINF_SUCCESS;
4415	}
4416
4417	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4418	uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4419	uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4420	if (RT_LIKELY( !fRsvd0
4421	&& !fRsvd1))
4422	{ /* likely */ }
4423	else
4424	{
4425	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4426	EVT_ILLEGAL_DTE_T Event;
4427	iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4428	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4429	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4430	}
4431
4432	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
4433	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
4434	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
4435	{ /* likely */ }
4436	else
4437	{
4438	/** @todo IOMMU: Add to IOLTB cache. */
4439	*pGCPhysSpa = uIova;
4440	return VINF_SUCCESS;
4441	}
4442
4443	/** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
4444	* below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
4445
4446	uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
4447	uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
4448	uint64_t cbRemaining = cbAccess;
4449	for (;;)
4450	{
4451	/* Walk the I/O page tables to translate the IOVA and check permission for the access. */
4452	IOWALKRESULT WalkResult;
4453	rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
4454	if (RT_SUCCESS(rc))
4455	{
4456	/** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
4457
4458	/* Store the translated base address before continuing to check permissions for any more pages. */
4459	if (cbRemaining == cbAccess)
4460	{
4461	RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
4462	*pGCPhysSpa = WalkResult.GCPhysSpa \| offSpa;
4463	}
4464
4465	uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
4466	if (cbRemaining > cbPhysPage - offIova)
4467	{
4468	cbRemaining -= (cbPhysPage - offIova);
4469	uBaseIova += cbPhysPage;
4470	offIova = 0;
4471	}
4472	else
4473	break;
4474	}
4475	else
4476	{
4477	Log((IOMMU_LOG_PFX ": I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
4478	uBaseIova, fAccess, rc));
4479	*pGCPhysSpa = NIL_RTGCPHYS;
4480	return rc;
4481	}
4482	}
4483
4484	return rc;
4485	}
4486
4487	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4488	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4489	}
4490
4491
4492	/**
4493	* Memory read request from a device.
4494	*
4495	* @returns VBox status code.
4496	* @param pDevIns The IOMMU device instance.
4497	* @param uDevId The device ID (bus, device, function).
4498	* @param uIova The I/O virtual address being read.
4499	* @param cbRead The number of bytes being read.
4500	* @param pGCPhysSpa Where to store the translated system physical address.
4501	*
4502	* @thread Any.
4503	*/
4504	static int iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, PRTGCPHYS pGCPhysSpa)
4505	{
4506	/* Validate. */
4507	Assert(pDevIns);
4508	Assert(pGCPhysSpa);
4509	Assert(cbRead > 0);
4510
4511	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4512
4513	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4514	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4515	if (Ctrl.n.u1IommuEn)
4516	{
4517	/** @todo IOMMU: IOTLB cache lookup. */
4518
4519	/* Lookup the IOVA from the device table. */
4520	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
4521	}
4522
4523	*pGCPhysSpa = uIova;
4524	return VINF_SUCCESS;
4525	}
4526
4527
4528	/**
4529	* Memory write request from a device.
4530	*
4531	* @returns VBox status code.
4532	* @param pDevIns The IOMMU device instance.
4533	* @param uDevId The device ID (bus, device, function).
4534	* @param uIova The I/O virtual address being written.
4535	* @param cbWrite The number of bytes being written.
4536	* @param pGCPhysSpa Where to store the translated physical address.
4537	*
4538	* @thread Any.
4539	*/
4540	static int iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite, PRTGCPHYS pGCPhysSpa)
4541	{
4542	/* Validate. */
4543	Assert(pDevIns);
4544	Assert(pGCPhysSpa);
4545	Assert(cbWrite > 0);
4546
4547	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4548
4549	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4550	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4551	if (Ctrl.n.u1IommuEn)
4552	{
4553	/** @todo IOMMU: IOTLB cache lookup. */
4554
4555	/* Lookup the IOVA from the device table. */
4556	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
4557	}
4558
4559	*pGCPhysSpa = uIova;
4560	return VINF_SUCCESS;
4561	}
4562
4563
4564	/**
4565	* Interrupt remap request from a device.
4566	*
4567	* @returns VBox status code.
4568	* @param pDevIns The IOMMU device instance.
4569	* @param uDevId The device ID (bus, device, function).
4570	* @param GCPhysIn The source MSI address.
4571	* @param uDataIn The source MSI data.
4572	* @param pGCPhysOut Where to store the remapped MSI address.
4573	* @param puDataOut Where to store the remapped MSI data.
4574	*/
4575	static int iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4576	PRTGCPHYS pGCPhysOut, uint32_t *puDataOut)
4577	{
4578	/* Validate. */
4579	Assert(pDevIns);
4580	Assert(pGCPhysOut);
4581	Assert(puDataOut);
4582
4583	/* Remove later. */
4584	RT_NOREF(uDevId, GCPhysIn, uDataIn, pGCPhysOut, puDataOut);
4585
4586	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4587
4588	/* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4589	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4590	if (Ctrl.n.u1IommuEn)
4591	{
4592	/** @todo IOMMU: iommuAmdLookupIntrTable. */
4593	}
4594
4595	*pGCPhysOut = GCPhysIn;
4596	*puDataOut = uDataIn;
4597	return VINF_SUCCESS;
4598	}
4599
4600
4601	/**
4602	* @callback_method_impl{FNIOMMMIONEWWRITE}
4603	*/
4604	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
4605	{
4606	NOREF(pvUser);
4607	Assert(cb == 4 \|\| cb == 8);
4608	Assert(!(off & (cb - 1)));
4609
4610	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
4611	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
4612	}
4613
4614
4615	/**
4616	* @callback_method_impl{FNIOMMMIONEWREAD}
4617	*/
4618	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
4619	{
4620	NOREF(pvUser);
4621	Assert(cb == 4 \|\| cb == 8);
4622	Assert(!(off & (cb - 1)));
4623
4624	uint64_t uResult;
4625	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
4626	if (cb == 8)
4627	(uint64_t )pv = uResult;
4628	else
4629	(uint32_t )pv = (uint32_t)uResult;
4630
4631	return rcStrict;
4632	}
4633
4634	# ifdef IN_RING3
4635
4636	/**
4637	* Processes an IOMMU command.
4638	*
4639	* @returns VBox status code.
4640	* @param pDevIns The IOMMU device instance.
4641	* @param pCmd The command to process.
4642	* @param GCPhysCmd The system physical address of the command.
4643	* @param pEvtError Where to store the error event in case of failures.
4644	*
4645	* @thread Command thread.
4646	*/
4647	static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4648	{
4649	IOMMU_ASSERT_NOT_LOCKED(pDevIns);
4650
4651	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4652	uint8_t const bCmd = pCmd->n.u4Opcode;
4653	switch (bCmd)
4654	{
4655	case IOMMU_CMD_COMPLETION_WAIT:
4656	{
4657	PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4658	AssertCompile(sizeof(pCmdComWait) == sizeof(pCmd));
4659
4660	/* Validate reserved bits in the command. */
4661	if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4662	{
4663	/* If Completion Store is requested, write the StoreData to the specified address.*/
4664	if (pCmdComWait->n.u1Store)
4665	{
4666	RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4667	uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4668	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4669	if (RT_FAILURE(rc))
4670	{
4671	Log((IOMMU_LOG_PFX ": Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4672	GCPhysStore, rc));
4673	iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4674	return VERR_IOMMU_CMD_HW_ERROR;
4675	}
4676	}
4677
4678	/* If command completion interrupt is requested, raise an interrupt. */
4679	if (pCmdComWait->n.u1Interrupt)
4680	{
4681	IOMMU_LOCK(pDevIns);
4682	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4683	if (Ctrl.n.u1CompWaitIntrEn)
4684	{
4685	/* Indicate that this command completed. */
4686	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4687
4688	/* Check and signal an interrupt if software wants to receive one when this command completes. */
4689	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4690	if (Ctrl.n.u1CompWaitIntrEn)
4691	iommuAmdRaiseMsiInterrupt(pDevIns);
4692	}
4693	IOMMU_UNLOCK(pDevIns);
4694	}
4695	return VINF_SUCCESS;
4696	}
4697	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4698	return VERR_IOMMU_CMD_INVALID_FORMAT;
4699	}
4700
4701	case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4702	{
4703	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4704	* then. */
4705	return VINF_SUCCESS;
4706	}
4707
4708	case IOMMU_CMD_INV_IOMMU_PAGES:
4709	{
4710	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4711	* then. */
4712	return VINF_SUCCESS;
4713	}
4714
4715	case IOMMU_CMD_INV_IOTLB_PAGES:
4716	{
4717	uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4718	if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4719	{
4720	/** @todo IOMMU: Implement remote IOTLB invalidation. */
4721	return VERR_NOT_IMPLEMENTED;
4722	}
4723	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4724	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4725	}
4726
4727	case IOMMU_CMD_INV_INTR_TABLE:
4728	{
4729	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4730	* then. */
4731	return VINF_SUCCESS;
4732	}
4733
4734	case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4735	{
4736	if (pThis->ExtFeat.n.u1PrefetchSup)
4737	{
4738	/** @todo IOMMU: Implement prefetch. Pretend success until then. */
4739	return VINF_SUCCESS;
4740	}
4741	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4742	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4743	}
4744
4745	case IOMMU_CMD_COMPLETE_PPR_REQ:
4746	{
4747	/* We don't support PPR requests yet. */
4748	Assert(!pThis->ExtFeat.n.u1PprSup);
4749	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4750	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4751	}
4752
4753	case IOMMU_CMD_INV_IOMMU_ALL:
4754	{
4755	if (pThis->ExtFeat.n.u1InvAllSup)
4756	{
4757	/** @todo IOMMU: Invalidate all. Pretend success until then. */
4758	return VINF_SUCCESS;
4759	}
4760	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4761	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4762	}
4763	}
4764
4765	Log((IOMMU_LOG_PFX ": Cmd(%#x): Unrecognized\n", bCmd));
4766	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4767	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4768	}
4769
4770
4771	/**
4772	* The IOMMU command thread.
4773	*
4774	* @returns VBox status code.
4775	* @param pDevIns The IOMMU device instance.
4776	* @param pThread The command thread.
4777	*/
4778	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4779	{
4780	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4781
4782	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4783	return VINF_SUCCESS;
4784
4785	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4786	{
4787	/*
4788	* Sleep perpetually until we are woken up to process commands.
4789	*/
4790	{
4791	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
4792	bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
4793	if (!fSignaled)
4794	{
4795	Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
4796	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
4797	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4798	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4799	break;
4800	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4801	ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
4802	}
4803	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
4804	}
4805
4806	/*
4807	* Fetch and process IOMMU commands.
4808	*/
4809	/** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
4810	* at a time) and is expensive due to calls to PGM for fetching guest memory.
4811	* We could optimize by fetching a bunch of commands at a time reducing
4812	* number of calls to PGM. In the longer run we could lock the memory and
4813	* mappings and accessing them directly. */
4814	IOMMU_LOCK(pDevIns);
4815
4816	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
4817	if (Status.n.u1CmdBufRunning)
4818	{
4819	/* Get the offset we need to read the command from memory (circular buffer offset). */
4820	uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
4821	uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
4822	Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
4823	Assert(offHead < cbCmdBuf);
4824	while (offHead != pThis->CmdBufTailPtr.n.off)
4825	{
4826	/* Read the command from memory. */
4827	CMD_GENERIC_T Cmd;
4828	RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
4829	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
4830	if (RT_SUCCESS(rc))
4831	{
4832	/* Increment the command buffer head pointer. */
4833	offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
4834	pThis->CmdBufHeadPtr.n.off = offHead;
4835
4836	/* Process the fetched command. */
4837	EVT_GENERIC_T EvtError;
4838	IOMMU_UNLOCK(pDevIns);
4839	rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
4840	IOMMU_LOCK(pDevIns);
4841	if (RT_FAILURE(rc))
4842	{
4843	if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
4844	\|\| rc == VERR_IOMMU_CMD_INVALID_FORMAT)
4845	{
4846	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
4847	iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
4848	}
4849	else if (rc == VERR_IOMMU_CMD_HW_ERROR)
4850	{
4851	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
4852	iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
4853	}
4854	break;
4855	}
4856	}
4857	else
4858	{
4859	EVT_CMD_HW_ERR_T EvtCmdHwErr;
4860	iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
4861	iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
4862	break;
4863	}
4864	}
4865	}
4866
4867	IOMMU_UNLOCK(pDevIns);
4868	}
4869
4870	LogFlow((IOMMU_LOG_PFX ": Command thread terminating\n"));
4871	return VINF_SUCCESS;
4872	}
4873
4874
4875	/**
4876	* Wakes up the command thread so it can respond to a state change.
4877	*
4878	* @returns VBox status code.
4879	* @param pDevIns The IOMMU device instance.
4880	* @param pThread The command thread.
4881	*/
4882	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4883	{
4884	RT_NOREF(pThread);
4885
4886	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4887	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
4888	}
4889
4890
4891	/**
4892	* @callback_method_impl{FNPCICONFIGREAD}
4893	*/
4894	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4895	unsigned cb, uint32_t *pu32Value)
4896	{
4897	/** @todo IOMMU: PCI config read stat counter. */
4898	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4899	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
4900	VBOXSTRICTRC_VAL(rcStrict)));
4901	return rcStrict;
4902	}
4903
4904
4905	/**
4906	* @callback_method_impl{FNPCICONFIGWRITE}
4907	*/
4908	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4909	unsigned cb, uint32_t u32Value)
4910	{
4911	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4912
4913	/*
4914	* Discard writes to read-only registers that are specific to the IOMMU.
4915	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
4916	* See PCI spec. 6.1. "Configuration Space Organization".
4917	*/
4918	switch (uAddress)
4919	{
4920	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
4921	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
4922	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
4923	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
4924	{
4925	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
4926	return VINF_SUCCESS;
4927	}
4928	}
4929
4930	IOMMU_LOCK(pDevIns);
4931
4932	VBOXSTRICTRC rcStrict;
4933	switch (uAddress)
4934	{
4935	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
4936	{
4937	if (pThis->IommuBar.n.u1Enable)
4938	{
4939	rcStrict = VINF_SUCCESS;
4940	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
4941	break;
4942	}
4943
4944	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
4945	if (pThis->IommuBar.n.u1Enable)
4946	{
4947	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
4948	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
4949	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
4950	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
4951	if (RT_FAILURE(rcStrict))
4952	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
4953	}
4954	break;
4955	}
4956
4957	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
4958	{
4959	if (!pThis->IommuBar.n.u1Enable)
4960	pThis->IommuBar.au32[1] = u32Value;
4961	else
4962	{
4963	rcStrict = VINF_SUCCESS;
4964	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
4965	}
4966	break;
4967	}
4968
4969	case IOMMU_PCI_OFF_MSI_CAP_HDR:
4970	{
4971	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
4972	RT_FALL_THRU();
4973	}
4974	default:
4975	{
4976	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4977	break;
4978	}
4979	}
4980
4981	IOMMU_UNLOCK(pDevIns);
4982
4983	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
4984	return rcStrict;
4985	}
4986
4987
4988	/**
4989	* @callback_method_impl{FNDBGFHANDLERDEV}
4990	*/
4991	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4992	{
4993	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4994	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4995	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4996
4997	LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
4998	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
4999
5000	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5001	/* Device Table Base Addresses (all segments). */
5002	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5003	{
5004	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5005	pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
5006	if (fVerbose)
5007	{
5008	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5009	IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
5010	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5011	}
5012	}
5013	/* Command Buffer Base Address Register. */
5014	{
5015	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5016	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5017	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5018	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5019	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
5020	if (fVerbose)
5021	{
5022	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5023	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5024	cEntries, cbBuffer);
5025	}
5026	}
5027	/* Event Log Base Address Register. */
5028	{
5029	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5030	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5031	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5032	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5033	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
5034	if (fVerbose)
5035	{
5036	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5037	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5038	cEntries, cbBuffer);
5039	}
5040	}
5041	/* IOMMU Control Register. */
5042	{
5043	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5044	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5045	if (fVerbose)
5046	{
5047	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5048	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5049	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5050	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5051	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5052	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5053	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5054	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5055	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5056	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5057	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5058	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5059	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5060	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5061	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5062	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5063	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5064	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5065	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5066	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5067	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5068	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5069	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5070	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5071	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5072	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5073	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5074	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5075	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5076	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5077	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5078	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5079	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5080	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5081	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5082	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5083	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5084	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5085	}
5086	}
5087	/* Exclusion Base Address Register. */
5088	{
5089	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5090	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5091	if (fVerbose)
5092	{
5093	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5094	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5095	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5096	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5097	}
5098	}
5099	/* Exclusion Range Limit Register. */
5100	{
5101	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5102	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5103	if (fVerbose)
5104	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
5105	}
5106	/* Extended Feature Register. */
5107	{
5108	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5109	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5110	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5111	if (fVerbose)
5112	{
5113	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5114	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5115	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5116	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5117	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5118	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5119	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5120	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5121	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5122	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5123	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5124	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5125	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5126	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5127	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5128	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5129	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5130	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5131	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5132	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5133	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5134	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5135	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5136	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5137	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5138	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5139	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5140	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5141	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5142	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5143	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5144	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5145	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5146	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5147	}
5148	}
5149	/* PPR Log Base Address Register. */
5150	{
5151	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5152	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5153	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5154	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5155	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5156	if (fVerbose)
5157	{
5158	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5159	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5160	cEntries, cbBuffer);
5161	}
5162	}
5163	/* Hardware Event (Hi) Register. */
5164	{
5165	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5166	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5167	if (fVerbose)
5168	{
5169	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5170	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5171	}
5172	}
5173	/* Hardware Event (Lo) Register. */
5174	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5175	/* Hardware Event Status. */
5176	{
5177	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5178	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5179	if (fVerbose)
5180	{
5181	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5182	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5183	}
5184	}
5185	/* Guest Virtual-APIC Log Base Address Register. */
5186	{
5187	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5188	uint8_t const uEncodedLen = GALogBar.n.u4Len;
5189	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5190	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5191	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5192	if (fVerbose)
5193	{
5194	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5195	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5196	cEntries, cbBuffer);
5197	}
5198	}
5199	/* Guest Virtual-APIC Log Tail Address Register. */
5200	{
5201	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5202	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5203	if (fVerbose)
5204	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5205	}
5206	/* PPR Log B Base Address Register. */
5207	{
5208	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5209	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5210	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5211	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5212	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5213	if (fVerbose)
5214	{
5215	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5216	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5217	cEntries, cbBuffer);
5218	}
5219	}
5220	/* Event Log B Base Address Register. */
5221	{
5222	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5223	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5224	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5225	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5226	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5227	if (fVerbose)
5228	{
5229	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5230	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5231	cEntries, cbBuffer);
5232	}
5233	}
5234	/* Device-Specific Feature Extension Register. */
5235	{
5236	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5237	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5238	if (fVerbose)
5239	{
5240	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5241	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5242	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5243	}
5244	}
5245	/* Device-Specific Control Extension Register. */
5246	{
5247	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5248	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5249	if (fVerbose)
5250	{
5251	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5252	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5253	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5254	}
5255	}
5256	/* Device-Specific Status Extension Register. */
5257	{
5258	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5259	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
5260	if (fVerbose)
5261	{
5262	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5263	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5264	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5265	}
5266	}
5267	/* MSI Miscellaneous Information Register (Lo and Hi). */
5268	{
5269	MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo;
5270	pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64);
5271	if (fVerbose)
5272	{
5273	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog);
5274	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize);
5275	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize);
5276	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize);
5277	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv);
5278	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr);
5279	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa);
5280	}
5281	}
5282	/* MSI Capability Header. */
5283	{
5284	MSI_CAP_HDR_T MsiCapHdr;
5285	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5286	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5287	if (fVerbose)
5288	{
5289	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5290	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5291	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5292	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5293	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5294	}
5295	}
5296	/* MSI Address Register (Lo and Hi). */
5297	{
5298	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5299	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5300	MSI_ADDR_T MsiAddr;
5301	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5302	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5303	if (fVerbose)
5304	{
5305	pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5306	pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5307	pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5308	pHlp->pfnPrintf(pHlp, " Address = %#Rx32\n", MsiAddr.n.u12Addr);
5309	pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#Rx32\n", MsiAddr.n.u32Rsvd0);
5310	}
5311	}
5312	/* MSI Data. */
5313	{
5314	MSI_DATA_T MsiData;
5315	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5316	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5317	if (fVerbose)
5318	{
5319	pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5320	MsiData.n.u8Vector);
5321	pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5322	pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5323	pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5324	"level" : "edge");
5325	}
5326	}
5327	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5328	{
5329	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5330	MsiMapCapHdr.u32 = 0;
5331	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5332	if (fVerbose)
5333	{
5334	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5335	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5336	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5337	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5338	}
5339	}
5340	/* Performance Optimization Control Register. */
5341	{
5342	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5343	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5344	if (fVerbose)
5345	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5346	}
5347	/* XT (x2APIC) General Interrupt Control Register. */
5348	{
5349	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5350	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5351	if (fVerbose)
5352	{
5353	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5354	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5355	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5356	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5357	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5358	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5359	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5360	}
5361	}
5362	/* XT (x2APIC) PPR Interrupt Control Register. */
5363	{
5364	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5365	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5366	if (fVerbose)
5367	{
5368	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5369	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5370	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5371	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5372	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5373	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5374	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5375	}
5376	}
5377	/* XT (X2APIC) GA Log Interrupt Control Register. */
5378	{
5379	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5380	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5381	if (fVerbose)
5382	{
5383	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5384	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5385	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5386	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5387	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5388	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5389	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5390	}
5391	}
5392	/* MARC Registers. */
5393	{
5394	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5395	{
5396	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5397	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5398	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5399
5400	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5401	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5402	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5403	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5404
5405	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5406	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5407	}
5408	}
5409	/* Reserved Register. */
5410	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5411	/* Command Buffer Head Pointer Register. */
5412	{
5413	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5414	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
5415	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
5416	}
5417	/* Command Buffer Tail Pointer Register. */
5418	{
5419	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5420	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
5421	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
5422	}
5423	/* Event Log Head Pointer Register. */
5424	{
5425	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5426	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
5427	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
5428	}
5429	/* Event Log Tail Pointer Register. */
5430	{
5431	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5432	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
5433	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
5434	}
5435	/* Status Register. */
5436	{
5437	IOMMU_STATUS_T const Status = pThis->Status;
5438	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5439	if (fVerbose)
5440	{
5441	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5442	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5443	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5444	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5445	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5446	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5447	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5448	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5449	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5450	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5451	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5452	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5453	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5454	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5455	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5456	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5457	}
5458	}
5459	/* PPR Log Head Pointer. */
5460	{
5461	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5462	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
5463	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
5464	}
5465	/* PPR Log Tail Pointer. */
5466	{
5467	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5468	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
5469	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
5470	}
5471	/* Guest Virtual-APIC Log Head Pointer. */
5472	{
5473	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5474	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
5475	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
5476	}
5477	/* Guest Virtual-APIC Log Tail Pointer. */
5478	{
5479	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5480	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
5481	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
5482	}
5483	/* PPR Log B Head Pointer. */
5484	{
5485	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5486	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
5487	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
5488	}
5489	/* PPR Log B Tail Pointer. */
5490	{
5491	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5492	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
5493	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
5494	}
5495	/* Event Log B Head Pointer. */
5496	{
5497	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5498	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
5499	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
5500	}
5501	/* Event Log B Tail Pointer. */
5502	{
5503	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5504	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
5505	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
5506	}
5507	/* PPR Log Auto Response Register. */
5508	{
5509	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5510	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5511	if (fVerbose)
5512	{
5513	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5514	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5515	}
5516	}
5517	/* PPR Log Overflow Early Warning Indicator Register. */
5518	{
5519	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5520	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5521	if (fVerbose)
5522	{
5523	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5524	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5525	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5526	}
5527	}
5528	/* PPR Log Overflow Early Warning Indicator Register. */
5529	{
5530	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5531	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5532	if (fVerbose)
5533	{
5534	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5535	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5536	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5537	}
5538	}
5539	}
5540
5541
5542	/**
5543	* @callback_method_impl{FNSSMDEVSAVEEXEC}
5544	*/
5545	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5546	{
5547	/** @todo IOMMU: Save state. */
5548	RT_NOREF2(pDevIns, pSSM);
5549	return VERR_NOT_IMPLEMENTED;
5550	}
5551
5552
5553	/**
5554	* @callback_method_impl{FNSSMDEVLOADEXEC}
5555	*/
5556	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5557	{
5558	/** @todo IOMMU: Load state. */
5559	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
5560	return VERR_NOT_IMPLEMENTED;
5561	}
5562
5563
5564	/**
5565	* @interface_method_impl{PDMDEVREG,pfnReset}
5566	*/
5567	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
5568	{
5569	/*
5570	* Resets read-write portion of the IOMMU state.
5571	*
5572	* State data not initialized here is expected to be initialized during
5573	* device construction and remain read-only through the lifetime of the VM.
5574	*/
5575	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5576	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5577	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5578
5579	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
5580
5581	pThis->CmdBufBaseAddr.u64 = 0;
5582	pThis->CmdBufBaseAddr.n.u4Len = 8;
5583
5584	pThis->EvtLogBaseAddr.u64 = 0;
5585	pThis->EvtLogBaseAddr.n.u4Len = 8;
5586
5587	pThis->Ctrl.u64 = 0;
5588
5589	pThis->ExclRangeBaseAddr.u64 = 0;
5590	pThis->ExclRangeLimit.u64 = 0;
5591
5592	pThis->PprLogBaseAddr.u64 = 0;
5593	pThis->PprLogBaseAddr.n.u4Len = 8;
5594
5595	pThis->HwEvtHi.u64 = 0;
5596	pThis->HwEvtLo = 0;
5597	pThis->HwEvtStatus.u64 = 0;
5598
5599	pThis->GALogBaseAddr.u64 = 0;
5600	pThis->GALogBaseAddr.n.u4Len = 8;
5601	pThis->GALogTailAddr.u64 = 0;
5602
5603	pThis->PprLogBBaseAddr.u64 = 0;
5604	pThis->PprLogBBaseAddr.n.u4Len = 8;
5605
5606	pThis->EvtLogBBaseAddr.u64 = 0;
5607	pThis->EvtLogBBaseAddr.n.u4Len = 8;
5608
5609	pThis->MsiMiscInfo.u64 = 0;
5610	pThis->PerfOptCtrl.u32 = 0;
5611
5612	pThis->XtGenIntrCtrl.u64 = 0;
5613	pThis->XtPprIntrCtrl.u64 = 0;
5614	pThis->XtGALogIntrCtrl.u64 = 0;
5615
5616	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
5617
5618	pThis->CmdBufHeadPtr.u64 = 0;
5619	pThis->CmdBufTailPtr.u64 = 0;
5620	pThis->EvtLogHeadPtr.u64 = 0;
5621	pThis->EvtLogTailPtr.u64 = 0;
5622
5623	pThis->Status.u64 = 0;
5624
5625	pThis->PprLogHeadPtr.u64 = 0;
5626	pThis->PprLogTailPtr.u64 = 0;
5627
5628	pThis->GALogHeadPtr.u64 = 0;
5629	pThis->GALogTailPtr.u64 = 0;
5630
5631	pThis->PprLogBHeadPtr.u64 = 0;
5632	pThis->PprLogBTailPtr.u64 = 0;
5633
5634	pThis->EvtLogBHeadPtr.u64 = 0;
5635	pThis->EvtLogBTailPtr.u64 = 0;
5636
5637	pThis->PprLogAutoResp.u64 = 0;
5638	pThis->PprLogOverflowEarly.u64 = 0;
5639	pThis->PprLogBOverflowEarly.u64 = 0;
5640
5641	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
5642	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
5643	}
5644
5645
5646	/**
5647	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5648	*/
5649	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
5650	{
5651	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5652	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5653	LogFlowFunc(("\n"));
5654
5655	/* Close the command thread semaphore. */
5656	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
5657	{
5658	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
5659	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
5660	}
5661	return VINF_SUCCESS;
5662	}
5663
5664
5665	/**
5666	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5667	*/
5668	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5669	{
5670	NOREF(iInstance);
5671
5672	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5673	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5674	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5675	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5676	int rc;
5677	LogFlowFunc(("\n"));
5678
5679	pThisCC->pDevInsR3 = pDevIns;
5680
5681	/*
5682	* Validate and read the configuration.
5683	*/
5684	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Device\|Function", "");
5685
5686	uint8_t uPciDevice;
5687	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Device", &uPciDevice, 0);
5688	if (RT_FAILURE(rc))
5689	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Device\""));
5690
5691	uint8_t uPciFunction;
5692	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Function", &uPciFunction, 2);
5693	if (RT_FAILURE(rc))
5694	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Function\""));
5695
5696	/*
5697	* Register the IOMMU with PDM.
5698	*/
5699	PDMIOMMUREGR3 IommuReg;
5700	RT_ZERO(IommuReg);
5701	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5702	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5703	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5704	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5705	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5706	rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
5707	if (RT_FAILURE(rc))
5708	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
5709	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
5710	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5711	N_("IOMMU helper version mismatch; got %#x expected %#x"),
5712	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
5713	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
5714	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5715	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
5716	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
5717
5718	/*
5719	* Initialize read-only PCI configuration space.
5720	*/
5721	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5722	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5723
5724	/* Header. */
5725	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
5726	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
5727	PDMPciDevSetCommand(pPciDev, 0); /* Command */
5728	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
5729	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
5730	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
5731	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
5732	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
5733	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
5734	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
5735	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
5736	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
5737	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
5738	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
5739
5740	/* Capability Header. */
5741	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
5742	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
5743	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
5744	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
5745	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
5746	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
5747	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
5748	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
5749	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
5750	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
5751
5752	/* Base Address Low Register. */
5753	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
5754
5755	/* Base Address High Register. */
5756	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
5757
5758	/* IOMMU Range Register. */
5759	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
5760
5761	/* Misc. Information Register 0. */
5762	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0,
5763	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
5764	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
5765	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
5766	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
5767	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
5768	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
5769
5770	/* Misc. Information Register 1. */
5771	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, 0);
5772
5773	/* MSI Capability Header register. */
5774	PDMMSIREG MsiReg;
5775	RT_ZERO(MsiReg);
5776	MsiReg.cMsiVectors = 1;
5777	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
5778	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
5779	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
5780	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5781	AssertRCReturn(rc, rc);
5782
5783	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
5784	#if 0
5785	/* MSI Address Lo. */
5786	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
5787	/* MSI Address Hi. */
5788	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
5789	/* MSI Data. */
5790	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
5791	#endif
5792
5793	#if 0
5794	/** @todo IOMMU: I don't know if we need to support this, enable later if
5795	* required. */
5796	/* MSI Mapping Capability Header register. */
5797	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
5798	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
5799	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
5800	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
5801	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
5802	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
5803	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
5804	#endif
5805
5806	/*
5807	* Register the PCI function with PDM.
5808	*/
5809	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /* fFlags */, uPciDevice, uPciFunction, "amd-iommu");
5810	AssertLogRelRCReturn(rc, rc);
5811
5812	/*
5813	* Intercept PCI config. space accesses.
5814	*/
5815	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5816	AssertLogRelRCReturn(rc, rc);
5817
5818	/*
5819	* Create the MMIO region.
5820	* Mapping of the region is done when software configures it via PCI config space.
5821	*/
5822	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
5823	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
5824	"AMD-IOMMU", &pThis->hMmio);
5825	AssertLogRelRCReturn(rc, rc);
5826
5827	/*
5828	* Register saved state.
5829	*/
5830	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
5831	NULL, NULL, NULL,
5832	NULL, iommuAmdR3SaveExec, NULL,
5833	NULL, iommuAmdR3LoadExec, NULL);
5834	AssertLogRelRCReturn(rc, rc);
5835
5836	/*
5837	* Register debugger info item.
5838	*/
5839	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5840	AssertLogRelRCReturn(rc, rc);
5841
5842	/*
5843	* Create the command thread and its event semaphore.
5844	*/
5845	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5846	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
5847	AssertLogRelRCReturn(rc, rc);
5848
5849	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5850	AssertLogRelRCReturn(rc, rc);
5851
5852	/*
5853	* Initialize read-only registers.
5854	*/
5855	/** @todo Don't remove the =0 assignment for now. It's just there so it's easier
5856	* for me to see existing features that we might want to implement. Do it
5857	* later. */
5858	pThis->ExtFeat.u64 = 0;
5859	pThis->ExtFeat.n.u1PrefetchSup = 0;
5860	pThis->ExtFeat.n.u1PprSup = 0;
5861	pThis->ExtFeat.n.u1X2ApicSup = 0;
5862	pThis->ExtFeat.n.u1NoExecuteSup = 0;
5863	pThis->ExtFeat.n.u1GstTranslateSup = 0;
5864	pThis->ExtFeat.n.u1InvAllSup = 0;
5865	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5866	pThis->ExtFeat.n.u1HwErrorSup = 1;
5867	pThis->ExtFeat.n.u1PerfCounterSup = 0;
5868	pThis->ExtFeat.n.u2HostAddrTranslateSize = IOMMU_MAX_HOST_PT_LEVEL;
5869	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
5870	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
5871	pThis->ExtFeat.n.u2SmiFilterSup = 0;
5872	pThis->ExtFeat.n.u3SmiFilterCount = 0;
5873	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5874	pThis->ExtFeat.n.u2DualPprLogSup = 0;
5875	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5876	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
5877	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5878	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5879	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5880	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5881	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5882	pThis->ExtFeat.n.u2MarcSup = 0;
5883	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5884	pThis->ExtFeat.n.u1PerfOptSup = 0;
5885	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5886	pThis->ExtFeat.n.u1GstIoSup = 0;
5887	pThis->ExtFeat.n.u1HostAccessSup = 0;
5888	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5889	pThis->ExtFeat.n.u1AttrForwardSup = 0;
5890	pThis->ExtFeat.n.u1HostDirtySup = 0;
5891	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5892	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5893	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5894
5895	pThis->RsvdReg = 0;
5896
5897	pThis->DevSpecificFeat.u64 = 0;
5898	pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
5899	pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
5900
5901	pThis->DevSpecificCtrl.u64 = 0;
5902	pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
5903	pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
5904
5905	pThis->DevSpecificStatus.u64 = 0;
5906	pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
5907	pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
5908
5909	/*
5910	* Initialize parts of the IOMMU state as it would during reset.
5911	* Must be called -after- initializing PCI config. space registers.
5912	*/
5913	iommuAmdR3Reset(pDevIns);
5914
5915	return VINF_SUCCESS;
5916	}
5917
5918	# else /* !IN_RING3 */
5919
5920	/**
5921	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5922	*/
5923	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5924	{
5925	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5926	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5927	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5928
5929	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5930
5931	/* Set up the MMIO RZ handlers. */
5932	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5933	AssertRCReturn(rc, rc);
5934
5935	/* Set up the IOMMU RZ callbacks. */
5936	PDMIOMMUREGCC IommuReg;
5937	RT_ZERO(IommuReg);
5938	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5939	IommuReg.idxIommu = pThis->idxIommu;
5940	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5941	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5942	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5943	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5944	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5945	AssertRCReturn(rc, rc);
5946
5947	return VINF_SUCCESS;
5948	}
5949
5950	# endif /* !IN_RING3 */
5951
5952	/**
5953	* The device registration structure.
5954	*/
5955	const PDMDEVREG g_DeviceIommuAmd =
5956	{
5957	/* .u32Version = */ PDM_DEVREG_VERSION,
5958	/* .uReserved0 = */ 0,
5959	/* .szName = */ "iommu-amd",
5960	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
5961	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
5962	/* .cMaxInstances = */ ~0U,
5963	/* .uSharedVersion = */ 42,
5964	/* .cbInstanceShared = */ sizeof(IOMMU),
5965	/* .cbInstanceCC = */ sizeof(IOMMUCC),
5966	/* .cbInstanceRC = */ sizeof(IOMMURC),
5967	/* .cMaxPciDevices = */ 1,
5968	/* .cMaxMsixVectors = */ 0,
5969	/* .pszDescription = */ "IOMMU (AMD)",
5970	#if defined(IN_RING3)
5971	/* .pszRCMod = */ "VBoxDDRC.rc",
5972	/* .pszR0Mod = */ "VBoxDDR0.r0",
5973	/* .pfnConstruct = */ iommuAmdR3Construct,
5974	/* .pfnDestruct = */ iommuAmdR3Destruct,
5975	/* .pfnRelocate = */ NULL,
5976	/* .pfnMemSetup = */ NULL,
5977	/* .pfnPowerOn = */ NULL,
5978	/* .pfnReset = */ iommuAmdR3Reset,
5979	/* .pfnSuspend = */ NULL,
5980	/* .pfnResume = */ NULL,
5981	/* .pfnAttach = */ NULL,
5982	/* .pfnDetach = */ NULL,
5983	/* .pfnQueryInterface = */ NULL,
5984	/* .pfnInitComplete = */ NULL,
5985	/* .pfnPowerOff = */ NULL,
5986	/* .pfnSoftReset = */ NULL,
5987	/* .pfnReserved0 = */ NULL,
5988	/* .pfnReserved1 = */ NULL,
5989	/* .pfnReserved2 = */ NULL,
5990	/* .pfnReserved3 = */ NULL,
5991	/* .pfnReserved4 = */ NULL,
5992	/* .pfnReserved5 = */ NULL,
5993	/* .pfnReserved6 = */ NULL,
5994	/* .pfnReserved7 = */ NULL,
5995	#elif defined(IN_RING0)
5996	/* .pfnEarlyConstruct = */ NULL,
5997	/* .pfnConstruct = */ iommuAmdRZConstruct,
5998	/* .pfnDestruct = */ NULL,
5999	/* .pfnFinalDestruct = */ NULL,
6000	/* .pfnRequest = */ NULL,
6001	/* .pfnReserved0 = */ NULL,
6002	/* .pfnReserved1 = */ NULL,
6003	/* .pfnReserved2 = */ NULL,
6004	/* .pfnReserved3 = */ NULL,
6005	/* .pfnReserved4 = */ NULL,
6006	/* .pfnReserved5 = */ NULL,
6007	/* .pfnReserved6 = */ NULL,
6008	/* .pfnReserved7 = */ NULL,
6009	#elif defined(IN_RC)
6010	/* .pfnConstruct = */ iommuAmdRZConstruct,
6011	/* .pfnReserved0 = */ NULL,
6012	/* .pfnReserved1 = */ NULL,
6013	/* .pfnReserved2 = */ NULL,
6014	/* .pfnReserved3 = */ NULL,
6015	/* .pfnReserved4 = */ NULL,
6016	/* .pfnReserved5 = */ NULL,
6017	/* .pfnReserved6 = */ NULL,
6018	/* .pfnReserved7 = */ NULL,
6019	#else
6020	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
6021	#endif
6022	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
6023	};
6024
6025	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
6026

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 84509

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