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source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 44633

最後變更 在這個檔案從44633是 44633,由 vboxsync 提交於 12 年 前

DevIchIntelHDA.cpp: Cleanups.
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1/* $Id: DevIchIntelHDA.cpp 44633 2013-02-11 15:09:46Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/version.h>
24
25#include <iprt/assert.h>
26#include <iprt/uuid.h>
27#include <iprt/string.h>
28#include <iprt/mem.h>
29#include <iprt/asm.h>
30#include <iprt/asm-math.h>
31
32#include "VBoxDD.h"
33
34extern "C" {
35#include "audio.h"
36}
37#include "DevCodec.h"
38
39
40/*******************************************************************************
41* Defined Constants And Macros *
42*******************************************************************************/
43//#define HDA_AS_PCI_EXPRESS
44#define VBOX_WITH_INTEL_HDA
45
46#if defined(VBOX_WITH_HP_HDA)
47/* HP Pavilion dv4t-1300 */
48# define HDA_PCI_VENDOR_ID 0x103c
49# define HDA_PCI_DEICE_ID 0x30f7
50#elif defined(VBOX_WITH_INTEL_HDA)
51/* Intel HDA controller */
52# define HDA_PCI_VENDOR_ID 0x8086
53# define HDA_PCI_DEICE_ID 0x2668
54#elif defined(VBOX_WITH_NVIDIA_HDA)
55/* nVidia HDA controller */
56# define HDA_PCI_VENDOR_ID 0x10de
57# define HDA_PCI_DEICE_ID 0x0ac0
58#else
59# error "Please specify your HDA device vendor/device IDs"
60#endif
61
62#define HDA_NREGS 112
63/* Registers */
64#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
65#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
66#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
67#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
68#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
69#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
70#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
71#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
72#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
73#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
74
75#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
76#define GCAP(pState) (HDA_REG((pState), GCAP))
77/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
78 * oss (15:12) - number of output streams supported
79 * iss (11:8) - number of input streams supported
80 * bss (7:3) - number of bidirectional streams supported
81 * bds (2:1) - number of serial data out signals supported
82 * b64sup (0) - 64 bit addressing supported.
83 */
84#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
85 ( (((oss) & 0xF) << 12) \
86 | (((iss) & 0xF) << 8) \
87 | (((bss) & 0x1F) << 3) \
88 | (((bds) & 0x3) << 2) \
89 | ((b64sup) & 1))
90#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
91#define VMIN(pState) (HDA_REG((pState), VMIN))
92
93#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
94#define VMAJ(pState) (HDA_REG((pState), VMAJ))
95
96#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
97#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
98
99#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
100#define INPAY(pState) (HDA_REG((pState), INPAY))
101
102#define ICH6_HDA_REG_GCTL (5)
103#define ICH6_HDA_GCTL_RST_SHIFT (0)
104#define ICH6_HDA_GCTL_FSH_SHIFT (1)
105#define ICH6_HDA_GCTL_UR_SHIFT (8)
106#define GCTL(pState) (HDA_REG((pState), GCTL))
107
108#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
109#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
110
111#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
112#define STATESTS(pState) (HDA_REG((pState), STATESTS))
113#define ICH6_HDA_STATES_SCSF 0x7
114
115#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
116#define ICH6_HDA_GSTS_FSH_SHIFT (1)
117#define GSTS(pState) (HDA_REG(pState, GSTS))
118
119#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
120#define ICH6_HDA_INTCTL_GIE_SHIFT 31
121#define ICH6_HDA_INTCTL_CIE_SHIFT 30
122#define ICH6_HDA_INTCTL_S0_SHIFT (0)
123#define ICH6_HDA_INTCTL_S1_SHIFT (1)
124#define ICH6_HDA_INTCTL_S2_SHIFT (2)
125#define ICH6_HDA_INTCTL_S3_SHIFT (3)
126#define ICH6_HDA_INTCTL_S4_SHIFT (4)
127#define ICH6_HDA_INTCTL_S5_SHIFT (5)
128#define ICH6_HDA_INTCTL_S6_SHIFT (6)
129#define ICH6_HDA_INTCTL_S7_SHIFT (7)
130#define INTCTL(pState) (HDA_REG((pState), INTCTL))
131#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
132#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
133#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
134#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
135
136/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
137 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
138 * the datasheet.
139 */
140#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
141#define SSYNC(pState) (HDA_REG((pState), SSYNC))
142
143#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
144#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
145#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
146#define ICH6_HDA_INTSTS_S0_SHIFT (0)
147#define ICH6_HDA_INTSTS_S1_SHIFT (1)
148#define ICH6_HDA_INTSTS_S2_SHIFT (2)
149#define ICH6_HDA_INTSTS_S3_SHIFT (3)
150#define ICH6_HDA_INTSTS_S4_SHIFT (4)
151#define ICH6_HDA_INTSTS_S5_SHIFT (5)
152#define ICH6_HDA_INTSTS_S6_SHIFT (6)
153#define ICH6_HDA_INTSTS_S7_SHIFT (7)
154#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
155#define INTSTS(pState) (HDA_REG((pState), INTSTS))
156#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
157#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
158#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
159#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
160
161#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
162#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
163#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
164#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
165#define ICH6_HDA_REG_CORBWP 15 /* 48 */
166#define ICH6_HDA_REG_CORBRP 16 /* 4A */
167#define ICH6_HDA_CORBRP_RST_SHIFT 15
168#define ICH6_HDA_CORBRP_WP_SHIFT 0
169#define ICH6_HDA_CORBRP_WP_MASK 0xFF
170
171#define CORBRP(pState) (HDA_REG(pState, CORBRP))
172#define CORBWP(pState) (HDA_REG(pState, CORBWP))
173
174#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
175#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
176#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
177
178#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
179
180
181#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
182#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
183#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
184
185#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
186#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
187#define ICH6_HDA_CORBSIZE_SZ 0x3
188#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
189#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
190/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
191
192#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
193#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
194
195#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
196#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
197
198#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
199#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
200#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
201#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
202
203#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
204#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
205#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
206
207#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
208#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
209#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
210#define ICH6_HDA_ROI_DMA_SHIFT (2)
211#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
212#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
213#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
214#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
215
216#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
217#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
218#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
219#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
220#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
221#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
222
223#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
224#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
225#define ICH6_HDA_RIRBSIZE_SZ 0x3
226
227#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
228#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
229
230
231#define ICH6_HDA_REG_IC 27 /* 0x60 */
232#define IC(pState) (HDA_REG(pState, IC))
233#define ICH6_HDA_REG_IR 28 /* 0x64 */
234#define IR(pState) (HDA_REG(pState, IR))
235#define ICH6_HDA_REG_IRS 29 /* 0x68 */
236#define ICH6_HDA_IRS_ICB_SHIFT (0)
237#define ICH6_HDA_IRS_IRV_SHIFT (1)
238#define IRS(pState) (HDA_REG(pState, IRS))
239#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
240#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
241
242#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
243#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
244#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
245#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
246#define DPBASE_ENABLED 1
247#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
248
249#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
250#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
251/* Note: sdnum here _MUST_ be stream reg number [0,7] */
252#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
253
254#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
255#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
256#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
257#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
258#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
259#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
260#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
261#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
262
263#define SD(func, num) SD##num##func
264#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
265#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
266#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
267#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
268#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
269#define ICH6_HDA_SDCTL_TP_SHIFT (18)
270#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
271#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
272#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
273#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
274#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
275#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
276#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
277
278#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
279#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
280#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
281#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
282#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
283#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
284#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
285#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
286
287#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
288#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
289#define ICH6_HDA_SDSTS_DE_SHIFT (4)
290#define ICH6_HDA_SDSTS_FE_SHIFT (3)
291#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
292
293#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
294#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
295#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
296#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
297#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
298#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
299#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
300#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
301
302#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
303
304#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
305#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
306#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
307#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
308#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
309#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
310#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
311#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
312
313#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
314
315#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
316#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
317#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
318#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
319#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
320#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
321#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
322#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
323
324#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
325
326#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
327#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
328#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
329#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
330#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
331#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
332#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
333#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
334
335/*
336 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
337 */
338#define HDA_SDFIFOW_8B (0x2)
339#define HDA_SDFIFOW_16B (0x3)
340#define HDA_SDFIFOW_32B (0x4)
341#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
342
343#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
344#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
345#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
346#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
347#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
348#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
349#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
350#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
351
352/*
353 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
354 * formula: size - 1
355 * Other values not listed are not supported.
356 */
357#define HDA_SDONFIFO_16B (0x0F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
360#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
361#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
362#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
363#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
364#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
365#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
366
367#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
368#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
369#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
370#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
371#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
372#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
373#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
374#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
375
376#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
377#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
378#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
379#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
380#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
381#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
382#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
383#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
384#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
385#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
386#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
387
388#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
389#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
390#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
391#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
392#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
393#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
394#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
395#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
396
397#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
398
399#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
400#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
401#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
402#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
403#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
404#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
405#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
406#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
407
408#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
409
410
411/*******************************************************************************
412* Structures and Typedefs *
413*******************************************************************************/
414typedef struct HDABDLEDESC
415{
416 uint64_t u64BdleCviAddr;
417 uint32_t u32BdleMaxCvi;
418 uint32_t u32BdleCvi;
419 uint32_t u32BdleCviLen;
420 uint32_t u32BdleCviPos;
421 bool fBdleCviIoc;
422 uint32_t cbUnderFifoW;
423 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
424} HDABDLEDESC, *PHDABDLEDESC;
425
426typedef struct HDASTREAMTRANSFERDESC
427{
428 uint64_t u64BaseDMA;
429 uint32_t u32Ctl;
430 uint32_t *pu32Sts;
431 uint8_t u8Strm;
432 uint32_t *pu32Lpib;
433 uint32_t u32Cbl;
434 uint32_t u32Fifos;
435} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
436
437typedef struct INTELHDLinkState
438{
439 /** Pointer to the device instance. */
440 PPDMDEVINSR3 pDevIns;
441 /** Pointer to the connector of the attached audio driver. */
442 PPDMIAUDIOCONNECTOR pDrv;
443 /** Pointer to the attached audio driver. */
444 PPDMIBASE pDrvBase;
445 /** The base interface for LUN\#0. */
446 PDMIBASE IBase;
447 RTGCPHYS addrMMReg;
448 uint32_t au32Regs[HDA_NREGS];
449 HDABDLEDESC stInBdle;
450 HDABDLEDESC stOutBdle;
451 HDABDLEDESC stMicBdle;
452 /** Interrupt on completion */
453 bool fCviIoc;
454 uint64_t u64CORBBase;
455 uint64_t u64RIRBBase;
456 uint64_t u64DPBase;
457 /** pointer to CORB buf */
458 uint32_t *pu32CorbBuf;
459 /** size in bytes of CORB buf */
460 uint32_t cbCorbBuf;
461 /** pointer on RIRB buf */
462 uint64_t *pu64RirbBuf;
463 /** size in bytes of RIRB buf */
464 uint32_t cbRirbBuf;
465 /** indicates if HDA in reset. */
466 bool fInReset;
467 CODECState Codec;
468 uint8_t u8Counter;
469 uint64_t u64BaseTS;
470} INTELHDLinkState, *PINTELHDLinkState;
471
472#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
473#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
474
475#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
476 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
477#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
478 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
479
480
481typedef struct PCIINTELHDLinkState
482{
483 PCIDevice dev;
484 INTELHDLinkState hda;
485} PCIINTELHDLinkState;
486
487
488/*******************************************************************************
489* Internal Functions *
490*******************************************************************************/
491static FNPDMDEVRESET hdaReset;
492
493/** @todo r=bird: Why aren't these static? And why use DECLCALLBACK for
494 * internal functions? */
495DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
496DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
497DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
498DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
499DECLCALLBACK(int) hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
500DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
501DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
502DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
503DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
504DECLCALLBACK(int) hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
505DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
506DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
507DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
508DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
509DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
510DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
511DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
512DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
513DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
514DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
515
516DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
517DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
518DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
519DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
520DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
521DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
522DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
523DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
524DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
525DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
526DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
527DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
528DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
529DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
530DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
531DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
532
533DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm,
534 PHDASTREAMTRANSFERDESC pStreamDesc);
535static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t offReg);
536static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
537#ifdef LOG_ENABLED
538static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
539#endif
540
541
542/*******************************************************************************
543* Global Variables *
544*******************************************************************************/
545/* see 302349 p 6.2*/
546static const struct
547{
548 /** Register offset in the register space. */
549 uint32_t offset;
550 /** Size in bytes. Registers of size > 4 are in fact tables. */
551 uint32_t size;
552 /** Readable bits. */
553 uint32_t readable;
554 /** Writable bits. */
555 uint32_t writable;
556 /** Read callback. */
557 int (*pfnRead)(INTELHDLinkState *pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
558 /** Write callback. */
559 int (*pfnWrite)(INTELHDLinkState *pState, uint32_t offset, uint32_t index, uint32_t u32Value);
560 /** Abbreviated name. */
561 const char *abbrev;
562 /** Full name. */
563 const char *name;
564} g_aIchIntelHDRegMap[HDA_NREGS] =
565{
566 /* offset size read mask write mask read callback write callback abbrev full name */
567 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
568 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
569 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
570 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
571 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
572 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
573 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
574 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
575 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
576 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
577 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
578 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
579 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
580 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
581 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
582 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
583 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
584 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
585 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
586 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
587 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
588 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
589 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
590 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
591 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
592 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
593 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
594 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
595 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
596 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
597 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
598 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
599 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
600 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
601
602 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
603 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
604 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
605 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
606 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
607 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
608 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
609 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
610 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
611 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
612
613 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
614 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
615 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
616 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
617 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
618 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
619 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
620 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
621 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
622 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
623
624 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
625 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
626 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
627 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
628 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
629 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
630 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
631 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
632 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
633 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
634
635 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
636 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
637 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
638 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
639 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
640 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
641 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
642 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
643 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
644 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
645
646 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
647 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
648 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
649 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
650 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
651 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
652 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
653 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
654 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
655 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
656
657 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
658 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
659 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
660 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
661 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
662 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
663 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
664 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
665 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
666 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
667
668 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
669 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
670 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
671 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
672 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
673 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
674 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
675 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
676 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
677 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
678
679 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
680 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
681 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
682 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
683 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
684 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
685 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
686 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
687 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
688 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
689};
690
691/** HDABDLEDESC field descriptors the v3+ saved state. */
692static SSMFIELD const g_aHdaBDLEDescFields[] =
693{
694 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
695 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
696 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
697 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
698 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
699 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
700 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
701 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
702 SSMFIELD_ENTRY_TERM()
703};
704
705/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
706static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
707{
708 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
709 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
710 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
711 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
712 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
713 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
714 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
715 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
716 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
717 SSMFIELD_ENTRY_TERM()
718};
719
720
721DECLINLINE(void) hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
722{
723 if (pState->u64DPBase & DPBASE_ENABLED)
724 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
725 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
726}
727DECLINLINE(uint32_t) hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
728{
729#if 0
730 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
731 {
732 case HDA_SDFIFOW_8B: return 8;
733 case HDA_SDFIFOW_16B: return 16;
734 case HDA_SDFIFOW_32B: return 32;
735 default:
736 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
737 }
738#endif
739 return 0;
740}
741
742static int hdaProcessInterrupt(INTELHDLinkState* pState)
743{
744#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
745 ( INTCTL_SX((pState), num) \
746 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
747 bool fIrq = false;
748 if ( INTCTL_CIE(pState)
749 && ( RIRBSTS_RINTFL(pState)
750 || RIRBSTS_RIRBOIS(pState)
751 || (STATESTS(pState) & WAKEEN(pState))))
752 fIrq = true;
753
754 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
755 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
756 fIrq = true;
757
758 if (INTCTL_GIE(pState))
759 {
760 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
761 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
762 }
763 return VINF_SUCCESS;
764}
765
766static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t offReg)
767{
768 /*
769 * Aliases HDA spec 3.3.45
770 */
771 switch (offReg)
772 {
773 case 0x2084:
774 return HDA_REG_IND_NAME(SD0LPIB);
775 case 0x20A4:
776 return HDA_REG_IND_NAME(SD1LPIB);
777 case 0x20C4:
778 return HDA_REG_IND_NAME(SD2LPIB);
779 case 0x20E4:
780 return HDA_REG_IND_NAME(SD3LPIB);
781 case 0x2104:
782 return HDA_REG_IND_NAME(SD4LPIB);
783 case 0x2124:
784 return HDA_REG_IND_NAME(SD5LPIB);
785 case 0x2144:
786 return HDA_REG_IND_NAME(SD6LPIB);
787 case 0x2164:
788 return HDA_REG_IND_NAME(SD7LPIB);
789 }
790
791 /*
792 * Binary search the
793 */
794 int idxHigh = RT_ELEMENTS(g_aIchIntelHDRegMap);
795 int idxLow = 0;
796 for (;;)
797 {
798#ifdef DEBUG_vvl
799 Assert( idxHigh >= 0
800 && idxLow >= 0);
801#endif
802 if ( idxHigh < idxLow
803 || idxHigh < 0)
804 break;
805 int idxMiddle = idxLow + (idxHigh - idxLow) / 2;
806 if (offReg < g_aIchIntelHDRegMap[idxMiddle].offset)
807 idxHigh = idxMiddle - 1;
808 else if (offReg >= g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size)
809 idxLow = idxMiddle + 1;
810 else if ( offReg >= g_aIchIntelHDRegMap[idxMiddle].offset
811 && offReg < g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size)
812 return idxMiddle;
813 }
814 return -1;
815}
816
817static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
818{
819 int rc = VINF_SUCCESS;
820 if (fLocal)
821 {
822 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
823 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
824 if (RT_FAILURE(rc))
825 AssertRCReturn(rc, rc);
826#ifdef DEBUG_CMD_BUFFER
827 uint8_t i = 0;
828 do
829 {
830 Log(("hda: corb%02x: ", i));
831 uint8_t j = 0;
832 do
833 {
834 const char *prefix;
835 if ((i + j) == CORBRP(pState))
836 prefix = "[R]";
837 else if ((i + j) == CORBWP(pState))
838 prefix = "[W]";
839 else
840 prefix = " "; /* three spaces */
841 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
842 j++;
843 } while (j < 8);
844 Log(("\n"));
845 i += 8;
846 } while(i != 0);
847#endif
848 }
849 else
850 {
851 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
852 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
853 if (RT_FAILURE(rc))
854 AssertRCReturn(rc, rc);
855#ifdef DEBUG_CMD_BUFFER
856 uint8_t i = 0;
857 do {
858 Log(("hda: rirb%02x: ", i));
859 uint8_t j = 0;
860 do {
861 const char *prefix;
862 if ((i + j) == RIRBWP(pState))
863 prefix = "[W]";
864 else
865 prefix = " ";
866 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
867 } while (++j < 8);
868 Log(("\n"));
869 i += 8;
870 } while (i != 0);
871#endif
872 }
873 return rc;
874}
875
876static int hdaCORBCmdProcess(INTELHDLinkState *pState)
877{
878 int rc;
879 uint8_t corbRp;
880 uint8_t corbWp;
881 uint8_t rirbWp;
882
883 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
884
885 rc = hdaCmdSync(pState, true);
886 if (RT_FAILURE(rc))
887 AssertRCReturn(rc, rc);
888 corbRp = CORBRP(pState);
889 corbWp = CORBWP(pState);
890 rirbWp = RIRBWP(pState);
891 Assert((corbWp != corbRp));
892 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
893 while (corbRp != corbWp)
894 {
895 uint32_t cmd;
896 uint64_t resp;
897 pfn = (PFNCODECVERBPROCESSOR)NULL;
898 corbRp++;
899 cmd = pState->pu32CorbBuf[corbRp];
900 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
901 if (RT_FAILURE(rc))
902 AssertRCReturn(rc, rc);
903 Assert(pfn);
904 (rirbWp)++;
905
906 if (RT_LIKELY(pfn))
907 rc = pfn(&pState->Codec, cmd, &resp);
908 else
909 rc = VERR_INVALID_FUNCTION;
910
911 if (RT_FAILURE(rc))
912 AssertRCReturn(rc, rc);
913 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
914 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
915 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
916 {
917 Log(("hda: unexpected unsolicited response.\n"));
918 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
919 return rc;
920 }
921 pState->pu64RirbBuf[rirbWp] = resp;
922 pState->u8Counter++;
923 if (pState->u8Counter == RINTCNT_N(pState))
924 break;
925 }
926 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
927 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
928 rc = hdaCmdSync(pState, false);
929 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
930 if (RIRBCTL_RIRB_RIC(pState))
931 {
932 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
933 pState->u8Counter = 0;
934 rc = hdaProcessInterrupt(pState);
935 }
936 if (RT_FAILURE(rc))
937 AssertRCReturn(rc, rc);
938 return rc;
939}
940
941static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
942{
943 Log(("hda: reset of stream (%d) started\n", u8Strm));
944 Assert(( pState
945 && pBdle
946 && pStreamDesc
947 && u8Strm <= 7));
948 memset(pBdle, 0, sizeof(HDABDLEDESC));
949 *pStreamDesc->pu32Lpib = 0;
950 *pStreamDesc->pu32Sts = 0;
951 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
952 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
953 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
954
955 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
956 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
957 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
958 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
959 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
960 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
961 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
962 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
963 Log(("hda: reset of stream (%d) finished\n", u8Strm));
964}
965
966
967DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
968{
969 *pu32Value = 0;
970 return VINF_SUCCESS;
971}
972DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
973{
974 return VINF_SUCCESS;
975}
976/* U8 */
977DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
978{
979 Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffffff00) == 0);
980 return hdaRegReadU32(pState, offset, index, pu32Value);
981}
982
983DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
984{
985 Assert(((u32Value & 0xffffff00) == 0));
986 return hdaRegWriteU32(pState, offset, index, u32Value);
987}
988/* U16 */
989DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
990{
991 Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffff0000) == 0);
992 return hdaRegReadU32(pState, offset, index, pu32Value);
993}
994
995DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
996{
997 Assert(((u32Value & 0xffff0000) == 0));
998 return hdaRegWriteU32(pState, offset, index, u32Value);
999}
1000
1001/* U24 */
1002DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1003{
1004 Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xff000000) == 0);
1005 return hdaRegReadU32(pState, offset, index, pu32Value);
1006}
1007
1008DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1009{
1010 Assert(((u32Value & 0xff000000) == 0));
1011 return hdaRegWriteU32(pState, offset, index, u32Value);
1012}
1013/* U32 */
1014DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1015{
1016 *pu32Value = pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable;
1017 return VINF_SUCCESS;
1018}
1019
1020DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1021{
1022 pState->au32Regs[index] = (u32Value & g_aIchIntelHDRegMap[index].writable)
1023 | (pState->au32Regs[index] & ~g_aIchIntelHDRegMap[index].writable);
1024 return VINF_SUCCESS;
1025}
1026
1027DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1028{
1029 return hdaRegReadU32(pState, offset, index, pu32Value);
1030}
1031
1032DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1033{
1034 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1035 {
1036 /* exit reset state */
1037 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1038 pState->fInReset = false;
1039 }
1040 else
1041 {
1042 /* enter reset state*/
1043 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
1044 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
1045 {
1046 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1047 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
1048 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
1049 }
1050 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
1051 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1052 pState->fInReset = true;
1053 }
1054 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1055 {
1056 /* Flush: GSTS:1 set, see 6.2.6*/
1057 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1058 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1059 }
1060 return VINF_SUCCESS;
1061}
1062
1063DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1064{
1065 uint32_t v = pState->au32Regs[index];
1066 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1067 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1068 return VINF_SUCCESS;
1069}
1070
1071DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1072{
1073 uint32_t v = 0;
1074 if ( RIRBSTS_RIRBOIS(pState)
1075 || RIRBSTS_RINTFL(pState)
1076 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1077 || STATESTS(pState))
1078 v |= RT_BIT(30);
1079#define HDA_IS_STREAM_EVENT(pState, stream) \
1080 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1081 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1082 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1083#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1084 MARK_STREAM(pState, 0, v);
1085 MARK_STREAM(pState, 1, v);
1086 MARK_STREAM(pState, 2, v);
1087 MARK_STREAM(pState, 3, v);
1088 MARK_STREAM(pState, 4, v);
1089 MARK_STREAM(pState, 5, v);
1090 MARK_STREAM(pState, 6, v);
1091 MARK_STREAM(pState, 7, v);
1092 v |= v ? RT_BIT(31) : 0;
1093 *pu32Value = v;
1094 return VINF_SUCCESS;
1095}
1096
1097DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1098{
1099 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1100 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState))
1101 - pState->u64BaseTS, 24, 1000);
1102 return VINF_SUCCESS;
1103}
1104
1105DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1106{
1107 return hdaRegReadU16(pState, offset, index, pu32Value);
1108}
1109
1110DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1111{
1112 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1113 CORBRP(pState) = 0;
1114 else
1115 return hdaRegWriteU8(pState, offset, index, u32Value);
1116 return VINF_SUCCESS;
1117}
1118
1119DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1120{
1121 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1122 AssertRC(rc);
1123 if ( CORBWP(pState) != CORBRP(pState)
1124 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1125 return hdaCORBCmdProcess(pState);
1126 return rc;
1127}
1128
1129DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1130{
1131 uint32_t v = CORBSTS(pState);
1132 CORBSTS(pState) &= ~(v & u32Value);
1133 return VINF_SUCCESS;
1134}
1135
1136DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1137{
1138 int rc;
1139 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1140 if (RT_FAILURE(rc))
1141 AssertRCReturn(rc, rc);
1142 if (CORBWP(pState) == CORBRP(pState))
1143 return VINF_SUCCESS;
1144 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1145 return VINF_SUCCESS;
1146 rc = hdaCORBCmdProcess(pState);
1147 return rc;
1148}
1149
1150DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1151{
1152 return hdaRegReadU24(pState, offset, index, pu32Value);
1153}
1154
1155DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1156{
1157 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1158 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1159 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1160 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1161 int rc = VINF_SUCCESS;
1162 if (fInReset)
1163 {
1164 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1165 * from reset
1166 */
1167 Assert((!fReset));
1168 Log(("hda: guest initiated exit of stream reset.\n"));
1169 goto l_done;
1170 }
1171 else if (fReset)
1172 {
1173 /*
1174 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1175 */
1176 uint8_t u8Strm = 0;
1177 PHDABDLEDESC pBdle = NULL;
1178 HDASTREAMTRANSFERDESC StreamDesc;
1179 Assert((!fInRun && !fRun));
1180 switch (index)
1181 {
1182 case ICH6_HDA_REG_SD0CTL:
1183 u8Strm = 0;
1184 pBdle = &pState->stInBdle;
1185 break;
1186 case ICH6_HDA_REG_SD4CTL:
1187 u8Strm = 4;
1188 pBdle = &pState->stOutBdle;
1189 break;
1190 default:
1191 Log(("hda: changing SRST bit on non-attached stream\n"));
1192 goto l_done;
1193 }
1194 Log(("hda: guest initiated enter to stream reset.\n"));
1195 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &StreamDesc);
1196 hdaStreamReset(pState, pBdle, &StreamDesc, u8Strm);
1197 goto l_done;
1198 }
1199
1200 /* we enter here to change DMA states only */
1201 if ( (fInRun && !fRun)
1202 || (fRun && !fInRun))
1203 {
1204 Assert((!fReset && !fInReset));
1205 switch (index)
1206 {
1207 case ICH6_HDA_REG_SD0CTL:
1208 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1209 break;
1210 case ICH6_HDA_REG_SD4CTL:
1211 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1212 break;
1213 default:
1214 Log(("hda: changing RUN bit on non-attached stream\n"));
1215 goto l_done;
1216 }
1217 }
1218
1219l_done:
1220 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1221 if (RT_FAILURE(rc))
1222 AssertRCReturn(rc, VINF_SUCCESS);
1223 return rc;
1224}
1225
1226DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1227{
1228 uint32_t v = HDA_REG_IND(pState, index);
1229 v &= ~(u32Value & v);
1230 HDA_REG_IND(pState, index) = v;
1231 hdaProcessInterrupt(pState);
1232 return VINF_SUCCESS;
1233}
1234
1235DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1236{
1237 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1238 if (RT_FAILURE(rc))
1239 AssertRCReturn(rc, VINF_SUCCESS);
1240 return rc;
1241}
1242
1243DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1244{
1245 switch (u32Value)
1246 {
1247 case HDA_SDFIFOW_8B:
1248 case HDA_SDFIFOW_16B:
1249 case HDA_SDFIFOW_32B:
1250 return hdaRegWriteU16(pState, offset, index, u32Value);
1251 default:
1252 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1253 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1254 }
1255 return VINF_SUCCESS;
1256}
1257/*
1258 * Note this method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39)
1259 *
1260 */
1261DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1262{
1263 switch (index)
1264 {
1265 /* SDInFIFOS is RO, n=0-3 */
1266 case ICH6_HDA_REG_SD0FIFOS:
1267 case ICH6_HDA_REG_SD1FIFOS:
1268 case ICH6_HDA_REG_SD2FIFOS:
1269 case ICH6_HDA_REG_SD3FIFOS:
1270 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1271 return VINF_SUCCESS;
1272 case ICH6_HDA_REG_SD4FIFOS:
1273 case ICH6_HDA_REG_SD5FIFOS:
1274 case ICH6_HDA_REG_SD6FIFOS:
1275 case ICH6_HDA_REG_SD7FIFOS:
1276 switch(u32Value)
1277 {
1278 case HDA_SDONFIFO_16B:
1279 case HDA_SDONFIFO_32B:
1280 case HDA_SDONFIFO_64B:
1281 case HDA_SDONFIFO_128B:
1282 case HDA_SDONFIFO_192B:
1283 return hdaRegWriteU16(pState, offset, index, u32Value);
1284
1285 case HDA_SDONFIFO_256B:
1286 Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1287 default:
1288 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1289 }
1290 return VINF_SUCCESS;
1291 default:
1292 AssertMsgFailed(("Something weird happened with register lookup routine"));
1293 }
1294 return VINF_SUCCESS;
1295}
1296
1297static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1298{
1299 Assert((pAudSetting));
1300#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1301 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1302 uint32_t u32HzMult = 1;
1303 uint32_t u32HzDiv = 1;
1304 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1305 {
1306 case 0: u32HzMult = 1; break;
1307 case 1: u32HzMult = 2; break;
1308 case 2: u32HzMult = 3; break;
1309 case 3: u32HzMult = 4; break;
1310 default:
1311 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1312 }
1313 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1314 {
1315 case 0: u32HzDiv = 1; break;
1316 case 1: u32HzDiv = 2; break;
1317 case 2: u32HzDiv = 3; break;
1318 case 3: u32HzDiv = 4; break;
1319 case 4: u32HzDiv = 5; break;
1320 case 5: u32HzDiv = 6; break;
1321 case 6: u32HzDiv = 7; break;
1322 case 7: u32HzDiv = 8; break;
1323 }
1324 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1325
1326 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1327 {
1328 case 0:
1329 Log(("hda: %s requested 8-bit\n", __FUNCTION__));
1330 pAudSetting->fmt = AUD_FMT_S8;
1331 break;
1332 case 1:
1333 Log(("hda: %s requested 16-bit\n", __FUNCTION__));
1334 pAudSetting->fmt = AUD_FMT_S16;
1335 break;
1336 case 2:
1337 Log(("hda: %s requested 20-bit\n", __FUNCTION__));
1338 break;
1339 case 3:
1340 Log(("hda: %s requested 24-bit\n", __FUNCTION__));
1341 break;
1342 case 4:
1343 Log(("hda: %s requested 32-bit\n", __FUNCTION__));
1344 pAudSetting->fmt = AUD_FMT_S32;
1345 break;
1346 default:
1347 AssertMsgFailed(("Unsupported"));
1348 }
1349 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1350 pAudSetting->fmt = AUD_FMT_S16;
1351 pAudSetting->endianness = 0;
1352#undef EXTRACT_VALUE
1353}
1354
1355DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1356{
1357#ifdef VBOX_WITH_HDA_CODEC_EMU
1358 /* @todo a bit more investigation is required here. */
1359 int rc = 0;
1360 audsettings_t as;
1361 /* no reason to reopen voice with same settings */
1362 if (u32Value == HDA_REG_IND(pState, index))
1363 return VINF_SUCCESS;
1364 hdaSdFmtToAudSettings(u32Value, &as);
1365 switch (index)
1366 {
1367 case ICH6_HDA_REG_SD0FMT:
1368 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1369 break;
1370 case ICH6_HDA_REG_SD4FMT:
1371 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1372 break;
1373 default:
1374 Log(("HDA: attempt to change format on %d\n", index));
1375 rc = 0;
1376 }
1377 return hdaRegWriteU16(pState, offset, index, u32Value);
1378#else
1379 return hdaRegWriteU16(pState, offset, index, u32Value);
1380#endif
1381}
1382
1383DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1384{
1385 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1386 if (RT_FAILURE(rc))
1387 AssertRCReturn(rc, VINF_SUCCESS);
1388 return rc;
1389}
1390
1391DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1392{
1393 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1394 if (RT_FAILURE(rc))
1395 AssertRCReturn(rc, VINF_SUCCESS);
1396 return rc;
1397}
1398
1399DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1400{
1401 int rc = VINF_SUCCESS;
1402 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1403 if ( CORBWP(pState) != CORBRP(pState)
1404 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1405 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1406
1407 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1408 return rc;
1409}
1410
1411DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1412{
1413 int rc = VINF_SUCCESS;
1414 uint64_t resp;
1415 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1416 /*
1417 * if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1418 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1419 */
1420 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1421 && !IRS_ICB(pState))
1422 {
1423 uint32_t cmd = IC(pState);
1424 if (CORBWP(pState) != CORBRP(pState))
1425 {
1426 /*
1427 * 3.4.3 defines behavior of immediate Command status register.
1428 */
1429 LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));
1430 return rc;
1431 }
1432 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1433 Log(("hda: IC:%x\n", cmd));
1434 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1435 if (RT_FAILURE(rc))
1436 AssertRCReturn(rc, rc);
1437 rc = pfn(&pState->Codec, cmd, &resp);
1438 if (RT_FAILURE(rc))
1439 AssertRCReturn(rc, rc);
1440 IR(pState) = (uint32_t)resp;
1441 Log(("hda: IR:%x\n", IR(pState)));
1442 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1443 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1444 return rc;
1445 }
1446 /*
1447 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1448 */
1449 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1450 && IRS_IRV(pState))
1451 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1452 return rc;
1453}
1454
1455DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1456{
1457 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1458 {
1459 RIRBWP(pState) = 0;
1460 }
1461 /* The remaining bits are O, see 6.2.22 */
1462 return VINF_SUCCESS;
1463}
1464
1465DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1466{
1467 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1468 if (RT_FAILURE(rc))
1469 AssertRCReturn(rc, rc);
1470 switch(index)
1471 {
1472 case ICH6_HDA_REG_CORBLBASE:
1473 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1474 pState->u64CORBBase |= pState->au32Regs[index];
1475 break;
1476 case ICH6_HDA_REG_CORBUBASE:
1477 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1478 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1479 break;
1480 case ICH6_HDA_REG_RIRLBASE:
1481 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1482 pState->u64RIRBBase |= pState->au32Regs[index];
1483 break;
1484 case ICH6_HDA_REG_RIRUBASE:
1485 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1486 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1487 break;
1488 case ICH6_HDA_REG_DPLBASE:
1489 /* @todo: first bit has special meaning */
1490 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1491 pState->u64DPBase |= pState->au32Regs[index];
1492 break;
1493 case ICH6_HDA_REG_DPUBASE:
1494 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1495 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1496 break;
1497 default:
1498 AssertMsgFailed(("Invalid index"));
1499 }
1500 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1501 return rc;
1502}
1503
1504DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1505{
1506 uint8_t v = RIRBSTS(pState);
1507 RIRBSTS(pState) &= ~(v & u32Value);
1508
1509 return hdaProcessInterrupt(pState);
1510}
1511
1512#ifdef LOG_ENABLED
1513static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1514{
1515#if 0
1516 uint64_t addr;
1517 uint32_t len;
1518 uint32_t ioc;
1519 uint8_t bdle[16];
1520 uint32_t counter;
1521 uint32_t i;
1522 uint32_t sum = 0;
1523 Assert(pBdle && pBdle->u32BdleMaxCvi);
1524 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1525 {
1526 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1527 addr = *(uint64_t *)bdle;
1528 len = *(uint32_t *)&bdle[8];
1529 ioc = *(uint32_t *)&bdle[12];
1530 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1531 sum += len;
1532 }
1533 Log(("hda: sum: %d\n", sum));
1534 for (i = 0; i < 8; ++i)
1535 {
1536 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1537 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1538 i , counter));
1539 }
1540#endif
1541}
1542#endif
1543
1544static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1545{
1546 uint8_t bdle[16];
1547 Assert(( pStreamDesc->u64BaseDMA
1548 && pBdle
1549 && pBdle->u32BdleMaxCvi));
1550 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1551 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1552 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1553 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1554#ifdef LOG_ENABLED
1555 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1556#endif
1557}
1558
1559DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1560 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1561{
1562 uint32_t cb2Copy;
1563 /*
1564 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1565 */
1566 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1567 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1568 /*
1569 * we may increase the counter in range of [0, FIFOS + 1]
1570 */
1571 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1572 Assert((u32SoundBackendBufferBytesAvail > 0));
1573
1574 /* sanity check to avoid overriding the backend audio buffer */
1575 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1576 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1577
1578 if (cb2Copy <= pBdle->cbUnderFifoW)
1579 return 0;
1580 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1581 return cb2Copy;
1582}
1583
1584DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1585 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1586{
1587 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1588 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1589 Assert((cbCopied));
1590 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1591 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
1592 * Probably we need to move the buffer, but it is rather hard to imagine a situation
1593 * where it might happen.
1594 */
1595 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
1596 if ( pBdle->cbUnderFifoW
1597 && pBdle->cbUnderFifoW <= cbCopied)
1598 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1599
1600 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1601 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
1602
1603 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
1604 pBdle->u32BdleCviPos += cbArranged2Copy;
1605
1606 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1607 /* We report all bytes (including previously unreported bytes) */
1608 *pu32DMACursor += cbCopied;
1609 /* Decrease the backend counter by the number of bytes we copied to the backend */
1610 *pu32BackendBufferCapacity -= cbCopied;
1611 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1612 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1613}
1614
1615DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1616 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1617{
1618 Assert((cbCopied, cbArranged2Copy));
1619 *pu32BackendBufferCapacity -= cbCopied;
1620 pBdle->u32BdleCviPos += cbCopied;
1621 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1622 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1623 pBdle->cbUnderFifoW = 0;
1624 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1625 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1626}
1627
1628DECLINLINE(void) hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1629 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1630{
1631 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1632 pBdle->u32BdleCviPos += cbCopied;
1633 pBdle->cbUnderFifoW += cbCopied;
1634 /* In case of a read transaction we're always copying from the backend buffer */
1635 if (pu32BackendBufferCapacity)
1636 *pu32BackendBufferCapacity -= cbCopied;
1637 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1638 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1639}
1640
1641DECLINLINE(bool) hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1642{
1643 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1644 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1645
1646 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1647
1648 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1649 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1650 hdaUpdatePosBuf(pState, pStreamDesc);
1651
1652 /* don't touch BdleCvi counter on uninitialized descriptor */
1653 if ( pBdle->u32BdleCviPos
1654 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1655 {
1656 pBdle->u32BdleCviPos = 0;
1657 pBdle->u32BdleCvi++;
1658 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1659 pBdle->u32BdleCvi = 0;
1660 }
1661 return fOnBufferEdge;
1662}
1663
1664DECLINLINE(void) hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1665 uint32_t cbInc)
1666{
1667 /*
1668 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
1669 * (ICH6 datasheet 18.2.38)
1670 */
1671 if (!pBdle->cbUnderFifoW)
1672 {
1673 *pStreamDesc->pu32Lpib += cbInc;
1674
1675 /*
1676 * Assert. The buffer counters should never overlap.
1677 */
1678 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1679
1680 hdaUpdatePosBuf(pState, pStreamDesc);
1681
1682 }
1683}
1684
1685static bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1686{
1687 bool fDoNextTransferLoop = true;
1688 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1689 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1690 {
1691 if ( !pBdle->cbUnderFifoW
1692 && pBdle->fBdleCviIoc)
1693 {
1694 /*
1695 * @todo - more carefully investigate BCIS flag.
1696 * Speech synthesis works fine on Mac Guest if this bit isn't set
1697 * but in general sound quality gets worse.
1698 */
1699 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1700
1701 /*
1702 * we should generate the interrupt if ICE bit of SDCTL register is set.
1703 */
1704 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1705 hdaProcessInterrupt(pState);
1706 }
1707 fDoNextTransferLoop = false;
1708 }
1709 return fDoNextTransferLoop;
1710}
1711
1712/*
1713 * hdaReadAudio - copies samples from audio backend to DMA.
1714 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
1715 */
1716static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1717{
1718 PHDABDLEDESC pBdle = &pState->stInBdle;
1719 uint32_t cbTransferred = 0;
1720 uint32_t cb2Copy = 0;
1721 uint32_t cbBackendCopy = 0;
1722
1723 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1724
1725 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1726 if (!cb2Copy)
1727 {
1728 /* if we enter here we can't report "unreported bits" */
1729 *fStop = true;
1730 goto l_done;
1731 }
1732
1733
1734 /*
1735 * read from backend input line to the last unreported position or at the begining.
1736 */
1737 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1738 /*
1739 * write the HDA DMA buffer
1740 */
1741 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1742
1743 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
1744 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1745
1746 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1747 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1748 else
1749 {
1750 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1751 *fStop = true;
1752 }
1753l_done:
1754 Assert((cbTransferred <= (SDFIFOS(pState, 0) + 1)));
1755 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1756 return cbTransferred;
1757}
1758
1759static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1760{
1761 PHDABDLEDESC pBdle = &pState->stOutBdle;
1762 uint32_t cbTransferred = 0;
1763 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1764 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1765
1766 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1767
1768 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1769
1770 /*
1771 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the previous unreported transfer we write at offset ''pBdle->cbUnderFifoW'')
1772 */
1773 if (!cb2Copy)
1774 {
1775 *fStop = true;
1776 goto l_done;
1777 }
1778
1779 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1780 /*
1781 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
1782 */
1783 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1784 {
1785 /*
1786 * Feed the newly fetched samples, including unreported ones, to the backend.
1787 */
1788 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1789 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1790 }
1791 else
1792 {
1793 /* Not enough bytes to be processed and reported, we'll try our luck next time around */
1794 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1795 *fStop = true;
1796 }
1797
1798l_done:
1799 Assert((cbTransferred <= (SDFIFOS(pState, 4) + 1)));
1800 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1801 return cbTransferred;
1802}
1803
1804/**
1805 * @interface_method_impl{HDACODEC,pfnReset}
1806 */
1807DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1808{
1809 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pvHDAState;
1810 return VINF_SUCCESS;
1811}
1812
1813DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm,
1814 PHDASTREAMTRANSFERDESC pStreamDesc)
1815{
1816 Assert(pState); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
1817
1818 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1819 pStreamDesc->u8Strm = u8Strm;
1820 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1821 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1822 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1823 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1824 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1825 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1826 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1827
1828 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1829
1830#ifdef LOG_ENABLED
1831 if ( pBdle
1832 && pBdle->u32BdleMaxCvi)
1833 {
1834 Log(("Initialization of transfer descriptor:\n"));
1835 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1836 }
1837#endif
1838}
1839
1840
1841/**
1842 * @interface_method_impl{HDACODEC,pfnTransfer}
1843 */
1844static DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1845{
1846 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pvHDAState;
1847 uint8_t u8Strm = 0;
1848 PHDABDLEDESC pBdle = NULL;
1849
1850 switch (src)
1851 {
1852 case PO_INDEX:
1853 {
1854 u8Strm = 4;
1855 pBdle = &pState->stOutBdle;
1856 break;
1857 }
1858 case PI_INDEX:
1859 {
1860 u8Strm = 0;
1861 pBdle = &pState->stInBdle;
1862 break;
1863 }
1864 default:
1865 return;
1866 }
1867
1868 HDASTREAMTRANSFERDESC StreamDesc;
1869 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &StreamDesc);
1870
1871 bool fStop = false;
1872 while (avail && !fStop)
1873 {
1874 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1875 && avail
1876 && StreamDesc.u64BaseDMA);
1877
1878 /* Fetch the Buffer Descriptor Entry (BDE). */
1879
1880 if (hdaIsTransferCountersOverlapped(pState, pBdle, &StreamDesc))
1881 hdaFetchBdle(pState, pBdle, &StreamDesc);
1882 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1883 Assert((avail >= 0 && (StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib)))); /* sanity */
1884 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
1885 Assert((u32CblLimit > hdaFifoWToSz(pState, &StreamDesc)));
1886 Log(("hda: CBL=%d, LPIB=%d\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
1887 uint32_t cb;
1888 switch (src)
1889 {
1890 case PO_INDEX:
1891 cb = hdaWriteAudio(pState, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1892 break;
1893 case PI_INDEX:
1894 cb = hdaReadAudio(pState, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1895 break;
1896 default:
1897 cb = 0;
1898 fStop = true;
1899 AssertMsgFailed(("Unsupported"));
1900 }
1901 Assert(cb <= StreamDesc.u32Fifos + 1);
1902 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1903
1904 /* Process end of buffer condition. */
1905 hdaStreamCounterUpdate(pState, pBdle, &StreamDesc, cb);
1906 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &StreamDesc) : fStop;
1907 }
1908}
1909
1910
1911/* MMIO callbacks */
1912
1913/**
1914 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
1915 *
1916 * @note During implementation, we discovered so-called "forgotten" or "hole"
1917 * registers whose description is not listed in the RPM, datasheet, or
1918 * spec.
1919 */
1920PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1921{
1922 int rc = VINF_SUCCESS;
1923 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1924 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg;
1925 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg);
1926 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL)
1927 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1928
1929 if (idxReg == -1)
1930 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
1931
1932 if (idxReg != -1)
1933 {
1934 /** @todo r=bird: Accesses crossing register boundraries aren't handled
1935 * right from what I can tell? If they are, please explain
1936 * what the rules are. */
1937 uint32_t mask = 0;
1938 uint32_t shift = (g_aIchIntelHDRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
1939 uint32_t u32Value = 0;
1940 switch(cb)
1941 {
1942 case 1: mask = 0x000000ff; break;
1943 case 2: mask = 0x0000ffff; break;
1944 case 4:
1945 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
1946 case 8:
1947 mask = 0xffffffff;
1948 cb = 4;
1949 break;
1950 }
1951#if 0
1952 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
1953 */
1954 //Assert((cb <= g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset)));
1955 if (cb > g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset))
1956 {
1957 int off = cb - (g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset));
1958 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
1959 if (RT_FAILURE(rc))
1960 AssertRCReturn (rc, rc);
1961 }
1962 //Assert(((offReg - g_aIchIntelHDRegMap[idxReg].offset) == 0));
1963#endif
1964 mask <<= shift;
1965 rc = g_aIchIntelHDRegMap[idxReg].pfnRead(&pThis->hda, offReg, idxReg, &u32Value);
1966 *(uint32_t *)pv |= (u32Value & mask);
1967 Log(("hda: read %s[%x/%x]\n", g_aIchIntelHDRegMap[idxReg].abbrev, u32Value, *(uint32_t *)pv));
1968 return rc;
1969 }
1970 *(uint32_t *)pv = 0xFF;
1971 Log(("hda: hole at %x is accessed for read\n", offReg));
1972 return rc;
1973}
1974
1975
1976/**
1977 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
1978 */
1979PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1980{
1981 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1982 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg;
1983 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg);
1984 int rc = VINF_SUCCESS;
1985
1986 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL)
1987 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1988
1989 if ( idxReg == -1
1990 || cb > 4)
1991 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", offReg, cb));
1992
1993 if (idxReg != -1)
1994 {
1995 /** @todo r=bird: This looks like code for handling unaligned register
1996 * accesses. If it isn't, then add a comment explaining what you're
1997 * trying to do here. OTOH, if it is then it has the following
1998 * issues:
1999 * -# You're calculating the wrong new value for the register.
2000 * -# You're not handling cross register accesses. Imagine a
2001 * 4-byte write starting at CORBCTL, or a 8-byte write.
2002 *
2003 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
2004 * nobody seems to be using it and it just adds complexity when reading
2005 * the code.
2006 *
2007 */
2008 uint32_t u32CurValue = pThis->hda.au32Regs[idxReg];
2009 uint32_t u32NewValue;
2010 uint32_t mask;
2011 switch (cb)
2012 {
2013 case 1:
2014 u32NewValue = *(uint8_t const *)pv;
2015 mask = 0xff;
2016 break;
2017 case 2:
2018 u32NewValue = *(uint16_t const *)pv;
2019 mask = 0xffff;
2020 break;
2021 case 4:
2022 case 8:
2023 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2024 u32NewValue = *(uint32_t const *)pv;
2025 mask = 0xffffffff;
2026 cb = 4;
2027 break;
2028 default:
2029 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2030 }
2031 /* cross-register access, see corresponding comment in hdaMMIORead */
2032#if 0
2033 if (cb > g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset))
2034 {
2035 int off = cb - (g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset));
2036 rc = hdaMMIOWrite(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2037 if (RT_FAILURE(rc))
2038 AssertRCReturn (rc, rc);
2039 }
2040#endif
2041 uint32_t shift = (g_aIchIntelHDRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
2042 mask <<= shift;
2043 u32NewValue <<= shift;
2044 u32NewValue &= mask;
2045 u32NewValue |= (u32CurValue & ~mask);
2046
2047 rc = g_aIchIntelHDRegMap[idxReg].pfnWrite(&pThis->hda, offReg, idxReg, u32NewValue);
2048 Log(("hda: write %s:(%x) %x => %x\n", g_aIchIntelHDRegMap[idxReg].abbrev, u32NewValue,
2049 u32CurValue, pThis->hda.au32Regs[idxReg]));
2050 return rc;
2051 }
2052
2053 Log(("hda: hole at %x is accessed for write\n", offReg));
2054 return rc;
2055}
2056
2057
2058/* PCI callback. */
2059
2060/**
2061 * @callback_method_impl{FNPCIIOREGIONMAP}
2062 */
2063static DECLCALLBACK(int) hdaMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2064{
2065 int rc;
2066 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2067 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2068 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
2069
2070 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2071 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2072 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
2073 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA");
2074
2075 if (RT_FAILURE(rc))
2076 return rc;
2077
2078 pThis->hda.addrMMReg = GCPhysAddress;
2079 return VINF_SUCCESS;
2080}
2081
2082
2083/* Saved state callbacks. */
2084
2085/**
2086 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2087 */
2088static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2089{
2090 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2091 /* Save Codec nodes states */
2092 codecSaveState(&pThis->hda.Codec, pSSM);
2093
2094 /* Save MMIO registers */
2095 AssertCompile(RT_ELEMENTS(pThis->hda.au32Regs) == 112);
2096 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->hda.au32Regs));
2097 SSMR3PutMem(pSSM, pThis->hda.au32Regs, sizeof(pThis->hda.au32Regs));
2098
2099 /* Save HDA dma counters */
2100 SSMR3PutStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2101 SSMR3PutStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2102 SSMR3PutStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2103 return VINF_SUCCESS;
2104}
2105
2106
2107/**
2108 * @callback_method_impl{FNSSMDEVLOADEXEC}
2109 */
2110static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2111{
2112 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2113
2114 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2115
2116 /*
2117 * Load Codec nodes states.
2118 */
2119 int rc = codecLoadState(&pThis->hda.Codec, pSSM, uVersion);
2120 if (RT_FAILURE(rc))
2121 return rc;
2122
2123 /*
2124 * Load MMIO registers.
2125 */
2126 uint32_t cRegs;
2127 switch (uVersion)
2128 {
2129 case HDA_SSM_VERSION_1:
2130 /* Starting with r71199, we would save 112 instead of 113
2131 registers due to some code cleanups. This only affected trunk
2132 builds in the 4.1 development period. */
2133 cRegs = 113;
2134 if (SSMR3HandleRevision(pSSM) >= 71199)
2135 {
2136 uint32_t uVer = SSMR3HandleVersion(pSSM);
2137 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2138 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2139 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2140 cRegs = 112;
2141 }
2142 break;
2143
2144 case HDA_SSM_VERSION_2:
2145 case HDA_SSM_VERSION_3:
2146 cRegs = 112;
2147 AssertCompile(RT_ELEMENTS(pThis->hda.au32Regs) == 112);
2148 break;
2149
2150 case HDA_SSM_VERSION:
2151 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2152 AssertLogRelMsgReturn(cRegs == RT_ELEMENTS(pThis->hda.au32Regs),
2153 ("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->hda.au32Regs)),
2154 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2155 break;
2156
2157 default:
2158 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2159 }
2160
2161 if (cRegs >= RT_ELEMENTS(pThis->hda.au32Regs))
2162 {
2163 SSMR3GetMem(pSSM, pThis->hda.au32Regs, sizeof(pThis->hda.au32Regs));
2164 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->hda.au32Regs)));
2165 }
2166 else
2167 {
2168 RT_ZERO(pThis->hda.au32Regs);
2169 SSMR3GetMem(pSSM, pThis->hda.au32Regs, sizeof(uint32_t) * cRegs);
2170 }
2171
2172 /*
2173 * Load HDA dma counters.
2174 */
2175 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2176 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2177 SSMR3GetStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), fFlags, paFields, NULL);
2178 SSMR3GetStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), fFlags, paFields, NULL);
2179 rc = SSMR3GetStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), fFlags, paFields, NULL);
2180 AssertRCReturn(rc, rc);
2181
2182 /*
2183 * Update stuff after the state changes.
2184 */
2185 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2186 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2187
2188 pThis->hda.u64CORBBase = RT_MAKE_U64(CORBLBASE(&pThis->hda), CORBUBASE(&pThis->hda));
2189 pThis->hda.u64RIRBBase = RT_MAKE_U64(RIRLBASE(&pThis->hda), RIRUBASE(&pThis->hda));
2190 pThis->hda.u64DPBase = RT_MAKE_U64(DPLBASE(&pThis->hda), DPUBASE(&pThis->hda));
2191 return VINF_SUCCESS;
2192}
2193
2194
2195/* Debug and log type formatters. */
2196
2197/**
2198 * @callback_method_impl{FNRTSTRFORMATTYPE}
2199 */
2200static DECLCALLBACK(size_t)
2201hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2202 const char *pszType, void const *pvValue,
2203 int cchWidth, int cchPrecision, unsigned fFlags,
2204 void *pvUser)
2205{
2206 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2207 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2208 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
2209 sdCtl,
2210 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT,
2211 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
2212 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
2213 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT,
2214 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
2215 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
2216 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
2217 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
2218}
2219
2220/**
2221 * @callback_method_impl{FNRTSTRFORMATTYPE}
2222 */
2223static DECLCALLBACK(size_t)
2224hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2225 const char *pszType, void const *pvValue,
2226 int cchWidth, int cchPrecision, unsigned fFlags,
2227 void *pvUser)
2228{
2229 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2230 uint32_t cb;
2231 switch (uSdFifos)
2232 {
2233 case HDA_SDONFIFO_16B: cb = 16; break;
2234 case HDA_SDONFIFO_32B: cb = 32; break;
2235 case HDA_SDONFIFO_64B: cb = 64; break;
2236 case HDA_SDONFIFO_128B: cb = 128; break;
2237 case HDA_SDONFIFO_192B: cb = 192; break;
2238 case HDA_SDONFIFO_256B: cb = 256; break;
2239 case HDA_SDINFIFO_120B: cb = 120; break;
2240 case HDA_SDINFIFO_160B: cb = 160; break;
2241 default: cb = 0; break;
2242 }
2243 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
2244}
2245
2246/**
2247 * @callback_method_impl{FNRTSTRFORMATTYPE}
2248 */
2249static DECLCALLBACK(size_t)
2250hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2251 const char *pszType, void const *pvValue,
2252 int cchWidth, int cchPrecision, unsigned fFlags,
2253 void *pvUser)
2254{
2255 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2256 uint32_t cb;
2257 switch (uSdFifos)
2258 {
2259 case HDA_SDFIFOW_8B: cb = 8; break;
2260 case HDA_SDFIFOW_16B: cb = 16; break;
2261 case HDA_SDFIFOW_32B: cb = 32; break;
2262 default: cb = 0; break;
2263 }
2264 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
2265}
2266
2267/**
2268 * @callback_method_impl{FNRTSTRFORMATTYPE}
2269 */
2270static DECLCALLBACK(size_t)
2271hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2272 const char *pszType, void const *pvValue,
2273 int cchWidth, int cchPrecision, unsigned fFlags,
2274 void *pvUser)
2275{
2276 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
2277 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2278 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
2279 uSdSts,
2280 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
2281 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
2282 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
2283 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
2284}
2285
2286
2287static int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2288{
2289 int iReg = 0;
2290 for (; iReg < HDA_NREGS; ++iReg)
2291 if (!RTStrICmp(g_aIchIntelHDRegMap[iReg].abbrev, pszArgs))
2292 return iReg;
2293 return -1;
2294}
2295
2296
2297static void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2298{
2299 Assert( pState
2300 && iHdaIndex >= 0
2301 && iHdaIndex < HDA_NREGS);
2302 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aIchIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2303}
2304
2305
2306/**
2307 * @callback_method_impl{FNDBGFHANDLERDEV}
2308 */
2309static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2310{
2311 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2312 INTELHDLinkState *hda = &pThis->hda;
2313 int iHdaRegisterIndex = hdaLookUpRegisterByName(hda, pszArgs);
2314 if (iHdaRegisterIndex != -1)
2315 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2316 else
2317 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2318 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2319}
2320
2321
2322static void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2323{
2324 Assert( pState
2325 && iHdaStrmIndex >= 0
2326 && iHdaStrmIndex < 7);
2327 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
2328 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2329 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2330 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2331 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2332}
2333
2334
2335static int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2336{
2337 /* todo: add args parsing */
2338 return -1;
2339}
2340
2341
2342/**
2343 * @callback_method_impl{FNDBGFHANDLERDEV}
2344 */
2345static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2346{
2347 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2348 INTELHDLinkState *hda = &pThis->hda;
2349 int iHdaStrmIndex = hdaLookUpStreamIndex(hda, pszArgs);
2350 if (iHdaStrmIndex != -1)
2351 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2352 else
2353 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2354 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2355}
2356
2357/**
2358 * @callback_method_impl{FNDBGFHANDLERDEV}
2359 */
2360static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2361{
2362 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2363 INTELHDLinkState *hda = &pThis->hda;
2364 if (hda->Codec.pfnCodecDbgListNodes)
2365 hda->Codec.pfnCodecDbgListNodes(&hda->Codec, pHlp, pszArgs);
2366 else
2367 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2368}
2369
2370
2371/**
2372 * @callback_method_impl{FNDBGFHANDLERDEV}
2373 */
2374static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2375{
2376 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2377 INTELHDLinkState *hda = &pThis->hda;
2378 if (hda->Codec.pfnCodecDbgSelector)
2379 hda->Codec.pfnCodecDbgSelector(&hda->Codec, pHlp, pszArgs);
2380 else
2381 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2382}
2383
2384
2385/* PDMIBASE */
2386
2387/**
2388 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2389 */
2390static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2391{
2392 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2393 Assert(&pThis->hda.IBase == pInterface);
2394
2395 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2396 return NULL;
2397}
2398
2399
2400/* PDMDEVREG */
2401
2402/**
2403 * Reset notification.
2404 *
2405 * @returns VBox status.
2406 * @param pDevIns The device instance data.
2407 *
2408 * @remark The original sources didn't install a reset handler, but it seems to
2409 * make sense to me so we'll do it.
2410 */
2411static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2412{
2413 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2414 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2415 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
2416 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2417 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2418 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2419 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2420 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2421 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2422 CORBRP(&pThis->hda) = 0x0;
2423 RIRBWP(&pThis->hda) = 0x0;
2424
2425 Log(("hda: inter HDA reset.\n"));
2426 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2427
2428 if (pThis->hda.pu32CorbBuf)
2429 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2430 else
2431 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2432
2433 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2434 if (pThis->hda.pu64RirbBuf)
2435 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2436 else
2437 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2438
2439 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2440
2441 HDABDLEDESC stEmptyBdle;
2442 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2443 {
2444 HDASTREAMTRANSFERDESC StreamDesc;
2445 PHDABDLEDESC pBdle = NULL;
2446 if (u8Strm == 0)
2447 pBdle = &pThis->hda.stInBdle;
2448 else if(u8Strm == 4)
2449 pBdle = &pThis->hda.stOutBdle;
2450 else
2451 {
2452 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2453 pBdle = &stEmptyBdle;
2454 }
2455 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &StreamDesc);
2456 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
2457 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2458 hdaStreamReset(&pThis->hda, pBdle, &StreamDesc, u8Strm);
2459 }
2460
2461 /* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
2462 STATESTS(&pThis->hda) = 0x1;
2463
2464 Log(("hda: reset finished\n"));
2465}
2466
2467
2468/**
2469 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2470 */
2471static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
2472{
2473 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2474
2475 int rc = codecDestruct(&pThis->hda.Codec);
2476 AssertRC(rc);
2477 if (pThis->hda.pu32CorbBuf)
2478 RTMemFree(pThis->hda.pu32CorbBuf);
2479 if (pThis->hda.pu64RirbBuf)
2480 RTMemFree(pThis->hda.pu64RirbBuf);
2481 return VINF_SUCCESS;
2482}
2483
2484/**
2485 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2486 */
2487static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2488 PCFGMNODE pCfgHandle)
2489{
2490 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2491 INTELHDLinkState *s = &pThis->hda;
2492 int rc;
2493
2494 Assert(iInstance == 0);
2495 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2496
2497 /*
2498 * Validations.
2499 */
2500 if (!CFGMR3AreValuesValid(pCfgHandle, "\0"))
2501 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2502 N_ ("Invalid configuration for the Intel HDA device"));
2503
2504 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2505 // poll some register(s).
2506
2507 /*
2508 * Initialize data (most of it anyway).
2509 */
2510 s->pDevIns = pDevIns;
2511 /* IBase */
2512 s->IBase.pfnQueryInterface = hdaQueryInterface;
2513
2514 /* PCI Device */
2515 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2516 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2517
2518 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2519 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2520 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2521 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2522 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2523 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2524 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2525 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2526 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2527 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2528 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2529
2530#if defined(HDA_AS_PCI_EXPRESS)
2531 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2532#elif defined(VBOX_WITH_MSI_DEVICES)
2533 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2534#else
2535 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2536#endif
2537
2538 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2539 /// of these values needs to be properly documented!
2540 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2541 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2542
2543 /* Power Management */
2544 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2545 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2546 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2547
2548#ifdef HDA_AS_PCI_EXPRESS
2549 /* PCI Express */
2550 PCIDevSetByte(&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2551 PCIDevSetByte(&pThis->dev, 0x80 + 1, 0x60); /* next */
2552 /* Device flags */
2553 PCIDevSetWord(&pThis->dev, 0x80 + 2,
2554 /* version */ 0x1 |
2555 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2556 /* MSI */ (100) << 9 );
2557 /* Device capabilities */
2558 PCIDevSetDWord(&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2559 /* Device control */
2560 PCIDevSetWord( &pThis->dev, 0x80 + 8, 0);
2561 /* Device status */
2562 PCIDevSetWord( &pThis->dev, 0x80 + 10, 0);
2563 /* Link caps */
2564 PCIDevSetDWord(&pThis->dev, 0x80 + 12, 0);
2565 /* Link control */
2566 PCIDevSetWord( &pThis->dev, 0x80 + 16, 0);
2567 /* Link status */
2568 PCIDevSetWord( &pThis->dev, 0x80 + 18, 0);
2569 /* Slot capabilities */
2570 PCIDevSetDWord(&pThis->dev, 0x80 + 20, 0);
2571 /* Slot control */
2572 PCIDevSetWord( &pThis->dev, 0x80 + 24, 0);
2573 /* Slot status */
2574 PCIDevSetWord( &pThis->dev, 0x80 + 26, 0);
2575 /* Root control */
2576 PCIDevSetWord( &pThis->dev, 0x80 + 28, 0);
2577 /* Root capabilities */
2578 PCIDevSetWord( &pThis->dev, 0x80 + 30, 0);
2579 /* Root status */
2580 PCIDevSetDWord(&pThis->dev, 0x80 + 32, 0);
2581 /* Device capabilities 2 */
2582 PCIDevSetDWord(&pThis->dev, 0x80 + 36, 0);
2583 /* Device control 2 */
2584 PCIDevSetQWord(&pThis->dev, 0x80 + 40, 0);
2585 /* Link control 2 */
2586 PCIDevSetQWord(&pThis->dev, 0x80 + 48, 0);
2587 /* Slot control 2 */
2588 PCIDevSetWord( &pThis->dev, 0x80 + 56, 0);
2589#endif
2590
2591 /*
2592 * Register the PCI device.
2593 */
2594 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
2595 if (RT_FAILURE(rc))
2596 return rc;
2597
2598 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaMap);
2599 if (RT_FAILURE(rc))
2600 return rc;
2601
2602#ifdef VBOX_WITH_MSI_DEVICES
2603 PDMMSIREG MsiReg;
2604 RT_ZERO(MsiReg);
2605 MsiReg.cMsiVectors = 1;
2606 MsiReg.iMsiCapOffset = 0x60;
2607 MsiReg.iMsiNextOffset = 0x50;
2608 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
2609 if (RT_FAILURE(rc))
2610 {
2611 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2612 PCIDevSetCapabilityList(&pThis->dev, 0x50);
2613 }
2614#endif
2615
2616 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2617 if (RT_FAILURE(rc))
2618 return rc;
2619
2620 /*
2621 * Attach driver.
2622 */
2623 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "Audio Driver Port");
2624 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2625 Log(("hda: No attached driver!\n"));
2626 else if (RT_FAILURE(rc))
2627 {
2628 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
2629 return rc;
2630 }
2631
2632
2633
2634 pThis->hda.Codec.pvHDAState = (void *)&pThis->hda;
2635 rc = codecConstruct(pDevIns, &pThis->hda.Codec, pCfgHandle);
2636 if (RT_FAILURE(rc))
2637 AssertRCReturn(rc, rc);
2638
2639 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2640 verb F20 should provide device/codec recognition. */
2641 Assert(pThis->hda.Codec.u16VendorId);
2642 Assert(pThis->hda.Codec.u16DeviceId);
2643 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2644 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2645
2646 hdaReset(pDevIns);
2647 pThis->hda.Codec.id = 0;
2648 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2649 pThis->hda.Codec.pfnReset = hdaCodecReset;
2650
2651 /*
2652 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2653 * hdaReset shouldn't affects these registers.
2654 */
2655 WAKEEN(&pThis->hda) = 0x0;
2656 STATESTS(&pThis->hda) = 0x0;
2657
2658 /*
2659 * Debug and string formatter types.
2660 */
2661 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
2662 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
2663 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
2664 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
2665
2666 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
2667 AssertRC(rc);
2668 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
2669 AssertRC(rc);
2670 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
2671 AssertRC(rc);
2672 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
2673 AssertRC(rc);
2674#if 0
2675 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2676 AssertRC(rc);
2677#endif
2678
2679 return VINF_SUCCESS;
2680}
2681
2682/**
2683 * The device registration structure.
2684 */
2685const PDMDEVREG g_DeviceICH6_HDA =
2686{
2687 /* u32Version */
2688 PDM_DEVREG_VERSION,
2689 /* szName */
2690 "hda",
2691 /* szRCMod */
2692 "",
2693 /* szR0Mod */
2694 "",
2695 /* pszDescription */
2696 "Intel HD Audio Controller",
2697 /* fFlags */
2698 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2699 /* fClass */
2700 PDM_DEVREG_CLASS_AUDIO,
2701 /* cMaxInstances */
2702 1,
2703 /* cbInstance */
2704 sizeof(PCIINTELHDLinkState),
2705 /* pfnConstruct */
2706 hdaConstruct,
2707 /* pfnDestruct */
2708 hdaDestruct,
2709 /* pfnRelocate */
2710 NULL,
2711 /* pfnIOCtl */
2712 NULL,
2713 /* pfnPowerOn */
2714 NULL,
2715 /* pfnReset */
2716 hdaReset,
2717 /* pfnSuspend */
2718 NULL,
2719 /* pfnResume */
2720 NULL,
2721 /* pfnAttach */
2722 NULL,
2723 /* pfnDetach */
2724 NULL,
2725 /* pfnQueryInterface. */
2726 NULL,
2727 /* pfnInitComplete */
2728 NULL,
2729 /* pfnPowerOff */
2730 NULL,
2731 /* pfnSoftReset */
2732 NULL,
2733 /* u32VersionEnd */
2734 PDM_DEVREG_VERSION
2735};
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