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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 82458

最後變更 在這個檔案從82458是 82451,由 vboxsync 提交於 5 年 前

DevIchAc97: Put debug path on the heap rather than always grabbing ~4KB of state data for it. bugref:9218
  • 屬性 svn:eol-style 設為 native
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1/* $Id: DevIchAc97.cpp 82451 2019-12-06 12:46:23Z vboxsync $ */
2/** @file
3 * DevIchAc97 - VBox ICH AC97 Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_AC97
23#include <VBox/log.h>
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/pdmaudioifs.h>
26
27#include <iprt/assert.h>
28#ifdef IN_RING3
29# ifdef DEBUG
30# include <iprt/file.h>
31# endif
32# include <iprt/mem.h>
33# include <iprt/semaphore.h>
34# include <iprt/string.h>
35# include <iprt/uuid.h>
36#endif
37
38#include "VBoxDD.h"
39
40#include "AudioMixBuffer.h"
41#include "AudioMixer.h"
42#include "DrvAudio.h"
43
44
45/*********************************************************************************************************************************
46* Defined Constants And Macros *
47*********************************************************************************************************************************/
48
49/** Current saved state version. */
50#define AC97_SAVED_STATE_VERSION 1
51
52/** Default timer frequency (in Hz). */
53#define AC97_TIMER_HZ_DEFAULT 100
54
55/** Maximum number of streams we support. */
56#define AC97_MAX_STREAMS 3
57
58/** Maximum FIFO size (in bytes). */
59#define AC97_FIFO_MAX 256
60
61#define AC97_SR_FIFOE RT_BIT(4) /**< rwc, FIFO error. */
62#define AC97_SR_BCIS RT_BIT(3) /**< rwc, Buffer completion interrupt status. */
63#define AC97_SR_LVBCI RT_BIT(2) /**< rwc, Last valid buffer completion interrupt. */
64#define AC97_SR_CELV RT_BIT(1) /**< ro, Current equals last valid. */
65#define AC97_SR_DCH RT_BIT(0) /**< ro, Controller halted. */
66#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
67#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
68#define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV)
69#define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
70
71#define AC97_CR_IOCE RT_BIT(4) /**< rw, Interrupt On Completion Enable. */
72#define AC97_CR_FEIE RT_BIT(3) /**< rw FIFO Error Interrupt Enable. */
73#define AC97_CR_LVBIE RT_BIT(2) /**< rw Last Valid Buffer Interrupt Enable. */
74#define AC97_CR_RR RT_BIT(1) /**< rw Reset Registers. */
75#define AC97_CR_RPBM RT_BIT(0) /**< rw Run/Pause Bus Master. */
76#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
77#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE)
78
79#define AC97_GC_WR 4 /**< rw Warm reset. */
80#define AC97_GC_CR 2 /**< rw Cold reset. */
81#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
82
83#define AC97_GS_MD3 RT_BIT(17) /**< rw */
84#define AC97_GS_AD3 RT_BIT(16) /**< rw */
85#define AC97_GS_RCS RT_BIT(15) /**< rwc */
86#define AC97_GS_B3S12 RT_BIT(14) /**< ro */
87#define AC97_GS_B2S12 RT_BIT(13) /**< ro */
88#define AC97_GS_B1S12 RT_BIT(12) /**< ro */
89#define AC97_GS_S1R1 RT_BIT(11) /**< rwc */
90#define AC97_GS_S0R1 RT_BIT(10) /**< rwc */
91#define AC97_GS_S1CR RT_BIT(9) /**< ro */
92#define AC97_GS_S0CR RT_BIT(8) /**< ro */
93#define AC97_GS_MINT RT_BIT(7) /**< ro */
94#define AC97_GS_POINT RT_BIT(6) /**< ro */
95#define AC97_GS_PIINT RT_BIT(5) /**< ro */
96#define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3))
97#define AC97_GS_MOINT RT_BIT(2) /**< ro */
98#define AC97_GS_MIINT RT_BIT(1) /**< ro */
99#define AC97_GS_GSCI RT_BIT(0) /**< rwc */
100#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
101 | AC97_GS_B2S12 \
102 | AC97_GS_B1S12 \
103 | AC97_GS_S1CR \
104 | AC97_GS_S0CR \
105 | AC97_GS_MINT \
106 | AC97_GS_POINT \
107 | AC97_GS_PIINT \
108 | AC97_GS_RSRVD \
109 | AC97_GS_MOINT \
110 | AC97_GS_MIINT)
111#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
112#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI)
113
114/** @name Buffer Descriptor (BD).
115 * @{ */
116#define AC97_BD_IOC RT_BIT(31) /**< Interrupt on Completion. */
117#define AC97_BD_BUP RT_BIT(30) /**< Buffer Underrun Policy. */
118
119#define AC97_BD_LEN_MASK 0xFFFF /**< Mask for the BDL buffer length. */
120
121#define AC97_MAX_BDLE 32 /**< Maximum number of BDLEs. */
122/** @} */
123
124/** @name Extended Audio ID Register (EAID).
125 * @{ */
126#define AC97_EAID_VRA RT_BIT(0) /**< Variable Rate Audio. */
127#define AC97_EAID_VRM RT_BIT(3) /**< Variable Rate Mic Audio. */
128#define AC97_EAID_REV0 RT_BIT(10) /**< AC'97 revision compliance. */
129#define AC97_EAID_REV1 RT_BIT(11) /**< AC'97 revision compliance. */
130/** @} */
131
132/** @name Extended Audio Control and Status Register (EACS).
133 * @{ */
134#define AC97_EACS_VRA RT_BIT(0) /**< Variable Rate Audio (4.2.1.1). */
135#define AC97_EACS_VRM RT_BIT(3) /**< Variable Rate Mic Audio (4.2.1.1). */
136/** @} */
137
138/** @name Baseline Audio Register Set (BARS).
139 * @{ */
140#define AC97_BARS_VOL_MASK 0x1f /**< Volume mask for the Baseline Audio Register Set (5.7.2). */
141#define AC97_BARS_GAIN_MASK 0x0f /**< Gain mask for the Baseline Audio Register Set. */
142#define AC97_BARS_VOL_MUTE_SHIFT 15 /**< Mute bit shift for the Baseline Audio Register Set (5.7.2). */
143/** @} */
144
145/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
146#define AC97_DB_FACTOR 4
147
148/** @name Recording inputs?
149 * @{ */
150#define AC97_REC_MIC UINT8_C(0)
151#define AC97_REC_CD UINT8_C(1)
152#define AC97_REC_VIDEO UINT8_C(2)
153#define AC97_REC_AUX UINT8_C(3)
154#define AC97_REC_LINE_IN UINT8_C(4)
155#define AC97_REC_STEREO_MIX UINT8_C(5)
156#define AC97_REC_MONO_MIX UINT8_C(6)
157#define AC97_REC_PHONE UINT8_C(7)
158#define AC97_REC_MASK UINT8_C(7)
159/** @} */
160
161/** @name Mixer registers / NAM BAR registers?
162 * @{ */
163#define AC97_Reset 0x00
164#define AC97_Master_Volume_Mute 0x02
165#define AC97_Headphone_Volume_Mute 0x04 /**< Also known as AUX, see table 16, section 5.7. */
166#define AC97_Master_Volume_Mono_Mute 0x06
167#define AC97_Master_Tone_RL 0x08
168#define AC97_PC_BEEP_Volume_Mute 0x0a
169#define AC97_Phone_Volume_Mute 0x0c
170#define AC97_Mic_Volume_Mute 0x0e
171#define AC97_Line_In_Volume_Mute 0x10
172#define AC97_CD_Volume_Mute 0x12
173#define AC97_Video_Volume_Mute 0x14
174#define AC97_Aux_Volume_Mute 0x16
175#define AC97_PCM_Out_Volume_Mute 0x18
176#define AC97_Record_Select 0x1a
177#define AC97_Record_Gain_Mute 0x1c
178#define AC97_Record_Gain_Mic_Mute 0x1e
179#define AC97_General_Purpose 0x20
180#define AC97_3D_Control 0x22
181#define AC97_AC_97_RESERVED 0x24
182#define AC97_Powerdown_Ctrl_Stat 0x26
183#define AC97_Extended_Audio_ID 0x28
184#define AC97_Extended_Audio_Ctrl_Stat 0x2a
185#define AC97_PCM_Front_DAC_Rate 0x2c
186#define AC97_PCM_Surround_DAC_Rate 0x2e
187#define AC97_PCM_LFE_DAC_Rate 0x30
188#define AC97_PCM_LR_ADC_Rate 0x32
189#define AC97_MIC_ADC_Rate 0x34
190#define AC97_6Ch_Vol_C_LFE_Mute 0x36
191#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
192#define AC97_Vendor_Reserved 0x58
193#define AC97_AD_Misc 0x76
194#define AC97_Vendor_ID1 0x7c
195#define AC97_Vendor_ID2 0x7e
196/** @} */
197
198/** @name Analog Devices miscellaneous regiter bits used in AD1980.
199 * @{ */
200#define AC97_AD_MISC_LOSEL RT_BIT(5) /**< Surround (rear) goes to line out outputs. */
201#define AC97_AD_MISC_HPSEL RT_BIT(10) /**< PCM (front) goes to headphone outputs. */
202/** @} */
203
204
205/** @name BUP flag values.
206 * @{ */
207#define BUP_SET RT_BIT_32(0)
208#define BUP_LAST RT_BIT_32(1)
209/** @} */
210
211/** @name AC'97 source indices.
212 * @note The order of these indices is fixed (also applies for saved states) for
213 * the moment. So make sure you know what you're done when altering this!
214 * @{
215 */
216#define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
217#define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
218#define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
219#define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
220/** @} */
221
222/** Port number (offset into NABM BAR) to stream index. */
223#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
224/** Port number (offset into NABM BAR) to stream index, but no masking. */
225#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
226
227/** @name Stream offsets
228 * @{ */
229#define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
230#define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
231#define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
232#define AC97_NABM_OFF_SR 0x6 /**< Status Register */
233#define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
234#define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
235#define AC97_NABM_OFF_CR 0xb /**< Control Register */
236#define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
237/** @} */
238
239
240/** @name PCM in NABM BAR registers (0x00..0x0f).
241 * @{ */
242#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
243#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
244#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
245#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
246#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
247#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
248#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
249/** @} */
250
251/** @name PCM out NABM BAR registers (0x10..0x1f).
252 * @{ */
253#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /**< PCM out: Buffer Descriptor Base Address */
254#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /**< PCM out: Current Index Value */
255#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /**< PCM out: Last Valid Index */
256#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /**< PCM out: Status Register */
257#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /**< PCM out: Position in Current Buffer */
258#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /**< PCM out: Prefetched Index Value */
259#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /**< PCM out: Control Register */
260/** @} */
261
262/** @name Mic in NABM BAR registers (0x20..0x2f).
263 * @{ */
264#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
265#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
266#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
267#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
268#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
269#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
270#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
271/** @} */
272
273/** @name Misc NABM BAR registers.
274 * @{ */
275/** NABMBAR: Global Control Register.
276 * @note This is kind of in the MIC IN area. */
277#define AC97_GLOB_CNT 0x2c
278/** NABMBAR: Global Status. */
279#define AC97_GLOB_STA 0x30
280/** Codec Access Semaphore Register. */
281#define AC97_CAS 0x34
282/** @} */
283
284
285/*********************************************************************************************************************************
286* Structures and Typedefs *
287*********************************************************************************************************************************/
288/** The ICH AC'97 (Intel) controller. */
289typedef struct AC97STATE *PAC97STATE;
290
291/**
292 * Buffer Descriptor List Entry (BDLE).
293 */
294typedef struct AC97BDLE
295{
296 /** Location of data buffer (bits 31:1). */
297 uint32_t addr;
298 /** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples). */
299 uint32_t ctl_len;
300} AC97BDLE;
301AssertCompileSize(AC97BDLE, 8);
302/** Pointer to BDLE. */
303typedef AC97BDLE *PAC97BDLE;
304
305/**
306 * Bus master register set for an audio stream.
307 */
308typedef struct AC97BMREGS
309{
310 uint32_t bdbar; /**< rw 0, Buffer Descriptor List: BAR (Base Address Register). */
311 uint8_t civ; /**< ro 0, Current index value. */
312 uint8_t lvi; /**< rw 0, Last valid index. */
313 uint16_t sr; /**< rw 1, Status register. */
314 uint16_t picb; /**< ro 0, Position in current buffer (in samples). */
315 uint8_t piv; /**< ro 0, Prefetched index value. */
316 uint8_t cr; /**< rw 0, Control register. */
317 int32_t bd_valid; /**< Whether current BDLE is initialized or not. */
318 AC97BDLE bd; /**< Current Buffer Descriptor List Entry (BDLE). */
319} AC97BMREGS;
320AssertCompileSizeAlignment(AC97BMREGS, 8);
321/** Pointer to the BM registers of an audio stream. */
322typedef AC97BMREGS *PAC97BMREGS;
323
324#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
325/**
326 * Asynchronous I/O state for an AC'97 stream.
327 */
328typedef struct AC97STREAMSTATEAIO
329{
330 /** Thread handle for the actual I/O thread. */
331 RTTHREAD Thread;
332 /** Event for letting the thread know there is some data to process. */
333 RTSEMEVENT Event;
334 /** Critical section for synchronizing access. */
335 RTCRITSECT CritSect;
336 /** Started indicator. */
337 volatile bool fStarted;
338 /** Shutdown indicator. */
339 volatile bool fShutdown;
340 /** Whether the thread should do any data processing or not. */
341 volatile bool fEnabled;
342 bool afPadding[5];
343} AC97STREAMSTATEAIO;
344/** Pointer to the async I/O state for an AC'97 stream. */
345typedef AC97STREAMSTATEAIO *PAC97STREAMSTATEAIO;
346#endif
347
348
349/**
350 * The internal state of an AC'97 stream.
351 */
352typedef struct AC97STREAMSTATE
353{
354 /** Criticial section for this stream. */
355 RTCRITSECT CritSect;
356 /** Circular buffer (FIFO) for holding DMA'ed data. */
357 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
358#if HC_ARCH_BITS == 32
359 uint32_t Padding;
360#endif
361 /** The stream's current configuration. */
362 PDMAUDIOSTREAMCFG Cfg; //+104
363 uint32_t Padding2;
364#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
365 /** Asynchronous I/O state members. */
366 AC97STREAMSTATEAIO AIO;
367#endif
368 /** Timestamp of the last DMA data transfer. */
369 uint64_t tsTransferLast;
370 /** Timestamp of the next DMA data transfer.
371 * Next for determining the next scheduling window.
372 * Can be 0 if no next transfer is scheduled. */
373 uint64_t tsTransferNext;
374 /** Transfer chunk size (in bytes) of a transfer period. */
375 uint32_t cbTransferChunk;
376 /** The stream's timer Hz rate.
377 * This value can can be different from the device's default Hz rate,
378 * depending on the rate the stream expects (e.g. for 5.1 speaker setups).
379 * Set in R3StreamInit(). */
380 uint16_t uTimerHz;
381 uint8_t Padding3[2];
382 /** (Virtual) clock ticks per transfer. */
383 uint64_t cTransferTicks;
384 /** Timestamp (in ns) of last stream update. */
385 uint64_t tsLastUpdateNs;
386} AC97STREAMSTATE;
387AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
388/** Pointer to internal state of an AC'97 stream. */
389typedef AC97STREAMSTATE *PAC97STREAMSTATE;
390
391/**
392 * Runtime configurable debug stuff for an AC'97 stream.
393 */
394typedef struct AC97STREAMDEBUGRT
395{
396 /** Whether debugging is enabled or not. */
397 bool fEnabled;
398 uint8_t Padding[7];
399 /** File for dumping stream reads / writes.
400 * For input streams, this dumps data being written to the device FIFO,
401 * whereas for output streams this dumps data being read from the device FIFO. */
402 R3PTRTYPE(PPDMAUDIOFILE) pFileStream;
403 /** File for dumping DMA reads / writes.
404 * For input streams, this dumps data being written to the device DMA,
405 * whereas for output streams this dumps data being read from the device DMA. */
406 R3PTRTYPE(PPDMAUDIOFILE) pFileDMA;
407} AC97STREAMDEBUGRT;
408
409/**
410 * Debug stuff for an AC'97 stream.
411 */
412typedef struct AC97STREAMDEBUG
413{
414 /** Runtime debug stuff. */
415 AC97STREAMDEBUGRT Runtime;
416} AC97STREAMDEBUG;
417
418/**
419 * The shared AC'97 stream state.
420 */
421typedef struct AC97STREAM
422{
423 /** Stream number (SDn). */
424 uint8_t u8SD;
425 uint8_t abPadding0[7];
426 /** Bus master registers of this stream. */
427 AC97BMREGS Regs;
428 /** The timer for pumping data thru the attached LUN drivers. */
429 TMTIMERHANDLE hTimer;
430} AC97STREAM;
431AssertCompileSizeAlignment(AC97STREAM, 8);
432/** Pointer to a shared AC'97 stream state. */
433typedef AC97STREAM *PAC97STREAM;
434
435
436/**
437 * The ring-3 AC'97 stream state.
438 */
439typedef struct AC97STREAMR3
440{
441 /** Stream number (SDn). */
442 uint8_t u8SD;
443 uint8_t abPadding0[7];
444 /** Internal state of this stream. */
445 AC97STREAMSTATE State;
446 /** Debug stuff. */
447 AC97STREAMDEBUG Dbg;
448} AC97STREAMR3;
449AssertCompileSizeAlignment(AC97STREAMR3, 8);
450/** Pointer to an AC'97 stream state for ring-3. */
451typedef AC97STREAMR3 *PAC97STREAMR3;
452
453
454#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
455/**
456 * Asynchronous I/O thread context (arguments).
457 */
458typedef struct AC97STREAMTHREADCTX
459{
460 PAC97STATE pThis;
461 PAC97STREAM pStream;
462} AC97STREAMTHREADCTX;
463/** Pointer to the context for an async I/O thread. */
464typedef AC97STREAMTHREADCTX *PAC97STREAMTHREADCTX;
465#endif
466
467/**
468 * A driver stream (host backend).
469 *
470 * Each driver has its own instances of audio mixer streams, which then
471 * can go into the same (or even different) audio mixer sinks.
472 */
473typedef struct AC97DRIVERSTREAM
474{
475 /** Associated mixer stream handle. */
476 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
477} AC97DRIVERSTREAM;
478/** Pointer to a driver stream. */
479typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
480
481/**
482 * A host backend driver (LUN).
483 */
484typedef struct AC97DRIVER
485{
486 /** Node for storing this driver in our device driver list of AC97STATE. */
487 RTLISTNODER3 Node;
488 /** Driver flags. */
489 PDMAUDIODRVFLAGS fFlags;
490 /** LUN # to which this driver has been assigned. */
491 uint8_t uLUN;
492 /** Whether this driver is in an attached state or not. */
493 bool fAttached;
494 uint8_t abPadding[2];
495 /** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
496 R3PTRTYPE(char *) pszDesc;
497 /** Pointer to attached driver base interface. */
498 R3PTRTYPE(PPDMIBASE) pDrvBase;
499 /** Audio connector interface to the underlying host backend. */
500 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
501 /** Driver stream for line input. */
502 AC97DRIVERSTREAM LineIn;
503 /** Driver stream for mic input. */
504 AC97DRIVERSTREAM MicIn;
505 /** Driver stream for output. */
506 AC97DRIVERSTREAM Out;
507} AC97DRIVER;
508/** Pointer to a host backend driver (LUN). */
509typedef AC97DRIVER *PAC97DRIVER;
510
511/**
512 * Debug settings.
513 */
514typedef struct AC97STATEDEBUG
515{
516 /** Whether debugging is enabled or not. */
517 bool fEnabled;
518 bool afAlignment[7];
519 /** Path where to dump the debug output to.
520 * Defaults to VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH. */
521 R3PTRTYPE(char *) pszOutPath;
522} AC97STATEDEBUG;
523
524
525/* Codec models. */
526typedef enum AC97CODEC
527{
528 AC97CODEC_INVALID = 0, /**< Customary illegal zero value. */
529 AC97CODEC_STAC9700, /**< SigmaTel STAC9700 */
530 AC97CODEC_AD1980, /**< Analog Devices AD1980 */
531 AC97CODEC_AD1981B, /**< Analog Devices AD1981B */
532 AC97CODEC_32BIT_HACK = 0x7fffffff
533} AC97CODEC;
534
535
536/**
537 * The shared AC'97 device state.
538 */
539typedef struct AC97STATE
540{
541 /** Critical section protecting the AC'97 state. */
542 PDMCRITSECT CritSect;
543 /** Global Control (Bus Master Control Register). */
544 uint32_t glob_cnt;
545 /** Global Status (Bus Master Control Register). */
546 uint32_t glob_sta;
547 /** Codec Access Semaphore Register (Bus Master Control Register). */
548 uint32_t cas;
549 uint32_t last_samp;
550 uint8_t mixer_data[256];
551 /** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
552 AC97STREAM aStreams[AC97_MAX_STREAMS];
553 /** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
554 uint16_t uTimerHz;
555 uint16_t au16Padding1[3];
556 uint8_t silence[128];
557 uint32_t bup_flag;
558 /** Codec model. */
559 AC97CODEC enmCodecModel;
560
561 /** PCI region \#0: NAM I/O ports. */
562 IOMIOPORTHANDLE hIoPortsNam;
563 /** PCI region \#0: NANM I/O ports. */
564 IOMIOPORTHANDLE hIoPortsNabm;
565
566 STAMCOUNTER StatUnimplementedNabmReads;
567 STAMCOUNTER StatUnimplementedNabmWrites;
568#ifdef VBOX_WITH_STATISTICS
569 STAMPROFILE StatTimer;
570 STAMPROFILE StatIn;
571 STAMPROFILE StatOut;
572 STAMCOUNTER StatBytesRead;
573 STAMCOUNTER StatBytesWritten;
574#endif
575} AC97STATE;
576AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
577AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
578#ifdef VBOX_WITH_STATISTICS
579AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
580AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
581AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
582#endif
583
584
585/**
586 * The ring-3 AC'97 device state.
587 */
588typedef struct AC97STATER3
589{
590 /** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
591 AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
592 /** R3 pointer to the device instance. */
593 PPDMDEVINSR3 pDevIns;
594 /** List of associated LUN drivers (AC97DRIVER). */
595 RTLISTANCHORR3 lstDrv;
596 /** The device's software mixer. */
597 R3PTRTYPE(PAUDIOMIXER) pMixer;
598 /** Audio sink for PCM output. */
599 R3PTRTYPE(PAUDMIXSINK) pSinkOut;
600 /** Audio sink for line input. */
601 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
602 /** Audio sink for microphone input. */
603 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
604 /** The base interface for LUN\#0. */
605 PDMIBASE IBase;
606 /** Debug settings. */
607 AC97STATEDEBUG Dbg;
608} AC97STATER3;
609AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
610/** Pointer to the ring-3 AC'97 device state. */
611typedef AC97STATER3 *PAC97STATER3;
612
613
614/**
615 * Acquires the AC'97 lock.
616 */
617#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
618 do { \
619 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
620 AssertRC(rcLock); \
621 } while (0)
622
623/**
624 * Acquires the AC'97 lock or returns.
625 */
626# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
627 do { \
628 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
629 if (rcLock == VINF_SUCCESS) \
630 break; \
631 AssertRC(rcLock); \
632 return rcLock; \
633 } while (0)
634
635/** Retrieves an attribute from a specific audio stream in RC. */
636#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
637
638/**
639 * Releases the AC'97 lock.
640 */
641#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
642 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
643
644/**
645 * Acquires the TM lock and AC'97 lock, returns on failure.
646 */
647#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
648 do { \
649 VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
650 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
651 { /* likely */ } \
652 else \
653 { \
654 AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
655 return rcLock; \
656 } \
657 } while (0)
658
659/**
660 * Releases the AC'97 lock and TM lock.
661 */
662#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
663 PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
664
665#ifndef VBOX_DEVICE_STRUCT_TESTCASE
666
667
668/*********************************************************************************************************************************
669* Internal Functions *
670*********************************************************************************************************************************/
671#ifdef IN_RING3
672static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce);
673static int ichac97R3StreamClose(PAC97STREAM pStream);
674static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
675static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
676static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
677static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
678static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
679 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
680static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
681 PAC97STREAMR3 pStreamCC, bool fInTimer);
682
683static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
684
685static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
686
687static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
688 PDMAUDIODSTSRCUNION dstSrc);
689
690# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
691static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STREAM pStream);
692static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAM pStream);
693static void ichac97R3StreamAsyncIOLock(PAC97STREAM pStream);
694static void ichac97R3StreamAsyncIOUnlock(PAC97STREAM pStream);
695/*static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable); Unused */
696# endif
697
698DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
699DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
700#endif /* IN_RING3 */
701
702
703/*********************************************************************************************************************************
704* Global Variables *
705*********************************************************************************************************************************/
706#ifdef IN_RING3
707/** NABM I/O port descriptions. */
708static const IOMIOPORTDESC g_aNabmPorts[] =
709{
710 { "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
711 { "", NULL, NULL, NULL },
712 { "", NULL, NULL, NULL },
713 { "", NULL, NULL, NULL },
714 { "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
715 { "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
716 { "PCM IN - SR", "PCM IN - SR", NULL, NULL },
717 { "", NULL, NULL, NULL },
718 { "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
719 { "", NULL, NULL, NULL },
720 { "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
721 { "PCM IN - CR", "PCM IN - CR", NULL, NULL },
722 { "", NULL, NULL, NULL },
723 { "", NULL, NULL, NULL },
724 { "", NULL, NULL, NULL },
725 { "", NULL, NULL, NULL },
726
727 { "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
728 { "", NULL, NULL, NULL },
729 { "", NULL, NULL, NULL },
730 { "", NULL, NULL, NULL },
731 { "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
732 { "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
733 { "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
734 { "", NULL, NULL, NULL },
735 { "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
736 { "", NULL, NULL, NULL },
737 { "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
738 { "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
739 { "", NULL, NULL, NULL },
740 { "", NULL, NULL, NULL },
741 { "", NULL, NULL, NULL },
742 { "", NULL, NULL, NULL },
743
744 { "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
745 { "", NULL, NULL, NULL },
746 { "", NULL, NULL, NULL },
747 { "", NULL, NULL, NULL },
748 { "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
749 { "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
750 { "MIC IN - SR", "MIC IN - SR", NULL, NULL },
751 { "", NULL, NULL, NULL },
752 { "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
753 { "", NULL, NULL, NULL },
754 { "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
755 { "MIC IN - CR", "MIC IN - CR", NULL, NULL },
756 { "GLOB CNT", "GLOB CNT", NULL, NULL },
757 { "", NULL, NULL, NULL },
758 { "", NULL, NULL, NULL },
759 { "", NULL, NULL, NULL },
760
761 { "GLOB STA", "GLOB STA", NULL, NULL },
762 { "", NULL, NULL, NULL },
763 { "", NULL, NULL, NULL },
764 { "", NULL, NULL, NULL },
765 { "CAS", "CAS", NULL, NULL },
766 { NULL, NULL, NULL, NULL },
767};
768
769#define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
770#define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
771#define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
772#define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
773/** @} */
774
775/** Port number (offset into NABM BAR) to stream index. */
776#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
777/** Port number (offset into NABM BAR) to stream index, but no masking. */
778#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
779
780/** @name Stream offsets
781 * @{ */
782#define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
783#define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
784#define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
785#define AC97_NABM_OFF_SR 0x6 /**< Status Register */
786#define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
787#define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
788#define AC97_NABM_OFF_CR 0xb /**< Control Register */
789#define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
790
791#endif
792
793
794
795static void ichac97WarmReset(PAC97STATE pThis)
796{
797 NOREF(pThis);
798}
799
800static void ichac97ColdReset(PAC97STATE pThis)
801{
802 NOREF(pThis);
803}
804
805
806#ifdef IN_RING3
807
808/**
809 * Retrieves the audio mixer sink of a corresponding AC'97 stream index.
810 *
811 * @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
812 * @param pThisCC The ring-3 AC'97 state.
813 * @param uIndex Stream index to get audio mixer sink for.
814 */
815DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
816{
817 switch (uIndex)
818 {
819 case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
820 case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
821 case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
822 default:
823 AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
824 }
825}
826
827/**
828 * Fetches the current BDLE (Buffer Descriptor List Entry) of an AC'97 audio stream.
829 *
830 * @returns IPRT status code.
831 * @param pDevIns The device instance.
832 * @param pStream AC'97 stream to fetch BDLE for.
833 *
834 * @remark Uses CIV as BDLE index.
835 */
836static void ichac97R3StreamFetchBDLE(PPDMDEVINS pDevIns, PAC97STREAM pStream)
837{
838 PAC97BMREGS pRegs = &pStream->Regs;
839
840 AC97BDLE BDLE;
841 PDMDevHlpPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
842 pRegs->bd_valid = 1;
843# ifndef RT_LITTLE_ENDIAN
844# error "Please adapt the code (audio buffers are little endian)!"
845# else
846 pRegs->bd.addr = RT_H2LE_U32(BDLE.addr & ~3);
847 pRegs->bd.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
848# endif
849 pRegs->picb = pRegs->bd.ctl_len & AC97_BD_LEN_MASK;
850 LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes), bup=%RTbool, ioc=%RTbool\n",
851 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
852 pRegs->bd.ctl_len & AC97_BD_LEN_MASK,
853 (pRegs->bd.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
854 RT_BOOL(pRegs->bd.ctl_len & AC97_BD_BUP),
855 RT_BOOL(pRegs->bd.ctl_len & AC97_BD_IOC)));
856}
857
858#endif /* IN_RING3 */
859
860/**
861 * Updates the status register (SR) of an AC'97 audio stream.
862 *
863 * @param pDevIns The device instance.
864 * @param pThis The shared AC'97 state.
865 * @param pStream AC'97 stream to update SR for.
866 * @param new_sr New value for status register (SR).
867 */
868static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
869{
870 PAC97BMREGS pRegs = &pStream->Regs;
871
872 bool fSignal = false;
873 int iIRQL = 0;
874
875 uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
876 uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
877
878 if (new_mask ^ old_mask)
879 {
880 /** @todo Is IRQ deasserted when only one of status bits is cleared? */
881 if (!new_mask)
882 {
883 fSignal = true;
884 iIRQL = 0;
885 }
886 else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
887 {
888 fSignal = true;
889 iIRQL = 1;
890 }
891 else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
892 {
893 fSignal = true;
894 iIRQL = 1;
895 }
896 }
897
898 pRegs->sr = new_sr;
899
900 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
901 pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
902
903 if (fSignal)
904 {
905 static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
906 Assert(pStream->u8SD < AC97_MAX_STREAMS);
907 if (iIRQL)
908 pThis->glob_sta |= s_aMasks[pStream->u8SD];
909 else
910 pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
911
912 LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
913 PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
914 }
915}
916
917/**
918 * Writes a new value to a stream's status register (SR).
919 *
920 * @param pDevIns The device instance.
921 * @param pThis The shared AC'97 device state.
922 * @param pStream Stream to update SR for.
923 * @param u32Val New value to set the stream's SR to.
924 */
925static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
926{
927 PAC97BMREGS pRegs = &pStream->Regs;
928
929 Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
930
931 pRegs->sr |= u32Val & ~(AC97_SR_RO_MASK | AC97_SR_WCLEAR_MASK);
932 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
933}
934
935#ifdef IN_RING3
936
937/**
938 * Returns whether an AC'97 stream is enabled or not.
939 *
940 * @returns IPRT status code.
941 * @param pThisCC The ring-3 AC'97 device state.
942 * @param pStream Stream to return status for.
943 */
944static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
945{
946 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
947 bool fIsEnabled = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
948
949 LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
950 return fIsEnabled;
951}
952
953/**
954 * Enables or disables an AC'97 audio stream.
955 *
956 * @returns IPRT status code.
957 * @param pThis The shared AC'97 state.
958 * @param pThisCC The ring-3 AC'97 state.
959 * @param pStream The AC'97 stream to enable or disable (shared
960 * state).
961 * @param pStreamCC The ring-3 stream state (matching to @a pStream).
962 * @param fEnable Whether to enable or disable the stream.
963 *
964 */
965static int ichac97R3StreamEnable(PAC97STATE pThis, PAC97STATER3 pThisCC,
966 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
967{
968 ichac97R3StreamLock(pStreamCC);
969
970 int rc = VINF_SUCCESS;
971
972# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
973 if (fEnable)
974 rc = ichac97R3StreamAsyncIOCreate(pThis, pStream);
975 if (RT_SUCCESS(rc))
976 ichac97R3StreamAsyncIOLock(pStream);
977# endif
978
979 if (fEnable)
980 {
981 if (pStreamCC->State.pCircBuf)
982 RTCircBufReset(pStreamCC->State.pCircBuf);
983
984 rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
985
986 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
987 { /* likely */ }
988 else
989 {
990 if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
991 {
992 int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
993 &pStreamCC->State.Cfg.Props);
994 AssertRC(rc2);
995 }
996
997 if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
998 {
999 int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
1000 &pStreamCC->State.Cfg.Props);
1001 AssertRC(rc2);
1002 }
1003 }
1004 }
1005 else
1006 rc = ichac97R3StreamClose(pStream);
1007
1008 if (RT_SUCCESS(rc))
1009 {
1010 /* First, enable or disable the stream and the stream's sink, if any. */
1011 rc = AudioMixerSinkCtl(ichac97R3IndexToSink(pThisCC, pStream->u8SD),
1012 fEnable ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
1013 }
1014
1015# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1016 ichac97R3StreamAsyncIOUnlock(pStream);
1017# endif
1018
1019 /* Make sure to leave the lock before (eventually) starting the timer. */
1020 ichac97R3StreamUnlock(pStreamCC);
1021
1022 LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1023 return rc;
1024}
1025
1026/**
1027 * Resets an AC'97 stream.
1028 *
1029 * @param pThis The shared AC'97 state.
1030 * @param pStream The AC'97 stream to reset (shared).
1031 * @param pStreamCC The AC'97 stream to reset (ring-3).
1032 */
1033static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1034{
1035 ichac97R3StreamLock(pStreamCC);
1036
1037 LogFunc(("[SD%RU8]\n", pStream->u8SD));
1038
1039 if (pStreamCC->State.pCircBuf)
1040 RTCircBufReset(pStreamCC->State.pCircBuf);
1041
1042 PAC97BMREGS pRegs = &pStream->Regs;
1043
1044 pRegs->bdbar = 0;
1045 pRegs->civ = 0;
1046 pRegs->lvi = 0;
1047
1048 pRegs->picb = 0;
1049 pRegs->piv = 0;
1050 pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1051 pRegs->bd_valid = 0;
1052
1053 RT_ZERO(pThis->silence);
1054
1055 ichac97R3StreamUnlock(pStreamCC);
1056}
1057
1058/**
1059 * Creates an AC'97 audio stream.
1060 *
1061 * @returns IPRT status code.
1062 * @param pThisCC The ring-3 AC'97 state.
1063 * @param pStream The AC'97 stream to create (shared).
1064 * @param pStreamCC The AC'97 stream to create (ring-3).
1065 * @param u8SD Stream descriptor number to assign.
1066 */
1067static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1068{
1069 LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1070
1071 AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1072 pStream->u8SD = u8SD;
1073 pStreamCC->u8SD = u8SD;
1074
1075 int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1076 AssertRCReturn(rc, rc);
1077
1078 pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1079
1080 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1081 { /* likely */ }
1082 else
1083 {
1084 char szFile[64];
1085
1086 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1087 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1088 else
1089 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1090
1091 char szPath[RTPATH_MAX];
1092 int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1093 0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1094 AssertRC(rc2);
1095 rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1096 AssertRC(rc2);
1097
1098 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1099 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1100 else
1101 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1102
1103 rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1104 0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1105 AssertRC(rc2);
1106
1107 rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1108 AssertRC(rc2);
1109
1110 /* Delete stale debugging files from a former run. */
1111 DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1112 DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1113 }
1114
1115 return rc;
1116}
1117
1118/**
1119 * Destroys an AC'97 audio stream.
1120 *
1121 * @returns IPRT status code.
1122 * @param pThis The shared AC'97 state.
1123 * @param pStream The AC'97 stream to destroy (shared).
1124 * @param pStreamCC The AC'97 stream to destroy (ring-3).
1125 */
1126static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1127{
1128 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1129
1130 ichac97R3StreamClose(pStream);
1131
1132 int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1133 AssertRC(rc2);
1134
1135# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1136 rc2 = ichac97R3StreamAsyncIODestroy(pThis, pStream);
1137 AssertRC(rc2);
1138# else
1139 RT_NOREF(pThis);
1140# endif
1141
1142 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1143 { /* likely */ }
1144 else
1145 {
1146 DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1147 pStreamCC->Dbg.Runtime.pFileStream = NULL;
1148
1149 DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1150 pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1151 }
1152
1153 if (pStreamCC->State.pCircBuf)
1154 {
1155 RTCircBufDestroy(pStreamCC->State.pCircBuf);
1156 pStreamCC->State.pCircBuf = NULL;
1157 }
1158
1159 LogFlowFuncLeave();
1160}
1161
1162/**
1163 * Destroys all AC'97 audio streams of the device.
1164 *
1165 * @param pThis The shared AC'97 state.
1166 * @param pThisCC The ring-3 AC'97 state.
1167 */
1168static void ichac97R3StreamsDestroy(PAC97STATE pThis, PAC97STATER3 pThisCC)
1169{
1170 LogFlowFuncEnter();
1171
1172 /*
1173 * Destroy all AC'97 streams.
1174 */
1175 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1176 ichac97R3StreamDestroy(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1177
1178 /*
1179 * Destroy all sinks.
1180 */
1181
1182 PDMAUDIODSTSRCUNION dstSrc;
1183 if (pThisCC->pSinkLineIn)
1184 {
1185 dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
1186 ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, dstSrc);
1187
1188 AudioMixerSinkDestroy(pThisCC->pSinkLineIn);
1189 pThisCC->pSinkLineIn = NULL;
1190 }
1191
1192 if (pThisCC->pSinkMicIn)
1193 {
1194 dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
1195 ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, dstSrc);
1196
1197 AudioMixerSinkDestroy(pThisCC->pSinkMicIn);
1198 pThisCC->pSinkMicIn = NULL;
1199 }
1200
1201 if (pThisCC->pSinkOut)
1202 {
1203 dstSrc.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
1204 ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, dstSrc);
1205
1206 AudioMixerSinkDestroy(pThisCC->pSinkOut);
1207 pThisCC->pSinkOut = NULL;
1208 }
1209}
1210
1211/**
1212 * Writes audio data from a mixer sink into an AC'97 stream's DMA buffer.
1213 *
1214 * @returns IPRT status code.
1215 * @param pDstStreamCC The AC'97 stream to write to (ring-3).
1216 * @param pSrcMixSink Mixer sink to get audio data to write from.
1217 * @param cbToWrite Number of bytes to write.
1218 * @param pcbWritten Number of bytes written. Optional.
1219 */
1220static int ichac97R3StreamWrite(PAC97STREAMR3 pDstStreamCC, PAUDMIXSINK pSrcMixSink, uint32_t cbToWrite, uint32_t *pcbWritten)
1221{
1222 AssertPtrReturn(pSrcMixSink, VERR_INVALID_POINTER);
1223 AssertReturn(cbToWrite > 0, VERR_INVALID_PARAMETER);
1224 /* pcbWritten is optional. */
1225
1226 PRTCIRCBUF pCircBuf = pDstStreamCC->State.pCircBuf;
1227 AssertPtr(pCircBuf);
1228
1229 uint32_t cbRead = 0;
1230
1231 void *pvDst;
1232 size_t cbDst;
1233 RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
1234
1235 if (cbDst)
1236 {
1237 int rc2 = AudioMixerSinkRead(pSrcMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbRead);
1238 AssertRC(rc2);
1239
1240 if (RT_LIKELY(!pDstStreamCC->Dbg.Runtime.fEnabled))
1241 { /* likely */ }
1242 else
1243 DrvAudioHlpFileWrite(pDstStreamCC->Dbg.Runtime.pFileStream, pvDst, cbRead, 0 /* fFlags */);
1244 }
1245
1246 RTCircBufReleaseWriteBlock(pCircBuf, cbRead);
1247
1248 if (pcbWritten)
1249 *pcbWritten = cbRead;
1250
1251 return VINF_SUCCESS;
1252}
1253
1254/**
1255 * Reads audio data from an AC'97 stream's DMA buffer and writes into a specified mixer sink.
1256 *
1257 * @returns IPRT status code.
1258 * @param pSrcStreamCC AC'97 stream to read audio data from (ring-3).
1259 * @param pDstMixSink Mixer sink to write audio data to.
1260 * @param cbToRead Number of bytes to read.
1261 * @param pcbRead Number of bytes read. Optional.
1262 */
1263static int ichac97R3StreamRead(PAC97STREAMR3 pSrcStreamCC, PAUDMIXSINK pDstMixSink, uint32_t cbToRead, uint32_t *pcbRead)
1264{
1265 AssertPtrReturn(pDstMixSink, VERR_INVALID_POINTER);
1266 AssertReturn(cbToRead > 0, VERR_INVALID_PARAMETER);
1267 /* pcbRead is optional. */
1268
1269 PRTCIRCBUF pCircBuf = pSrcStreamCC->State.pCircBuf;
1270 AssertPtr(pCircBuf);
1271
1272 void *pvSrc;
1273 size_t cbSrc;
1274
1275 int rc = VINF_SUCCESS;
1276
1277 uint32_t cbReadTotal = 0;
1278 uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1279
1280 while (cbLeft)
1281 {
1282 uint32_t cbWritten = 0;
1283
1284 RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1285
1286 if (cbSrc)
1287 {
1288 if (RT_LIKELY(!pSrcStreamCC->Dbg.Runtime.fEnabled))
1289 { /* likely */ }
1290 else
1291 DrvAudioHlpFileWrite(pSrcStreamCC->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1292
1293 rc = AudioMixerSinkWrite(pDstMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1294 AssertRC(rc);
1295
1296 Assert(cbSrc >= cbWritten);
1297 Log3Func(("[SD%RU8] %RU32/%zu bytes read\n", pSrcStreamCC->u8SD, cbWritten, cbSrc));
1298 }
1299
1300 RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1301
1302 if ( !cbWritten /* Nothing written? */
1303 || RT_FAILURE(rc))
1304 break;
1305
1306 Assert(cbLeft >= cbWritten);
1307 cbLeft -= cbWritten;
1308
1309 cbReadTotal += cbWritten;
1310 }
1311
1312 if (pcbRead)
1313 *pcbRead = cbReadTotal;
1314
1315 return rc;
1316}
1317
1318# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1319
1320/**
1321 * Asynchronous I/O thread for an AC'97 stream.
1322 * This will do the heavy lifting work for us as soon as it's getting notified by another thread.
1323 *
1324 * @returns IPRT status code.
1325 * @param hThreadSelf Thread handle.
1326 * @param pvUser User argument. Must be of type PAC97STREAMTHREADCTX.
1327 */
1328static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
1329{
1330 PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)pvUser;
1331 AssertPtr(pCtx);
1332
1333 PAC97STATE pThis = pCtx->pThis;
1334 AssertPtr(pThis);
1335
1336 PAC97STREAM pStream = pCtx->pStream;
1337 AssertPtr(pStream);
1338
1339 PAC97STREAMSTATEAIO pAIO = &pCtx->pStreamCC->State.AIO;
1340
1341 ASMAtomicXchgBool(&pAIO->fStarted, true);
1342
1343 RTThreadUserSignal(hThreadSelf);
1344
1345 /** @todo r=bird: What wasn't mentioned by the original author of this
1346 * code, is that pCtx is now invalid as it must be assumed to be out
1347 * of scope in the parent thread. It is a 'ing stack object! */
1348
1349 LogFunc(("[SD%RU8] Started\n", pStream->u8SD));
1350
1351 for (;;)
1352 {
1353 Log2Func(("[SD%RU8] Waiting ...\n", pStream->u8SD));
1354
1355 int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
1356 if (RT_FAILURE(rc2))
1357 break;
1358
1359 if (ASMAtomicReadBool(&pAIO->fShutdown))
1360 break;
1361
1362 rc2 = RTCritSectEnter(&pAIO->CritSect);
1363 if (RT_SUCCESS(rc2))
1364 {
1365 if (!pAIO->fEnabled)
1366 {
1367 RTCritSectLeave(&pAIO->CritSect);
1368 continue;
1369 }
1370
1371 ichac97R3StreamUpdate(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fInTimer */);
1372
1373 int rc3 = RTCritSectLeave(&pAIO->CritSect);
1374 AssertRC(rc3);
1375 }
1376
1377 AssertRC(rc2);
1378 }
1379
1380 LogFunc(("[SD%RU8] Ended\n", pStream->u8SD));
1381
1382 ASMAtomicXchgBool(&pAIO->fStarted, false);
1383
1384 return VINF_SUCCESS;
1385}
1386
1387/**
1388 * Creates the async I/O thread for a specific AC'97 audio stream.
1389 *
1390 * @returns IPRT status code.
1391 * @param pThis The shared AC'97 state.
1392 * @param pStream AC'97 audio stream to create the async I/O thread for.
1393 */
1394static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STREAM pStream)
1395{
1396 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1397
1398 int rc;
1399
1400 if (!ASMAtomicReadBool(&pAIO->fStarted))
1401 {
1402 pAIO->fShutdown = false;
1403 pAIO->fEnabled = true; /* Enabled by default. */
1404
1405 rc = RTSemEventCreate(&pAIO->Event);
1406 if (RT_SUCCESS(rc))
1407 {
1408 rc = RTCritSectInit(&pAIO->CritSect);
1409 if (RT_SUCCESS(rc))
1410 {
1411/** @todo r=bird: Why is Ctx on the stack? There is no mention of this in
1412 * the thread structure. Besides, you only wait 10seconds, if the
1413 * host is totally overloaded, it may go out of scope before the new
1414 * thread has finished with it and it will like crash and burn.
1415 *
1416 * Also, there is RTThreadCreateF for giving threads complicated
1417 * names.
1418 *
1419 * Why aren't this code using the PDM threads (PDMDevHlpThreadCreate)?
1420 * They would help you with managing stuff like VM suspending, resuming
1421 * and powering off.
1422 *
1423 * Finally, just create the threads at construction time. */
1424 AC97STREAMTHREADCTX Ctx = { pThis, pStream };
1425# error "Busted code! Do not pass a structure living on the parent stack to the poor thread!"
1426
1427 char szThreadName[64];
1428 RTStrPrintf2(szThreadName, sizeof(szThreadName), "ac97AIO%RU8", pStream->u8SD);
1429
1430 rc = RTThreadCreate(&pAIO->Thread, ichac97R3StreamAsyncIOThread, &Ctx,
1431 0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, szThreadName);
1432 if (RT_SUCCESS(rc))
1433 rc = RTThreadUserWait(pAIO->Thread, 10 * 1000 /* 10s timeout */);
1434 }
1435 }
1436 }
1437 else
1438 rc = VINF_SUCCESS;
1439
1440 LogFunc(("[SD%RU8] Returning %Rrc\n", pStream->u8SD, rc));
1441 return rc;
1442}
1443
1444/**
1445 * Lets the stream's async I/O thread know that there is some data to process.
1446 *
1447 * @returns IPRT status code.
1448 * @param pStreamCC The AC'97 stream to notify async I/O thread
1449 * for (ring-3).
1450 */
1451static int ichac97R3StreamAsyncIONotify(PAC97STREAM pStreamCC)
1452{
1453 LogFunc(("[SD%RU8]\n", pStreamCC->u8SD));
1454 return RTSemEventSignal(pStreamCC->State.AIO.Event);
1455}
1456
1457/**
1458 * Destroys the async I/O thread of a specific AC'97 audio stream.
1459 *
1460 * @returns IPRT status code.
1461 * @param pThis The shared AC'97 state.
1462 * @param pStream AC'97 audio stream to destroy the async I/O thread for.
1463 */
1464static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAM pStream)
1465{
1466 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1467
1468 if (!ASMAtomicReadBool(&pAIO->fStarted))
1469 return VINF_SUCCESS;
1470
1471 ASMAtomicWriteBool(&pAIO->fShutdown, true);
1472
1473 int rc = ichac97R3StreamAsyncIONotify(pStreamCC);
1474 AssertRC(rc);
1475
1476 int rcThread;
1477 rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1478 LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
1479
1480 if (RT_SUCCESS(rc))
1481 {
1482 rc = RTCritSectDelete(&pAIO->CritSect);
1483 AssertRC(rc);
1484
1485 rc = RTSemEventDestroy(pAIO->Event);
1486 AssertRC(rc);
1487
1488 pAIO->fStarted = false;
1489 pAIO->fShutdown = false;
1490 pAIO->fEnabled = false;
1491 }
1492
1493 LogFunc(("[SD%RU8] Returning %Rrc\n", pStream->u8SD, rc));
1494 return rc;
1495}
1496
1497/**
1498 * Locks the async I/O thread of a specific AC'97 audio stream.
1499 *
1500 * @param pStream AC'97 stream to lock async I/O thread for.
1501 */
1502static void ichac97R3StreamAsyncIOLock(PAC97STREAM pStream)
1503{
1504 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1505
1506 if (!ASMAtomicReadBool(&pAIO->fStarted))
1507 return;
1508
1509 int rc2 = RTCritSectEnter(&pAIO->CritSect);
1510 AssertRC(rc2);
1511}
1512
1513/**
1514 * Unlocks the async I/O thread of a specific AC'97 audio stream.
1515 *
1516 * @param pStream AC'97 stream to unlock async I/O thread for.
1517 */
1518static void ichac97R3StreamAsyncIOUnlock(PAC97STREAM pStream)
1519{
1520 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1521
1522 if (!ASMAtomicReadBool(&pAIO->fStarted))
1523 return;
1524
1525 int rc2 = RTCritSectLeave(&pAIO->CritSect);
1526 AssertRC(rc2);
1527}
1528
1529#if 0 /* Unused */
1530/**
1531 * Enables (resumes) or disables (pauses) the async I/O thread.
1532 *
1533 * @param pStream AC'97 stream to enable/disable async I/O thread for.
1534 * @param fEnable Whether to enable or disable the I/O thread.
1535 *
1536 * @remarks Does not do locking.
1537 */
1538static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable)
1539{
1540 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1541 ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
1542}
1543#endif
1544# endif /* VBOX_WITH_AUDIO_AC97_ASYNC_IO */
1545
1546# ifdef LOG_ENABLED
1547static void ichac97R3BDLEDumpAll(PPDMDEVINS pDevIns, uint64_t u64BDLBase, uint16_t cBDLE)
1548{
1549 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
1550 if (!u64BDLBase)
1551 return;
1552
1553 uint32_t cbBDLE = 0;
1554 for (uint16_t i = 0; i < cBDLE; i++)
1555 {
1556 AC97BDLE BDLE;
1557 PDMDevHlpPhysRead(pDevIns, u64BDLBase + i * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
1558
1559# ifndef RT_LITTLE_ENDIAN
1560# error "Please adapt the code (audio buffers are little endian)!"
1561# else
1562 BDLE.addr = RT_H2LE_U32(BDLE.addr & ~3);
1563 BDLE.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
1564#endif
1565 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32 [%RU32 bytes], bup:%RTbool, ioc:%RTbool)\n",
1566 i, BDLE.addr,
1567 BDLE.ctl_len & AC97_BD_LEN_MASK,
1568 (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
1569 RT_BOOL(BDLE.ctl_len & AC97_BD_BUP),
1570 RT_BOOL(BDLE.ctl_len & AC97_BD_IOC)));
1571
1572 cbBDLE += (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1; /** @todo r=andy Ditto. */
1573 }
1574
1575 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
1576}
1577# endif /* LOG_ENABLED */
1578
1579/**
1580 * Updates an AC'97 stream by doing its required data transfers.
1581 * The host sink(s) set the overall pace.
1582 *
1583 * This routine is called by both, the synchronous and the asynchronous
1584 * (VBOX_WITH_AUDIO_AC97_ASYNC_IO), implementations.
1585 *
1586 * When running synchronously, the device DMA transfers *and* the mixer sink
1587 * processing is within the device timer.
1588 *
1589 * When running asynchronously, only the device DMA transfers are done in the
1590 * device timer, whereas the mixer sink processing then is done in the stream's
1591 * own async I/O thread. This thread also will call this function
1592 * (with fInTimer set to @c false).
1593 *
1594 * @param pDevIns The device instance.
1595 * @param pThis The shared AC'97 state.
1596 * @param pThisCC The ring-3 AC'97 state.
1597 * @param pStream The AC'97 stream to update (shared).
1598 * @param pStreamCC The AC'97 stream to update (ring-3).
1599 * @param fInTimer Whether to this function was called from the timer
1600 * context or an asynchronous I/O stream thread (if supported).
1601 */
1602static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1603 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fInTimer)
1604{
1605 RT_NOREF(fInTimer);
1606
1607 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1608 AssertPtr(pSink);
1609
1610 if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1611 return;
1612
1613 int rc2;
1614
1615 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT) /* Output (SDO). */
1616 {
1617# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1618 if (fInTimer)
1619# endif
1620 {
1621 const uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1622 if (cbStreamFree)
1623 {
1624 Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1625 pStream->u8SD,
1626 (pStream->Regs.picb << 1), DrvAudioHlpBytesToMilli((pStream->Regs.picb << 1), &pStreamCC->State.Cfg.Props),
1627 cbStreamFree, DrvAudioHlpBytesToMilli(cbStreamFree, &pStreamCC->State.Cfg.Props),
1628 pStreamCC->State.cbTransferChunk, DrvAudioHlpBytesToMilli(pStreamCC->State.cbTransferChunk, &pStreamCC->State.Cfg.Props)));
1629
1630 /* Do the DMA transfer. */
1631 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1632 RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1633 AssertRC(rc2);
1634
1635 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1636 }
1637 }
1638
1639 Log3Func(("[SD%RU8] fInTimer=%RTbool\n", pStream->u8SD, fInTimer));
1640
1641# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1642 rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1643 AssertRC(rc2);
1644# endif
1645
1646# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1647 if (!fInTimer) /* In async I/O thread */
1648 {
1649# endif
1650 const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1651 const uint32_t cbStreamReadable = ichac97R3StreamGetUsed(pStreamCC);
1652 const uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1653
1654 Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32\n", pStream->u8SD, cbSinkWritable, cbStreamReadable));
1655
1656 if (cbToReadFromStream)
1657 {
1658 /* Read (guest output) data and write it to the stream's sink. */
1659 rc2 = ichac97R3StreamRead(pStreamCC, pSink, cbToReadFromStream, NULL /* pcbRead */);
1660 AssertRC(rc2);
1661 }
1662# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1663 }
1664#endif
1665 /* When running synchronously, update the associated sink here.
1666 * Otherwise this will be done in the async I/O thread. */
1667 rc2 = AudioMixerSinkUpdate(pSink);
1668 AssertRC(rc2);
1669 }
1670 else /* Input (SDI). */
1671 {
1672# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1673 if (!fInTimer)
1674 {
1675# endif
1676 rc2 = AudioMixerSinkUpdate(pSink);
1677 AssertRC(rc2);
1678
1679 /* Is the sink ready to be read (host input data) from? If so, by how much? */
1680 uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1681
1682 /* How much (guest input) data is available for writing at the moment for the AC'97 stream? */
1683 uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1684
1685 Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStream->u8SD, cbSinkReadable, cbStreamFree));
1686
1687 /* Do not read more than the sink can provide at the moment.
1688 * The host sets the overall pace. */
1689 if (cbSinkReadable > cbStreamFree)
1690 cbSinkReadable = cbStreamFree;
1691
1692 if (cbSinkReadable)
1693 {
1694 /* Write (guest input) data to the stream which was read from stream's sink before. */
1695 rc2 = ichac97R3StreamWrite(pStreamCC, pSink, cbSinkReadable, NULL /* pcbWritten */);
1696 AssertRC(rc2);
1697 }
1698# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1699 }
1700 else /* fInTimer */
1701 {
1702# endif
1703
1704# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1705 const uint64_t tsNowNs = RTTimeNanoTS();
1706 if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1707 {
1708 rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1709 AssertRC(rc2);
1710
1711 pStreamCC->State.tsLastUpdateNs = tsNowNs;
1712 }
1713# endif
1714
1715 const uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1716 if (cbStreamUsed)
1717 {
1718 /* When running synchronously, do the DMA data transfers here.
1719 * Otherwise this will be done in the stream's async I/O thread. */
1720 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1721 AssertRC(rc2);
1722 }
1723# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1724 }
1725# endif
1726 }
1727}
1728
1729#endif /* IN_RING3 */
1730
1731/**
1732 * Sets a AC'97 mixer control to a specific value.
1733 *
1734 * @returns IPRT status code.
1735 * @param pThis The shared AC'97 state.
1736 * @param uMixerIdx Mixer control to set value for.
1737 * @param uVal Value to set.
1738 */
1739static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1740{
1741 AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1742 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1743
1744 LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1745 uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1746
1747 pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1748 pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1749}
1750
1751/**
1752 * Gets a value from a specific AC'97 mixer control.
1753 *
1754 * @returns Retrieved mixer control value.
1755 * @param pThis The shared AC'97 state.
1756 * @param uMixerIdx Mixer control to get value for.
1757 */
1758static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1759{
1760 AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1761 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1762 UINT16_MAX);
1763 return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1764}
1765
1766#ifdef IN_RING3
1767
1768/**
1769 * Retrieves a specific driver stream of a AC'97 driver.
1770 *
1771 * @returns Pointer to driver stream if found, or NULL if not found.
1772 * @param pDrv Driver to retrieve driver stream for.
1773 * @param enmDir Stream direction to retrieve.
1774 * @param dstSrc Stream destination / source to retrieve.
1775 */
1776static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
1777{
1778 PAC97DRIVERSTREAM pDrvStream = NULL;
1779
1780 if (enmDir == PDMAUDIODIR_IN)
1781 {
1782 LogFunc(("enmRecSource=%d\n", dstSrc.enmSrc));
1783
1784 switch (dstSrc.enmSrc)
1785 {
1786 case PDMAUDIORECSRC_LINE:
1787 pDrvStream = &pDrv->LineIn;
1788 break;
1789 case PDMAUDIORECSRC_MIC:
1790 pDrvStream = &pDrv->MicIn;
1791 break;
1792 default:
1793 AssertFailed();
1794 break;
1795 }
1796 }
1797 else if (enmDir == PDMAUDIODIR_OUT)
1798 {
1799 LogFunc(("enmPlaybackDest=%d\n", dstSrc.enmDst));
1800
1801 switch (dstSrc.enmDst)
1802 {
1803 case PDMAUDIOPLAYBACKDST_FRONT:
1804 pDrvStream = &pDrv->Out;
1805 break;
1806 default:
1807 AssertFailed();
1808 break;
1809 }
1810 }
1811 else
1812 AssertFailed();
1813
1814 return pDrvStream;
1815}
1816
1817/**
1818 * Adds a driver stream to a specific mixer sink.
1819 *
1820 * @returns IPRT status code.
1821 * @param pMixSink Mixer sink to add driver stream to.
1822 * @param pCfg Stream configuration to use.
1823 * @param pDrv Driver stream to add.
1824 */
1825static int ichac97R3MixerAddDrvStream(PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1826{
1827 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1828
1829 PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
1830 if (!pStreamCfg)
1831 return VERR_NO_MEMORY;
1832
1833 if (!RTStrPrintf(pStreamCfg->szName, sizeof(pStreamCfg->szName), "%s", pCfg->szName))
1834 {
1835 DrvAudioHlpStreamCfgFree(pStreamCfg);
1836 return VERR_BUFFER_OVERFLOW;
1837 }
1838
1839 LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1840
1841 int rc;
1842
1843 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->u);
1844 if (pDrvStream)
1845 {
1846 AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1847
1848 PAUDMIXSTREAM pMixStrm;
1849 rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
1850 LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1851 if (RT_SUCCESS(rc))
1852 {
1853 rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1854 LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1855 if (RT_SUCCESS(rc))
1856 {
1857 /* If this is an input stream, always set the latest (added) stream
1858 * as the recording source.
1859 * @todo Make the recording source dynamic (CFGM?). */
1860 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
1861 {
1862 PDMAUDIOBACKENDCFG Cfg;
1863 rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
1864 if (RT_SUCCESS(rc))
1865 {
1866 if (Cfg.cMaxStreamsIn) /* At least one input source available? */
1867 {
1868 rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
1869 LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
1870 pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
1871
1872 if (RT_SUCCESS(rc))
1873 LogRel2(("AC97: Set recording source for '%s' to '%s'\n", pStreamCfg->szName, Cfg.szName));
1874 }
1875 else
1876 LogRel(("AC97: Backend '%s' currently is not offering any recording source for '%s'\n",
1877 Cfg.szName, pStreamCfg->szName));
1878 }
1879 else if (RT_FAILURE(rc))
1880 LogFunc(("LUN#%RU8: Unable to retrieve backend configuratio for '%s', rc=%Rrc\n",
1881 pDrv->uLUN, pStreamCfg->szName, rc));
1882 }
1883 }
1884 }
1885
1886 if (RT_SUCCESS(rc))
1887 pDrvStream->pMixStrm = pMixStrm;
1888 }
1889 else
1890 rc = VERR_INVALID_PARAMETER;
1891
1892 DrvAudioHlpStreamCfgFree(pStreamCfg);
1893
1894 LogFlowFuncLeaveRC(rc);
1895 return rc;
1896}
1897
1898/**
1899 * Adds all current driver streams to a specific mixer sink.
1900 *
1901 * @returns IPRT status code.
1902 * @param pThisCC The ring-3 AC'97 state.
1903 * @param pMixSink Mixer sink to add stream to.
1904 * @param pCfg Stream configuration to use.
1905 */
1906static int ichac97R3MixerAddDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1907{
1908 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1909
1910 if (!DrvAudioHlpStreamCfgIsValid(pCfg))
1911 return VERR_INVALID_PARAMETER;
1912
1913 int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1914 if (RT_FAILURE(rc))
1915 return rc;
1916
1917 PAC97DRIVER pDrv;
1918 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1919 {
1920 int rc2 = ichac97R3MixerAddDrvStream(pMixSink, pCfg, pDrv);
1921 if (RT_FAILURE(rc2))
1922 LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1923
1924 /* Do not pass failure to rc here, as there might be drivers which aren't
1925 * configured / ready yet. */
1926 }
1927
1928 LogFlowFuncLeaveRC(rc);
1929 return rc;
1930}
1931
1932/**
1933 * Adds a specific AC'97 driver to the driver chain.
1934 *
1935 * @return IPRT status code.
1936 * @param pThisCC The ring-3 AC'97 device state.
1937 * @param pDrv The AC'97 driver to add.
1938 */
1939static int ichac97R3MixerAddDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1940{
1941 int rc = VINF_SUCCESS;
1942
1943 if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1944 rc = ichac97R3MixerAddDrvStream(pThisCC->pSinkLineIn, &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1945
1946 if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1947 {
1948 int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkOut, &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1949 if (RT_SUCCESS(rc))
1950 rc = rc2;
1951 }
1952
1953 if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1954 {
1955 int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkMicIn, &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1956 if (RT_SUCCESS(rc))
1957 rc = rc2;
1958 }
1959
1960 return rc;
1961}
1962
1963/**
1964 * Removes a specific AC'97 driver from the driver chain and destroys its
1965 * associated streams.
1966 *
1967 * @param pThisCC The ring-3 AC'97 device state.
1968 * @param pDrv AC'97 driver to remove.
1969 */
1970static void ichac97R3MixerRemoveDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1971{
1972 if (pDrv->MicIn.pMixStrm)
1973 {
1974 if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkMicIn) == pDrv->MicIn.pMixStrm)
1975 AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, NULL);
1976
1977 AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
1978 AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
1979 pDrv->MicIn.pMixStrm = NULL;
1980 }
1981
1982 if (pDrv->LineIn.pMixStrm)
1983 {
1984 if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkLineIn) == pDrv->LineIn.pMixStrm)
1985 AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, NULL);
1986
1987 AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
1988 AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
1989 pDrv->LineIn.pMixStrm = NULL;
1990 }
1991
1992 if (pDrv->Out.pMixStrm)
1993 {
1994 AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
1995 AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
1996 pDrv->Out.pMixStrm = NULL;
1997 }
1998
1999 RTListNodeRemove(&pDrv->Node);
2000}
2001
2002/**
2003 * Removes a driver stream from a specific mixer sink.
2004 *
2005 * @param pMixSink Mixer sink to remove audio streams from.
2006 * @param enmDir Stream direction to remove.
2007 * @param dstSrc Stream destination / source to remove.
2008 * @param pDrv Driver stream to remove.
2009 */
2010static void ichac97R3MixerRemoveDrvStream(PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc, PAC97DRIVER pDrv)
2011{
2012 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, dstSrc);
2013 if (pDrvStream)
2014 {
2015 if (pDrvStream->pMixStrm)
2016 {
2017 AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
2018
2019 AudioMixerStreamDestroy(pDrvStream->pMixStrm);
2020 pDrvStream->pMixStrm = NULL;
2021 }
2022 }
2023}
2024
2025/**
2026 * Removes all driver streams from a specific mixer sink.
2027 *
2028 * @param pThisCC The ring-3 AC'97 state.
2029 * @param pMixSink Mixer sink to remove audio streams from.
2030 * @param enmDir Stream direction to remove.
2031 * @param dstSrc Stream destination / source to remove.
2032 */
2033static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
2034 PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
2035{
2036 AssertPtrReturnVoid(pMixSink);
2037
2038 PAC97DRIVER pDrv;
2039 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
2040 {
2041 ichac97R3MixerRemoveDrvStream(pMixSink, enmDir, dstSrc, pDrv);
2042 }
2043}
2044
2045/**
2046 * Calculates and returns the ticks for a specified amount of bytes.
2047 *
2048 * @returns Calculated ticks
2049 * @param pDevIns The device instance.
2050 * @param pStream AC'97 stream to calculate ticks for (shared).
2051 * @param pStreamCC AC'97 stream to calculate ticks for (ring-3).
2052 * @param cbBytes Bytes to calculate ticks for.
2053 */
2054static uint64_t ichac97R3StreamTransferCalcNext(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2055{
2056 if (!cbBytes)
2057 return 0;
2058
2059 const uint64_t usBytes = DrvAudioHlpBytesToMicro(cbBytes, &pStreamCC->State.Cfg.Props);
2060 const uint64_t cTransferTicks = PDMDevHlpTimerFromMicro(pDevIns, pStream->hTimer, usBytes);
2061
2062 Log3Func(("[SD%RU8] Timer %uHz, cbBytes=%RU32 -> usBytes=%RU64, cTransferTicks=%RU64\n",
2063 pStream->u8SD, pStreamCC->State.uTimerHz, cbBytes, usBytes, cTransferTicks));
2064
2065 return cTransferTicks;
2066}
2067
2068/**
2069 * Updates the next transfer based on a specific amount of bytes.
2070 *
2071 * @param pDevIns The device instance.
2072 * @param pStream The AC'97 stream to update (shared).
2073 * @param pStreamCC The AC'97 stream to update (ring-3).
2074 * @param cbBytes Bytes to update next transfer for.
2075 */
2076static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2077{
2078 if (!cbBytes)
2079 return;
2080
2081 /* Calculate the bytes we need to transfer to / from the stream's DMA per iteration.
2082 * This is bound to the device's Hz rate and thus to the (virtual) timing the device expects. */
2083 pStreamCC->State.cbTransferChunk = cbBytes;
2084
2085 /* Update the transfer ticks. */
2086 pStreamCC->State.cTransferTicks = ichac97R3StreamTransferCalcNext(pDevIns, pStream, pStreamCC,
2087 pStreamCC->State.cbTransferChunk);
2088 Assert(pStreamCC->State.cTransferTicks); /* Paranoia. */
2089}
2090
2091/**
2092 * Opens an AC'97 stream with its current mixer settings.
2093 *
2094 * This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
2095 * the last set sample rate in the AC'97 mixer for this stream.
2096 *
2097 * @returns IPRT status code.
2098 * @param pThis The shared AC'97 device state (shared).
2099 * @param pThisCC The shared AC'97 device state (ring-3).
2100 * @param pStream The AC'97 stream to open (shared).
2101 * @param pStreamCC The AC'97 stream to open (ring-3).
2102 * @param fForce Whether to force re-opening the stream or not.
2103 * Otherwise re-opening only will happen if the PCM properties have changed.
2104 */
2105static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2106{
2107 PDMAUDIOSTREAMCFG Cfg;
2108 RT_ZERO(Cfg);
2109 Cfg.Props.cChannels = 2;
2110 Cfg.Props.cbSample = 2 /* 16-bit */;
2111 Cfg.Props.fSigned = true;
2112 Cfg.Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(Cfg.Props.cbSample, Cfg.Props.cChannels);
2113
2114 int rc = VINF_SUCCESS;
2115 PAUDMIXSINK pMixSink;
2116 switch (pStream->u8SD)
2117 {
2118 case AC97SOUNDSOURCE_PI_INDEX:
2119 {
2120 Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
2121 Cfg.enmDir = PDMAUDIODIR_IN;
2122 Cfg.u.enmSrc = PDMAUDIORECSRC_LINE;
2123 Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2124 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
2125
2126 pMixSink = pThisCC->pSinkLineIn;
2127 break;
2128 }
2129
2130 case AC97SOUNDSOURCE_MC_INDEX:
2131 {
2132 Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
2133 Cfg.enmDir = PDMAUDIODIR_IN;
2134 Cfg.u.enmSrc = PDMAUDIORECSRC_MIC;
2135 Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2136 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
2137
2138 pMixSink = pThisCC->pSinkMicIn;
2139 break;
2140 }
2141
2142 case AC97SOUNDSOURCE_PO_INDEX:
2143 {
2144 Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
2145 Cfg.enmDir = PDMAUDIODIR_OUT;
2146 Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
2147 Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2148 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
2149
2150 pMixSink = pThisCC->pSinkOut;
2151 break;
2152 }
2153
2154 default:
2155 rc = VERR_NOT_SUPPORTED;
2156 pMixSink = NULL;
2157 break;
2158 }
2159
2160 if (RT_SUCCESS(rc))
2161 {
2162 /* Only (re-)create the stream (and driver chain) if we really have to.
2163 * Otherwise avoid this and just reuse it, as this costs performance. */
2164 if ( !DrvAudioHlpPCMPropsAreEqual(&Cfg.Props, &pStreamCC->State.Cfg.Props)
2165 || fForce)
2166 {
2167 LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n",
2168 Cfg.szName, Cfg.Props.uHz, Cfg.Props.cChannels, Cfg.Props.fSigned ? "S" : "U", Cfg.Props.cbSample * 8));
2169
2170 LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
2171
2172 if (Cfg.Props.uHz)
2173 {
2174 Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
2175
2176 /*
2177 * Set the stream's timer Hz rate, based on the PCM properties Hz rate.
2178 */
2179 if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
2180 {
2181 if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
2182 pStreamCC->State.uTimerHz = 200;
2183 else /* Just take the global Hz rate otherwise. */
2184 pStreamCC->State.uTimerHz = pThis->uTimerHz;
2185 }
2186 else
2187 pStreamCC->State.uTimerHz = pThis->uTimerHz;
2188
2189 /* Set scheduling hint (if available). */
2190 if (pStreamCC->State.uTimerHz)
2191 Cfg.Device.cMsSchedulingHint = 1000 /* ms */ / pStreamCC->State.uTimerHz;
2192
2193 if (pStreamCC->State.pCircBuf)
2194 {
2195 RTCircBufDestroy(pStreamCC->State.pCircBuf);
2196 pStreamCC->State.pCircBuf = NULL;
2197 }
2198
2199 rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, DrvAudioHlpMilliToBytes(100 /* ms */, &Cfg.Props)); /** @todo Make this configurable. */
2200 if (RT_SUCCESS(rc))
2201 {
2202 ichac97R3MixerRemoveDrvStreams(pThisCC, pMixSink, Cfg.enmDir, Cfg.u);
2203
2204 rc = ichac97R3MixerAddDrvStreams(pThisCC, pMixSink, &Cfg);
2205 if (RT_SUCCESS(rc))
2206 rc = DrvAudioHlpStreamCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2207 }
2208 }
2209 }
2210 else
2211 LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2212 }
2213
2214 LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2215 return rc;
2216}
2217
2218/**
2219 * Closes an AC'97 stream.
2220 *
2221 * @returns IPRT status code.
2222 * @param pStream The AC'97 stream to close (shared).
2223 */
2224static int ichac97R3StreamClose(PAC97STREAM pStream)
2225{
2226 RT_NOREF(pStream);
2227 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2228 return VINF_SUCCESS;
2229}
2230
2231/**
2232 * Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2233 * side with the current AC'97 mixer settings for this stream.
2234 *
2235 * @returns IPRT status code.
2236 * @param pThis The shared AC'97 device state.
2237 * @param pThisCC The ring-3 AC'97 device state.
2238 * @param pStream The AC'97 stream to re-open (shared).
2239 * @param pStreamCC The AC'97 stream to re-open (ring-3).
2240 * @param fForce Whether to force re-opening the stream or not.
2241 * Otherwise re-opening only will happen if the PCM properties have changed.
2242 */
2243static int ichac97R3StreamReOpen(PAC97STATE pThis, PAC97STATER3 pThisCC,
2244 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2245{
2246 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2247 Assert(pStream->u8SD == pStreamCC->u8SD);
2248 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2249 Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2250
2251 int rc = ichac97R3StreamClose(pStream);
2252 if (RT_SUCCESS(rc))
2253 rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, fForce);
2254
2255 return rc;
2256}
2257
2258/**
2259 * Locks an AC'97 stream for serialized access.
2260 *
2261 * @returns IPRT status code.
2262 * @param pStreamCC The AC'97 stream to lock (ring-3).
2263 */
2264static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2265{
2266 int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2267 AssertRC(rc2);
2268}
2269
2270/**
2271 * Unlocks a formerly locked AC'97 stream.
2272 *
2273 * @returns IPRT status code.
2274 * @param pStreamCC The AC'97 stream to unlock (ring-3).
2275 */
2276static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2277{
2278 int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2279 AssertRC(rc2);
2280}
2281
2282/**
2283 * Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2284 *
2285 * @returns Available data (in bytes).
2286 * @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2287 */
2288static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2289{
2290 if (!pStreamCC->State.pCircBuf)
2291 return 0;
2292
2293 return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2294}
2295
2296/**
2297 * Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2298 *
2299 * @returns Free data (in bytes).
2300 * @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2301 */
2302static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2303{
2304 if (!pStreamCC->State.pCircBuf)
2305 return 0;
2306
2307 return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2308}
2309
2310/**
2311 * Sets the volume of a specific AC'97 mixer control.
2312 *
2313 * This currently only supports attenuation -- gain support is currently not implemented.
2314 *
2315 * @returns IPRT status code.
2316 * @param pThis The shared AC'97 state.
2317 * @param pThisCC The ring-3 AC'97 state.
2318 * @param index AC'97 mixer index to set volume for.
2319 * @param enmMixerCtl Corresponding audio mixer sink.
2320 * @param uVal Volume value to set.
2321 */
2322static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2323{
2324 /*
2325 * From AC'97 SoundMax Codec AD1981A/AD1981B:
2326 * "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2327 * D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2328 * set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2329 * these bits are set to 1."
2330 *
2331 * Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2332 * control and the optional 6th bit is not used. Note that this logic only applies to the
2333 * master volume controls.
2334 */
2335 if (index == AC97_Master_Volume_Mute || index == AC97_Headphone_Volume_Mute || index == AC97_Master_Volume_Mono_Mute)
2336 {
2337 if (uVal & RT_BIT(5)) /* D5 bit set? */
2338 uVal |= RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0);
2339 if (uVal & RT_BIT(13)) /* D13 bit set? */
2340 uVal |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8);
2341 }
2342
2343 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2344 uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2345 uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2346
2347 /* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2348 * volume controls, 0 means 12dB gain and 8 means unity gain.
2349 */
2350 if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2351 {
2352# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2353 /* NB: Currently there is no gain support, only attenuation. */
2354 uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2355 uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2356# endif
2357 }
2358 Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2359 Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2360
2361 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2362 LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2363
2364 /*
2365 * For AC'97 volume controls, each additional step means -1.5dB attenuation with
2366 * zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2367 * steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2368 */
2369 uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2370 uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2371
2372 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2373
2374 int rc = VINF_SUCCESS;
2375
2376 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2377 {
2378 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2379 PAUDMIXSINK pSink = NULL;
2380
2381 switch (enmMixerCtl)
2382 {
2383 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2384 rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2385 break;
2386
2387 case PDMAUDIOMIXERCTL_FRONT:
2388 pSink = pThisCC->pSinkOut;
2389 break;
2390
2391 case PDMAUDIOMIXERCTL_MIC_IN:
2392 case PDMAUDIOMIXERCTL_LINE_IN:
2393 /* These are recognized but do nothing. */
2394 break;
2395
2396 default:
2397 AssertFailed();
2398 rc = VERR_NOT_SUPPORTED;
2399 break;
2400 }
2401
2402 if (pSink)
2403 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2404 }
2405
2406 ichac97MixerSet(pThis, index, uVal);
2407
2408 if (RT_FAILURE(rc))
2409 LogFlowFunc(("Failed with %Rrc\n", rc));
2410
2411 return rc;
2412}
2413
2414/**
2415 * Sets the gain of a specific AC'97 recording control.
2416 *
2417 * NB: gain support is currently not implemented in PDM audio.
2418 *
2419 * @returns IPRT status code.
2420 * @param pThis The shared AC'97 state.
2421 * @param pThisCC The ring-3 AC'97 state.
2422 * @param index AC'97 mixer index to set volume for.
2423 * @param enmMixerCtl Corresponding audio mixer sink.
2424 * @param uVal Volume value to set.
2425 */
2426static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2427{
2428 /*
2429 * For AC'97 recording controls, each additional step means +1.5dB gain with
2430 * zero being 0dB gain and 15 being +22.5dB gain.
2431 */
2432 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2433 uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2434 uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2435
2436 Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2437 Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2438
2439 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2440 LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2441
2442 uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2443 uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2444
2445 /* We do not currently support gain. Since AC'97 does not support attenuation
2446 * for the recording input, the best we can do is set the maximum volume.
2447 */
2448# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2449 /* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2450 * support attenuation for the recording inputs, the best we can do is set the
2451 * maximum volume.
2452 */
2453 lVol = rVol = PDMAUDIO_VOLUME_MAX;
2454# endif
2455
2456 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2457
2458 int rc = VINF_SUCCESS;
2459
2460 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2461 {
2462 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2463 PAUDMIXSINK pSink = NULL;
2464
2465 switch (enmMixerCtl)
2466 {
2467 case PDMAUDIOMIXERCTL_MIC_IN:
2468 pSink = pThisCC->pSinkMicIn;
2469 break;
2470
2471 case PDMAUDIOMIXERCTL_LINE_IN:
2472 pSink = pThisCC->pSinkLineIn;
2473 break;
2474
2475 default:
2476 AssertFailed();
2477 rc = VERR_NOT_SUPPORTED;
2478 break;
2479 }
2480
2481 if (pSink) {
2482 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2483 /* There is only one AC'97 recording gain control. If line in
2484 * is changed, also update the microphone. If the optional dedicated
2485 * microphone is changed, only change that.
2486 * NB: The codecs we support do not have the dedicated microphone control.
2487 */
2488 if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2489 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2490 }
2491 }
2492
2493 ichac97MixerSet(pThis, index, uVal);
2494
2495 if (RT_FAILURE(rc))
2496 LogFlowFunc(("Failed with %Rrc\n", rc));
2497
2498 return rc;
2499}
2500
2501/**
2502 * Converts an AC'97 recording source index to a PDM audio recording source.
2503 *
2504 * @returns PDM audio recording source.
2505 * @param uIdx AC'97 index to convert.
2506 */
2507static PDMAUDIORECSRC ichac97R3IdxToRecSource(uint8_t uIdx)
2508{
2509 switch (uIdx)
2510 {
2511 case AC97_REC_MIC: return PDMAUDIORECSRC_MIC;
2512 case AC97_REC_CD: return PDMAUDIORECSRC_CD;
2513 case AC97_REC_VIDEO: return PDMAUDIORECSRC_VIDEO;
2514 case AC97_REC_AUX: return PDMAUDIORECSRC_AUX;
2515 case AC97_REC_LINE_IN: return PDMAUDIORECSRC_LINE;
2516 case AC97_REC_PHONE: return PDMAUDIORECSRC_PHONE;
2517 default:
2518 break;
2519 }
2520
2521 LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2522 return PDMAUDIORECSRC_MIC;
2523}
2524
2525/**
2526 * Converts a PDM audio recording source to an AC'97 recording source index.
2527 *
2528 * @returns AC'97 recording source index.
2529 * @param enmRecSrc PDM audio recording source to convert.
2530 */
2531static uint8_t ichac97R3RecSourceToIdx(PDMAUDIORECSRC enmRecSrc)
2532{
2533 switch (enmRecSrc)
2534 {
2535 case PDMAUDIORECSRC_MIC: return AC97_REC_MIC;
2536 case PDMAUDIORECSRC_CD: return AC97_REC_CD;
2537 case PDMAUDIORECSRC_VIDEO: return AC97_REC_VIDEO;
2538 case PDMAUDIORECSRC_AUX: return AC97_REC_AUX;
2539 case PDMAUDIORECSRC_LINE: return AC97_REC_LINE_IN;
2540 case PDMAUDIORECSRC_PHONE: return AC97_REC_PHONE;
2541 default:
2542 break;
2543 }
2544
2545 LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2546 return AC97_REC_MIC;
2547}
2548
2549/**
2550 * Returns the audio direction of a specified stream descriptor.
2551 *
2552 * @return Audio direction.
2553 */
2554DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2555{
2556 switch (uSD)
2557 {
2558 case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2559 case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2560 case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2561 }
2562
2563 AssertFailed();
2564 return PDMAUDIODIR_UNKNOWN;
2565}
2566
2567#endif /* IN_RING3 */
2568
2569#ifdef IN_RING3
2570
2571/**
2572 * Performs an AC'97 mixer record select to switch to a different recording
2573 * source.
2574 *
2575 * @param pThis The shared AC'97 state.
2576 * @param val AC'97 recording source index to set.
2577 */
2578static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2579{
2580 uint8_t rs = val & AC97_REC_MASK;
2581 uint8_t ls = (val >> 8) & AC97_REC_MASK;
2582
2583 const PDMAUDIORECSRC ars = ichac97R3IdxToRecSource(rs);
2584 const PDMAUDIORECSRC als = ichac97R3IdxToRecSource(ls);
2585
2586 rs = ichac97R3RecSourceToIdx(ars);
2587 ls = ichac97R3RecSourceToIdx(als);
2588
2589 LogRel(("AC97: Record select to left=%s, right=%s\n", DrvAudioHlpRecSrcToStr(ars), DrvAudioHlpRecSrcToStr(als)));
2590
2591 ichac97MixerSet(pThis, AC97_Record_Select, rs | (ls << 8));
2592}
2593
2594/**
2595 * Resets the AC'97 mixer.
2596 *
2597 * @returns IPRT status code.
2598 * @param pThis The shared AC'97 state.
2599 * @param pThisCC The ring-3 AC'97 state.
2600 */
2601static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2602{
2603 LogFlowFuncEnter();
2604
2605 RT_ZERO(pThis->mixer_data);
2606
2607 /* Note: Make sure to reset all registers first before bailing out on error. */
2608
2609 ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2610 ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2611 ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2612
2613 ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2614 ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2615 ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2616 ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2617 ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2618 ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2619 ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2620 ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2621
2622 /* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2623 const uint16_t fEAID = AC97_EAID_REV1 | AC97_EACS_VRA | AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2624 const uint16_t fEACS = AC97_EACS_VRA | AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2625
2626 LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2627
2628 ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2629 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2630 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2631 ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2632 ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2633 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2634 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2635
2636 if (pThis->enmCodecModel == AC97CODEC_AD1980)
2637 {
2638 /* Analog Devices 1980 (AD1980) */
2639 ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2640 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2641 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2642 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2643 }
2644 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2645 {
2646 /* Analog Devices 1981B (AD1981B) */
2647 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2648 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2649 }
2650 else
2651 {
2652 /* Sigmatel 9700 (STAC9700) */
2653 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2654 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2655 }
2656 ichac97R3MixerRecordSelect(pThis, 0);
2657
2658 /* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2659 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2660
2661 /* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2662 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2663 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2664 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2665
2666 /* The default for record controls is 0 dB gain with mute on. */
2667 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2668 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2669
2670 return VINF_SUCCESS;
2671}
2672
2673# if 0 /* Unused */
2674static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2675{
2676 LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2677
2678 if (!(pThis->bup_flag & BUP_SET))
2679 {
2680 if (pThis->bup_flag & BUP_LAST)
2681 {
2682 unsigned int i;
2683 uint32_t *p = (uint32_t*)pThis->silence;
2684 for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2685 *p++ = pThis->last_samp;
2686 }
2687 else
2688 RT_ZERO(pThis->silence);
2689
2690 pThis->bup_flag |= BUP_SET;
2691 }
2692
2693 while (cbElapsed)
2694 {
2695 uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2696 uint32_t cbWrittenToStream;
2697
2698 int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2699 pThis->silence, cbToWrite, &cbWrittenToStream);
2700 if (RT_SUCCESS(rc2))
2701 {
2702 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2703 LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2704 }
2705
2706 /* Always report all data as being written;
2707 * backends who were not able to catch up have to deal with it themselves. */
2708 Assert(cbElapsed >= cbToWrite);
2709 cbElapsed -= cbToWrite;
2710 }
2711}
2712# endif /* Unused */
2713
2714/**
2715 * @callback_method_impl{FNTMTIMERDEV,
2716 * Timer callback which handles the audio data transfers on a periodic basis.}
2717 */
2718static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2719{
2720 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2721 STAM_PROFILE_START(&pThis->StatTimer, a);
2722 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2723 PAC97STREAM pStream = (PAC97STREAM)pvUser;
2724 PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2725 RT_NOREF(pTimer);
2726
2727 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2728 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2729 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2730
2731 ichac97R3StreamUpdate(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fInTimer */);
2732
2733 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2734 if (pSink && AudioMixerSinkIsActive(pSink))
2735 {
2736 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC, pStream->Regs.picb << 1); /** @todo r=andy Assumes 16-bit samples. */
2737 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2738 }
2739
2740 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2741}
2742
2743
2744/**
2745 * Sets the virtual device timer to a new expiration time.
2746 *
2747 * @param pDevIns The device instance.
2748 * @param pStream AC'97 stream to set timer for.
2749 * @param cTicksToDeadline The number of ticks to the new deadline.
2750 *
2751 * @remarks This used to be more complicated a long time ago...
2752 */
2753DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2754{
2755 int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /*pu64Now*/);
2756 AssertRC(rc);
2757}
2758
2759
2760/**
2761 * Transfers data of an AC'97 stream according to its usage (input / output).
2762 *
2763 * For an SDO (output) stream this means reading DMA data from the device to
2764 * the AC'97 stream's internal FIFO buffer.
2765 *
2766 * For an SDI (input) stream this is reading audio data from the AC'97 stream's
2767 * internal FIFO buffer and writing it as DMA data to the device.
2768 *
2769 * @returns IPRT status code.
2770 * @param pDevIns The device instance.
2771 * @param pThis The shared AC'97 state.
2772 * @param pStream The AC'97 stream to update (shared).
2773 * @param pStreamCC The AC'97 stream to update (ring-3).
2774 * @param cbToProcessMax Maximum of data (in bytes) to process.
2775 */
2776static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2777 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2778{
2779 if (!cbToProcessMax)
2780 return VINF_SUCCESS;
2781
2782#ifdef VBOX_STRICT
2783 const unsigned cbFrame = DrvAudioHlpPCMPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2784#endif
2785
2786 /* Make sure to only process an integer number of audio frames. */
2787 Assert(cbToProcessMax % cbFrame == 0);
2788
2789 ichac97R3StreamLock(pStreamCC);
2790
2791 PAC97BMREGS pRegs = &pStream->Regs;
2792
2793 if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2794 {
2795 if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2796 {
2797 switch (pStream->u8SD)
2798 {
2799 case AC97SOUNDSOURCE_PO_INDEX:
2800 /*ichac97R3WriteBUP(pThis, cbToProcess);*/
2801 break;
2802
2803 default:
2804 break;
2805 }
2806 }
2807
2808 ichac97R3StreamUnlock(pStreamCC);
2809 return VINF_SUCCESS;
2810 }
2811
2812 /* BCIS flag still set? Skip iteration. */
2813 if (pRegs->sr & AC97_SR_BCIS)
2814 {
2815 Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2816
2817 ichac97R3StreamUnlock(pStreamCC);
2818 return VINF_SUCCESS;
2819 }
2820
2821 uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2822 uint32_t cbProcessedTotal = 0;
2823
2824 PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2825 AssertPtr(pCircBuf);
2826
2827 int rc = VINF_SUCCESS;
2828
2829 Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2830
2831 while (cbLeft)
2832 {
2833 if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2834 {
2835 Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2836 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2837 if (pRegs->civ == pRegs->lvi)
2838 {
2839 pRegs->sr |= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2840 pThis->bup_flag = 0;
2841
2842 rc = VINF_EOF;
2843 break;
2844 }
2845
2846 pRegs->sr &= ~AC97_SR_CELV;
2847 pRegs->civ = pRegs->piv;
2848 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2849
2850 ichac97R3StreamFetchBDLE(pDevIns, pStream);
2851 continue;
2852 }
2853
2854 uint32_t cbChunk = cbLeft;
2855
2856 switch (pStream->u8SD)
2857 {
2858 case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2859 {
2860 void *pvDst;
2861 size_t cbDst;
2862
2863 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2864
2865 if (cbDst)
2866 {
2867 int rc2 = PDMDevHlpPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2868 AssertRC(rc2);
2869
2870 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2871 { /* likely */ }
2872 else
2873 DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2874 }
2875
2876 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2877
2878 cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2879 break;
2880 }
2881
2882 case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2883 case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2884 {
2885 void *pvSrc;
2886 size_t cbSrc;
2887
2888 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2889
2890 if (cbSrc)
2891 {
2892/** @todo r=bird: Just curious, DevHDA uses PDMDevHlpPCIPhysWrite here. So,
2893 * is AC97 not subject to PCI busmaster enable/disable? */
2894 int rc2 = PDMDevHlpPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2895 AssertRC(rc2);
2896
2897 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2898 { /* likely */ }
2899 else
2900 DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2901 }
2902
2903 RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2904
2905 cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2906 break;
2907 }
2908
2909 default:
2910 AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2911 rc = VERR_NOT_SUPPORTED;
2912 break;
2913 }
2914
2915 if (RT_FAILURE(rc))
2916 break;
2917
2918 if (cbChunk)
2919 {
2920 cbProcessedTotal += cbChunk;
2921 Assert(cbProcessedTotal <= cbToProcessMax);
2922 Assert(cbLeft >= cbChunk);
2923 cbLeft -= cbChunk;
2924 Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2925
2926 pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2927 pRegs->bd.addr += cbChunk;
2928 }
2929
2930 LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2931 pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2932
2933 if (!pRegs->picb)
2934 {
2935 uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2936
2937 if (pRegs->bd.ctl_len & AC97_BD_IOC)
2938 {
2939 new_sr |= AC97_SR_BCIS;
2940 }
2941
2942 if (pRegs->civ == pRegs->lvi)
2943 {
2944 /* Did we run out of data? */
2945 LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2946
2947 new_sr |= AC97_SR_LVBCI | AC97_SR_DCH | AC97_SR_CELV;
2948 pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2949
2950 rc = VINF_EOF;
2951 }
2952 else
2953 {
2954 pRegs->civ = pRegs->piv;
2955 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2956 ichac97R3StreamFetchBDLE(pDevIns, pStream);
2957 }
2958
2959 ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2960 }
2961
2962 if (/* All data processed? */
2963 rc == VINF_EOF
2964 /* ... or an error occurred? */
2965 || RT_FAILURE(rc))
2966 {
2967 break;
2968 }
2969 }
2970
2971 ichac97R3StreamUnlock(pStreamCC);
2972
2973 LogFlowFuncLeaveRC(rc);
2974 return rc;
2975}
2976
2977#endif /* IN_RING3 */
2978
2979
2980/**
2981 * @callback_method_impl{FNIOMIOPORTNEWIN}
2982 */
2983static DECLCALLBACK(VBOXSTRICTRC)
2984ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2985{
2986 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2987 RT_NOREF(pvUser);
2988
2989 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
2990
2991 /* Get the index of the NABMBAR port. */
2992 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
2993 && offPort != AC97_GLOB_CNT)
2994 {
2995 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
2996 PAC97BMREGS pRegs = &pStream->Regs;
2997
2998 switch (cb)
2999 {
3000 case 1:
3001 switch (offPort & AC97_NABM_OFF_MASK)
3002 {
3003 case AC97_NABM_OFF_CIV:
3004 /* Current Index Value Register */
3005 *pu32 = pRegs->civ;
3006 Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3007 break;
3008 case AC97_NABM_OFF_LVI:
3009 /* Last Valid Index Register */
3010 *pu32 = pRegs->lvi;
3011 Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3012 break;
3013 case AC97_NABM_OFF_PIV:
3014 /* Prefetched Index Value Register */
3015 *pu32 = pRegs->piv;
3016 Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3017 break;
3018 case AC97_NABM_OFF_CR:
3019 /* Control Register */
3020 *pu32 = pRegs->cr;
3021 Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3022 break;
3023 case AC97_NABM_OFF_SR:
3024 /* Status Register (lower part) */
3025 *pu32 = RT_LO_U8(pRegs->sr);
3026 Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3027 break;
3028 default:
3029 *pu32 = UINT32_MAX;
3030 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3031 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3032 break;
3033 }
3034 break;
3035
3036 case 2:
3037 switch (offPort & AC97_NABM_OFF_MASK)
3038 {
3039 case AC97_NABM_OFF_SR:
3040 /* Status Register */
3041 *pu32 = pRegs->sr;
3042 Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3043 break;
3044 case AC97_NABM_OFF_PICB:
3045 /* Position in Current Buffer */
3046 *pu32 = pRegs->picb;
3047 Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3048 break;
3049 default:
3050 *pu32 = UINT32_MAX;
3051 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3052 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3053 break;
3054 }
3055 break;
3056
3057 case 4:
3058 switch (offPort & AC97_NABM_OFF_MASK)
3059 {
3060 case AC97_NABM_OFF_BDBAR:
3061 /* Buffer Descriptor Base Address Register */
3062 *pu32 = pRegs->bdbar;
3063 Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3064 break;
3065 case AC97_NABM_OFF_CIV:
3066 /* 32-bit access: Current Index Value Register +
3067 * Last Valid Index Register +
3068 * Status Register */
3069 *pu32 = pRegs->civ | (pRegs->lvi << 8) | (pRegs->sr << 16); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3070 Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
3071 AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
3072 break;
3073 case AC97_NABM_OFF_PICB:
3074 /* 32-bit access: Position in Current Buffer Register +
3075 * Prefetched Index Value Register +
3076 * Control Register */
3077 *pu32 = pRegs->picb | (pRegs->piv << 16) | (pRegs->cr << 24); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3078 Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
3079 AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
3080 break;
3081
3082 default:
3083 *pu32 = UINT32_MAX;
3084 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3085 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3086 break;
3087 }
3088 break;
3089
3090 default:
3091 DEVAC97_UNLOCK(pDevIns, pThis);
3092 AssertFailed();
3093 return VERR_IOM_IOPORT_UNUSED;
3094 }
3095 }
3096 else
3097 {
3098 switch (cb)
3099 {
3100 case 1:
3101 switch (offPort)
3102 {
3103 case AC97_CAS:
3104 /* Codec Access Semaphore Register */
3105 Log3Func(("CAS %d\n", pThis->cas));
3106 *pu32 = pThis->cas;
3107 pThis->cas = 1;
3108 break;
3109 default:
3110 *pu32 = UINT32_MAX;
3111 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3112 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3113 break;
3114 }
3115 break;
3116
3117 case 2:
3118 *pu32 = UINT32_MAX;
3119 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3120 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3121 break;
3122
3123 case 4:
3124 switch (offPort)
3125 {
3126 case AC97_GLOB_CNT:
3127 /* Global Control */
3128 *pu32 = pThis->glob_cnt;
3129 Log3Func(("glob_cnt -> %#x\n", *pu32));
3130 break;
3131 case AC97_GLOB_STA:
3132 /* Global Status */
3133 *pu32 = pThis->glob_sta | AC97_GS_S0CR;
3134 Log3Func(("glob_sta -> %#x\n", *pu32));
3135 break;
3136 default:
3137 *pu32 = UINT32_MAX;
3138 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3139 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3140 break;
3141 }
3142 break;
3143
3144 default:
3145 DEVAC97_UNLOCK(pDevIns, pThis);
3146 AssertFailed();
3147 return VERR_IOM_IOPORT_UNUSED;
3148 }
3149 }
3150
3151 DEVAC97_UNLOCK(pDevIns, pThis);
3152 return VINF_SUCCESS;
3153}
3154
3155/**
3156 * @callback_method_impl{FNIOMIOPORTNEWOUT}
3157 */
3158static DECLCALLBACK(VBOXSTRICTRC)
3159ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3160{
3161 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3162#ifdef IN_RING3
3163 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3164#endif
3165 RT_NOREF(pvUser);
3166
3167 VBOXSTRICTRC rc = VINF_SUCCESS;
3168 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3169 && offPort != AC97_GLOB_CNT)
3170 {
3171#ifdef IN_RING3
3172 PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
3173#endif
3174 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3175 PAC97BMREGS pRegs = &pStream->Regs;
3176
3177 DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
3178 switch (cb)
3179 {
3180 case 1:
3181 switch (offPort & AC97_NABM_OFF_MASK)
3182 {
3183 /*
3184 * Last Valid Index.
3185 */
3186 case AC97_NABM_OFF_LVI:
3187 if ( (pRegs->cr & AC97_CR_RPBM)
3188 && (pRegs->sr & AC97_SR_DCH))
3189 {
3190#ifdef IN_RING3
3191 pRegs->sr &= ~(AC97_SR_DCH | AC97_SR_CELV);
3192 pRegs->civ = pRegs->piv;
3193 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3194#else
3195 rc = VINF_IOM_R3_IOPORT_WRITE;
3196#endif
3197 }
3198 pRegs->lvi = u32 % AC97_MAX_BDLE;
3199 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3200 break;
3201
3202 /*
3203 * Control Registers.
3204 */
3205 case AC97_NABM_OFF_CR:
3206#ifdef IN_RING3
3207 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3208 if (u32 & AC97_CR_RR) /* Busmaster reset. */
3209 {
3210 Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3211
3212 /* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3213 Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3214
3215 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3216 ichac97R3StreamReset(pThis, pStream, pStreamCC);
3217
3218 ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3219 }
3220 else
3221 {
3222 pRegs->cr = u32 & AC97_CR_VALID_MASK;
3223
3224 if (!(pRegs->cr & AC97_CR_RPBM))
3225 {
3226 Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3227
3228 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3229
3230 pRegs->sr |= AC97_SR_DCH;
3231 }
3232 else
3233 {
3234 Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3235
3236 pRegs->civ = pRegs->piv;
3237 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3238
3239 pRegs->sr &= ~AC97_SR_DCH;
3240
3241 /* Fetch the initial BDLE descriptor. */
3242 ichac97R3StreamFetchBDLE(pDevIns, pStream);
3243# ifdef LOG_ENABLED
3244 ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1);
3245# endif
3246 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3247
3248 /* Arm the timer for this stream. */
3249 /** @todo r=bird: This function returns bool, not VBox status! */
3250 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3251 }
3252 }
3253#else /* !IN_RING3 */
3254 rc = VINF_IOM_R3_IOPORT_WRITE;
3255#endif
3256 break;
3257
3258 /*
3259 * Status Registers.
3260 */
3261 case AC97_NABM_OFF_SR:
3262 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3263 break;
3264
3265 default:
3266 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3267 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3268 break;
3269 }
3270 break;
3271
3272 case 2:
3273 switch (offPort & AC97_NABM_OFF_MASK)
3274 {
3275 case AC97_NABM_OFF_SR:
3276 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3277 break;
3278 default:
3279 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3280 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3281 break;
3282 }
3283 break;
3284
3285 case 4:
3286 switch (offPort & AC97_NABM_OFF_MASK)
3287 {
3288 case AC97_NABM_OFF_BDBAR:
3289 /* Buffer Descriptor list Base Address Register */
3290 pRegs->bdbar = u32 & ~3;
3291 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3292 break;
3293 default:
3294 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3295 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3296 break;
3297 }
3298 break;
3299
3300 default:
3301 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3302 break;
3303 }
3304 DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3305 }
3306 else
3307 {
3308 switch (cb)
3309 {
3310 case 1:
3311 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3312 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3313 break;
3314
3315 case 2:
3316 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3317 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3318 break;
3319
3320 case 4:
3321 switch (offPort)
3322 {
3323 case AC97_GLOB_CNT:
3324 /* Global Control */
3325 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3326 if (u32 & AC97_GC_WR)
3327 ichac97WarmReset(pThis);
3328 if (u32 & AC97_GC_CR)
3329 ichac97ColdReset(pThis);
3330 if (!(u32 & (AC97_GC_WR | AC97_GC_CR)))
3331 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3332 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3333 DEVAC97_UNLOCK(pDevIns, pThis);
3334 break;
3335 case AC97_GLOB_STA:
3336 /* Global Status */
3337 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3338 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3339 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3340 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3341 DEVAC97_UNLOCK(pDevIns, pThis);
3342 break;
3343 default:
3344 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3345 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3346 break;
3347 }
3348 break;
3349
3350 default:
3351 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3352 break;
3353 }
3354 }
3355
3356 return rc;
3357}
3358
3359/**
3360 * @callback_method_impl{FNIOMIOPORTNEWIN}
3361 */
3362static DECLCALLBACK(VBOXSTRICTRC)
3363ichac97IoPortNamRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
3364{
3365 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3366 RT_NOREF(pvUser);
3367 Assert(offPort < 256);
3368
3369 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3370
3371 VBOXSTRICTRC rc = VINF_SUCCESS;
3372 switch (cb)
3373 {
3374 case 1:
3375 {
3376 LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3377 pThis->cas = 0;
3378 *pu32 = UINT32_MAX;
3379 break;
3380 }
3381
3382 case 2:
3383 {
3384 pThis->cas = 0;
3385 *pu32 = ichac97MixerGet(pThis, offPort);
3386 break;
3387 }
3388
3389 case 4:
3390 {
3391 LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3392 pThis->cas = 0;
3393 *pu32 = UINT32_MAX;
3394 break;
3395 }
3396
3397 default:
3398 {
3399 AssertFailed();
3400 rc = VERR_IOM_IOPORT_UNUSED;
3401 }
3402 }
3403
3404 DEVAC97_UNLOCK(pDevIns, pThis);
3405 return rc;
3406}
3407
3408/**
3409 * @callback_method_impl{FNIOMIOPORTNEWOUT}
3410 */
3411static DECLCALLBACK(VBOXSTRICTRC)
3412ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3413{
3414 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3415#ifdef IN_RING3
3416 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3417#endif
3418 RT_NOREF(pvUser);
3419
3420 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3421
3422 VBOXSTRICTRC rc = VINF_SUCCESS;
3423 switch (cb)
3424 {
3425 case 1:
3426 {
3427 LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3428 pThis->cas = 0;
3429 break;
3430 }
3431
3432 case 2:
3433 {
3434 pThis->cas = 0;
3435 switch (offPort)
3436 {
3437 case AC97_Reset:
3438#ifdef IN_RING3
3439 ichac97R3Reset(pDevIns);
3440#else
3441 rc = VINF_IOM_R3_IOPORT_WRITE;
3442#endif
3443 break;
3444 case AC97_Powerdown_Ctrl_Stat:
3445 u32 &= ~0xf;
3446 u32 |= ichac97MixerGet(pThis, offPort) & 0xf;
3447 ichac97MixerSet(pThis, offPort, u32);
3448 break;
3449 case AC97_Master_Volume_Mute:
3450 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3451 {
3452 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3453 break; /* Register controls surround (rear), do nothing. */
3454 }
3455#ifdef IN_RING3
3456 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3457#else
3458 rc = VINF_IOM_R3_IOPORT_WRITE;
3459#endif
3460 break;
3461 case AC97_Headphone_Volume_Mute:
3462 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3463 {
3464 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3465 {
3466 /* Register controls PCM (front) outputs. */
3467#ifdef IN_RING3
3468 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3469#else
3470 rc = VINF_IOM_R3_IOPORT_WRITE;
3471#endif
3472 }
3473 }
3474 break;
3475 case AC97_PCM_Out_Volume_Mute:
3476#ifdef IN_RING3
3477 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3478#else
3479 rc = VINF_IOM_R3_IOPORT_WRITE;
3480#endif
3481 break;
3482 case AC97_Line_In_Volume_Mute:
3483#ifdef IN_RING3
3484 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3485#else
3486 rc = VINF_IOM_R3_IOPORT_WRITE;
3487#endif
3488 break;
3489 case AC97_Record_Select:
3490#ifdef IN_RING3
3491 ichac97R3MixerRecordSelect(pThis, u32);
3492#else
3493 rc = VINF_IOM_R3_IOPORT_WRITE;
3494#endif
3495 break;
3496 case AC97_Record_Gain_Mute:
3497#ifdef IN_RING3
3498 /* Newer Ubuntu guests rely on that when controlling gain and muting
3499 * the recording (capturing) levels. */
3500 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3501#else
3502 rc = VINF_IOM_R3_IOPORT_WRITE;
3503#endif
3504 break;
3505 case AC97_Record_Gain_Mic_Mute:
3506#ifdef IN_RING3
3507 /* Ditto; see note above. */
3508 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3509#else
3510 rc = VINF_IOM_R3_IOPORT_WRITE;
3511#endif
3512 break;
3513 case AC97_Vendor_ID1:
3514 case AC97_Vendor_ID2:
3515 LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3516 break;
3517 case AC97_Extended_Audio_ID:
3518 LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3519 break;
3520 case AC97_Extended_Audio_Ctrl_Stat:
3521#ifdef IN_RING3
3522 /*
3523 * Handle VRA bits.
3524 */
3525 if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3526 {
3527 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3528 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3529 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3530
3531 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3532 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3533 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3534 }
3535 else
3536 LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3537
3538 /*
3539 * Handle VRM bits.
3540 */
3541 if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3542 {
3543 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3544 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3545 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3546 }
3547 else
3548 LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3549
3550 LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3551 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3552#else /* !IN_RING3 */
3553 rc = VINF_IOM_R3_IOPORT_WRITE;
3554#endif
3555 break;
3556 case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3557#ifdef IN_RING3
3558 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3559 {
3560 LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3561 ichac97MixerSet(pThis, offPort, u32);
3562 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3563 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3564 }
3565 else
3566 LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3567#else
3568 rc = VINF_IOM_R3_IOPORT_WRITE;
3569#endif
3570 break;
3571 case AC97_MIC_ADC_Rate: /* Input slot 6. */
3572#ifdef IN_RING3
3573 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3574 {
3575 LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3576 ichac97MixerSet(pThis, offPort, u32);
3577 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3578 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3579 }
3580 else
3581 LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3582#else
3583 rc = VINF_IOM_R3_IOPORT_WRITE;
3584#endif
3585 break;
3586 case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3587#ifdef IN_RING3
3588 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3589 {
3590 LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3591 ichac97MixerSet(pThis, offPort, u32);
3592 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3593 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3594 }
3595 else
3596 LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3597#else
3598 rc = VINF_IOM_R3_IOPORT_WRITE;
3599#endif
3600 break;
3601 default:
3602 LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3603 ichac97MixerSet(pThis, offPort, u32);
3604 break;
3605 }
3606 break;
3607 }
3608
3609 case 4:
3610 {
3611 LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3612 pThis->cas = 0;
3613 break;
3614 }
3615
3616 default:
3617 AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3618 break;
3619 }
3620
3621 DEVAC97_UNLOCK(pDevIns, pThis);
3622 return rc;
3623}
3624
3625#ifdef IN_RING3
3626
3627/**
3628 * Saves (serializes) an AC'97 stream using SSM.
3629 *
3630 * @param pDevIns Device instance.
3631 * @param pSSM Saved state manager (SSM) handle to use.
3632 * @param pStream AC'97 stream to save.
3633 */
3634static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3635{
3636 PAC97BMREGS pRegs = &pStream->Regs;
3637 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3638
3639 pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3640 pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3641 pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3642 pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3643 pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3644 pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3645 pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3646 pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3647 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3648 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3649}
3650
3651/**
3652 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3653 */
3654static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3655{
3656 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3657 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3658 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3659 LogFlowFuncEnter();
3660
3661 pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3662 pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3663 pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3664
3665 /*
3666 * The order that the streams are saved here is fixed, so don't change.
3667 */
3668 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3669 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3670 ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3671
3672 pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3673
3674 /* The stream order is against fixed and set in stone. */
3675 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3676 afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3677 afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3678 afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3679 AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3680 pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3681
3682 LogFlowFuncLeaveRC(VINF_SUCCESS);
3683 return VINF_SUCCESS;
3684}
3685
3686/**
3687 * Loads an AC'97 stream from SSM.
3688 *
3689 * @returns IPRT status code.
3690 * @param pDevIns The device instance.
3691 * @param pSSM Saved state manager (SSM) handle to use.
3692 * @param pStream AC'97 stream to load.
3693 */
3694static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3695{
3696 PAC97BMREGS pRegs = &pStream->Regs;
3697 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3698
3699 pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3700 pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3701 pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3702 pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3703 pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3704 pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3705 pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3706 pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3707 pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3708 return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3709}
3710
3711/**
3712 * @callback_method_impl{FNSSMDEVLOADEXEC}
3713 */
3714static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3715{
3716 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3717 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3718 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3719
3720 LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3721
3722 AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3723 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3724
3725 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3726 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3727 pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3728
3729 /*
3730 * The order the streams are loaded here is critical (defined by
3731 * AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3732 */
3733 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3734 {
3735 int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3736 AssertRCReturn(rc2, rc2);
3737 }
3738
3739 pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3740
3741 ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3742 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3743 ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3744 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3745 ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3746 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3747 ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3748 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3749 ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3750 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3751 ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3752 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3753 ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3754 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3755 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3756 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3757 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3758
3759 /*
3760 * Again the stream order is set is stone.
3761 */
3762 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3763 int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3764 AssertRCReturn(rc2, rc2);
3765
3766 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3767 {
3768 const bool fEnable = RT_BOOL(afActiveStrms[i]);
3769 const PAC97STREAM pStream = &pThis->aStreams[i];
3770 const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3771
3772 rc2 = ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, fEnable);
3773 AssertRC(rc2);
3774 if ( fEnable
3775 && RT_SUCCESS(rc2))
3776 {
3777 /* Re-arm the timer for this stream. */
3778 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3779 }
3780
3781 /* Keep going. */
3782 }
3783
3784 pThis->bup_flag = 0;
3785 pThis->last_samp = 0;
3786
3787 return VINF_SUCCESS;
3788}
3789
3790
3791/**
3792 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3793 */
3794static DECLCALLBACK(void *) ichac97R3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3795{
3796 PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3797 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3798 return NULL;
3799}
3800
3801
3802/**
3803 * Powers off the device.
3804 *
3805 * @param pDevIns Device instance to power off.
3806 */
3807static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3808{
3809 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3810 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3811
3812 LogRel2(("AC97: Powering off ...\n"));
3813
3814 /* Note: Involves mixer stream / sink destruction, so also do this here
3815 * instead of in ichac97R3Destruct(). */
3816 ichac97R3StreamsDestroy(pThis, pThisCC);
3817
3818 /*
3819 * Note: Destroy the mixer while powering off and *not* in ichac97R3Destruct,
3820 * giving the mixer the chance to release any references held to
3821 * PDM audio streams it maintains.
3822 */
3823 if (pThisCC->pMixer)
3824 {
3825 AudioMixerDestroy(pThisCC->pMixer);
3826 pThisCC->pMixer = NULL;
3827 }
3828}
3829
3830
3831/**
3832 * @interface_method_impl{PDMDEVREG,pfnReset}
3833 *
3834 * @remarks The original sources didn't install a reset handler, but it seems to
3835 * make sense to me so we'll do it.
3836 */
3837static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3838{
3839 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3840 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3841
3842 LogRel(("AC97: Reset\n"));
3843
3844 /*
3845 * Reset the mixer too. The Windows XP driver seems to rely on
3846 * this. At least it wants to read the vendor id before it resets
3847 * the codec manually.
3848 */
3849 ichac97R3MixerReset(pThis, pThisCC);
3850
3851 /*
3852 * Reset all streams.
3853 */
3854 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3855 {
3856 ichac97R3StreamEnable(pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3857 ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3858 }
3859
3860 /*
3861 * Reset mixer sinks.
3862 *
3863 * Do the reset here instead of in ichac97R3StreamReset();
3864 * the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3865 */
3866 AudioMixerSinkReset(pThisCC->pSinkLineIn);
3867 AudioMixerSinkReset(pThisCC->pSinkMicIn);
3868 AudioMixerSinkReset(pThisCC->pSinkOut);
3869}
3870
3871
3872/**
3873 * Attach command, internal version.
3874 *
3875 * This is called to let the device attach to a driver for a specified LUN
3876 * during runtime. This is not called during VM construction, the device
3877 * constructor has to attach to all the available drivers.
3878 *
3879 * @returns VBox status code.
3880 * @param pDevIns The device instance.
3881 * @param pThisCC The ring-3 AC'97 device state.
3882 * @param iLun The logical unit which is being attached.
3883 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3884 * @param ppDrv Attached driver instance on success. Optional.
3885 */
3886static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, uint32_t fFlags, PAC97DRIVER *ppDrv)
3887{
3888 RT_NOREF(fFlags);
3889
3890 /*
3891 * Attach driver.
3892 */
3893 char *pszDesc;
3894 if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", iLun) <= 0)
3895 AssertLogRelFailedReturn(VERR_NO_MEMORY);
3896
3897 PPDMIBASE pDrvBase;
3898 int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3899 if (RT_SUCCESS(rc))
3900 {
3901 PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3902 if (pDrv)
3903 {
3904 pDrv->pDrvBase = pDrvBase;
3905 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3906 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n", iLun, rc));
3907 pDrv->uLUN = iLun;
3908 pDrv->pszDesc = pszDesc;
3909
3910 /*
3911 * For now we always set the driver at LUN 0 as our primary
3912 * host backend. This might change in the future.
3913 */
3914 if (iLun == 0)
3915 pDrv->fFlags |= PDMAUDIODRVFLAGS_PRIMARY;
3916
3917 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", iLun, pDrv->pConnector, pDrv->fFlags));
3918
3919 /* Attach to driver list if not attached yet. */
3920 if (!pDrv->fAttached)
3921 {
3922 RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3923 pDrv->fAttached = true;
3924 }
3925
3926 if (ppDrv)
3927 *ppDrv = pDrv;
3928 }
3929 else
3930 rc = VERR_NO_MEMORY;
3931 }
3932 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3933 LogFunc(("No attached driver for LUN #%u\n", iLun));
3934
3935 if (RT_FAILURE(rc))
3936 {
3937 /* Only free this string on failure;
3938 * must remain valid for the live of the driver instance. */
3939 RTStrFree(pszDesc);
3940 }
3941
3942 LogFunc(("iLun=%u, fFlags=0x%x, rc=%Rrc\n", iLun, fFlags, rc));
3943 return rc;
3944}
3945
3946/**
3947 * Detach command, internal version.
3948 *
3949 * This is called to let the device detach from a driver for a specified LUN
3950 * during runtime.
3951 *
3952 * @returns VBox status code.
3953 * @param pThisCC The ring-3 AC'97 device state.
3954 * @param pDrv Driver to detach from device.
3955 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3956 */
3957static int ichac97R3DetachInternal(PAC97STATER3 pThisCC, PAC97DRIVER pDrv, uint32_t fFlags)
3958{
3959 RT_NOREF(fFlags);
3960
3961 /* First, remove the driver from our list and destory it's associated streams.
3962 * This also will un-set the driver as a recording source (if associated). */
3963 ichac97R3MixerRemoveDrv(pThisCC, pDrv);
3964
3965 /* Next, search backwards for a capable (attached) driver which now will be the
3966 * new recording source. */
3967 PDMAUDIODSTSRCUNION dstSrc;
3968 PAC97DRIVER pDrvCur;
3969 RTListForEachReverse(&pThisCC->lstDrv, pDrvCur, AC97DRIVER, Node)
3970 {
3971 if (!pDrvCur->pConnector)
3972 continue;
3973
3974 PDMAUDIOBACKENDCFG Cfg;
3975 int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
3976 if (RT_FAILURE(rc2))
3977 continue;
3978
3979 dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
3980 PAC97DRIVERSTREAM pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
3981 if ( pDrvStrm
3982 && pDrvStrm->pMixStrm)
3983 {
3984 rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, pDrvStrm->pMixStrm);
3985 if (RT_SUCCESS(rc2))
3986 LogRel2(("AC97: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
3987 }
3988
3989 dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
3990 pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
3991 if ( pDrvStrm
3992 && pDrvStrm->pMixStrm)
3993 {
3994 rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, pDrvStrm->pMixStrm);
3995 if (RT_SUCCESS(rc2))
3996 LogRel2(("AC97: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
3997 }
3998 }
3999
4000 LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4001 return VINF_SUCCESS;
4002}
4003
4004/**
4005 * @interface_method_impl{PDMDEVREGR3,pfnAttach}
4006 */
4007static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4008{
4009 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4010 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4011
4012 LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4013
4014 DEVAC97_LOCK(pDevIns, pThis);
4015
4016 PAC97DRIVER pDrv;
4017 int rc2 = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, fFlags, &pDrv);
4018 if (RT_SUCCESS(rc2))
4019 rc2 = ichac97R3MixerAddDrv(pThisCC, pDrv);
4020
4021 if (RT_FAILURE(rc2))
4022 LogFunc(("Failed with %Rrc\n", rc2));
4023
4024 DEVAC97_UNLOCK(pDevIns, pThis);
4025
4026 return VINF_SUCCESS;
4027}
4028
4029/**
4030 * @interface_method_impl{PDMDEVREG,pfnDetach}
4031 */
4032static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4033{
4034 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4035 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4036
4037 LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4038
4039 DEVAC97_LOCK(pDevIns, pThis);
4040
4041 PAC97DRIVER pDrv, pDrvNext;
4042 RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4043 {
4044 if (pDrv->uLUN == iLUN)
4045 {
4046 int rc2 = ichac97R3DetachInternal(pThisCC, pDrv, fFlags);
4047 if (RT_SUCCESS(rc2))
4048 {
4049 RTStrFree(pDrv->pszDesc);
4050 RTMemFree(pDrv);
4051 pDrv = NULL;
4052 }
4053
4054 break;
4055 }
4056 }
4057
4058 DEVAC97_UNLOCK(pDevIns, pThis);
4059}
4060
4061/**
4062 * Replaces a driver with a the NullAudio drivers.
4063 *
4064 * @returns VBox status code.
4065 * @param pDevIns The device instance.
4066 * @param pThisCC The ring-3 AC'97 device state.
4067 * @param iLun The logical unit which is being replaced.
4068 */
4069static int ichac97R3ReconfigLunWithNullAudio(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun)
4070{
4071 int rc = PDMDevHlpDriverReconfigure2(pDevIns, iLun, "AUDIO", "NullAudio");
4072 if (RT_SUCCESS(rc))
4073 rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags */, NULL /* ppDrv */);
4074 LogFunc(("pThisCC=%p, iLun=%u, rc=%Rrc\n", pThisCC, iLun, rc));
4075 return rc;
4076}
4077
4078/**
4079 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4080 */
4081static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
4082{
4083 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4084 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4085
4086 LogFlowFuncEnter();
4087
4088 PAC97DRIVER pDrv, pDrvNext;
4089 RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4090 {
4091 RTListNodeRemove(&pDrv->Node);
4092 RTMemFree(pDrv->pszDesc);
4093 RTMemFree(pDrv);
4094 }
4095
4096 /* Sanity. */
4097 Assert(RTListIsEmpty(&pThisCC->lstDrv));
4098
4099 return VINF_SUCCESS;
4100}
4101
4102/**
4103 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4104 */
4105static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4106{
4107 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4108 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4109 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4110 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4111 Assert(iInstance == 0); RT_NOREF(iInstance);
4112
4113 /*
4114 * Initialize data so we can run the destructor without scewing up.
4115 */
4116 pThisCC->pDevIns = pDevIns;
4117 pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4118 RTListInit(&pThisCC->lstDrv);
4119
4120 /*
4121 * Validate and read configuration.
4122 */
4123 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Codec|TimerHz|DebugEnabled|DebugPathOut", "");
4124
4125 char szCodec[20];
4126 int rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4127 if (RT_FAILURE(rc))
4128 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4129 N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4130
4131 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4132 if (RT_FAILURE(rc))
4133 return PDMDEV_SET_ERROR(pDevIns, rc,
4134 N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4135
4136 if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4137 LogRel(("AC97: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4138
4139 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4140 if (RT_FAILURE(rc))
4141 return PDMDEV_SET_ERROR(pDevIns, rc,
4142 N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4143
4144 rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4145 if (RT_FAILURE(rc))
4146 return PDMDEV_SET_ERROR(pDevIns, rc,
4147 N_("AC97 configuration error: failed to read debugging output path flag as string"));
4148
4149 if (pThisCC->Dbg.fEnabled)
4150 LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4151
4152 /*
4153 * The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4154 * in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4155 * 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4156 */
4157 if (!strcmp(szCodec, "STAC9700"))
4158 pThis->enmCodecModel = AC97CODEC_STAC9700;
4159 else if (!strcmp(szCodec, "AD1980"))
4160 pThis->enmCodecModel = AC97CODEC_AD1980;
4161 else if (!strcmp(szCodec, "AD1981B"))
4162 pThis->enmCodecModel = AC97CODEC_AD1981B;
4163 else
4164 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4165 N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4166
4167 LogRel(("AC97: Using codec '%s'\n", szCodec));
4168
4169 /*
4170 * Use an own critical section for the device instead of the default
4171 * one provided by PDM. This allows fine-grained locking in combination
4172 * with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4173 */
4174 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4175 AssertRCReturn(rc, rc);
4176
4177 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4178 AssertRCReturn(rc, rc);
4179
4180 /*
4181 * Initialize data (most of it anyway).
4182 */
4183 /* PCI Device */
4184 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4185 PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4186 PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4187 PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4188 PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4189 PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4190 PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4191 PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4192 PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4193 PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4194 PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4195 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4196 PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4197 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4198 PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4199 PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4200
4201 if (pThis->enmCodecModel == AC97CODEC_AD1980)
4202 {
4203 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4204 PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4205 }
4206 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4207 {
4208 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4209 PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4210 }
4211 else
4212 {
4213 PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4214 PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4215 }
4216
4217 /*
4218 * Register the PCI device and associated I/O regions.
4219 */
4220 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4221 if (RT_FAILURE(rc))
4222 return rc;
4223
4224 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /*iPciRegion*/, 256 /*cPorts*/,
4225 ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/,
4226 "ICHAC97 NAM", NULL /*paExtDescs*/, &pThis->hIoPortsNam);
4227 AssertRCReturn(rc, rc);
4228
4229 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /*iPciRegion*/, 64 /*cPorts*/,
4230 ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/,
4231 "ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4232 AssertRCReturn(rc, rc);
4233
4234 /*
4235 * Saved state.
4236 */
4237 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4238 if (RT_FAILURE(rc))
4239 return rc;
4240
4241# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4242 LogRel(("AC97: Asynchronous I/O enabled\n"));
4243# endif
4244
4245 /*
4246 * Attach drivers. We ASSUME they are configured consecutively without any
4247 * gaps, so we stop when we hit the first LUN w/o a driver configured.
4248 */
4249 for (unsigned iLun = 0; ; iLun++)
4250 {
4251 AssertBreak(iLun < UINT8_MAX);
4252 LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4253 rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags */, NULL /* ppDrv */);
4254 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4255 {
4256 LogFunc(("cLUNs=%u\n", iLun));
4257 break;
4258 }
4259 if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4260 {
4261 ichac97R3ReconfigLunWithNullAudio(pDevIns, pThisCC, iLun); /* Pretend attaching to the NULL audio backend will never fail. */
4262 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4263 N_("Host audio backend initialization has failed. "
4264 "Selecting the NULL audio backend with the consequence that no sound is audible"));
4265 }
4266 else
4267 AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4268 }
4269
4270 rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4271 AssertRCReturn(rc, rc);
4272 rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkLineIn);
4273 AssertRCReturn(rc, rc);
4274 rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkMicIn);
4275 AssertRCReturn(rc, rc);
4276 rc = AudioMixerCreateSink(pThisCC->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThisCC->pSinkOut);
4277 AssertRCReturn(rc, rc);
4278
4279 /*
4280 * Create all hardware streams.
4281 */
4282 AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4283 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4284 {
4285 rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4286 AssertRCReturn(rc, rc);
4287 }
4288
4289 /*
4290 * Create the emulation timers (one per stream).
4291 *
4292 * We must the critical section for the timers as the device has a
4293 * noop section associated with it.
4294 *
4295 * Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4296 * relies on exact (virtual) DMA timing and uses DMA Position Buffers
4297 * instead of the LPIB registers.
4298 */
4299 static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4300 AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4301 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4302 {
4303 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4304 TMTIMER_FLAGS_NO_CRIT_SECT, s_apszNames[i], &pThis->aStreams[i].hTimer);
4305 AssertRCReturn(rc, rc);
4306
4307 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4308 AssertRCReturn(rc, rc);
4309 }
4310
4311
4312# ifdef VBOX_WITH_AUDIO_AC97_ONETIME_INIT
4313 PAC97DRIVER pDrv;
4314 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
4315 {
4316 /*
4317 * Only primary drivers are critical for the VM to run. Everything else
4318 * might not worth showing an own error message box in the GUI.
4319 */
4320 if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
4321 continue;
4322
4323 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
4324 AssertPtr(pCon);
4325
4326 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
4327 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
4328 bool fValidOut = AudioMixerStreamIsValid(pDrv->Out.pMixStrm);
4329
4330 if ( !fValidLineIn
4331 && !fValidMicIn
4332 && !fValidOut)
4333 {
4334 LogRel(("AC97: Falling back to NULL backend (no sound audible)\n"));
4335 ichac97R3Reset(pDevIns);
4336 ichac97R3ReconfigLunWithNullAudio(pdEvIns, pThsiCC, iLun);
4337 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4338 N_("No audio devices could be opened. "
4339 "Selecting the NULL audio backend with the consequence that no sound is audible"));
4340 }
4341 else
4342 {
4343 bool fWarn = false;
4344
4345 PDMAUDIOBACKENDCFG backendCfg;
4346 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
4347 if (RT_SUCCESS(rc2))
4348 {
4349 if (backendCfg.cMaxStreamsIn)
4350 {
4351 /* If the audio backend supports two or more input streams at once,
4352 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
4353 if (backendCfg.cMaxStreamsIn >= 2)
4354 fWarn = !fValidLineIn || !fValidMicIn;
4355 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
4356 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
4357 * One of the two simply is not in use then. */
4358 else if (backendCfg.cMaxStreamsIn == 1)
4359 fWarn = !fValidLineIn && !fValidMicIn;
4360 /* Don't warn if our backend is not able of supporting any input streams at all. */
4361 }
4362
4363 if ( !fWarn
4364 && backendCfg.cMaxStreamsOut)
4365 {
4366 fWarn = !fValidOut;
4367 }
4368 }
4369 else
4370 {
4371 LogRel(("AC97: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
4372 fWarn = true;
4373 }
4374
4375 if (fWarn)
4376 {
4377 char szMissingStreams[255] = "";
4378 size_t len = 0;
4379 if (!fValidLineIn)
4380 {
4381 LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
4382 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
4383 }
4384 if (!fValidMicIn)
4385 {
4386 LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
4387 len += RTStrPrintf(szMissingStreams + len,
4388 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
4389 }
4390 if (!fValidOut)
4391 {
4392 LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
4393 len += RTStrPrintf(szMissingStreams + len,
4394 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
4395 }
4396
4397 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4398 N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
4399 "output or depending on audio input may hang. Make sure your host audio device "
4400 "is working properly. Check the logfile for error messages of the audio "
4401 "subsystem"), szMissingStreams);
4402 }
4403 }
4404 }
4405# endif /* VBOX_WITH_AUDIO_AC97_ONETIME_INIT */
4406
4407 ichac97R3Reset(pDevIns);
4408
4409 /*
4410 * Register statistics.
4411 */
4412 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4413 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4414# ifdef VBOX_WITH_STATISTICS
4415 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4416 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4417 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4418 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4419 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4420# endif
4421
4422 LogFlowFuncLeaveRC(VINF_SUCCESS);
4423 return VINF_SUCCESS;
4424}
4425
4426#else /* !IN_RING3 */
4427
4428/**
4429 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4430 */
4431static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4432{
4433 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4434 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4435
4436 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4437 AssertRCReturn(rc, rc);
4438
4439 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/);
4440 AssertRCReturn(rc, rc);
4441 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/);
4442 AssertRCReturn(rc, rc);
4443
4444 return VINF_SUCCESS;
4445}
4446
4447#endif /* !IN_RING3 */
4448
4449/**
4450 * The device registration structure.
4451 */
4452const PDMDEVREG g_DeviceICHAC97 =
4453{
4454 /* .u32Version = */ PDM_DEVREG_VERSION,
4455 /* .uReserved0 = */ 0,
4456 /* .szName = */ "ichac97",
4457 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4458 /* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4459 /* .cMaxInstances = */ 1,
4460 /* .uSharedVersion = */ 42,
4461 /* .cbInstanceShared = */ sizeof(AC97STATE),
4462 /* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4463 /* .cbInstanceRC = */ 0,
4464 /* .cMaxPciDevices = */ 1,
4465 /* .cMaxMsixVectors = */ 0,
4466 /* .pszDescription = */ "ICH AC'97 Audio Controller",
4467#if defined(IN_RING3)
4468 /* .pszRCMod = */ "VBoxDDRC.rc",
4469 /* .pszR0Mod = */ "VBoxDDR0.r0",
4470 /* .pfnConstruct = */ ichac97R3Construct,
4471 /* .pfnDestruct = */ ichac97R3Destruct,
4472 /* .pfnRelocate = */ NULL,
4473 /* .pfnMemSetup = */ NULL,
4474 /* .pfnPowerOn = */ NULL,
4475 /* .pfnReset = */ ichac97R3Reset,
4476 /* .pfnSuspend = */ NULL,
4477 /* .pfnResume = */ NULL,
4478 /* .pfnAttach = */ ichac97R3Attach,
4479 /* .pfnDetach = */ ichac97R3Detach,
4480 /* .pfnQueryInterface = */ NULL,
4481 /* .pfnInitComplete = */ NULL,
4482 /* .pfnPowerOff = */ ichac97R3PowerOff,
4483 /* .pfnSoftReset = */ NULL,
4484 /* .pfnReserved0 = */ NULL,
4485 /* .pfnReserved1 = */ NULL,
4486 /* .pfnReserved2 = */ NULL,
4487 /* .pfnReserved3 = */ NULL,
4488 /* .pfnReserved4 = */ NULL,
4489 /* .pfnReserved5 = */ NULL,
4490 /* .pfnReserved6 = */ NULL,
4491 /* .pfnReserved7 = */ NULL,
4492#elif defined(IN_RING0)
4493 /* .pfnEarlyConstruct = */ NULL,
4494 /* .pfnConstruct = */ ichac97RZConstruct,
4495 /* .pfnDestruct = */ NULL,
4496 /* .pfnFinalDestruct = */ NULL,
4497 /* .pfnRequest = */ NULL,
4498 /* .pfnReserved0 = */ NULL,
4499 /* .pfnReserved1 = */ NULL,
4500 /* .pfnReserved2 = */ NULL,
4501 /* .pfnReserved3 = */ NULL,
4502 /* .pfnReserved4 = */ NULL,
4503 /* .pfnReserved5 = */ NULL,
4504 /* .pfnReserved6 = */ NULL,
4505 /* .pfnReserved7 = */ NULL,
4506#elif defined(IN_RC)
4507 /* .pfnConstruct = */ ichac97RZConstruct,
4508 /* .pfnReserved0 = */ NULL,
4509 /* .pfnReserved1 = */ NULL,
4510 /* .pfnReserved2 = */ NULL,
4511 /* .pfnReserved3 = */ NULL,
4512 /* .pfnReserved4 = */ NULL,
4513 /* .pfnReserved5 = */ NULL,
4514 /* .pfnReserved6 = */ NULL,
4515 /* .pfnReserved7 = */ NULL,
4516#else
4517# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4518#endif
4519 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4520};
4521
4522#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4523
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