DevHdaStream.h@ 89869

最後變更在這個檔案從89869是 89869,由 vboxsync 提交於 4 年前
DevHda: Implemented DMA-on-WALCLK access too. Cleanups. bugref:9890
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1	/* $Id: DevHdaStream.h 89869 2021-06-23 19:06:11Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Streams.
4	*/
5
6	/*
7	* Copyright (C) 2017-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
25	# error "Only include DevHda.h!"
26	#endif
27
28
29	/**
30	* Structure containing HDA stream debug stuff, configurable at runtime.
31	*/
32	typedef struct HDASTREAMDEBUGRT
33	{
34	/** Whether debugging is enabled or not. */
35	bool fEnabled;
36	uint8_t Padding[7];
37	/** File for dumping stream reads / writes.
38	* For input streams, this dumps data being written to the device FIFO,
39	* whereas for output streams this dumps data being read from the device FIFO. */
40	R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
41	/** File for dumping raw DMA reads / writes.
42	* For input streams, this dumps data being written to the device DMA,
43	* whereas for output streams this dumps data being read from the device DMA. */
44	R3PTRTYPE(PAUDIOHLPFILE) pFileDMARaw;
45	/** File for dumping mapped (that is, extracted) DMA reads / writes. */
46	R3PTRTYPE(PAUDIOHLPFILE) pFileDMAMapped;
47	} HDASTREAMDEBUGRT;
48
49	/**
50	* Structure containing HDA stream debug information.
51	*/
52	typedef struct HDASTREAMDEBUG
53	{
54	/** Runtime debug info. */
55	HDASTREAMDEBUGRT Runtime;
56	#ifdef DEBUG
57	/** Critical section to serialize access if needed. */
58	RTCRITSECT CritSect;
59	uint32_t Padding0[2];
60	/** Number of total read accesses. */
61	uint64_t cReadsTotal;
62	/** Number of total DMA bytes read. */
63	uint64_t cbReadTotal;
64	/** Timestamp (in ns) of last read access. */
65	uint64_t tsLastReadNs;
66	/** Number of total write accesses. */
67	uint64_t cWritesTotal;
68	/** Number of total DMA bytes written. */
69	uint64_t cbWrittenTotal;
70	/** Number of total write accesses since last iteration (Hz). */
71	uint64_t cWritesHz;
72	/** Number of total DMA bytes written since last iteration (Hz). */
73	uint64_t cbWrittenHz;
74	/** Timestamp (in ns) of beginning a new write slot. */
75	uint64_t tsWriteSlotBegin;
76	/** Number of current silence samples in a (consecutive) row. */
77	uint64_t csSilence;
78	/** Number of silent samples in a row to consider an audio block as audio gap (silence). */
79	uint64_t cSilenceThreshold;
80	/** How many bytes to skip in an audio stream before detecting silence.
81	* (useful for intros and silence at the beginning of a song). */
82	uint64_t cbSilenceReadMin;
83	#else
84	uint64_t au64Alignment[2];
85	#endif
86	} HDASTREAMDEBUG;
87
88	/**
89	* Internal state of a HDA stream.
90	*/
91	typedef struct HDASTREAMSTATE
92	{
93	/** Flag indicating whether this stream currently is
94	* in reset mode and therefore not acccessible by the guest. */
95	volatile bool fInReset;
96	/** Flag indicating if the stream is in running state or not. */
97	volatile bool fRunning;
98	/** The stream's I/O timer Hz rate. */
99	uint16_t uTimerIoHz;
100	/** How many interrupts are pending due to
101	* BDLE interrupt-on-completion (IOC) bits set. */
102	uint8_t cTransferPendingInterrupts;
103	/** Unused, padding. */
104	uint8_t abPadding1[2];
105	/** Input streams only: Set when we switch from feeding the guest silence and
106	* commits to proving actual audio input bytes. */
107	bool fInputPreBuffered;
108	/** Input streams only: The number of bytes we need to prebuffer. */
109	uint32_t cbInputPreBuffer;
110	uint32_t u32Padding2;
111	/** Timestamp (absolute, in timer ticks) of the last DMA data transfer.
112	* @note This is used for wall clock (WALCLK) calculations. */
113	uint64_t volatile tsTransferLast;
114	/** The stream's current configuration (matches SDnFMT). */
115	PDMAUDIOSTREAMCFG Cfg;
116	/** Timestamp (real time, in ns) of last DMA transfer. */
117	uint64_t tsLastTransferNs;
118	/** Timestamp (real time, in ns) of last stream read (to backends).
119	* When running in async I/O mode, this differs from \a tsLastTransferNs,
120	* because reading / processing will be done in a separate stream. */
121	uint64_t tsLastReadNs;
122
123	/** This is set to the timer clock time when the msInitialDelay period is over.
124	* Once reached, this is set to zero to avoid unnecessary time queries. */
125	uint64_t tsAioDelayEnd;
126	/** The start time for the playback (on the timer clock). */
127	uint64_t tsStart;
128
129	/** @name DMA engine
130	* @{ */
131	/** Timestamp (absolute, in timer ticks) of the next DMA data transfer.
132	* Next for determining the next scheduling window.
133	* Can be 0 if no next transfer is scheduled. */
134	uint64_t tsTransferNext;
135	/** The size of the current DMA transfer period. */
136	uint32_t cbCurDmaPeriod;
137	/** The size of an average transfer. */
138	uint32_t cbAvgTransfer;
139
140	/** Current circular buffer read offset (for tracing & logging). */
141	uint64_t offRead;
142	/** Current circular buffer write offset (for tracing & logging). */
143	uint64_t offWrite;
144
145	/** The offset into the current BDLE. */
146	uint32_t offCurBdle;
147	/** LVI + 1 */
148	uint16_t cBdles;
149	/** The index of the current BDLE.
150	* This is the entry which period is currently "running" on the DMA timer. */
151	uint8_t idxCurBdle;
152	/** The number of prologue scheduling steps.
153	* This is used when the tail BDLEs doesn't have IOC set. */
154	uint8_t cSchedulePrologue;
155	/** Number of scheduling steps. */
156	uint16_t cSchedule;
157	/** Current scheduling step. */
158	uint16_t idxSchedule;
159	/** Current loop number within the current scheduling step. */
160	uint32_t idxScheduleLoop;
161
162	/** Buffer descriptors and additional timer scheduling state.
163	* (Same as HDABDLEDESC, with more sensible naming.) */
164	struct
165	{
166	/** The buffer address. */
167	uint64_t GCPhys;
168	/** The buffer size (guest bytes). */
169	uint32_t cb;
170	/** The flags (only bit 0 is defined). */
171	uint32_t fFlags;
172	} aBdl[256];
173	/** Scheduling steps. */
174	struct
175	{
176	/** Number of timer ticks per period.
177	* ASSUMES that we don't need a full second and that the timer resolution
178	* isn't much higher than nanoseconds. */
179	uint32_t cPeriodTicks;
180	/** The period length in host bytes. */
181	uint32_t cbPeriod;
182	/** Number of times to repeat the period. */
183	uint32_t cLoops;
184	/** The BDL index of the first entry. */
185	uint8_t idxFirst;
186	/** The number of BDL entries. */
187	uint8_t cEntries;
188	uint8_t abPadding[2];
189	} aSchedule[512+8];
190
191	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
192	/** Number of valid bytes in abDma.
193	* @note Volatile to prevent the compiler from re-reading it after we've
194	* validated the value in ring-0. */
195	uint32_t volatile cbDma;
196	/** Total number of bytes going via abDma this timer period. */
197	uint32_t cbDmaTotal;
198	/** DMA bounce buffer for ring-0 register reads (LPIB). */
199	uint8_t abDma[2048 - 8];
200	#endif
201	/** @} */
202	} HDASTREAMSTATE;
203	AssertCompileSizeAlignment(HDASTREAMSTATE, 16);
204	AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 8);
205	AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 16);
206	AssertCompileMemberAlignment(HDASTREAMSTATE, aSchedule, 16);
207
208	/**
209	* An HDA stream (SDI / SDO) - shared.
210	*
211	* @note This HDA stream has nothing to do with a regular audio stream handled
212	* by the audio connector or the audio mixer. This HDA stream is a serial
213	* data in/out stream (SDI/SDO) defined in hardware and can contain
214	* multiple audio streams in one single SDI/SDO (interleaving streams).
215	*
216	* Contains only register values which do not change until a stream reset
217	* occurs.
218	*/
219	typedef struct HDASTREAM
220	{
221	/** Internal state of this stream. */
222	HDASTREAMSTATE State;
223
224	/** Stream descriptor number (SDn). */
225	uint8_t u8SD;
226	/** Current channel index.
227	* For a stereo stream, this is u8Channel + 1. */
228	uint8_t u8Channel;
229	/** FIFO Watermark (checked + translated in bytes, FIFOW).
230	* This will be update from hdaRegWriteSDFIFOW() and also copied
231	* hdaR3StreamInit() for some reason. */
232	uint8_t u8FIFOW;
233
234	/** @name Register values at stream setup.
235	* These will all be copied in hdaR3StreamInit().
236	* @{ */
237	/** FIFO Size (checked + translated in bytes, FIFOS).
238	* This is supposedly the max number of bytes we'll be DMA'ing in one chunk
239	* and correspondingly the LPIB & wall clock update jumps. However, we're
240	* not at all being honest with the guest about this. */
241	uint8_t u8FIFOS;
242	/** Cyclic Buffer Length (SDnCBL) - Represents the size of the ring buffer. */
243	uint32_t u32CBL;
244	/** Last Valid Index (SDnLVI). */
245	uint16_t u16LVI;
246	/** Format (SDnFMT). */
247	uint16_t u16FMT;
248	uint8_t abPadding[4];
249	/** DMA base address (SDnBDPU - SDnBDPL). */
250	uint64_t u64BDLBase;
251	/** @} */
252
253	/** The timer for pumping data thru the attached LUN drivers. */
254	TMTIMERHANDLE hTimer;
255
256	#if 0
257	/** Pad the structure size to a 64 byte alignment. */
258	uint64_t au64Padding1[2];
259	#endif
260	} HDASTREAM;
261	AssertCompileMemberAlignment(HDASTREAM, State.aBdl, 16);
262	AssertCompileMemberAlignment(HDASTREAM, State.aSchedule, 16);
263	AssertCompileSizeAlignment(HDASTREAM, 64);
264	/** Pointer to an HDA stream (SDI / SDO). */
265	typedef HDASTREAM *PHDASTREAM;
266
267
268	/**
269	* An HDA stream (SDI / SDO) - ring-3 bits.
270	*/
271	typedef struct HDASTREAMR3
272	{
273	/** Stream descriptor number (SDn). */
274	uint8_t u8SD;
275	uint8_t abPadding[7];
276	/** The shared state for the parent HDA device. */
277	R3PTRTYPE(PHDASTATE) pHDAStateShared;
278	/** The ring-3 state for the parent HDA device. */
279	R3PTRTYPE(PHDASTATER3) pHDAStateR3;
280	/** Pointer to HDA sink this stream is attached to. */
281	R3PTRTYPE(PHDAMIXERSINK) pMixSink;
282	/** Internal state of this stream. */
283	struct
284	{
285	/** Circular buffer (FIFO) for holding DMA'ed data. */
286	R3PTRTYPE(PRTCIRCBUF) pCircBuf;
287	#ifdef HDA_USE_DMA_ACCESS_HANDLER
288	/** List of DMA handlers. */
289	RTLISTANCHORR3 lstDMAHandlers;
290	#endif
291	/** The mixer sink this stream has registered AIO update callback with.
292	* This is NULL till we register it, typically in hdaR3StreamEnable.
293	* (The problem with following the pMixSink assignment is that hdaR3StreamReset
294	* sets it without updating the HDA sink structure, so things get out of
295	* wack in hdaR3MixerControl later in the initial device reset.) */
296	PAUDMIXSINK pAioRegSink;
297
298	/** Size of the DMA buffer (pCircBuf) in bytes. */
299	uint32_t StatDmaBufSize;
300	/** Number of used bytes in the DMA buffer (pCircBuf). */
301	uint32_t StatDmaBufUsed;
302	/** Counter for all under/overflows problems. */
303	STAMCOUNTER StatDmaFlowProblems;
304	/** Counter for unresovled under/overflows problems. */
305	STAMCOUNTER StatDmaFlowErrors;
306	/** Number of bytes involved in unresolved flow errors. */
307	STAMCOUNTER StatDmaFlowErrorBytes;
308	/** DMA skipped because buffer interrupt pending. */
309	STAMCOUNTER StatDmaSkippedPendingBcis;
310
311	STAMPROFILE StatStart;
312	STAMPROFILE StatReset;
313	STAMPROFILE StatStop;
314	} State;
315	/** Debug bits. */
316	HDASTREAMDEBUG Dbg;
317	uint64_t au64Alignment[3];
318	} HDASTREAMR3;
319	AssertCompileSizeAlignment(HDASTREAMR3, 64);
320	/** Pointer to an HDA stream (SDI / SDO). */
321	typedef HDASTREAMR3 *PHDASTREAMR3;
322
323	/** @name Stream functions (all contexts).
324	* @{
325	*/
326	VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
327	uint64_t tsNow, uint32_t cbToTransfer);
328	VBOXSTRICTRC hdaStreamMaybeDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis,
329	PHDASTREAM pStreamShared, uint64_t tsNow);
330	/** @} */
331
332	#ifdef IN_RING3
333
334	/** @name Stream functions (ring-3).
335	* @{
336	*/
337	int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis,
338	PHDASTATER3 pThisCC, uint8_t uSD);
339	void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3);
340	int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
341	PHDASTREAMR3 pStreamR3, uint8_t uSD);
342	void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC,
343	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD);
344	int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable);
345	void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow);
346	void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared);
347
348	uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
349	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
350	DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser);
351	# ifdef HDA_USE_DMA_ACCESS_HANDLER
352	bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream);
353	void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream);
354	# endif
355	/** @} */
356
357	#endif /* IN_RING3 */
358	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaStream_h */
359

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source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.h@ 89869

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