VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHDACommon.h@ 82406

最後變更 在這個檔案從82406是 82406,由 vboxsync 提交於 5 年 前

DevHDA: Cleanups. bugref:9218
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
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1/* $Id: DevHDACommon.h 82406 2019-12-05 00:47:02Z vboxsync $ */
2/** @file
3 * DevHDACommon.h - Shared HDA device defines / functions.
4 */
5
6/*
7 * Copyright (C) 2016-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_DevHDACommon_h
19#define VBOX_INCLUDED_SRC_Audio_DevHDACommon_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include "AudioMixer.h"
25#include <VBox/log.h> /* LOG_ENABLED */
26
27 /** Read callback. */
28typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
29 /** Write callback. */
30typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
31
32/**
33 * HDA register descriptor.
34 *
35 * See 302349 p 6.2.
36 */
37typedef struct HDAREGDESC
38{
39 /** Register offset in the register space. */
40 uint32_t offset;
41 /** Size in bytes. Registers of size > 4 are in fact tables. */
42 uint32_t size;
43 /** Readable bits. */
44 uint32_t readable;
45 /** Writable bits. */
46 uint32_t writable;
47 /** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
48 * specify the handling (read/write) policy of the register. */
49 uint32_t fFlags;
50 /** Read callback. */
51 FNHDAREGREAD *pfnRead;
52 /** Write callback. */
53 FNHDAREGWRITE *pfnWrite;
54 /** Index into the register storage array. */
55 uint32_t mem_idx;
56 /** Abbreviated name. */
57 const char *abbrev;
58 /** Descripton. */
59 const char *desc;
60} HDAREGDESC;
61/** Pointer to a a const HDA register descriptor. */
62typedef HDAREGDESC const *PCHDAREGDESC;
63
64/**
65 * HDA register aliases (HDA spec 3.3.45).
66 * @remarks Sorted by offReg.
67 */
68typedef struct HDAREGALIAS
69{
70 /** The alias register offset. */
71 uint32_t offReg;
72 /** The register index. */
73 int idxAlias;
74} HDAREGALIAS;
75
76/**
77 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
78 * Bidirectional streams are currently *not* supported.
79 *
80 * Note: When changing any of those values, be prepared for some saved state
81 * fixups / trouble!
82 */
83#define HDA_MAX_SDI 4
84#define HDA_MAX_SDO 4
85#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
86AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
87
88/** Number of general registers. */
89#define HDA_NUM_GENERAL_REGS 34
90/** Number of total registers in the HDA's register map. */
91#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
92/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
93#define HDA_MAX_TAGS 16
94
95/**
96 * ICH6 datasheet defines limits for FIFOS registers (18.2.39).
97 * Formula: size - 1
98 * Other values not listed are not supported.
99 */
100/** Maximum FIFO size (in bytes). */
101#define HDA_FIFO_MAX 256
102
103/** Default timer frequency (in Hz).
104 *
105 * Lowering this value can ask for trouble, as backends then can run
106 * into data underruns.
107 *
108 * Note: For handling surround setups (e.g. 5.1 speaker setups) we need
109 * a higher Hz rate, as the device emulation otherwise will come into
110 * timing trouble, making the output (DMA reads) crackling. */
111#define HDA_TIMER_HZ_DEFAULT 100
112
113/** Default position adjustment (in audio samples).
114 *
115 * For snd_hda_intel (Linux guests), the first BDL entry always is being used as
116 * so-called BDL adjustment, which can vary, and is being used for chipsets which
117 * misbehave and/or are incorrectly implemented.
118 *
119 * The BDL adjustment entry *always* has the IOC (Interrupt on Completion) bit set.
120 *
121 * For Intel Baytrail / Braswell implementations the BDL default adjustment is 32 frames, whereas
122 * for ICH / PCH it's only one (1) frame.
123 *
124 * See default_bdl_pos_adj() and snd_hdac_stream_setup_periods() for more information.
125 *
126 * By default we apply some simple heuristics in hdaStreamInit().
127 */
128#define HDA_POS_ADJUST_DEFAULT 0
129
130/** HDA's (fixed) audio frame size in bytes.
131 * We only support 16-bit stereo frames at the moment. */
132#define HDA_FRAME_SIZE_DEFAULT 4
133
134/** Offset of the SD0 register map. */
135#define HDA_REG_DESC_SD0_BASE 0x80
136
137/** Turn a short global register name into an memory index and a stringized name. */
138#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
139
140/** Turns a short stream register name into an memory index and a stringized name. */
141#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
142
143/** Same as above for a register *not* stored in memory. */
144#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
145
146extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
147
148/**
149 * NB: Register values stored in memory (au32Regs[]) are indexed through
150 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
151 * register descriptors in g_aHdaRegMap[] are indexed through the
152 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
153 *
154 * The au32Regs[] layout is kept unchanged for saved state
155 * compatibility.
156 */
157
158/* Registers */
159#define HDA_REG_IND_NAME(x) HDA_REG_##x
160#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
161#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
162#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
163
164
165#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
166#define HDA_RMX_GCAP 0
167/**
168 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
169 *
170 * oss (15:12) - Number of output streams supported.
171 * iss (11:8) - Number of input streams supported.
172 * bss (7:3) - Number of bidirectional streams supported.
173 * bds (2:1) - Number of serial data out (SDO) signals supported.
174 * b64sup (0) - 64 bit addressing supported.
175 */
176#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
177 ( (((oss) & 0xF) << 12) \
178 | (((iss) & 0xF) << 8) \
179 | (((bss) & 0x1F) << 3) \
180 | (((bds) & 0x3) << 2) \
181 | ((b64sup) & 1))
182
183#define HDA_REG_VMIN 1 /* 0x02 */
184#define HDA_RMX_VMIN 1
185
186#define HDA_REG_VMAJ 2 /* 0x03 */
187#define HDA_RMX_VMAJ 2
188
189#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
190#define HDA_RMX_OUTPAY 3
191
192#define HDA_REG_INPAY 4 /* 0x06-0x07 */
193#define HDA_RMX_INPAY 4
194
195#define HDA_REG_GCTL 5 /* 0x08-0x0B */
196#define HDA_RMX_GCTL 5
197#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
198#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
199#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
200
201#define HDA_REG_WAKEEN 6 /* 0x0C */
202#define HDA_RMX_WAKEEN 6
203
204#define HDA_REG_STATESTS 7 /* 0x0E */
205#define HDA_RMX_STATESTS 7
206#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
207
208#define HDA_REG_GSTS 8 /* 0x10-0x11*/
209#define HDA_RMX_GSTS 8
210#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
211
212#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
213#define HDA_RMX_OUTSTRMPAY 112
214
215#define HDA_REG_INSTRMPAY 10 /* 0x1a */
216#define HDA_RMX_INSTRMPAY 113
217
218#define HDA_REG_INTCTL 11 /* 0x20 */
219#define HDA_RMX_INTCTL 9
220#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
221#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
222/** Bits 0-29 correspond to streams 0-29. */
223#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
224
225#define HDA_REG_INTSTS 12 /* 0x24 */
226#define HDA_RMX_INTSTS 10
227#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
228#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
229
230#define HDA_REG_WALCLK 13 /* 0x30 */
231/**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
232
233/**
234 * Note: The HDA specification defines a SSYNC register at offset 0x38. The
235 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
236 * the datasheet.
237 */
238#define HDA_REG_SSYNC 14 /* 0x34 */
239#define HDA_RMX_SSYNC 12
240
241#define HDA_REG_CORBLBASE 15 /* 0x40 */
242#define HDA_RMX_CORBLBASE 13
243
244#define HDA_REG_CORBUBASE 16 /* 0x44 */
245#define HDA_RMX_CORBUBASE 14
246
247#define HDA_REG_CORBWP 17 /* 0x48 */
248#define HDA_RMX_CORBWP 15
249
250#define HDA_REG_CORBRP 18 /* 0x4A */
251#define HDA_RMX_CORBRP 16
252#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
253
254#define HDA_REG_CORBCTL 19 /* 0x4C */
255#define HDA_RMX_CORBCTL 17
256#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
257#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
258
259#define HDA_REG_CORBSTS 20 /* 0x4D */
260#define HDA_RMX_CORBSTS 18
261
262#define HDA_REG_CORBSIZE 21 /* 0x4E */
263#define HDA_RMX_CORBSIZE 19
264#define HDA_CORBSIZE_SZ_CAP 0xF0
265#define HDA_CORBSIZE_SZ 0x3
266
267/** Number of CORB buffer entries. */
268#define HDA_CORB_SIZE 256
269/** CORB element size (in bytes). */
270#define HDA_CORB_ELEMENT_SIZE 4
271/** Number of RIRB buffer entries. */
272#define HDA_RIRB_SIZE 256
273/** RIRB element size (in bytes). */
274#define HDA_RIRB_ELEMENT_SIZE 8
275
276#define HDA_REG_RIRBLBASE 22 /* 0x50 */
277#define HDA_RMX_RIRBLBASE 20
278
279#define HDA_REG_RIRBUBASE 23 /* 0x54 */
280#define HDA_RMX_RIRBUBASE 21
281
282#define HDA_REG_RIRBWP 24 /* 0x58 */
283#define HDA_RMX_RIRBWP 22
284#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
285
286#define HDA_REG_RINTCNT 25 /* 0x5A */
287#define HDA_RMX_RINTCNT 23
288
289/** Maximum number of Response Interrupts. */
290#define HDA_MAX_RINTCNT 256
291
292#define HDA_REG_RIRBCTL 26 /* 0x5C */
293#define HDA_RMX_RIRBCTL 24
294#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
295#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
296#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
297
298#define HDA_REG_RIRBSTS 27 /* 0x5D */
299#define HDA_RMX_RIRBSTS 25
300#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
301#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
302
303#define HDA_REG_RIRBSIZE 28 /* 0x5E */
304#define HDA_RMX_RIRBSIZE 26
305
306#define HDA_REG_IC 29 /* 0x60 */
307#define HDA_RMX_IC 27
308
309#define HDA_REG_IR 30 /* 0x64 */
310#define HDA_RMX_IR 28
311
312#define HDA_REG_IRS 31 /* 0x68 */
313#define HDA_RMX_IRS 29
314#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
315#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
316
317#define HDA_REG_DPLBASE 32 /* 0x70 */
318#define HDA_RMX_DPLBASE 30
319
320#define HDA_REG_DPUBASE 33 /* 0x74 */
321#define HDA_RMX_DPUBASE 31
322
323#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
324
325#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
326#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
327/** Note: sdnum here _MUST_ be stream reg number [0,7]. */
328#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
329
330#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
331
332/** @todo Condense marcos! */
333
334#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
335#define HDA_RMX_SD0CTL 32
336#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
337#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
338#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
339#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
340#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
341#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
342#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
343
344#define HDA_SDCTL_NUM_MASK 0xF
345#define HDA_SDCTL_NUM_SHIFT 20
346#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
347#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
348#define HDA_SDCTL_STRIPE_MASK 0x3
349#define HDA_SDCTL_STRIPE_SHIFT 16
350#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
351#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
352#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
353#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
354#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
355
356#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
357#define HDA_RMX_SD0STS 33
358#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
359#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
360#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
361#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
362#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
363#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
364#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
365
366#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
367#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
368#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
369#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
370
371#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
372#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
373#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
374#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
375#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
376#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
377#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
378#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
379#define HDA_RMX_SD0LPIB 34
380#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
381#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
382#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
383#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
384#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
385#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
386#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
387
388#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
389#define HDA_RMX_SD0CBL 35
390#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
391#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
392#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
393#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
394#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
395#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
396#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
397
398#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
399#define HDA_RMX_SD0LVI 36
400#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
401#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
402#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
403#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
404#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
405#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
406#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
407
408#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
409#define HDA_RMX_SD0FIFOW 37
410#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
411#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
412#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
413#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
414#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
415#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
416#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
417
418/*
419 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
420 */
421#define HDA_SDFIFOW_8B 0x2
422#define HDA_SDFIFOW_16B 0x3
423#define HDA_SDFIFOW_32B 0x4
424
425#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
426#define HDA_RMX_SD0FIFOS 38
427#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
428#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
429#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
430#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
431#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
432#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
433#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
434
435#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
436#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
437
438#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
439#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
440#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
441#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
442#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
443#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
444
445#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
446#define HDA_RMX_SD0FMT 39
447#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
448#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
449#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
450#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
451#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
452#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
453#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
454
455#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
456#define HDA_RMX_SD0BDPL 40
457#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
458#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
459#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
460#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
461#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
462#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
463#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
464
465#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
466#define HDA_RMX_SD0BDPU 41
467#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
468#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
469#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
470#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
471#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
472#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
473#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
474
475#define HDA_CODEC_CAD_SHIFT 28
476/** Encodes the (required) LUN into a codec command. */
477#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
478
479#define HDA_SDFMT_NON_PCM_SHIFT 15
480#define HDA_SDFMT_NON_PCM_MASK 0x1
481#define HDA_SDFMT_BASE_RATE_SHIFT 14
482#define HDA_SDFMT_BASE_RATE_MASK 0x1
483#define HDA_SDFMT_MULT_SHIFT 11
484#define HDA_SDFMT_MULT_MASK 0x7
485#define HDA_SDFMT_DIV_SHIFT 8
486#define HDA_SDFMT_DIV_MASK 0x7
487#define HDA_SDFMT_BITS_SHIFT 4
488#define HDA_SDFMT_BITS_MASK 0x7
489#define HDA_SDFMT_CHANNELS_MASK 0xF
490
491#define HDA_SDFMT_TYPE RT_BIT(15)
492#define HDA_SDFMT_TYPE_PCM (0)
493#define HDA_SDFMT_TYPE_NON_PCM (1)
494
495#define HDA_SDFMT_BASE RT_BIT(14)
496#define HDA_SDFMT_BASE_48KHZ (0)
497#define HDA_SDFMT_BASE_44KHZ (1)
498
499#define HDA_SDFMT_MULT_1X (0)
500#define HDA_SDFMT_MULT_2X (1)
501#define HDA_SDFMT_MULT_3X (2)
502#define HDA_SDFMT_MULT_4X (3)
503
504#define HDA_SDFMT_DIV_1X (0)
505#define HDA_SDFMT_DIV_2X (1)
506#define HDA_SDFMT_DIV_3X (2)
507#define HDA_SDFMT_DIV_4X (3)
508#define HDA_SDFMT_DIV_5X (4)
509#define HDA_SDFMT_DIV_6X (5)
510#define HDA_SDFMT_DIV_7X (6)
511#define HDA_SDFMT_DIV_8X (7)
512
513#define HDA_SDFMT_8_BIT (0)
514#define HDA_SDFMT_16_BIT (1)
515#define HDA_SDFMT_20_BIT (2)
516#define HDA_SDFMT_24_BIT (3)
517#define HDA_SDFMT_32_BIT (4)
518
519#define HDA_SDFMT_CHAN_MONO (0)
520#define HDA_SDFMT_CHAN_STEREO (1)
521
522/** Emits a SDnFMT register format.
523 * Also being used in the codec's converter format. */
524#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
525 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
526 | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
527 | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
528 | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
529 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
530 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
531
532/** Interrupt on completion (IOC) flag. */
533#define HDA_BDLE_F_IOC RT_BIT(0)
534
535
536
537/** The HDA controller. */
538typedef struct HDASTATE *PHDASTATE;
539/** The HDA stream. */
540typedef struct HDASTREAM *PHDASTREAM;
541
542typedef struct HDAMIXERSINK *PHDAMIXERSINK;
543
544
545/**
546 * Internal state of a Buffer Descriptor List Entry (BDLE),
547 * needed to keep track of the data needed for the actual device
548 * emulation.
549 */
550typedef struct HDABDLESTATE
551{
552 /** Own index within the BDL (Buffer Descriptor List). */
553 uint32_t u32BDLIndex;
554 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
555 * Used to check if we need fill up the FIFO again. */
556 uint32_t cbBelowFIFOW;
557 /** Current offset in DMA buffer (in bytes).*/
558 uint32_t u32BufOff;
559 uint32_t Padding;
560} HDABDLESTATE, *PHDABDLESTATE;
561
562/**
563 * BDL description structure.
564 * Do not touch this, as this must match to the HDA specs.
565 */
566typedef struct HDABDLEDESC
567{
568 /** Starting address of the actual buffer. Must be 128-bit aligned. */
569 uint64_t u64BufAddr;
570 /** Size of the actual buffer (in bytes). */
571 uint32_t u32BufSize;
572 /** Bit 0: Interrupt on completion; the controller will generate
573 * an interrupt when the last byte of the buffer has been
574 * fetched by the DMA engine.
575 *
576 * Rest is reserved for further use and must be 0. */
577 uint32_t fFlags;
578} HDABDLEDESC, *PHDABDLEDESC;
579AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
580
581/**
582 * Buffer Descriptor List Entry (BDLE) (3.6.3).
583 */
584typedef struct HDABDLE
585{
586 /** The actual BDL description. */
587 HDABDLEDESC Desc;
588 /** Internal state of this BDLE.
589 * Not part of the actual BDLE registers. */
590 HDABDLESTATE State;
591} HDABDLE;
592AssertCompileSizeAlignment(HDABDLE, 8);
593/** Pointer to a buffer descriptor list entry (BDLE). */
594typedef HDABDLE *PHDABDLE;
595
596/** @name Object lookup functions.
597 * @{
598 */
599#ifdef IN_RING3
600PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATE pThis, uint8_t uSD);
601#endif
602PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
603PHDASTREAM hdaGetStreamFromSD(PHDASTATE pThis, uint8_t uSD);
604#ifdef IN_RING3
605PHDASTREAM hdaR3GetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink);
606#endif
607/** @} */
608
609/** @name Interrupt functions.
610 * @{
611 */
612#ifdef LOG_ENABLED
613int hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
614# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
615#else
616int hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
617# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
618#endif
619/** @} */
620
621/** @name Wall clock (WALCLK) functions.
622 * @{
623 */
624uint64_t hdaWalClkGetCurrent(PHDASTATE pThis);
625#ifdef IN_RING3
626bool hdaR3WalClkSet(PHDASTATE pThis, uint64_t u64WalClk, bool fForce);
627#endif
628/** @} */
629
630/** @name DMA utility functions.
631 * @{
632 */
633#ifdef IN_RING3
634int hdaR3DMARead(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf, uint32_t *pcbRead);
635int hdaR3DMAWrite(PHDASTATE pThis, PHDASTREAM pStream, const void *pvBuf, uint32_t cbBuf, uint32_t *pcbWritten);
636#endif
637/** @} */
638
639/** @name Register functions.
640 * @{
641 */
642uint32_t hdaGetINTSTS(PHDASTATE pThis);
643#ifdef IN_RING3
644int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
645#endif /* IN_RING3 */
646/** @} */
647
648/** @name BDLE (Buffer Descriptor List Entry) functions.
649 * @{
650 */
651#ifdef IN_RING3
652# ifdef LOG_ENABLED
653void hdaR3BDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
654# endif
655int hdaR3BDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
656bool hdaR3BDLEIsComplete(PHDABDLE pBDLE);
657bool hdaR3BDLENeedsInterrupt(PHDABDLE pBDLE);
658#endif /* IN_RING3 */
659/** @} */
660
661/** @name Device timer functions.
662 * @{
663 */
664#ifdef IN_RING3
665bool hdaR3TimerSet(PPDMDEVINS pDevIns, PHDASTREAM pStream, uint64_t u64Expire, bool fForce, uint64_t tsNow);
666#endif
667/** @} */
668
669#endif /* !VBOX_INCLUDED_SRC_Audio_DevHDACommon_h */
670
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