DevHDA.cpp@ 75606

最後變更在這個檔案從75606是 75606,由 vboxsync 提交於 6 年前

r126749 (5.2: Audio/CoreAudio: Resolved a todo: Use the stream backend's buffer size for initializing the internal ring buffer instead of some random value).
r126747 (5.2: Audio/AC97: Removed dead code (VBOX_WITH_AUDIO_AC97_CALLBACKS, never has been used and not needed anyway)).
r126746 (5.2: Build fix).
r126745 (5.2: Audio/HDA: Renaming nit).
r126744 (5.2: Audio/AC97: Fixed setting the stream's scheduling hint).
r126743 (5.2: Audio/AC97: Fix for ichac97R3StreamAsyncIOThread() when async I/O is enabled (currently disabled)).

屬性 svn:eol-style 設為 native
屬性 svn:keywords 設為 Author Date Id Revision

檔案大小: 195.1 KB

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1	/* $Id: DevHDA.cpp 75606 2018-11-20 10:26:04Z vboxsync $ */
2	/** @file
3	* DevHDA.cpp - VBox Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2018 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.alldomusa.eu.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_HDA
27	#include <VBox/log.h>
28
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/version.h>
32	#include <VBox/AssertGuest.h>
33
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36	#include <iprt/asm-math.h>
37	#include <iprt/file.h>
38	#include <iprt/list.h>
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	# include <iprt/semaphore.h>
42	# include <iprt/string.h>
43	# include <iprt/uuid.h>
44	#endif
45
46	#include "VBoxDD.h"
47
48	#include "AudioMixBuffer.h"
49	#include "AudioMixer.h"
50
51	#include "DevHDA.h"
52	#include "DevHDACommon.h"
53
54	#include "HDACodec.h"
55	#include "HDAStream.h"
56	# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) \|\| defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
57	# include "HDAStreamChannel.h"
58	# endif
59	#include "HDAStreamMap.h"
60	#include "HDAStreamPeriod.h"
61
62	#include "DrvAudio.h"
63
64
65	/*********************************************************************************************************************************
66	* Defined Constants And Macros *
67	*********************************************************************************************************************************/
68	//#define HDA_AS_PCI_EXPRESS
69
70	/* Installs a DMA access handler (via PGM callback) to monitor
71	* HDA's DMA operations, that is, writing / reading audio stream data.
72	*
73	* !!! Note: Certain guests are that timing sensitive that when enabling !!!
74	* !!! such a handler will mess up audio completely (e.g. Windows 7). !!! */
75	//#define HDA_USE_DMA_ACCESS_HANDLER
76	#ifdef HDA_USE_DMA_ACCESS_HANDLER
77	# include <VBox/vmm/pgm.h>
78	#endif
79
80	/* Uses the DMA access handler to read the written DMA audio (output) data.
81	* Only valid if HDA_USE_DMA_ACCESS_HANDLER is set.
82	*
83	* Also see the note / warning for HDA_USE_DMA_ACCESS_HANDLER. */
84	//# define HDA_USE_DMA_ACCESS_HANDLER_WRITING
85
86	/* Useful to debug the device' timing. */
87	//#define HDA_DEBUG_TIMING
88
89	/* To debug silence coming from the guest in form of audio gaps.
90	* Very crude implementation for now. */
91	//#define HDA_DEBUG_SILENCE
92
93	#if defined(VBOX_WITH_HP_HDA)
94	/* HP Pavilion dv4t-1300 */
95	# define HDA_PCI_VENDOR_ID 0x103c
96	# define HDA_PCI_DEVICE_ID 0x30f7
97	#elif defined(VBOX_WITH_INTEL_HDA)
98	/* Intel HDA controller */
99	# define HDA_PCI_VENDOR_ID 0x8086
100	# define HDA_PCI_DEVICE_ID 0x2668
101	#elif defined(VBOX_WITH_NVIDIA_HDA)
102	/* nVidia HDA controller */
103	# define HDA_PCI_VENDOR_ID 0x10de
104	# define HDA_PCI_DEVICE_ID 0x0ac0
105	#else
106	# error "Please specify your HDA device vendor/device IDs"
107	#endif
108
109	/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
110	#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
111	# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
112	#endif
113
114	/**
115	* Acquires the HDA lock.
116	*/
117	#define DEVHDA_LOCK(a_pThis) \
118	do { \
119	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
120	AssertRC(rcLock); \
121	} while (0)
122
123	/**
124	* Acquires the HDA lock or returns.
125	*/
126	# define DEVHDA_LOCK_RETURN(a_pThis, a_rcBusy) \
127	do { \
128	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, a_rcBusy); \
129	if (rcLock != VINF_SUCCESS) \
130	{ \
131	AssertRC(rcLock); \
132	return rcLock; \
133	} \
134	} while (0)
135
136	/**
137	* Acquires the HDA lock or returns.
138	*/
139	# define DEVHDA_LOCK_RETURN_VOID(a_pThis) \
140	do { \
141	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
142	if (rcLock != VINF_SUCCESS) \
143	{ \
144	AssertRC(rcLock); \
145	return; \
146	} \
147	} while (0)
148
149	/**
150	* Releases the HDA lock.
151	*/
152	#define DEVHDA_UNLOCK(a_pThis) \
153	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
154
155	/**
156	* Acquires the TM lock and HDA lock, returns on failure.
157	*/
158	#define DEVHDA_LOCK_BOTH_RETURN_VOID(a_pThis, a_SD) \
159	do { \
160	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], VERR_IGNORED); \
161	if (rcLock != VINF_SUCCESS) \
162	{ \
163	AssertRC(rcLock); \
164	return; \
165	} \
166	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
167	if (rcLock != VINF_SUCCESS) \
168	{ \
169	AssertRC(rcLock); \
170	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
171	return; \
172	} \
173	} while (0)
174
175	/**
176	* Acquires the TM lock and HDA lock, returns on failure.
177	*/
178	#define DEVHDA_LOCK_BOTH_RETURN(a_pThis, a_SD, a_rcBusy) \
179	do { \
180	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], (a_rcBusy)); \
181	if (rcLock != VINF_SUCCESS) \
182	return rcLock; \
183	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
184	if (rcLock != VINF_SUCCESS) \
185	{ \
186	AssertRC(rcLock); \
187	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
188	return rcLock; \
189	} \
190	} while (0)
191
192	/**
193	* Releases the HDA lock and TM lock.
194	*/
195	#define DEVHDA_UNLOCK_BOTH(a_pThis, a_SD) \
196	do { \
197	PDMCritSectLeave(&(a_pThis)->CritSect); \
198	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
199	} while (0)
200
201
202	/*********************************************************************************************************************************
203	* Structures and Typedefs *
204	*********************************************************************************************************************************/
205
206	/**
207	* Structure defining a (host backend) driver stream.
208	* Each driver has its own instances of audio mixer streams, which then
209	* can go into the same (or even different) audio mixer sinks.
210	*/
211	typedef struct HDADRIVERSTREAM
212	{
213	/** Associated mixer handle. */
214	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
215	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
216
217	#ifdef HDA_USE_DMA_ACCESS_HANDLER
218	/**
219	* Struct for keeping an HDA DMA access handler context.
220	*/
221	typedef struct HDADMAACCESSHANDLER
222	{
223	/** Node for storing this handler in our list in HDASTREAMSTATE. */
224	RTLISTNODER3 Node;
225	/** Pointer to stream to which this access handler is assigned to. */
226	R3PTRTYPE(PHDASTREAM) pStream;
227	/** Access handler type handle. */
228	PGMPHYSHANDLERTYPE hAccessHandlerType;
229	/** First address this handler uses. */
230	RTGCPHYS GCPhysFirst;
231	/** Last address this handler uses. */
232	RTGCPHYS GCPhysLast;
233	/** Actual BDLE address to handle. */
234	RTGCPHYS BDLEAddr;
235	/** Actual BDLE buffer size to handle. */
236	RTGCPHYS BDLESize;
237	/** Whether the access handler has been registered or not. */
238	bool fRegistered;
239	uint8_t Padding[3];
240	} HDADMAACCESSHANDLER, *PHDADMAACCESSHANDLER;
241	#endif
242
243	/**
244	* Struct for maintaining a host backend driver.
245	* This driver must be associated to one, and only one,
246	* HDA codec. The HDA controller does the actual multiplexing
247	* of HDA codec data to various host backend drivers then.
248	*
249	* This HDA device uses a timer in order to synchronize all
250	* read/write accesses across all attached LUNs / backends.
251	*/
252	typedef struct HDADRIVER
253	{
254	/** Node for storing this driver in our device driver list of HDASTATE. */
255	RTLISTNODER3 Node;
256	/** Pointer to HDA controller (state). */
257	R3PTRTYPE(PHDASTATE) pHDAState;
258	/** Driver flags. */
259	PDMAUDIODRVFLAGS fFlags;
260	uint8_t u32Padding0[2];
261	/** LUN to which this driver has been assigned. */
262	uint8_t uLUN;
263	/** Whether this driver is in an attached state or not. */
264	bool fAttached;
265	/** Pointer to attached driver base interface. */
266	R3PTRTYPE(PPDMIBASE) pDrvBase;
267	/** Audio connector interface to the underlying host backend. */
268	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
269	/** Mixer stream for line input. */
270	HDADRIVERSTREAM LineIn;
271	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
272	/** Mixer stream for mic input. */
273	HDADRIVERSTREAM MicIn;
274	#endif
275	/** Mixer stream for front output. */
276	HDADRIVERSTREAM Front;
277	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
278	/** Mixer stream for center/LFE output. */
279	HDADRIVERSTREAM CenterLFE;
280	/** Mixer stream for rear output. */
281	HDADRIVERSTREAM Rear;
282	#endif
283	} HDADRIVER;
284
285
286	/*********************************************************************************************************************************
287	* Internal Functions *
288	*********************************************************************************************************************************/
289	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
290	#ifdef IN_RING3
291	static void hdaR3GCTLReset(PHDASTATE pThis);
292	#endif
293
294	/** @name Register read/write stubs.
295	* @{
296	*/
297	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
298	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
299	/** @} */
300
301	/** @name Global register set read/write functions.
302	* @{
303	*/
304	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
305	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
306	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
307	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
308	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
309	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
310	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
311	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
312	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
313	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
314	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
315	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
316	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
317	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
318	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
319	/** @} */
320
321	/** @name {IOB}SDn write functions.
322	* @{
323	*/
324	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
325	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
326	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
327	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
328	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
329	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
330	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
331	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
332	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
333	/** @} */
334
335	/** @name Generic register read/write functions.
336	* @{
337	*/
338	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
339	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
340	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
341	#ifdef IN_RING3
342	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
343	#endif
344	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
345	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
346	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
347	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
348	/** @} */
349
350	/** @name HDA device functions.
351	* @{
352	*/
353	#ifdef IN_RING3
354	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
355	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
356	# ifdef HDA_USE_DMA_ACCESS_HANDLER
357	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
358	void *pvBuf, size_t cbBuf,
359	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
360	# endif
361	#endif /* IN_RING3 */
362	/** @} */
363
364	/** @name HDA mixer functions.
365	* @{
366	*/
367	#ifdef IN_RING3
368	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv);
369	#endif
370	/** @} */
371
372
373	/*********************************************************************************************************************************
374	* Global Variables *
375	*********************************************************************************************************************************/
376
377	/** No register description (RD) flags defined. */
378	#define HDA_RD_FLAG_NONE 0
379	/** Writes to SD are allowed while RUN bit is set. */
380	#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
381
382	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
383	#define HDA_REG_MAP_STRM(offset, name) \
384	/* offset size read mask write mask flags read callback write callback index + abbrev description */ \
385	/* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
386	/* Offset 0x80 (SD0) */ \
387	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
388	/* Offset 0x83 (SD0) */ \
389	{ offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
390	/* Offset 0x84 (SD0) */ \
391	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
392	/* Offset 0x88 (SD0) */ \
393	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
394	/* Offset 0x8C (SD0) */ \
395	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
396	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
397	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
398	/* Offset 0x90 (SD0) */ \
399	{ offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
400	/* Offset 0x92 (SD0) */ \
401	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
402	/* Reserved: 0x94 - 0x98. */ \
403	/* Offset 0x98 (SD0) */ \
404	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
405	/* Offset 0x9C (SD0) */ \
406	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
407
408	/** Defines a single audio stream register set (e.g. OSD0). */
409	#define HDA_REG_MAP_DEF_STREAM(index, name) \
410	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
411
412	/* See 302349 p 6.2. */
413	const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
414	{
415	/* offset size read mask write mask flags read callback write callback index + abbrev */
416	/------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ /
417	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
418	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
419	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
420	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
421	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
422	{ 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
423	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
424	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
425	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
426	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
427	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
428	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
429	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
430	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
431	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
432	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
433	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
434	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
435	{ 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
436	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
437	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
438	{ 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
439	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
440	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
441	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
442	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
443	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
444	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
445	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
446	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
447	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
448	{ 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
449	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
450	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
451	/* 4 Serial Data In (SDI). */
452	HDA_REG_MAP_DEF_STREAM(0, SD0),
453	HDA_REG_MAP_DEF_STREAM(1, SD1),
454	HDA_REG_MAP_DEF_STREAM(2, SD2),
455	HDA_REG_MAP_DEF_STREAM(3, SD3),
456	/* 4 Serial Data Out (SDO). */
457	HDA_REG_MAP_DEF_STREAM(4, SD4),
458	HDA_REG_MAP_DEF_STREAM(5, SD5),
459	HDA_REG_MAP_DEF_STREAM(6, SD6),
460	HDA_REG_MAP_DEF_STREAM(7, SD7)
461	};
462
463	const HDAREGALIAS g_aHdaRegAliases[] =
464	{
465	{ 0x2084, HDA_REG_SD0LPIB },
466	{ 0x20a4, HDA_REG_SD1LPIB },
467	{ 0x20c4, HDA_REG_SD2LPIB },
468	{ 0x20e4, HDA_REG_SD3LPIB },
469	{ 0x2104, HDA_REG_SD4LPIB },
470	{ 0x2124, HDA_REG_SD5LPIB },
471	{ 0x2144, HDA_REG_SD6LPIB },
472	{ 0x2164, HDA_REG_SD7LPIB }
473	};
474
475	#ifdef IN_RING3
476
477	/** HDABDLEDESC field descriptors for the v7 saved state. */
478	static SSMFIELD const g_aSSMBDLEDescFields7[] =
479	{
480	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
481	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
482	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
483	SSMFIELD_ENTRY_TERM()
484	};
485
486	/** HDABDLESTATE field descriptors for the v6+ saved state. */
487	static SSMFIELD const g_aSSMBDLEStateFields6[] =
488	{
489	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
490	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
491	SSMFIELD_ENTRY_OLD(FIFO, HDA_FIFO_MAX), /* Deprecated; now is handled in the stream's circular buffer. */
492	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
493	SSMFIELD_ENTRY_TERM()
494	};
495
496	/** HDABDLESTATE field descriptors for the v7 saved state. */
497	static SSMFIELD const g_aSSMBDLEStateFields7[] =
498	{
499	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
500	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
501	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
502	SSMFIELD_ENTRY_TERM()
503	};
504
505	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
506	static SSMFIELD const g_aSSMStreamStateFields6[] =
507	{
508	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
509	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
510	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
511	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
512	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
513	SSMFIELD_ENTRY_TERM()
514	};
515
516	/** HDASTREAMSTATE field descriptors for the v7 saved state. */
517	static SSMFIELD const g_aSSMStreamStateFields7[] =
518	{
519	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
520	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
521	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
522	SSMFIELD_ENTRY_TERM()
523	};
524
525	/** HDASTREAMPERIOD field descriptors for the v7 saved state. */
526	static SSMFIELD const g_aSSMStreamPeriodFields7[] =
527	{
528	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64StartWalClk),
529	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64ElapsedWalClk),
530	SSMFIELD_ENTRY(HDASTREAMPERIOD, framesTransferred),
531	SSMFIELD_ENTRY(HDASTREAMPERIOD, cIntPending),
532	SSMFIELD_ENTRY_TERM()
533	};
534
535	/**
536	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
537	*/
538	static uint32_t const g_afMasks[5] =
539	{
540	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
541	};
542
543	#endif /* IN_RING3 */
544
545
546
547	/**
548	* Retrieves the number of bytes of a FIFOW register.
549	*
550	* @return Number of bytes of a given FIFOW register.
551	*/
552	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
553	{
554	uint32_t cb;
555	switch (u32RegFIFOW)
556	{
557	case HDA_SDFIFOW_8B: cb = 8; break;
558	case HDA_SDFIFOW_16B: cb = 16; break;
559	case HDA_SDFIFOW_32B: cb = 32; break;
560	default: cb = 0; break;
561	}
562
563	Assert(RT_IS_POWER_OF_TWO(cb));
564	return cb;
565	}
566
567	#ifdef IN_RING3
568	/**
569	* Reschedules pending interrupts for all audio streams which have complete
570	* audio periods but did not have the chance to issue their (pending) interrupts yet.
571	*
572	* @param pThis The HDA device state.
573	*/
574	static void hdaR3ReschedulePendingInterrupts(PHDASTATE pThis)
575	{
576	bool fInterrupt = false;
577
578	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
579	{
580	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
581	if (!pStream)
582	continue;
583
584	if ( hdaR3StreamPeriodIsComplete (&pStream->State.Period)
585	&& hdaR3StreamPeriodNeedsInterrupt(&pStream->State.Period)
586	&& hdaR3WalClkSet(pThis, hdaR3StreamPeriodGetAbsElapsedWalClk(&pStream->State.Period), false /* fForce */))
587	{
588	fInterrupt = true;
589	break;
590	}
591	}
592
593	LogFunc(("fInterrupt=%RTbool\n", fInterrupt));
594
595	# ifndef LOG_ENABLED
596	hdaProcessInterrupt(pThis);
597	# else
598	hdaProcessInterrupt(pThis, __FUNCTION__);
599	# endif
600	}
601	#endif /* IN_RING3 */
602
603	/**
604	* Looks up a register at the exact offset given by @a offReg.
605	*
606	* @returns Register index on success, -1 if not found.
607	* @param offReg The register offset.
608	*/
609	static int hdaRegLookup(uint32_t offReg)
610	{
611	/*
612	* Aliases.
613	*/
614	if (offReg >= g_aHdaRegAliases[0].offReg)
615	{
616	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
617	if (offReg == g_aHdaRegAliases[i].offReg)
618	return g_aHdaRegAliases[i].idxAlias;
619	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
620	return -1;
621	}
622
623	/*
624	* Binary search the
625	*/
626	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
627	int idxLow = 0;
628	for (;;)
629	{
630	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
631	if (offReg < g_aHdaRegMap[idxMiddle].offset)
632	{
633	if (idxLow == idxMiddle)
634	break;
635	idxEnd = idxMiddle;
636	}
637	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
638	{
639	idxLow = idxMiddle + 1;
640	if (idxLow >= idxEnd)
641	break;
642	}
643	else
644	return idxMiddle;
645	}
646
647	#ifdef RT_STRICT
648	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
649	Assert(g_aHdaRegMap[i].offset != offReg);
650	#endif
651	return -1;
652	}
653
654	#ifdef IN_RING3
655
656	/**
657	* Looks up a register covering the offset given by @a offReg.
658	*
659	* @returns Register index on success, -1 if not found.
660	* @param offReg The register offset.
661	*/
662	static int hdaR3RegLookupWithin(uint32_t offReg)
663	{
664	/*
665	* Aliases.
666	*/
667	if (offReg >= g_aHdaRegAliases[0].offReg)
668	{
669	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
670	{
671	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
672	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
673	return g_aHdaRegAliases[i].idxAlias;
674	}
675	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
676	return -1;
677	}
678
679	/*
680	* Binary search the register map.
681	*/
682	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
683	int idxLow = 0;
684	for (;;)
685	{
686	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
687	if (offReg < g_aHdaRegMap[idxMiddle].offset)
688	{
689	if (idxLow == idxMiddle)
690	break;
691	idxEnd = idxMiddle;
692	}
693	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
694	{
695	idxLow = idxMiddle + 1;
696	if (idxLow >= idxEnd)
697	break;
698	}
699	else
700	return idxMiddle;
701	}
702
703	# ifdef RT_STRICT
704	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
705	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
706	# endif
707	return -1;
708	}
709
710
711	/**
712	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
713	*
714	* @returns IPRT status code.
715	* @param pThis HDA state.
716	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
717	* or false to synchronize the device state's RIRB buffer with the HDA state.
718	*
719	* @todo r=andy Break this up into two functions?
720	*/
721	static int hdaR3CmdSync(PHDASTATE pThis, bool fLocal)
722	{
723	int rc = VINF_SUCCESS;
724	if (fLocal)
725	{
726	if (pThis->u64CORBBase)
727	{
728	AssertPtr(pThis->pu32CorbBuf);
729	Assert(pThis->cbCorbBuf);
730
731	/** @todo r=bird: An explanation is required why PDMDevHlpPhysRead is used with
732	* the CORB and PDMDevHlpPCIPhysWrite with RIRB below. There are
733	* similar unexplained inconsistencies in DevHDACommon.cpp. */
734	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
735	Log(("hdaR3CmdSync/CORB: read %RGp LB %#x (%Rrc)\n", pThis->u64CORBBase, pThis->cbCorbBuf, rc));
736	AssertRCReturn(rc, rc);
737	}
738	}
739	else
740	{
741	if (pThis->u64RIRBBase)
742	{
743	AssertPtr(pThis->pu64RirbBuf);
744	Assert(pThis->cbRirbBuf);
745
746	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
747	Log(("hdaR3CmdSync/RIRB: phys read %RGp LB %#x (%Rrc)\n", pThis->u64RIRBBase, pThis->pu64RirbBuf, rc));
748	AssertRCReturn(rc, rc);
749	}
750	}
751
752	# ifdef DEBUG_CMD_BUFFER
753	LogFunc(("fLocal=%RTbool\n", fLocal));
754
755	uint8_t i = 0;
756	do
757	{
758	LogFunc(("CORB%02x: ", i));
759	uint8_t j = 0;
760	do
761	{
762	const char *pszPrefix;
763	if ((i + j) == HDA_REG(pThis, CORBRP))
764	pszPrefix = "[R]";
765	else if ((i + j) == HDA_REG(pThis, CORBWP))
766	pszPrefix = "[W]";
767	else
768	pszPrefix = " "; /* three spaces */
769	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
770	j++;
771	} while (j < 8);
772	Log(("\n"));
773	i += 8;
774	} while(i != 0);
775
776	do
777	{
778	LogFunc(("RIRB%02x: ", i));
779	uint8_t j = 0;
780	do
781	{
782	const char *prefix;
783	if ((i + j) == HDA_REG(pThis, RIRBWP))
784	prefix = "[W]";
785	else
786	prefix = " ";
787	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
788	} while (++j < 8);
789	Log(("\n"));
790	i += 8;
791	} while (i != 0);
792	# endif
793	return rc;
794	}
795
796	/**
797	* Processes the next CORB buffer command in the queue.
798	*
799	* This will invoke the HDA codec verb dispatcher.
800	*
801	* @returns IPRT status code.
802	* @param pThis HDA state.
803	*/
804	static int hdaR3CORBCmdProcess(PHDASTATE pThis)
805	{
806	uint8_t corbRp = HDA_REG(pThis, CORBRP);
807	uint8_t corbWp = HDA_REG(pThis, CORBWP);
808	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
809
810	Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", corbRp, corbWp, rirbWp));
811
812	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
813	{
814	LogFunc(("CORB DMA not active, skipping\n"));
815	return VINF_SUCCESS;
816	}
817
818	Assert(pThis->cbCorbBuf);
819
820	int rc = hdaR3CmdSync(pThis, true /* Sync from guest */);
821	AssertRCReturn(rc, rc);
822
823	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
824
825	if (!cIntCnt) /* 0 means 256 interrupts. */
826	cIntCnt = HDA_MAX_RINTCNT;
827
828	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
829	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
830
831	while (corbRp != corbWp)
832	{
833	corbRp = (corbRp + 1) % (pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE); /* Advance +1 as the first command(s) are at CORBWP + 1. */
834
835	uint32_t uCmd = pThis->pu32CorbBuf[corbRp];
836	uint64_t uResp = 0;
837
838	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
839	if (RT_FAILURE(rc))
840	LogFunc(("Codec lookup failed with rc=%Rrc\n", rc));
841
842	Log3Func(("Codec verb %08x -> response %016lx\n", uCmd, uResp));
843
844	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
845	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
846	{
847	LogFunc(("Unexpected unsolicited response.\n"));
848	HDA_REG(pThis, CORBRP) = corbRp;
849
850	/** @todo r=andy No CORB/RIRB syncing to guest required in that case? */
851	return rc;
852	}
853
854	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
855
856	pThis->pu64RirbBuf[rirbWp] = uResp;
857
858	pThis->u16RespIntCnt++;
859
860	bool fSendInterrupt = false;
861
862	if (pThis->u16RespIntCnt == cIntCnt) /* Response interrupt count reached? */
863	{
864	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
865
866	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
867	fSendInterrupt = true;
868
869	}
870	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
871	{
872	Log3Func(("Command buffer empty\n"));
873	fSendInterrupt = true;
874	}
875
876	if (fSendInterrupt)
877	{
878	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
879	{
880	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
881
882	# ifndef LOG_ENABLED
883	rc = hdaProcessInterrupt(pThis);
884	# else
885	rc = hdaProcessInterrupt(pThis, __FUNCTION__);
886	# endif
887	}
888	}
889	}
890
891	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
892	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
893
894	HDA_REG(pThis, CORBRP) = corbRp;
895	HDA_REG(pThis, RIRBWP) = rirbWp;
896
897	rc = hdaR3CmdSync(pThis, false /* Sync to guest */);
898	AssertRCReturn(rc, rc);
899
900	if (RT_FAILURE(rc))
901	AssertRCReturn(rc, rc);
902
903	return rc;
904	}
905
906	#endif /* IN_RING3 */
907
908	/* Register access handlers. */
909
910	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
911	{
912	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
913	*pu32Value = 0;
914	return VINF_SUCCESS;
915	}
916
917	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
918	{
919	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
920	return VINF_SUCCESS;
921	}
922
923	/* U8 */
924	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
925	{
926	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
927	return hdaRegReadU32(pThis, iReg, pu32Value);
928	}
929
930	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
931	{
932	Assert((u32Value & 0xffffff00) == 0);
933	return hdaRegWriteU32(pThis, iReg, u32Value);
934	}
935
936	/* U16 */
937	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
938	{
939	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
940	return hdaRegReadU32(pThis, iReg, pu32Value);
941	}
942
943	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
944	{
945	Assert((u32Value & 0xffff0000) == 0);
946	return hdaRegWriteU32(pThis, iReg, u32Value);
947	}
948
949	/* U24 */
950	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
951	{
952	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
953	return hdaRegReadU32(pThis, iReg, pu32Value);
954	}
955
956	#ifdef IN_RING3
957	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
958	{
959	Assert((u32Value & 0xff000000) == 0);
960	return hdaRegWriteU32(pThis, iReg, u32Value);
961	}
962	#endif
963
964	/* U32 */
965	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
966	{
967	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
968
969	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
970
971	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
972
973	DEVHDA_UNLOCK(pThis);
974	return VINF_SUCCESS;
975	}
976
977	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
978	{
979	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
980
981	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
982
983	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
984	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
985	DEVHDA_UNLOCK(pThis);
986	return VINF_SUCCESS;
987	}
988
989	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
990	{
991	RT_NOREF_PV(iReg);
992	#ifdef IN_RING3
993	DEVHDA_LOCK(pThis);
994	#else
995	if (!(u32Value & HDA_GCTL_CRST))
996	return VINF_IOM_R3_MMIO_WRITE;
997	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
998	#endif
999
1000	if (u32Value & HDA_GCTL_CRST)
1001	{
1002	/* Set the CRST bit to indicate that we're leaving reset mode. */
1003	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
1004	LogFunc(("Guest leaving HDA reset\n"));
1005	}
1006	else
1007	{
1008	#ifdef IN_RING3
1009	/* Enter reset state. */
1010	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1011	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1012	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1013
1014	/* Clear the CRST bit to indicate that we're in reset state. */
1015	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1016
1017	hdaR3GCTLReset(pThis);
1018	#else
1019	AssertFailedReturnStmt(DEVHDA_UNLOCK(pThis), VINF_IOM_R3_MMIO_WRITE);
1020	#endif
1021	}
1022
1023	if (u32Value & HDA_GCTL_FCNTRL)
1024	{
1025	/* Flush: GSTS:1 set, see 6.2.6. */
1026	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1027	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1028	}
1029
1030	DEVHDA_UNLOCK(pThis);
1031	return VINF_SUCCESS;
1032	}
1033
1034	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1035	{
1036	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1037
1038	uint32_t v = HDA_REG_IND(pThis, iReg);
1039	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1040
1041	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1042
1043	DEVHDA_UNLOCK(pThis);
1044	return VINF_SUCCESS;
1045	}
1046
1047	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1048	{
1049	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
1050
1051	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1052	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1053	#ifdef LOG_ENABLED
1054	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
1055	LogFlowFunc(("[SD%RU8] LPIB=%RU32, CBL=%RU32\n", uSD, u32LPIB, u32CBL));
1056	#endif
1057
1058	*pu32Value = u32LPIB;
1059
1060	DEVHDA_UNLOCK(pThis);
1061	return VINF_SUCCESS;
1062	}
1063
1064	#ifdef IN_RING3
1065	/**
1066	* Returns the current maximum value the wall clock counter can be set to.
1067	* This maximum value depends on all currently handled HDA streams and their own current timing.
1068	*
1069	* @return Current maximum value the wall clock counter can be set to.
1070	* @param pThis HDA state.
1071	*
1072	* @remark Does not actually set the wall clock counter.
1073	*/
1074	static uint64_t hdaR3WalClkGetMax(PHDASTATE pThis)
1075	{
1076	const uint64_t u64WalClkCur = ASMAtomicReadU64(&pThis->u64WalClk);
1077	const uint64_t u64FrontAbsWalClk = pThis->SinkFront.pStream
1078	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkFront.pStream->State.Period) : 0;
1079	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1080	# error "Implement me!"
1081	# endif
1082	const uint64_t u64LineInAbsWalClk = pThis->SinkLineIn.pStream
1083	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkLineIn.pStream->State.Period) : 0;
1084	# ifdef VBOX_WITH_HDA_MIC_IN
1085	const uint64_t u64MicInAbsWalClk = pThis->SinkMicIn.pStream
1086	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkMicIn.pStream->State.Period) : 0;
1087	# endif
1088
1089	uint64_t u64WalClkNew = RT_MAX(u64WalClkCur, u64FrontAbsWalClk);
1090	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1091	# error "Implement me!"
1092	# endif
1093	u64WalClkNew = RT_MAX(u64WalClkNew, u64LineInAbsWalClk);
1094	# ifdef VBOX_WITH_HDA_MIC_IN
1095	u64WalClkNew = RT_MAX(u64WalClkNew, u64MicInAbsWalClk);
1096	# endif
1097
1098	Log3Func(("%RU64 -> Front=%RU64, LineIn=%RU64 -> %RU64\n",
1099	u64WalClkCur, u64FrontAbsWalClk, u64LineInAbsWalClk, u64WalClkNew));
1100
1101	return u64WalClkNew;
1102	}
1103	#endif /* IN_RING3 */
1104
1105	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1106	{
1107	#ifdef IN_RING3
1108	RT_NOREF(iReg);
1109
1110	DEVHDA_LOCK(pThis);
1111
1112	*pu32Value = RT_LO_U32(ASMAtomicReadU64(&pThis->u64WalClk));
1113
1114	Log3Func(("%RU32 (max @ %RU64)\n",*pu32Value, hdaR3WalClkGetMax(pThis)));
1115
1116	DEVHDA_UNLOCK(pThis);
1117	return VINF_SUCCESS;
1118	#else
1119	RT_NOREF(pThis, iReg, pu32Value);
1120	return VINF_IOM_R3_MMIO_READ;
1121	#endif
1122	}
1123
1124	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1125	{
1126	RT_NOREF(iReg);
1127	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1128
1129	if (u32Value & HDA_CORBRP_RST)
1130	{
1131	/* Do a CORB reset. */
1132	if (pThis->cbCorbBuf)
1133	{
1134	#ifdef IN_RING3
1135	Assert(pThis->pu32CorbBuf);
1136	RT_BZERO((void *)pThis->pu32CorbBuf, pThis->cbCorbBuf);
1137	#else
1138	DEVHDA_UNLOCK(pThis);
1139	return VINF_IOM_R3_MMIO_WRITE;
1140	#endif
1141	}
1142
1143	LogRel2(("HDA: CORB reset\n"));
1144
1145	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1146	}
1147	else
1148	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1149
1150	DEVHDA_UNLOCK(pThis);
1151	return VINF_SUCCESS;
1152	}
1153
1154	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1155	{
1156	#ifdef IN_RING3
1157	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1158
1159	int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1160	AssertRC(rc);
1161
1162	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Start DMA engine. */
1163	{
1164	rc = hdaR3CORBCmdProcess(pThis);
1165	}
1166	else
1167	LogFunc(("CORB DMA not running, skipping\n"));
1168
1169	DEVHDA_UNLOCK(pThis);
1170	return rc;
1171	#else
1172	RT_NOREF(pThis, iReg, u32Value);
1173	return VINF_IOM_R3_MMIO_WRITE;
1174	#endif
1175	}
1176
1177	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1178	{
1179	#ifdef IN_RING3
1180	RT_NOREF(iReg);
1181	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1182
1183	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
1184	{
1185	LogFunc(("CORB DMA is (still) running, skipping\n"));
1186
1187	DEVHDA_UNLOCK(pThis);
1188	return VINF_SUCCESS;
1189	}
1190
1191	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1192
1193	uint16_t cEntries = HDA_CORB_SIZE; /* Set default. */
1194
1195	switch (u32Value)
1196	{
1197	case 0: /* 8 byte; 2 entries. */
1198	cEntries = 2;
1199	break;
1200
1201	case 1: /* 64 byte; 16 entries. */
1202	cEntries = 16;
1203	break;
1204
1205	case 2: /* 1 KB; 256 entries. */
1206	/* Use default size. */
1207	break;
1208
1209	default:
1210	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1211	u32Value = 2;
1212	/* Use default size. */
1213	break;
1214	}
1215
1216	uint32_t cbCorbBuf = cEntries * HDA_CORB_ELEMENT_SIZE;
1217	Assert(cbCorbBuf <= HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Paranoia. */
1218
1219	if (cbCorbBuf != pThis->cbCorbBuf)
1220	{
1221	RT_BZERO(pThis->pu32CorbBuf, HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Clear CORB when setting a new size. */
1222	pThis->cbCorbBuf = cbCorbBuf;
1223	}
1224
1225	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1226
1227	HDA_REG(pThis, CORBSIZE) = u32Value;
1228
1229	DEVHDA_UNLOCK(pThis);
1230	return VINF_SUCCESS;
1231	#else
1232	RT_NOREF(pThis, iReg, u32Value);
1233	return VINF_IOM_R3_MMIO_WRITE;
1234	#endif
1235	}
1236
1237	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1238	{
1239	RT_NOREF_PV(iReg);
1240	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1241
1242	uint32_t v = HDA_REG(pThis, CORBSTS);
1243	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1244
1245	DEVHDA_UNLOCK(pThis);
1246	return VINF_SUCCESS;
1247	}
1248
1249	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1250	{
1251	#ifdef IN_RING3
1252	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1253
1254	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1255	AssertRCSuccess(rc);
1256
1257	rc = hdaR3CORBCmdProcess(pThis);
1258
1259	DEVHDA_UNLOCK(pThis);
1260	return rc;
1261	#else
1262	RT_NOREF(pThis, iReg, u32Value);
1263	return VINF_IOM_R3_MMIO_WRITE;
1264	#endif
1265	}
1266
1267	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1268	{
1269	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1270
1271	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
1272	if (pStream)
1273	{
1274	pStream->u32CBL = u32Value;
1275	LogFlowFunc(("[SD%RU8] CBL=%RU32\n", pStream->u8SD, u32Value));
1276	}
1277	else
1278	LogFunc(("[SD%RU8] Warning: Changing SDCBL on non-attached stream (0x%x)\n",
1279	HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
1280
1281	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1282	AssertRCSuccess(rc);
1283
1284	DEVHDA_UNLOCK(pThis);
1285	return rc;
1286	}
1287
1288	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1289	{
1290	#ifdef IN_RING3
1291	/* Get the stream descriptor. */
1292	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1293
1294	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1295
1296	/*
1297	* Some guests write too much (that is, 32-bit with the top 8 bit being junk)
1298	* instead of 24-bit required for SDCTL. So just mask this here to be safe.
1299	*/
1300	u32Value &= 0x00ffffff;
1301
1302	bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1303	bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1304
1305	bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1306	bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1307
1308	LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1309	uSD, fRun, fInRun, fReset, fInReset, u32Value));
1310
1311	/*
1312	* Extract the stream tag the guest wants to use for this specific
1313	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1314	* state, so we're doing the lookup and assignment here.
1315	*
1316	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1317	*/
1318	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1319	if (uTag > HDA_MAX_TAGS)
1320	{
1321	LogFunc(("[SD%RU8] Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
1322
1323	int rc = hdaRegWriteU24(pThis, iReg, u32Value);
1324	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1325	return rc;
1326	}
1327
1328	PHDATAG pTag = &pThis->aTags[uTag];
1329	AssertPtr(pTag);
1330
1331	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1332
1333	/* Assign new values. */
1334	pTag->uTag = uTag;
1335	pTag->pStream = hdaGetStreamFromSD(pThis, uSD);
1336
1337	PHDASTREAM pStream = pTag->pStream;
1338	AssertPtr(pStream);
1339
1340	if (fInReset)
1341	{
1342	Assert(!fReset);
1343	Assert(!fInRun && !fRun);
1344
1345	/* Exit reset state. */
1346	ASMAtomicXchgBool(&pStream->State.fInReset, false);
1347
1348	/* Report that we're done resetting this stream by clearing SRST. */
1349	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1350
1351	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1352	}
1353	else if (fReset)
1354	{
1355	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1356	Assert(!fInRun && !fRun);
1357
1358	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1359
1360	hdaR3StreamLock(pStream);
1361
1362	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1363	hdaR3StreamAsyncIOLock(pStream);
1364	# endif
1365	/* Make sure to remove the run bit before doing the actual stream reset. */
1366	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
1367
1368	hdaR3StreamReset(pThis, pStream, pStream->u8SD);
1369
1370	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1371	hdaR3StreamAsyncIOUnlock(pStream);
1372	# endif
1373	hdaR3StreamUnlock(pStream);
1374	}
1375	else
1376	{
1377	/*
1378	* We enter here to change DMA states only.
1379	*/
1380	if (fInRun != fRun)
1381	{
1382	Assert(!fReset && !fInReset);
1383	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1384
1385	hdaR3StreamLock(pStream);
1386
1387	int rc2;
1388
1389	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1390	if (fRun)
1391	rc2 = hdaR3StreamAsyncIOCreate(pStream);
1392
1393	hdaR3StreamAsyncIOLock(pStream);
1394	# endif
1395	if (fRun)
1396	{
1397	/* (Re-)initialize the stream with current values. */
1398	rc2 = hdaR3StreamInit(pStream, pStream->u8SD);
1399	AssertRC(rc2);
1400
1401	/* Remove the old stream from the device setup. */
1402	rc2 = hdaR3RemoveStream(pThis, &pStream->State.Cfg);
1403	AssertRC(rc2);
1404
1405	/* Add the stream to the device setup. */
1406	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
1407	AssertRC(rc2);
1408	}
1409
1410	/* Enable/disable the stream. */
1411	rc2 = hdaR3StreamEnable(pStream, fRun /* fEnable */);
1412	AssertRC(rc2);
1413
1414	if (fRun)
1415	{
1416	/* Keep track of running streams. */
1417	pThis->cStreamsActive++;
1418
1419	/* (Re-)init the stream's period. */
1420	hdaR3StreamPeriodInit(&pStream->State.Period,
1421	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
1422
1423	/* Begin a new period for this stream. */
1424	rc2 = hdaR3StreamPeriodBegin(&pStream->State.Period, hdaWalClkGetCurrent(pThis)/* Use current wall clock time */);
1425	AssertRC(rc2);
1426
1427	rc2 = hdaR3TimerSet(pThis, pStream, TMTimerGet(pThis->pTimer[pStream->u8SD]) + pStream->State.cTransferTicks, false /* fForce */);
1428	AssertRC(rc2);
1429	}
1430	else
1431	{
1432	/* Keep track of running streams. */
1433	Assert(pThis->cStreamsActive);
1434	if (pThis->cStreamsActive)
1435	pThis->cStreamsActive--;
1436
1437	/* Make sure to (re-)schedule outstanding (delayed) interrupts. */
1438	hdaR3ReschedulePendingInterrupts(pThis);
1439
1440	/* Reset the period. */
1441	hdaR3StreamPeriodReset(&pStream->State.Period);
1442	}
1443
1444	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1445	hdaR3StreamAsyncIOUnlock(pStream);
1446	# endif
1447	/* Make sure to leave the lock before (eventually) starting the timer. */
1448	hdaR3StreamUnlock(pStream);
1449	}
1450	}
1451
1452	int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
1453	AssertRC(rc2);
1454
1455	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1456	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1457	#else /* !IN_RING3 */
1458	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1459	return VINF_IOM_R3_MMIO_WRITE;
1460	#endif /* IN_RING3 */
1461	}
1462
1463	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1464	{
1465	#ifdef IN_RING3
1466	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, STS, iReg);
1467
1468	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1469
1470	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1471	if (!pStream)
1472	{
1473	AssertMsgFailed(("[SD%RU8] Warning: Writing SDSTS on non-attached stream (0x%x)\n",
1474	HDA_SD_NUM_FROM_REG(pThis, STS, iReg), u32Value));
1475
1476	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1477	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1478	return rc;
1479	}
1480
1481	hdaR3StreamLock(pStream);
1482
1483	uint32_t v = HDA_REG_IND(pThis, iReg);
1484
1485	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1486	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1487
1488	/* Some guests tend to write SDnSTS even if the stream is not running.
1489	* So make sure to check if the RUN bit is set first. */
1490	const bool fRunning = pStream->State.fRunning;
1491
1492	Log3Func(("[SD%RU8] fRunning=%RTbool %R[sdsts]\n", pStream->u8SD, fRunning, v));
1493
1494	PHDASTREAMPERIOD pPeriod = &pStream->State.Period;
1495
1496	if (hdaR3StreamPeriodLock(pPeriod))
1497	{
1498	const bool fNeedsInterrupt = hdaR3StreamPeriodNeedsInterrupt(pPeriod);
1499	if (fNeedsInterrupt)
1500	hdaR3StreamPeriodReleaseInterrupt(pPeriod);
1501
1502	if (hdaR3StreamPeriodIsComplete(pPeriod))
1503	{
1504	/* Make sure to try to update the WALCLK register if a period is complete.
1505	* Use the maximum WALCLK value all (active) streams agree to. */
1506	const uint64_t uWalClkMax = hdaR3WalClkGetMax(pThis);
1507	if (uWalClkMax > hdaWalClkGetCurrent(pThis))
1508	hdaR3WalClkSet(pThis, uWalClkMax, false /* fForce */);
1509
1510	hdaR3StreamPeriodEnd(pPeriod);
1511
1512	if (fRunning)
1513	hdaR3StreamPeriodBegin(pPeriod, hdaWalClkGetCurrent(pThis) /* Use current wall clock time */);
1514	}
1515
1516	hdaR3StreamPeriodUnlock(pPeriod); /* Unlock before processing interrupt. */
1517	}
1518
1519	# ifndef LOG_ENABLED
1520	hdaProcessInterrupt(pThis);
1521	# else
1522	hdaProcessInterrupt(pThis, __FUNCTION__);
1523	# endif
1524
1525	const uint64_t tsNow = TMTimerGet(pThis->pTimer[uSD]);
1526	Assert(tsNow >= pStream->State.tsTransferLast);
1527
1528	const uint64_t cTicksElapsed = tsNow - pStream->State.tsTransferLast;
1529	# ifdef LOG_ENABLED
1530	const uint64_t cTicksTransferred = pStream->State.cbTransferProcessed * pStream->State.cTicksPerByte;
1531	# endif
1532
1533	uint64_t cTicksToNext = pStream->State.cTransferTicks;
1534	if (cTicksToNext) /* Only do any calculations if the stream currently is set up for transfers. */
1535	{
1536	Log3Func(("[SD%RU8] cTicksElapsed=%RU64, cTicksTransferred=%RU64, cTicksToNext=%RU64\n",
1537	pStream->u8SD, cTicksElapsed, cTicksTransferred, cTicksToNext));
1538
1539	Log3Func(("[SD%RU8] cbTransferProcessed=%RU32, cbTransferChunk=%RU32, cbTransferSize=%RU32\n",
1540	pStream->u8SD, pStream->State.cbTransferProcessed, pStream->State.cbTransferChunk, pStream->State.cbTransferSize));
1541
1542	if (cTicksElapsed <= cTicksToNext)
1543	{
1544	cTicksToNext = cTicksToNext - cTicksElapsed;
1545	}
1546	else /* Catch up. */
1547	{
1548	Log3Func(("[SD%RU8] Warning: Lagging behind (%RU64 ticks elapsed, maximum allowed is %RU64)\n",
1549	pStream->u8SD, cTicksElapsed, cTicksToNext));
1550
1551	LogRelMax2(64, ("HDA: Stream #%RU8 interrupt lagging behind (expected %uus, got %uus), trying to catch up ...\n",
1552	pStream->u8SD,
1553	(TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pThis->uTimerHz) / 1000,(tsNow - pStream->State.tsTransferLast) / 1000));
1554
1555	cTicksToNext = 0;
1556	}
1557
1558	Log3Func(("[SD%RU8] -> cTicksToNext=%RU64\n", pStream->u8SD, cTicksToNext));
1559
1560	/* Reset processed data counter. */
1561	pStream->State.cbTransferProcessed = 0;
1562	pStream->State.tsTransferNext = tsNow + cTicksToNext;
1563
1564	/* Only re-arm the timer if there were pending transfer interrupts left
1565	* -- it could happen that we land in here if a guest writes to SDnSTS
1566	* unconditionally. */
1567	if (pStream->State.cTransferPendingInterrupts)
1568	{
1569	pStream->State.cTransferPendingInterrupts--;
1570
1571	/* Re-arm the timer. */
1572	LogFunc(("Timer set SD%RU8\n", pStream->u8SD));
1573	hdaR3TimerSet(pThis, pStream, tsNow + cTicksToNext, false /* fForce */);
1574	}
1575	}
1576
1577	hdaR3StreamUnlock(pStream);
1578
1579	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1580	return VINF_SUCCESS;
1581	#else /* IN_RING3 */
1582	RT_NOREF(pThis, iReg, u32Value);
1583	return VINF_IOM_R3_MMIO_WRITE;
1584	#endif /* !IN_RING3 */
1585	}
1586
1587	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1588	{
1589	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1590
1591	if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
1592	{ /* nothing to do */ }
1593	else
1594	{
1595	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1596	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1597	if (pStream)
1598	{
1599	/** @todo Validate LVI. */
1600	pStream->u16LVI = u32Value;
1601	LogFunc(("[SD%RU8] Updating LVI to %RU16\n", uSD, pStream->u16LVI));
1602
1603	#ifdef HDA_USE_DMA_ACCESS_HANDLER
1604	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1605	{
1606	/* Try registering the DMA handlers.
1607	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
1608	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
1609	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
1610	}
1611	#endif
1612	}
1613	else
1614	AssertMsgFailed(("[SD%RU8] Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
1615
1616	int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
1617	AssertRC(rc2);
1618	}
1619
1620	DEVHDA_UNLOCK(pThis);
1621	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1622	}
1623
1624	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1625	{
1626	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1627
1628	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1629
1630	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
1631	{
1632	#ifndef IN_RING0
1633	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
1634	DEVHDA_UNLOCK(pThis);
1635	return VINF_SUCCESS;
1636	#else
1637	DEVHDA_UNLOCK(pThis);
1638	return VINF_IOM_R3_MMIO_WRITE;
1639	#endif
1640	}
1641
1642	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
1643	if (!pStream)
1644	{
1645	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
1646
1647	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1648	DEVHDA_UNLOCK(pThis);
1649	return rc;
1650	}
1651
1652	uint32_t u32FIFOW = 0;
1653
1654	switch (u32Value)
1655	{
1656	case HDA_SDFIFOW_8B:
1657	case HDA_SDFIFOW_16B:
1658	case HDA_SDFIFOW_32B:
1659	u32FIFOW = u32Value;
1660	break;
1661	default:
1662	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
1663	u32Value, uSD));
1664	u32FIFOW = HDA_SDFIFOW_32B;
1665	break;
1666	}
1667
1668	if (u32FIFOW)
1669	{
1670	pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
1671	LogFunc(("[SD%RU8] Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
1672
1673	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
1674	AssertRC(rc2);
1675	}
1676
1677	DEVHDA_UNLOCK(pThis);
1678	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1679	}
1680
1681	/**
1682	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1683	*/
1684	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1685	{
1686	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1687
1688	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1689
1690	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
1691	{
1692	LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
1693
1694	DEVHDA_UNLOCK(pThis);
1695	return VINF_SUCCESS;
1696	}
1697
1698	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1699	if (!pStream)
1700	{
1701	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
1702
1703	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1704	DEVHDA_UNLOCK(pThis);
1705	return rc;
1706	}
1707
1708	uint32_t u32FIFOS = 0;
1709
1710	switch(u32Value)
1711	{
1712	case HDA_SDOFIFO_16B:
1713	case HDA_SDOFIFO_32B:
1714	case HDA_SDOFIFO_64B:
1715	case HDA_SDOFIFO_128B:
1716	case HDA_SDOFIFO_192B:
1717	case HDA_SDOFIFO_256B:
1718	u32FIFOS = u32Value;
1719	break;
1720
1721	default:
1722	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1723	u32Value, uSD));
1724	u32FIFOS = HDA_SDOFIFO_192B;
1725	break;
1726	}
1727
1728	if (u32FIFOS)
1729	{
1730	pStream->u16FIFOS = u32FIFOS + 1;
1731	LogFunc(("[SD%RU8] Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
1732
1733	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
1734	AssertRC(rc2);
1735	}
1736
1737	DEVHDA_UNLOCK(pThis);
1738	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1739	}
1740
1741	#ifdef IN_RING3
1742
1743	/**
1744	* Adds an audio output stream to the device setup using the given configuration.
1745	*
1746	* @returns IPRT status code.
1747	* @param pThis Device state.
1748	* @param pCfg Stream configuration to use for adding a stream.
1749	*/
1750	static int hdaR3AddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1751	{
1752	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1753	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1754
1755	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1756
1757	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1758
1759	int rc = VINF_SUCCESS;
1760
1761	bool fUseFront = true; /* Always use front out by default. */
1762	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1763	bool fUseRear;
1764	bool fUseCenter;
1765	bool fUseLFE;
1766
1767	fUseRear = fUseCenter = fUseLFE = false;
1768
1769	/*
1770	* Use commonly used setups for speaker configurations.
1771	*/
1772
1773	/** @todo Make the following configurable through mixer API and/or CFGM? */
1774	switch (pCfg->Props.cChannels)
1775	{
1776	case 3: /* 2.1: Front (Stereo) + LFE. */
1777	{
1778	fUseLFE = true;
1779	break;
1780	}
1781
1782	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1783	{
1784	fUseRear = true;
1785	break;
1786	}
1787
1788	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1789	{
1790	fUseRear = true;
1791	fUseLFE = true;
1792	break;
1793	}
1794
1795	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1796	{
1797	fUseRear = true;
1798	fUseCenter = true;
1799	fUseLFE = true;
1800	break;
1801	}
1802
1803	default: /* Unknown; fall back to 2 front channels (stereo). */
1804	{
1805	rc = VERR_NOT_SUPPORTED;
1806	break;
1807	}
1808	}
1809	# else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1810	/* Only support mono or stereo channels. */
1811	if ( pCfg->Props.cChannels != 1 /* Mono */
1812	&& pCfg->Props.cChannels != 2 /* Stereo */)
1813	{
1814	rc = VERR_NOT_SUPPORTED;
1815	}
1816	# endif /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1817
1818	if (rc == VERR_NOT_SUPPORTED)
1819	{
1820	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n", pCfg->Props.cChannels));
1821
1822	/* Fall back to 2 channels (see below in fUseFront block). */
1823	rc = VINF_SUCCESS;
1824	}
1825
1826	do
1827	{
1828	if (RT_FAILURE(rc))
1829	break;
1830
1831	if (fUseFront)
1832	{
1833	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1834
1835	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1836	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1837
1838	pCfg->Props.cChannels = 2;
1839	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1840
1841	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1842	}
1843
1844	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1845	if ( RT_SUCCESS(rc)
1846	&& (fUseCenter \|\| fUseLFE))
1847	{
1848	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1849
1850	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
1851	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1852
1853	pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
1854	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1855
1856	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1857	}
1858
1859	if ( RT_SUCCESS(rc)
1860	&& fUseRear)
1861	{
1862	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1863
1864	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
1865	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1866
1867	pCfg->Props.cChannels = 2;
1868	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1869
1870	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
1871	}
1872	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1873
1874	} while (0);
1875
1876	LogFlowFuncLeaveRC(rc);
1877	return rc;
1878	}
1879
1880	/**
1881	* Adds an audio input stream to the device setup using the given configuration.
1882	*
1883	* @returns IPRT status code.
1884	* @param pThis Device state.
1885	* @param pCfg Stream configuration to use for adding a stream.
1886	*/
1887	static int hdaR3AddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1888	{
1889	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1890	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1891
1892	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
1893
1894	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1895
1896	int rc;
1897
1898	switch (pCfg->DestSource.Source)
1899	{
1900	case PDMAUDIORECSOURCE_LINE:
1901	{
1902	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
1903	break;
1904	}
1905	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1906	case PDMAUDIORECSOURCE_MIC:
1907	{
1908	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
1909	break;
1910	}
1911	# endif
1912	default:
1913	rc = VERR_NOT_SUPPORTED;
1914	break;
1915	}
1916
1917	LogFlowFuncLeaveRC(rc);
1918	return rc;
1919	}
1920
1921	/**
1922	* Adds an audio stream to the device setup using the given configuration.
1923	*
1924	* @returns IPRT status code.
1925	* @param pThis Device state.
1926	* @param pCfg Stream configuration to use for adding a stream.
1927	*/
1928	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1929	{
1930	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1931	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1932
1933	int rc;
1934
1935	LogFlowFuncEnter();
1936
1937	switch (pCfg->enmDir)
1938	{
1939	case PDMAUDIODIR_OUT:
1940	rc = hdaR3AddStreamOut(pThis, pCfg);
1941	break;
1942
1943	case PDMAUDIODIR_IN:
1944	rc = hdaR3AddStreamIn(pThis, pCfg);
1945	break;
1946
1947	default:
1948	rc = VERR_NOT_SUPPORTED;
1949	AssertFailed();
1950	break;
1951	}
1952
1953	LogFlowFunc(("Returning %Rrc\n", rc));
1954
1955	return rc;
1956	}
1957
1958	/**
1959	* Removes an audio stream from the device setup using the given configuration.
1960	*
1961	* @returns IPRT status code.
1962	* @param pThis Device state.
1963	* @param pCfg Stream configuration to use for removing a stream.
1964	*/
1965	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1966	{
1967	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1968	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1969
1970	int rc = VINF_SUCCESS;
1971
1972	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
1973	switch (pCfg->enmDir)
1974	{
1975	case PDMAUDIODIR_IN:
1976	{
1977	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1978
1979	switch (pCfg->DestSource.Source)
1980	{
1981	case PDMAUDIORECSOURCE_UNKNOWN: break;
1982	case PDMAUDIORECSOURCE_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
1983	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1984	case PDMAUDIORECSOURCE_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
1985	# endif
1986	default:
1987	rc = VERR_NOT_SUPPORTED;
1988	break;
1989	}
1990
1991	break;
1992	}
1993
1994	case PDMAUDIODIR_OUT:
1995	{
1996	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Dest));
1997
1998	switch (pCfg->DestSource.Dest)
1999	{
2000	case PDMAUDIOPLAYBACKDEST_UNKNOWN: break;
2001	case PDMAUDIOPLAYBACKDEST_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
2002	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2003	case PDMAUDIOPLAYBACKDEST_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
2004	case PDMAUDIOPLAYBACKDEST_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
2005	# endif
2006	default:
2007	rc = VERR_NOT_SUPPORTED;
2008	break;
2009	}
2010	break;
2011	}
2012
2013	default:
2014	rc = VERR_NOT_SUPPORTED;
2015	break;
2016	}
2017
2018	if ( RT_SUCCESS(rc)
2019	&& enmMixerCtl != PDMAUDIOMIXERCTL_UNKNOWN)
2020	{
2021	rc = hdaCodecRemoveStream(pThis->pCodec, enmMixerCtl);
2022	}
2023
2024	LogFlowFuncLeaveRC(rc);
2025	return rc;
2026	}
2027	#endif /* IN_RING3 */
2028
2029	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2030	{
2031	DEVHDA_LOCK(pThis);
2032
2033	# ifdef LOG_ENABLED
2034	if (!hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg)))
2035	LogFunc(("[SD%RU8] Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2036	HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2037	# endif
2038
2039
2040	/* Write the wanted stream format into the register in any case.
2041	*
2042	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
2043	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
2044	*
2045	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2046	* and therefore disabling the device completely. */
2047	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2048	AssertRC(rc);
2049
2050	DEVHDA_UNLOCK(pThis);
2051	return VINF_SUCCESS; /* Never return failure. */
2052	}
2053
2054	/* Note: Will be called for both, BDPL and BDPU, registers. */
2055	DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2056	{
2057	#ifdef IN_RING3
2058	DEVHDA_LOCK(pThis);
2059
2060	int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2061	AssertRC(rc2);
2062
2063	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2064	if (!pStream)
2065	{
2066	DEVHDA_UNLOCK(pThis);
2067	return VINF_SUCCESS;
2068	}
2069
2070	/* Update BDL base. */
2071	pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2072	HDA_STREAM_REG(pThis, BDPU, uSD));
2073
2074	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2075	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
2076	{
2077	/* Try registering the DMA handlers.
2078	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
2079	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
2080	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
2081	}
2082	# endif
2083
2084	LogFlowFunc(("[SD%RU8] BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2085
2086	DEVHDA_UNLOCK(pThis);
2087	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2088	#else /* !IN_RING3 */
2089	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2090	return VINF_IOM_R3_MMIO_WRITE;
2091	#endif /* IN_RING3 */
2092	}
2093
2094	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2095	{
2096	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2097	}
2098
2099	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2100	{
2101	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2102	}
2103
2104	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2105	{
2106	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
2107
2108	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2109	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2110	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2111	{
2112	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2113	}
2114
2115	int rc = hdaRegReadU32(pThis, iReg, pu32Value);
2116	DEVHDA_UNLOCK(pThis);
2117
2118	return rc;
2119	}
2120
2121	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2122	{
2123	RT_NOREF_PV(iReg);
2124	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2125
2126	/*
2127	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2128	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2129	*/
2130	if ( (u32Value & HDA_IRS_ICB)
2131	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2132	{
2133	#ifdef IN_RING3
2134	uint32_t uCmd = HDA_REG(pThis, IC);
2135
2136	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2137	{
2138	DEVHDA_UNLOCK(pThis);
2139
2140	/*
2141	* 3.4.3: Defines behavior of immediate Command status register.
2142	*/
2143	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2144	return VINF_SUCCESS;
2145	}
2146
2147	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2148
2149	uint64_t uResp;
2150	int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2151	HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2152	if (RT_FAILURE(rc2))
2153	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2154
2155	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2156	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2157	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2158	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2159
2160	DEVHDA_UNLOCK(pThis);
2161	return VINF_SUCCESS;
2162	#else /* !IN_RING3 */
2163	DEVHDA_UNLOCK(pThis);
2164	return VINF_IOM_R3_MMIO_WRITE;
2165	#endif /* !IN_RING3 */
2166	}
2167
2168	/*
2169	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2170	*/
2171	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2172
2173	DEVHDA_UNLOCK(pThis);
2174	return VINF_SUCCESS;
2175	}
2176
2177	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2178	{
2179	RT_NOREF(iReg);
2180	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2181
2182	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2183	{
2184	LogFunc(("CORB DMA (still) running, skipping\n"));
2185
2186	DEVHDA_UNLOCK(pThis);
2187	return VINF_SUCCESS;
2188	}
2189
2190	if (u32Value & HDA_RIRBWP_RST)
2191	{
2192	/* Do a RIRB reset. */
2193	if (pThis->cbRirbBuf)
2194	{
2195	Assert(pThis->pu64RirbBuf);
2196	RT_BZERO((void *)pThis->pu64RirbBuf, pThis->cbRirbBuf);
2197	}
2198
2199	LogRel2(("HDA: RIRB reset\n"));
2200
2201	HDA_REG(pThis, RIRBWP) = 0;
2202	}
2203
2204	/* The remaining bits are O, see 6.2.22. */
2205
2206	DEVHDA_UNLOCK(pThis);
2207	return VINF_SUCCESS;
2208	}
2209
2210	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2211	{
2212	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2213
2214	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2215	{
2216	LogFunc(("CORB DMA is (still) running, skipping\n"));
2217
2218	DEVHDA_UNLOCK(pThis);
2219	return VINF_SUCCESS;
2220	}
2221
2222	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2223	AssertRC(rc);
2224
2225	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2226
2227	DEVHDA_UNLOCK(pThis);
2228	return rc;
2229	}
2230
2231	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2232	{
2233	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2234	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2235
2236	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2237	AssertRCSuccess(rc);
2238
2239	switch (iReg)
2240	{
2241	case HDA_REG_CORBLBASE:
2242	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2243	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2244	break;
2245	case HDA_REG_CORBUBASE:
2246	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2247	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2248	break;
2249	case HDA_REG_RIRBLBASE:
2250	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2251	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2252	break;
2253	case HDA_REG_RIRBUBASE:
2254	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2255	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2256	break;
2257	case HDA_REG_DPLBASE:
2258	{
2259	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2260	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2261
2262	/* Also make sure to handle the DMA position enable bit. */
2263	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2264	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2265	break;
2266	}
2267	case HDA_REG_DPUBASE:
2268	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2269	break;
2270	default:
2271	AssertMsgFailed(("Invalid index\n"));
2272	break;
2273	}
2274
2275	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2276	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2277
2278	DEVHDA_UNLOCK(pThis);
2279	return rc;
2280	}
2281
2282	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2283	{
2284	RT_NOREF_PV(iReg);
2285	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2286
2287	uint8_t v = HDA_REG(pThis, RIRBSTS);
2288	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2289
2290	#ifndef LOG_ENABLED
2291	int rc = hdaProcessInterrupt(pThis);
2292	#else
2293	int rc = hdaProcessInterrupt(pThis, __FUNCTION__);
2294	#endif
2295
2296	DEVHDA_UNLOCK(pThis);
2297	return rc;
2298	}
2299
2300	#ifdef IN_RING3
2301
2302	/**
2303	* Retrieves a corresponding sink for a given mixer control.
2304	* Returns NULL if no sink is found.
2305	*
2306	* @return PHDAMIXERSINK
2307	* @param pThis HDA state.
2308	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2309	*/
2310	static PHDAMIXERSINK hdaR3MixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2311	{
2312	PHDAMIXERSINK pSink;
2313
2314	switch (enmMixerCtl)
2315	{
2316	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2317	/* Fall through is intentional. */
2318	case PDMAUDIOMIXERCTL_FRONT:
2319	pSink = &pThis->SinkFront;
2320	break;
2321	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2322	case PDMAUDIOMIXERCTL_CENTER_LFE:
2323	pSink = &pThis->SinkCenterLFE;
2324	break;
2325	case PDMAUDIOMIXERCTL_REAR:
2326	pSink = &pThis->SinkRear;
2327	break;
2328	# endif
2329	case PDMAUDIOMIXERCTL_LINE_IN:
2330	pSink = &pThis->SinkLineIn;
2331	break;
2332	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2333	case PDMAUDIOMIXERCTL_MIC_IN:
2334	pSink = &pThis->SinkMicIn;
2335	break;
2336	# endif
2337	default:
2338	pSink = NULL;
2339	AssertMsgFailed(("Unhandled mixer control\n"));
2340	break;
2341	}
2342
2343	return pSink;
2344	}
2345
2346	/**
2347	* Adds a specific HDA driver to the driver chain.
2348	*
2349	* @return IPRT status code.
2350	* @param pThis HDA state.
2351	* @param pDrv HDA driver to add.
2352	*/
2353	static int hdaR3MixerAddDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2354	{
2355	int rc = VINF_SUCCESS;
2356
2357	PHDASTREAM pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkLineIn);
2358	if ( pStream
2359	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2360	{
2361	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkLineIn.pMixSink, &pStream->State.Cfg, pDrv);
2362	if (RT_SUCCESS(rc))
2363	rc = rc2;
2364	}
2365
2366	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2367	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkMicIn);
2368	if ( pStream
2369	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2370	{
2371	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkMicIn.pMixSink, &pStream->State.Cfg, pDrv);
2372	if (RT_SUCCESS(rc))
2373	rc = rc2;
2374	}
2375	# endif
2376
2377	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkFront);
2378	if ( pStream
2379	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2380	{
2381	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkFront.pMixSink, &pStream->State.Cfg, pDrv);
2382	if (RT_SUCCESS(rc))
2383	rc = rc2;
2384	}
2385
2386	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2387	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkCenterLFE);
2388	if ( pStream
2389	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2390	{
2391	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkCenterLFE.pMixSink, &pStream->State.Cfg, pDrv);
2392	if (RT_SUCCESS(rc))
2393	rc = rc2;
2394	}
2395
2396	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkRear);
2397	if ( pStream
2398	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2399	{
2400	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkRear.pMixSink, &pStream->State.Cfg, pDrv);
2401	if (RT_SUCCESS(rc))
2402	rc = rc2;
2403	}
2404	# endif
2405
2406	return rc;
2407	}
2408
2409	/**
2410	* Removes a specific HDA driver from the driver chain and destroys its
2411	* associated streams.
2412	*
2413	* @param pThis HDA state.
2414	* @param pDrv HDA driver to remove.
2415	*/
2416	static void hdaR3MixerRemoveDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2417	{
2418	AssertPtrReturnVoid(pThis);
2419	AssertPtrReturnVoid(pDrv);
2420
2421	if (pDrv->LineIn.pMixStrm)
2422	{
2423	if (AudioMixerSinkGetRecordingSource(pThis->SinkLineIn.pMixSink) == pDrv->LineIn.pMixStrm)
2424	AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, NULL);
2425
2426	AudioMixerSinkRemoveStream(pThis->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
2427	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2428	pDrv->LineIn.pMixStrm = NULL;
2429	}
2430
2431	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2432	if (pDrv->MicIn.pMixStrm)
2433	{
2434	if (AudioMixerSinkGetRecordingSource(pThis->SinkMicIn.pMixSink) == pDrv->MicIn.pMixStrm)
2435	AudioMixerSinkSetRecordingSource(&pThis->SinkMicIn.pMixSink, NULL);
2436
2437	AudioMixerSinkRemoveStream(pThis->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
2438	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2439	pDrv->MicIn.pMixStrm = NULL;
2440	}
2441	# endif
2442
2443	if (pDrv->Front.pMixStrm)
2444	{
2445	AudioMixerSinkRemoveStream(pThis->SinkFront.pMixSink, pDrv->Front.pMixStrm);
2446	AudioMixerStreamDestroy(pDrv->Front.pMixStrm);
2447	pDrv->Front.pMixStrm = NULL;
2448	}
2449
2450	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2451	if (pDrv->CenterLFE.pMixStrm)
2452	{
2453	AudioMixerSinkRemoveStream(pThis->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
2454	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm);
2455	pDrv->CenterLFE.pMixStrm = NULL;
2456	}
2457
2458	if (pDrv->Rear.pMixStrm)
2459	{
2460	AudioMixerSinkRemoveStream(pThis->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
2461	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm);
2462	pDrv->Rear.pMixStrm = NULL;
2463	}
2464	# endif
2465
2466	RTListNodeRemove(&pDrv->Node);
2467	}
2468
2469	/**
2470	* Adds a driver stream to a specific mixer sink.
2471	*
2472	* @returns IPRT status code (ignored by caller).
2473	* @param pThis HDA state.
2474	* @param pMixSink Audio mixer sink to add audio streams to.
2475	* @param pCfg Audio stream configuration to use for the audio streams to add.
2476	* @param pDrv Driver stream to add.
2477	*/
2478	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2479	{
2480	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2481	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2482	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2483
2484	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2485
2486	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
2487	if (!pStreamCfg)
2488	return VERR_NO_MEMORY;
2489
2490	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
2491
2492	int rc = VINF_SUCCESS;
2493
2494	PHDADRIVERSTREAM pDrvStream = NULL;
2495
2496	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2497	{
2498	LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
2499
2500	switch (pStreamCfg->DestSource.Source)
2501	{
2502	case PDMAUDIORECSOURCE_LINE:
2503	pDrvStream = &pDrv->LineIn;
2504	break;
2505	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2506	case PDMAUDIORECSOURCE_MIC:
2507	pDrvStream = &pDrv->MicIn;
2508	break;
2509	# endif
2510	default:
2511	rc = VERR_NOT_SUPPORTED;
2512	break;
2513	}
2514	}
2515	else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
2516	{
2517	LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
2518
2519	switch (pStreamCfg->DestSource.Dest)
2520	{
2521	case PDMAUDIOPLAYBACKDEST_FRONT:
2522	pDrvStream = &pDrv->Front;
2523	break;
2524	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2525	case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
2526	pDrvStream = &pDrv->CenterLFE;
2527	break;
2528	case PDMAUDIOPLAYBACKDEST_REAR:
2529	pDrvStream = &pDrv->Rear;
2530	break;
2531	# endif
2532	default:
2533	rc = VERR_NOT_SUPPORTED;
2534	break;
2535	}
2536	}
2537	else
2538	rc = VERR_NOT_SUPPORTED;
2539
2540	if (RT_SUCCESS(rc))
2541	{
2542	AssertPtr(pDrvStream);
2543	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2544
2545	PAUDMIXSTREAM pMixStrm;
2546	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
2547	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2548	if (RT_SUCCESS(rc))
2549	{
2550	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2551	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2552	if (RT_SUCCESS(rc))
2553	{
2554	/* If this is an input stream, always set the latest (added) stream
2555	* as the recording source.
2556	* @todo Make the recording source dynamic (CFGM?). */
2557	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2558	{
2559	PDMAUDIOBACKENDCFG Cfg;
2560	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
2561	if (RT_SUCCESS(rc))
2562	{
2563	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
2564	{
2565	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
2566	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
2567	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
2568
2569	if (RT_SUCCESS(rc))
2570	LogRel(("HDA: Set recording source for '%s' to '%s'\n",
2571	pStreamCfg->szName, Cfg.szName));
2572	}
2573	else
2574	LogRel(("HDA: Backend '%s' currently is not offering any recording source for '%s'\n",
2575	Cfg.szName, pStreamCfg->szName));
2576	}
2577	else if (RT_FAILURE(rc))
2578	LogFunc(("LUN#%RU8: Unable to retrieve backend configuration for '%s', rc=%Rrc\n",
2579	pDrv->uLUN, pStreamCfg->szName, rc));
2580	}
2581	}
2582	}
2583
2584	if (RT_SUCCESS(rc))
2585	pDrvStream->pMixStrm = pMixStrm;
2586	}
2587
2588	if (pStreamCfg)
2589	{
2590	RTMemFree(pStreamCfg);
2591	pStreamCfg = NULL;
2592	}
2593
2594	LogFlowFuncLeaveRC(rc);
2595	return rc;
2596	}
2597
2598	/**
2599	* Adds all current driver streams to a specific mixer sink.
2600	*
2601	* @returns IPRT status code.
2602	* @param pThis HDA state.
2603	* @param pMixSink Audio mixer sink to add stream to.
2604	* @param pCfg Audio stream configuration to use for the audio streams to add.
2605	*/
2606	static int hdaR3MixerAddDrvStreams(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
2607	{
2608	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2609	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2610	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2611
2612	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2613
2614	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
2615	return VERR_INVALID_PARAMETER;
2616
2617	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
2618	if (RT_FAILURE(rc))
2619	return rc;
2620
2621	PHDADRIVER pDrv;
2622	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2623	{
2624	int rc2 = hdaR3MixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
2625	if (RT_FAILURE(rc2))
2626	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
2627
2628	/* Do not pass failure to rc here, as there might be drivers which aren't
2629	* configured / ready yet. */
2630	}
2631
2632	return rc;
2633	}
2634
2635	/**
2636	* @interface_method_impl{HDACODEC,pfnCbMixerAddStream}
2637	*
2638	* Adds a new audio stream to a specific mixer control.
2639	*
2640	* Depending on the mixer control the stream then gets assigned to one of the internal
2641	* mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
2642	*
2643	* @return IPRT status code.
2644	* @param pThis HDA state.
2645	* @param enmMixerCtl Mixer control to assign new stream to.
2646	* @param pCfg Stream configuration for the new stream.
2647	*/
2648	static DECLCALLBACK(int) hdaR3MixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
2649	{
2650	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2651	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2652
2653	int rc;
2654
2655	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2656	if (pSink)
2657	{
2658	rc = hdaR3MixerAddDrvStreams(pThis, pSink->pMixSink, pCfg);
2659
2660	AssertPtr(pSink->pMixSink);
2661	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2662	}
2663	else
2664	rc = VERR_NOT_FOUND;
2665
2666	LogFlowFuncLeaveRC(rc);
2667	return rc;
2668	}
2669
2670	/**
2671	* @interface_method_impl{HDACODEC,pfnCbMixerRemoveStream}
2672	*
2673	* Removes a specified mixer control from the HDA's mixer.
2674	*
2675	* @return IPRT status code.
2676	* @param pThis HDA state.
2677	* @param enmMixerCtl Mixer control to remove.
2678	*
2679	* @remarks Can be called as a callback by the HDA codec.
2680	*/
2681	static DECLCALLBACK(int) hdaR3MixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2682	{
2683	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2684
2685	int rc;
2686
2687	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2688	if (pSink)
2689	{
2690	PHDADRIVER pDrv;
2691	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2692	{
2693	PAUDMIXSTREAM pMixStream = NULL;
2694	switch (enmMixerCtl)
2695	{
2696	/*
2697	* Input.
2698	*/
2699	case PDMAUDIOMIXERCTL_LINE_IN:
2700	pMixStream = pDrv->LineIn.pMixStrm;
2701	pDrv->LineIn.pMixStrm = NULL;
2702	break;
2703	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2704	case PDMAUDIOMIXERCTL_MIC_IN:
2705	pMixStream = pDrv->MicIn.pMixStrm;
2706	pDrv->MicIn.pMixStrm = NULL;
2707	break;
2708	# endif
2709	/*
2710	* Output.
2711	*/
2712	case PDMAUDIOMIXERCTL_FRONT:
2713	pMixStream = pDrv->Front.pMixStrm;
2714	pDrv->Front.pMixStrm = NULL;
2715	break;
2716	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2717	case PDMAUDIOMIXERCTL_CENTER_LFE:
2718	pMixStream = pDrv->CenterLFE.pMixStrm;
2719	pDrv->CenterLFE.pMixStrm = NULL;
2720	break;
2721	case PDMAUDIOMIXERCTL_REAR:
2722	pMixStream = pDrv->Rear.pMixStrm;
2723	pDrv->Rear.pMixStrm = NULL;
2724	break;
2725	# endif
2726	default:
2727	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2728	break;
2729	}
2730
2731	if (pMixStream)
2732	{
2733	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2734	AudioMixerStreamDestroy(pMixStream);
2735
2736	pMixStream = NULL;
2737	}
2738	}
2739
2740	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2741	rc = VINF_SUCCESS;
2742	}
2743	else
2744	rc = VERR_NOT_FOUND;
2745
2746	LogFunc(("Mixer control=%s, rc=%Rrc\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2747	return rc;
2748	}
2749
2750	/**
2751	* @interface_method_impl{HDACODEC,pfnCbMixerControl}
2752	*
2753	* Controls an input / output converter widget, that is, which converter is connected
2754	* to which stream (and channel).
2755	*
2756	* @returns IPRT status code.
2757	* @param pThis HDA State.
2758	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2759	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2760	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2761	*
2762	* @remarks Can be called as a callback by the HDA codec.
2763	*/
2764	static DECLCALLBACK(int) hdaR3MixerControl(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2765	{
2766	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), uSD, uChannel));
2767
2768	if (uSD == 0) /* Stream number 0 is reserved. */
2769	{
2770	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2771	return VINF_SUCCESS;
2772	}
2773	/* uChannel is optional. */
2774
2775	/* SDn0 starts as 1. */
2776	Assert(uSD);
2777	uSD--;
2778
2779	# ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2780	/* Only SDI0 (Line-In) is supported. */
2781	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2782	&& uSD >= 1)
2783	{
2784	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2785	uSD = 0;
2786	}
2787	# endif
2788
2789	int rc = VINF_SUCCESS;
2790
2791	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2792	if (pSink)
2793	{
2794	AssertPtr(pSink->pMixSink);
2795
2796	/* If this an output stream, determine the correct SD#. */
2797	if ( (uSD < HDA_MAX_SDI)
2798	&& AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
2799	{
2800	uSD += HDA_MAX_SDI;
2801	}
2802
2803	/* Detach the existing stream from the sink. */
2804	if ( pSink->pStream
2805	&& ( pSink->pStream->u8SD != uSD
2806	\|\| pSink->pStream->u8Channel != uChannel)
2807	)
2808	{
2809	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2810	pSink->pMixSink->pszName, pSink->pStream->u8SD, pSink->pStream->u8Channel));
2811
2812	hdaR3StreamLock(pSink->pStream);
2813
2814	/* Only disable the stream if the stream descriptor # has changed. */
2815	if (pSink->pStream->u8SD != uSD)
2816	hdaR3StreamEnable(pSink->pStream, false);
2817
2818	pSink->pStream->pMixSink = NULL;
2819
2820	hdaR3StreamUnlock(pSink->pStream);
2821
2822	pSink->pStream = NULL;
2823	}
2824
2825	Assert(uSD < HDA_MAX_STREAMS);
2826
2827	/* Attach the new stream to the sink.
2828	* Enabling the stream will be done by the gust via a separate SDnCTL call then. */
2829	if (pSink->pStream == NULL)
2830	{
2831	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2832	pSink->pMixSink->pszName, uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2833
2834	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2835	if (pStream)
2836	{
2837	hdaR3StreamLock(pStream);
2838
2839	pSink->pStream = pStream;
2840
2841	pStream->u8Channel = uChannel;
2842	pStream->pMixSink = pSink;
2843
2844	hdaR3StreamUnlock(pStream);
2845
2846	rc = VINF_SUCCESS;
2847	}
2848	else
2849	rc = VERR_NOT_IMPLEMENTED;
2850	}
2851	}
2852	else
2853	rc = VERR_NOT_FOUND;
2854
2855	if (RT_FAILURE(rc))
2856	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2857	uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2858
2859	LogFlowFuncLeaveRC(rc);
2860	return rc;
2861	}
2862
2863	/**
2864	* @interface_method_impl{HDACODEC,pfnCbMixerSetVolume}
2865	*
2866	* Sets the volume of a specified mixer control.
2867	*
2868	* @return IPRT status code.
2869	* @param pThis HDA State.
2870	* @param enmMixerCtl Mixer control to set volume for.
2871	* @param pVol Pointer to volume data to set.
2872	*
2873	* @remarks Can be called as a callback by the HDA codec.
2874	*/
2875	static DECLCALLBACK(int) hdaR3MixerSetVolume(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2876	{
2877	int rc;
2878
2879	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2880	if ( pSink
2881	&& pSink->pMixSink)
2882	{
2883	LogRel2(("HDA: Setting volume for mixer sink '%s' to %RU8/%RU8 (%s)\n",
2884	pSink->pMixSink->pszName, pVol->uLeft, pVol->uRight, pVol->fMuted ? "Muted" : "Unmuted"));
2885
2886	/* Set the volume.
2887	* We assume that the codec already converted it to the correct range. */
2888	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2889	}
2890	else
2891	rc = VERR_NOT_FOUND;
2892
2893	LogFlowFuncLeaveRC(rc);
2894	return rc;
2895	}
2896
2897	/**
2898	* Main routine for the stream's timer.
2899	*
2900	* @param pDevIns Device instance.
2901	* @param pTimer Timer this callback was called for.
2902	* @param pvUser Pointer to associated HDASTREAM.
2903	*/
2904	static DECLCALLBACK(void) hdaR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2905	{
2906	RT_NOREF(pDevIns, pTimer);
2907
2908	PHDASTREAM pStream = (PHDASTREAM)pvUser;
2909	AssertPtr(pStream);
2910
2911	PHDASTATE pThis = pStream->pHDAState;
2912
2913	DEVHDA_LOCK_BOTH_RETURN_VOID(pStream->pHDAState, pStream->u8SD);
2914
2915	hdaR3StreamUpdate(pStream, true /* fInTimer */);
2916
2917	/* Flag indicating whether to kick the timer again for a new data processing round. */
2918	bool fSinkActive = false;
2919	if (pStream->pMixSink)
2920	fSinkActive = AudioMixerSinkIsActive(pStream->pMixSink->pMixSink);
2921
2922	if (fSinkActive)
2923	{
2924	const bool fTimerScheduled = hdaR3StreamTransferIsScheduled(pStream);
2925	Log3Func(("fSinksActive=%RTbool, fTimerScheduled=%RTbool\n", fSinkActive, fTimerScheduled));
2926	if (!fTimerScheduled)
2927	hdaR3TimerSet(pThis, pStream,
2928	TMTimerGet(pThis->pTimer[pStream->u8SD])
2929	+ TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pStream->pHDAState->uTimerHz,
2930	true /* fForce */);
2931	}
2932	else
2933	Log3Func(("fSinksActive=%RTbool\n", fSinkActive));
2934
2935	DEVHDA_UNLOCK_BOTH(pThis, pStream->u8SD);
2936	}
2937
2938	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2939	/**
2940	* HC access handler for the FIFO.
2941	*
2942	* @returns VINF_SUCCESS if the handler have carried out the operation.
2943	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2944	* @param pVM VM Handle.
2945	* @param pVCpu The cross context CPU structure for the calling EMT.
2946	* @param GCPhys The physical address the guest is writing to.
2947	* @param pvPhys The HC mapping of that address.
2948	* @param pvBuf What the guest is reading/writing.
2949	* @param cbBuf How much it's reading/writing.
2950	* @param enmAccessType The access type.
2951	* @param enmOrigin Who is making the access.
2952	* @param pvUser User argument.
2953	*/
2954	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
2955	void *pvBuf, size_t cbBuf,
2956	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2957	{
2958	RT_NOREF(pVM, pVCpu, pvPhys, pvBuf, enmOrigin);
2959
2960	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)pvUser;
2961	AssertPtr(pHandler);
2962
2963	PHDASTREAM pStream = pHandler->pStream;
2964	AssertPtr(pStream);
2965
2966	Assert(GCPhys >= pHandler->GCPhysFirst);
2967	Assert(GCPhys <= pHandler->GCPhysLast);
2968	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2969
2970	/* Not within BDLE range? Bail out. */
2971	if ( (GCPhys < pHandler->BDLEAddr)
2972	\|\| (GCPhys + cbBuf > pHandler->BDLEAddr + pHandler->BDLESize))
2973	{
2974	return VINF_PGM_HANDLER_DO_DEFAULT;
2975	}
2976
2977	switch(enmAccessType)
2978	{
2979	case PGMACCESSTYPE_WRITE:
2980	{
2981	# ifdef DEBUG
2982	PHDASTREAMDBGINFO pStreamDbg = &pStream->Dbg;
2983
2984	const uint64_t tsNowNs = RTTimeNanoTS();
2985	const uint32_t tsElapsedMs = (tsNowNs - pStreamDbg->tsWriteSlotBegin) / 1000 / 1000;
2986
2987	uint64_t cWritesHz = ASMAtomicReadU64(&pStreamDbg->cWritesHz);
2988	uint64_t cbWrittenHz = ASMAtomicReadU64(&pStreamDbg->cbWrittenHz);
2989
2990	if (tsElapsedMs >= (1000 / HDA_TIMER_HZ_DEFAULT))
2991	{
2992	LogFunc(("[SD%RU8] %RU32ms elapsed, cbWritten=%RU64, cWritten=%RU64 -- %RU32 bytes on average per time slot (%zums)\n",
2993	pStream->u8SD, tsElapsedMs, cbWrittenHz, cWritesHz,
2994	ASMDivU64ByU32RetU32(cbWrittenHz, cWritesHz ? cWritesHz : 1), 1000 / HDA_TIMER_HZ_DEFAULT));
2995
2996	pStreamDbg->tsWriteSlotBegin = tsNowNs;
2997
2998	cWritesHz = 0;
2999	cbWrittenHz = 0;
3000	}
3001
3002	cWritesHz += 1;
3003	cbWrittenHz += cbBuf;
3004
3005	ASMAtomicIncU64(&pStreamDbg->cWritesTotal);
3006	ASMAtomicAddU64(&pStreamDbg->cbWrittenTotal, cbBuf);
3007
3008	ASMAtomicWriteU64(&pStreamDbg->cWritesHz, cWritesHz);
3009	ASMAtomicWriteU64(&pStreamDbg->cbWrittenHz, cbWrittenHz);
3010
3011	LogFunc(("[SD%RU8] Writing %3zu @ 0x%x (off %zu)\n",
3012	pStream->u8SD, cbBuf, GCPhys, GCPhys - pHandler->BDLEAddr));
3013
3014	LogFunc(("[SD%RU8] cWrites=%RU64, cbWritten=%RU64 -> %RU32 bytes on average\n",
3015	pStream->u8SD, pStreamDbg->cWritesTotal, pStreamDbg->cbWrittenTotal,
3016	ASMDivU64ByU32RetU32(pStreamDbg->cbWrittenTotal, pStreamDbg->cWritesTotal)));
3017	# endif
3018
3019	if (pThis->fDebugEnabled)
3020	{
3021	RTFILE fh;
3022	RTFileOpen(&fh, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAAccessWrite.pcm",
3023	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
3024	RTFileWrite(fh, pvBuf, cbBuf, NULL);
3025	RTFileClose(fh);
3026	}
3027
3028	# ifdef HDA_USE_DMA_ACCESS_HANDLER_WRITING
3029	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
3030	AssertPtr(pCircBuf);
3031
3032	uint8_t pbBuf = (uint8_t )pvBuf;
3033	while (cbBuf)
3034	{
3035	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3036	void *pvChunk;
3037	size_t cbChunk;
3038	RTCircBufAcquireWriteBlock(pCircBuf, cbBuf, &pvChunk, &cbChunk);
3039
3040	if (cbChunk)
3041	{
3042	memcpy(pvChunk, pbBuf, cbChunk);
3043
3044	pbBuf += cbChunk;
3045	Assert(cbBuf >= cbChunk);
3046	cbBuf -= cbChunk;
3047	}
3048	else
3049	{
3050	//AssertMsg(RTCircBufFree(pCircBuf), ("No more space but still %zu bytes to write\n", cbBuf));
3051	break;
3052	}
3053
3054	LogFunc(("[SD%RU8] cbChunk=%zu\n", pStream->u8SD, cbChunk));
3055
3056	RTCircBufReleaseWriteBlock(pCircBuf, cbChunk);
3057	}
3058	# endif /* HDA_USE_DMA_ACCESS_HANDLER_WRITING */
3059	break;
3060	}
3061
3062	default:
3063	AssertMsgFailed(("Access type not implemented\n"));
3064	break;
3065	}
3066
3067	return VINF_PGM_HANDLER_DO_DEFAULT;
3068	}
3069	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
3070
3071	/**
3072	* Soft reset of the device triggered via GCTL.
3073	*
3074	* @param pThis HDA state.
3075	*
3076	*/
3077	static void hdaR3GCTLReset(PHDASTATE pThis)
3078	{
3079	LogFlowFuncEnter();
3080
3081	pThis->cStreamsActive = 0;
3082
3083	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
3084	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3085	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3086	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3087	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3088	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
3089	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
3090	HDA_REG(pThis, CORBRP) = 0x0;
3091	HDA_REG(pThis, CORBWP) = 0x0;
3092	HDA_REG(pThis, RIRBWP) = 0x0;
3093	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
3094	* RIRB response -- so initialize RINTCNT to 1 by default. */
3095	HDA_REG(pThis, RINTCNT) = 0x1;
3096
3097	/*
3098	* Stop any audio currently playing and/or recording.
3099	*/
3100	pThis->SinkFront.pStream = NULL;
3101	if (pThis->SinkFront.pMixSink)
3102	AudioMixerSinkReset(pThis->SinkFront.pMixSink);
3103	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3104	pThis->SinkMicIn.pStream = NULL;
3105	if (pThis->SinkMicIn.pMixSink)
3106	AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
3107	# endif
3108	pThis->SinkLineIn.pStream = NULL;
3109	if (pThis->SinkLineIn.pMixSink)
3110	AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
3111	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3112	pThis->SinkCenterLFE = NULL;
3113	if (pThis->SinkCenterLFE.pMixSink)
3114	AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
3115	pThis->SinkRear.pStream = NULL;
3116	if (pThis->SinkRear.pMixSink)
3117	AudioMixerSinkReset(pThis->SinkRear.pMixSink);
3118	# endif
3119
3120	/*
3121	* Reset the codec.
3122	*/
3123	if ( pThis->pCodec
3124	&& pThis->pCodec->pfnReset)
3125	{
3126	pThis->pCodec->pfnReset(pThis->pCodec);
3127	}
3128
3129	/*
3130	* Set some sensible defaults for which HDA sinks
3131	* are connected to which stream number.
3132	*
3133	* We use SD0 for input and SD4 for output by default.
3134	* These stream numbers can be changed by the guest dynamically lateron.
3135	*/
3136	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3137	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3138	# endif
3139	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3140
3141	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3142	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3143	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3144	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3145	# endif
3146
3147	/* Reset CORB. */
3148	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
3149	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3150
3151	/* Reset RIRB. */
3152	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
3153	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3154
3155	/* Clear our internal response interrupt counter. */
3156	pThis->u16RespIntCnt = 0;
3157
3158	for (uint8_t uSD = 0; uSD < HDA_MAX_STREAMS; ++uSD)
3159	{
3160	int rc2 = hdaR3StreamEnable(&pThis->aStreams[uSD], false /* fEnable */);
3161	if (RT_SUCCESS(rc2))
3162	{
3163	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
3164	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
3165	hdaR3StreamReset(pThis, &pThis->aStreams[uSD], uSD);
3166	}
3167	}
3168
3169	/* Clear stream tags <-> objects mapping table. */
3170	RT_ZERO(pThis->aTags);
3171
3172	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3173	HDA_REG(pThis, STATESTS) = 0x1;
3174
3175	LogFlowFuncLeave();
3176	LogRel(("HDA: Reset\n"));
3177	}
3178
3179	#endif /* IN_RING3 */
3180
3181	/* MMIO callbacks */
3182
3183	/**
3184	* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3185	*
3186	* @note During implementation, we discovered so-called "forgotten" or "hole"
3187	* registers whose description is not listed in the RPM, datasheet, or
3188	* spec.
3189	*/
3190	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3191	{
3192	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3193	int rc;
3194	RT_NOREF_PV(pvUser);
3195	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3196
3197	/*
3198	* Look up and log.
3199	*/
3200	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3201	int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
3202	#ifdef LOG_ENABLED
3203	unsigned const cbLog = cb;
3204	uint32_t offRegLog = offReg;
3205	#endif
3206
3207	Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
3208	Assert(cb == 4); Assert((offReg & 3) == 0);
3209
3210	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
3211
3212	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3213	LogFunc(("Access to registers except GCTL is blocked while reset\n"));
3214
3215	if (idxRegDsc == -1)
3216	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
3217
3218	if (idxRegDsc != -1)
3219	{
3220	/* Leave lock before calling read function. */
3221	DEVHDA_UNLOCK(pThis);
3222
3223	/* ASSUMES gapless DWORD at end of map. */
3224	if (g_aHdaRegMap[idxRegDsc].size == 4)
3225	{
3226	/*
3227	* Straight forward DWORD access.
3228	*/
3229	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3230	Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3231	}
3232	else
3233	{
3234	/*
3235	* Multi register read (unless there are trailing gaps).
3236	* ASSUMES that only DWORD reads have sideeffects.
3237	*/
3238	#ifdef IN_RING3
3239	uint32_t u32Value = 0;
3240	unsigned cbLeft = 4;
3241	do
3242	{
3243	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3244	uint32_t u32Tmp = 0;
3245
3246	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3247	Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3248	if (rc != VINF_SUCCESS)
3249	break;
3250	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3251
3252	cbLeft -= cbReg;
3253	offReg += cbReg;
3254	idxRegDsc++;
3255	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3256
3257	if (rc == VINF_SUCCESS)
3258	(uint32_t )pv = u32Value;
3259	else
3260	Assert(!IOM_SUCCESS(rc));
3261	#else /* !IN_RING3 */
3262	/* Take the easy way out. */
3263	rc = VINF_IOM_R3_MMIO_READ;
3264	#endif /* !IN_RING3 */
3265	}
3266	}
3267	else
3268	{
3269	DEVHDA_UNLOCK(pThis);
3270
3271	rc = VINF_IOM_MMIO_UNUSED_FF;
3272	Log3Func(("\tHole at %x is accessed for read\n", offReg));
3273	}
3274
3275	/*
3276	* Log the outcome.
3277	*/
3278	#ifdef LOG_ENABLED
3279	if (cbLog == 4)
3280	Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3281	else if (cbLog == 2)
3282	Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3283	else if (cbLog == 1)
3284	Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3285	#endif
3286	return rc;
3287	}
3288
3289
3290	DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3291	{
3292	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
3293
3294	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3295	{
3296	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
3297	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3298	g_aHdaRegMap[idxRegDsc].abbrev));
3299
3300	DEVHDA_UNLOCK(pThis);
3301	return VINF_SUCCESS;
3302	}
3303
3304	/*
3305	* Handle RD (register description) flags.
3306	*/
3307
3308	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3309	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3310	{
3311	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3312
3313	/*
3314	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3315	* while SDCTL's RUN bit is set. So just ignore those values.
3316	*/
3317
3318	/* Is the RUN bit currently set? */
3319	if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
3320	/* Are writes to the register denied if RUN bit is set? */
3321	&& !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
3322	{
3323	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
3324	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3325	g_aHdaRegMap[idxRegDsc].abbrev));
3326
3327	DEVHDA_UNLOCK(pThis);
3328	return VINF_SUCCESS;
3329	}
3330	}
3331
3332	/* Leave the lock before calling write function. */
3333	/** @todo r=bird: Why do we need to do that?? There is no
3334	* explanation why this is necessary here...
3335	*
3336	* More or less all write functions retake the lock, so why not let
3337	* those who need to drop the lock or take additional locks release
3338	* it? See, releasing a lock you already got always runs the risk
3339	* of someone else grabbing it and forcing you to wait, better to
3340	* do the two-three things a write handle needs to do than enter
3341	* and exit the lock all the time. */
3342	DEVHDA_UNLOCK(pThis);
3343
3344	#ifdef LOG_ENABLED
3345	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3346	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3347	#endif
3348	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3349	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s, rc=%d\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3350	g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog, rc));
3351	RT_NOREF(pszLog);
3352	return rc;
3353	}
3354
3355
3356	/**
3357	* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3358	*/
3359	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
3360	{
3361	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3362	int rc;
3363	RT_NOREF_PV(pvUser);
3364	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3365
3366	/*
3367	* The behavior of accesses that aren't aligned on natural boundraries is
3368	* undefined. Just reject them outright.
3369	*/
3370	/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3371	Assert(cb == 1 \|\| cb == 2 \|\| cb == 4 \|\| cb == 8);
3372	if (GCPhysAddr & (cb - 1))
3373	return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3374
3375	/*
3376	* Look up and log the access.
3377	*/
3378	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3379	int idxRegDsc = hdaRegLookup(offReg);
3380	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3381	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3382	#endif
3383	uint64_t u64Value;
3384	if (cb == 4) u64Value = (uint32_t const )pv;
3385	else if (cb == 2) u64Value = (uint16_t const )pv;
3386	else if (cb == 1) u64Value = (uint8_t const )pv;
3387	else if (cb == 8) u64Value = (uint64_t const )pv;
3388	else
3389	{
3390	u64Value = 0; /* shut up gcc. */
3391	AssertReleaseMsgFailed(("%u\n", cb));
3392	}
3393
3394	#ifdef LOG_ENABLED
3395	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3396	if (idxRegDsc == -1)
3397	Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, (uint32_t const )pv, cb));
3398	else if (cb == 4)
3399	Log3Func(("@%#05x u32=%#010x %s\n", offReg, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3400	else if (cb == 2)
3401	Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, (uint16_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3402	else if (cb == 1)
3403	Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, (uint8_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3404
3405	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3406	Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3407	#endif
3408
3409	/*
3410	* Try for a direct hit first.
3411	*/
3412	if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3413	{
3414	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3415	Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3416	}
3417	/*
3418	* Partial or multiple register access, loop thru the requested memory.
3419	*/
3420	else
3421	{
3422	#ifdef IN_RING3
3423	/*
3424	* If it's an access beyond the start of the register, shift the input
3425	* value and fill in missing bits. Natural alignment rules means we
3426	* will only see 1 or 2 byte accesses of this kind, so no risk of
3427	* shifting out input values.
3428	*/
3429	if (idxRegDsc == -1 && (idxRegDsc = hdaR3RegLookupWithin(offReg)) != -1)
3430	{
3431	uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3432	offReg -= cbBefore;
3433	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3434	u64Value <<= cbBefore * 8;
3435	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3436	Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3437	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3438	}
3439
3440	/* Loop thru the write area, it may cover multiple registers. */
3441	rc = VINF_SUCCESS;
3442	for (;;)
3443	{
3444	uint32_t cbReg;
3445	if (idxRegDsc != -1)
3446	{
3447	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3448	cbReg = g_aHdaRegMap[idxRegDsc].size;
3449	if (cb < cbReg)
3450	{
3451	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3452	Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3453	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3454	}
3455	# ifdef LOG_ENABLED
3456	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3457	# endif
3458	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3459	Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3460	}
3461	else
3462	{
3463	LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3464	cbReg = 1;
3465	}
3466	if (rc != VINF_SUCCESS)
3467	break;
3468	if (cbReg >= cb)
3469	break;
3470
3471	/* Advance. */
3472	offReg += cbReg;
3473	cb -= cbReg;
3474	u64Value >>= cbReg * 8;
3475	if (idxRegDsc == -1)
3476	idxRegDsc = hdaRegLookup(offReg);
3477	else
3478	{
3479	idxRegDsc++;
3480	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3481	\|\| g_aHdaRegMap[idxRegDsc].offset != offReg)
3482	{
3483	idxRegDsc = -1;
3484	}
3485	}
3486	}
3487
3488	#else /* !IN_RING3 */
3489	/* Take the simple way out. */
3490	rc = VINF_IOM_R3_MMIO_WRITE;
3491	#endif /* !IN_RING3 */
3492	}
3493
3494	return rc;
3495	}
3496
3497
3498	/* PCI callback. */
3499
3500	#ifdef IN_RING3
3501	/**
3502	* @callback_method_impl{FNPCIIOREGIONMAP}
3503	*/
3504	static DECLCALLBACK(int) hdaR3PciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3505	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3506	{
3507	RT_NOREF(iRegion, enmType);
3508	PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3509
3510	/*
3511	* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3512	*
3513	* Let IOM talk DWORDs when reading, saves a lot of complications. On
3514	* writing though, we have to do it all ourselves because of sideeffects.
3515	*/
3516	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3517	int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3518	IOMMMIO_FLAGS_READ_DWORD
3519	\| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3520	hdaMMIOWrite, hdaMMIORead, "HDA");
3521
3522	if (RT_FAILURE(rc))
3523	return rc;
3524
3525	if (pThis->fRZEnabled)
3526	{
3527	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3528	"hdaMMIOWrite", "hdaMMIORead");
3529	if (RT_FAILURE(rc))
3530	return rc;
3531
3532	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3533	"hdaMMIOWrite", "hdaMMIORead");
3534	if (RT_FAILURE(rc))
3535	return rc;
3536	}
3537
3538	pThis->MMIOBaseAddr = GCPhysAddress;
3539	return VINF_SUCCESS;
3540	}
3541
3542
3543	/* Saved state workers and callbacks. */
3544
3545	static int hdaR3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStream)
3546	{
3547	RT_NOREF(pDevIns);
3548	#ifdef VBOX_STRICT
3549	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3550	#endif
3551
3552	Log2Func(("[SD%RU8]\n", pStream->u8SD));
3553
3554	/* Save stream ID. */
3555	int rc = SSMR3PutU8(pSSM, pStream->u8SD);
3556	AssertRCReturn(rc, rc);
3557	Assert(pStream->u8SD < HDA_MAX_STREAMS);
3558
3559	rc = SSMR3PutStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3560	AssertRCReturn(rc, rc);
3561
3562	#ifdef VBOX_STRICT /* Sanity checks. */
3563	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
3564	HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
3565	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
3566	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
3567
3568	Assert(u64BaseDMA == pStream->u64BDLBase);
3569	Assert(u16LVI == pStream->u16LVI);
3570	Assert(u32CBL == pStream->u32CBL);
3571	#endif
3572
3573	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
3574	0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3575	AssertRCReturn(rc, rc);
3576
3577	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3578	0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3579	AssertRCReturn(rc, rc);
3580
3581	rc = SSMR3PutStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
3582	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
3583	AssertRCReturn(rc, rc);
3584
3585	#ifdef VBOX_STRICT /* Sanity checks. */
3586	PHDABDLE pBDLE = &pStream->State.BDLE;
3587	if (u64BaseDMA)
3588	{
3589	Assert(pStream->State.uCurBDLE <= u16LVI + 1);
3590
3591	HDABDLE curBDLE;
3592	rc = hdaR3BDLEFetch(pThis, &curBDLE, u64BaseDMA, pStream->State.uCurBDLE);
3593	AssertRC(rc);
3594
3595	Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
3596	Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
3597	Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
3598	}
3599	else
3600	{
3601	Assert(pBDLE->Desc.u64BufAdr == 0);
3602	Assert(pBDLE->Desc.u32BufSize == 0);
3603	}
3604	#endif
3605
3606	uint32_t cbCircBufSize = 0;
3607	uint32_t cbCircBufUsed = 0;
3608
3609	if (pStream->State.pCircBuf)
3610	{
3611	cbCircBufSize = (uint32_t)RTCircBufSize(pStream->State.pCircBuf);
3612	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
3613	}
3614
3615	rc = SSMR3PutU32(pSSM, cbCircBufSize);
3616	AssertRCReturn(rc, rc);
3617
3618	rc = SSMR3PutU32(pSSM, cbCircBufUsed);
3619	AssertRCReturn(rc, rc);
3620
3621	if (cbCircBufUsed)
3622	{
3623	/*
3624	* We now need to get the circular buffer's data without actually modifying
3625	* the internal read / used offsets -- otherwise we would end up with broken audio
3626	* data after saving the state.
3627	*
3628	* So get the current read offset and serialize the buffer data manually based on that.
3629	*/
3630	size_t cbCircBufOffRead = RTCircBufOffsetRead(pStream->State.pCircBuf);
3631
3632	void *pvBuf;
3633	size_t cbBuf;
3634	RTCircBufAcquireReadBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3635
3636	if (cbBuf)
3637	{
3638	size_t cbToRead = cbCircBufUsed;
3639	size_t cbEnd = 0;
3640
3641	if (cbCircBufUsed > cbCircBufOffRead)
3642	cbEnd = cbCircBufUsed - cbCircBufOffRead;
3643
3644	if (cbEnd) /* Save end of buffer first. */
3645	{
3646	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf + cbCircBufSize - cbEnd / End of buffer */, cbEnd);
3647	AssertRCReturn(rc, rc);
3648
3649	Assert(cbToRead >= cbEnd);
3650	cbToRead -= cbEnd;
3651	}
3652
3653	if (cbToRead) /* Save remaining stuff at start of buffer (if any). */
3654	{
3655	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf - cbCircBufUsed / Start of buffer */, cbToRead);
3656	AssertRCReturn(rc, rc);
3657	}
3658	}
3659
3660	RTCircBufReleaseReadBlock(pStream->State.pCircBuf, 0 /* Don't advance read pointer -- see comment above */);
3661	}
3662
3663	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3664	pStream->u8SD,
3665	HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, CBL, pStream->u8SD), HDA_STREAM_REG(pThis, LVI, pStream->u8SD)));
3666
3667	#ifdef LOG_ENABLED
3668	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3669	#endif
3670
3671	return rc;
3672	}
3673
3674	/**
3675	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3676	*/
3677	static DECLCALLBACK(int) hdaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3678	{
3679	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3680
3681	/* Save Codec nodes states. */
3682	hdaCodecSaveState(pThis->pCodec, pSSM);
3683
3684	/* Save MMIO registers. */
3685	SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3686	SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3687
3688	/* Save controller-specifc internals. */
3689	SSMR3PutU64(pSSM, pThis->u64WalClk);
3690	SSMR3PutU8(pSSM, pThis->u8IRQL);
3691
3692	/* Save number of streams. */
3693	SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
3694
3695	/* Save stream states. */
3696	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3697	{
3698	int rc = hdaR3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3699	AssertRCReturn(rc, rc);
3700	}
3701
3702	return VINF_SUCCESS;
3703	}
3704
3705	/**
3706	* Does required post processing when loading a saved state.
3707	*
3708	* @param pThis Pointer to HDA state.
3709	*/
3710	static int hdaR3LoadExecPost(PHDASTATE pThis)
3711	{
3712	int rc = VINF_SUCCESS;
3713
3714	/*
3715	* Enable all previously active streams.
3716	*/
3717	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3718	{
3719	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
3720	if (pStream)
3721	{
3722	int rc2;
3723
3724	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3725	if (fActive)
3726	{
3727	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
3728	/* Make sure to also create the async I/O thread before actually enabling the stream. */
3729	rc2 = hdaR3StreamAsyncIOCreate(pStream);
3730	AssertRC(rc2);
3731
3732	/* ... and enabling it. */
3733	hdaR3StreamAsyncIOEnable(pStream, true /* fEnable */);
3734	#endif
3735	/* Resume the stream's period. */
3736	hdaR3StreamPeriodResume(&pStream->State.Period);
3737
3738	/* (Re-)enable the stream. */
3739	rc2 = hdaR3StreamEnable(pStream, true /* fEnable */);
3740	AssertRC(rc2);
3741
3742	/* Add the stream to the device setup. */
3743	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
3744	AssertRC(rc2);
3745
3746	#ifdef HDA_USE_DMA_ACCESS_HANDLER
3747	/* (Re-)install the DMA handler. */
3748	hdaR3StreamRegisterDMAHandlers(pThis, pStream);
3749	#endif
3750	if (hdaR3StreamTransferIsScheduled(pStream))
3751	hdaR3TimerSet(pThis, pStream, hdaR3StreamTransferGetNext(pStream), true /* fForce */);
3752
3753	/* Also keep track of the currently active streams. */
3754	pThis->cStreamsActive++;
3755	}
3756	}
3757	}
3758
3759	LogFlowFuncLeaveRC(rc);
3760	return rc;
3761	}
3762
3763
3764	/**
3765	* Handles loading of all saved state versions older than the current one.
3766	*
3767	* @param pThis Pointer to HDA state.
3768	* @param pSSM Pointer to SSM handle.
3769	* @param uVersion Saved state version to load.
3770	* @param uPass Loading stage to handle.
3771	*/
3772	static int hdaR3LoadExecLegacy(PHDASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3773	{
3774	RT_NOREF(uPass);
3775
3776	int rc = VINF_SUCCESS;
3777
3778	/*
3779	* Load MMIO registers.
3780	*/
3781	uint32_t cRegs;
3782	switch (uVersion)
3783	{
3784	case HDA_SSM_VERSION_1:
3785	/* Starting with r71199, we would save 112 instead of 113
3786	registers due to some code cleanups. This only affected trunk
3787	builds in the 4.1 development period. */
3788	cRegs = 113;
3789	if (SSMR3HandleRevision(pSSM) >= 71199)
3790	{
3791	uint32_t uVer = SSMR3HandleVersion(pSSM);
3792	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3793	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3794	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3795	cRegs = 112;
3796	}
3797	break;
3798
3799	case HDA_SSM_VERSION_2:
3800	case HDA_SSM_VERSION_3:
3801	cRegs = 112;
3802	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3803	break;
3804
3805	/* Since version 4 we store the register count to stay flexible. */
3806	case HDA_SSM_VERSION_4:
3807	case HDA_SSM_VERSION_5:
3808	case HDA_SSM_VERSION_6:
3809	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3810	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3811	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3812	break;
3813
3814	default:
3815	LogRel(("HDA: Warning: Unsupported / too new saved state version (%RU32)\n", uVersion));
3816	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3817	}
3818
3819	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3820	{
3821	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3822	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3823	}
3824	else
3825	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3826
3827	/* Make sure to update the base addresses first before initializing any streams down below. */
3828	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3829	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3830	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3831
3832	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3833	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3834
3835	/*
3836	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3837	* every BDLE state, whereas it only needs to be stored
3838	* once for every stream. Most of the BDLE state we can
3839	* get out of the registers anyway, so just ignore those values.
3840	*
3841	* Also, only the current BDLE was saved, regardless whether
3842	* there were more than one (and there are at least two entries,
3843	* according to the spec).
3844	*/
3845	#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3846	{ \
3847	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3848	AssertRCReturn(rc, rc); \
3849	rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
3850	AssertRCReturn(rc, rc); \
3851	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3852	AssertRCReturn(rc, rc); \
3853	rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3854	AssertRCReturn(rc, rc); \
3855	rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
3856	AssertRCReturn(rc, rc); \
3857	rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3858	AssertRCReturn(rc, rc); \
3859	bool fIOC; \
3860	rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
3861	AssertRCReturn(rc, rc); \
3862	x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
3863	rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3864	AssertRCReturn(rc, rc); \
3865	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
3866	AssertRCReturn(rc, rc); \
3867	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3868	AssertRCReturn(rc, rc); \
3869	}
3870
3871	/*
3872	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3873	*/
3874	switch (uVersion)
3875	{
3876	case HDA_SSM_VERSION_1:
3877	case HDA_SSM_VERSION_2:
3878	case HDA_SSM_VERSION_3:
3879	case HDA_SSM_VERSION_4:
3880	{
3881	/* Only load the internal states.
3882	* The rest will be initialized from the saved registers later. */
3883
3884	/* Note 1: Only the current BDLE for a stream was saved! */
3885	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3886
3887	/* Output */
3888	PHDASTREAM pStream = &pThis->aStreams[4];
3889	rc = hdaR3StreamInit(pStream, 4 /* Stream descriptor, hardcoded */);
3890	if (RT_FAILURE(rc))
3891	break;
3892	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3893	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3894
3895	/* Microphone-In */
3896	pStream = &pThis->aStreams[2];
3897	rc = hdaR3StreamInit(pStream, 2 /* Stream descriptor, hardcoded */);
3898	if (RT_FAILURE(rc))
3899	break;
3900	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3901	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3902
3903	/* Line-In */
3904	pStream = &pThis->aStreams[0];
3905	rc = hdaR3StreamInit(pStream, 0 /* Stream descriptor, hardcoded */);
3906	if (RT_FAILURE(rc))
3907	break;
3908	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3909	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3910	break;
3911	}
3912
3913	#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3914
3915	default: /* Since v5 we support flexible stream and BDLE counts. */
3916	{
3917	uint32_t cStreams;
3918	rc = SSMR3GetU32(pSSM, &cStreams);
3919	if (RT_FAILURE(rc))
3920	break;
3921
3922	if (cStreams > HDA_MAX_STREAMS)
3923	cStreams = HDA_MAX_STREAMS; /* Sanity. */
3924
3925	/* Load stream states. */
3926	for (uint32_t i = 0; i < cStreams; i++)
3927	{
3928	uint8_t uStreamID;
3929	rc = SSMR3GetU8(pSSM, &uStreamID);
3930	if (RT_FAILURE(rc))
3931	break;
3932
3933	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
3934	HDASTREAM StreamDummy;
3935
3936	if (!pStream)
3937	{
3938	pStream = &StreamDummy;
3939	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3940	}
3941
3942	rc = hdaR3StreamInit(pStream, uStreamID);
3943	if (RT_FAILURE(rc))
3944	{
3945	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3946	break;
3947	}
3948
3949	/*
3950	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3951	*/
3952
3953	if (uVersion == HDA_SSM_VERSION_5)
3954	{
3955	/* Get the current BDLE entry and skip the rest. */
3956	uint16_t cBDLE;
3957
3958	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3959	AssertRC(rc);
3960	rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3961	AssertRC(rc);
3962	rc = SSMR3GetU16(pSSM, &pStream->State.uCurBDLE); /* uCurBDLE */
3963	AssertRC(rc);
3964	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3965	AssertRC(rc);
3966
3967	uint32_t u32BDLEIndex;
3968	for (uint16_t a = 0; a < cBDLE; a++)
3969	{
3970	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3971	AssertRC(rc);
3972	rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3973	AssertRC(rc);
3974
3975	/* Does the current BDLE index match the current BDLE to process? */
3976	if (u32BDLEIndex == pStream->State.uCurBDLE)
3977	{
3978	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3979	AssertRC(rc);
3980	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
3981	AssertRC(rc);
3982	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.u32BufOff); /* u32BufOff */
3983	AssertRC(rc);
3984	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3985	AssertRC(rc);
3986	}
3987	else /* Skip not current BDLEs. */
3988	{
3989	rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
3990	+ sizeof(uint8_t) * 256 /* au8FIFO */
3991	+ sizeof(uint32_t) /* u32BufOff */
3992	+ sizeof(uint32_t)); /* End marker */
3993	AssertRC(rc);
3994	}
3995	}
3996	}
3997	else
3998	{
3999	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4000	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
4001	if (RT_FAILURE(rc))
4002	break;
4003
4004	/* Get HDABDLEDESC. */
4005	uint32_t uMarker;
4006	rc = SSMR3GetU32(pSSM, &uMarker); /* Begin marker. */
4007	AssertRC(rc);
4008	Assert(uMarker == UINT32_C(0x19200102) /* SSMR3STRUCT_BEGIN */);
4009	rc = SSMR3GetU64(pSSM, &pStream->State.BDLE.Desc.u64BufAdr);
4010	AssertRC(rc);
4011	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.Desc.u32BufSize);
4012	AssertRC(rc);
4013	bool fFlags = false;
4014	rc = SSMR3GetBool(pSSM, &fFlags); /* Saved states < v7 only stored the IOC as boolean flag. */
4015	AssertRC(rc);
4016	pStream->State.BDLE.Desc.fFlags = fFlags ? HDA_BDLE_FLAG_IOC : 0;
4017	rc = SSMR3GetU32(pSSM, &uMarker); /* End marker. */
4018	AssertRC(rc);
4019	Assert(uMarker == UINT32_C(0x19920406) /* SSMR3STRUCT_END */);
4020
4021	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4022	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
4023	if (RT_FAILURE(rc))
4024	break;
4025
4026	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4027	uStreamID,
4028	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4029	#ifdef LOG_ENABLED
4030	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4031	#endif
4032	}
4033
4034	} /* for cStreams */
4035	break;
4036	} /* default */
4037	}
4038
4039	return rc;
4040	}
4041
4042	/**
4043	* @callback_method_impl{FNSSMDEVLOADEXEC}
4044	*/
4045	static DECLCALLBACK(int) hdaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4046	{
4047	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4048
4049	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4050
4051	LogRel2(("hdaR3LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4052
4053	/*
4054	* Load Codec nodes states.
4055	*/
4056	int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4057	if (RT_FAILURE(rc))
4058	{
4059	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4060	return rc;
4061	}
4062
4063	if (uVersion < HDA_SSM_VERSION) /* Handle older saved states? */
4064	{
4065	rc = hdaR3LoadExecLegacy(pThis, pSSM, uVersion, uPass);
4066	if (RT_SUCCESS(rc))
4067	rc = hdaR3LoadExecPost(pThis);
4068
4069	return rc;
4070	}
4071
4072	/*
4073	* Load MMIO registers.
4074	*/
4075	uint32_t cRegs;
4076	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4077	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4078	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4079
4080	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4081	{
4082	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4083	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4084	}
4085	else
4086	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4087
4088	/* Make sure to update the base addresses first before initializing any streams down below. */
4089	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
4090	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
4091	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
4092
4093	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
4094	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
4095
4096	/*
4097	* Load controller-specifc internals.
4098	* Don't annoy other team mates (forgot this for state v7).
4099	*/
4100	if ( SSMR3HandleRevision(pSSM) >= 116273
4101	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4102	{
4103	rc = SSMR3GetU64(pSSM, &pThis->u64WalClk);
4104	AssertRC(rc);
4105
4106	rc = SSMR3GetU8(pSSM, &pThis->u8IRQL);
4107	AssertRC(rc);
4108	}
4109
4110	/*
4111	* Load streams.
4112	*/
4113	uint32_t cStreams;
4114	rc = SSMR3GetU32(pSSM, &cStreams);
4115	AssertRC(rc);
4116
4117	if (cStreams > HDA_MAX_STREAMS)
4118	cStreams = HDA_MAX_STREAMS; /* Sanity. */
4119
4120	Log2Func(("cStreams=%RU32\n", cStreams));
4121
4122	/* Load stream states. */
4123	for (uint32_t i = 0; i < cStreams; i++)
4124	{
4125	uint8_t uStreamID;
4126	rc = SSMR3GetU8(pSSM, &uStreamID);
4127	AssertRC(rc);
4128
4129	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
4130	HDASTREAM StreamDummy;
4131
4132	if (!pStream)
4133	{
4134	pStream = &StreamDummy;
4135	LogRel2(("HDA: Warning: Loading of stream #%RU8 not supported, skipping to load ...\n", uStreamID));
4136	}
4137
4138	rc = hdaR3StreamInit(pStream, uStreamID);
4139	if (RT_FAILURE(rc))
4140	{
4141	LogRel(("HDA: Stream #%RU8: Loading initialization failed, rc=%Rrc\n", uStreamID, rc));
4142	/* Continue. */
4143	}
4144
4145	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4146	0 /* fFlags */, g_aSSMStreamStateFields7,
4147	NULL);
4148	AssertRC(rc);
4149
4150	/*
4151	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4152	*/
4153	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
4154	0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
4155	AssertRC(rc);
4156
4157	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4158	0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
4159	AssertRC(rc);
4160
4161	Log2Func(("[SD%RU8] %R[bdle]\n", pStream->u8SD, &pStream->State.BDLE));
4162
4163	/*
4164	* Load period state.
4165	* Don't annoy other team mates (forgot this for state v7).
4166	*/
4167	hdaR3StreamPeriodInit(&pStream->State.Period,
4168	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
4169
4170	if ( SSMR3HandleRevision(pSSM) >= 116273
4171	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4172	{
4173	rc = SSMR3GetStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
4174	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
4175	AssertRC(rc);
4176	}
4177
4178	/*
4179	* Load internal (FIFO) buffer.
4180	*/
4181	uint32_t cbCircBufSize = 0;
4182	rc = SSMR3GetU32(pSSM, &cbCircBufSize); /* cbCircBuf */
4183	AssertRC(rc);
4184
4185	uint32_t cbCircBufUsed = 0;
4186	rc = SSMR3GetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4187	AssertRC(rc);
4188
4189	if (cbCircBufSize) /* If 0, skip the buffer. */
4190	{
4191	/* Paranoia. */
4192	AssertReleaseMsg(cbCircBufSize <= _1M,
4193	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4194	cbCircBufSize, uStreamID));
4195	AssertReleaseMsg(cbCircBufUsed <= cbCircBufSize,
4196	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4197	cbCircBufUsed, cbCircBufSize, uStreamID));
4198	AssertPtr(pStream->State.pCircBuf);
4199
4200	/* Do we need to cre-create the circular buffer do fit the data size? */
4201	if (cbCircBufSize != (uint32_t)RTCircBufSize(pStream->State.pCircBuf))
4202	{
4203	RTCircBufDestroy(pStream->State.pCircBuf);
4204	pStream->State.pCircBuf = NULL;
4205
4206	rc = RTCircBufCreate(&pStream->State.pCircBuf, cbCircBufSize);
4207	AssertRC(rc);
4208	}
4209
4210	if ( RT_SUCCESS(rc)
4211	&& cbCircBufUsed)
4212	{
4213	void *pvBuf;
4214	size_t cbBuf;
4215
4216	RTCircBufAcquireWriteBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4217
4218	if (cbBuf)
4219	{
4220	rc = SSMR3GetMem(pSSM, pvBuf, cbBuf);
4221	AssertRC(rc);
4222	}
4223
4224	RTCircBufReleaseWriteBlock(pStream->State.pCircBuf, cbBuf);
4225
4226	Assert(cbBuf == cbCircBufUsed);
4227	}
4228	}
4229
4230	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4231	uStreamID,
4232	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4233	#ifdef LOG_ENABLED
4234	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4235	#endif
4236	/** @todo (Re-)initialize active periods? */
4237
4238	} /* for cStreams */
4239
4240	rc = hdaR3LoadExecPost(pThis);
4241	AssertRC(rc);
4242
4243	LogFlowFuncLeaveRC(rc);
4244	return rc;
4245	}
4246
4247	/* IPRT format type handlers. */
4248
4249	/**
4250	* @callback_method_impl{FNRTSTRFORMATTYPE}
4251	*/
4252	static DECLCALLBACK(size_t) hdaR3StrFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4253	const char pszType, void const pvValue,
4254	int cchWidth, int cchPrecision, unsigned fFlags,
4255	void *pvUser)
4256	{
4257	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4258	PHDABDLE pBDLE = (PHDABDLE)pvValue;
4259	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4260	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
4261	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
4262	pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
4263	}
4264
4265	/**
4266	* @callback_method_impl{FNRTSTRFORMATTYPE}
4267	*/
4268	static DECLCALLBACK(size_t) hdaR3StrFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4269	const char pszType, void const pvValue,
4270	int cchWidth, int cchPrecision, unsigned fFlags,
4271	void *pvUser)
4272	{
4273	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4274	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4275	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4276	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4277	uSDCTL,
4278	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4279	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4280	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4281	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4282	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4283	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4284	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4285	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4286	}
4287
4288	/**
4289	* @callback_method_impl{FNRTSTRFORMATTYPE}
4290	*/
4291	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4292	const char pszType, void const pvValue,
4293	int cchWidth, int cchPrecision, unsigned fFlags,
4294	void *pvUser)
4295	{
4296	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4297	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4298	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4299	}
4300
4301	/**
4302	* @callback_method_impl{FNRTSTRFORMATTYPE}
4303	*/
4304	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4305	const char pszType, void const pvValue,
4306	int cchWidth, int cchPrecision, unsigned fFlags,
4307	void *pvUser)
4308	{
4309	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4310	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4311	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4312	}
4313
4314	/**
4315	* @callback_method_impl{FNRTSTRFORMATTYPE}
4316	*/
4317	static DECLCALLBACK(size_t) hdaR3StrFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4318	const char pszType, void const pvValue,
4319	int cchWidth, int cchPrecision, unsigned fFlags,
4320	void *pvUser)
4321	{
4322	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4323	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4324	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4325	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4326	uSdSts,
4327	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4328	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4329	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4330	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4331	}
4332
4333	/* Debug info dumpers */
4334
4335	static int hdaR3DbgLookupRegByName(const char *pszArgs)
4336	{
4337	int iReg = 0;
4338	for (; iReg < HDA_NUM_REGS; ++iReg)
4339	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4340	return iReg;
4341	return -1;
4342	}
4343
4344
4345	static void hdaR3DbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4346	{
4347	Assert( pThis
4348	&& iHdaIndex >= 0
4349	&& iHdaIndex < HDA_NUM_REGS);
4350	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4351	}
4352
4353	/**
4354	* @callback_method_impl{FNDBGFHANDLERDEV}
4355	*/
4356	static DECLCALLBACK(void) hdaR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4357	{
4358	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4359	int iHdaRegisterIndex = hdaR3DbgLookupRegByName(pszArgs);
4360	if (iHdaRegisterIndex != -1)
4361	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4362	else
4363	{
4364	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
4365	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4366	}
4367	}
4368
4369	static void hdaR3DbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4370	{
4371	Assert( pThis
4372	&& iIdx >= 0
4373	&& iIdx < HDA_MAX_STREAMS);
4374
4375	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4376
4377	pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
4378	pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
4379	pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
4380	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
4381	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
4382	pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStream->State.BDLE);
4383	}
4384
4385	static void hdaR3DbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4386	{
4387	Assert( pThis
4388	&& iIdx >= 0
4389	&& iIdx < HDA_MAX_STREAMS);
4390
4391	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4392	const PHDABDLE pBDLE = &pStream->State.BDLE;
4393
4394	pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
4395
4396	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
4397	HDA_STREAM_REG(pThis, BDPU, iIdx));
4398	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
4399	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
4400
4401	if (!u64BaseDMA)
4402	return;
4403
4404	pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
4405
4406	pHlp->pfnPrintf(pHlp, "\tMemory:\n");
4407
4408	uint32_t cbBDLE = 0;
4409	for (uint16_t i = 0; i < u16LVI + 1; i++)
4410	{
4411	HDABDLEDESC bd;
4412	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4413
4414	pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
4415	pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
4416
4417	cbBDLE += bd.u32BufSize;
4418	}
4419
4420	pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
4421
4422	if (cbBDLE != u32CBL)
4423	pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
4424
4425	pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
4426	if (!u64BaseDMA) /* No DMA base given? Bail out. */
4427	{
4428	pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
4429	return;
4430	}
4431
4432	for (int i = 0; i < u16LVI + 1; i++)
4433	{
4434	uint32_t uDMACnt;
4435	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
4436	&uDMACnt, sizeof(uDMACnt));
4437
4438	pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
4439	}
4440	}
4441
4442	static int hdaR3DbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
4443	{
4444	RT_NOREF(pThis, pszArgs);
4445	/** @todo Add args parsing. */
4446	return -1;
4447	}
4448
4449	/**
4450	* @callback_method_impl{FNDBGFHANDLERDEV}
4451	*/
4452	static DECLCALLBACK(void) hdaR3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4453	{
4454	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4455	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4456	if (iHdaStreamdex != -1)
4457	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4458	else
4459	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4460	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4461	}
4462
4463	/**
4464	* @callback_method_impl{FNDBGFHANDLERDEV}
4465	*/
4466	static DECLCALLBACK(void) hdaR3DbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4467	{
4468	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4469	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4470	if (iHdaStreamdex != -1)
4471	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4472	else
4473	for (iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4474	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4475	}
4476
4477	/**
4478	* @callback_method_impl{FNDBGFHANDLERDEV}
4479	*/
4480	static DECLCALLBACK(void) hdaR3DbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4481	{
4482	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4483
4484	if (pThis->pCodec->pfnDbgListNodes)
4485	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4486	else
4487	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4488	}
4489
4490	/**
4491	* @callback_method_impl{FNDBGFHANDLERDEV}
4492	*/
4493	static DECLCALLBACK(void) hdaR3DbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4494	{
4495	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4496
4497	if (pThis->pCodec->pfnDbgSelector)
4498	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4499	else
4500	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4501	}
4502
4503	/**
4504	* @callback_method_impl{FNDBGFHANDLERDEV}
4505	*/
4506	static DECLCALLBACK(void) hdaR3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4507	{
4508	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4509
4510	if (pThis->pMixer)
4511	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4512	else
4513	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4514	}
4515
4516
4517	/* PDMIBASE */
4518
4519	/**
4520	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4521	*/
4522	static DECLCALLBACK(void ) hdaR3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4523	{
4524	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4525	Assert(&pThis->IBase == pInterface);
4526
4527	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4528	return NULL;
4529	}
4530
4531
4532	/* PDMDEVREG */
4533
4534	/**
4535	* Attach command, internal version.
4536	*
4537	* This is called to let the device attach to a driver for a specified LUN
4538	* during runtime. This is not called during VM construction, the device
4539	* constructor has to attach to all the available drivers.
4540	*
4541	* @returns VBox status code.
4542	* @param pThis HDA state.
4543	* @param uLUN The logical unit which is being detached.
4544	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4545	* @param ppDrv Attached driver instance on success. Optional.
4546	*/
4547	static int hdaR3AttachInternal(PHDASTATE pThis, unsigned uLUN, uint32_t fFlags, PHDADRIVER *ppDrv)
4548	{
4549	RT_NOREF(fFlags);
4550
4551	/*
4552	* Attach driver.
4553	*/
4554	char *pszDesc;
4555	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4556	AssertLogRelFailedReturn(VERR_NO_MEMORY);
4557
4558	PPDMIBASE pDrvBase;
4559	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
4560	&pThis->IBase, &pDrvBase, pszDesc);
4561	if (RT_SUCCESS(rc))
4562	{
4563	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4564	if (pDrv)
4565	{
4566	pDrv->pDrvBase = pDrvBase;
4567	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4568	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4569	pDrv->pHDAState = pThis;
4570	pDrv->uLUN = uLUN;
4571
4572	/*
4573	* For now we always set the driver at LUN 0 as our primary
4574	* host backend. This might change in the future.
4575	*/
4576	if (pDrv->uLUN == 0)
4577	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
4578
4579	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
4580
4581	/* Attach to driver list if not attached yet. */
4582	if (!pDrv->fAttached)
4583	{
4584	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4585	pDrv->fAttached = true;
4586	}
4587
4588	if (ppDrv)
4589	*ppDrv = pDrv;
4590	}
4591	else
4592	rc = VERR_NO_MEMORY;
4593	}
4594	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4595	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4596
4597	if (RT_FAILURE(rc))
4598	{
4599	/* Only free this string on failure;
4600	* must remain valid for the live of the driver instance. */
4601	RTStrFree(pszDesc);
4602	}
4603
4604	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4605	return rc;
4606	}
4607
4608	/**
4609	* Detach command, internal version.
4610	*
4611	* This is called to let the device detach from a driver for a specified LUN
4612	* during runtime.
4613	*
4614	* @returns VBox status code.
4615	* @param pThis HDA state.
4616	* @param pDrv Driver to detach from device.
4617	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4618	*/
4619	static int hdaR3DetachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint32_t fFlags)
4620	{
4621	RT_NOREF(fFlags);
4622
4623	/* First, remove the driver from our list and destory it's associated streams.
4624	* This also will un-set the driver as a recording source (if associated). */
4625	hdaR3MixerRemoveDrv(pThis, pDrv);
4626
4627	/* Next, search backwards for a capable (attached) driver which now will be the
4628	* new recording source. */
4629	PHDADRIVER pDrvCur;
4630	RTListForEachReverse(&pThis->lstDrv, pDrvCur, HDADRIVER, Node)
4631	{
4632	if (!pDrvCur->pConnector)
4633	continue;
4634
4635	PDMAUDIOBACKENDCFG Cfg;
4636	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4637	if (RT_FAILURE(rc2))
4638	continue;
4639
4640	PHDADRIVERSTREAM pDrvStrm;
4641	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4642	pDrvStrm = &pDrvCur->MicIn;
4643	if ( pDrvStrm
4644	&& pDrvStrm->pMixStrm)
4645	{
4646	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkMicIn.pMixSink, pDrvStrm->pMixStrm);
4647	if (RT_SUCCESS(rc2))
4648	LogRel2(("HDA: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4649	}
4650	# endif
4651	pDrvStrm = &pDrvCur->LineIn;
4652	if ( pDrvStrm
4653	&& pDrvStrm->pMixStrm)
4654	{
4655	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, pDrvStrm->pMixStrm);
4656	if (RT_SUCCESS(rc2))
4657	LogRel2(("HDA: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4658	}
4659	}
4660
4661	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4662	return VINF_SUCCESS;
4663	}
4664
4665	/**
4666	* @interface_method_impl{PDMDEVREG,pfnAttach}
4667	*/
4668	static DECLCALLBACK(int) hdaR3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4669	{
4670	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4671
4672	DEVHDA_LOCK_RETURN(pThis, VERR_IGNORED);
4673
4674	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4675
4676	PHDADRIVER pDrv;
4677	int rc2 = hdaR3AttachInternal(pThis, uLUN, fFlags, &pDrv);
4678	if (RT_SUCCESS(rc2))
4679	rc2 = hdaR3MixerAddDrv(pThis, pDrv);
4680
4681	if (RT_FAILURE(rc2))
4682	LogFunc(("Failed with %Rrc\n", rc2));
4683
4684	DEVHDA_UNLOCK(pThis);
4685
4686	return VINF_SUCCESS;
4687	}
4688
4689	/**
4690	* @interface_method_impl{PDMDEVREG,pfnDetach}
4691	*/
4692	static DECLCALLBACK(void) hdaR3Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4693	{
4694	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4695
4696	DEVHDA_LOCK(pThis);
4697
4698	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4699
4700	PHDADRIVER pDrv, pDrvNext;
4701	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, HDADRIVER, Node)
4702	{
4703	if (pDrv->uLUN == uLUN)
4704	{
4705	int rc2 = hdaR3DetachInternal(pThis, pDrv, fFlags);
4706	if (RT_SUCCESS(rc2))
4707	{
4708	RTMemFree(pDrv);
4709	pDrv = NULL;
4710	}
4711
4712	break;
4713	}
4714	}
4715
4716	DEVHDA_UNLOCK(pThis);
4717	}
4718
4719	/**
4720	* Powers off the device.
4721	*
4722	* @param pDevIns Device instance to power off.
4723	*/
4724	static DECLCALLBACK(void) hdaR3PowerOff(PPDMDEVINS pDevIns)
4725	{
4726	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4727
4728	DEVHDA_LOCK_RETURN_VOID(pThis);
4729
4730	LogRel2(("HDA: Powering off ...\n"));
4731
4732	/* Ditto goes for the codec, which in turn uses the mixer. */
4733	hdaCodecPowerOff(pThis->pCodec);
4734
4735	/*
4736	* Note: Destroy the mixer while powering off and not in hdaR3Destruct,
4737	* giving the mixer the chance to release any references held to
4738	* PDM audio streams it maintains.
4739	*/
4740	if (pThis->pMixer)
4741	{
4742	AudioMixerDestroy(pThis->pMixer);
4743	pThis->pMixer = NULL;
4744	}
4745
4746	DEVHDA_UNLOCK(pThis);
4747	}
4748
4749
4750	/**
4751	* Re-attaches (replaces) a driver with a new driver.
4752	*
4753	* This is only used by to attach the Null driver when it failed to attach the
4754	* one that was configured.
4755	*
4756	* @returns VBox status code.
4757	* @param pThis Device instance to re-attach driver to.
4758	* @param pDrv Driver instance used for attaching to.
4759	* If NULL is specified, a new driver will be created and appended
4760	* to the driver list.
4761	* @param uLUN The logical unit which is being re-detached.
4762	* @param pszDriver New driver name to attach.
4763	*/
4764	static int hdaR3ReattachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4765	{
4766	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4767	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4768
4769	int rc;
4770
4771	if (pDrv)
4772	{
4773	rc = hdaR3DetachInternal(pThis, pDrv, 0 /* fFlags */);
4774	if (RT_SUCCESS(rc))
4775	rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4776
4777	if (RT_FAILURE(rc))
4778	return rc;
4779
4780	pDrv = NULL;
4781	}
4782
4783	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4784	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4785	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4786
4787	/* Remove LUN branch. */
4788	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4789
4790	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4791
4792	do
4793	{
4794	PCFGMNODE pLunL0;
4795	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4796	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4797	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4798
4799	PCFGMNODE pLunL1, pLunL2;
4800	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4801	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4802	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4803
4804	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4805
4806	} while (0);
4807
4808	if (RT_SUCCESS(rc))
4809	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
4810
4811	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4812
4813	#undef RC_CHECK
4814
4815	return rc;
4816	}
4817
4818
4819	/**
4820	* @interface_method_impl{PDMDEVREG,pfnReset}
4821	*/
4822	static DECLCALLBACK(void) hdaR3Reset(PPDMDEVINS pDevIns)
4823	{
4824	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4825
4826	LogFlowFuncEnter();
4827
4828	DEVHDA_LOCK_RETURN_VOID(pThis);
4829
4830	/*
4831	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4832	* hdaR3Reset shouldn't affects these registers.
4833	*/
4834	HDA_REG(pThis, WAKEEN) = 0x0;
4835
4836	hdaR3GCTLReset(pThis);
4837
4838	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4839	* but we can take a shortcut.
4840	*/
4841	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4842
4843	DEVHDA_UNLOCK(pThis);
4844	}
4845
4846
4847	/**
4848	* @interface_method_impl{PDMDEVREG,pfnRelocate}
4849	*/
4850	static DECLCALLBACK(void) hdaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4851	{
4852	NOREF(offDelta);
4853	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4854	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4855	}
4856
4857
4858	/**
4859	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4860	*/
4861	static DECLCALLBACK(int) hdaR3Destruct(PPDMDEVINS pDevIns)
4862	{
4863	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4864	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4865	DEVHDA_LOCK(pThis); /** @todo r=bird: this will fail on early constructor failure. */
4866
4867	PHDADRIVER pDrv;
4868	while (!RTListIsEmpty(&pThis->lstDrv))
4869	{
4870	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4871
4872	RTListNodeRemove(&pDrv->Node);
4873	RTMemFree(pDrv);
4874	}
4875
4876	if (pThis->pCodec)
4877	{
4878	hdaCodecDestruct(pThis->pCodec);
4879
4880	RTMemFree(pThis->pCodec);
4881	pThis->pCodec = NULL;
4882	}
4883
4884	RTMemFree(pThis->pu32CorbBuf);
4885	pThis->pu32CorbBuf = NULL;
4886
4887	RTMemFree(pThis->pu64RirbBuf);
4888	pThis->pu64RirbBuf = NULL;
4889
4890	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4891	hdaR3StreamDestroy(&pThis->aStreams[i]);
4892
4893	DEVHDA_UNLOCK(pThis);
4894	return VINF_SUCCESS;
4895	}
4896
4897
4898	/**
4899	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4900	*/
4901	static DECLCALLBACK(int) hdaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4902	{
4903	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4904	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4905	Assert(iInstance == 0); RT_NOREF(iInstance);
4906
4907	/*
4908	* Initialize the state sufficently to make the destructor work.
4909	*/
4910	pThis->uAlignmentCheckMagic = HDASTATE_ALIGNMENT_CHECK_MAGIC;
4911	RTListInit(&pThis->lstDrv);
4912	/** @todo r=bird: There are probably other things which should be
4913	* initialized here before we start failing. */
4914
4915	/*
4916	* Validations.
4917	*/
4918	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
4919	"TimerHz\0"
4920	"PosAdjustEnabled\0"
4921	"PosAdjustFrames\0"
4922	"DebugEnabled\0"
4923	"DebugPathOut\0"))
4924	{
4925	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4926	N_ ("Invalid configuration for the Intel HDA device"));
4927	}
4928
4929	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
4930	if (RT_FAILURE(rc))
4931	return PDMDEV_SET_ERROR(pDevIns, rc,
4932	N_("HDA configuration error: failed to read RCEnabled as boolean"));
4933
4934
4935	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, HDA_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4936	if (RT_FAILURE(rc))
4937	return PDMDEV_SET_ERROR(pDevIns, rc,
4938	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4939
4940	if (pThis->uTimerHz != HDA_TIMER_HZ_DEFAULT)
4941	LogRel(("HDA: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4942
4943	rc = CFGMR3QueryBoolDef(pCfg, "PosAdjustEnabled", &pThis->fPosAdjustEnabled, true);
4944	if (RT_FAILURE(rc))
4945	return PDMDEV_SET_ERROR(pDevIns, rc,
4946	N_("HDA configuration error: failed to read position adjustment enabled as boolean"));
4947
4948	if (!pThis->fPosAdjustEnabled)
4949	LogRel(("HDA: Position adjustment is disabled\n"));
4950
4951	rc = CFGMR3QueryU16Def(pCfg, "PosAdjustFrames", &pThis->cPosAdjustFrames, HDA_POS_ADJUST_DEFAULT);
4952	if (RT_FAILURE(rc))
4953	return PDMDEV_SET_ERROR(pDevIns, rc,
4954	N_("HDA configuration error: failed to read position adjustment frames as unsigned integer"));
4955
4956	if (pThis->cPosAdjustFrames)
4957	LogRel(("HDA: Using custom position adjustment (%RU16 audio frames)\n", pThis->cPosAdjustFrames));
4958
4959	rc = CFGMR3QueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
4960	if (RT_FAILURE(rc))
4961	return PDMDEV_SET_ERROR(pDevIns, rc,
4962	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4963
4964	rc = CFGMR3QueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
4965	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4966	if (RT_FAILURE(rc))
4967	return PDMDEV_SET_ERROR(pDevIns, rc,
4968	N_("HDA configuration error: failed to read debugging output path flag as string"));
4969
4970	if (!strlen(pThis->Dbg.szOutPath))
4971	RTStrPrintf(pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath), VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4972
4973	if (pThis->Dbg.fEnabled)
4974	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4975
4976	/*
4977	* Use an own critical section for the device instead of the default
4978	* one provided by PDM. This allows fine-grained locking in combination
4979	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4980	*/
4981	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4982	AssertRCReturn(rc, rc);
4983
4984	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4985	AssertRCReturn(rc, rc);
4986
4987	/*
4988	* Initialize data (most of it anyway).
4989	*/
4990	pThis->pDevInsR3 = pDevIns;
4991	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4992	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4993	/* IBase */
4994	pThis->IBase.pfnQueryInterface = hdaR3QueryInterface;
4995
4996	/* PCI Device */
4997	PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4998	PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4999
5000	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5001	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5002	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5003	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5004	PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5005	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5006	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5007	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5008	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
5009	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5010	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5011
5012	#if defined(HDA_AS_PCI_EXPRESS)
5013	PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5014	#elif defined(VBOX_WITH_MSI_DEVICES)
5015	PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5016	#else
5017	PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5018	#endif
5019
5020	/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5021	/// of these values needs to be properly documented!
5022	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5023	PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5024
5025	/* Power Management */
5026	PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5027	PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5028	PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
5029
5030	#ifdef HDA_AS_PCI_EXPRESS
5031	/* PCI Express */
5032	PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5033	PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5034	/* Device flags */
5035	PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5036	/* version */ 0x1 \|
5037	/* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) \|
5038	/* MSI */ (100) << 9 );
5039	/* Device capabilities */
5040	PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5041	/* Device control */
5042	PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5043	/* Device status */
5044	PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5045	/* Link caps */
5046	PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5047	/* Link control */
5048	PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5049	/* Link status */
5050	PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5051	/* Slot capabilities */
5052	PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5053	/* Slot control */
5054	PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5055	/* Slot status */
5056	PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5057	/* Root control */
5058	PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5059	/* Root capabilities */
5060	PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5061	/* Root status */
5062	PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5063	/* Device capabilities 2 */
5064	PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5065	/* Device control 2 */
5066	PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5067	/* Link control 2 */
5068	PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5069	/* Slot control 2 */
5070	PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5071	#endif
5072
5073	/*
5074	* Register the PCI device.
5075	*/
5076	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5077	if (RT_FAILURE(rc))
5078	return rc;
5079
5080	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaR3PciIoRegionMap);
5081	if (RT_FAILURE(rc))
5082	return rc;
5083
5084	#ifdef VBOX_WITH_MSI_DEVICES
5085	PDMMSIREG MsiReg;
5086	RT_ZERO(MsiReg);
5087	MsiReg.cMsiVectors = 1;
5088	MsiReg.iMsiCapOffset = 0x60;
5089	MsiReg.iMsiNextOffset = 0x50;
5090	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5091	if (RT_FAILURE(rc))
5092	{
5093	/* That's OK, we can work without MSI */
5094	PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5095	}
5096	#endif
5097
5098	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaR3SaveExec, hdaR3LoadExec);
5099	if (RT_FAILURE(rc))
5100	return rc;
5101
5102	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
5103	LogRel(("HDA: Asynchronous I/O enabled\n"));
5104	#endif
5105
5106	uint8_t uLUN;
5107	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5108	{
5109	LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5110	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
5111	if (RT_FAILURE(rc))
5112	{
5113	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5114	rc = VINF_SUCCESS;
5115	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5116	{
5117	hdaR3ReattachInternal(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5118	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5119	N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
5120	"with the consequence that no sound is audible"));
5121	/* Attaching to the NULL audio backend will never fail. */
5122	rc = VINF_SUCCESS;
5123	}
5124	break;
5125	}
5126	}
5127
5128	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5129
5130	if (RT_SUCCESS(rc))
5131	{
5132	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5133	if (RT_SUCCESS(rc))
5134	{
5135	/*
5136	* Add mixer output sinks.
5137	*/
5138	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5139	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5140	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5141	AssertRC(rc);
5142	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5143	AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5144	AssertRC(rc);
5145	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5146	AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5147	AssertRC(rc);
5148	#else
5149	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5150	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5151	AssertRC(rc);
5152	#endif
5153	/*
5154	* Add mixer input sinks.
5155	*/
5156	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5157	AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5158	AssertRC(rc);
5159	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5160	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5161	AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5162	AssertRC(rc);
5163	#endif
5164	/* There is no master volume control. Set the master to max. */
5165	PDMAUDIOVOLUME vol = { false, 255, 255 };
5166	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5167	AssertRC(rc);
5168	}
5169	}
5170
5171	if (RT_SUCCESS(rc))
5172	{
5173	/* Allocate CORB buffer. */
5174	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
5175	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5176	if (pThis->pu32CorbBuf)
5177	{
5178	/* Allocate RIRB buffer. */
5179	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
5180	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5181	if (pThis->pu64RirbBuf)
5182	{
5183	/* Allocate codec. */
5184	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5185	if (!pThis->pCodec)
5186	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5187	}
5188	else
5189	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating RIRB"));
5190	}
5191	else
5192	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating CORB"));
5193
5194	if (RT_SUCCESS(rc))
5195	{
5196	/* Set codec callbacks to this controller. */
5197	pThis->pCodec->pfnCbMixerAddStream = hdaR3MixerAddStream;
5198	pThis->pCodec->pfnCbMixerRemoveStream = hdaR3MixerRemoveStream;
5199	pThis->pCodec->pfnCbMixerControl = hdaR3MixerControl;
5200	pThis->pCodec->pfnCbMixerSetVolume = hdaR3MixerSetVolume;
5201
5202	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5203
5204	/* Construct the codec. */
5205	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5206	if (RT_FAILURE(rc))
5207	AssertRCReturn(rc, rc);
5208
5209	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5210	verb F20 should provide device/codec recognition. */
5211	Assert(pThis->pCodec->u16VendorId);
5212	Assert(pThis->pCodec->u16DeviceId);
5213	PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5214	PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5215	}
5216	}
5217
5218	if (RT_SUCCESS(rc))
5219	{
5220	/*
5221	* Create all hardware streams.
5222	*/
5223	static const char * const s_apszNames[] =
5224	{
5225	"HDA SD0", "HDA SD1", "HDA SD2", "HDA SD3",
5226	"HDA SD4", "HDA SD5", "HDA SD6", "HDA SD7",
5227	};
5228	AssertCompile(RT_ELEMENTS(s_apszNames) == HDA_MAX_STREAMS);
5229	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
5230	{
5231	/* Create the emulation timer (per stream).
5232	*
5233	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver
5234	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
5235	* instead of the LPIB registers.
5236	*/
5237	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaR3Timer, &pThis->aStreams[i],
5238	TMTIMER_FLAGS_NO_CRIT_SECT, s_apszNames[i], &pThis->pTimer[i]);
5239	AssertRCReturn(rc, rc);
5240
5241	/* Use our own critcal section for the device timer.
5242	* That way we can control more fine-grained when to lock what. */
5243	rc = TMR3TimerSetCritSect(pThis->pTimer[i], &pThis->CritSect);
5244	AssertRCReturn(rc, rc);
5245
5246	rc = hdaR3StreamCreate(&pThis->aStreams[i], pThis, i /* u8SD */);
5247	AssertRC(rc);
5248	}
5249
5250	#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
5251	/*
5252	* Initialize the driver chain.
5253	*/
5254	PHDADRIVER pDrv;
5255	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5256	{
5257	/*
5258	* Only primary drivers are critical for the VM to run. Everything else
5259	* might not worth showing an own error message box in the GUI.
5260	*/
5261	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
5262	continue;
5263
5264	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5265	AssertPtr(pCon);
5266
5267	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5268	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5269	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5270	# endif
5271	bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5272	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5273	/** @todo Anything to do here? */
5274	# endif
5275
5276	if ( !fValidLineIn
5277	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5278	&& !fValidMicIn
5279	# endif
5280	&& !fValidOut)
5281	{
5282	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5283
5284	hdaR3Reset(pDevIns);
5285	hdaR3ReattachInternal(pThis, pDrv, pDrv->uLUN, "NullAudio");
5286
5287	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5288	N_("No audio devices could be opened. Selecting the NULL audio backend "
5289	"with the consequence that no sound is audible"));
5290	}
5291	else
5292	{
5293	bool fWarn = false;
5294
5295	PDMAUDIOBACKENDCFG backendCfg;
5296	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5297	if (RT_SUCCESS(rc2))
5298	{
5299	if (backendCfg.cMaxStreamsIn)
5300	{
5301	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5302	/* If the audio backend supports two or more input streams at once,
5303	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5304	if (backendCfg.cMaxStreamsIn >= 2)
5305	fWarn = !fValidLineIn \|\| !fValidMicIn;
5306	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5307	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5308	* One of the two simply is not in use then. */
5309	else if (backendCfg.cMaxStreamsIn == 1)
5310	fWarn = !fValidLineIn && !fValidMicIn;
5311	/* Don't warn if our backend is not able of supporting any input streams at all. */
5312	# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5313	/* We only have line-in as input source. */
5314	fWarn = !fValidLineIn;
5315	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5316	}
5317
5318	if ( !fWarn
5319	&& backendCfg.cMaxStreamsOut)
5320	{
5321	fWarn = !fValidOut;
5322	}
5323	}
5324	else
5325	{
5326	LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
5327	fWarn = true;
5328	}
5329
5330	if (fWarn)
5331	{
5332	char szMissingStreams[255];
5333	size_t len = 0;
5334	if (!fValidLineIn)
5335	{
5336	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5337	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5338	}
5339	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5340	if (!fValidMicIn)
5341	{
5342	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5343	len += RTStrPrintf(szMissingStreams + len,
5344	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5345	}
5346	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5347	if (!fValidOut)
5348	{
5349	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5350	len += RTStrPrintf(szMissingStreams + len,
5351	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5352	}
5353
5354	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5355	N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
5356	"output or depending on audio input may hang. Make sure your host audio device "
5357	"is working properly. Check the logfile for error messages of the audio "
5358	"subsystem"), szMissingStreams);
5359	}
5360	}
5361	}
5362	#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
5363	}
5364
5365	if (RT_SUCCESS(rc))
5366	{
5367	hdaR3Reset(pDevIns);
5368
5369	/*
5370	* Debug and string formatter types.
5371	*/
5372	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaR3DbgInfo);
5373	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaR3DbgInfoBDLE);
5374	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaR3DbgInfoStream);
5375	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaR3DbgInfoCodecNodes);
5376	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaR3DbgInfoCodecSelector);
5377	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaR3DbgInfoMixer);
5378
5379	rc = RTStrFormatTypeRegister("bdle", hdaR3StrFmtBDLE, NULL);
5380	AssertRC(rc);
5381	rc = RTStrFormatTypeRegister("sdctl", hdaR3StrFmtSDCTL, NULL);
5382	AssertRC(rc);
5383	rc = RTStrFormatTypeRegister("sdsts", hdaR3StrFmtSDSTS, NULL);
5384	AssertRC(rc);
5385	rc = RTStrFormatTypeRegister("sdfifos", hdaR3StrFmtSDFIFOS, NULL);
5386	AssertRC(rc);
5387	rc = RTStrFormatTypeRegister("sdfifow", hdaR3StrFmtSDFIFOW, NULL);
5388	AssertRC(rc);
5389
5390	/*
5391	* Some debug assertions.
5392	*/
5393	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5394	{
5395	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5396	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5397
5398	/* binary search order. */
5399	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
5400	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5401	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5402
5403	/* alignment. */
5404	AssertReleaseMsg( pReg->size == 1
5405	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
5406	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
5407	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
5408	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5409
5410	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5411	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
5412	if (pReg->offset & 3)
5413	{
5414	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5415	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5416	if (pPrevReg)
5417	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
5418	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5419	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
5420	}
5421	#if 0
5422	if ((pReg->offset + pReg->size) & 3)
5423	{
5424	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5425	if (pNextReg)
5426	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5427	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5428	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5429	}
5430	#endif
5431	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5432	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
5433	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5434	}
5435	}
5436
5437	# ifdef VBOX_WITH_STATISTICS
5438	if (RT_SUCCESS(rc))
5439	{
5440	/*
5441	* Register statistics.
5442	*/
5443	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaR3Timer.");
5444	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5445	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5446	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5447	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5448	}
5449	# endif
5450
5451	LogFlowFuncLeaveRC(rc);
5452	return rc;
5453	}
5454
5455	/**
5456	* The device registration structure.
5457	*/
5458	const PDMDEVREG g_DeviceHDA =
5459	{
5460	/* u32Version */
5461	PDM_DEVREG_VERSION,
5462	/* szName */
5463	"hda",
5464	/* szRCMod */
5465	"VBoxDDRC.rc",
5466	/* szR0Mod */
5467	"VBoxDDR0.r0",
5468	/* pszDescription */
5469	"Intel HD Audio Controller",
5470	/* fFlags */
5471	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
5472	/* fClass */
5473	PDM_DEVREG_CLASS_AUDIO,
5474	/* cMaxInstances */
5475	1,
5476	/* cbInstance */
5477	sizeof(HDASTATE),
5478	/* pfnConstruct */
5479	hdaR3Construct,
5480	/* pfnDestruct */
5481	hdaR3Destruct,
5482	/* pfnRelocate */
5483	hdaR3Relocate,
5484	/* pfnMemSetup */
5485	NULL,
5486	/* pfnPowerOn */
5487	NULL,
5488	/* pfnReset */
5489	hdaR3Reset,
5490	/* pfnSuspend */
5491	NULL,
5492	/* pfnResume */
5493	NULL,
5494	/* pfnAttach */
5495	hdaR3Attach,
5496	/* pfnDetach */
5497	hdaR3Detach,
5498	/* pfnQueryInterface. */
5499	NULL,
5500	/* pfnInitComplete */
5501	NULL,
5502	/* pfnPowerOff */
5503	hdaR3PowerOff,
5504	/* pfnSoftReset */
5505	NULL,
5506	/* u32VersionEnd */
5507	PDM_DEVREG_VERSION
5508	};
5509
5510	#endif /* IN_RING3 */
5511	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5512

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 75606

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